93f81bd490
repo: https://github.com/T-head-Semi/opensbi commit: 89182b257c8798e15e4c685c1af0c2862d528d2a Change-Id: I7b39d66729e0108661a6f4c9e28acbdb303684ea
57 lines
1.4 KiB
ArmAsm
57 lines
1.4 KiB
ArmAsm
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2020 Western Digital Corporation or its affiliates.
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*
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* Authors:
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* Anup Patel <anup.patel@wdc.com>
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*/
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#include <sbi/riscv_asm.h>
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#include <sbi/sbi_trap.h>
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/*
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* We assume that faulting instruction is is 4-byte long and blindly
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* increment SEPC by 4.
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*
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* The trap info will be saved as follows:
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* A3 <- pointer struct sbi_trap_info
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* A4 <- temporary
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*/
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.align 3
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.global __sbi_expected_trap
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__sbi_expected_trap:
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/* Without H-extension so, MTVAL2 and MTINST CSRs not available */
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csrr a4, CSR_MEPC
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REG_S a4, SBI_TRAP_INFO_OFFSET(epc)(a3)
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csrr a4, CSR_MCAUSE
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REG_S a4, SBI_TRAP_INFO_OFFSET(cause)(a3)
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csrr a4, CSR_MTVAL
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REG_S a4, SBI_TRAP_INFO_OFFSET(tval)(a3)
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REG_S zero, SBI_TRAP_INFO_OFFSET(tval2)(a3)
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REG_S zero, SBI_TRAP_INFO_OFFSET(tinst)(a3)
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csrr a4, CSR_MEPC
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addi a4, a4, 4
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csrw CSR_MEPC, a4
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mret
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.align 3
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.global __sbi_expected_trap_hext
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__sbi_expected_trap_hext:
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/* With H-extension so, MTVAL2 and MTINST CSRs available */
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csrr a4, CSR_MEPC
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REG_S a4, SBI_TRAP_INFO_OFFSET(epc)(a3)
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csrr a4, CSR_MCAUSE
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REG_S a4, SBI_TRAP_INFO_OFFSET(cause)(a3)
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csrr a4, CSR_MTVAL
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REG_S a4, SBI_TRAP_INFO_OFFSET(tval)(a3)
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csrr a4, CSR_MTVAL2
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REG_S a4, SBI_TRAP_INFO_OFFSET(tval2)(a3)
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csrr a4, CSR_MTINST
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REG_S a4, SBI_TRAP_INFO_OFFSET(tinst)(a3)
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csrr a4, CSR_MEPC
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addi a4, a4, 4
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csrw CSR_MEPC, a4
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mret
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