5c7dd7acc3
repo: https://github.com/T-head-Semi/linux commit: b1313fe517ca3703119dcc99ef3bbf75ab42bcfb Change-Id: I6cbb35294024ea3a66140e311f4bb705fd7fd626
26 lines
692 B
Plaintext
26 lines
692 B
Plaintext
Alpine MSIX controller
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See arm,gic-v3.txt for SPI and MSI definitions.
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Required properties:
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- compatible: should be "al,alpine-msix"
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- reg: physical base address and size of the registers
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- interrupt-controller: identifies the node as an interrupt controller
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- msi-controller: identifies the node as an PCI Message Signaled Interrupt
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controller
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- al,msi-base-spi: SPI base of the MSI frame
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- al,msi-num-spis: number of SPIs assigned to the MSI frame, relative to SPI0
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Example:
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msix: msix {
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compatible = "al,alpine-msix";
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reg = <0x0 0xfbe00000 0x0 0x100000>;
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interrupt-parent = <&gic>;
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interrupt-controller;
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msi-controller;
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al,msi-base-spi = <160>;
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al,msi-num-spis = <160>;
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};
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