134 lines
3.0 KiB
C
134 lines
3.0 KiB
C
/*
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* Copyright CviTek Inc.
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*
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* Created Time: May, 2021
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*/
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#ifndef __CVI_CIF_H__
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#define __CVI_CIF_H__
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#ifdef __cplusplus
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extern "C" {
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#endif /* __cplusplus */
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#ifdef RUN_IN_SRAM
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#include "drv/cif_drv.h"
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#elif (RUN_TYPE == CVIRTOS)
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#include "cif_drv.h"
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#endif
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#include "gpio.h"
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#include "cif_uapi.h"
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#include "sensor.h"
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#define CIF_MAX_CSI_NUM 2
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#define CIF_MAX_MAC_NUM 3
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#define CSIMAC0_INTR_NUM (22)
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#define CSIMAC1_INTR_NUM (23)
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/* Register Base Address */
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#define DPHY_TOP_BASE (0x0A0D0000)
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#define DPHY_4L_BASE (0x0A0D0300)
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#define DPHY_2L_BASE (0x0A0D0600)
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#define SENSOR_MAC0_BASE (0x0A0C2000)
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#define SENSOR_MAC1_BASE (0x0A0C4000)
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#define SENSOR_MAC_VI_BASE (0x0A0C6000)
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#define SENSOR_CSI0_BASE (0x0A0C2400)
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#define SENSOR_CSI1_BASE (0x0A0C4400)
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// CAM_PLL
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#define CLK_CAM0_SRC_DIV (0x030028C0)
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#define CLK_CAM1_SRC_DIV (0x030028C4)
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/* Register fileds */
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#define DPHY_TOP_REG_04 (DPHY_TOP_BASE + 0x04)
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#define DPHY_TOP_REG_30 (DPHY_TOP_BASE + 0x30)
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#define DPHY_4L_REG_04 (DPHY_4L_BASE + 0x04)
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#define DPHY_4L_REG_08 (DPHY_4L_BASE + 0x08)
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#define DPHY_4L_REG_0C (DPHY_4L_BASE + 0x0C)
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#define DPHY_4L_REG_10 (DPHY_4L_BASE + 0x10)
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#define DPHY_2L_REG_04 (DPHY_2L_BASE + 0x04)
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#define DPHY_2L_REG_08 (DPHY_2L_BASE + 0x08)
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#define DPHY_2L_REG_0C (DPHY_2L_BASE + 0x0C)
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#define DPHY_2L_REG_10 (DPHY_2L_BASE + 0x10)
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// CAM_PLL
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#define REG_CAM_DIV_DIS (4)
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#define REG_CAM_SRC (8)
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#define REG_CAM_SRC_MASK (3 << REG_CAM_SRC)
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#define REG_CAM_DIV (16)
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#define REG_CAM_DIV_MASK (0x3F << REG_CAM_DIV)
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/* Macro */
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#define CSI_HDR_ID_VALUE (0xfff00)
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#define CSI_HDR_VC_VALUE (0xdff00)
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#define CSI_LINEAR_VALUE (0xcff00)
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#define CIF_PHY_LANE_NUM 6
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#define MAX_PAD_NUM 19
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#define ENOIOCTLCMD 515 /* No ioctl command */
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/* Struct */
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struct cvi_csi_status {
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unsigned int errcnt_ecc;
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unsigned int errcnt_crc;
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unsigned int errcnt_hdr;
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unsigned int errcnt_wc;
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unsigned int fifo_full;
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};
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struct cvi_lvds_status {
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unsigned int fifo_full;
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};
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struct cvi_link {
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struct cif_ctx cif_ctx;
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unsigned int irq_num;
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// struct reset_control *phy_reset;
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// struct reset_control *phy_apb_reset;
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unsigned int is_on;
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struct cif_param param;
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struct combo_dev_attr_s attr;
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enum clk_edge_e clk_edge;
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enum output_msb_e msb;
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unsigned int crop_top;
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unsigned int distance_fp;
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int snsr_rst_pin;
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enum of_gpio_flags snsr_rst_pol;
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union {
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struct cvi_csi_status sts_csi;
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struct cvi_lvds_status sts_lvds;
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};
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// struct device *dev;
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enum rx_mac_clk_e mac_clk;
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enum ttl_bt_fmt_out bt_fmt_out;
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};
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struct cvi_cam_clk {
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int is_on;
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// struct clk *clk_o;
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};
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struct cvi_cif_dev {
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uint32_t devno;
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// struct miscdevice miscdev;
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// spinlock_t lock;
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// struct mutex mutex;
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struct cvi_link link[MAX_LINK_NUM];
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// struct cvi_cam_clk clk_cam0;
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// struct cvi_cam_clk clk_cam1;
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// struct cvi_cam_clk vip_sys2;
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// struct cvi_cam_clk clk_div_0_src_vip_sys_2; /* mipipll */
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// struct cvi_cam_clk clk_div_1_src_vip_sys_2; /* fpll */
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unsigned int max_mac_clk;
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void *pad_ctrl;
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};
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#endif //__CVI_CIF_H__
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