5c7dd7acc3
repo: https://github.com/T-head-Semi/linux commit: b1313fe517ca3703119dcc99ef3bbf75ab42bcfb Change-Id: I6cbb35294024ea3a66140e311f4bb705fd7fd626
79 lines
1.7 KiB
C
79 lines
1.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* arch/sh/kernel/cpu/sh2a/clock-sh7203.c
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*
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* SH7203 support for the clock framework
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*
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* Copyright (C) 2007 Kieran Bingham (MPC-Data Ltd)
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*
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* Based on clock-sh7263.c
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* Copyright (C) 2006 Yoshinori Sato
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*
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* Based on clock-sh4.c
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* Copyright (C) 2005 Paul Mundt
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <asm/clock.h>
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#include <asm/freq.h>
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#include <asm/io.h>
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static const int pll1rate[]={8,12,16,0};
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static const int pfc_divisors[]={1,2,3,4,6,8,12};
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#define ifc_divisors pfc_divisors
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static unsigned int pll2_mult;
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static void master_clk_init(struct clk *clk)
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{
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clk->rate *= pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0003] * pll2_mult;
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}
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static struct sh_clk_ops sh7203_master_clk_ops = {
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.init = master_clk_init,
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};
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static unsigned long module_clk_recalc(struct clk *clk)
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{
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int idx = (__raw_readw(FREQCR) & 0x0007);
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return clk->parent->rate / pfc_divisors[idx];
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}
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static struct sh_clk_ops sh7203_module_clk_ops = {
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.recalc = module_clk_recalc,
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};
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static unsigned long bus_clk_recalc(struct clk *clk)
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{
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int idx = (__raw_readw(FREQCR) & 0x0007);
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return clk->parent->rate / pfc_divisors[idx-2];
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}
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static struct sh_clk_ops sh7203_bus_clk_ops = {
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.recalc = bus_clk_recalc,
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};
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static struct sh_clk_ops sh7203_cpu_clk_ops = {
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.recalc = followparent_recalc,
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};
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static struct sh_clk_ops *sh7203_clk_ops[] = {
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&sh7203_master_clk_ops,
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&sh7203_module_clk_ops,
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&sh7203_bus_clk_ops,
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&sh7203_cpu_clk_ops,
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};
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void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx)
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{
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if (test_mode_pin(MODE_PIN1))
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pll2_mult = 4;
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else if (test_mode_pin(MODE_PIN0))
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pll2_mult = 2;
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else
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pll2_mult = 1;
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if (idx < ARRAY_SIZE(sh7203_clk_ops))
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*ops = sh7203_clk_ops[idx];
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}
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