f6d4f57c24
update .gitignore file 1.cv1812h hw_mcu st7789v3 support 2.add sample_panel. [sensor]cv4001 add wdr mode [refactor](PQbin) refactor md5 value calculation way [feat](fastboot): Renew fastboot interface [sensor]drop frame in flip [cv181x][vo]Bring up lvds panel. [sensor]modify vts_reg value and def_vts Change-Id: Ie9ebc4b4a969218cad8a6f4a7a9d5d65e54f155a
237 lines
4.4 KiB
C
237 lines
4.4 KiB
C
#ifndef _U_CVI_VIP_DISP_H_
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#define _U_CVI_VIP_DISP_H_
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#ifndef LANE_MAX_NUM
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#define LANE_MAX_NUM 5
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#endif
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#define MAX_VO_PINS 32
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#define MAX_MCU_INSTR 256
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enum cvi_disp_intf {
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CVI_VIP_DISP_INTF_DSI = 0,
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CVI_VIP_DISP_INTF_BT,
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CVI_VIP_DISP_INTF_I80,
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CVI_VIP_DISP_INTF_HW_MCU,
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CVI_VIP_DISP_INTF_LVDS,
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CVI_VIP_DISP_INTF_MAX,
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};
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struct cvi_dsi_intf_cfg {
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__u32 pixelclock;
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__u8 bitsperdata;
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__u8 lane_id[4];
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__u8 lane_pn_swap[4];
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};
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enum LVDS_OUT_BIT {
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LVDS_OUT_6BIT = 0,
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LVDS_OUT_8BIT,
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LVDS_OUT_10BIT,
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LVDS_OUT_MAX,
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};
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enum LVDS_MODE {
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LVDS_MODE_JEIDA = 0,
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LVDS_MODE_VESA,
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LVDS_MODE_MAX,
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};
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/*
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* @pixelclock: pixel clock in kHz
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*/
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struct cvi_lvds_intf_cfg {
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__u32 pixelclock;
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enum LVDS_OUT_BIT out_bits;
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enum LVDS_MODE mode;
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__u8 chn_num;
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__u8 vs_out_en;
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__u8 hs_out_en;
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__u8 hs_blk_en;
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__u8 msb_lsb_data_swap;
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__u8 serial_msb_first;
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__u8 even_odd_link_swap;
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__u8 enable;
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__s8 lane_id[LANE_MAX_NUM];
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__u8 lane_pn_swap[LANE_MAX_NUM];
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__u32 backlight_gpio_num;
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__s8 backlight_avtive;
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};
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enum sclr_top_vo_bt_mux {
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SCLR_VO_MUX_BT_VS = 0,
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SCLR_VO_MUX_BT_HS,
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SCLR_VO_MUX_BT_HDE,
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SCLR_VO_MUX_BT_DATA0,
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SCLR_VO_MUX_BT_DATA1,
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SCLR_VO_MUX_BT_DATA2,
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SCLR_VO_MUX_BT_DATA3,
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SCLR_VO_MUX_BT_DATA4,
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SCLR_VO_MUX_BT_DATA5,
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SCLR_VO_MUX_BT_DATA6,
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SCLR_VO_MUX_BT_DATA7,
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SCLR_VO_MUX_BT_DATA8,
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SCLR_VO_MUX_BT_DATA9,
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SCLR_VO_MUX_BT_DATA10,
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SCLR_VO_MUX_BT_DATA11,
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SCLR_VO_MUX_BT_DATA12,
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SCLR_VO_MUX_BT_DATA13,
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SCLR_VO_MUX_BT_DATA14,
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SCLR_VO_MUX_BT_DATA15,
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SCLR_VO_MUX_TG_HS_TILE = 30,
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SCLR_VO_MUX_TG_VS_TILE,
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SCLR_VO_BT_MUX_MAX,
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};
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enum sclr_top_vo_mcu_mux {
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SCLR_VO_MUX_MCU_CS = 0,
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SCLR_VO_MUX_MCU_RS,
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SCLR_VO_MUX_MCU_WR,
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SCLR_VO_MUX_MCU_RD,
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SCLR_VO_MUX_MCU_DATA0,
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SCLR_VO_MUX_MCU_DATA1,
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SCLR_VO_MUX_MCU_DATA2,
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SCLR_VO_MUX_MCU_DATA3,
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SCLR_VO_MUX_MCU_DATA4,
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SCLR_VO_MUX_MCU_DATA5,
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SCLR_VO_MUX_MCU_DATA6,
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SCLR_VO_MUX_MCU_DATA7,
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SCLR_VO_MCU_MUX_MAX,
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};
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enum sclr_top_vo_sel {
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SCLR_VO_CLK0 = 0,
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SCLR_VO_CLK1,
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SCLR_VO_D0,
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SCLR_VO_D1,
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SCLR_VO_D2,
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SCLR_VO_D3,
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SCLR_VO_D4,
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SCLR_VO_D5,
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SCLR_VO_D6,
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SCLR_VO_D7,
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SCLR_VO_D8,
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SCLR_VO_D9,
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SCLR_VO_D10,
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SCLR_VO_D11,
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SCLR_VO_D12,
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SCLR_VO_D13,
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SCLR_VO_D14,
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SCLR_VO_D15,
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SCLR_VO_D16,
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SCLR_VO_D17,
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SCLR_VO_D18,
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SCLR_VO_D19,
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SCLR_VO_D20,
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SCLR_VO_D21,
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SCLR_VO_D22,
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SCLR_VO_D23,
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SCLR_VO_D24,
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SCLR_VO_D25,
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SCLR_VO_D26,
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SCLR_VO_D27,
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SCLR_VO_D_MAX,
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};
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enum sclr_top_vo_d_sel {
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SCLR_VO_VIVO_D0 = SCLR_VO_D13,
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SCLR_VO_VIVO_D1 = SCLR_VO_D14,
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SCLR_VO_VIVO_D2 = SCLR_VO_D15,
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SCLR_VO_VIVO_D3 = SCLR_VO_D16,
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SCLR_VO_VIVO_D4 = SCLR_VO_D17,
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SCLR_VO_VIVO_D5 = SCLR_VO_D18,
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SCLR_VO_VIVO_D6 = SCLR_VO_D19,
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SCLR_VO_VIVO_D7 = SCLR_VO_D20,
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SCLR_VO_VIVO_D8 = SCLR_VO_D21,
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SCLR_VO_VIVO_D9 = SCLR_VO_D22,
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SCLR_VO_VIVO_D10 = SCLR_VO_D23,
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SCLR_VO_VIVO_CLK = SCLR_VO_CLK1,
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SCLR_VO_MIPI_TXM4 = SCLR_VO_D24,
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SCLR_VO_MIPI_TXP4 = SCLR_VO_D25,
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SCLR_VO_MIPI_TXM3 = SCLR_VO_D26,
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SCLR_VO_MIPI_TXP3 = SCLR_VO_D27,
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SCLR_VO_MIPI_TXM2 = SCLR_VO_D0,
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SCLR_VO_MIPI_TXP2 = SCLR_VO_CLK0,
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SCLR_VO_MIPI_TXM1 = SCLR_VO_D2,
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SCLR_VO_MIPI_TXP1 = SCLR_VO_D1,
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SCLR_VO_MIPI_TXM0 = SCLR_VO_D4,
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SCLR_VO_MIPI_TXP0 = SCLR_VO_D3,
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SCLR_VO_MIPI_RXN5 = SCLR_VO_D12,
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SCLR_VO_MIPI_RXP5 = SCLR_VO_D11,
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SCLR_VO_MIPI_RXN2 = SCLR_VO_D10,
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SCLR_VO_MIPI_RXP2 = SCLR_VO_D9,
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SCLR_VO_MIPI_RXN1 = SCLR_VO_D8,
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SCLR_VO_MIPI_RXP1 = SCLR_VO_D7,
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SCLR_VO_MIPI_RXN0 = SCLR_VO_D6,
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SCLR_VO_MIPI_RXP0 = SCLR_VO_D5,
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SCLR_VO_PAD_MAX = SCLR_VO_D_MAX
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};
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struct vo_d_remap {
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enum sclr_top_vo_d_sel sel;
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__u32 mux;
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};
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struct vo_pins {
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unsigned char pin_num;
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struct vo_d_remap d_pins[MAX_VO_PINS];
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};
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enum BT_MODE {
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BT_MODE_656 = 0,
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BT_MODE_1120,
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BT_MODE_601,
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BT_MODE_MAX,
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};
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/*
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* @pixelclock: pixel clock in kHz
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*/
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struct cvi_bt_intf_cfg {
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__u32 pixelclock;
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enum BT_MODE mode;
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struct vo_pins pins;
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};
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struct cvi_i80_instr {
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__u8 delay;
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__u8 data_type;
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__u8 data;
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};
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enum MCU_MODE {
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MCU_MODE_RGB565 = 0,
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MCU_MODE_RGB888,
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MCU_MODE_MAX,
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};
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struct MCU_INSTRS {
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unsigned char instr_num;
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struct cvi_i80_instr instr_cmd[MAX_MCU_INSTR];
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};
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struct cvi_hw_mcu_intf_cfg {
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enum MCU_MODE mode;
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struct vo_pins pins;
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__u32 lcd_power_gpio_num;
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__s8 lcd_power_avtive;
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__u32 backlight_gpio_num;
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__s8 backlight_avtive;
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__u32 reset_gpio_num;
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__s8 reset_avtive;
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struct MCU_INSTRS instrs;
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__u32 pixelclock;
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};
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struct cvi_disp_intf_cfg {
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enum cvi_disp_intf intf_type;
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union {
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struct cvi_dsi_intf_cfg dsi_cfg;
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struct cvi_lvds_intf_cfg lvds_cfg;
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struct cvi_bt_intf_cfg bt_cfg;
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struct cvi_hw_mcu_intf_cfg mcu_cfg;
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};
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};
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#endif // _U_CVI_VIP_DISP_H_
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