5c7dd7acc3
repo: https://github.com/T-head-Semi/linux commit: b1313fe517ca3703119dcc99ef3bbf75ab42bcfb Change-Id: I6cbb35294024ea3a66140e311f4bb705fd7fd626
33 lines
1.0 KiB
Plaintext
33 lines
1.0 KiB
Plaintext
What: /sys/class/iommu/<iommu>/intel-iommu/address
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Date: June 2014
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KernelVersion: 3.17
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Contact: Alex Williamson <alex.williamson@redhat.com>
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Description:
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Physical address of the VT-d DRHD for this IOMMU.
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Format: %llx. This allows association of a sysfs
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intel-iommu with a DMAR DRHD table entry.
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What: /sys/class/iommu/<iommu>/intel-iommu/cap
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Date: June 2014
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KernelVersion: 3.17
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Contact: Alex Williamson <alex.williamson@redhat.com>
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Description:
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The cached hardware capability register value
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of this DRHD unit. Format: %llx.
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What: /sys/class/iommu/<iommu>/intel-iommu/ecap
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Date: June 2014
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KernelVersion: 3.17
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Contact: Alex Williamson <alex.williamson@redhat.com>
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Description:
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The cached hardware extended capability register
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value of this DRHD unit. Format: %llx.
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What: /sys/class/iommu/<iommu>/intel-iommu/version
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Date: June 2014
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KernelVersion: 3.17
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Contact: Alex Williamson <alex.williamson@redhat.com>
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Description:
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The architecture version as reported from the
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VT-d VER_REG. Format: %d:%d, major:minor
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