f8fc109960
repo: https://github.com/u-boot/u-boot commit: d80bb749fab53da72c4a0e09b8c2d2aaa3103c91 Change-Id: Ie6434426e1ec15bc08bb1832798e371f3fd5fb29
67 lines
1.6 KiB
C
67 lines
1.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Interrupt Timer Subsystem
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*
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* Copyright (C) 2017 Intel Corporation.
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* Copyright 2019 Google LLC
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*
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* Modified from coreboot itss.h
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*/
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#ifndef _ASM_ARCH_ITSS_H
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#define _ASM_ARCH_ITSS_H
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#include <irq.h>
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#define GPIO_IRQ_START 50
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#define GPIO_IRQ_END ITSS_MAX_IRQ
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#define ITSS_MAX_IRQ 119
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#define IRQS_PER_IPC 32
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#define NUM_IPC_REGS DIV_ROUND_UP(ITSS_MAX_IRQ, IRQS_PER_IPC)
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/* Max PXRC registers in ITSS */
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#define MAX_PXRC_CONFIG (PCR_ITSS_PIRQH_ROUT - PCR_ITSS_PIRQA_ROUT + 1)
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/* PIRQA Routing Control Register */
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#define PCR_ITSS_PIRQA_ROUT 0x3100
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/* PIRQB Routing Control Register */
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#define PCR_ITSS_PIRQB_ROUT 0x3101
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/* PIRQC Routing Control Register */
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#define PCR_ITSS_PIRQC_ROUT 0x3102
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/* PIRQD Routing Control Register */
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#define PCR_ITSS_PIRQD_ROUT 0x3103
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/* PIRQE Routing Control Register */
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#define PCR_ITSS_PIRQE_ROUT 0x3104
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/* PIRQF Routing Control Register */
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#define PCR_ITSS_PIRQF_ROUT 0x3105
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/* PIRQG Routing Control Register */
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#define PCR_ITSS_PIRQG_ROUT 0x3106
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/* PIRQH Routing Control Register */
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#define PCR_ITSS_PIRQH_ROUT 0x3107
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/* ITSS Interrupt polarity control */
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#define PCR_ITSS_IPC0_CONF 0x3200
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/* ITSS Power reduction control */
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#define PCR_ITSS_ITSSPRC 0x3300
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struct itss_plat {
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#if CONFIG_IS_ENABLED(OF_PLATDATA)
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/* Put this first since driver model will copy the data here */
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struct dtd_intel_itss dtplat;
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#endif
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};
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/* struct pmc_route - Routing for PMC to GPIO */
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struct pmc_route {
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u32 pmc;
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u32 gpio;
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};
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struct itss_priv {
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struct pmc_route *route;
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uint route_count;
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u32 irq_snapshot[NUM_IPC_REGS];
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};
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#endif /* _ASM_ARCH_ITSS_H */
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