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/*
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* @brief SMSC 87x0 simple PHY driver
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*
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* @note
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* Copyright(C) NXP Semiconductors, 2012
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* All rights reserved.
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*
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* @par
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* LPC products. This software is supplied "AS IS" without any warranties of
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* any kind, and NXP Semiconductors and its licensor disclaim any and
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* all warranties, express or implied, including all implied warranties of
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* merchantability, fitness for a particular purpose and non-infringement of
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* intellectual property rights. NXP Semiconductors assumes no responsibility
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* or liability for the use of the software, conveys no license or rights under any
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* patent, copyright, mask work right, or any other intellectual property rights in
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* or to any products. NXP Semiconductors reserves the right to make changes
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* in the software without notification. NXP Semiconductors also makes no
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* representation or warranty that such application will be suitable for the
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* specified use without further testing or modification.
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*
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* @par
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors' and its
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* licensor's relevant copyrights in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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*/
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#include "chip.h"
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#include "lpc_phy.h"
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/** @defgroup SMSC87X0_PHY BOARD: PHY status and control driver for the SMSC 87x0
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* @ingroup BOARD_PHY
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* Various functions for controlling and monitoring the status of the
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* SMSC 87x0 PHY.
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* @{
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*/
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/* LAN8720 PHY register offsets */
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#define LAN8_BCR_REG 0x0 /*!< Basic Control Register */
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#define LAN8_BSR_REG 0x1 /*!< Basic Status Reg */
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#define LAN8_PHYID1_REG 0x2 /*!< PHY ID 1 Reg */
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#define LAN8_PHYID2_REG 0x3 /*!< PHY ID 2 Reg */
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#define LAN8_PHYSPLCTL_REG 0x1F/*!< PHY special control/status Reg */
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/* LAN8720 BCR register definitions */
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#define LAN8_RESET (1 << 15) /*!< 1= S/W Reset */
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#define LAN8_LOOPBACK (1 << 14) /*!< 1=loopback Enabled */
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#define LAN8_SPEED_SELECT (1 << 13) /*!< 1=Select 100MBps */
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#define LAN8_AUTONEG (1 << 12) /*!< 1=Enable auto-negotiation */
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#define LAN8_POWER_DOWN (1 << 11) /*!< 1=Power down PHY */
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#define LAN8_ISOLATE (1 << 10) /*!< 1=Isolate PHY */
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#define LAN8_RESTART_AUTONEG (1 << 9) /*!< 1=Restart auto-negoatiation */
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#define LAN8_DUPLEX_MODE (1 << 8) /*!< 1=Full duplex mode */
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/* LAN8720 BSR register definitions */
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#define LAN8_100BASE_T4 (1 << 15) /*!< T4 mode */
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#define LAN8_100BASE_TX_FD (1 << 14) /*!< 100MBps full duplex */
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#define LAN8_100BASE_TX_HD (1 << 13) /*!< 100MBps half duplex */
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#define LAN8_10BASE_T_FD (1 << 12) /*!< 100Bps full duplex */
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#define LAN8_10BASE_T_HD (1 << 11) /*!< 10MBps half duplex */
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#define LAN8_AUTONEG_COMP (1 << 5) /*!< Auto-negotation complete */
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#define LAN8_RMT_FAULT (1 << 4) /*!< Fault */
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#define LAN8_AUTONEG_ABILITY (1 << 3) /*!< Auto-negotation supported */
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#define LAN8_LINK_STATUS (1 << 2) /*!< 1=Link active */
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#define LAN8_JABBER_DETECT (1 << 1) /*!< Jabber detect */
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#define LAN8_EXTEND_CAPAB (1 << 0) /*!< Supports extended capabilities */
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/* LAN8720 PHYSPLCTL status definitions */
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#define LAN8_SPEEDMASK (7 << 2) /*!< Speed and duplex mask */
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#define LAN8_SPEED100F (6 << 2) /*!< 100BT full duplex */
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#define LAN8_SPEED10F (5 << 2) /*!< 10BT full duplex */
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#define LAN8_SPEED100H (2 << 2) /*!< 100BT half duplex */
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#define LAN8_SPEED10H (1 << 2) /*!< 10BT half duplex */
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/* LAN8720 PHY ID 1/2 register definitions */
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#define LAN8_PHYID1_OUI 0x0007 /*!< Expected PHY ID1 */
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#define LAN8_PHYID2_OUI 0xC0F0 /*!< Expected PHY ID2, except last 4 bits */
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/* DP83848 PHY update flags */
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static uint32_t physts, olddphysts;
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/* PHY update counter for state machine */
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static int32_t phyustate;
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/* Pointer to delay function used for this driver */
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static p_msDelay_func_t pDelayMs;
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/* Write to the PHY. Will block for delays based on the pDelayMs function. Returns
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true on success, or false on failure */
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static Status lpc_mii_write(uint8_t reg, uint16_t data)
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{
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Status sts = ERROR;
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int32_t mst = 250;
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/* Write value for register */
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Chip_ENET_StartMIIWrite(LPC_ETHERNET, reg, data);
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/* Wait for unbusy status */
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while (mst > 0) {
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if (Chip_ENET_IsMIIBusy(LPC_ETHERNET)) {
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mst--;
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pDelayMs(1);
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}
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else {
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mst = 0;
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sts = SUCCESS;
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}
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}
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return sts;
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}
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/* Read from the PHY. Will block for delays based on the pDelayMs function. Returns
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true on success, or false on failure */
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static Status lpc_mii_read(uint8_t reg, uint16_t *data)
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{
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Status sts = ERROR;
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int32_t mst = 250;
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/* Start register read */
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Chip_ENET_StartMIIRead(LPC_ETHERNET, reg);
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/* Wait for unbusy status */
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while (mst > 0) {
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if (!Chip_ENET_IsMIIBusy(LPC_ETHERNET)) {
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mst = 0;
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*data = Chip_ENET_ReadMIIData(LPC_ETHERNET);
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sts = SUCCESS;
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}
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else {
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mst--;
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pDelayMs(1);
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}
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}
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return sts;
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}
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/* Update PHY status from passed value */
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static void smsc_update_phy_sts(uint16_t linksts, uint16_t sdsts)
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{
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/* Update link active status */
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if (linksts & LAN8_LINK_STATUS) {
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physts |= PHY_LINK_CONNECTED;
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}
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else {
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physts &= ~PHY_LINK_CONNECTED;
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}
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switch (sdsts & LAN8_SPEEDMASK) {
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case LAN8_SPEED100F:
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default:
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physts |= PHY_LINK_SPEED100;
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physts |= PHY_LINK_FULLDUPLX;
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break;
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case LAN8_SPEED10F:
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physts &= ~PHY_LINK_SPEED100;
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physts |= PHY_LINK_FULLDUPLX;
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break;
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case LAN8_SPEED100H:
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physts |= PHY_LINK_SPEED100;
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physts &= ~PHY_LINK_FULLDUPLX;
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break;
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case LAN8_SPEED10H:
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physts &= ~PHY_LINK_SPEED100;
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physts &= ~PHY_LINK_FULLDUPLX;
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break;
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}
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/* If the status has changed, indicate via change flag */
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if ((physts & (PHY_LINK_SPEED100 | PHY_LINK_FULLDUPLX | PHY_LINK_CONNECTED)) !=
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(olddphysts & (PHY_LINK_SPEED100 | PHY_LINK_FULLDUPLX | PHY_LINK_CONNECTED))) {
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olddphysts = physts;
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physts |= PHY_LINK_CHANGED;
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}
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}
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/* Initialize the SMSC 87x0 PHY */
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uint32_t lpc_phy_init(bool rmii, p_msDelay_func_t pDelayMsFunc)
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{
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uint16_t tmp;
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int32_t i;
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pDelayMs = pDelayMsFunc;
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/* Initial states for PHY status and state machine */
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olddphysts = physts = phyustate = 0;
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/* Only first read and write are checked for failure */
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/* Put the DP83848C in reset mode and wait for completion */
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if (lpc_mii_write(LAN8_BCR_REG, LAN8_RESET) != SUCCESS) {
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return ERROR;
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}
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i = 400;
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while (i > 0) {
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pDelayMs(1);
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if (lpc_mii_read(LAN8_BCR_REG, &tmp) != SUCCESS) {
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return ERROR;
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}
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if (!(tmp & (LAN8_RESET | LAN8_POWER_DOWN))) {
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i = -1;
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}
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else {
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i--;
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}
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}
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/* Timeout? */
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if (i == 0) {
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return ERROR;
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}
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/* Setup link */
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lpc_mii_write(LAN8_BCR_REG, LAN8_AUTONEG);
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/* The link is not set active at this point, but will be detected
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later */
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return SUCCESS;
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}
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/* Phy status update state machine */
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uint32_t lpcPHYStsPoll(void)
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{
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static uint16_t sts;
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switch (phyustate) {
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default:
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case 0:
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/* Read BMSR to clear faults */
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Chip_ENET_StartMIIRead(LPC_ETHERNET, LAN8_BSR_REG);
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physts &= ~PHY_LINK_CHANGED;
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physts = physts | PHY_LINK_BUSY;
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phyustate = 1;
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break;
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case 1:
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/* Wait for read status state */
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if (!Chip_ENET_IsMIIBusy(LPC_ETHERNET)) {
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/* Get PHY status with link state */
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sts = Chip_ENET_ReadMIIData(LPC_ETHERNET);
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Chip_ENET_StartMIIRead(LPC_ETHERNET, LAN8_PHYSPLCTL_REG);
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phyustate = 2;
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}
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break;
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case 2:
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/* Wait for read status state */
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if (!Chip_ENET_IsMIIBusy(LPC_ETHERNET)) {
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/* Update PHY status */
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physts &= ~PHY_LINK_BUSY;
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smsc_update_phy_sts(sts, Chip_ENET_ReadMIIData(LPC_ETHERNET));
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phyustate = 0;
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}
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break;
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}
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return physts;
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}
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/**
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* @}
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*/
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