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yegaogang
2024-07-08 21:03:06 +08:00
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Examples/CMakeLists.txt Normal file
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ADD_SUBDIRECTORY(NfcrdlibEx1_DiscoveryLoop)
IF(NOT FRONTEND_RC663)
ADD_SUBDIRECTORY(NfcrdlibEx3_NFCForum)
ENDIF()
ADD_SUBDIRECTORY(NfcrdlibEx4_MIFAREClassic)
ADD_SUBDIRECTORY(NfcrdlibEx5_ISO15693)
ADD_SUBDIRECTORY(NfcrdlibEx6_LPCD)
IF(NOT FRONTEND_RC663)
ADD_SUBDIRECTORY(NfcrdlibEx8_HCE_T4T)
ENDIF()
ADD_SUBDIRECTORY(NfcrdlibEx9_NTagI2C)
IF(WITH_NDA)
ADD_SUBDIRECTORY(NfcrdlibEx7_MIFAREPlus)
ADD_SUBDIRECTORY(NfcrdlibEx10_MIFAREDESFire_EVx)
ENDIF()
ADD_SUBDIRECTORY(Nfcrdlib_SimplifiedAPI_ISO)
IF(WITH_ECP)
ADD_SUBDIRECTORY(NfcrdlibEx2_ECP)
ENDIF()

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PROJECT(NfcrdlibEx1_DiscoveryLoop)
FILE(GLOB NfcrdlibEx1_DiscoveryLoop_Sources
*.c
src/*.c
)
include_directories(
intfs
types
)
ADD_EXECUTABLE(NfcrdlibEx1_DiscoveryLoop
${NfcrdlibEx1_DiscoveryLoop_Sources}
)
TARGET_LINK_LIBRARIES(
NfcrdlibEx1_DiscoveryLoop
phOsal
DAL
NxpRdLib_acDiscLoop
NxpRdLib_halHw
NxpRdLib_KeyStore
NxpRdLib_phTools
NxpRdLib_palFelica
NxpRdLib_palI18092mPI
NxpRdLib_palI14443p4a
NxpRdLib_palI14443p4
NxpRdLib_palI14443p4
NxpRdLib_palMifare
NxpRdLib_alFelica
NxpRdLib_alMful
NxpRdLib_alMfdf
NxpRdLib_alT1T
NxpRdLib_alTop
NxpRdLib_alMfc
NxpRdLib_lnLlcp
NxpRdLib_palI18092mT
NxpRdLib_CryptoSym
NxpRdLib_CryptoRng
NxpRdLib_palI14443p4mC
NxpRdLib_ceT4T
NxpRdLib_palEpcUid
NxpRdLib_alMfdfEVx
NxpRdLib_alMfNtag42XDna
NxpRdLib_phNfcLib
)

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/*----------------------------------------------------------------------------*/
/* Copyright 2016-2023 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may only */
/* be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that you */
/* have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*----------------------------------------------------------------------------*/
/** \file
* Example Source for NfcrdlibEx1_DiscoveryLoop that uses the Discovery loop implementation.
* By default Discovery Loop will work as per NFC Forum Activity Specification v2.2
* which will configure the Reader in both POLL and LISTEN (only for Universal device)
* modes of discovery loop.Displays detected tag information(like UID, SAK, Product Type)
* and prints information when it gets activated as a target by an external Initiator/reader.
*
* By enabling "ENABLE_DISC_CONFIG" macro, few of the most common Discovery Loop configuration
* are been updated to values defined in this Example.
* By enabling "ENABLE_EMVCO_PROF", Discovery Loop will be configured as per EMVCo Polling
* specification else the Discovery Loop will still be configured to NFC Forum but user defined
* values as per this Application.
*
* NFC Forum Mode: Whenever multiple technologies are detected, example will select first
* detected technology to resolve. Example will activate device at index zero whenever multiple
* device is detected.
*
* For EMVCo profile, this example provide full EMVCo digital demonstration along with option to
* use different SELECT PPSE Commands.
*
* Please refer Readme.txt file for Hardware Pin Configuration, Software Configuration and steps to build and
* execute the project which is present in the same project directory.
*
* $Author$
* $Revision$ (v07.10.00)
* $Date$
*/
/**
* Reader Library Headers
*/
#include <phApp_Init.h>
/* Local headers */
#include <NfcrdlibEx1_DiscoveryLoop.h>
#include <NfcrdlibEx1_EmvcoProfile.h>
/*******************************************************************************
** Definitions
*******************************************************************************/
phacDiscLoop_Sw_DataParams_t * pDiscLoop; /* Discovery loop component */
/*The below variables needs to be initialized according to example requirements by a customer */
uint8_t sens_res[2] = {0x04, 0x00}; /* ATQ bytes - needed for anti-collision */
uint8_t nfc_id1[3] = {0xA1, 0xA2, 0xA3}; /* user defined bytes of the UID (one is hardcoded) - needed for anti-collision */
uint8_t sel_res = 0x40;
uint8_t nfc_id3 = 0xFA; /* NFC3 byte - required for anti-collision */
uint8_t poll_res[18] = {0x01, 0xFE, 0xB2, 0xB3, 0xB4, 0xB5,
0xB6, 0xB7, 0xC0, 0xC1, 0xC2, 0xC3,
0xC4, 0xC5, 0xC6, 0xC7, 0x23, 0x45 };
#ifdef PHOSAL_FREERTOS_STATIC_MEM_ALLOCATION
uint32_t aDiscTaskBuffer[DISC_DEMO_TASK_STACK];
#else /* PHOSAL_FREERTOS_STATIC_MEM_ALLOCATION */
#define aDiscTaskBuffer NULL
#endif /* PHOSAL_FREERTOS_STATIC_MEM_ALLOCATION */
#ifdef PH_OSAL_FREERTOS
const uint8_t bTaskName[configMAX_TASK_NAME_LEN] = {"DiscLoop"};
#else
const uint8_t bTaskName[] = {"DiscLoop"};
#endif /* PH_OSAL_FREERTOS */
/*******************************************************************************
** Static Defines
*******************************************************************************/
/* This is used to save restore Poll Config.
* If in case application has update/change PollCfg to resolve Tech
* when Multiple Tech was detected in previous poll cycle
*/
static uint16_t bSavePollTechCfg;
static volatile uint8_t bInfLoop = 1U;
/*******************************************************************************
** Prototypes
*******************************************************************************/
void DiscoveryLoop_Demo(void *pDataParams);
uint16_t NFCForumProcess(uint16_t wEntryPoint, phStatus_t DiscLoopStatus);
#ifdef ENABLE_DISC_CONFIG
static phStatus_t LoadProfile(phacDiscLoop_Profile_t bProfile);
#endif /* ENABLE_DISC_CONFIG */
/*******************************************************************************
** Code
*******************************************************************************/
int main(void)
{
do
{
phStatus_t status = PH_ERR_INTERNAL_ERROR;
phNfcLib_Status_t dwStatus;
#ifdef PH_PLATFORM_HAS_ICFRONTEND
phNfcLib_AppContext_t AppContext = {0};
#endif /* PH_PLATFORM_HAS_ICFRONTEND */
#ifndef PH_OSAL_NULLOS
phOsal_ThreadObj_t DiscLoop;
#endif /* PH_OSAL_NULLOS */
/* Perform Controller specific initialization. */
phApp_CPU_Init();
/* Perform OSAL Initialization. */
(void)phOsal_Init();
DEBUG_PRINTF("\n DiscoveryLoop Example: \n");
#ifdef PH_PLATFORM_HAS_ICFRONTEND
status = phbalReg_Init(&sBalParams, sizeof(phbalReg_Type_t));
CHECK_STATUS(status);
AppContext.pBalDataparams = &sBalParams;
dwStatus = phNfcLib_SetContext(&AppContext);
CHECK_NFCLIB_STATUS(dwStatus);
#endif
/* Initialize library */
dwStatus = phNfcLib_Init();
CHECK_NFCLIB_STATUS(dwStatus);
if(dwStatus != PH_NFCLIB_STATUS_SUCCESS) break;
/* Set the generic pointer */
pHal = phNfcLib_GetDataParams(PH_COMP_HAL);
pDiscLoop = phNfcLib_GetDataParams(PH_COMP_AC_DISCLOOP);
/* Initialize other components that are not initialized by NFCLIB and configure Discovery Loop. */
status = phApp_Comp_Init(pDiscLoop);
CHECK_STATUS(status);
if(status != PH_ERR_SUCCESS) break;
/* Perform Platform Init */
status = phApp_Configure_IRQ();
CHECK_STATUS(status);
if(status != PH_ERR_SUCCESS) break;
#ifndef PH_OSAL_NULLOS
DiscLoop.pTaskName = (uint8_t *)bTaskName;
DiscLoop.pStackBuffer = aDiscTaskBuffer;
DiscLoop.priority = DISC_DEMO_TASK_PRIO;
DiscLoop.stackSizeInNum = DISC_DEMO_TASK_STACK;
phOsal_ThreadCreate(&DiscLoop.ThreadHandle, &DiscLoop, &DiscoveryLoop_Demo, pDiscLoop);
phOsal_StartScheduler();
DEBUG_PRINTF("RTOS Error : Scheduler exited. \n");
#else
(void)DiscoveryLoop_Demo(pDiscLoop);
#endif
} while(0);
while(bInfLoop); /* Comes here if initialization failure or scheduler exit due to error */
return 0;
}
/**
* This function demonstrates the usage of discovery loop.
* The discovery loop can run with default setting Or can be configured as demonstrated and
* is used to detects and reports the NFC technology type.
* \param pDataParams The discovery loop data parameters
* \note This function will never return
*/
void DiscoveryLoop_Demo(void *pDataParams)
{
phStatus_t status, statustmp;
uint16_t wEntryPoint;
phacDiscLoop_Profile_t bProfile = PHAC_DISCLOOP_PROFILE_UNKNOWN;
/* This call shall allocate secure context before calling any secure function,
* when FreeRtos trust zone is enabled.
* */
phOsal_ThreadSecureStack( 512 );
#ifdef ENABLE_DISC_CONFIG
#ifndef ENABLE_EMVCO_PROF
bProfile = PHAC_DISCLOOP_PROFILE_NFC;
#else
bProfile = PHAC_DISCLOOP_PROFILE_EMVCO;
#endif
/* Load selected profile for Discovery loop */
LoadProfile(bProfile);
#endif /* ENABLE_DISC_CONFIG */
#ifdef NXPBUILD__PHHAL_HW_TARGET
/* Initialize the setting for Listen Mode */
status = phApp_HALConfigAutoColl();
CHECK_STATUS(status);
#endif /* NXPBUILD__PHHAL_HW_TARGET */
/* Get Poll Configuration */
status = phacDiscLoop_GetConfig(pDataParams, PHAC_DISCLOOP_CONFIG_PAS_POLL_TECH_CFG, &bSavePollTechCfg);
CHECK_STATUS(status);
/* Start in poll mode */
wEntryPoint = PHAC_DISCLOOP_ENTRY_POINT_POLL;
status = PHAC_DISCLOOP_LPCD_NO_TECH_DETECTED;
/* Switch off RF field */
statustmp = phhalHw_FieldOff(pHal);
CHECK_STATUS(statustmp);
while(1)
{
/* Before polling set Discovery Poll State to Detection , as later in the code it can be changed to e.g. PHAC_DISCLOOP_POLL_STATE_REMOVAL*/
statustmp = phacDiscLoop_SetConfig(pDataParams, PHAC_DISCLOOP_CONFIG_NEXT_POLL_STATE, PHAC_DISCLOOP_POLL_STATE_DETECTION);
CHECK_STATUS(statustmp);
#if !defined(ENABLE_EMVCO_PROF) && defined(PH_EXAMPLE1_LPCD_ENABLE)
#ifdef NXPBUILD__PHHAL_HW_RC663
if (wEntryPoint == PHAC_DISCLOOP_ENTRY_POINT_POLL)
#else
/* Configure LPCD */
if ((status & PH_ERR_MASK) == PHAC_DISCLOOP_LPCD_NO_TECH_DETECTED)
#endif
{
status = phApp_ConfigureLPCD();
CHECK_STATUS(status);
}
/* Bool to enable LPCD feature. */
status = phacDiscLoop_SetConfig(pDataParams, PHAC_DISCLOOP_CONFIG_ENABLE_LPCD, PH_ON);
CHECK_STATUS(status);
#endif /* PH_EXAMPLE1_LPCD_ENABLE*/
/* Start discovery loop */
status = phacDiscLoop_Run(pDataParams, wEntryPoint);
if(bProfile == PHAC_DISCLOOP_PROFILE_EMVCO)
{
#if defined(ENABLE_EMVCO_PROF)
EmvcoProfileProcess(pDataParams, status);
#endif /* ENABLE_EMVCO_PROF */
}
else
{
wEntryPoint = NFCForumProcess(wEntryPoint, status);
/* Set Poll Configuration */
statustmp = phacDiscLoop_SetConfig(pDataParams, PHAC_DISCLOOP_CONFIG_PAS_POLL_TECH_CFG, bSavePollTechCfg);
CHECK_STATUS(statustmp);
/* Switch off RF field */
statustmp = phhalHw_FieldOff(pHal);
CHECK_STATUS(statustmp);
/* Wait for field-off time-out */
statustmp = phhalHw_Wait(pHal, PHHAL_HW_TIME_MICROSECONDS, 5100);
CHECK_STATUS(statustmp);
}
}
}
uint16_t NFCForumProcess(uint16_t wEntryPoint, phStatus_t DiscLoopStatus)
{
phStatus_t status;
uint16_t wTechDetected = 0;
uint16_t wNumberOfTags = 0;
uint16_t wValue;
uint8_t bIndex;
uint16_t wReturnEntryPoint;
if(wEntryPoint == PHAC_DISCLOOP_ENTRY_POINT_POLL)
{
if((DiscLoopStatus & PH_ERR_MASK) == PHAC_DISCLOOP_MULTI_TECH_DETECTED)
{
DEBUG_PRINTF (" \n Multiple technology detected: \n");
status = phacDiscLoop_GetConfig(pDiscLoop, PHAC_DISCLOOP_CONFIG_TECH_DETECTED, &wTechDetected);
CHECK_STATUS(status);
if(PHAC_DISCLOOP_CHECK_ANDMASK(wTechDetected, PHAC_DISCLOOP_POS_BIT_MASK_A))
{
DEBUG_PRINTF (" \tType A detected... \n");
}
if(PHAC_DISCLOOP_CHECK_ANDMASK(wTechDetected, PHAC_DISCLOOP_POS_BIT_MASK_B))
{
DEBUG_PRINTF (" \tType B detected... \n");
}
if(PHAC_DISCLOOP_CHECK_ANDMASK(wTechDetected, PHAC_DISCLOOP_POS_BIT_MASK_F212))
{
DEBUG_PRINTF (" \tType F detected with baud rate 212... \n");
}
if(PHAC_DISCLOOP_CHECK_ANDMASK(wTechDetected, PHAC_DISCLOOP_POS_BIT_MASK_F424))
{
DEBUG_PRINTF (" \tType F detected with baud rate 424... \n");
}
if(PHAC_DISCLOOP_CHECK_ANDMASK(wTechDetected, PHAC_DISCLOOP_POS_BIT_MASK_V))
{
DEBUG_PRINTF(" \tType V / ISO 15693 / T5T detected... \n");
}
/* Select 1st Detected Technology to Resolve*/
for(bIndex = 0; bIndex < PHAC_DISCLOOP_PASS_POLL_MAX_TECHS_SUPPORTED; bIndex++)
{
if(PHAC_DISCLOOP_CHECK_ANDMASK(wTechDetected, (1 << bIndex)))
{
/* Configure for one of the detected technology */
status = phacDiscLoop_SetConfig(pDiscLoop, PHAC_DISCLOOP_CONFIG_PAS_POLL_TECH_CFG, (1 << bIndex));
CHECK_STATUS(status);
break;
}
}
/* Print the technology resolved */
phApp_PrintTech((1 << bIndex));
/* Set Discovery Poll State to collision resolution */
status = phacDiscLoop_SetConfig(pDiscLoop, PHAC_DISCLOOP_CONFIG_NEXT_POLL_STATE, PHAC_DISCLOOP_POLL_STATE_COLLISION_RESOLUTION);
CHECK_STATUS(status);
/* Restart discovery loop in poll mode from collision resolution phase */
DiscLoopStatus = phacDiscLoop_Run(pDiscLoop, wEntryPoint);
}
if((DiscLoopStatus & PH_ERR_MASK) == PHAC_DISCLOOP_MULTI_DEVICES_RESOLVED)
{
/* Get Detected Technology Type */
status = phacDiscLoop_GetConfig(pDiscLoop, PHAC_DISCLOOP_CONFIG_TECH_DETECTED, &wTechDetected);
CHECK_STATUS(status);
/* Get number of tags detected */
status = phacDiscLoop_GetConfig(pDiscLoop, PHAC_DISCLOOP_CONFIG_NR_TAGS_FOUND, &wNumberOfTags);
CHECK_STATUS(status);
DEBUG_PRINTF (" \n Multiple cards resolved: %d cards \n",wNumberOfTags);
phApp_PrintTagInfo(pDiscLoop, wNumberOfTags, wTechDetected);
if(wNumberOfTags > 1)
{
/* Get 1st Detected Technology and Activate device at index 0 */
for(bIndex = 0; bIndex < PHAC_DISCLOOP_PASS_POLL_MAX_TECHS_SUPPORTED; bIndex++)
{
if(PHAC_DISCLOOP_CHECK_ANDMASK(wTechDetected, (1 << bIndex)))
{
DEBUG_PRINTF("\t Activating one card...\n");
status = phacDiscLoop_ActivateCard(pDiscLoop, bIndex, 0);
break;
}
}
if(((status & PH_ERR_MASK) == PHAC_DISCLOOP_DEVICE_ACTIVATED) ||
((status & PH_ERR_MASK) == PHAC_DISCLOOP_PASSIVE_TARGET_ACTIVATED) ||
((status & PH_ERR_MASK) == PHAC_DISCLOOP_MERGED_SEL_RES_FOUND))
{
/* Get Detected Technology Type */
status = phacDiscLoop_GetConfig(pDiscLoop, PHAC_DISCLOOP_CONFIG_TECH_DETECTED, &wTechDetected);
CHECK_STATUS(status);
phApp_PrintTagInfo(pDiscLoop, 0x01, wTechDetected);
}
else
{
PRINT_INFO("\t\tCard activation failed...\n");
}
}
/* Switch to LISTEN mode after POLL mode */
}
else if (((DiscLoopStatus & PH_ERR_MASK) == PHAC_DISCLOOP_NO_TECH_DETECTED) ||
((DiscLoopStatus & PH_ERR_MASK) == PHAC_DISCLOOP_NO_DEVICE_RESOLVED))
{
/* Switch to LISTEN mode after POLL mode */
}
else if((DiscLoopStatus & PH_ERR_MASK) == PHAC_DISCLOOP_EXTERNAL_RFON)
{
/*
* If external RF is detected during POLL, return back so that the application
* can restart the loop in LISTEN mode
*/
}
else if((DiscLoopStatus & PH_ERR_MASK) == PHAC_DISCLOOP_MERGED_SEL_RES_FOUND)
{
DEBUG_PRINTF (" \n Device having T4T and NFC-DEP support detected... \n");
/* Get Detected Technology Type */
status = phacDiscLoop_GetConfig(pDiscLoop, PHAC_DISCLOOP_CONFIG_TECH_DETECTED, &wTechDetected);
CHECK_STATUS(status);
phApp_PrintTagInfo(pDiscLoop, 1, wTechDetected);
/* Switch to LISTEN mode after POLL mode */
}
else if((DiscLoopStatus & PH_ERR_MASK) == PHAC_DISCLOOP_DEVICE_ACTIVATED)
{
DEBUG_PRINTF (" \n Card detected and activated successfully... \n");
status = phacDiscLoop_GetConfig(pDiscLoop, PHAC_DISCLOOP_CONFIG_NR_TAGS_FOUND, &wNumberOfTags);
CHECK_STATUS(status);
/* Get Detected Technology Type */
status = phacDiscLoop_GetConfig(pDiscLoop, PHAC_DISCLOOP_CONFIG_TECH_DETECTED, &wTechDetected);
CHECK_STATUS(status);
phApp_PrintTagInfo(pDiscLoop, wNumberOfTags, wTechDetected);
/* Switch to LISTEN mode after POLL mode */
}
else if((DiscLoopStatus & PH_ERR_MASK) == PHAC_DISCLOOP_ACTIVE_TARGET_ACTIVATED)
{
DEBUG_PRINTF (" \n Active target detected... \n");
/* Switch to LISTEN mode after POLL mode */
}
else if((DiscLoopStatus & PH_ERR_MASK) == PHAC_DISCLOOP_PASSIVE_TARGET_ACTIVATED)
{
DEBUG_PRINTF (" \n Passive target detected... \n");
/* Get Detected Technology Type */
status = phacDiscLoop_GetConfig(pDiscLoop, PHAC_DISCLOOP_CONFIG_TECH_DETECTED, &wTechDetected);
CHECK_STATUS(status);
phApp_PrintTagInfo(pDiscLoop, 1, wTechDetected);
/* Switch to LISTEN mode after POLL mode */
}
else if ((DiscLoopStatus & PH_ERR_MASK) == PHAC_DISCLOOP_LPCD_NO_TECH_DETECTED)
{
/* LPCD is succeed but no tag is detected. */
}
else
{
if((DiscLoopStatus & PH_ERR_MASK) == PHAC_DISCLOOP_FAILURE)
{
status = phacDiscLoop_GetConfig(pDiscLoop, PHAC_DISCLOOP_CONFIG_ADDITIONAL_INFO, &wValue);
CHECK_STATUS(status);
DEBUG_ERROR_PRINT(PrintErrorInfo(wValue));
}
else
{
DEBUG_ERROR_PRINT(PrintErrorInfo(status));
}
}
/* Update the Entry point to LISTEN mode. */
wReturnEntryPoint = PHAC_DISCLOOP_ENTRY_POINT_LISTEN;
}
else
{
if((DiscLoopStatus & PH_ERR_MASK) == PHAC_DISCLOOP_EXTERNAL_RFOFF)
{
/*
* Enters here if in the target/card mode and external RF is not available
* Wait for LISTEN timeout till an external RF is detected.
* Application may choose to go into standby at this point.
*/
status = phhalHw_EventConsume(pHal);
CHECK_STATUS(status);
status = phhalHw_SetConfig(pHal, PHHAL_HW_CONFIG_RFON_INTERRUPT, PH_ON);
CHECK_STATUS(status);
status = phhalHw_EventWait(pHal, LISTEN_PHASE_TIME_MS);
if((status & PH_ERR_MASK) == PH_ERR_IO_TIMEOUT)
{
wReturnEntryPoint = PHAC_DISCLOOP_ENTRY_POINT_POLL;
}
else
{
wReturnEntryPoint = PHAC_DISCLOOP_ENTRY_POINT_LISTEN;
}
}
else
{
if((DiscLoopStatus & PH_ERR_MASK) == PHAC_DISCLOOP_ACTIVATED_BY_PEER)
{
DEBUG_PRINTF (" \n Device activated in listen mode... \n");
}
else if ((DiscLoopStatus & PH_ERR_MASK) == PH_ERR_INVALID_PARAMETER)
{
/* In case of Front end used is RC663, then listen mode is not supported.
* Switch from listen mode to poll mode. */
}
else
{
if((DiscLoopStatus & PH_ERR_MASK) == PHAC_DISCLOOP_FAILURE)
{
status = phacDiscLoop_GetConfig(pDiscLoop, PHAC_DISCLOOP_CONFIG_ADDITIONAL_INFO, &wValue);
CHECK_STATUS(status);
DEBUG_ERROR_PRINT(PrintErrorInfo(wValue));
}
else
{
DEBUG_ERROR_PRINT(PrintErrorInfo(status));
}
}
/* On successful activated by Peer, switch to LISTEN mode */
wReturnEntryPoint = PHAC_DISCLOOP_ENTRY_POINT_POLL;
}
}
return wReturnEntryPoint;
}
#ifdef ENABLE_DISC_CONFIG
/**
* This function will load/configure Discovery loop with default values based on interested profile
* Application can read these values from EEPROM area and load/configure Discovery loop via SetConfig
* \param bProfile Reader Library Profile
* \note Values used below are default and is for demonstration purpose.
*/
static phStatus_t LoadProfile(phacDiscLoop_Profile_t bProfile)
{
phStatus_t status = PH_ERR_SUCCESS;
uint16_t wPasPollConfig = 0;
uint16_t wActPollConfig = 0;
uint16_t wPasLisConfig = 0;
uint16_t wActLisConfig = 0;
#ifdef NXPBUILD__PHAC_DISCLOOP_TYPEA_TAGS
wPasPollConfig |= PHAC_DISCLOOP_POS_BIT_MASK_A;
#endif
#ifdef NXPBUILD__PHAC_DISCLOOP_TYPEB_TAGS
wPasPollConfig |= PHAC_DISCLOOP_POS_BIT_MASK_B;
#endif
#ifdef NXPBUILD__PHAC_DISCLOOP_TYPEF_TAGS
wPasPollConfig |= (PHAC_DISCLOOP_POS_BIT_MASK_F212 | PHAC_DISCLOOP_POS_BIT_MASK_F424);
#endif
#ifdef NXPBUILD__PHAC_DISCLOOP_TYPEV_TAGS
wPasPollConfig |= PHAC_DISCLOOP_POS_BIT_MASK_V;
#endif
#ifdef NXPBUILD__PHAC_DISCLOOP_I18000P3M3_TAGS
wPasPollConfig |= PHAC_DISCLOOP_POS_BIT_MASK_18000P3M3;
#endif
#ifdef NXPBUILD__PHAC_DISCLOOP_TYPEA_P2P_ACTIVE
wActPollConfig |= PHAC_DISCLOOP_ACT_POS_BIT_MASK_106;
#endif
#ifdef NXPBUILD__PHAC_DISCLOOP_TYPEF212_P2P_ACTIVE
wActPollConfig |= PHAC_DISCLOOP_ACT_POS_BIT_MASK_212;
#endif
#ifdef NXPBUILD__PHAC_DISCLOOP_TYPEF424_P2P_ACTIVE
wActPollConfig |= PHAC_DISCLOOP_ACT_POS_BIT_MASK_424;
#endif
#ifdef NXPBUILD__PHAC_DISCLOOP_TYPEA_TARGET_PASSIVE
wPasLisConfig |= PHAC_DISCLOOP_POS_BIT_MASK_A;
#endif
#ifdef NXPBUILD__PHAC_DISCLOOP_TYPEF212_TARGET_PASSIVE
wPasLisConfig |= PHAC_DISCLOOP_POS_BIT_MASK_F212;
#endif
#ifdef NXPBUILD__PHAC_DISCLOOP_TYPEF424_TARGET_PASSIVE
wPasLisConfig |= PHAC_DISCLOOP_POS_BIT_MASK_F424;
#endif
#ifdef NXPBUILD__PHAC_DISCLOOP_TYPEA_TARGET_ACTIVE
wActLisConfig |= PHAC_DISCLOOP_POS_BIT_MASK_A;
#endif
#ifdef NXPBUILD__PHAC_DISCLOOP_TYPEF212_TARGET_ACTIVE
wActLisConfig |= PHAC_DISCLOOP_POS_BIT_MASK_F212;
#endif
#ifdef NXPBUILD__PHAC_DISCLOOP_TYPEF424_TARGET_ACTIVE
wActLisConfig |= PHAC_DISCLOOP_POS_BIT_MASK_F424;
#endif
if(bProfile == PHAC_DISCLOOP_PROFILE_NFC)
{
/* passive Bailout bitmap config. */
status = phacDiscLoop_SetConfig(pDiscLoop, PHAC_DISCLOOP_CONFIG_BAIL_OUT, 0x00);
CHECK_STATUS(status);
/* Set Passive poll bitmap config. */
status = phacDiscLoop_SetConfig(pDiscLoop, PHAC_DISCLOOP_CONFIG_PAS_POLL_TECH_CFG, wPasPollConfig);
CHECK_STATUS(status);
/* Set Active poll bitmap config. */
status = phacDiscLoop_SetConfig(pDiscLoop, PHAC_DISCLOOP_CONFIG_ACT_POLL_TECH_CFG, wActPollConfig);
CHECK_STATUS(status);
/* Set Passive listen bitmap config. */
status = phacDiscLoop_SetConfig(pDiscLoop, PHAC_DISCLOOP_CONFIG_PAS_LIS_TECH_CFG, wPasLisConfig);
CHECK_STATUS(status);
/* Set Active listen bitmap config. */
status = phacDiscLoop_SetConfig(pDiscLoop, PHAC_DISCLOOP_CONFIG_ACT_LIS_TECH_CFG, wActLisConfig);
CHECK_STATUS(status);
/* reset collision Pending */
status = phacDiscLoop_SetConfig(pDiscLoop, PHAC_DISCLOOP_CONFIG_COLLISION_PENDING, PH_OFF);
CHECK_STATUS(status);
/* whether anti-collision is supported or not. */
status = phacDiscLoop_SetConfig(pDiscLoop, PHAC_DISCLOOP_CONFIG_ANTI_COLL, PH_ON);
CHECK_STATUS(status);
/* Poll Mode default state*/
status = phacDiscLoop_SetConfig(pDiscLoop, PHAC_DISCLOOP_CONFIG_NEXT_POLL_STATE, PHAC_DISCLOOP_POLL_STATE_DETECTION);
CHECK_STATUS(status);
#ifdef NXPBUILD__PHAC_DISCLOOP_TYPEA_TAGS
/* Device limit for Type A */
status = phacDiscLoop_SetConfig(pDiscLoop, PHAC_DISCLOOP_CONFIG_TYPEA_DEVICE_LIMIT, 1);
CHECK_STATUS(status);
/* Passive polling Tx Guard times in micro seconds. */
status = phacDiscLoop_SetConfig(pDiscLoop, PHAC_DISCLOOP_CONFIG_GTA_VALUE_US, 5100);
CHECK_STATUS(status);
#endif
#ifdef NXPBUILD__PHAC_DISCLOOP_TYPEB_TAGS
/* Device limit for Type B */
status = phacDiscLoop_SetConfig(pDiscLoop, PHAC_DISCLOOP_CONFIG_TYPEB_DEVICE_LIMIT, 1);
CHECK_STATUS(status);
status = phacDiscLoop_SetConfig(pDiscLoop, PHAC_DISCLOOP_CONFIG_GTB_VALUE_US, 5100);
CHECK_STATUS(status);
#endif
#ifdef NXPBUILD__PHAC_DISCLOOP_TYPEF_TAGS
/* Device limit for Type F */
status = phacDiscLoop_SetConfig(pDiscLoop, PHAC_DISCLOOP_CONFIG_TYPEF_DEVICE_LIMIT, 1);
CHECK_STATUS(status);
/* Guard time for Type F. This guard time is applied when Type F poll before Type B */
status = phacDiscLoop_SetConfig(pDiscLoop, PHAC_DISCLOOP_CONFIG_GTFB_VALUE_US, 20400);
CHECK_STATUS(status);
/* Guard time for Type F. This guard time is applied when Type B poll before Type F */
status = phacDiscLoop_SetConfig(pDiscLoop, PHAC_DISCLOOP_CONFIG_GTBF_VALUE_US, 15300);
CHECK_STATUS(status);
#endif
#ifdef NXPBUILD__PHAC_DISCLOOP_TYPEV_TAGS
/* Device limit for Type V (ISO 15693) */
status = phacDiscLoop_SetConfig(pDiscLoop, PHAC_DISCLOOP_CONFIG_TYPEV_DEVICE_LIMIT, 1);
CHECK_STATUS(status);
status = phacDiscLoop_SetConfig(pDiscLoop, PHAC_DISCLOOP_CONFIG_GTV_VALUE_US, 5200);
CHECK_STATUS(status);
#endif
#ifdef NXPBUILD__PHAC_DISCLOOP_I18000P3M3_TAGS
/* Device limit for 18000P3M3 */
status = phacDiscLoop_SetConfig(pDiscLoop, PHAC_DISCLOOP_CONFIG_18000P3M3_DEVICE_LIMIT, 1);
CHECK_STATUS(status);
status = phacDiscLoop_SetConfig(pDiscLoop, PHAC_DISCLOOP_CONFIG_GT18000P3M3_VALUE_US, 10000);
CHECK_STATUS(status);
#endif
/* Discovery loop Operation mode */
status = phacDiscLoop_SetConfig(pDiscLoop, PHAC_DISCLOOP_CONFIG_OPE_MODE, RD_LIB_MODE_NFC);
CHECK_STATUS(status);
}
else if(bProfile == PHAC_DISCLOOP_PROFILE_EMVCO)
{
/* EMVCO */
/* passive Bailout bitmap config. */
status = phacDiscLoop_SetConfig(pDiscLoop, PHAC_DISCLOOP_CONFIG_BAIL_OUT, 0x00);
CHECK_STATUS(status);
/* passive poll bitmap config. */
status = phacDiscLoop_SetConfig(pDiscLoop, PHAC_DISCLOOP_CONFIG_PAS_POLL_TECH_CFG, (PHAC_DISCLOOP_POS_BIT_MASK_A | PHAC_DISCLOOP_POS_BIT_MASK_B));
CHECK_STATUS(status);
/* Active Listen bitmap config. */
status = phacDiscLoop_SetConfig(pDiscLoop, PHAC_DISCLOOP_CONFIG_PAS_LIS_TECH_CFG, 0x00);
CHECK_STATUS(status);
/* Active Listen bitmap config. */
status = phacDiscLoop_SetConfig(pDiscLoop, PHAC_DISCLOOP_CONFIG_ACT_LIS_TECH_CFG, 0x00);
CHECK_STATUS(status);
/* Active Poll bitmap config. */
status = phacDiscLoop_SetConfig(pDiscLoop, PHAC_DISCLOOP_CONFIG_ACT_POLL_TECH_CFG, 0x00);
CHECK_STATUS(status);
/* Bool to enable LPCD feature. */
status = phacDiscLoop_SetConfig(pDiscLoop, PHAC_DISCLOOP_CONFIG_ENABLE_LPCD, PH_OFF);
CHECK_STATUS(status);
/* reset collision Pending */
status = phacDiscLoop_SetConfig(pDiscLoop, PHAC_DISCLOOP_CONFIG_COLLISION_PENDING, PH_OFF);
CHECK_STATUS(status);
/* whether anti-collision is supported or not. */
status = phacDiscLoop_SetConfig(pDiscLoop, PHAC_DISCLOOP_CONFIG_ANTI_COLL, PH_ON);
CHECK_STATUS(status);
/* Poll Mode default state*/
status = phacDiscLoop_SetConfig(pDiscLoop, PHAC_DISCLOOP_CONFIG_NEXT_POLL_STATE, PHAC_DISCLOOP_POLL_STATE_DETECTION);
CHECK_STATUS(status);
#ifdef NXPBUILD__PHAC_DISCLOOP_TYPEA_TAGS
/* Device limit for Type A */
status = phacDiscLoop_SetConfig(pDiscLoop, PHAC_DISCLOOP_CONFIG_TYPEA_DEVICE_LIMIT, 1);
CHECK_STATUS(status);
/* Passive polling Tx Guard times in micro seconds. */
status = phacDiscLoop_SetConfig(pDiscLoop, PHAC_DISCLOOP_CONFIG_GTA_VALUE_US, 5100);
CHECK_STATUS(status);
/* Configure FSDI for the 14443P4A tags */
status = phacDiscLoop_SetConfig(pDiscLoop, PHAC_DISCLOOP_CONFIG_TYPEA_I3P4_FSDI, 0x08);
CHECK_STATUS(status);
/* Configure CID for the 14443P4A tags */
status = phacDiscLoop_SetConfig(pDiscLoop, PHAC_DISCLOOP_CONFIG_TYPEA_I3P4_CID, 0x00);
CHECK_STATUS(status);
/* Configure DRI for the 14443P4A tags */
status = phacDiscLoop_SetConfig(pDiscLoop, PHAC_DISCLOOP_CONFIG_TYPEA_I3P4_DRI, 0x00);
CHECK_STATUS(status);
/* Configure DSI for the 14443P4A tags */
status = phacDiscLoop_SetConfig(pDiscLoop, PHAC_DISCLOOP_CONFIG_TYPEA_I3P4_DSI, 0x00);
CHECK_STATUS(status);
#endif
#ifdef NXPBUILD__PHAC_DISCLOOP_TYPEB_TAGS
/* Device limit for Type B */
status = phacDiscLoop_SetConfig(pDiscLoop, PHAC_DISCLOOP_CONFIG_TYPEB_DEVICE_LIMIT, 1);
CHECK_STATUS(status);
status = phacDiscLoop_SetConfig(pDiscLoop, PHAC_DISCLOOP_CONFIG_GTB_VALUE_US, 5100);
CHECK_STATUS(status);
/* Configure AFI for the type B tags */
status = phacDiscLoop_SetConfig(pDiscLoop, PHAC_DISCLOOP_CONFIG_TYPEB_AFI_REQ, 0x00);
CHECK_STATUS(status);
/* Configure FSDI for the type B tags */
status = phacDiscLoop_SetConfig(pDiscLoop, PHAC_DISCLOOP_CONFIG_TYPEB_FSDI, 0x08);
CHECK_STATUS(status);
/* Configure CID for the type B tags */
status = phacDiscLoop_SetConfig(pDiscLoop, PHAC_DISCLOOP_CONFIG_TYPEB_CID, 0x00);
CHECK_STATUS(status);
/* Configure DRI for the type B tags */
status = phacDiscLoop_SetConfig(pDiscLoop, PHAC_DISCLOOP_CONFIG_TYPEB_DRI, 0x00);
CHECK_STATUS(status);
/* Configure DSI for the type B tags */
status = phacDiscLoop_SetConfig(pDiscLoop, PHAC_DISCLOOP_CONFIG_TYPEB_DSI, 0x00);
CHECK_STATUS(status);
/* Configure Extended ATQB support for the type B tags */
status = phacDiscLoop_SetConfig(pDiscLoop, PHAC_DISCLOOP_CONFIG_TYPEB_EXTATQB, 0x00);
CHECK_STATUS(status);
#endif
/* Configure reader library mode */
status = phacDiscLoop_SetConfig(pDiscLoop, PHAC_DISCLOOP_CONFIG_OPE_MODE, RD_LIB_MODE_EMVCO);
CHECK_STATUS(status);
}
else
{
/* Do Nothing */
}
return status;
}
#endif /* ENABLE_DISC_CONFIG */

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__________________________________________________
NXPNFCRDLIB EXAMPLE : NFCRDLIBEX1_DISCOVERYLOOP
(V07.10.00)
__________________________________________________
Table of Contents
_________________
1 Document Purpose
2 Description of the NfcrdlibEx1_DiscoveryLoop
3 Restrictions on NfcrdlibEx1_DiscoveryLoop
4 Configurations of NfcrdlibEx1_DiscoveryLoop
5 Package Contents
6 Mandatory materials (not included)
7 Hardware Configuration
8 Software Configuration
9 Steps to build NfcrdlibEx1_DiscoveryLoop for LPC1769 with PN5190 using MCUXpresso
10 Steps to build NfcrdlibEx1_DiscoveryLoop for LPC1769 with PN5180 using MCUXpresso
11 Steps to build NfcrdlibEx1_DiscoveryLoop for LPC1769 with RC663 using MCUXpresso
12 Steps to build NfcrdlibEx1_DiscoveryLoop for PN7462AU using MCUXpresso
13 Steps to build NfcrdlibEx1_DiscoveryLoop for FRDM-K82F using MCUXpresso
14 Selection of Board / OSAL / Frontend (MCUXpresso)
15 Steps to follow for PI / Linux / CMake
16 Running NfcrdlibEx1_DiscoveryLoop
17 List of supported NFC Reader Boards/ICs
18 Reference Documents
1 Document Purpose
==================
This document describes the steps to be followed to execute
NfcrdlibEx1_DiscoveryLoop example as well as it's known problems and
restrictions.
2 Description of the NfcrdlibEx1_DiscoveryLoop
==============================================
- NfcrdlibEx1_DiscoveryLoop can be run with CLEV663B, PN5180, PN5190
and PN7462AU. (See Section-17 for supported versions)
- This example will use both POLL and LISTEN modes of discovery loop.
- It displays/prints detected tag information (like UID, SAK, Product
Type for MIfare Cards) and prints information when it gets activated
as a target by an external Initiator/reader.
- This example will load/configure Discovery loop with default values
based on the interested profile (Nfc, Emvco) via SetConfig.
- Whenever multiple technologies are detected, example will select
first detected technology to resolve.
- This example will activate device at index zero whenever multiple
devices are detected.
- For EMVCo profile, this example provide full EMVCo digital
demonstration.
3 Restrictions on NfcrdlibEx1_DiscoveryLoop
===========================================
- NfcrdlibEx1_DiscoveryLoop is restricted to be run on NFC Reader
Boards/ICs mentioned in Section-17.
- The APIs are intended for NXP contact-less reader ICs only, as such
the APIs are not to be ported to any technology from any other
vendor.
- NXP will not support porting to any other vendor platform.
- This software project requires NxpNfcRdLib v07.10.00 or later.
- **IMPORTANT** The default used MCU Type is K82. When executing
example on LPC1769 or PN7462AU, the MCU Type has to be changed in
the MCUXpresso IDE.
- For switching to MCU Type to PN7462AU, see Section-12
- For switching to MCU Type to LPC1769, see Section-9, Section-10 and
Section-11.
4 Configurations of NfcrdlibEx1_DiscoveryLoop
=============================================
- The example application can be run with default configuratin Or can
be configured by enabling ENABLE_DISC_CONFIG to different settings
Or can be configure to work as EMVCo digital loopback application,
by enabling both ENABLE_DISC_CONFIG and ENABLE_EMVCO_PROF
- The Default configuration example application is written to detect
and activate one tag of supported technologies.
- Listen mode is supported only for PN5180 and PN7462AU and this
example application receives ATR_REQ or RATS from a NFC Peer/Reader.
Additional functionality is not supported in this example.
- With CLRC663, owing to the hardware limitations of CLRC663, it only
supports poll without Active mode.
5 Package Contents
==================
- Readme.txt
+ This readme file
- NfcrdlibEx1_DiscoveryLoop.c
+ Main example file.
- intfs/NfcrdlibEx1_DiscoveryLoop.h
+ Interfaces/Defines specific to the example
- intfs/ph_NxpBuild_App.h
+ Reader library build configuration file
- src/phApp_Helper.c
- src/phApp_PN5180_Init.c
- src/phApp_PN5190_Init.c
- src/phApp_PN7462AU_Init.c
- src/phApp_RC663_Init.c
- src/phApp_Init.c and intfs/phApp_Init.h
+ Common utility functions (common across all examples)
- src/NfcrdlibEx1_EmvcoProfile.c
+ Emvco profile funtions specific to the example
- mcux/.cproject and mcux/.project
+ MCUXpresso project configuration file
- cr_startup_lpc175x_6x.c
+ Startup required to compile example for LPC1769 Micro Controller.
6 Mandatory materials (not included)
====================================
- MCUXpresso IDE. It can be downloaded from
[http://www.nxp.com/products/:MCUXpresso-IDE]
- SDK for Freedom K82 Board
([http://www.nxp.com/products/:FRDM-K82F]). The pre-build SDK can
be downloaded from
[https://mcuxpresso.nxp.com/en/license?hash=9897a8c19a6bc569c3fade7141f0f405&hash_download=true&to_vault=true]
See MCUXpresso User Manual for steps needed to install an SDK.
- Plugin to extend MCUXpresso to support PN7462AU. (Required for
MCUXpresso versions before MCUXpressoIDE_10.0.2)
- LPCXpresso LPC1769 / Freedom K82 development boards For NFC ICs
listed in Section-17 (Note: PN7462AU (Section-17 Bullet-3) does not
need any other other microcontroller).
7 Hardware Configuration
========================
Before starting this application, HW Changes may be required for the
used board. Refer to the following User Manuals / Application notes
before starting with this example.
- AN11211: Quick Start Up Guide RC663 Blueboard
- AN11744: PN5180 Evaluation board quick start guide
- AN11802: NFC Reader Library for Linux Installation Guidelines
- AN12550: PNEV5190B Evaluation board quick start guide
8 Software Configuration
========================
- The Software can be compiled for Cortex M3 LPC1769 micro-controller,
Cortex M4 Freedom K82 and Cortex M0 based PN7462AU from NXP.
- Since this example can be configured to run on various MCU ICs and
various NFC ICs, appropriate changes are required as mentioned in
Section-9, Section-10, Section-11, Section-12 and Section-13.
9 Steps to build NfcrdlibEx1_DiscoveryLoop for LPC1769 with PN5190 using MCUXpresso
===================================================================================
See "PNEV5190B Evaluation board quick start guide" in AN12550 (See
Section-18, Bullet-6 below)
10 Steps to build NfcrdlibEx1_DiscoveryLoop for LPC1769 with PN5180 using MCUXpresso
====================================================================================
See "Importing provided SW example projects" in AN11908 (See
Section-18, Bullet-2 below)
11 Steps to build NfcrdlibEx1_DiscoveryLoop for LPC1769 with RC663 using MCUXpresso
===================================================================================
See "Importing provided SW example projects" in AN11022 (See
Section-18, Bullet-3 below)
12 Steps to build NfcrdlibEx1_DiscoveryLoop for PN7462AU using MCUXpresso
=========================================================================
- For MCUXpresso versions before MCUXpressoIDE_10.0.2, See "Adding
PN7462AU Plugin" in UM10883. (See Section-18, Bullet-4 below)
- See "Importing provided SW example projects" in UM10883.
13 Steps to build NfcrdlibEx1_DiscoveryLoop for FRDM-K82F using MCUXpresso
==========================================================================
See "Import projects to the MCUXpresso" in AN11908. (See Section-18,
Bullet-2 below)
14 Selection of Board / OSAL / Frontend (MCUXpresso)
====================================================
For MCUXpresso, the selection of Board / OSAL / Frontend has to be
done via -D (Preprocessor defines).
1) To select the board go to "Project Properties" --> "C/C++ Build"
--> "Settings" --> "Preprocessor" --> "Defined symbols (-D)", and
define the relevant PHDRIVER_<BoardNFCCombination>_BOARD macro.
e.g. For using K82 with Pn5190 use PHDRIVER_K82F_PNEV5190B_BOARD
and for LPC1769 with PN5190 use PHDRIVER_LPC1769PN5190_BOARD. For
list of supported boards refer to
Platform\DAL\cfg\BoardSelection.h.
2) To select the osal/os type, go to "Project Properties" --> "C/C++
Build" --> "Settings" --> "Preprocessor" --> "Defined symbols
(-D)".
e.g. For using FreeRTOS use PH_OSAL_FREERTOS. For other options
refer to RTOS\phOsal\inc\phOsal_Config.h.
15 Steps to follow for PI / Linux / CMake
=========================================
The steps are described in AN11802. (See Section-18, Bullet-5 below)
16 Running NfcrdlibEx1_DiscoveryLoop
====================================
When this application is running in default configuration on the
target MCU setup and when you bring the NFC cards or phone in
proximity, the example application will detect and reports the NFC
technology types detected. Upon using MACRO ENABLE_EMVCO_PROF, this
application will work as EMVCo Digital Loopback Application
17 List of supported NFC Reader Boards/ICs
==========================================
1) CLEV6630B v2.0 Customer Evaluation Board
2) PNEV5180B v2.0 Customer Evaluation Board
3) PN7462AU v2.1 Customer Evaluation Board
4) PNEV5190B v1.0 Customer Evaluation Board
18 Reference Documents
======================
1) UM10954 : PN5180 SW Quick start guide
[http://www.nxp.com/docs/en/user-guide/UM10954.pdf]
2) AN11908 : NFC Reader Library for FRDM-K82F Board Installation
guidelines
[http://www.nxp.com/docs/en/application-note/AN11908.pdf]
3) AN11022 : CLRC663 Evaluation board quick start guide
[http://www.nxp.com/docs/en/application-note/AN11022.pdf]
4) UM10883 : PN7462AU Quick Start Guide - Development Kit
[http://www.nxp.com/docs/en/user-guide/UM10883.pdf]
5) AN11802 : NFC Reader Library for Linux Installation Guidelines
[http://www.nxp.com/docs/en/application-note/AN11802.pdf]
6) AN12550 : PNEV5190B Evaluation board quick start guide
----------------------------------------------------------------------
For updates of this example, see
[http://www.nxp.com/products/:NFC-READER-LIBRARY]

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/*----------------------------------------------------------------------------*/
/* Copyright 2016-2021 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may only */
/* be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that you */
/* have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*----------------------------------------------------------------------------*/
/** \file
* Example Source Header for NfcrdlibEx1_DiscoveryLoop application.
*
* $Author: NXP $
* $Revision: $ (v07.10.00)
* $Date: $
*/
#ifndef NFCRDLIBEX1_DISCOVERYLOOP_H
#define NFCRDLIBEX1_DISCOVERYLOOP_H
#include <ph_Status.h>
#if defined (NXPBUILD__PHHAL_HW_PN5180) || \
defined (NXPBUILD__PHHAL_HW_PN5190) || \
defined (NXPBUILD__PHHAL_HW_RC663) || \
defined (NXPBUILD__PHHAL_HW_PN7462AU) || \
defined (NXPBUILD__PHHAL_HW_PN7642)
#define PH_EXAMPLE1_LPCD_ENABLE /* If LPCD needs to be configured and used over HAL or over DiscLoop */
#endif
#define LISTEN_PHASE_TIME_MS 300 /* Listen Phase TIME */
/* Enables configuring of Discovery loop */
#define ENABLE_DISC_CONFIG
/* Enable EMVCO profile in discovery loop i.e. discovery loop will be configured to work in EMVCo mode
* EMVCO is one of the profile in which Discovery loop can be configured to work. By default Discovery Loop will
* work as per NFC Forum Activity Specification v2.2. which will configure the Reader in both POLL and LISTEN
* (only for Universal device) modes of discovery loop.
* So, to enable EMVCO profile, configurability of Discovery loop should be ENABLED by enabling
* ENABLE_EMVCO_PROF macro.
*/
#ifdef ENABLE_DISC_CONFIG
// #define ENABLE_EMVCO_PROF
#endif /* ENABLE_DISC_CONFIG */
#ifdef PH_OSAL_FREERTOS
#ifdef PHOSAL_FREERTOS_STATIC_MEM_ALLOCATION
#define DISC_DEMO_TASK_STACK (1800/4)
#else /* PHOSAL_FREERTOS_STATIC_MEM_ALLOCATION */
#if defined( __PN74XXXX__) || defined(__PN76XX__)
#define DISC_DEMO_TASK_STACK (1600/4)
#else /* defined( __PN74XXXX__) || defined(__PN76XX__) */
#define DISC_DEMO_TASK_STACK (1650)
#endif /* defined( __PN74XXXX__) || defined(__PN76XX__) */
#endif /* PHOSAL_FREERTOS_STATIC_MEM_ALLOCATION */
#define DISC_DEMO_TASK_PRIO 4
#endif /* PH_OSAL_FREERTOS */
#ifdef PH_OSAL_LINUX
#define DISC_DEMO_TASK_STACK 0x20000
#define DISC_DEMO_TASK_PRIO 0
#endif /* PH_OSAL_LINUX */
#endif /* NFCRDLIBEX1_DISCOVERYLOOP_H */

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/*----------------------------------------------------------------------------*/
/* Copyright 2020 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may only */
/* be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that you */
/* have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*----------------------------------------------------------------------------*/
/** \file
* Example Header for NfcrdlibEx1_DiscoveryLoop to work with EMVCo Profile.
*
* $Author$
* $Revision$ (v07.10.00)
* $Date$
*/
#ifndef NFCRDLIBEX1_EMVCOPROFILE_H
#define NFCRDLIBEX1_EMVCOPROFILE_H
#include <ph_Status.h>
#include <phacDiscLoop.h>
void EmvcoProfileProcess (phacDiscLoop_Sw_DataParams_t * pDataParams, phStatus_t eDiscStatus);
#endif /* NFCRDLIBEX1_EMVCOPROFILE_H */

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/*----------------------------------------------------------------------------*/
/* Copyright 2016-2023 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may only */
/* be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that you */
/* have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*----------------------------------------------------------------------------*/
/** \file
* Example Source abstracting component header specific to HW used in the examples
* This file shall be present in all examples. A customer does not need to touch/modify this file. This file
* purely depends on the phNxpBuild_Lpc.h or phNxpBuild_App.h
* The phAppInit.h externs the component data structures initialized here that is in turn included by the core examples.
* The core example shall not use any other variable defined here except the RdLib component data structures(as explained above)
* The RdLib component initialization requires some user defined data and function pointers.
* These are defined in the respective examples and externed here.
*
* Keystore and Crypto initialization needs to be handled by application.
*
* $Author$
* $Revision$ (v07.10.00)
* $Date$
*
*/
#ifndef PHAPP_INIT_H
#define PHAPP_INIT_H
/* Status header */
#include <ph_Status.h>
/* Driver Header */
#include <phDriver.h>
/* NFCLIB Header */
#include <phNfcLib.h>
/* LLCP header */
#include <phlnLlcp.h>
/* SNEP header */
#include <phnpSnep.h>
/* Check for K82 controller based boards. */
#if defined(PHDRIVER_FRDM_K82FPN5180_BOARD) || \
defined(PHDRIVER_FRDM_K82FRC663_BOARD) || \
defined(PHDRIVER_K82F_PNEV5190B_BOARD)
#define PHDRIVER_KINETIS_K82
#endif
/* Check for LPC1769 controller based boards. */
#if defined(PHDRIVER_LPC1769PN5180_BOARD) || \
defined(PHDRIVER_LPC1769RC663_BOARD) || \
defined(PHDRIVER_LPC1769PN5190_BOARD)
#define PHDRIVER_LPC1769
#endif
#if defined(PHDRIVER_PIPN5180_BOARD) || \
defined(PHDRIVER_PIRC663_BOARD) || \
defined(PHDRIVER_PIPN5190_BOARD)
#include <phDriver_Linux_Int.h>
#endif
#ifdef PHDRIVER_KINETIS_K82
# include <fsl_debug_console.h>
# include <stdio.h>
#endif
#if !defined(__PN76XX__)
#ifdef DEBUG
#ifdef PHDRIVER_KINETIS_K82
#if SDK_DEBUGCONSOLE==1
#define DEBUG_PRINTF DbgConsole_Printf
#else
#define DEBUG_PRINTF(...) printf(__VA_ARGS__);
#endif
#else /* PHDRIVER_KINETIS_K82 */
#include <stdio.h>
#define DEBUG_PRINTF(...) printf(__VA_ARGS__); fflush(stdout)
#endif /* PHDRIVER_KINETIS_K82 */
#else /* DEBUG */
#define DEBUG_PRINTF(...)
#define DEBUG_SCANF(...)
#endif /* DEBUG */
#else /* __PN76XX__ */
#if (SEGGER_RTT_ENABLE == 1)
#include "SEGGER_RTT.h"
#define DEBUG_PRINTF(...) SEGGER_RTT_printf(0, __VA_ARGS__);
#define DEBUG_SCANF(Input , data) *data = (SEGGER_RTT_WaitKey() - 0x30); SEGGER_RTT_WaitKey()
#else
#if DEBUG
#include <fsl_debug_console.h>
#define DEBUG_PRINTF(...) PRINTF(__VA_ARGS__);
#define DEBUG_SCANF(...) SCANF(__VA_ARGS__);while ((GETCHAR()) != '\n');
#define DEBUG_GETCHAR GETCHAR
#else
#define DEBUG_PRINTF(...)
#define DEBUG_SCANF(...)
#endif /* DEBUG */
#endif /* (SEGGER_RTT_ENABLE == 1) */
#endif /* __PN76XX__ */
/*******************************************************************************
** Global Variable Declaration
*******************************************************************************/
#define PH_NFCRDLIB_EXAMPLE_LPCD_GUARDTIME 100 /* LPCD Guard time(T4) in milli-seconds configured by application for Rc663. */
#define PH_NFCRDLIB_EXAMPLE_LPCD_RFON_TIME 56 /* LPCD RFON time(T3) in micro-seconds configured by application for Rc663. */
/* HAL & BAL declarations */
#ifdef PH_PLATFORM_HAS_ICFRONTEND
extern phbalReg_Type_t sBalParams;
#endif /* PH_PLATFORM_HAS_ICFRONTEND */
#ifdef NXPBUILD__PHLN_LLCP_SW
extern phlnLlcp_Sw_DataParams_t slnLlcp; /* LLCP component */
#endif /* NXPBUILD__PHLN_LLCP_SW */
#ifdef NXPBUILD__PHHAL_HW_PN5180
extern phhalHw_Pn5180_DataParams_t * pHal;
#endif /* NXPBUILD__PHHAL_HW_PN5180 */
#ifdef NXPBUILD__PHHAL_HW_PN5190
extern phhalHw_Pn5190_DataParams_t * pHal;
#endif /* NXPBUILD__PHHAL_HW_PN5190 */
#ifdef NXPBUILD__PHHAL_HW_RC663
extern phhalHw_Rc663_DataParams_t * pHal;
#endif /* NXPBUILD__PHHAL_HW_RC663 */
#ifdef NXPBUILD__PHHAL_HW_PN7462AU
extern phhalHw_PN7462AU_DataParams_t * pHal;
#endif /* NXPBUILD__PHHAL_HW_PN7462AU */
#ifdef NXPBUILD__PHHAL_HW_PN76XX
extern phhalHw_Pn76xx_DataParams_t * pHal;
#endif /* NXPBUILD__PHHAL_HW_PN76XX */
/**************************************************Prints if error is detected**************************************************************/
/* Enable(1) / Disable(0) printing error/info */
#define DETECT_ERROR 0
#if DETECT_ERROR
#define DEBUG_ERROR_PRINT(x) x
#define PRINT_INFO(...) DEBUG_PRINTF(__VA_ARGS__)
#else
#define DEBUG_ERROR_PRINT(x)
#define PRINT_INFO(...)
#endif
#define CHECK_STATUS(x) \
if ((x) != PH_ERR_SUCCESS) \
{ \
DEBUG_PRINTF("Line: %d Error - (0x%04X) has occurred : 0xCCEE CC-Component ID, EE-Error code. Refer-ph_Status.h\n", __LINE__, (x)); \
}
/* prints if error is detected */
#define CHECK_SUCCESS(x) \
if ((x) != PH_ERR_SUCCESS) \
{ \
DEBUG_PRINTF("\nLine: %d Error - (0x%04X) has occurred : 0xCCEE CC-Component ID, EE-Error code. Refer-ph_Status.h\n ", __LINE__, (x)); \
return (x); \
}
/* prints if error is detected */
#define CHECK_NFCLIB_STATUS(x) \
if ((x) != PH_NFCLIB_STATUS_SUCCESS) \
{ \
DEBUG_PRINTF("\nLine: %d Error - (0x%04X) has occurred in NFCLIB\n ", __LINE__, (x)); \
}
/*********************************************************************************************************************************************/
/*******************************************************************************
** Function Declarations
*******************************************************************************/
extern void phApp_CPU_Init(void);
extern phStatus_t phApp_Comp_Init(void * pDiscLoopParams);
extern phStatus_t phApp_HALConfigAutoColl(void);
extern phStatus_t phApp_ConfigureLPCD(void);
extern void phApp_PrintTagInfo(phacDiscLoop_Sw_DataParams_t *pDataParams, uint16_t wNumberOfTags, uint16_t wTagsDetected);
extern void phApp_PrintTech(uint8_t TechType);
extern void phApp_Print_Buff(uint8_t *pBuff, uint8_t num);
extern void PrintErrorInfo(phStatus_t wStatus);
extern phStatus_t phApp_Configure_IRQ();
#ifdef PH_PLATFORM_HAS_ICFRONTEND
extern void CLIF_IRQHandler(void);
#endif /* PH_PLATFORM_HAS_ICFRONTEND */
#endif /* PHAPP_INIT_H */

View File

@ -0,0 +1,288 @@
/*----------------------------------------------------------------------------*/
/* Copyright 2016-2023 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may only */
/* be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that you */
/* have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*----------------------------------------------------------------------------*/
/** \file
* Application specific selection of Reader Library Components
*
* $Author$
* $Revision$ (v07.10.00)
* $Date$
*
*/
#ifndef PH_NXPBUILD_APP_H_INC
#define PH_NXPBUILD_APP_H_INC
/** \defgroup ph_NxpBuild NXP Build
* \brief Controls the Inclusion of required components, Inclusion SRC/DATA within components and the Build Dependencies between the components
* @{
*/
/* NXPBUILD_DELETE: included code lines should be always removed from code */
/* NXP BUILD DEFINES */
/* use #define to include components */
/* comment out #define to exclude components */
/* DEBUG build mode */
/*#define NXPBUILD__PH_DEBUG*/ /**< DEBUG build definition */
//#define NXPRDLIB_REM_GEN_INTFS
/*********************************************************************************************************************************************************************************/
#if defined(__PN74XXXX__) || defined (__PN73XXXX__)
#define NXPBUILD__PHHAL_HW_PN7462AU /**< NFC Controller PN7462AU HAL */
#endif
#ifdef __PN76XX__
#ifdef __PN7642__
#define NXPBUILD__PHHAL_HW_PN7642 /**< NFC Controller PN7642 HAL */
#elif __PN7640__
#define NXPBUILD__PHHAL_HW_PN7640 /**< NFC Controller PN7640 HAL */
#else
#error " PN76 platform definition (__PN7642__ or __PN7640__) missing !!! "
#endif
#if defined(__PN7642__) || defined(__PN7640__)
#define NXPBUILD__PHHAL_HW_PN76XX /**< NFC Controller PN76XX HAL */
#endif
#endif /* __PN76XX__ */
#if defined(PHDRIVER_LPC1769PN5180_BOARD) \
|| defined(PHDRIVER_FRDM_K82FPN5180_BOARD)
# define NXPBUILD__PHHAL_HW_PN5180
#endif
#if defined(PHDRIVER_LPC1769PN5190_BOARD) \
|| defined(PHDRIVER_K82F_PNEV5190B_BOARD)
# define NXPBUILD__PHHAL_HW_PN5190
#endif
#if defined(PHDRIVER_LPC1769RC663_BOARD) \
|| defined(PHDRIVER_FRDM_K82FRC663_BOARD)
# define NXPBUILD__PHHAL_HW_RC663
#endif
#if defined(NXPBUILD__PHHAL_HW_PN5180) || \
defined(NXPBUILD__PHHAL_HW_PN5190) || \
defined(NXPBUILD__PHHAL_HW_PN76XX) || \
defined(NXPBUILD__PHHAL_HW_PN7462AU)
#define NXPBUILD__PHHAL_HW_TARGET /**< Dependency checking if target mode macros should be enabled */
#endif
/*********************************************************************************************************************************************************************************/
#define NXPBUILD__PHPAL_I14443P3A_SW /**< PAL ISO 14443-3A SW Component is included. */
#define NXPBUILD__PHPAL_I14443P3B_SW /**< PAL ISO 14443-3B SW Component is included. */
#define NXPBUILD__PHPAL_I14443P4A_SW /**< PAL ISO 14443-4A SW Component is included. */
#define NXPBUILD__PHPAL_I14443P4_SW /**< PAL ISO 14443-4 SW Component is included. */
#define NXPBUILD__PHPAL_MIFARE_SW /**< PAL MIFARE SW Component is included */
//#define NXPBUILD__PHPAL_MIFARE_STUB /**< PAL MIFARE STUB Component is included */
#define NXPBUILD__PHPAL_FELICA_SW /**< PAL Felica SW Component is included. */
#define NXPBUILD__PHPAL_SLI15693_SW /**< PAL SLI 15693 Component is included. */
#ifndef NXPBUILD__PHHAL_HW_PN7640
#define NXPBUILD__PHPAL_I18000P3M3_SW /**< PAL ISO 18000p3m3 Component is included. */
#endif /* NXPBUILD__PHHAL_HW_PN7640 */
#ifdef NXPBUILD__PHHAL_HW_RC663 /**< If FE HAL is RC663, then include EPC UID PAL as required, otherwise exclude. */
#define NXPBUILD__PHPAL_EPCUID_SW /**< PAL EPC UID SW Component is included. */
#endif
#ifndef NXPBUILD__PHHAL_HW_PN76XX
#define NXPBUILD__PHPAL_I18092MPI_SW /**< PAL ISO18092 (P2P) SW Component is included. */
#endif /* NXPBUILD__PHHAL_HW_PN76XX */
#ifndef NXPBUILD__PHHAL_HW_RC663 /**< If FE HAL is RC663, then exclude ISO14443 Card Mode PAL & ISO18092 Target Mode PAL, otherwise include as required. */
// #define NXPBUILD__PHPAL_I14443P4MC_SW /**< PAL ISO 14443-4 Card Mode SW Component is included. */
// #define NXPBUILD__PHPAL_I18092MT_SW /**< PAL ISO 18092 Target Mode SW Component is included. */
#endif /* NXPBUILD__PHHAL_HW_RC663 */
/*********************************************************************************************************************************************************************************/
#define NXPBUILD__PHAC_DISCLOOP_SW /**< Discovery Loop Activity SW Component is included. */
#ifdef NXPBUILD__PHAC_DISCLOOP_SW /**< If DiscLoop SW Component is included, macros( & it's dependencies) to include/exclude SRC/DATA within Discloop is defined. */
#if defined (NXPBUILD__PHHAL_HW_PN5180) || \
defined (NXPBUILD__PHHAL_HW_PN5190) || \
defined (NXPBUILD__PHHAL_HW_RC663) || \
defined (NXPBUILD__PHHAL_HW_PN7462AU) || \
defined (NXPBUILD__PHHAL_HW_PN7642)
#define NXPBUILD__PHAC_DISCLOOP_LPCD /**< SRC to enable LPCD is included. */
#endif
#ifdef NXPBUILD__PHPAL_I14443P3A_SW
#define NXPBUILD__PHAC_DISCLOOP_TYPEA_I3P3_TAGS /**< SRC/DATA to Detect/CollRes/Activate cards such as MFC, MFUL, MFP SL1 etc is included. */
#define NXPBUILD__PHAC_DISCLOOP_TYPEA_JEWEL_TAGS /**< SRC/DATA to Detect cards such as NFC Forum T1T, Topaz/Jewel is included. */
#if defined(NXPBUILD__PHPAL_I14443P4A_SW) && defined(NXPBUILD__PHPAL_I14443P4_SW)
#define NXPBUILD__PHAC_DISCLOOP_TYPEA_I3P4_TAGS /**< SRC/DATA to Detect cards such as MFDF, MFP, T4AT NFC Forum Tag or Type A EMVCo is included. */
#endif
#endif /* NXPBUILD__PHPAL_I14443P3A_SW */
#if defined(NXPBUILD__PHPAL_I14443P3A_SW) && defined(NXPBUILD__PHPAL_I18092MPI_SW)
#define NXPBUILD__PHAC_DISCLOOP_TYPEA_P2P_TAGS /**< SRC/DATA to Detect Peer Passive Type A P2P Target mode devices is included. */
#endif
#ifndef NXPBUILD__PHHAL_HW_RC663
#ifdef NXPBUILD__PHPAL_I18092MPI_SW
#define NXPBUILD__PHAC_DISCLOOP_TYPEA_P2P_ACTIVE /**< SRC/DATA to Detect Peer Active Type A P2P Target mode devices is included. */
#define NXPBUILD__PHAC_DISCLOOP_TYPEF212_P2P_ACTIVE/**< SRC/DATA to Detect Peer Active Type F212 P2P Target mode devices is included. */
#define NXPBUILD__PHAC_DISCLOOP_TYPEF424_P2P_ACTIVE/**< SRC/DATA to Detect Peer Active Type F424 P2P Target mode devices is included. */
#endif /* NXPBUILD__PHPAL_I18092MPI_SW */
#endif /* NXPBUILD__PHHAL_HW_RC663 */
#ifdef NXPBUILD__PHPAL_FELICA_SW
#define NXPBUILD__PHAC_DISCLOOP_FELICA_TAGS /**< SRC/DATA to Detect FeliCa Cards is included. */
#ifdef NXPBUILD__PHPAL_I18092MPI_SW
#define NXPBUILD__PHAC_DISCLOOP_TYPEF_P2P_TAGS /**< SRC/DATA to Detect Peer Passive Type F P2P Target mode devices is included. */
#endif /* NXPBUILD__PHPAL_I18092MPI_SW */
#endif /* NXPBUILD__PHPAL_FELICA_SW */
#ifdef NXPBUILD__PHPAL_I14443P3B_SW
#define NXPBUILD__PHAC_DISCLOOP_TYPEB_I3P3B_TAGS /**< SRC/DATA to Detect Type B Cards that operate at Layer3 level is included */
#ifdef NXPBUILD__PHPAL_I14443P4_SW
#define NXPBUILD__PHAC_DISCLOOP_TYPEB_I3P4B_TAGS /**< SRC/DATA to Detect Type B Cards such as NFC Forum Type 4 Tags, EMVCo Type B Cards etc is included */
#endif /* NXPBUILD__PHPAL_I14443P4_SW */
#endif /* NXPBUILD__PHPAL_I14443P3B_SW */
#ifdef NXPBUILD__PHPAL_SLI15693_SW
#define NXPBUILD__PHAC_DISCLOOP_TYPEV_TAGS /**< SRC/DATA to Detect Type V Cards such as ICODE SLI/SLIX/SLI2/Tesa Cards is included*/
#endif /* NXPBUILD__PHPAL_SLI15693_SW */
#ifdef NXPBUILD__PHPAL_I18000P3M3_SW
#define NXPBUILD__PHAC_DISCLOOP_I18000P3M3_TAGS /**< SRC/DATA to Detect ICODE ILT Cards such as SMARTRAC StackIt Cards is included*/
#endif /* NXPBUILD__PHPAL_I18000P3M3_SW */
#ifndef NXPBUILD__PHHAL_HW_RC663 /**< If FE HAL is RC663, target mode is not supported at all, hence exclude those SRC, otherwise include as required */
#ifdef NXPBUILD__PHHAL_HW_TARGET
#define NXPBUILD__PHAC_DISCLOOP_TYPEA_TARGET_PASSIVE /**< SRC to Initialize Type A passive listen config and subsequently call HAL AutoColl is included. */
#ifndef NXPBUILD__PHHAL_HW_PN76XX
#define NXPBUILD__PHAC_DISCLOOP_TYPEA_TARGET_ACTIVE /**< SRC to Initialize Type A active listen config and subsequently call HAL AutoColl is included. */
#define NXPBUILD__PHAC_DISCLOOP_TYPEF212_TARGET_PASSIVE/**< SRC to Initialize Type F212 passive listen config and subsequently call HAL AutoColl is included. */
#define NXPBUILD__PHAC_DISCLOOP_TYPEF212_TARGET_ACTIVE /**< SRC to Initialize Type F212 active listen config and subsequently call HAL AutoColl is included. */
#define NXPBUILD__PHAC_DISCLOOP_TYPEF424_TARGET_PASSIVE/**< SRC to Initialize Type F424 passive listen config and subsequently call HAL AutoColl is included. */
#define NXPBUILD__PHAC_DISCLOOP_TYPEF424_TARGET_ACTIVE /**< SRC to Initialize Type F424 active listen config and subsequently call HAL AutoColl is included. */
#endif /* NXPBUILD__PHHAL_HW_PN76XX */
#endif /* NXPBUILD__PHHAL_HW_TARGET */
#endif
#endif /* NXPBUILD__PHAC_DISCLOOP_SW */
/*********************************************************************************************************************************************************************************/
#define NXPBUILD__PHNFCLIB /**< Simplified API Interface, If enabling this the entry point should be this component in the application */
/*********************************************************************************************************************************************************************************/
//#define NXPBUILD__PH_CIDMANAGER_SW /**< CID Manager SW Component is included. */
#define NXPBUILD__PH_KEYSTORE_SW /**< SW KeyStore Component is included. */
#if defined(NXPBUILD__PHHAL_HW_RC663) && !defined(NXPBUILD__PH_KEYSTORE_SW)
#define NXPBUILD__PH_KEYSTORE_RC663 /**< RC663 KeyStore Component is included. */
#endif
//#define NXPBUILD__PH_NDA_MFDF /**< MIFARE DESFire contactless IC */
#define NXPBUILD__PH_CRYPTOSYM_SW /**< Crypto Symbols SW Component is included. */
#define NXPBUILD__PH_CRYPTORNG_SW /**< Crypto RNG SW Component is included. */
/*********************************************************************************************************************************************************************************/
#ifdef NXPBUILD__PHPAL_FELICA_SW
#define NXPBUILD__PHAL_FELICA_SW /**< AL FeliCa SW Component is included */
#endif /* NXPBUILD__PHPAL_FELICA_SW */
#ifdef NXPBUILD__PHPAL_MIFARE_SW
#if defined(NXPBUILD__PH_KEYSTORE_SW) || defined(NXPBUILD__PH_KEYSTORE_RC663)
#define NXPBUILD__PHAL_MFC_SW /**< AL MIFARE Classic contactless IC SW Component is included */
#endif
#define NXPBUILD__PHAL_MFUL_SW /**< AL Mifare Ultrlight SW Component is included */
#define NXPBUILD__PHAL_MFDF_SW /**< AL Mifare DesFire SW Component is included */
//#define NXPBUILD__PHAL_MFNTAG42XDNA_SW /**< AL MIFARE Prime Ntag42XDna contactless IC SW Component is included */
#endif /* NXPBUILD__PHPAL_MIFARE_SW */
#define NXPBUILD__PHAL_T1T_SW /**< AL Type T1 Tag SW Component is included */
#ifdef NXPBUILD__PHPAL_SLI15693_SW
#define NXPBUILD__PHAL_ICODE_SW /**< AL ICODE SW COMPONENT is included */
#endif /* NXPBUILD__PHPAL_SLI15693_SW */
#ifdef NXPBUILD__PHAL_T1T_SW
#define NXPBUILD__PHAL_TOP_T1T_SW /**< AL TOP T1T Tag SW Component is included */
#endif /* NXPBUILD__PHAL_T1T_SW */
#ifdef NXPBUILD__PHAL_MFUL_SW
#define NXPBUILD__PHAL_TOP_T2T_SW /**< AL TOP T2T Tag SW Component is included */
#endif /* NXPBUILD__PHAL_MFUL_SW*/
#ifdef NXPBUILD__PHAL_FELICA_SW
#define NXPBUILD__PHAL_TOP_T3T_SW /**< AL TOP T3T Tag SW Component is included */
#endif /* NXPBUILD__PHAL_FELICA_SW*/
#ifdef NXPBUILD__PHPAL_MIFARE_SW
#define NXPBUILD__PHAL_TOP_T4T_SW /**< AL TOP T4T Tag SW Component is included */
#endif /* NXPBUILD__PHPAL_MIFARE_SW*/
#ifdef NXPBUILD__PHAL_ICODE_SW
#define NXPBUILD__PHAL_TOP_T5T_SW /**< AL TOP T5T Tag SW Component is included */
#endif /* NXPBUILD__PHAL_ICODE_SW*/
#ifdef NXPBUILD__PHPAL_I14443P3A_SW
#define NXPBUILD__PHAL_TOP_MFC_SW /**< AL TOP MFC Tag SW Component is included */
#endif /* NXPBUILD__PHPAL_I14443P3A_SW*/
#if defined(NXPBUILD__PHAL_TOP_T1T_SW) || \
defined(NXPBUILD__PHAL_TOP_T2T_SW) || \
defined(NXPBUILD__PHAL_TOP_T3T_SW) || \
defined(NXPBUILD__PHAL_TOP_T4T_SW) || \
defined(NXPBUILD__PHAL_TOP_T5T_SW) || \
defined(NXPBUILD__PHAL_TOP_MFC_SW)
#define NXPBUILD__PHAL_TOP_SW /**< AL for TagOps Mapping SW Component is included.Required for NDEF operations */
#endif
#ifdef NXPBUILD__PHPAL_I18000P3M3_SW
#define NXPBUILD__PHAL_I18000P3M3_SW /**< AL ISO18000p3m3 SW Component is included */
#endif /* NXPBUILD__PHPAL_I18000P3M3_SW */
#ifdef NXPBUILD__PHPAL_I14443P4MC_SW
#if !defined(PH_OSAL_NULLOS)
#define NXPBUILD__PHCE_T4T_SW /**< AL HCE T2AT SW Component is included */
//#define NXPBUILD__PHCE_T4T_PROPRIETARY /**< SRC to handle HCE T4AT Proprietary Commands is included */
/*#define NXPBUILD__PHCE_T4T_EXT_NDEF */ /**< SRC to handle Extended NDEF Support as per T4T spec 3.0 is included */
#endif
#endif /* NXPBUILD__PHPAL_I14443P4MC_SW */
/* LLCP Components */
#if defined(NXPBUILD__PHPAL_I18092MPI_SW) || defined(NXPBUILD__PHPAL_I18092MT_SW)
#if !defined(PH_OSAL_NULLOS)
// #define NXPBUILD__PHLN_LLCP_SW /**< Link LLCP SW Component is included */
#endif
#endif
/* SNEP components */
#ifdef NXPBUILD__PHLN_LLCP_SW
#define NXPBUILD__PHNP_SNEP_SW /**< Protocol SNEP SW Component is included */
#endif /* NXPBUILD__PHLN_LLCP_SW */
/* Enable/disable Debugging */
/*#define NXPBUILD__PH_DEBUG*/ /**< TODO: To be checked if required */
/** @}
* end of ph_NxpBuild
*/
#endif /* PH_NXPBUILD_APP_H_INC */

View File

@ -0,0 +1,342 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?><?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
<storageModule moduleId="org.eclipse.cdt.core.settings">
<cconfiguration id="com.crt.advproject.config.exe.debug.738429693">
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.crt.advproject.config.exe.debug.738429693" moduleId="org.eclipse.cdt.core.settings" name="DebugLPC1769">
<externalSettings />
<extensions>
<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser" />
<extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser" />
<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser" />
<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser" />
<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser" />
<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser" />
<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser" />
</extensions>
</storageModule>
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
<configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="rm -rf" description="Debug build for LPC1769" errorParsers="org.eclipse.cdt.core.CWDLocator;org.eclipse.cdt.core.GmakeErrorParser;org.eclipse.cdt.core.GCCErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.GASErrorParser" id="com.crt.advproject.config.exe.debug.738429693" name="DebugLPC1769" parent="com.crt.advproject.config.exe.debug" postannouncebuildStep="Performing post-build steps" postbuildStep="arm-none-eabi-size &quot;${BuildArtifactFileName}&quot; ; arm-none-eabi-objcopy -O binary &quot;${BuildArtifactFileName}&quot; &quot;${BuildArtifactFileBaseName}.bin&quot; ; #checksum -p ${TargetChip} -d &quot;${BuildArtifactFileBaseName}.bin&quot;" preannouncebuildStep="" prebuildStep="">
<folderInfo id="com.crt.advproject.config.exe.debug.738429693." name="/" resourcePath="">
<toolChain errorParsers="" id="com.crt.advproject.toolchain.exe.debug.1486081712" name="Code Red MCU Tools" superClass="com.crt.advproject.toolchain.exe.debug">
<targetPlatform binaryParser="org.eclipse.cdt.core.ELF;org.eclipse.cdt.core.GNU_ELF" id="com.crt.advproject.platform.exe.debug.1843864105" name="ARM-based MCU (Debug)" superClass="com.crt.advproject.platform.exe.debug" />
<builder autoBuildTarget="all" buildPath="${workspace_loc:/NfcrdlibEx1_DiscoveryLoop_mcux}/DebugLPC1769" cleanBuildTarget="clean" enableAutoBuild="false" enableCleanBuild="false" enabledIncrementalBuild="true" errorParsers="org.eclipse.cdt.core.GmakeErrorParser;org.eclipse.cdt.core.CWDLocator" id="com.crt.advproject.builder.exe.debug.1999230655" incrementalBuildTarget="all" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="4" stopOnErr="true" superClass="com.crt.advproject.builder.exe.debug" />
<tool id="com.crt.advproject.cpp.exe.debug.1675794760" name="MCU C++ Compiler" superClass="com.crt.advproject.cpp.exe.debug">
<option id="com.crt.advproject.cpp.hdrlib.891527009" name="Library headers" superClass="com.crt.advproject.cpp.hdrlib" useByScannerDiscovery="false" />
<option id="gnu.cpp.compiler.option.preprocessor.def.153629260" name="Defined symbols (-D)" superClass="gnu.cpp.compiler.option.preprocessor.def" useByScannerDiscovery="false" />
<option id="com.crt.advproject.cpp.fpu.1740448131" name="Floating point" superClass="com.crt.advproject.cpp.fpu" useByScannerDiscovery="false" />
</tool>
<tool command="arm-none-eabi-gcc" commandLinePattern="${COMMAND} ${FLAGS} ${OUTPUT_FLAG} ${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" errorParsers="org.eclipse.cdt.core.GCCErrorParser" id="com.crt.advproject.gcc.exe.debug.441056261" name="MCU C Compiler" superClass="com.crt.advproject.gcc.exe.debug">
<option id="com.crt.advproject.gcc.arch.2038529659" name="Architecture" superClass="com.crt.advproject.gcc.arch" useByScannerDiscovery="false" value="com.crt.advproject.gcc.target.cm3" valueType="enumerated" />
<option id="com.crt.advproject.gcc.thumb.1879215782" name="Thumb mode" superClass="com.crt.advproject.gcc.thumb" useByScannerDiscovery="false" value="true" valueType="boolean" />
<option id="com.crt.advproject.gcc.hdrlib.1573272634" name="Library headers" superClass="com.crt.advproject.gcc.hdrlib" useByScannerDiscovery="false" />
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="gnu.c.compiler.option.preprocessor.def.symbols.1031812916" name="Defined symbols (-D)" superClass="gnu.c.compiler.option.preprocessor.def.symbols" useByScannerDiscovery="false" valueType="definedSymbols">
<listOptionValue builtIn="false" value="__USE_LPCOPEN" />
<listOptionValue builtIn="false" value="PH_OSAL_FREERTOS" />
<listOptionValue builtIn="false" value="PHDRIVER_LPC1769PN5180_BOARD" />
<listOptionValue builtIn="false" value="CORE_M3" />
<listOptionValue builtIn="false" value="__REDLIB__" />
<listOptionValue builtIn="false" value="DEBUG" />
<listOptionValue builtIn="false" value="__CODE_RED" />
<listOptionValue builtIn="false" value="NXPBUILD_CUSTOMER_HEADER_INCLUDED" />
</option>
<option id="gnu.c.compiler.option.misc.other.1808498294" name="Other flags" superClass="gnu.c.compiler.option.misc.other" useByScannerDiscovery="false" value="-c -fmessage-length=0 -fno-builtin -ffunction-sections -fdata-sections -Wno-unknown-pragmas -Wno-strict-aliasing" valueType="string" />
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<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/DAL/boards}&quot;" />
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/DAL/cfg}&quot;" />
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/DAL/inc}&quot;" />
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/DAL/src/LPCOpen}&quot;" />
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/lpc_board_nxp_lpcxpresso_1769/inc}&quot;" />
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/lpc_chip_175x_6x/inc}&quot;" />
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View File

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<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>NfcrdlibEx1_DiscoveryLoop_mcux</name>
<comment></comment>
<projects>
<project>FreeRTOS</project>
<project>lpc_board_nxp_lpcxpresso_1769</project>
<project>lpc_chip_175x_6x</project>
<project>NxpNfcRdLib</project>
<project>SDK_2.x_FRDM-K82F</project>
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</link>
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View File

@ -0,0 +1,493 @@
//*****************************************************************************
// LPC175x_6x Microcontroller Startup code for use with LPCXpresso IDE
//
// Version : 140114
//*****************************************************************************
//
// Copyright(C) NXP Semiconductors, 2014
// All rights reserved.
//
// Software that is described herein is for illustrative purposes only
// which provides customers with programming information regarding the
// LPC products. This software is supplied "AS IS" without any warranties of
// any kind, and NXP Semiconductors and its licensor disclaim any and
// all warranties, express or implied, including all implied warranties of
// merchantability, fitness for a particular purpose and non-infringement of
// intellectual property rights. NXP Semiconductors assumes no responsibility
// or liability for the use of the software, conveys no license or rights under any
// patent, copyright, mask work right, or any other intellectual property rights in
// or to any products. NXP Semiconductors reserves the right to make changes
// in the software without notification. NXP Semiconductors also makes no
// representation or warranty that such application will be suitable for the
// specified use without further testing or modification.
//
// Permission to use, copy, modify, and distribute this software and its
// documentation is hereby granted, under NXP Semiconductors' and its
// licensor's relevant copyrights in the software, without fee, provided that it
// is used in conjunction with NXP Semiconductors microcontrollers. This
// copyright, permission, and disclaimer notice must appear in all copies of
// this code.
//*****************************************************************************
#include <ph_Status.h>
#include <cr_section_macros.h>
#include <NXP/crp.h>
#ifdef DEBUG
# define VT_IMAGE_LENGTH 0x76706b64U
#else /* DEBUG */
# define VT_IMAGE_LENGTH 0xFFFFFFFFU
#endif /* DEBUG */
#if defined (__cplusplus)
#ifdef __REDLIB__
#error Redlib does not support C++
#else
//*****************************************************************************
//
// The entry point for the C++ library startup
//
//*****************************************************************************
extern "C" {
extern void __libc_init_array(void);
}
#endif
#endif
#define WEAK __attribute__ ((weak))
#define ALIAS(f) __attribute__ ((weak, alias (#f)))
__CRP const unsigned int CRP_WORD = CRP_NO_CRP;
//*****************************************************************************
#if defined (__cplusplus)
extern "C" {
#endif
//*****************************************************************************
#if defined (__USE_CMSIS) || defined (__USE_LPCOPEN)
// Declaration of external SystemInit function
void SystemInit(void);
extern void Board_SystemInit(void);
extern void Chip_SystemInit(void);
extern void SystemCoreClockUpdate(void);
#endif
//*****************************************************************************
//
// Forward declaration of the default handlers. These are aliased.
// When the application defines a handler (with the same name), this will
// automatically take precedence over these weak definitions
//
//*****************************************************************************
void ResetISR(void);
WEAK void NMI_Handler(void);
//WEAK void HardFault_Handler(void);
WEAK void MemManage_Handler(void);
WEAK void BusFault_Handler(void);
WEAK void UsageFault_Handler(void);
WEAK void SVC_Handler(void);
WEAK void DebugMon_Handler(void);
WEAK void PendSV_Handler(void);
WEAK void SysTick_Handler(void);
WEAK void IntDefaultHandler(void);
/* The prototype shows it is a naked function - in effect this is just an
assembly function. */
void HardFault_Handler( void ) __attribute__( ( naked ) );
//*****************************************************************************
//
// Forward declaration of the specific IRQ handlers. These are aliased
// to the IntDefaultHandler, which is a 'forever' loop. When the application
// defines a handler (with the same name), this will automatically take
// precedence over these weak definitions
//
//*****************************************************************************
void WDT_IRQHandler(void) ALIAS(IntDefaultHandler);
void TIMER0_IRQHandler(void) ALIAS(IntDefaultHandler);
void TIMER1_IRQHandler(void) ALIAS(IntDefaultHandler);
void TIMER2_IRQHandler(void) ALIAS(IntDefaultHandler);
void TIMER3_IRQHandler(void) ALIAS(IntDefaultHandler);
void UART0_IRQHandler(void) ALIAS(IntDefaultHandler);
void UART1_IRQHandler(void) ALIAS(IntDefaultHandler);
void UART2_IRQHandler(void) ALIAS(IntDefaultHandler);
void UART3_IRQHandler(void) ALIAS(IntDefaultHandler);
void PWM1_IRQHandler(void) ALIAS(IntDefaultHandler);
void I2C0_IRQHandler(void) ALIAS(IntDefaultHandler);
void I2C1_IRQHandler(void) ALIAS(IntDefaultHandler);
void I2C2_IRQHandler(void) ALIAS(IntDefaultHandler);
void SPI_IRQHandler(void) ALIAS(IntDefaultHandler);
void SSP0_IRQHandler(void) ALIAS(IntDefaultHandler);
void SSP1_IRQHandler(void) ALIAS(IntDefaultHandler);
void PLL0_IRQHandler(void) ALIAS(IntDefaultHandler);
void RTC_IRQHandler(void) ALIAS(IntDefaultHandler);
void EINT0_IRQHandler(void) ALIAS(IntDefaultHandler);
void EINT1_IRQHandler(void) ALIAS(IntDefaultHandler);
void EINT2_IRQHandler(void) ALIAS(IntDefaultHandler);
void CLIF_IRQHandler(void) ALIAS(IntDefaultHandler);
void ADC_IRQHandler(void) ALIAS(IntDefaultHandler);
void BOD_IRQHandler(void) ALIAS(IntDefaultHandler);
void USB_IRQHandler(void) ALIAS(IntDefaultHandler);
void CAN_IRQHandler(void) ALIAS(IntDefaultHandler);
void DMA_IRQHandler(void) ALIAS(IntDefaultHandler);
void I2S_IRQHandler(void) ALIAS(IntDefaultHandler);
#if defined (__USE_LPCOPEN)
void ETH_IRQHandler(void) ALIAS(IntDefaultHandler);
#else
void ENET_IRQHandler(void) ALIAS(IntDefaultHandler);
#endif
void RIT_IRQHandler(void) ALIAS(IntDefaultHandler);
void MCPWM_IRQHandler(void) ALIAS(IntDefaultHandler);
void QEI_IRQHandler(void) ALIAS(IntDefaultHandler);
void PLL1_IRQHandler(void) ALIAS(IntDefaultHandler);
void USBActivity_IRQHandler(void) ALIAS(IntDefaultHandler);
void CANActivity_IRQHandler(void) ALIAS(IntDefaultHandler);
void UART4_IRQHandler(void) ALIAS(IntDefaultHandler);
void SSP2_IRQHandler(void) ALIAS(IntDefaultHandler);
void LCD_IRQHandler(void) ALIAS(IntDefaultHandler);
void GPIO_IRQHandler(void) ALIAS(IntDefaultHandler);
void PWM0_IRQHandler(void) ALIAS(IntDefaultHandler);
void EEPROM_IRQHandler(void) ALIAS(IntDefaultHandler);
//*****************************************************************************
//
// The entry point for the application.
// __main() is the entry point for Redlib based applications
// main() is the entry point for Newlib based applications
//
//*****************************************************************************
#if defined (__REDLIB__)
extern void __main(void);
#endif
extern int main(void);
//*****************************************************************************
//
// External declaration for the pointer to the stack top from the Linker Script
//
//*****************************************************************************
extern void _vStackTop(void);
//*****************************************************************************
#if defined (__cplusplus)
} // extern "C"
#endif
//*****************************************************************************
//
// The vector table.
// This relies on the linker script to place at correct location in memory.
//
//*****************************************************************************
extern void (* const g_pfnVectors[])(void);
__attribute__ ((section(".isr_vector")))
void (* const g_pfnVectors[])(void) = {
// Core Level - CM3
&_vStackTop, // The initial stack pointer
ResetISR, // The reset handler
NMI_Handler, // The NMI handler
HardFault_Handler, // The hard fault handler
MemManage_Handler, // The MPU fault handler
BusFault_Handler, // The bus fault handler
UsageFault_Handler, // The usage fault handler
0, // Reserved
0, // Reserved
0, // Reserved
0, // Reserved
SVC_Handler, // SVCall handler
DebugMon_Handler, // Debug monitor handler
0, // Reserved
PendSV_Handler, // The PendSV handler
SysTick_Handler, // The SysTick handler
// Chip Level - LPC17
WDT_IRQHandler, // 16, 0x40 - WDT
TIMER0_IRQHandler, // 17, 0x44 - TIMER0
TIMER1_IRQHandler, // 18, 0x48 - TIMER1
TIMER2_IRQHandler, // 19, 0x4c - TIMER2
TIMER3_IRQHandler, // 20, 0x50 - TIMER3
UART0_IRQHandler, // 21, 0x54 - UART0
UART1_IRQHandler, // 22, 0x58 - UART1
UART2_IRQHandler, // 23, 0x5c - UART2
UART3_IRQHandler, // 24, 0x60 - UART3
PWM1_IRQHandler, // 25, 0x64 - PWM1
I2C0_IRQHandler, // 26, 0x68 - I2C0
I2C1_IRQHandler, // 27, 0x6c - I2C1
I2C2_IRQHandler, // 28, 0x70 - I2C2
SPI_IRQHandler, // 29, 0x74 - SPI
SSP0_IRQHandler, // 30, 0x78 - SSP0
SSP1_IRQHandler, // 31, 0x7c - SSP1
PLL0_IRQHandler, // 32, 0x80 - PLL0 (Main PLL)
RTC_IRQHandler, // 33, 0x84 - RTC
EINT0_IRQHandler, // 34, 0x88 - EINT0
EINT1_IRQHandler, // 35, 0x8c - EINT1
EINT2_IRQHandler, // 36, 0x90 - EINT2
CLIF_IRQHandler, // 37, 0x94 - EINT3 (Used for CLIF IRQ)
ADC_IRQHandler, // 38, 0x98 - ADC
BOD_IRQHandler, // 39, 0x9c - BOD
USB_IRQHandler, // 40, 0xA0 - USB
CAN_IRQHandler, // 41, 0xa4 - CAN
DMA_IRQHandler, // 42, 0xa8 - GP DMA
I2S_IRQHandler, // 43, 0xac - I2S
#if defined (__USE_LPCOPEN)
ETH_IRQHandler, // 44, 0xb0 - Ethernet
#else
ENET_IRQHandler, // 44, 0xb0 - Ethernet
#endif
RIT_IRQHandler, // 45, 0xb4 - RITINT
MCPWM_IRQHandler, // 46, 0xb8 - Motor Control PWM
QEI_IRQHandler, // 47, 0xbc - Quadrature Encoder
PLL1_IRQHandler, // 48, 0xc0 - PLL1 (USB PLL)
USBActivity_IRQHandler, // 49, 0xc4 - USB Activity interrupt to wakeup
CANActivity_IRQHandler, // 50, 0xc8 - CAN Activity interrupt to wakeup
UART4_IRQHandler, //; 51 UART4
SSP2_IRQHandler, //; 52 SSP2
LCD_IRQHandler, //; 53 LCD
GPIO_IRQHandler, //; 54 GPIO
PWM0_IRQHandler , //; 55 PWM0
EEPROM_IRQHandler, //; 56 EEPROM
(void *)VT_IMAGE_LENGTH, //; 57 VT Checksum for CRC Check of Vector Table.
};
//*****************************************************************************
// Functions to carry out the initialization of RW and BSS data sections. These
// are written as separate functions rather than being inlined within the
// ResetISR() function in order to cope with MCUs with multiple banks of
// memory.
//*****************************************************************************
__attribute__ ((section(".after_vectors")))
void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
unsigned int *pulDest = (unsigned int*) start;
unsigned int *pulSrc = (unsigned int*) romstart;
unsigned int loop;
for (loop = 0; loop < len; loop = loop + 4)
*pulDest++ = *pulSrc++;
}
__attribute__ ((section(".after_vectors")))
void bss_init(unsigned int start, unsigned int len) {
unsigned int *pulDest = (unsigned int*) start;
unsigned int loop;
for (loop = 0; loop < len; loop = loop + 4)
*pulDest++ = 0;
}
//*****************************************************************************
// The following symbols are constructs generated by the linker, indicating
// the location of various points in the "Global Section Table". This table is
// created by the linker via the Code Red managed linker script mechanism. It
// contains the load address, execution address and length of each RW data
// section and the execution and length of each BSS (zero initialized) section.
//*****************************************************************************
extern unsigned int __data_section_table;
extern unsigned int __data_section_table_end;
extern unsigned int __bss_section_table;
extern unsigned int __bss_section_table_end;
//*****************************************************************************
// Reset entry point for your code.
// Sets up a simple runtime environment and initializes the C/C++
// library.
//*****************************************************************************
__attribute__ ((section(".after_vectors")))
void
ResetISR(void) {
//
// Copy the data sections from flash to SRAM.
//
unsigned int LoadAddr, ExeAddr, SectionLen;
unsigned int *SectionTableAddr;
// Load base address of Global Section Table
SectionTableAddr = &__data_section_table;
// Copy the data sections from flash to SRAM.
while (SectionTableAddr < &__data_section_table_end) {
LoadAddr = *SectionTableAddr++;
ExeAddr = *SectionTableAddr++;
SectionLen = *SectionTableAddr++;
data_init(LoadAddr, ExeAddr, SectionLen);
}
// At this point, SectionTableAddr = &__bss_section_table;
// Zero fill the bss segment
while (SectionTableAddr < &__bss_section_table_end) {
ExeAddr = *SectionTableAddr++;
SectionLen = *SectionTableAddr++;
bss_init(ExeAddr, SectionLen);
}
#if defined (__USE_CMSIS) || defined (__USE_LPCOPEN)
SystemInit();
#endif
#if defined (__cplusplus)
//
// Call C++ library initialisation
//
__libc_init_array();
#endif
#if defined (__REDLIB__)
// Call the Redlib library, which in turn calls main()
__main() ;
#else
main();
#endif
//
// main() shouldn't return, but if it does, we'll just enter an infinite loop
//
while (1) {
;
}
}
/* Set up and initialize hardware prior to call to main */
void SystemInit(void)
{
unsigned int *pSCB_VTOR = (unsigned int *) 0xE000ED08;
#if defined(__IAR_SYSTEMS_ICC__)
extern void *__vector_table;
*pSCB_VTOR = (unsigned int) &__vector_table;
#elif defined(__CODE_RED)
*pSCB_VTOR = (unsigned int) &g_pfnVectors;
#elif defined(__ARMCC_VERSION)
extern void *__Vectors;
*pSCB_VTOR = (unsigned int) &__Vectors;
#endif
#if defined(__FPU_PRESENT) && __FPU_PRESENT == 1
fpuInit();
#endif
#if defined(NO_BOARD_LIB)
/* Chip specific SystemInit */
Chip_SystemInit();
#else
/* Setup system clocking and muxing */
Board_SystemInit();
#endif
/* Update system core clock rate. */
SystemCoreClockUpdate();
}
//*****************************************************************************
// Default exception handlers. Override the ones here by defining your own
// handler routines in your application code.
//*****************************************************************************
__attribute__ ((section(".after_vectors")))
void NMI_Handler(void)
{ while(1) {}
}
/* The fault handler implementation calls a function called
prvGetRegistersFromStack(). */
__attribute__ ((section(".after_vectors")))
void HardFault_Handler(void)
{
/* Use assembly to pick up date, but feed to C Code. */
__asm( ".syntax divided\n"
"MOVS R0, #4 \n"
"MOV R1, LR \n"
"TST R0, R1 \n"
"BEQ _MSP \n"
"MRS R0, PSP \n"
"B HardFault_HandlerC \n"
"_MSP: \n"
"MRS R0, MSP \n"
"B HardFault_HandlerC \n"
".syntax divided\n") ;
__asm(".syntax unified");
}
__attribute__ ((section(".after_vectors")))
void HardFault_HandlerC(
unsigned long *args)
{
volatile unsigned long cm_r0;
volatile unsigned long cm_r1;
volatile unsigned long cm_r2;
volatile unsigned long cm_r3;
volatile unsigned long cm_r12;
volatile unsigned long cm_lr;
volatile unsigned long cm_pc;
volatile unsigned long cm_psr;
//if (((uint32_t) args < PH_RAM_MEM_END)&& ( (uint32_t)args > PH_RAM_MEM_START))
//0x10000000 -- 0x8000
//0x2007c000 -- 0x8000
{
cm_r0 = ((unsigned long)args[0]);
cm_r1 = ((unsigned long)args[1]);
cm_r2 = ((unsigned long)args[2]);
cm_r3 = ((unsigned long)args[3]);
cm_r12 = ((unsigned long)args[4]);
cm_lr = ((unsigned long)args[5]);
cm_pc = ((unsigned long)args[6]);
cm_psr = ((unsigned long)args[7]);
PH_UNUSED_VARIABLE(cm_r0);
PH_UNUSED_VARIABLE(cm_r1);
PH_UNUSED_VARIABLE(cm_r2);
PH_UNUSED_VARIABLE(cm_r3);
PH_UNUSED_VARIABLE(cm_r12);
PH_UNUSED_VARIABLE(cm_lr);
PH_UNUSED_VARIABLE(cm_pc);
PH_UNUSED_VARIABLE(cm_psr);
}
/* Break into the debugger */
__asm("BKPT #0\n");
while (1)
{
__asm("wfi\n");
}
}
__attribute__ ((section(".after_vectors")))
void MemManage_Handler(void)
{ while(1) {}
}
__attribute__ ((section(".after_vectors")))
void BusFault_Handler(void)
{ while(1) {}
}
__attribute__ ((section(".after_vectors")))
void UsageFault_Handler(void)
{ while(1) {}
}
__attribute__ ((section(".after_vectors")))
void SVC_Handler(void)
{ while(1) {}
}
__attribute__ ((section(".after_vectors")))
void DebugMon_Handler(void)
{ while(1) {}
}
__attribute__ ((section(".after_vectors")))
void PendSV_Handler(void)
{ while(1) {}
}
//*****************************************************************************
//
// Processor ends up here if an unexpected interrupt occurs or a specific
// handler is not present in the application code.
//
//*****************************************************************************
__attribute__ ((section(".after_vectors")))
void IntDefaultHandler(void)
{ while(1) {}
}

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/*----------------------------------------------------------------------------*/
/* Copyright 2020 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may only */
/* be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that you */
/* have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*----------------------------------------------------------------------------*/
/** \file
* Example Source for NfcrdlibEx1_EmvcoProfile.c that uses the Discovery loop implementation.
* Uses EMVCo POLL mode of discovery loop. Once a EMVCo Tag is been activated selected SELECT PPSE Exchange
* will be perform and print the Response of the same.
* This example will load/configure Discovery loop with user values based on EMVCo Profile via SetConfig.
*
* $Author$
* $Revision$ (v07.10.00)
* $Date$
*/
#include <phApp_Init.h>
#include <NfcrdlibEx1_DiscoveryLoop.h>
#include <NfcrdlibEx1_EmvcoProfile.h>
#ifdef ENABLE_EMVCO_PROF
/*******************************************************************************
** Static Defines
*******************************************************************************/
#define PRETTY_PRINTING /**< Enable pretty printing */
#define MiN_VALID_DATA_SIZE 6
#define PHAC_EMVCO_MAX_BUFFSIZE 600 /**< Maximum buffer size for Emvco. */
//#define RUN_TEST_SUIT
typedef enum{
eEmdRes_EOT = 0x70,
eEmdRes_SW_0 = 0x90,
eEmdRes_SW_1 = 0x00,
}eEmvcoRespByte;
#ifdef RUN_TEST_SUIT
/* EMVCo: Select PPSE Command */
static uint8_t PPSE_SELECT_APDU[] = { 0x00, 0xA4, 0x04, 0x00, 0x0E, 0x32, 0x50, 0x41, 0x59,
0x2E, 0x53, 0x59, 0x53, 0x2E, 0x44, 0x44, 0x46, 0x30, 0x31, 0x00 };
#else
uint8_t PPSE_response_buffer[256];
uint8_t PPSE_respsize;
/*Define Macro for the PPSE command with different P2 value in PPSE command*/
#define PPSE_FCI
//#define PPSE_FMD
//#define PPSE_FCP
//#define PPSE_NO_LE
/* CLA = 0x00
* INS = 0xA4
* P1 = 0x04
* P2 = 0x00
* LC = 0x0E,
* DF = 0x32, 0x50, 0x41, 0x59, 0x2E, 0x53, 0x59, 0x53, 0x2E, 0x44, 0x44, 0x46, 0x30, 0x31
* LE = 0x00
*/
/*P2 parameter values of
* 000000xxb = Return FCI template, optional use of FCI tag and length ,
* 000001xxb = Return FCP template, mandatory use of FCP tag and length,
* 000010xxb = Return FMD template, mandatory use of FMD tag and length,
* 000011xxb = No response data if Le field absent, or proprietary if Le field present
* */
#ifdef PPSE_FCI
/* EMVCo: Select PPSE Command */
static uint8_t PPSE_SELECT_APDU[] = { 0x00, 0xA4, 0x04, 0x00, 0x0E, 0x32, 0x50, 0x41, 0x59,
0x2E, 0x53, 0x59, 0x53, 0x2E, 0x44, 0x44, 0x46, 0x30, 0x31, 0x00 };
#endif
#ifdef PPSE_FCP
/* EMVCo: Select PPSE Command */
static uint8_t PPSE_SELECT_APDU[] = { 0x00, 0xA4, 0x04, 0x04, 0x0E, 0x32, 0x50, 0x41, 0x59,
0x2E, 0x53, 0x59, 0x53, 0x2E, 0x44, 0x44, 0x46, 0x30, 0x31, 0x00 };
#endif
#ifdef PPSE_FMD
/* EMVCo: Select PPSE Command */
static uint8_t PPSE_SELECT_APDU[] = { 0x00, 0xA4, 0x04, 0x08, 0x0E, 0x32, 0x50, 0x41, 0x59,
0x2E, 0x53, 0x59, 0x53, 0x2E, 0x44, 0x44, 0x46, 0x30, 0x31, 0x00 };
#endif
#ifdef PPSE_NO_LE
/* EMVCo: Select PPSE Command */
static uint8_t PPSE_SELECT_APDU[] = { 0x00, 0xA4, 0x04, 0x0C, 0x0E, 0x32, 0x50, 0x41, 0x59,
0x2E, 0x53, 0x59, 0x53, 0x2E, 0x44, 0x44, 0x46, 0x30, 0x31 };
#endif
#endif
uint8_t command_buffer[PHAC_EMVCO_MAX_BUFFSIZE];
uint8_t *response_buffer;
static phStatus_t EmvcoDataExchange(uint8_t * com_buffer, uint8_t cmdsize, uint8_t ** resp_buffer, uint32_t * wRxLength);
static void EmvcoRfReset(phacDiscLoop_Sw_DataParams_t * pDataParams);
static phStatus_t EmvcoDataLoopBack(phacDiscLoop_Sw_DataParams_t * pDataParams);
void EmvcoProfileProcess (phacDiscLoop_Sw_DataParams_t * pDataParams,phStatus_t eDiscStatus)
{
phStatus_t status = eDiscStatus;
if((status & PH_ERR_MASK) == PHAC_DISCLOOP_DEVICE_ACTIVATED)
{
status = EmvcoDataLoopBack(pDataParams);
}
if((status & PH_ERR_MASK) != PHAC_DISCLOOP_NO_TECH_DETECTED)
{
/* Perform RF Reset */
EmvcoRfReset(pDataParams);
}
}
/**
* \brief Perform RF Reset as per Emvco Specification
* \return Status code
* \retval #PH_ERR_SUCCESS Operation successful.
* \retval Other Depending on implementation and underlying component.
*/
static void EmvcoRfReset(phacDiscLoop_Sw_DataParams_t * pDataParams)
{
phStatus_t status = PH_ERR_SUCCESS;
/*RF Field OFF*/
status = phhalHw_FieldOff(pDataParams->pHalDataParams);
CHECK_STATUS(status);
status = phhalHw_Wait(pDataParams->pHalDataParams,PHHAL_HW_TIME_MICROSECONDS, 5100);
CHECK_STATUS(status);
/*RF Field ON*/
status = phhalHw_FieldOn(pDataParams->pHalDataParams);
CHECK_STATUS(status);
}
/**
* \brief EMVCo Loop-Back function
* This Loop-Back function converts each received R-APDU into the next C-APDU (by stripping the
* status words), and sends this C-APDU back to the card simulator.
* Also this function send SELECT_PPSE command after card activation.
* Loop-Back Function exist when EOT (End Of Test) Command is received from the card simulator.
* \return Status code
* \retval #PH_ERR_SUCCESS Operation successful.
* \retval Other Depending on implementation and underlying component.
*/
static phStatus_t EmvcoDataLoopBack(phacDiscLoop_Sw_DataParams_t * pDataParams)
{
uint32_t cmdsize, respsize;
phStatus_t status;
uint8_t bEndOfLoopBack = 0;
uint8_t bRemovalProcedure = PH_OFF;
cmdsize = sizeof(PPSE_SELECT_APDU);
status = EmvcoDataExchange(PPSE_SELECT_APDU, cmdsize, &response_buffer, &respsize);
#ifndef RUN_TEST_SUIT
/*Check if P1 is 0x04 which means that the data field consists of DF name */
if(PPSE_SELECT_APDU[2] == 0x04)
{
DEBUG_PRINTF("\n DF Name: \n");
/* DF Size = Total Command size - size of(PDU Header + Expected Len(Le))*/
phApp_Print_Buff(&PPSE_SELECT_APDU[5], PPSE_SELECT_APDU[4]);
}
if (respsize > 0)
{
memcpy(&PPSE_response_buffer[0],response_buffer,respsize);
DEBUG_PRINTF("\n SELECT_PPSE Res:\n");
/* Status word removed */
phApp_Print_Buff(PPSE_response_buffer, (respsize - 2));
DEBUG_PRINTF("\nTransaction Done Remove card\n");
}
else
{
DEBUG_PRINTF("\nFCI not recieved\n");
#ifdef PPSE_NO_LE
DEBUG_PRINTF("Transaction Done Remove card\n");
#else
DEBUG_PRINTF("Transaction Failed Replace the card\n");
#endif
}
#endif
while (!bEndOfLoopBack)
{
if (respsize > 0)
{
if (respsize >= MiN_VALID_DATA_SIZE)
{
/* EOT (End Of Test) Command. Exit the loop */
if (eEmdRes_EOT == response_buffer[1])
{
/* Second byte = 0x70, stop the loopback */
bEndOfLoopBack = 1;
bRemovalProcedure = PH_ON;
}
else if (eEmdRes_SW_0 == response_buffer[respsize - 2])
{
/* Format the card response into a new command without the status word 0x90 0x00 */
cmdsize = respsize - 2; /* To Remove two bytes of status word */
memcpy(command_buffer, response_buffer, cmdsize);
/* Send back(Command) : Received Response - Status_Word */
status = EmvcoDataExchange(command_buffer, cmdsize, &response_buffer, &respsize);
}
else
{
/* error Abort Loopback */
bEndOfLoopBack = 1;
}
}
else/*if (respsize <6)*/
{
/* re-send the select appli APDU */
status = EmvcoDataExchange(PPSE_SELECT_APDU, cmdsize, &response_buffer, &respsize);
if (respsize == 0)
{
bEndOfLoopBack = 1;
}
}
}/*if(respsize > 0)*/
else
{
bEndOfLoopBack = 1;
}
}/*while (!bEndOfLoopBack)*/
if(bRemovalProcedure == PH_ON)
{
/* Set Poll state to perform Tag removal procedure*/
status = phacDiscLoop_SetConfig(pDataParams, PHAC_DISCLOOP_CONFIG_NEXT_POLL_STATE, PHAC_DISCLOOP_POLL_STATE_REMOVAL);
CHECK_STATUS(status);
status = phacDiscLoop_Run(pDataParams, PHAC_DISCLOOP_ENTRY_POINT_POLL);
}
return status;
}
/**
* \brief Exchange Data APDU Packets for EMVCO (ISO14443-4 Exchange)
* This function will Exchange APDU data packets provided by Loop-Back Application
* \return Status code
* \retval #PH_ERR_SUCCESS Operation successful.
* \retval Other Depending on implementation and underlying component.
*/
static phStatus_t EmvcoDataExchange(uint8_t * com_buffer, uint8_t cmdsize, uint8_t ** resp_buffer, uint32_t * wRxLength)
{
phStatus_t status;
uint8_t *ppRxBuffer;
uint16_t wRxLen = 0;
status = phpalI14443p4_Exchange(phNfcLib_GetDataParams(PH_COMP_PAL_ISO14443P4), PH_EXCHANGE_DEFAULT,
com_buffer, cmdsize, &ppRxBuffer, &wRxLen);
if (PH_ERR_SUCCESS == status)
{
/* set the pointer to the start of the R-APDU */
*resp_buffer = &ppRxBuffer[0];
}
else
{
/* Exchange not successful, reset the number of rxd bytes */
wRxLen = 0x00;
}
*wRxLength = wRxLen;
return status;
}
#endif /* ENABLE_EMVCO_PROF */

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/*----------------------------------------------------------------------------*/
/* Copyright 2020 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may only */
/* be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that you */
/* have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*----------------------------------------------------------------------------*/
/** \file
* Example Source abstracting component data structure and code initialization and code specific to HW used in the examples
* This file shall be present in all examples. A customer does not need to touch/modify this file. This file
* purely depends on the phNxpBuild_Lpc.h or phNxpBuild_App.h
* The phAppInit.h externs the component data structures initialized here that is in turn included by the core examples.
* The core example shall not use any other variable defined here except the RdLib component data structures(as explained above)
* The RdLib component initialization requires some user defined data and function pointers.
* These are defined in the respective examples and externed here.
*
* Keystore and Crypto initialization needs to be handled by application.
*
* $Author$
* $Revision$ (v07.10.00)
* $Date$
*
*/
#include "phApp_Init.h"
#include <phOsal.h>
/*******************************************************************************
** Function Declarations
*******************************************************************************/
/*******************************************************************************
** Function Definitions
*******************************************************************************/
/* Print technology being resolved */
void phApp_PrintTech(uint8_t TechType)
{
switch(TechType)
{
case PHAC_DISCLOOP_POS_BIT_MASK_A:
DEBUG_PRINTF ("\tResolving Type A... \n");
break;
case PHAC_DISCLOOP_POS_BIT_MASK_B:
DEBUG_PRINTF ("\tResolving Type B... \n");
break;
case PHAC_DISCLOOP_POS_BIT_MASK_F212:
DEBUG_PRINTF ("\tResolving Type F with baud rate 212... \n");
break;
case PHAC_DISCLOOP_POS_BIT_MASK_F424:
DEBUG_PRINTF ("\tResolving Type F with baud rate 424... \n");
break;
case PHAC_DISCLOOP_POS_BIT_MASK_V:
DEBUG_PRINTF ("\tResolving Type V... \n");
break;
default:
break;
}
}
/**
* This function will print buffer content
* \param *pBuff Buffer Reference
* \param num data size to be print
*/
void phApp_Print_Buff(uint8_t *pBuff, uint8_t num)
{
uint32_t i;
for(i = 0; i < num; i++)
{
DEBUG_PRINTF(" %02X",pBuff[i]);
}
}
/**
* This function will print Tag information
* \param pDataParams The discovery loop data parameters
* \param wNumberOfTags Total number of tags detected
* \param wTagsDetected Technology Detected
*/
void phApp_PrintTagInfo(phacDiscLoop_Sw_DataParams_t *pDataParams, uint16_t wNumberOfTags, uint16_t wTagsDetected)
{
#if defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_TAGS) || \
defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_P2P_ACTIVE) || \
defined(NXPBUILD__PHAC_DISCLOOP_TYPEB_TAGS) || \
defined(NXPBUILD__PHAC_DISCLOOP_TYPEF_TAGS) || \
defined(NXPBUILD__PHAC_DISCLOOP_TYPEV_TAGS) || \
defined(NXPBUILD__PHAC_DISCLOOP_I18000P3M3_TAGS)
uint8_t bIndex;
#endif
#if defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_TAGS) || defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_P2P_ACTIVE)
uint8_t bTagType;
#endif
#if defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_TAGS) || defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_P2P_ACTIVE)
if (PHAC_DISCLOOP_CHECK_ANDMASK(wTagsDetected, PHAC_DISCLOOP_POS_BIT_MASK_A))
{
if(pDataParams->sTypeATargetInfo.bT1TFlag)
{
DEBUG_PRINTF("\tTechnology : Type A");
DEBUG_PRINTF ("\n\t\tUID :");
phApp_Print_Buff( pDataParams->sTypeATargetInfo.aTypeA_I3P3[0].aUid,
pDataParams->sTypeATargetInfo.aTypeA_I3P3[0].bUidSize);
DEBUG_PRINTF ("\n\t\tSAK : 0x%02x",pDataParams->sTypeATargetInfo.aTypeA_I3P3[0].aSak);
DEBUG_PRINTF ("\n\t\tType: Type 1 Tag\n");
}
else
{
DEBUG_PRINTF("\tTechnology : Type A");
for(bIndex = 0; bIndex < wNumberOfTags; bIndex++)
{
DEBUG_PRINTF ("\n\t\tCard: %d",bIndex + 1);
DEBUG_PRINTF ("\n\t\tUID :");
phApp_Print_Buff( pDataParams->sTypeATargetInfo.aTypeA_I3P3[bIndex].aUid,
pDataParams->sTypeATargetInfo.aTypeA_I3P3[bIndex].bUidSize);
DEBUG_PRINTF ("\n\t\tSAK : 0x%02x",pDataParams->sTypeATargetInfo.aTypeA_I3P3[bIndex].aSak);
if ((pDataParams->sTypeATargetInfo.aTypeA_I3P3[bIndex].aSak & (uint8_t) ~0xFB) == 0)
{
/* Bit b3 is set to zero, [Digital] 4.8.2 */
/* Mask out all other bits except for b7 and b6 */
bTagType = (pDataParams->sTypeATargetInfo.aTypeA_I3P3[bIndex].aSak & 0x60);
bTagType = bTagType >> 5;
switch(bTagType)
{
case PHAC_DISCLOOP_TYPEA_TYPE2_TAG_CONFIG_MASK:
DEBUG_PRINTF ("\n\t\tType: Type 2 Tag\n");
break;
case PHAC_DISCLOOP_TYPEA_TYPE4A_TAG_CONFIG_MASK:
DEBUG_PRINTF ("\n\t\tType: Type 4A Tag\n");
break;
case PHAC_DISCLOOP_TYPEA_TYPE_NFC_DEP_TAG_CONFIG_MASK:
DEBUG_PRINTF ("\n\t\tType: P2P\n");
break;
case PHAC_DISCLOOP_TYPEA_TYPE_NFC_DEP_TYPE4A_TAG_CONFIG_MASK:
DEBUG_PRINTF ("\n\t\tType: Type NFC_DEP and 4A Tag\n");
break;
default:
break;
}
}
}
}
}
#endif
#ifdef NXPBUILD__PHAC_DISCLOOP_TYPEB_TAGS
if (PHAC_DISCLOOP_CHECK_ANDMASK(wTagsDetected, PHAC_DISCLOOP_POS_BIT_MASK_B))
{
DEBUG_PRINTF("\tTechnology : Type B");
/* Loop through all the Type B tags detected and print the Pupi */
for (bIndex = 0; bIndex < wNumberOfTags; bIndex++)
{
DEBUG_PRINTF ("\n\t\tCard: %d",bIndex + 1);
DEBUG_PRINTF ("\n\t\tUID :");
/* PUPI Length is always 4 bytes */
phApp_Print_Buff( pDataParams->sTypeBTargetInfo.aTypeB_I3P3[bIndex].aPupi, 0x04);
}
DEBUG_PRINTF("\n");
}
#endif /* NXPBUILD__PHAC_DISCLOOP_TYPEB_TAGS */
#ifdef NXPBUILD__PHAC_DISCLOOP_TYPEF_TAGS
if( PHAC_DISCLOOP_CHECK_ANDMASK(wTagsDetected, PHAC_DISCLOOP_POS_BIT_MASK_F212) ||
PHAC_DISCLOOP_CHECK_ANDMASK(wTagsDetected, PHAC_DISCLOOP_POS_BIT_MASK_F424))
{
DEBUG_PRINTF("\tTechnology : Type F");
/* Loop through all the type F tags and print the IDm */
for (bIndex = 0; bIndex < wNumberOfTags; bIndex++)
{
DEBUG_PRINTF ("\n\t\tCard: %d",bIndex + 1);
DEBUG_PRINTF ("\n\t\tUID :");
phApp_Print_Buff( pDataParams->sTypeFTargetInfo.aTypeFTag[bIndex].aIDmPMm,
PHAC_DISCLOOP_FELICA_IDM_LENGTH );
if ((pDataParams->sTypeFTargetInfo.aTypeFTag[bIndex].aIDmPMm[0] == 0x01) &&
(pDataParams->sTypeFTargetInfo.aTypeFTag[bIndex].aIDmPMm[1] == 0xFE))
{
/* This is Type F tag with P2P capabilities */
DEBUG_PRINTF ("\n\t\tType: P2P");
}
else
{
/* This is Type F T3T tag */
DEBUG_PRINTF ("\n\t\tType: Type 3 Tag");
}
if(pDataParams->sTypeFTargetInfo.aTypeFTag[bIndex].bBaud != PHAC_DISCLOOP_CON_BITR_212)
{
DEBUG_PRINTF ("\n\t\tBit Rate: 424\n");
}
else
{
DEBUG_PRINTF ("\n\t\tBit Rate: 212\n");
}
}
}
#endif /* NXPBUILD__PHAC_DISCLOOP_TYPEF_TAGS */
#ifdef NXPBUILD__PHAC_DISCLOOP_TYPEV_TAGS
if (PHAC_DISCLOOP_CHECK_ANDMASK(wTagsDetected, PHAC_DISCLOOP_POS_BIT_MASK_V))
{
DEBUG_PRINTF("\tTechnology : Type V / ISO 15693 / T5T");
/* Loop through all the Type V tags detected and print the UIDs */
for (bIndex = 0; bIndex < wNumberOfTags; bIndex++)
{
DEBUG_PRINTF ("\n\t\tCard: %d",bIndex + 1);
DEBUG_PRINTF ("\n\t\tUID :");
phApp_Print_Buff( pDataParams->sTypeVTargetInfo.aTypeV[bIndex].aUid, 0x08);
}
DEBUG_PRINTF("\n");
}
#endif /* NXPBUILD__PHAC_DISCLOOP_TYPEV_TAGS */
#ifdef NXPBUILD__PHAC_DISCLOOP_I18000P3M3_TAGS
if (PHAC_DISCLOOP_CHECK_ANDMASK(wTagsDetected, PHAC_DISCLOOP_POS_BIT_MASK_18000P3M3))
{
DEBUG_PRINTF("\tTechnology : ISO 18000p3m3 / EPC Gen2");
/* Loop through all the 18000p3m3 tags detected and print the UII */
for (bIndex = 0; bIndex < wNumberOfTags; bIndex++)
{
DEBUG_PRINTF("\n\t\tCard: %d",bIndex + 1);
DEBUG_PRINTF("\n\t\tUII :");
phApp_Print_Buff(
pDataParams->sI18000p3m3TargetInfo.aI18000p3m3[bIndex].aUii,
(pDataParams->sI18000p3m3TargetInfo.aI18000p3m3[bIndex].wUiiLength / 8));
}
DEBUG_PRINTF("\n");
}
#endif /* NXPBUILD__PHAC_DISCLOOP_I18000P3M3_TAGS */
}
/**
* This function will print Error information received from Reader Lib
* \param wStatus Error status
*/
void PrintErrorInfo(phStatus_t wStatus)
{
DEBUG_PRINTF("\n ErrorInfo Comp:");
switch(wStatus & 0xFF00)
{
case PH_COMP_BAL:
DEBUG_PRINTF("\t PH_COMP_BAL");
break;
case PH_COMP_HAL:
DEBUG_PRINTF("\t PH_COMP_HAL");
break;
case PH_COMP_PAL_ISO14443P3A:
DEBUG_PRINTF("\t PH_COMP_PAL_ISO14443P3A");
break;
case PH_COMP_PAL_ISO14443P3B:
DEBUG_PRINTF("\t PH_COMP_PAL_ISO14443P3B");
break;
case PH_COMP_PAL_ISO14443P4A:
DEBUG_PRINTF("\t PH_COMP_PAL_ISO14443P4A");
break;
case PH_COMP_PAL_ISO14443P4:
DEBUG_PRINTF("\t PH_COMP_PAL_ISO14443P4");
break;
case PH_COMP_PAL_FELICA:
DEBUG_PRINTF("\t PH_COMP_PAL_FELICA");
break;
case PH_COMP_PAL_EPCUID:
DEBUG_PRINTF("\t PH_COMP_PAL_EPCUID");
break;
case PH_COMP_PAL_SLI15693:
DEBUG_PRINTF("\t PH_COMP_PAL_SLI15693");
break;
case PH_COMP_PAL_I18000P3M3:
DEBUG_PRINTF("\t PH_COMP_PAL_I18000P3M3");
break;
case PH_COMP_PAL_I18092MPI:
DEBUG_PRINTF("\t PH_COMP_PAL_I18092MPI");
break;
case PH_COMP_PAL_I18092MT:
DEBUG_PRINTF("\t PH_COMP_PAL_I18092MT");
break;
case PH_COMP_PAL_I14443P4MC:
DEBUG_PRINTF("\t PH_COMP_PAL_I14443P4MC");
break;
case PH_COMP_AC_DISCLOOP:
DEBUG_PRINTF("\t PH_COMP_AC_DISCLOOP");
break;
case PH_COMP_OSAL:
DEBUG_PRINTF("\t PH_COMP_OSAL");
break;
default:
DEBUG_PRINTF("\t 0x%x",(wStatus & PH_COMPID_MASK));
break;
}
DEBUG_PRINTF("\t type:");
switch(wStatus & PH_ERR_MASK)
{
case PH_ERR_SUCCESS_INCOMPLETE_BYTE:
DEBUG_PRINTF("\t PH_ERR_SUCCESS_INCOMPLETE_BYTE");
break;
case PH_ERR_IO_TIMEOUT:
DEBUG_PRINTF("\t PH_ERR_IO_TIMEOUT");
break;
case PH_ERR_INTEGRITY_ERROR:
DEBUG_PRINTF("\t PH_ERR_INTEGRITY_ERROR");
break;
case PH_ERR_COLLISION_ERROR:
DEBUG_PRINTF("\t PH_ERR_COLLISION_ERROR");
break;
case PH_ERR_BUFFER_OVERFLOW:
DEBUG_PRINTF("\t PH_ERR_BUFFER_OVERFLOW");
break;
case PH_ERR_FRAMING_ERROR:
DEBUG_PRINTF("\t PH_ERR_FRAMING_ERROR");
break;
case PH_ERR_PROTOCOL_ERROR:
DEBUG_PRINTF("\t PH_ERR_PROTOCOL_ERROR");
break;
case PH_ERR_RF_ERROR:
DEBUG_PRINTF("\t PH_ERR_RF_ERROR");
break;
case PH_ERR_EXT_RF_ERROR:
DEBUG_PRINTF("\t PH_ERR_EXT_RF_ERROR");
break;
case PH_ERR_NOISE_ERROR:
DEBUG_PRINTF("\t PH_ERR_NOISE_ERROR");
break;
case PH_ERR_ABORTED:
DEBUG_PRINTF("\t PH_ERR_ABORTED");
break;
case PH_ERR_INTERNAL_ERROR:
DEBUG_PRINTF("\t PH_ERR_INTERNAL_ERROR");
break;
case PH_ERR_INVALID_DATA_PARAMS:
DEBUG_PRINTF("\t PH_ERR_INVALID_DATA_PARAMS");
break;
case PH_ERR_INVALID_PARAMETER:
DEBUG_PRINTF("\t PH_ERR_INVALID_PARAMETER");
break;
case PH_ERR_PARAMETER_OVERFLOW:
DEBUG_PRINTF("\t PH_ERR_PARAMETER_OVERFLOW");
break;
case PH_ERR_UNSUPPORTED_PARAMETER:
DEBUG_PRINTF("\t PH_ERR_UNSUPPORTED_PARAMETER");
break;
case PH_ERR_OSAL_ERROR:
DEBUG_PRINTF("\t PH_ERR_OSAL_ERROR");
break;
case PHAC_DISCLOOP_LPCD_NO_TECH_DETECTED:
DEBUG_PRINTF("\t PHAC_DISCLOOP_LPCD_NO_TECH_DETECTED");
break;
case PHAC_DISCLOOP_COLLISION_PENDING:
DEBUG_PRINTF("\t PHAC_DISCLOOP_COLLISION_PENDING");
break;
default:
DEBUG_PRINTF("\t 0x%x",(wStatus & PH_ERR_MASK));
break;
}
}
/******************************************************************************
** End Of File
******************************************************************************/

View File

@ -0,0 +1,438 @@
/*----------------------------------------------------------------------------*/
/* Copyright 2016-2022 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may only */
/* be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that you */
/* have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*----------------------------------------------------------------------------*/
/** \file
* Example Source abstracting component data structure and code initialization and code specific to HW used in the examples
* This file shall be present in all examples. A customer does not need to touch/modify this file. This file
* purely depends on the phNxpBuild_Lpc.h or phNxpBuild_App.h
* The phAppInit.h externs the component data structures initialized here that is in turn included by the core examples.
* The core example shall not use any other variable defined here except the RdLib component data structures(as explained above)
* The RdLib component initialization requires some user defined data and function pointers.
* These are defined in the respective examples and externed here.
*
* Keystore and Crypto initialization needs to be handled by application.
*
* $Author$
* $Revision$ (v07.10.00)
* $Date$
*
*/
/* Status header */
#include <ph_Status.h>
#include "phApp_Init.h"
/* LLCP header */
#include <phlnLlcp.h>
#include <phOsal.h>
#ifdef PH_PLATFORM_HAS_ICFRONTEND
#include "BoardSelection.h"
#endif
#ifdef PHDRIVER_KINETIS_K82
#include <fsl_port.h>
#include <fsl_pit.h>
#ifdef DEBUG
#include <fsl_clock.h>
#endif /* DEBUG */
#endif /* PHDRIVER_KINETIS_K82 */
#ifdef PHDRIVER_KINETIS_K82
#ifdef DEBUG
#define KINETIS_K82_DEBUG_UART_CLK_FREQ CLOCK_GetOsc0ErClkFreq()
#define KINETIS_K82_DEBUG_UART_BASEADDR (uint32_t)(LPUART4)
#define KINETIS_K82_DEBUG_UART_INSTANCE 4U
#define KINETIS_K82_DEBUG_UART_BAUDRATE 115200
#define KINETIS_K82_DEBUG_UART_TYPE DEBUG_CONSOLE_DEVICE_TYPE_LPUART
#endif /* DEBUG */
/*! @brief Clock configuration structure. */
typedef struct _clock_config
{
mcg_config_t mcgConfig; /*!< MCG configuration. */
sim_clock_config_t simConfig; /*!< SIM configuration. */
osc_config_t oscConfig; /*!< OSC configuration. */
uint32_t coreClock; /*!< core clock frequency. */
} clock_config_t;
#endif /* PHDRIVER_KINETIS_K82 */
#ifdef PH_OSAL_LINUX
# define PI_IRQ_POLLING_TASK_PRIO 0
# define PI_IRQ_POLLING_TASK_STACK 0x20000
phOsal_ThreadObj_t gphPiThreadObj;
#endif /* PH_OSAL_LINUX */
#if defined(PHDRIVER_LPC1769) && defined(__CC_ARM)
uint32_t SystemCoreClock;
#endif
/*******************************************************************************
** Function Declarations
*******************************************************************************/
#ifdef PHDRIVER_KINETIS_K82
static void phApp_K82_Init(void);
#endif /* PHDRIVER_KINETIS_K82 */
#ifdef PH_OSAL_LINUX
static void phExample_IrqPolling(void* param);
#endif /* PH_OSAL_LINUX */
phStatus_t phApp_Configure_IRQ();
/*******************************************************************************
** Clock configuration of K82 Platform
*******************************************************************************/
#ifdef PHDRIVER_KINETIS_K82
/* Configuration for enter RUN mode. Core clock = 50MHz. */
const clock_config_t g_defaultClockConfigRun = {
.mcgConfig =
{
.mcgMode = kMCG_ModePEE, /* Work in PEE mode. */
.irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enable. */
.ircs = kMCG_IrcSlow, /* Select IRC32k. */
.fcrdiv = 0U, /* FCRDIV is 0. */
.frdiv = 4U,
.drs = kMCG_DrsLow, /* Low frequency range. */
.dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25%. */
.oscsel = kMCG_OscselOsc, /* Select OSC. */
.pll0Config =
{
.enableMode = 0U, .prdiv = 0x01U, .vdiv = 0x01U,
},
},
.simConfig =
{
.pllFllSel = 1U, /* PLLFLLSEL select PLL. */
.pllFllDiv = 0U, /* PLLFLLSEL clock divider divisor. */
.pllFllFrac = 0U, /* PLLFLLSEL clock divider fraction. */
.er32kSrc = 5U, /* ERCLK32K selection, use RTC. */
.clkdiv1 = 0x01140000U, /* SIM_CLKDIV1. */
},
.oscConfig = {.freq = CPU_XTAL_CLK_HZ,
.capLoad = 0,
.workMode = kOSC_ModeOscLowPower,
.oscerConfig =
{
.enableMode = kOSC_ErClkEnable,
#if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER)
.erclkDiv = 0U,
#endif
}},
};
#endif /* PHDRIVER_KINETIS_K82 */
/*******************************************************************************
** Global Variable Declaration
*******************************************************************************/
#ifdef NXPBUILD__PHLN_LLCP_SW
phlnLlcp_Sw_DataParams_t slnLlcp; /* LLCP component */
#endif /* NXPBUILD__PHLN_LLCP_SW */
/* General information bytes to be sent with ATR Request */
#if defined(NXPBUILD__PHPAL_I18092MPI_SW) || defined(NXPBUILD__PHPAL_I18092MT_SW)
uint8_t aLLCPGeneralBytes[36] = { 0x46,0x66,0x6D,
0x01,0x01,0x10, /*VERSION*/
0x03,0x02,0x00,0x01, /*WKS*/
0x04,0x01,0xF1 /*LTO*/
};
uint8_t bLLCPGBLength = 13;
#endif
/* ATR Response or ATS Response holder */
#if defined(NXPBUILD__PHPAL_I14443P4A_SW) || \
defined(NXPBUILD__PHPAL_I18092MPI_SW)
uint8_t aResponseHolder[64];
#endif
/* prints if error is detected */
#define CHECK_SUCCESS(x) \
if ((x) != PH_ERR_SUCCESS) \
{ \
DEBUG_PRINTF("\nLine: %d Error - (0x%04X) has occurred : 0xCCEE CC-Component ID, EE-Error code. Refer-ph_Status.h\n ", __LINE__, (x)); \
return (x); \
}
/*******************************************************************************
** Function Definitions
*******************************************************************************/
#ifdef PHDRIVER_KINETIS_K82
static void phApp_K82_Init(void)
{
#ifdef DEBUG
uint32_t uartClkSrcFreq;
#endif /* DEBUG */
pit_config_t pitConfig; /* Structure of initialize PIT */
CLOCK_SetSimSafeDivs();
CLOCK_InitOsc0(&g_defaultClockConfigRun.oscConfig);
CLOCK_SetXtal0Freq(CPU_XTAL_CLK_HZ);
CLOCK_BootToPeeMode(g_defaultClockConfigRun.mcgConfig.oscsel, kMCG_PllClkSelPll0,
&g_defaultClockConfigRun.mcgConfig.pll0Config);
CLOCK_SetInternalRefClkConfig(g_defaultClockConfigRun.mcgConfig.irclkEnableMode,
g_defaultClockConfigRun.mcgConfig.ircs, g_defaultClockConfigRun.mcgConfig.fcrdiv);
CLOCK_SetSimConfig(&g_defaultClockConfigRun.simConfig);
SystemCoreClockUpdate();
/*
* pitConfig.enableRunInDebug = false;
*/
PIT_GetDefaultConfig(&pitConfig);
/* Init pit module */
PIT_Init(PIT, &pitConfig);
#ifdef DEBUG
/* Initialize LPUART4 pins below used to Print */
/* Ungate the port clock */
CLOCK_EnableClock(kCLOCK_PortC);
/* Affects PORTC_PCR14 register */
PORT_SetPinMux(PORTC, 14U, kPORT_MuxAlt3);
/* Affects PORTC_PCR15 register */
PORT_SetPinMux(PORTC, 15U, kPORT_MuxAlt3);
/* SIM_SOPT2[27:26]:
* 00: Clock Disabled
* 01: MCGFLLCLK, or MCGPLLCLK, or IRC48M
* 10: OSCERCLK
* 11: MCGIRCCLK
*/
CLOCK_SetLpuartClock(2);
uartClkSrcFreq = KINETIS_K82_DEBUG_UART_CLK_FREQ;
DbgConsole_Init(KINETIS_K82_DEBUG_UART_INSTANCE, KINETIS_K82_DEBUG_UART_BAUDRATE, KINETIS_K82_DEBUG_UART_TYPE, uartClkSrcFreq);
#endif /* DEBUG */
}
#endif /* PHDRIVER_KINETIS_K82 */
#ifdef PH_PLATFORM_HAS_ICFRONTEND
/**
* This function will initialize Host Controller interfaced with NXP Reader IC's.
* Any initialization which is not generic across Platforms, should be done here.
* Note: For NXP NFC Controllers HOST initialization is not required.
*/
void phApp_CPU_Init(void)
{
#if defined PHDRIVER_KINETIS_K82
phApp_K82_Init();
#elif defined(PHDRIVER_LPC1769) && defined(__CC_ARM)
SystemCoreClock = (( unsigned long ) 96000000);
#elif defined(PH_OSAL_LINUX) && defined(NXPBUILD__PHHAL_HW_PN5190)
phStatus_t status;
status = PiGpio_OpenIrq();
if ((status & PH_ERR_MASK) != PH_ERR_SUCCESS)
{
DEBUG_PRINTF("\n PiGpio_OpenIrq failed \n");
DEBUG_PRINTF("\n Couldn't open PN5190 Kernel IRQ Driver.\n Halting here!!FIX IT!!\n");
while(1);
}
#else
/* In case of LPC series, startup file takes care of initializing clock and ports.
* No initialization is required in Linux environment. */
#endif
}
#endif /* PH_PLATFORM_HAS_ICFRONTEND */
/**
* This function will initialize Reader LIbrary Component
*/
phStatus_t phApp_Comp_Init(void * pDiscLoopParams)
{
phStatus_t wStatus = PH_ERR_SUCCESS;
#if defined(NXPBUILD__PHPAL_I18092MPI_SW) || defined(NXPBUILD__PHPAL_I18092MT_SW) || \
defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_P2P_TAGS) || defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_P2P_ACTIVE) || \
defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_I3P4_TAGS) || defined(NXPBUILD__PHAC_DISCLOOP_TYPEF_P2P_TAGS) || \
defined(NXPBUILD__PHAC_DISCLOOP_TYPEF212_P2P_ACTIVE) || defined(NXPBUILD__PHAC_DISCLOOP_TYPEF424_P2P_ACTIVE)
phacDiscLoop_Sw_DataParams_t * pDiscLoop = (phacDiscLoop_Sw_DataParams_t *)pDiscLoopParams;
#endif
/* Initialize the LLCP component */
#ifdef NXPBUILD__PHLN_LLCP_SW
slnLlcp.sLocalLMParams.wMiu = 0x00; /* 128 bytes only */
slnLlcp.sLocalLMParams.wWks = 0x11; /* SNEP & LLCP */
slnLlcp.sLocalLMParams.bLto = 100; /* Maximum LTO */
slnLlcp.sLocalLMParams.bOpt = 0x02;
slnLlcp.sLocalLMParams.bAvailableTlv = PHLN_LLCP_TLV_MIUX_MASK | PHLN_LLCP_TLV_WKS_MASK |
PHLN_LLCP_TLV_LTO_MASK | PHLN_LLCP_TLV_OPT_MASK;
wStatus = phlnLlcp_Sw_Init(
&slnLlcp,
sizeof(phlnLlcp_Sw_DataParams_t),
aLLCPGeneralBytes,
&bLLCPGBLength);
#endif /* NXPBUILD__PHLN_LLCP_SW */
#ifdef NXPBUILD__PHAC_DISCLOOP_SW
#if defined(NXPBUILD__PHPAL_I18092MPI_SW) || defined(NXPBUILD__PHPAL_I18092MT_SW)
/* Assign the GI for Type A */
pDiscLoop->sTypeATargetInfo.sTypeA_P2P.pGi = (uint8_t *)aLLCPGeneralBytes;
pDiscLoop->sTypeATargetInfo.sTypeA_P2P.bGiLength = bLLCPGBLength;
/* Assign the GI for Type F */
pDiscLoop->sTypeFTargetInfo.sTypeF_P2P.pGi = (uint8_t *)aLLCPGeneralBytes;
pDiscLoop->sTypeFTargetInfo.sTypeF_P2P.bGiLength = bLLCPGBLength;
#endif
#if defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_P2P_TAGS) || defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_P2P_ACTIVE)
/* Assign ATR response for Type A */
pDiscLoop->sTypeATargetInfo.sTypeA_P2P.pAtrRes = aResponseHolder;
#endif
#if defined(NXPBUILD__PHAC_DISCLOOP_TYPEF_P2P_TAGS) || defined(NXPBUILD__PHAC_DISCLOOP_TYPEF212_P2P_ACTIVE) || \
defined(NXPBUILD__PHAC_DISCLOOP_TYPEF424_P2P_ACTIVE)
/* Assign ATR response for Type F */
pDiscLoop->sTypeFTargetInfo.sTypeF_P2P.pAtrRes = aResponseHolder;
#endif
#ifdef NXPBUILD__PHAC_DISCLOOP_TYPEA_I3P4_TAGS
/* Assign ATS buffer for Type A */
pDiscLoop->sTypeATargetInfo.sTypeA_I3P4.pAts = aResponseHolder;
#endif /* NXPBUILD__PHAC_DISCLOOP_TYPEA_I3P4_TAGS */
#endif /* NXPBUILD__PHAC_DISCLOOP_SW */
return wStatus;
}
phStatus_t phApp_Configure_IRQ()
{
#ifdef PH_OSAL_LINUX
phStatus_t wStatus;
#endif /* PH_OSAL_LINUX */
#ifdef PH_PLATFORM_HAS_ICFRONTEND
#if !(defined(PH_OSAL_LINUX) && defined(NXPBUILD__PHHAL_HW_PN5190))
phDriver_Pin_Config_t pinCfg;
pinCfg.bOutputLogic = PH_DRIVER_SET_LOW;
pinCfg.bPullSelect = PHDRIVER_PIN_IRQ_PULL_CFG;
pinCfg.eInterruptConfig = PIN_IRQ_TRIGGER_TYPE;
phDriver_PinConfig(PHDRIVER_PIN_IRQ, PH_DRIVER_PINFUNC_INTERRUPT, &pinCfg);
#endif
#ifdef PHDRIVER_LPC1769
NVIC_SetPriority(EINT_IRQn, EINT_PRIORITY);
/* Enable interrupt in the NVIC */
NVIC_ClearPendingIRQ(EINT_IRQn);
NVIC_EnableIRQ(EINT_IRQn);
#endif /* PHDRIVER_LPC1769 */
#ifdef PH_OSAL_LINUX
gphPiThreadObj.pTaskName = (uint8_t *) "IrqPolling";
gphPiThreadObj.pStackBuffer = NULL;
gphPiThreadObj.priority = PI_IRQ_POLLING_TASK_PRIO;
gphPiThreadObj.stackSizeInNum = PI_IRQ_POLLING_TASK_STACK;
PH_CHECK_SUCCESS_FCT(wStatus, phOsal_ThreadCreate(&gphPiThreadObj.ThreadHandle, &gphPiThreadObj,
&phExample_IrqPolling, NULL));
#endif /* PH_OSAL_LINUX */
#ifdef PHDRIVER_KINETIS_K82
NVIC_SetPriority(EINT_IRQn, EINT_PRIORITY);
NVIC_ClearPendingIRQ(EINT_IRQn);
EnableIRQ(EINT_IRQn);
#endif /* PHDRIVER_KINETIS_K82 */
#endif /* #ifdef PH_PLATFORM_HAS_ICFRONTEND */
return PH_ERR_SUCCESS;
}
#ifdef PH_OSAL_LINUX
/*
* \brief: The purpose of this Thread is to detect RF signal from an External Peer .
*/
static void phExample_IrqPolling(void* param)
{
uint8_t bgpioVal = 0;
uint8_t bhighOrLow = 0;
#if defined(NXPBUILD__PHHAL_HW_RC663) || defined(NXPBUILD__PHHAL_HW_PN5180)
if(PIN_IRQ_TRIGGER_TYPE == PH_DRIVER_INTERRUPT_RISINGEDGE)
{
bhighOrLow = 1;
}
while(PiGpio_read(PHDRIVER_PIN_IRQ, &bgpioVal) != PH_ERR_SUCCESS)
{
PiGpio_unexport(PHDRIVER_PIN_IRQ);
PiGpio_export(PHDRIVER_PIN_IRQ);
PiGpio_set_direction(PHDRIVER_PIN_IRQ, false);
if(PIN_IRQ_TRIGGER_TYPE == PH_DRIVER_INTERRUPT_RISINGEDGE)
{
PiGpio_set_edge(PHDRIVER_PIN_IRQ, true, false);
}
else
{
PiGpio_set_edge(PHDRIVER_PIN_IRQ, false, true);
}
}
/* Initial status: If pin is already Active, post an event. */
if(bgpioVal == bhighOrLow)
{
CLIF_IRQHandler();
}
#endif
while(1)
{
/* Block forever for Raising Edge in PHDRIVER_PIN_IRQ. */
#if defined(NXPBUILD__PHHAL_HW_RC663) || defined(NXPBUILD__PHHAL_HW_PN5180)
if(PiGpio_poll(PHDRIVER_PIN_IRQ, bhighOrLow, -1) == PH_ERR_SUCCESS)
#elif defined(NXPBUILD__PHHAL_HW_PN5190)
if(PiGpio_Irq() == PH_ERR_SUCCESS)
#endif
{
CLIF_IRQHandler();
}
else
{
PiGpio_unexport(PHDRIVER_PIN_IRQ);
PiGpio_export(PHDRIVER_PIN_IRQ);
PiGpio_set_direction(PHDRIVER_PIN_IRQ, false);
if(PIN_IRQ_TRIGGER_TYPE == PH_DRIVER_INTERRUPT_RISINGEDGE)
{
PiGpio_set_edge(PHDRIVER_PIN_IRQ, true, false);
}
else
{
PiGpio_set_edge(PHDRIVER_PIN_IRQ, false, true);
}
}
}
}
#endif /* PH_OSAL_LINUX */
/******************************************************************************
** End Of File
******************************************************************************/

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@ -0,0 +1,179 @@
/*----------------------------------------------------------------------------*/
/* Copyright 2020,2023 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may only */
/* be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that you */
/* have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*----------------------------------------------------------------------------*/
/** \file
* Example Source abstracting component data structure and code initialization and code specific to HW used in the examples
* This file shall be present in all examples. A customer does not need to touch/modify this file. This file
* purely depends on the phNxpBuild_Lpc.h or phNxpBuild_App.h
* The phAppInit.h externs the component data structures initialized here that is in turn included by the core examples.
* The core example shall not use any other variable defined here except the RdLib component data structures(as explained above)
* The RdLib component initialization requires some user defined data and function pointers.
* These are defined in the respective examples and externed here.
*
* Keystore and Crypto initialization needs to be handled by application.
*
* $Author$
* $Revision$ (v07.10.00)
* $Date$
*
*/
/* Status header */
#include <ph_Status.h>
#include "phApp_Init.h"
#ifdef NXPBUILD__PHHAL_HW_PN5180
#include "BoardSelection.h"
/* HAL specific headers */
#include <phhalHw_Pn5180_Instr.h>
/*******************************************************************************
** Function Declarations
*******************************************************************************/
/*******************************************************************************
** Global Variable Declaration
*******************************************************************************/
phbalReg_Type_t sBalParams;
phhalHw_Pn5180_DataParams_t * pHal;
#ifdef NXPBUILD__PHHAL_HW_TARGET
/* Parameters for L3 activation during Autocoll */
extern uint8_t sens_res[2] ;
extern uint8_t nfc_id1[3] ;
extern uint8_t sel_res ;
extern uint8_t nfc_id3 ;
extern uint8_t poll_res[18] ;
#endif /* NXPBUILD__PHHAL_HW_TARGET */
/*******************************************************************************
** Function Definitions
*******************************************************************************/
/**
* This function will initialize Hal Target Config
*/
phStatus_t phApp_HALConfigAutoColl(void)
{
#ifdef NXPBUILD__PHHAL_HW_TARGET
phStatus_t wStatus;
uint8_t baDynamicUidConfig[1U] = { 1U };
uint8_t baReadEepromConfig[24U] = { 0U };
/* Read Set Listen Parameters data from EEPROM */
wStatus = phhalHw_Pn5180_Instr_ReadE2Prom(
(phhalHw_Pn5180_DataParams_t *) pHal,
PHHAL_HW_PN5180_SET_LISTEN_E2PROM_ADDR,
baReadEepromConfig,
24U
);
CHECK_SUCCESS(wStatus);
/* Verify EEPROM data and configure Set Listen Parameters if EEPROM data is not correct. */
if ((memcmp(&baReadEepromConfig[0U], sens_res, 2U) != 0x00) ||
(memcmp(&baReadEepromConfig[2U], nfc_id1, 3U) != 0x00) ||
(memcmp(&baReadEepromConfig[5U], &sel_res, 1U) != 0x00) ||
(memcmp(&baReadEepromConfig[6U], poll_res, 18U) != 0x00))
{
/* Configure Set Listen Parameters. */
wStatus = phhalHw_Pn5180_SetListenParameters(
pHal,
&sens_res[0],
&nfc_id1[0],
sel_res,
&poll_res[0],
nfc_id3
);
CHECK_SUCCESS(wStatus);
}
if (pHal->wFirmwareVer < 0x308U)
{
/* With Pn5180 FW version < 3.8, only static UID is supported. */
baDynamicUidConfig[0] = 0x00;
}
/* Read Dynamic UID configuration from EEPROM */
wStatus = phhalHw_Pn5180_Instr_ReadE2Prom(
(phhalHw_Pn5180_DataParams_t *) pHal,
PHHAL_HW_PN5180_DYN_UID_CFG_E2PROM_ADDR,
baReadEepromConfig,
1U
);
CHECK_SUCCESS(wStatus);
/* Verify EEPROM data and perform Dynamic UID configuration if EEPROM data is not correct. */
if (memcmp(baReadEepromConfig, baDynamicUidConfig, 1U) != 0x00)
{
/* Configure Dynamic UID */
wStatus = phhalHw_Pn5180_Instr_WriteE2Prom(
(phhalHw_Pn5180_DataParams_t *) pHal,
PHHAL_HW_PN5180_DYN_UID_CFG_E2PROM_ADDR,
baDynamicUidConfig,
1U
);
CHECK_SUCCESS(wStatus);
}
#endif /* NXPBUILD__PHHAL_HW_TARGET */
return PH_ERR_SUCCESS;
}
/* Configure LPCD (for PN5180) */
phStatus_t phApp_ConfigureLPCD(void)
{
/**
* PHHAL_HW_CONFIG_SET_LPCD_WAKEUPTIME_MS 0x0070U //< Used value for wakeup counter in msecs, i.e. after this amount of time IC will wakes up from standby.
* PHHAL_HW_CONFIG_LPCD_MODE 0x0071U //< Used to set options PHHAL_HW_PN5180_LPCD_MODE_DEFAULT or PHHAL_HW_PN5180_LPCD_MODE_POWERDOWN_GUARDED
* PHHAL_HW_CONFIG_LPCD_REF 0x0072U //< Used to set or get LPCD Ref
*/
phStatus_t status = PH_ERR_SUCCESS;
uint16_t wConfig = PHHAL_HW_CONFIG_LPCD_REF;
uint16_t wValue;
uint8_t bLPCD_Threshold_EEPROMAddress = 0x37;
uint8_t bLPCD_Threshold = 0x10;
wValue = PHHAL_HW_PN5180_LPCD_MODE_POWERDOWN;
wConfig = PHHAL_HW_CONFIG_LPCD_MODE;
//status = phhalHw_Pn5180_Int_LPCD_GetConfig(pHal, wConfig, &wValue);
status = phhalHw_Pn5180_Instr_WriteE2Prom(pHal,bLPCD_Threshold_EEPROMAddress, &bLPCD_Threshold, 1 );
CHECK_SUCCESS(status);
status = phhalHw_Pn5180_Int_LPCD_SetConfig(
pHal,
wConfig,
wValue
);
return status;
}
void CLIF_IRQHandler(void)
{
/* Read the interrupt status of external interrupt attached to the reader IC IRQ pin */
if (phDriver_PinRead(PHDRIVER_PIN_IRQ, PH_DRIVER_PINFUNC_INTERRUPT))
{
phDriver_PinClearIntStatus(PHDRIVER_PIN_IRQ);
/* Call application registered callback. */
if (pHal->pRFISRCallback != NULL)
{
pHal->pRFISRCallback(pHal);
}
}
}
#endif /* NXPBUILD__PHHAL_HW_PN5180 */
/******************************************************************************
** End Of File
******************************************************************************/

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@ -0,0 +1,52 @@
PROJECT(NfcrdlibEx3_NFCForum)
FILE(GLOB NfcrdlibEx3_NFCForum_Sources
*.c
src/*.c
)
include_directories(
intfs
types
)
ADD_EXECUTABLE(NfcrdlibEx3_NFCForum
${NfcrdlibEx3_NFCForum_Sources}
)
TARGET_LINK_LIBRARIES(
NfcrdlibEx3_NFCForum
phOsal
DAL
NxpRdLib_acDiscLoop
NxpRdLib_halHw
NxpRdLib_KeyStore
NxpRdLib_phTools
NxpRdLib_palFelica
NxpRdLib_palI18092mPI
NxpRdLib_palI14443p4a
NxpRdLib_palI14443p4
NxpRdLib_palI14443p4
NxpRdLib_palMifare
NxpRdLib_alFelica
NxpRdLib_alMful
NxpRdLib_alMfdf
NxpRdLib_alT1T
NxpRdLib_alTop
NxpRdLib_alMfc
NxpRdLib_lnLlcp
NxpRdLib_phTools
NxpRdLib_palI18092mT
NxpRdLib_npSnep
NxpRdLib_CryptoSym
NxpRdLib_CryptoRng
NxpRdLib_palI14443p4mC
NxpRdLib_ceT4T
NxpRdLib_palEpcUid
NxpRdLib_alMfNtag42XDna
NxpRdLib_phNfcLib
)

File diff suppressed because it is too large Load Diff

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__________________________________________________
NXPNFCRDLIB EXAMPLE : NFCRDLIBEX3_NFCFORUM
(V07.10.00)
__________________________________________________
Table of Contents
_________________
1 Document Purpose
2 Description of the NfcrdlibEx3_NFCForum
3 Restrictions on NfcrdlibEx3_NFCForum
4 Configurations of NfcrdlibEx3_NFCForum
5 Package Contents
6 Mandatory materials (not included)
7 Hardware Configuration
8 Software Configuration
9 Steps to build NfcrdlibEx3_NFCForum for LPC1769 with PN5190 using MCUXpresso
10 Steps to build NfcrdlibEx3_NFCForum for LPC1769 with PN5180 using MCUXpresso
11 Steps to build NfcrdlibEx3_NFCForum for PN7462AU using MCUXpresso
12 Steps to build NfcrdlibEx3_NFCForum for FRDM-K82F using MCUXpresso
13 Selection of Board / OSAL / Frontend (MCUXpresso)
14 Steps to follow for PI / Linux / CMake
15 Running NfcrdlibEx3_NFCForum
16 List of supported NFC Reader Boards/ICs
17 Reference Documents
1 Document Purpose
==================
This document describes the steps to be followed to execute
NfcrdlibEx3_NFCForum example as well as it's known problems and
restrictions.
2 Description of the NfcrdlibEx3_NFCForum
=========================================
- NfcrdlibEx3_NFCForum can be run with PN5180, PN5190 and PN7462AU.
(See Section-16 for supported versions).
- This example will demonstrate both Peer to Peer (P2P) and Reader
functions to detect type A, type B, type F tags, type V tags and
18000p3m3 tags.
- If any P2P device is brought in proximity then this example will go
into P2P Mode.
- When SNEP Client is enabled then this example performs SNEP PUT onto
the Peer device.
- By default the configured SNEP PUT message is "www.nxp.com".
- To demonstrate SNEP Server, the SNEP Client needs to be disabled as
no control can be provided with boards as incase of mobiles (Just
like the Touch-to-beam feature on Mobiles).
- The maximum length of SNEP PUT from peer device that can be received
by SNEP Server with this example is 1KB (1024 Bytes).
- If any NFC cards/devices (Type A, Type B or Type F) are brought in
proximity then this example will behave as a reader and will detect
and print the NFC technology type detected along with NDEF message
from the tag if present.
3 Restrictions on NfcrdlibEx3_NFCForum
======================================
- NfcrdlibEx3_NFCForum is restricted to be run on NFC Reader
Boards/ICs mentioned in Section-16.
- For PN7462AU (Section-16 Bullet-2) either of SNEP Client or SNEP
Sever can be enabled at a time (See Section-8).
- For PN7462AU (Section-16 Bullet-2) the project should be build only
with Release configuration or Debug Configuration with semi hosting
disabled.
- The APIs are intended for NXP contact-less reader ICs only, as such
the APIs are not to be ported to any technology from any other
vendor.
- NXP will not support porting to any other vendor platform.
- This software project requires NxpNfcRdLib v07.10.00 or later.
- **IMPORTANT** The default used MCU Type is K82. When executing
example on LPC1769 or PN7462AU, the MCU Type has to be changed in
the MCUXpresso IDE.
- For switching to MCU Type to PN7462AU, see Section-11
- For switching to MCU Type to LPC1769, see Section-9, Section-10 and
Section-.
4 Configurations of NfcrdlibEx3_NFCForum
========================================
- The example application is written to detect and activate one tag of
supported technologies.
- If switching between supported NFC Reader boards mention in 16, user
is adviced to include the appropriate define in file mentioned in
Section-, Bullet-, Bullet-, Bullet-.
5 Package Contents
==================
- Readme.txt
+ This readme file
- NfcrdlibEx3_NFCForum.c
+ Main example file.
- intfs/NfcrdlibEx3_NFCForum.h
+ Interfaces/Defines specific to the example
- intfs/ph_NxpBuild_App.h
+ Reader library build configuration file
- src/phApp_Helper.c
- src/phApp_PN5180_Init.c
- src/phApp_PN5190_Init.c
- src/phApp_PN7462AU_Init.c
- src/phApp_RC663_Init.c
- src/phApp_Init.c and intfs/phApp_Init.h
+ Common utility functions (common across all examples)
- src/cards.c and intfs/cards.h
+ Common utility functions and APIs for cards
- mcux/.cproject and mcux/.project
+ MCUXpresso project configuration file
- cr_startup_lpc175x_6x.c
+ Startup required to compile example for LPC1769 Micro Controller.
6 Mandatory materials (not included)
====================================
- MCUXpresso IDE. It can be downloaded from
[http://www.nxp.com/products/:MCUXpresso-IDE]
- SDK for Freedom K82 Board
([http://www.nxp.com/products/:FRDM-K82F]). The pre-build SDK can
be downloaded from
[https://mcuxpresso.nxp.com/en/license?hash=9897a8c19a6bc569c3fade7141f0f405&hash_download=true&to_vault=true]
See MCUXpresso User Manual for steps needed to install an SDK.
- Plugin to extend MCUXpresso to support PN7462AU. (Required for
MCUXpresso versions before MCUXpressoIDE_10.0.2)
- LPCXpresso LPC1769 / Freedom K82 development boards For NFC ICs
listed in Section-16 (Note: PN7462AU (Section-16 Bullet-2) does not
need any other other microcontroller).
7 Hardware Configuration
========================
Before starting this application, HW Changes may be required for the
used board. Refer to the following User Manuals / Application notes
before starting with this example.
- AN11744: PN5180 Evaluation board quick start guide
- AN11802: NFC Reader Library for Linux Installation Guidelines
- AN12550: PNEV5190B Evaluation board quick start guide
8 Software Configuration
========================
- The Software can be compiled for Cortex M3 LPC1769 micro-controller,
Cortex M4 Freedom K82 and Cortex M0 based PN7462AU from NXP.
- Since this example can be configured to run on various MCU ICs and
various NFC ICs, appropriate changes are required as mentioned in
Section-9, Section-10, Section-11 and Section-12.
- Only reader library layers mentioned in the header file
ph_NxpBuild_App.h are enabled in build for this project.
- NfcrdlibEx3_NFCForum itself can be configured for the following
items:
Listen Mode : In discovery loop listen mode, active listen or
passive listen can be selectively enabled/disabled by
defining "ACTIVE_MODE" and "PASSIVE_MODE"
respectively.
Poll Mode : In discovery loop poll mode, active poll or passive
poll can be selectively enabled/disabled by defining
"ACTIVE_MODE" and "PASSIVE_MODE" respectively.
Active Mode : To enable Active Mode. If Disabled both Active Poll
and Active Listen discovery loop configuration will
be disabled.
Passive Mode : To enable Passive Mode. If Disabled both Passive Poll
and Passive Listen discovery loop configuration will
be disabled.
SNEP Client : To enable SNEP Client functionality i.e. to perform
SNEP PUT onto remote peer device (Mobile/Board).
SNEP Server : To enable SNEP Server functionality i.e. to send SNEP
PUT Message from remote peer device (Mobile/Board).
9 Steps to build NfcrdlibEx3_NFCForum for LPC1769 with PN5190 using MCUXpresso
==============================================================================
See "PNEV5190B Evaluation board quick start guide" in AN12550 (See
Section-17, Bullet-5 below)
10 Steps to build NfcrdlibEx3_NFCForum for LPC1769 with PN5180 using MCUXpresso
===============================================================================
See "Importing provided SW example projects" in AN11908 (See
Section-17, Bullet-2 below)
11 Steps to build NfcrdlibEx3_NFCForum for PN7462AU using MCUXpresso
====================================================================
- For MCUXpresso versions before MCUXpressoIDE_10.0.2, See "Adding
PN7462AU Plugin" in UM10883. (See Section-17, Bullet-3 below)
- See "Importing provided SW example projects" in UM10883.
12 Steps to build NfcrdlibEx3_NFCForum for FRDM-K82F using MCUXpresso
=====================================================================
See "Import projects to the MCUXpresso" in AN11908. (See Section-17,
Bullet-2 below)
13 Selection of Board / OSAL / Frontend (MCUXpresso)
====================================================
For MCUXpresso, the selection of Board / OSAL / Frontend has to be
done via -D (Preprocessor defines).
1) To select the board go to "Project Properties" --> "C/C++ Build"
--> "Settings" --> "Preprocessor" --> "Defined symbols (-D)", and
define the relevant PHDRIVER_<BoardNFCCombination>_BOARD macro.
e.g. For using K82 with Pn5190 use PHDRIVER_K82F_PNEV5190B_BOARD
and for LPC1769 with PN5190 use PHDRIVER_LPC1769PN5190_BOARD. For
list of supported boards refer to
Platform\DAL\cfg\BoardSelection.h.
2) To select the osal/os type, go to "Project Properties" --> "C/C++
Build" --> "Settings" --> "Preprocessor" --> "Defined symbols
(-D)".
e.g. For using FreeRTOS use PH_OSAL_FREERTOS. For other options
refer to RTOS\phOsal\inc\phOsal_Config.h.
14 Steps to follow for PI / Linux / CMake
=========================================
The steps are described in AN11802. (See Section-17, Bullet-4 below)
15 Running NfcrdlibEx3_NFCForum
===============================
When the application is running:
1) If any NFC cards/devices (Type A, Type B or Type F) are brought in
proximity then this example will behave as a reader and will detect
and report the NFC technology types detected along with NDEF
message from the tag if present.
2) If any P2P device is brought in proximity then this example will
dynamically switch between Initiator or Target mode and performs
SNEP PUT if both Poll and Listen Modes are enabled. If SNEP Client
is disabled then Peer P2P device can perform SNEP PUT operation
which will be received by this example.
16 List of supported NFC Reader Boards/ICs
==========================================
1) PNEV5180B v2.0 Customer Evaluation Board
2) PN7462AU v2.1 Customer Evaluation Board
3) PNEV5190B v1.0 Customer Evaluation Board
17 Reference Documents
======================
1) UM10954 : PN5180 SW Quick start guide
[http://www.nxp.com/docs/en/user-guide/UM10954.pdf]
2) AN11908 : NFC Reader Library for FRDM-K82F Board Installation
guidelines
[http://www.nxp.com/docs/en/application-note/AN11908.pdf]
3) UM10883 : PN7462AU Quick Start Guide - Development Kit
[http://www.nxp.com/docs/en/user-guide/UM10883.pdf]
4) AN11802 : NFC Reader Library for Linux Installation Guidelines
[http://www.nxp.com/docs/en/application-note/AN11802.pdf]
5) AN12550 : PNEV5190B Evaluation board quick start guide
----------------------------------------------------------------------
For updates of this example, see
[http://www.nxp.com/products/:NFC-READER-LIBRARY]

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@ -0,0 +1,195 @@
/*----------------------------------------------------------------------------*/
/* Copyright 2016-2021 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may only */
/* be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that you */
/* have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*----------------------------------------------------------------------------*/
/** \file
* Example Source Header for NfcrdlibEx3_NFCForum application.
*
* $Author: NXP $
* $Revision: $ (v07.10.00)
* $Date: $
*/
#ifndef EX3_NFCFORUM_H
#define EX3_NFCFORUM_H
/**
* Reader Library Headers
*/
#include <ph_Status.h>
#if defined (NXPBUILD__PHHAL_HW_PN5180) || \
defined (NXPBUILD__PHHAL_HW_PN5190) || \
defined (NXPBUILD__PHHAL_HW_RC663) || \
defined (NXPBUILD__PHHAL_HW_PN7462AU) || \
defined (NXPBUILD__PHHAL_HW_PN7642)
#define PH_EXAMPLE3_LPCD_ENABLE /* If LPCD needs to be configured and used over HAL or over DiscLoop */
#endif
/*******************************************************************************
** Macros
*******************************************************************************/
/* Print system critical errors (with which execution can't proceed further)
* and halt the execution. */
#define ERROR_CRITICAL(...) DEBUG_PRINTF(__VA_ARGS__); while(1) { /* Nothing to do */ }
#ifdef PH_OSAL_FREERTOS
#if defined(NXPBUILD__PHHAL_HW_PN5180) || defined(NXPBUILD__PHHAL_HW_PN5190)
#define RDLIB_TASK_STACK (2200/4)
#define SNEP_SERVER_TASK_STACK (1000/4)
#define SNEP_CLIENT_TASK_STACK (1000/4)
#else
/* NXPBUILD__PHHAL_HW_PN7462AU */
#define RDLIB_TASK_STACK (1400/4)
#define SNEP_SERVER_TASK_STACK (600/4)
#define SNEP_CLIENT_TASK_STACK (500/4)
#endif
#define RDLIB_TASK_PRIO 4
#define SNEP_SERVER_TASK_PRIO 3
#define SNEP_CLIENT_TASK_PRIO 3
#elif defined PH_OSAL_LINUX
#define RDLIB_TASK_STACK 0x20000
#define RDLIB_TASK_PRIO 0
#define SNEP_SERVER_TASK_STACK 0x20000
#define SNEP_SERVER_TASK_PRIO 0
#define SNEP_CLIENT_TASK_STACK 0x20000
#define SNEP_CLIENT_TASK_PRIO 0
#endif /* PH_OSAL_FREERTOS || PH_OSAL_LINUX */
#define LISTEN_PHASE_TIME_MS 300 /**< Listen Phase TIME */
/* Enable Discovery Loop Active mode. */
#ifndef NXPBUILD__PHHAL_HW_PN76XX
#define ACTIVE_MODE
#endif /* NXPBUILD__PHHAL_HW_PN76XX */
/* Enable Discovery Loop Passive mode. */
#define PASSIVE_MODE
/* Enable initiator/reader mode polling configuration in Discovery Loop. */
#define INITIATOR_MODE
/* Enable listen mode configuration (target/card mode) in Discovery Loop. */
#define TARGET_MODE
#ifndef NXPBUILD__PHHAL_HW_PN76XX
/* Enable SNEP client PUT operation in this example. */
#define SNEP_CLIENT
/* Enable SNEP server to receive a SNEP PUT message in this example. */
#define SNEP_SERVER
#endif /* NXPBUILD__PHHAL_HW_PN76XX */
/* Un-comment following line to enable SNEP PUT of 1K text message else SNEP PUT of URI (www.nxp.com) will be enabled by default. */
/* #define NDEF_TEXT_1K */
#ifdef NDEF_TEXT_1K
/* SNEP PUT text message used in this example. */
static const uint8_t baSnepAppBuf[] = {
0xC1, /* NDEF Record Structure */
0x01, /* TYPE LENGTH */
0x00, 0x00, 0x04, 0x01, /* PAYLOAD LENGTH */
0x54, /* TYPE TEXT */
0x02, /* ID UTF8 */
0x65, 0x6E, /* LOCALE EN */
'N','X','P',' ','S','e','m','i','c','o','n','d','u','c','t','o','r','s',' ','c','r','e','a','t','e','s',' ','s','o','l'
,'u','t','i','o','n','s',' ','t','h','a','t',' ','e','n','a','b','l','e',' ','s','e','c','u','r','e',' ','c','o','n','n'
,'e','c','t','i','o','n','s',' ','f','o','r',' ','a',' ','s','m','a','r','t','e','r',' ','w','o','r','l','d','.',' ','B'
,'u','i','l','d','i','n','g',' ','o','n',' ','i','t','s',' ','e','x','p','e','r','t','i','s','e',' ','i','n',' ','H','i'
,'g','h',' ','P','e','r','f','o','r','m','a','n','c','e',' ','M','i','x','e','d',' ','S','i','g','n','a','l',' ','e','l'
,'e','c','t','r','o','n','i','c','s',',',' ','N','X','P',' ','i','s',' ','d','r','i','v','i','n','g',' ','i','n','n','o'
,'v','a','t','i','o','n',' ','i','n',' ','t','h','e',' ','a','u','t','o','m','o','t','i','v','e',',',' ','i','d','e','n'
,'t','i','f','i','c','a','t','i','o','n',' ','a','n','d',' ','m','o','b','i','l','e',' ','i','n','d','u','s','t','r','i'
,'e','s',',',' ','a','n','d',' ','i','n',' ','a','p','p','l','i','c','a','t','i','o','n',' ','a','r','e','a','s',' ','i'
,'n','c','l','u','d','i','n','g',' ','w','i','r','e','l','e','s','s',' ','i','n','f','r','a','s','t','r','u','c','t','u'
,'r','e',',',' ','l','i','g','h','t','i','n','g',',',' ','h','e','a','l','t','h','c','a','r','e',',',' ','i','n','d','u'
,'s','t','r','i','a','l',',',' ','c','o','n','s','u','m','e','r',' ','t','e','c','h',' ','a','n','d',' ','c','o','m','p'
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,'i','n','g',' ','t','h','e',' ','h','i','g','h','e','s','t',' ','s','e','c','u','r','i','t','y',' ','a','n','d',' ','r'
,'e','l','i','a','b','i','l','i','t','y',' ','(','e','.','g','.',' ','s','m','a','r','t',' ','c','a','r','d','s',',',' '
,'s','e','c','u','r','e',' ','d','o','n','g','l','e','s',',',' ','S','A','M',' ','m','o','d','u','l','e','s','.','.','.'
,')',' ','w','e',' ','p','r','o','v','i','d','e',' ','d','i','f','f','e','r','e','n','t',' ','p','l','a','t','f','o','r'
,'m','s',' ','a','c','c','o','r','d','i','n','g',' ','t','o',' ','a','p','p','l','i','c','a','t','i','o','n',' ','n','e'
,'e','d','s',' ','r','a','n','g','i','n','g',' ','f','r','o','m',' ','o','u','r',' ','w','e','l','l',' ','e','s','t','a'
,'b','l','i','s','h','e','d',' ','W','E','-','c','o','n','t','a','c','t',' ','c','o','n','t','r','o','l','l','e','r',' '
,'f','a','m','i','l','y',' ','t','o',' ','o','u','r',' ','S','m','a','r','t','M','X',' ','a','n','d',' ','S','m','a','r'
,'t','X','A',' ','d','e','v','i','c','e','s','.',' ','O','u','r',' ','M','I','F','A','R','E',' ','c','o','n','t','a','c'
,'t','l','e','s','s',' ','s','m','a','r','t',' ','c','a','r','d',' ','I','C','s',' ','p','r','o','v','i','d','e',' ','t'
,'h','e',' ','m','o','s','t',' ','a','d','v','a','n','c','e','d',' ','c','o','m','b','i','n','a','t','i','o','n',' ','o'
,'f',' ','s','e','c','u','r','i','t','y',' ','a','n','d',' ','c','o','n','v','e','n','i','e','n','c','e',' ','f','o','r'
,' ','c','o','n','t','a','c','t','l','e','s','s',' ','i','n','t','e','r','f','a','c','i','n','g',' ','i','n',' ','a','c'
,'c','o','r','d','a','n','c','e',' ','w','i','t','h',' ','t','h','e',' ','I','S','O',' ','1','4','4','4','3','A',' ','i'
,'n','t','e','r','f','a','c','e',' ','s','t','a','n','d','a','r','d','.',' ','O','u','r',' ','I','C','O','D','E',' ','a'
,'n','d',' ','U','C','O','D','E',' ','f','a','m','i','l','i','e','s',' ','o','f',' ','R','F','I','D',' ','I','C','s',' '
,'a','r','e',' ','s','p','e','c','i','f','i','c','a','l','l','y',' ','d','e','s','i','g','n','e','d',' ','f','o','r',' '
,'h','i','g','h','-','v','o','l','u','m','e',' ','s','m','a','r','t',' ','l','a','b','e','l',' ','a','p','p','l','i','c'
,'a','t','i','o','n','s','.',' ','I','n',' ','a','d','d','i','t','i','o','n',' ','o','u','r',' ','H','I','T','A','G',' '
,'f','a','m','i','l','y',' ','o','f',' ','I','C','s',',',' ','w','i','t','h',' ','a','n',' ','o','p','e','r','a','t','i'
,'n','g',' ','r','a','n','g','e',' ','o','f',' ','m','o','r','e',' ','t','h','a','n',' ','o','n','e',' ','m','e','t','e'
,'r','.'
};
#else
/* Short SNEP PUT URI message used in this example. */
static const uint8_t baSnepAppBuf[] = {
0xC1, /* NDEF record structure */
0x01, /* TYPE LENGTH */
0x00, 0x00, 0x00, 0x08, /* PAYLOAD LENGTH */
0x55, /* TYPE TEXT */
0x01, /* ID UTF8 */
'n','x','p','.','c','o','m'
};
#endif /* NDEF_TEXT_1K */
#define SNEP_PUT 0x01
#define SNEP_RECEIVED_PUT 0x80
/**
* Read NDEF message from detected tag.
* */
phStatus_t ReadNdefMessage(
uint8_t TopTagType); /* [in] Tag type from which to read NDEF */
/**
* Reader library thread. This is the main thread which starts discovery loop
* in listen mode and poll mode (one at a time) and manages switching between
* both listen and poll modes.
* */
void TReaderLibrary(
void *pDataParams); /* [in] Input parameter to thread. */
#ifdef SNEP_SERVER
/**
* SNEP Server Task. This Task registers SNEP Server and waits for Remote Client
* to PUT SNEP Message.
* Refer phnpSnep.h for more info.
* APIs which does PAL or HAL exchange should not be called from application
* thread.
*/
void TSNEPServer(
void * pLlcp /* [in] Input parameter to thread. */
);
#endif /* SNEP_SERVER */
#ifdef SNEP_CLIENT
/**
* SNEP Client Task. This Task registers SNEP Client and waits till Remote Server
* accepts connection and then perform SNEP PUT action.
* Refer phnpSnep.h for more info.
* APIs which does PAL or HAL exchange should not be called from application
* thread.
*/
void TSNEPClient(
void * pLlcp /* [in] Input parameter to thread. */
);
#endif /* SNEP_CLIENT */
#endif /* EX3_NFCFORUM_H */

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/*
* Copyright (c), NXP Semiconductors Gratkorn / Austria
*
* (C)NXP Semiconductors
* All rights are reserved. Reproduction in whole or in part is
* prohibited without the written consent of the copyright owner.
* NXP reserves the right to make changes without notice at any time.
* NXP makes no warranty, expressed, implied or statutory, including but
* not limited to any implied warranty of merchantability or fitness for any
*particular purpose, or that the use will not infringe any third party patent,
* copyright or trademark. NXP must not be liable for any loss or damage
* arising from its use.
*/
/** \file
* Cards identification.
* $Author: Purnank G (ing05193) $
* $Revision: 5458 $ (v07.10.00)
* $Date: 2016-07-06 14:59:09 +0530 (Wed, 06 Jul 2016) $
*
* History:
*
*
*/
#ifndef CARDS_H
#define CARDS_H
#include <ph_Status.h>
/*
* SAK codes
*/
#define sak_ul 0x00
#define sak_ulc 0x00
#define sak_mini 0x09
#define sak_mfc_1k 0x08
#define sak_mfc_4k 0x18
#define sak_mfp_2k_sl1 0x08
#define sak_mfp_4k_sl1 0x18
#define sak_mfp_2k_sl2 0x10
#define sak_mfp_4k_sl2 0x11
#define sak_mfp_2k_sl3 0x20
#define sak_mfp_4k_sl3 0x20
#define sak_desfire 0x20
#define sak_jcop 0x28
#define sak_layer4 0x20
/*
* ATQ codes
*/
#define atqa_ul 0x4400
#define atqa_ulc 0x4400
#define atqa_mfc 0x0200
#define atqa_mfp_s 0x0400
#define atqa_mfp_x 0x4200
#define atqa_desfire 0x4403
#define atqa_jcop 0x0400
#define atqa_mini 0x0400
#define atqa_nPA 0x0800
/*
* MIFARE cards
*/
#define mifare_ultralight 0x01
#define mifare_ultralight_c 0x02
#define mifare_classic 0x03
#define mifare_classic_1k 0x04
#define mifare_classic_4k 0x05
#define mifare_plus 0x06
#define mifare_plus_2k_sl1 0x07
#define mifare_plus_4k_sl1 0x08
#define mifare_plus_2k_sl2 0x09
#define mifare_plus_4k_sl2 0x0A
#define mifare_plus_2k_sl3 0x0B
#define mifare_plus_4k_sl3 0x0C
#define mifare_desfire 0x0D
#define jcop 0x0F
#define mifare_mini 0x10
#define nPA 0x11
/*
* Exported functions
*/
uint8_t DetectClassic(uint8_t *pAtqa, uint8_t *bSak);
uint32_t DetectMifare(uint8_t *pAtqa, uint8_t *bSak);
void DumpBuffer(uint8_t *pBuffer, uint32_t dwBufferLength);
#endif /* CARDS_H */

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/*----------------------------------------------------------------------------*/
/* Copyright 2016-2023 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may only */
/* be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that you */
/* have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*----------------------------------------------------------------------------*/
/** \file
* Example Source abstracting component header specific to HW used in the examples
* This file shall be present in all examples. A customer does not need to touch/modify this file. This file
* purely depends on the phNxpBuild_Lpc.h or phNxpBuild_App.h
* The phAppInit.h externs the component data structures initialized here that is in turn included by the core examples.
* The core example shall not use any other variable defined here except the RdLib component data structures(as explained above)
* The RdLib component initialization requires some user defined data and function pointers.
* These are defined in the respective examples and externed here.
*
* Keystore and Crypto initialization needs to be handled by application.
*
* $Author$
* $Revision$ (v07.10.00)
* $Date$
*
*/
#ifndef PHAPP_INIT_H
#define PHAPP_INIT_H
/* Status header */
#include <ph_Status.h>
/* Driver Header */
#include <phDriver.h>
/* NFCLIB Header */
#include <phNfcLib.h>
/* LLCP header */
#include <phlnLlcp.h>
/* SNEP header */
#include <phnpSnep.h>
/* Check for K82 controller based boards. */
#if defined(PHDRIVER_FRDM_K82FPN5180_BOARD) || \
defined(PHDRIVER_FRDM_K82FRC663_BOARD) || \
defined(PHDRIVER_K82F_PNEV5190B_BOARD)
#define PHDRIVER_KINETIS_K82
#endif
/* Check for LPC1769 controller based boards. */
#if defined(PHDRIVER_LPC1769PN5180_BOARD) || \
defined(PHDRIVER_LPC1769RC663_BOARD) || \
defined(PHDRIVER_LPC1769PN5190_BOARD)
#define PHDRIVER_LPC1769
#endif
#if defined(PHDRIVER_PIPN5180_BOARD) || \
defined(PHDRIVER_PIRC663_BOARD) || \
defined(PHDRIVER_PIPN5190_BOARD)
#include <phDriver_Linux_Int.h>
#endif
#ifdef PHDRIVER_KINETIS_K82
# include <fsl_debug_console.h>
# include <stdio.h>
#endif
#if !defined(__PN76XX__)
#ifdef DEBUG
#ifdef PHDRIVER_KINETIS_K82
#if SDK_DEBUGCONSOLE==1
#define DEBUG_PRINTF DbgConsole_Printf
#else
#define DEBUG_PRINTF(...) printf(__VA_ARGS__);
#endif
#else /* PHDRIVER_KINETIS_K82 */
#include <stdio.h>
#define DEBUG_PRINTF(...) printf(__VA_ARGS__); fflush(stdout)
#endif /* PHDRIVER_KINETIS_K82 */
#else /* DEBUG */
#define DEBUG_PRINTF(...)
#define DEBUG_SCANF(...)
#endif /* DEBUG */
#else /* __PN76XX__ */
#if (SEGGER_RTT_ENABLE == 1)
#include "SEGGER_RTT.h"
#define DEBUG_PRINTF(...) SEGGER_RTT_printf(0, __VA_ARGS__);
#define DEBUG_SCANF(Input , data) *data = (SEGGER_RTT_WaitKey() - 0x30); SEGGER_RTT_WaitKey()
#else
#if DEBUG
#include <fsl_debug_console.h>
#define DEBUG_PRINTF(...) PRINTF(__VA_ARGS__);
#define DEBUG_SCANF(...) SCANF(__VA_ARGS__);while ((GETCHAR()) != '\n');
#define DEBUG_GETCHAR GETCHAR
#else
#define DEBUG_PRINTF(...)
#define DEBUG_SCANF(...)
#endif /* DEBUG */
#endif /* (SEGGER_RTT_ENABLE == 1) */
#endif /* __PN76XX__ */
/*******************************************************************************
** Global Variable Declaration
*******************************************************************************/
#define PH_NFCRDLIB_EXAMPLE_LPCD_GUARDTIME 100 /* LPCD Guard time(T4) in milli-seconds configured by application for Rc663. */
#define PH_NFCRDLIB_EXAMPLE_LPCD_RFON_TIME 56 /* LPCD RFON time(T3) in micro-seconds configured by application for Rc663. */
/* HAL & BAL declarations */
#ifdef PH_PLATFORM_HAS_ICFRONTEND
extern phbalReg_Type_t sBalParams;
#endif /* PH_PLATFORM_HAS_ICFRONTEND */
#ifdef NXPBUILD__PHLN_LLCP_SW
extern phlnLlcp_Sw_DataParams_t slnLlcp; /* LLCP component */
#endif /* NXPBUILD__PHLN_LLCP_SW */
#ifdef NXPBUILD__PHHAL_HW_PN5180
extern phhalHw_Pn5180_DataParams_t * pHal;
#endif /* NXPBUILD__PHHAL_HW_PN5180 */
#ifdef NXPBUILD__PHHAL_HW_PN5190
extern phhalHw_Pn5190_DataParams_t * pHal;
#endif /* NXPBUILD__PHHAL_HW_PN5190 */
#ifdef NXPBUILD__PHHAL_HW_RC663
extern phhalHw_Rc663_DataParams_t * pHal;
#endif /* NXPBUILD__PHHAL_HW_RC663 */
#ifdef NXPBUILD__PHHAL_HW_PN7462AU
extern phhalHw_PN7462AU_DataParams_t * pHal;
#endif /* NXPBUILD__PHHAL_HW_PN7462AU */
#ifdef NXPBUILD__PHHAL_HW_PN76XX
extern phhalHw_Pn76xx_DataParams_t * pHal;
#endif /* NXPBUILD__PHHAL_HW_PN76XX */
/**************************************************Prints if error is detected**************************************************************/
/* Enable(1) / Disable(0) printing error/info */
#define DETECT_ERROR 0
#if DETECT_ERROR
#define DEBUG_ERROR_PRINT(x) x
#define PRINT_INFO(...) DEBUG_PRINTF(__VA_ARGS__)
#else
#define DEBUG_ERROR_PRINT(x)
#define PRINT_INFO(...)
#endif
#define CHECK_STATUS(x) \
if ((x) != PH_ERR_SUCCESS) \
{ \
DEBUG_PRINTF("Line: %d Error - (0x%04X) has occurred : 0xCCEE CC-Component ID, EE-Error code. Refer-ph_Status.h\n", __LINE__, (x)); \
}
/* prints if error is detected */
#define CHECK_SUCCESS(x) \
if ((x) != PH_ERR_SUCCESS) \
{ \
DEBUG_PRINTF("\nLine: %d Error - (0x%04X) has occurred : 0xCCEE CC-Component ID, EE-Error code. Refer-ph_Status.h\n ", __LINE__, (x)); \
return (x); \
}
/* prints if error is detected */
#define CHECK_NFCLIB_STATUS(x) \
if ((x) != PH_NFCLIB_STATUS_SUCCESS) \
{ \
DEBUG_PRINTF("\nLine: %d Error - (0x%04X) has occurred in NFCLIB\n ", __LINE__, (x)); \
}
/*********************************************************************************************************************************************/
/*******************************************************************************
** Function Declarations
*******************************************************************************/
extern void phApp_CPU_Init(void);
extern phStatus_t phApp_Comp_Init(void * pDiscLoopParams);
extern phStatus_t phApp_HALConfigAutoColl(void);
extern phStatus_t phApp_ConfigureLPCD(void);
extern void phApp_PrintTagInfo(phacDiscLoop_Sw_DataParams_t *pDataParams, uint16_t wNumberOfTags, uint16_t wTagsDetected);
extern void phApp_PrintTech(uint8_t TechType);
extern void phApp_Print_Buff(uint8_t *pBuff, uint8_t num);
extern void PrintErrorInfo(phStatus_t wStatus);
extern phStatus_t phApp_Configure_IRQ();
#ifdef PH_PLATFORM_HAS_ICFRONTEND
extern void CLIF_IRQHandler(void);
#endif /* PH_PLATFORM_HAS_ICFRONTEND */
#endif /* PHAPP_INIT_H */

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/*----------------------------------------------------------------------------*/
/* Copyright 2016-2023 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may only */
/* be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that you */
/* have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*----------------------------------------------------------------------------*/
/** \file
* Application specific selection of Reader Library Components
*
* $Author$
* $Revision$ (v07.10.00)
* $Date$
*
*/
#ifndef PH_NXPBUILD_APP_H_INC
#define PH_NXPBUILD_APP_H_INC
/** \defgroup ph_NxpBuild NXP Build
* \brief Controls the Inclusion of required components, Inclusion SRC/DATA within components and the Build Dependencies between the components
* @{
*/
/* NXPBUILD_DELETE: included code lines should be always removed from code */
/* NXP BUILD DEFINES */
/* use #define to include components */
/* comment out #define to exclude components */
/* DEBUG build mode */
/*#define NXPBUILD__PH_DEBUG*/ /**< DEBUG build definition */
//#define NXPRDLIB_REM_GEN_INTFS
/*********************************************************************************************************************************************************************************/
#if defined(__PN74XXXX__) || defined (__PN73XXXX__)
#define NXPBUILD__PHHAL_HW_PN7462AU /**< NFC Controller PN7462AU HAL */
#endif
#ifdef __PN76XX__
#ifdef __PN7642__
#define NXPBUILD__PHHAL_HW_PN7642 /**< NFC Controller PN7642 HAL */
#elif __PN7640__
#define NXPBUILD__PHHAL_HW_PN7640 /**< NFC Controller PN7640 HAL */
#else
#error " PN76 platform definition (__PN7642__ or __PN7640__) missing !!! "
#endif
#if defined(__PN7642__) || defined(__PN7640__)
#define NXPBUILD__PHHAL_HW_PN76XX /**< NFC Controller PN76XX HAL */
#endif
#endif /* __PN76XX__ */
#if defined(PHDRIVER_LPC1769PN5180_BOARD) \
|| defined(PHDRIVER_FRDM_K82FPN5180_BOARD)
# define NXPBUILD__PHHAL_HW_PN5180
#endif
#if defined(PHDRIVER_LPC1769PN5190_BOARD) \
|| defined(PHDRIVER_K82F_PNEV5190B_BOARD)
# define NXPBUILD__PHHAL_HW_PN5190
#endif
#if defined(PHDRIVER_LPC1769RC663_BOARD) \
|| defined(PHDRIVER_FRDM_K82FRC663_BOARD)
/* WARNING: This example is not supported for RC663 */
# define NXPBUILD__PHHAL_HW_RC663
#endif
#if defined(NXPBUILD__PHHAL_HW_PN5180) || \
defined(NXPBUILD__PHHAL_HW_PN5190) || \
defined(NXPBUILD__PHHAL_HW_PN76XX) || \
defined(NXPBUILD__PHHAL_HW_PN7462AU)
#define NXPBUILD__PHHAL_HW_TARGET /**< Dependency checking if target mode macros should be enabled */
#endif
/*********************************************************************************************************************************************************************************/
#define NXPBUILD__PHPAL_I14443P3A_SW /**< PAL ISO 14443-3A SW Component is included. */
#define NXPBUILD__PHPAL_I14443P3B_SW /**< PAL ISO 14443-3B SW Component is included. */
#define NXPBUILD__PHPAL_I14443P4A_SW /**< PAL ISO 14443-4A SW Component is included. */
#define NXPBUILD__PHPAL_I14443P4_SW /**< PAL ISO 14443-4 SW Component is included. */
#define NXPBUILD__PHPAL_MIFARE_SW /**< PAL MIFARE SW Component is included */
//#define NXPBUILD__PHPAL_MIFARE_STUB /**< PAL MIFARE STUB Component is included */
#define NXPBUILD__PHPAL_FELICA_SW /**< PAL Felica SW Component is included. */
#define NXPBUILD__PHPAL_SLI15693_SW /**< PAL SLI 15693 Component is included. */
#ifndef NXPBUILD__PHHAL_HW_PN7640
#define NXPBUILD__PHPAL_I18000P3M3_SW /**< PAL ISO 18000p3m3 Component is included. */
#endif /* NXPBUILD__PHHAL_HW_PN7640 */
#ifdef NXPBUILD__PHHAL_HW_RC663 /**< If FE HAL is RC663, then include EPC UID PAL as required, otherwise exclude. */
#define NXPBUILD__PHPAL_EPCUID_SW /**< PAL EPC UID SW Component is included. */
#endif
#ifndef NXPBUILD__PHHAL_HW_PN76XX
#define NXPBUILD__PHPAL_I18092MPI_SW /**< PAL ISO18092 (P2P) SW Component is included. */
#endif /* NXPBUILD__PHHAL_HW_PN76XX */
#ifndef NXPBUILD__PHHAL_HW_RC663 /**< If FE HAL is RC663, then exclude ISO14443 Card Mode PAL & ISO18092 Target Mode PAL, otherwise include as required. */
// #define NXPBUILD__PHPAL_I14443P4MC_SW /**< PAL ISO 14443-4 Card Mode SW Component is included. */
#ifndef NXPBUILD__PHHAL_HW_PN76XX
#define NXPBUILD__PHPAL_I18092MT_SW /**< PAL ISO 18092 Target Mode SW Component is included. */
#endif /* NXPBUILD__PHHAL_HW_PN76XX */
#endif /* NXPBUILD__PHHAL_HW_RC663 */
/*********************************************************************************************************************************************************************************/
#define NXPBUILD__PHAC_DISCLOOP_SW /**< Discovery Loop Activity SW Component is included. */
#ifdef NXPBUILD__PHAC_DISCLOOP_SW /**< If DiscLoop SW Component is included, macros( & it's dependencies) to include/exclude SRC/DATA within Discloop is defined. */
#if defined (NXPBUILD__PHHAL_HW_PN5180) || \
defined (NXPBUILD__PHHAL_HW_PN5190) || \
defined (NXPBUILD__PHHAL_HW_RC663) || \
defined (NXPBUILD__PHHAL_HW_PN7462AU) || \
defined (NXPBUILD__PHHAL_HW_PN7642)
#define NXPBUILD__PHAC_DISCLOOP_LPCD /**< SRC to enable LPCD is included. */
#endif
#ifdef NXPBUILD__PHPAL_I14443P3A_SW
#define NXPBUILD__PHAC_DISCLOOP_TYPEA_I3P3_TAGS /**< SRC/DATA to Detect/CollRes/Activate cards such as MFC, MFUL, MFP SL1 etc is included. */
#define NXPBUILD__PHAC_DISCLOOP_TYPEA_JEWEL_TAGS /**< SRC/DATA to Detect cards such as NFC Forum T1T, Topaz/Jewel is included. */
#if defined(NXPBUILD__PHPAL_I14443P4A_SW) && defined(NXPBUILD__PHPAL_I14443P4_SW)
#define NXPBUILD__PHAC_DISCLOOP_TYPEA_I3P4_TAGS /**< SRC/DATA to Detect cards such as MFDF, MFP, T4AT NFC Forum Tag or Type A EMVCo is included. */
#endif
#endif /* NXPBUILD__PHPAL_I14443P3A_SW */
#if defined(NXPBUILD__PHPAL_I14443P3A_SW) && defined(NXPBUILD__PHPAL_I18092MPI_SW)
#define NXPBUILD__PHAC_DISCLOOP_TYPEA_P2P_TAGS /**< SRC/DATA to Detect Peer Passive Type A P2P Target mode devices is included. */
#endif
#ifdef NXPBUILD__PHPAL_I18092MPI_SW
#define NXPBUILD__PHAC_DISCLOOP_TYPEA_P2P_ACTIVE /**< SRC/DATA to Detect Peer Active Type A P2P Target mode devices is included. */
#define NXPBUILD__PHAC_DISCLOOP_TYPEF212_P2P_ACTIVE/**< SRC/DATA to Detect Peer Active Type F212 P2P Target mode devices is included. */
#define NXPBUILD__PHAC_DISCLOOP_TYPEF424_P2P_ACTIVE/**< SRC/DATA to Detect Peer Active Type F424 P2P Target mode devices is included. */
#endif /* NXPBUILD__PHPAL_I18092MPI_SW */
#ifdef NXPBUILD__PHPAL_FELICA_SW
#define NXPBUILD__PHAC_DISCLOOP_FELICA_TAGS /**< SRC/DATA to Detect FeliCa Cards is included. */
#ifdef NXPBUILD__PHPAL_I18092MPI_SW
#define NXPBUILD__PHAC_DISCLOOP_TYPEF_P2P_TAGS /**< SRC/DATA to Detect Peer Passive Type F P2P Target mode devices is included. */
#endif /* NXPBUILD__PHPAL_I18092MPI_SW */
#endif /* NXPBUILD__PHPAL_FELICA_SW */
#ifdef NXPBUILD__PHPAL_I14443P3B_SW
#define NXPBUILD__PHAC_DISCLOOP_TYPEB_I3P3B_TAGS /**< SRC/DATA to Detect Type B Cards that operate at Layer3 level is included */
#ifdef NXPBUILD__PHPAL_I14443P4_SW
#define NXPBUILD__PHAC_DISCLOOP_TYPEB_I3P4B_TAGS /**< SRC/DATA to Detect Type B Cards such as NFC Forum Type 4 Tags, EMVCo Type B Cards etc is included */
#endif /* NXPBUILD__PHPAL_I14443P4_SW */
#endif /* NXPBUILD__PHPAL_I14443P3B_SW */
#ifdef NXPBUILD__PHPAL_SLI15693_SW
#define NXPBUILD__PHAC_DISCLOOP_TYPEV_TAGS /**< SRC/DATA to Detect Type V Cards such as ICODE SLI/SLIX/SLI2/Tesa Cards is included*/
#endif /* NXPBUILD__PHPAL_SLI15693_SW */
#ifdef NXPBUILD__PHPAL_I18000P3M3_SW
#define NXPBUILD__PHAC_DISCLOOP_I18000P3M3_TAGS /**< SRC/DATA to Detect ICODE ILT Cards such as SMARTRAC StackIt Cards is included*/
#endif /* NXPBUILD__PHPAL_I18000P3M3_SW */
#ifndef NXPBUILD__PHHAL_HW_RC663 /**< If FE HAL is RC663, target mode is not supported at all, hence exclude those SRC, otherwise include as required */
#ifdef NXPBUILD__PHHAL_HW_TARGET
#define NXPBUILD__PHAC_DISCLOOP_TYPEA_TARGET_PASSIVE /**< SRC to Initialize Type A passive listen config and subsequently call HAL AutoColl is included. */
#ifndef NXPBUILD__PHHAL_HW_PN76XX
#define NXPBUILD__PHAC_DISCLOOP_TYPEA_TARGET_ACTIVE /**< SRC to Initialize Type A active listen config and subsequently call HAL AutoColl is included. */
#define NXPBUILD__PHAC_DISCLOOP_TYPEF212_TARGET_PASSIVE/**< SRC to Initialize Type F212 passive listen config and subsequently call HAL AutoColl is included. */
#define NXPBUILD__PHAC_DISCLOOP_TYPEF212_TARGET_ACTIVE /**< SRC to Initialize Type F212 active listen config and subsequently call HAL AutoColl is included. */
#define NXPBUILD__PHAC_DISCLOOP_TYPEF424_TARGET_PASSIVE/**< SRC to Initialize Type F424 passive listen config and subsequently call HAL AutoColl is included. */
#define NXPBUILD__PHAC_DISCLOOP_TYPEF424_TARGET_ACTIVE /**< SRC to Initialize Type F424 active listen config and subsequently call HAL AutoColl is included. */
#endif /* NXPBUILD__PHHAL_HW_PN76XX */
#endif /* NXPBUILD__PHHAL_HW_TARGET */
#endif
#endif /* NXPBUILD__PHAC_DISCLOOP_SW */
/*********************************************************************************************************************************************************************************/
#define NXPBUILD__PHNFCLIB /**< Simplified API Interface, If enabling this the entry point should be this component in the application */
/*********************************************************************************************************************************************************************************/
//#define NXPBUILD__PH_CIDMANAGER_SW /**< CID Manager SW Component is included. */
//#define NXPBUILD__PH_KEYSTORE_SW /**< SW KeyStore Component is included. */
#if defined(NXPBUILD__PHHAL_HW_RC663) && !defined(NXPBUILD__PH_KEYSTORE_SW)
#define NXPBUILD__PH_KEYSTORE_RC663 /**< RC663 KeyStore Component is included. */
#endif
//#define NXPBUILD__PH_NDA_MFDF /**< MIFARE DESFire contactless IC */
//#define NXPBUILD__PH_CRYPTOSYM_SW /**< Crypto Symbols SW Component is included. */
//#define NXPBUILD__PH_CRYPTORNG_SW /**< Crypto RNG SW Component is included. */
/*********************************************************************************************************************************************************************************/
#ifdef NXPBUILD__PHPAL_FELICA_SW
#define NXPBUILD__PHAL_FELICA_SW /**< AL FeliCa SW Component is included */
#endif /* NXPBUILD__PHPAL_FELICA_SW */
#ifdef NXPBUILD__PHPAL_MIFARE_SW
#if defined(NXPBUILD__PH_KEYSTORE_SW) || defined(NXPBUILD__PH_KEYSTORE_RC663)
#define NXPBUILD__PHAL_MFC_SW /**< AL MIFARE Classic contactless IC SW Component is included */
#endif
#define NXPBUILD__PHAL_MFUL_SW /**< AL Mifare Ultrlight SW Component is included */
#define NXPBUILD__PHAL_MFDF_SW /**< AL Mifare DesFire SW Component is included */
//#define NXPBUILD__PHAL_MFNTAG42XDNA_SW /**< AL MIFARE Prime Ntag42XDna contactless IC SW Component is included */
#endif /* NXPBUILD__PHPAL_MIFARE_SW */
#ifdef NXPBUILD__PHPAL_I14443P3A_SW
#define NXPBUILD__PHAL_T1T_SW /**< AL Type T1 Tag SW Component is included */
#endif /* NXPBUILD__PHPAL_I14443P3A_SW */
#ifdef NXPBUILD__PHPAL_SLI15693_SW
#define NXPBUILD__PHAL_ICODE_SW /**< AL ICODE SW COMPONENT is included */
#endif /* NXPBUILD__PHPAL_SLI15693_SW */
#ifdef NXPBUILD__PHAL_T1T_SW
#define NXPBUILD__PHAL_TOP_T1T_SW /**< AL TOP T1T Tag SW Component is included */
#endif /* NXPBUILD__PHAL_T1T_SW */
#ifdef NXPBUILD__PHAL_MFUL_SW
#define NXPBUILD__PHAL_TOP_T2T_SW /**< AL TOP T2T Tag SW Component is included */
#endif /* NXPBUILD__PHAL_MFUL_SW*/
#ifdef NXPBUILD__PHAL_FELICA_SW
#define NXPBUILD__PHAL_TOP_T3T_SW /**< AL TOP T3T Tag SW Component is included */
#endif /* NXPBUILD__PHAL_FELICA_SW*/
#ifdef NXPBUILD__PHPAL_MIFARE_SW
#define NXPBUILD__PHAL_TOP_T4T_SW /**< AL TOP T4T Tag SW Component is included */
#endif /* NXPBUILD__PHPAL_MIFARE_SW*/
#ifdef NXPBUILD__PHAL_ICODE_SW
#define NXPBUILD__PHAL_TOP_T5T_SW /**< AL TOP T5T Tag SW Component is included */
#endif /* NXPBUILD__PHAL_ICODE_SW*/
#ifdef NXPBUILD__PHPAL_I14443P3A_SW
#define NXPBUILD__PHAL_TOP_MFC_SW /**< AL TOP MFC Tag SW Component is included */
#endif /* NXPBUILD__PHPAL_I14443P3A_SW*/
#if defined(NXPBUILD__PHAL_TOP_T1T_SW) || \
defined(NXPBUILD__PHAL_TOP_T2T_SW) || \
defined(NXPBUILD__PHAL_TOP_T3T_SW) || \
defined(NXPBUILD__PHAL_TOP_T4T_SW) || \
defined(NXPBUILD__PHAL_TOP_T5T_SW) || \
defined(NXPBUILD__PHAL_TOP_MFC_SW)
#define NXPBUILD__PHAL_TOP_SW /**< AL for TagOps Mapping SW Component is included.Required for NDEF operations */
#endif
#ifdef NXPBUILD__PHPAL_I18000P3M3_SW
#define NXPBUILD__PHAL_I18000P3M3_SW /**< AL ISO18000p3m3 SW Component is included */
#endif /* NXPBUILD__PHPAL_I18000P3M3_SW */
#ifdef NXPBUILD__PHPAL_I14443P4MC_SW
#if !defined(PH_OSAL_NULLOS)
#define NXPBUILD__PHCE_T4T_SW /**< AL HCE T2AT SW Component is included */
//#define NXPBUILD__PHCE_T4T_PROPRIETARY /**< SRC to handle HCE T4AT Proprietary Commands is included */
/*#define NXPBUILD__PHCE_T4T_EXT_NDEF */ /**< SRC to handle Extended NDEF Support as per T4T spec 3.0 is included */
#endif
#endif /* NXPBUILD__PHPAL_I14443P4MC_SW */
/* LLCP Components */
#if defined(NXPBUILD__PHPAL_I18092MPI_SW) || defined(NXPBUILD__PHPAL_I18092MT_SW)
#if !defined(PH_OSAL_NULLOS)
#define NXPBUILD__PHLN_LLCP_SW /**< Link LLCP SW Component is included */
#endif
#endif
/* SNEP components */
#ifdef NXPBUILD__PHLN_LLCP_SW
#define NXPBUILD__PHNP_SNEP_SW /**< Protocol SNEP SW Component is included */
#endif /* NXPBUILD__PHLN_LLCP_SW */
/* Enable/disable Debugging */
/*#define NXPBUILD__PH_DEBUG*/ /**< TODO: To be checked if required */
/** @}
* end of ph_NxpBuild
*/
#endif /* PH_NXPBUILD_APP_H_INC */

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</storageModule>
<storageModule moduleId="com.nxp.mcuxpresso.core.datamodels">
<sdkName>SDK_2.x_FRDM-K82F</sdkName>
<sdkVersion>2.6.0</sdkVersion>
</storageModule>
</cproject>

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@ -0,0 +1,89 @@
<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>NfcrdlibEx3_NFCForum_mcux</name>
<comment></comment>
<projects>
<project>FreeRTOS</project>
<project>lpc_board_nxp_lpcxpresso_1769</project>
<project>lpc_chip_175x_6x</project>
<project>NxpNfcRdLib</project>
<project>SDK_2.x_FRDM-K82F</project>
</projects>
<buildSpec>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
<triggers>full,incremental,</triggers>
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</natures>
<linkedResources>
<link>
<name>DAL</name>
<type>2</type>
<locationURI>PARENT-3-PROJECT_LOC/Platform/DAL</locationURI>
</link>
<link>
<name>FreeRTOS</name>
<type>2</type>
<locationURI>PARENT-3-PROJECT_LOC/RTOS/FreeRTOS</locationURI>
</link>
<link>
<name>NfcrdlibEx3_NFCForum.c</name>
<type>1</type>
<locationURI>PARENT-1-PROJECT_LOC/NfcrdlibEx3_NFCForum.c</locationURI>
</link>
<link>
<name>NxpNfcRdLib</name>
<type>2</type>
<locationURI>PARENT-3-PROJECT_LOC/NxpNfcRdLib</locationURI>
</link>
<link>
<name>PN7462AU</name>
<type>2</type>
<locationURI>PARENT-3-PROJECT_LOC/Platform/PN7462AU</locationURI>
</link>
<link>
<name>Readme.txt</name>
<type>1</type>
<locationURI>PARENT-1-PROJECT_LOC/Readme.txt</locationURI>
</link>
<link>
<name>intfs</name>
<type>2</type>
<locationURI>PARENT-1-PROJECT_LOC/intfs</locationURI>
</link>
<link>
<name>phOsal</name>
<type>2</type>
<locationURI>virtual:/virtual</locationURI>
</link>
<link>
<name>src</name>
<type>2</type>
<locationURI>PARENT-1-PROJECT_LOC/src</locationURI>
</link>
<link>
<name>phOsal/inc</name>
<type>2</type>
<locationURI>PARENT-3-PROJECT_LOC/RTOS/phOsal/inc</locationURI>
</link>
<link>
<name>phOsal/src</name>
<type>2</type>
<locationURI>PARENT-3-PROJECT_LOC/RTOS/phOsal/src</locationURI>
</link>
</linkedResources>
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@ -0,0 +1,493 @@
//*****************************************************************************
// LPC175x_6x Microcontroller Startup code for use with LPCXpresso IDE
//
// Version : 140114
//*****************************************************************************
//
// Copyright(C) NXP Semiconductors, 2014
// All rights reserved.
//
// Software that is described herein is for illustrative purposes only
// which provides customers with programming information regarding the
// LPC products. This software is supplied "AS IS" without any warranties of
// any kind, and NXP Semiconductors and its licensor disclaim any and
// all warranties, express or implied, including all implied warranties of
// merchantability, fitness for a particular purpose and non-infringement of
// intellectual property rights. NXP Semiconductors assumes no responsibility
// or liability for the use of the software, conveys no license or rights under any
// patent, copyright, mask work right, or any other intellectual property rights in
// or to any products. NXP Semiconductors reserves the right to make changes
// in the software without notification. NXP Semiconductors also makes no
// representation or warranty that such application will be suitable for the
// specified use without further testing or modification.
//
// Permission to use, copy, modify, and distribute this software and its
// documentation is hereby granted, under NXP Semiconductors' and its
// licensor's relevant copyrights in the software, without fee, provided that it
// is used in conjunction with NXP Semiconductors microcontrollers. This
// copyright, permission, and disclaimer notice must appear in all copies of
// this code.
//*****************************************************************************
#include <ph_Status.h>
#include <cr_section_macros.h>
#include <NXP/crp.h>
#ifdef DEBUG
# define VT_IMAGE_LENGTH 0x76706b64U
#else /* DEBUG */
# define VT_IMAGE_LENGTH 0xFFFFFFFFU
#endif /* DEBUG */
#if defined (__cplusplus)
#ifdef __REDLIB__
#error Redlib does not support C++
#else
//*****************************************************************************
//
// The entry point for the C++ library startup
//
//*****************************************************************************
extern "C" {
extern void __libc_init_array(void);
}
#endif
#endif
#define WEAK __attribute__ ((weak))
#define ALIAS(f) __attribute__ ((weak, alias (#f)))
__CRP const unsigned int CRP_WORD = CRP_NO_CRP;
//*****************************************************************************
#if defined (__cplusplus)
extern "C" {
#endif
//*****************************************************************************
#if defined (__USE_CMSIS) || defined (__USE_LPCOPEN)
// Declaration of external SystemInit function
void SystemInit(void);
extern void Board_SystemInit(void);
extern void Chip_SystemInit(void);
extern void SystemCoreClockUpdate(void);
#endif
//*****************************************************************************
//
// Forward declaration of the default handlers. These are aliased.
// When the application defines a handler (with the same name), this will
// automatically take precedence over these weak definitions
//
//*****************************************************************************
void ResetISR(void);
WEAK void NMI_Handler(void);
//WEAK void HardFault_Handler(void);
WEAK void MemManage_Handler(void);
WEAK void BusFault_Handler(void);
WEAK void UsageFault_Handler(void);
WEAK void SVC_Handler(void);
WEAK void DebugMon_Handler(void);
WEAK void PendSV_Handler(void);
WEAK void SysTick_Handler(void);
WEAK void IntDefaultHandler(void);
/* The prototype shows it is a naked function - in effect this is just an
assembly function. */
void HardFault_Handler( void ) __attribute__( ( naked ) );
//*****************************************************************************
//
// Forward declaration of the specific IRQ handlers. These are aliased
// to the IntDefaultHandler, which is a 'forever' loop. When the application
// defines a handler (with the same name), this will automatically take
// precedence over these weak definitions
//
//*****************************************************************************
void WDT_IRQHandler(void) ALIAS(IntDefaultHandler);
void TIMER0_IRQHandler(void) ALIAS(IntDefaultHandler);
void TIMER1_IRQHandler(void) ALIAS(IntDefaultHandler);
void TIMER2_IRQHandler(void) ALIAS(IntDefaultHandler);
void TIMER3_IRQHandler(void) ALIAS(IntDefaultHandler);
void UART0_IRQHandler(void) ALIAS(IntDefaultHandler);
void UART1_IRQHandler(void) ALIAS(IntDefaultHandler);
void UART2_IRQHandler(void) ALIAS(IntDefaultHandler);
void UART3_IRQHandler(void) ALIAS(IntDefaultHandler);
void PWM1_IRQHandler(void) ALIAS(IntDefaultHandler);
void I2C0_IRQHandler(void) ALIAS(IntDefaultHandler);
void I2C1_IRQHandler(void) ALIAS(IntDefaultHandler);
void I2C2_IRQHandler(void) ALIAS(IntDefaultHandler);
void SPI_IRQHandler(void) ALIAS(IntDefaultHandler);
void SSP0_IRQHandler(void) ALIAS(IntDefaultHandler);
void SSP1_IRQHandler(void) ALIAS(IntDefaultHandler);
void PLL0_IRQHandler(void) ALIAS(IntDefaultHandler);
void RTC_IRQHandler(void) ALIAS(IntDefaultHandler);
void EINT0_IRQHandler(void) ALIAS(IntDefaultHandler);
void EINT1_IRQHandler(void) ALIAS(IntDefaultHandler);
void EINT2_IRQHandler(void) ALIAS(IntDefaultHandler);
void CLIF_IRQHandler(void) ALIAS(IntDefaultHandler);
void ADC_IRQHandler(void) ALIAS(IntDefaultHandler);
void BOD_IRQHandler(void) ALIAS(IntDefaultHandler);
void USB_IRQHandler(void) ALIAS(IntDefaultHandler);
void CAN_IRQHandler(void) ALIAS(IntDefaultHandler);
void DMA_IRQHandler(void) ALIAS(IntDefaultHandler);
void I2S_IRQHandler(void) ALIAS(IntDefaultHandler);
#if defined (__USE_LPCOPEN)
void ETH_IRQHandler(void) ALIAS(IntDefaultHandler);
#else
void ENET_IRQHandler(void) ALIAS(IntDefaultHandler);
#endif
void RIT_IRQHandler(void) ALIAS(IntDefaultHandler);
void MCPWM_IRQHandler(void) ALIAS(IntDefaultHandler);
void QEI_IRQHandler(void) ALIAS(IntDefaultHandler);
void PLL1_IRQHandler(void) ALIAS(IntDefaultHandler);
void USBActivity_IRQHandler(void) ALIAS(IntDefaultHandler);
void CANActivity_IRQHandler(void) ALIAS(IntDefaultHandler);
void UART4_IRQHandler(void) ALIAS(IntDefaultHandler);
void SSP2_IRQHandler(void) ALIAS(IntDefaultHandler);
void LCD_IRQHandler(void) ALIAS(IntDefaultHandler);
void GPIO_IRQHandler(void) ALIAS(IntDefaultHandler);
void PWM0_IRQHandler(void) ALIAS(IntDefaultHandler);
void EEPROM_IRQHandler(void) ALIAS(IntDefaultHandler);
//*****************************************************************************
//
// The entry point for the application.
// __main() is the entry point for Redlib based applications
// main() is the entry point for Newlib based applications
//
//*****************************************************************************
#if defined (__REDLIB__)
extern void __main(void);
#endif
extern int main(void);
//*****************************************************************************
//
// External declaration for the pointer to the stack top from the Linker Script
//
//*****************************************************************************
extern void _vStackTop(void);
//*****************************************************************************
#if defined (__cplusplus)
} // extern "C"
#endif
//*****************************************************************************
//
// The vector table.
// This relies on the linker script to place at correct location in memory.
//
//*****************************************************************************
extern void (* const g_pfnVectors[])(void);
__attribute__ ((section(".isr_vector")))
void (* const g_pfnVectors[])(void) = {
// Core Level - CM3
&_vStackTop, // The initial stack pointer
ResetISR, // The reset handler
NMI_Handler, // The NMI handler
HardFault_Handler, // The hard fault handler
MemManage_Handler, // The MPU fault handler
BusFault_Handler, // The bus fault handler
UsageFault_Handler, // The usage fault handler
0, // Reserved
0, // Reserved
0, // Reserved
0, // Reserved
SVC_Handler, // SVCall handler
DebugMon_Handler, // Debug monitor handler
0, // Reserved
PendSV_Handler, // The PendSV handler
SysTick_Handler, // The SysTick handler
// Chip Level - LPC17
WDT_IRQHandler, // 16, 0x40 - WDT
TIMER0_IRQHandler, // 17, 0x44 - TIMER0
TIMER1_IRQHandler, // 18, 0x48 - TIMER1
TIMER2_IRQHandler, // 19, 0x4c - TIMER2
TIMER3_IRQHandler, // 20, 0x50 - TIMER3
UART0_IRQHandler, // 21, 0x54 - UART0
UART1_IRQHandler, // 22, 0x58 - UART1
UART2_IRQHandler, // 23, 0x5c - UART2
UART3_IRQHandler, // 24, 0x60 - UART3
PWM1_IRQHandler, // 25, 0x64 - PWM1
I2C0_IRQHandler, // 26, 0x68 - I2C0
I2C1_IRQHandler, // 27, 0x6c - I2C1
I2C2_IRQHandler, // 28, 0x70 - I2C2
SPI_IRQHandler, // 29, 0x74 - SPI
SSP0_IRQHandler, // 30, 0x78 - SSP0
SSP1_IRQHandler, // 31, 0x7c - SSP1
PLL0_IRQHandler, // 32, 0x80 - PLL0 (Main PLL)
RTC_IRQHandler, // 33, 0x84 - RTC
EINT0_IRQHandler, // 34, 0x88 - EINT0
EINT1_IRQHandler, // 35, 0x8c - EINT1
EINT2_IRQHandler, // 36, 0x90 - EINT2
CLIF_IRQHandler, // 37, 0x94 - EINT3 (Used for CLIF IRQ)
ADC_IRQHandler, // 38, 0x98 - ADC
BOD_IRQHandler, // 39, 0x9c - BOD
USB_IRQHandler, // 40, 0xA0 - USB
CAN_IRQHandler, // 41, 0xa4 - CAN
DMA_IRQHandler, // 42, 0xa8 - GP DMA
I2S_IRQHandler, // 43, 0xac - I2S
#if defined (__USE_LPCOPEN)
ETH_IRQHandler, // 44, 0xb0 - Ethernet
#else
ENET_IRQHandler, // 44, 0xb0 - Ethernet
#endif
RIT_IRQHandler, // 45, 0xb4 - RITINT
MCPWM_IRQHandler, // 46, 0xb8 - Motor Control PWM
QEI_IRQHandler, // 47, 0xbc - Quadrature Encoder
PLL1_IRQHandler, // 48, 0xc0 - PLL1 (USB PLL)
USBActivity_IRQHandler, // 49, 0xc4 - USB Activity interrupt to wakeup
CANActivity_IRQHandler, // 50, 0xc8 - CAN Activity interrupt to wakeup
UART4_IRQHandler, //; 51 UART4
SSP2_IRQHandler, //; 52 SSP2
LCD_IRQHandler, //; 53 LCD
GPIO_IRQHandler, //; 54 GPIO
PWM0_IRQHandler , //; 55 PWM0
EEPROM_IRQHandler, //; 56 EEPROM
(void *)VT_IMAGE_LENGTH, //; 57 VT Checksum for CRC Check of Vector Table.
};
//*****************************************************************************
// Functions to carry out the initialization of RW and BSS data sections. These
// are written as separate functions rather than being inlined within the
// ResetISR() function in order to cope with MCUs with multiple banks of
// memory.
//*****************************************************************************
__attribute__ ((section(".after_vectors")))
void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
unsigned int *pulDest = (unsigned int*) start;
unsigned int *pulSrc = (unsigned int*) romstart;
unsigned int loop;
for (loop = 0; loop < len; loop = loop + 4)
*pulDest++ = *pulSrc++;
}
__attribute__ ((section(".after_vectors")))
void bss_init(unsigned int start, unsigned int len) {
unsigned int *pulDest = (unsigned int*) start;
unsigned int loop;
for (loop = 0; loop < len; loop = loop + 4)
*pulDest++ = 0;
}
//*****************************************************************************
// The following symbols are constructs generated by the linker, indicating
// the location of various points in the "Global Section Table". This table is
// created by the linker via the Code Red managed linker script mechanism. It
// contains the load address, execution address and length of each RW data
// section and the execution and length of each BSS (zero initialized) section.
//*****************************************************************************
extern unsigned int __data_section_table;
extern unsigned int __data_section_table_end;
extern unsigned int __bss_section_table;
extern unsigned int __bss_section_table_end;
//*****************************************************************************
// Reset entry point for your code.
// Sets up a simple runtime environment and initializes the C/C++
// library.
//*****************************************************************************
__attribute__ ((section(".after_vectors")))
void
ResetISR(void) {
//
// Copy the data sections from flash to SRAM.
//
unsigned int LoadAddr, ExeAddr, SectionLen;
unsigned int *SectionTableAddr;
// Load base address of Global Section Table
SectionTableAddr = &__data_section_table;
// Copy the data sections from flash to SRAM.
while (SectionTableAddr < &__data_section_table_end) {
LoadAddr = *SectionTableAddr++;
ExeAddr = *SectionTableAddr++;
SectionLen = *SectionTableAddr++;
data_init(LoadAddr, ExeAddr, SectionLen);
}
// At this point, SectionTableAddr = &__bss_section_table;
// Zero fill the bss segment
while (SectionTableAddr < &__bss_section_table_end) {
ExeAddr = *SectionTableAddr++;
SectionLen = *SectionTableAddr++;
bss_init(ExeAddr, SectionLen);
}
#if defined (__USE_CMSIS) || defined (__USE_LPCOPEN)
SystemInit();
#endif
#if defined (__cplusplus)
//
// Call C++ library initialisation
//
__libc_init_array();
#endif
#if defined (__REDLIB__)
// Call the Redlib library, which in turn calls main()
__main() ;
#else
main();
#endif
//
// main() shouldn't return, but if it does, we'll just enter an infinite loop
//
while (1) {
;
}
}
/* Set up and initialize hardware prior to call to main */
void SystemInit(void)
{
unsigned int *pSCB_VTOR = (unsigned int *) 0xE000ED08;
#if defined(__IAR_SYSTEMS_ICC__)
extern void *__vector_table;
*pSCB_VTOR = (unsigned int) &__vector_table;
#elif defined(__CODE_RED)
*pSCB_VTOR = (unsigned int) &g_pfnVectors;
#elif defined(__ARMCC_VERSION)
extern void *__Vectors;
*pSCB_VTOR = (unsigned int) &__Vectors;
#endif
#if defined(__FPU_PRESENT) && __FPU_PRESENT == 1
fpuInit();
#endif
#if defined(NO_BOARD_LIB)
/* Chip specific SystemInit */
Chip_SystemInit();
#else
/* Setup system clocking and muxing */
Board_SystemInit();
#endif
/* Update system core clock rate. */
SystemCoreClockUpdate();
}
//*****************************************************************************
// Default exception handlers. Override the ones here by defining your own
// handler routines in your application code.
//*****************************************************************************
__attribute__ ((section(".after_vectors")))
void NMI_Handler(void)
{ while(1) {}
}
/* The fault handler implementation calls a function called
prvGetRegistersFromStack(). */
__attribute__ ((section(".after_vectors")))
void HardFault_Handler(void)
{
/* Use assembly to pick up date, but feed to C Code. */
__asm( ".syntax divided\n"
"MOVS R0, #4 \n"
"MOV R1, LR \n"
"TST R0, R1 \n"
"BEQ _MSP \n"
"MRS R0, PSP \n"
"B HardFault_HandlerC \n"
"_MSP: \n"
"MRS R0, MSP \n"
"B HardFault_HandlerC \n"
".syntax divided\n") ;
__asm(".syntax unified");
}
__attribute__ ((section(".after_vectors")))
void HardFault_HandlerC(
unsigned long *args)
{
volatile unsigned long cm_r0;
volatile unsigned long cm_r1;
volatile unsigned long cm_r2;
volatile unsigned long cm_r3;
volatile unsigned long cm_r12;
volatile unsigned long cm_lr;
volatile unsigned long cm_pc;
volatile unsigned long cm_psr;
//if (((uint32_t) args < PH_RAM_MEM_END)&& ( (uint32_t)args > PH_RAM_MEM_START))
//0x10000000 -- 0x8000
//0x2007c000 -- 0x8000
{
cm_r0 = ((unsigned long)args[0]);
cm_r1 = ((unsigned long)args[1]);
cm_r2 = ((unsigned long)args[2]);
cm_r3 = ((unsigned long)args[3]);
cm_r12 = ((unsigned long)args[4]);
cm_lr = ((unsigned long)args[5]);
cm_pc = ((unsigned long)args[6]);
cm_psr = ((unsigned long)args[7]);
PH_UNUSED_VARIABLE(cm_r0);
PH_UNUSED_VARIABLE(cm_r1);
PH_UNUSED_VARIABLE(cm_r2);
PH_UNUSED_VARIABLE(cm_r3);
PH_UNUSED_VARIABLE(cm_r12);
PH_UNUSED_VARIABLE(cm_lr);
PH_UNUSED_VARIABLE(cm_pc);
PH_UNUSED_VARIABLE(cm_psr);
}
/* Break into the debugger */
__asm("BKPT #0\n");
while (1)
{
__asm("wfi\n");
}
}
__attribute__ ((section(".after_vectors")))
void MemManage_Handler(void)
{ while(1) {}
}
__attribute__ ((section(".after_vectors")))
void BusFault_Handler(void)
{ while(1) {}
}
__attribute__ ((section(".after_vectors")))
void UsageFault_Handler(void)
{ while(1) {}
}
__attribute__ ((section(".after_vectors")))
void SVC_Handler(void)
{ while(1) {}
}
__attribute__ ((section(".after_vectors")))
void DebugMon_Handler(void)
{ while(1) {}
}
__attribute__ ((section(".after_vectors")))
void PendSV_Handler(void)
{ while(1) {}
}
//*****************************************************************************
//
// Processor ends up here if an unexpected interrupt occurs or a specific
// handler is not present in the application code.
//
//*****************************************************************************
__attribute__ ((section(".after_vectors")))
void IntDefaultHandler(void)
{ while(1) {}
}

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/*
* Copyright (c), NXP Semiconductors Bangalore / India
*
* (C)NXP Semiconductors
* All rights are reserved. Reproduction in whole or in part is
* prohibited without the written consent of the copyright owner.
* NXP reserves the right to make changes without notice at any time.
* NXP makes no warranty, expressed, implied or statutory, including but
* not limited to any implied warranty of merchantability or fitness for any
*particular purpose, or that the use will not infringe any third party patent,
* copyright or trademark. NXP must not be liable for any loss or damage
* arising from its use.
*/
/** \file
* Example Source for Card product type detection.
* $Author: Purnank G (ing05193) $
* $Revision: 5458 $ (v07.10.00)
* $Date: 2016-07-06 14:59:09 +0530 (Wed, 06 Jul 2016) $
*
* History:
* BK: Generated 25. Sept 2014
*
*/
/**
* Example Header
*/
#include <phApp_Init.h>
/* Status code definitions */
#include "cards.h"
/*******************************************************************************
** DetectClassic
** This function recognize MIFARE Classic contactless IC card is in field.
** PH_ON will be returned if mifare Classic is detected else PH_OFF.
*******************************************************************************/
uint8_t DetectClassic(uint8_t *pAtqa, uint8_t *bSak)
{
uint32_t sak_atqa = 0;
uint8_t bStatus = PH_OFF;
sak_atqa = bSak[0] << 24 | pAtqa[0] << 8 | pAtqa[1];
sak_atqa &= 0xFFFF0FFF;
/* Detect mini or classic */
switch (sak_atqa)
{
case sak_mfc_1k << 24 | atqa_mfc:
case sak_mfc_4k << 24 | atqa_mfc:
case sak_mfp_2k_sl1 << 24 | atqa_mfp_s:
case sak_mini << 24 | atqa_mini:
case sak_mfp_4k_sl1 << 24 | atqa_mfp_s:
case sak_mfp_2k_sl1 << 24 | atqa_mfp_x:
case sak_mfp_4k_sl1 << 24 | atqa_mfp_x:
bStatus = PH_ON;
break;
default:
break;
}
return bStatus;
}
/*******************************************************************************
** DetectMifare
** This function recognize which kind of mifare card is in field.
** Card type will be returned.
** If 0 returned, card isn't recognized.
*******************************************************************************/
uint32_t DetectMifare(uint8_t *pAtqa, uint8_t *bSak)
{
uint32_t sak_atqa = 0;
uint16_t detected_card = 0xFFFF;
sak_atqa = bSak[0] << 24 | pAtqa[0] << 8 | pAtqa[1];
sak_atqa &= 0xFFFF0FFF;
/* Detect mini or classic */
switch (sak_atqa)
{
case sak_mfc_1k << 24 | atqa_mfc:
DEBUG_PRINTF("Product: MIFARE Classic\n");
detected_card &= mifare_classic;
break;
case sak_mfc_4k << 24 | atqa_mfc:
DEBUG_PRINTF("Product: MIFARE Classic\n");
detected_card &= mifare_classic;
break;
case sak_mfp_2k_sl1 << 24 | atqa_mfp_s:
DEBUG_PRINTF("Product: MIFARE Classic\n");
detected_card &= mifare_classic;
break;
case sak_mini << 24 | atqa_mini:
DEBUG_PRINTF("Product: MIFARE Mini\n");
detected_card &= mifare_mini;
break;
case sak_mfp_4k_sl1 << 24 | atqa_mfp_s:
DEBUG_PRINTF("Product: MIFARE Classic\n");
detected_card &= mifare_classic;
break;
case sak_mfp_2k_sl1 << 24 | atqa_mfp_x:
DEBUG_PRINTF("Product: MIFARE Classic\n");
detected_card &= mifare_classic;
break;
case sak_mfp_4k_sl1 << 24 | atqa_mfp_x:
DEBUG_PRINTF("Product: MIFARE Classic\n");
detected_card &= mifare_classic;
break;
default:
detected_card = 0xFFFF;
break;
}
if (detected_card == 0xFFFF)
{
sak_atqa = bSak[0] << 24 | pAtqa[0] << 8 | pAtqa[1];
switch (sak_atqa)
{
case sak_ul << 24 | atqa_ul:
DEBUG_PRINTF("Product: MIFARE Ultralight contactless IC\n");
detected_card &= mifare_ultralight;
break;
case sak_mfp_2k_sl2 << 24 | atqa_mfp_s:
DEBUG_PRINTF("Product: MIFARE Plus contactless IC\n");
detected_card &= mifare_plus;
break;
case sak_mfp_2k_sl3 << 24 | atqa_mfp_s:
DEBUG_PRINTF("Product: MIFARE Plus\n");
detected_card &= mifare_plus;
break;
case sak_mfp_4k_sl2 << 24 | atqa_mfp_s:
DEBUG_PRINTF("Product: MIFARE Plus\n");
detected_card &= mifare_plus;
break;
case sak_mfp_2k_sl2 << 24 | atqa_mfp_x:
DEBUG_PRINTF("Product: MIFARE Plus\n");
detected_card &= mifare_plus;
break;
case sak_mfp_2k_sl3 << 24 | atqa_mfp_x:
DEBUG_PRINTF("Product: MIFARE Plus\n");
detected_card &= mifare_plus;
break;
case sak_mfp_4k_sl2 << 24 | atqa_mfp_x:
DEBUG_PRINTF("Product: MIFARE Plus\n");
detected_card &= mifare_plus;
break;
case sak_desfire << 24 | atqa_desfire:
DEBUG_PRINTF("Product: MIFARE DESFire contactless IC\n");
detected_card &= mifare_desfire;
break;
case sak_jcop << 24 | atqa_jcop:
DEBUG_PRINTF("Payment card:\n");
detected_card &= jcop;
break;
case sak_layer4 << 24 | atqa_nPA:
DEBUG_PRINTF("German eID (neuer Personalausweis) detected\n");
detected_card &= nPA;
break;
default:
return 0;
}
}
return detected_card;
}
/**
* Dump buffer content in both HEX and ASCII character.
*/
void DumpBuffer(
uint8_t *pBuffer,
uint32_t dwBufferLength
)
{
uint32_t i;
uint8_t aTempBuffer[17] = {0};
/* Debug print is not enabled in Release Mode. Required only for release mode. */
PH_UNUSED_VARIABLE(aTempBuffer[0]);
for(i = 0; i < dwBufferLength; i++)
{
if((i % 16) == 0)
{
if(i != 0)
{
DEBUG_PRINTF(" |%s|\n", aTempBuffer);
}
DEBUG_PRINTF("\t\t[%04X] ", i);
}
DEBUG_PRINTF(" %02X", pBuffer[i]);
if((pBuffer[i] < 0x20) || (pBuffer[i] > 0x7e))
{
aTempBuffer[i % 16] = '.';
}
else
{
aTempBuffer[i % 16] = pBuffer[i];
}
aTempBuffer[16] = 0;
}
while((i % 16) != 0)
{
DEBUG_PRINTF(" ");
aTempBuffer[((i++) % 16)] = ' ';
}
DEBUG_PRINTF(" |%s|\n", aTempBuffer);
}
/******************************************************************************
** End Of File
******************************************************************************/

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@ -0,0 +1,375 @@
/*----------------------------------------------------------------------------*/
/* Copyright 2020, 2023 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may only */
/* be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that you */
/* have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*----------------------------------------------------------------------------*/
/** \file
* Example Source abstracting component data structure and code initialization and code specific to HW used in the examples
* This file shall be present in all examples. A customer does not need to touch/modify this file. This file
* purely depends on the phNxpBuild_Lpc.h or phNxpBuild_App.h
* The phAppInit.h externs the component data structures initialized here that is in turn included by the core examples.
* The core example shall not use any other variable defined here except the RdLib component data structures(as explained above)
* The RdLib component initialization requires some user defined data and function pointers.
* These are defined in the respective examples and externed here.
*
* Keystore and Crypto initialization needs to be handled by application.
*
* $Author$
* $Revision$ (v07.10.00)
* $Date$
*
*/
#include "phApp_Init.h"
#include <phOsal.h>
/*******************************************************************************
** Function Declarations
*******************************************************************************/
/*******************************************************************************
** Function Definitions
*******************************************************************************/
/* Print technology being resolved */
void phApp_PrintTech(uint8_t TechType)
{
switch(TechType)
{
case PHAC_DISCLOOP_POS_BIT_MASK_A:
DEBUG_PRINTF ("\tResolving Type A... \n");
break;
case PHAC_DISCLOOP_POS_BIT_MASK_B:
DEBUG_PRINTF ("\tResolving Type B... \n");
break;
case PHAC_DISCLOOP_POS_BIT_MASK_F212:
DEBUG_PRINTF ("\tResolving Type F with baud rate 212... \n");
break;
case PHAC_DISCLOOP_POS_BIT_MASK_F424:
DEBUG_PRINTF ("\tResolving Type F with baud rate 424... \n");
break;
case PHAC_DISCLOOP_POS_BIT_MASK_V:
DEBUG_PRINTF ("\tResolving Type V... \n");
break;
default:
break;
}
}
/**
* This function will print buffer content
* \param *pBuff Buffer Reference
* \param num data size to be print
*/
void phApp_Print_Buff(uint8_t *pBuff, uint8_t num)
{
uint32_t i;
for(i = 0; i < num; i++)
{
DEBUG_PRINTF(" %02X",pBuff[i]);
}
}
/**
* This function will print Tag information
* \param pDataParams The discovery loop data parameters
* \param wNumberOfTags Total number of tags detected
* \param wTagsDetected Technology Detected
*/
void phApp_PrintTagInfo(phacDiscLoop_Sw_DataParams_t *pDataParams, uint16_t wNumberOfTags, uint16_t wTagsDetected)
{
#if defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_TAGS) || \
defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_P2P_ACTIVE) || \
defined(NXPBUILD__PHAC_DISCLOOP_TYPEB_TAGS) || \
defined(NXPBUILD__PHAC_DISCLOOP_TYPEF_TAGS) || \
defined(NXPBUILD__PHAC_DISCLOOP_TYPEV_TAGS) || \
defined(NXPBUILD__PHAC_DISCLOOP_I18000P3M3_TAGS)
uint16_t bIndex;
#endif
#if defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_TAGS) || defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_P2P_ACTIVE)
uint8_t bTagType;
#endif
#if defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_TAGS) || defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_P2P_ACTIVE)
if (PHAC_DISCLOOP_CHECK_ANDMASK(wTagsDetected, PHAC_DISCLOOP_POS_BIT_MASK_A))
{
if(pDataParams->sTypeATargetInfo.bT1TFlag)
{
DEBUG_PRINTF("\tTechnology : Type A");
DEBUG_PRINTF ("\n\t\tUID :");
phApp_Print_Buff( pDataParams->sTypeATargetInfo.aTypeA_I3P3[0].aUid,
pDataParams->sTypeATargetInfo.aTypeA_I3P3[0].bUidSize);
DEBUG_PRINTF ("\n\t\tSAK : 0x%02x",pDataParams->sTypeATargetInfo.aTypeA_I3P3[0].aSak);
DEBUG_PRINTF ("\n\t\tType: Type 1 Tag\n");
}
else
{
DEBUG_PRINTF("\tTechnology : Type A");
for(bIndex = 0; bIndex < wNumberOfTags; bIndex++)
{
DEBUG_PRINTF ("\n\t\tCard: %d",bIndex + 1);
DEBUG_PRINTF ("\n\t\tUID :");
phApp_Print_Buff( pDataParams->sTypeATargetInfo.aTypeA_I3P3[bIndex].aUid,
pDataParams->sTypeATargetInfo.aTypeA_I3P3[bIndex].bUidSize);
DEBUG_PRINTF ("\n\t\tSAK : 0x%02x",pDataParams->sTypeATargetInfo.aTypeA_I3P3[bIndex].aSak);
if ((pDataParams->sTypeATargetInfo.aTypeA_I3P3[bIndex].aSak & (uint8_t) ~0xFB) == 0)
{
/* Bit b3 is set to zero, [Digital] 4.8.2 */
/* Mask out all other bits except for b7 and b6 */
bTagType = (pDataParams->sTypeATargetInfo.aTypeA_I3P3[bIndex].aSak & 0x60);
bTagType = bTagType >> 5;
switch(bTagType)
{
case PHAC_DISCLOOP_TYPEA_TYPE2_TAG_CONFIG_MASK:
DEBUG_PRINTF ("\n\t\tType: Type 2 Tag\n");
break;
case PHAC_DISCLOOP_TYPEA_TYPE4A_TAG_CONFIG_MASK:
DEBUG_PRINTF ("\n\t\tType: Type 4A Tag\n");
break;
case PHAC_DISCLOOP_TYPEA_TYPE_NFC_DEP_TAG_CONFIG_MASK:
DEBUG_PRINTF ("\n\t\tType: P2P\n");
break;
case PHAC_DISCLOOP_TYPEA_TYPE_NFC_DEP_TYPE4A_TAG_CONFIG_MASK:
DEBUG_PRINTF ("\n\t\tType: Type NFC_DEP and 4A Tag\n");
break;
default:
break;
}
}
}
}
}
#endif
#ifdef NXPBUILD__PHAC_DISCLOOP_TYPEB_TAGS
if (PHAC_DISCLOOP_CHECK_ANDMASK(wTagsDetected, PHAC_DISCLOOP_POS_BIT_MASK_B))
{
DEBUG_PRINTF("\tTechnology : Type B");
/* Loop through all the Type B tags detected and print the Pupi */
for (bIndex = 0; bIndex < wNumberOfTags; bIndex++)
{
DEBUG_PRINTF ("\n\t\tCard: %d",bIndex + 1);
DEBUG_PRINTF ("\n\t\tUID :");
/* PUPI Length is always 4 bytes */
phApp_Print_Buff( pDataParams->sTypeBTargetInfo.aTypeB_I3P3[bIndex].aPupi, 0x04);
}
DEBUG_PRINTF("\n");
}
#endif /* NXPBUILD__PHAC_DISCLOOP_TYPEB_TAGS */
#ifdef NXPBUILD__PHAC_DISCLOOP_TYPEF_TAGS
if( PHAC_DISCLOOP_CHECK_ANDMASK(wTagsDetected, PHAC_DISCLOOP_POS_BIT_MASK_F212) ||
PHAC_DISCLOOP_CHECK_ANDMASK(wTagsDetected, PHAC_DISCLOOP_POS_BIT_MASK_F424))
{
DEBUG_PRINTF("\tTechnology : Type F");
/* Loop through all the type F tags and print the IDm */
for (bIndex = 0; bIndex < wNumberOfTags; bIndex++)
{
DEBUG_PRINTF ("\n\t\tCard: %d",bIndex + 1);
DEBUG_PRINTF ("\n\t\tUID :");
phApp_Print_Buff( pDataParams->sTypeFTargetInfo.aTypeFTag[bIndex].aIDmPMm,
PHAC_DISCLOOP_FELICA_IDM_LENGTH );
if ((pDataParams->sTypeFTargetInfo.aTypeFTag[bIndex].aIDmPMm[0] == 0x01) &&
(pDataParams->sTypeFTargetInfo.aTypeFTag[bIndex].aIDmPMm[1] == 0xFE))
{
/* This is Type F tag with P2P capabilities */
DEBUG_PRINTF ("\n\t\tType: P2P");
}
else
{
/* This is Type F T3T tag */
DEBUG_PRINTF ("\n\t\tType: Type 3 Tag");
}
if(pDataParams->sTypeFTargetInfo.aTypeFTag[bIndex].bBaud != PHAC_DISCLOOP_CON_BITR_212)
{
DEBUG_PRINTF ("\n\t\tBit Rate: 424\n");
}
else
{
DEBUG_PRINTF ("\n\t\tBit Rate: 212\n");
}
}
}
#endif /* NXPBUILD__PHAC_DISCLOOP_TYPEF_TAGS */
#ifdef NXPBUILD__PHAC_DISCLOOP_TYPEV_TAGS
if (PHAC_DISCLOOP_CHECK_ANDMASK(wTagsDetected, PHAC_DISCLOOP_POS_BIT_MASK_V))
{
DEBUG_PRINTF("\tTechnology : Type V / ISO 15693 / T5T");
/* Loop through all the Type V tags detected and print the UIDs */
for (bIndex = 0; bIndex < wNumberOfTags; bIndex++)
{
DEBUG_PRINTF ("\n\t\tCard: %d",bIndex + 1);
DEBUG_PRINTF ("\n\t\tUID :");
phApp_Print_Buff( pDataParams->sTypeVTargetInfo.aTypeV[bIndex].aUid, 0x08);
}
DEBUG_PRINTF("\n");
}
#endif /* NXPBUILD__PHAC_DISCLOOP_TYPEV_TAGS */
#ifdef NXPBUILD__PHAC_DISCLOOP_I18000P3M3_TAGS
if (PHAC_DISCLOOP_CHECK_ANDMASK(wTagsDetected, PHAC_DISCLOOP_POS_BIT_MASK_18000P3M3))
{
DEBUG_PRINTF("\tTechnology : ISO 18000p3m3 / EPC Gen2");
/* Loop through all the 18000p3m3 tags detected and print the UII */
for (bIndex = 0; bIndex < wNumberOfTags; bIndex++)
{
DEBUG_PRINTF("\n\t\tCard: %d",bIndex + 1);
DEBUG_PRINTF("\n\t\tUII :");
phApp_Print_Buff(
pDataParams->sI18000p3m3TargetInfo.aI18000p3m3[bIndex].aUii,
(pDataParams->sI18000p3m3TargetInfo.aI18000p3m3[bIndex].wUiiLength / 8));
}
DEBUG_PRINTF("\n");
}
#endif /* NXPBUILD__PHAC_DISCLOOP_I18000P3M3_TAGS */
}
/**
* This function will print Error information received from Reader Lib
* \param wStatus Error status
*/
void PrintErrorInfo(phStatus_t wStatus)
{
DEBUG_PRINTF("\n ErrorInfo Comp:");
switch(wStatus & 0xFF00)
{
case PH_COMP_BAL:
DEBUG_PRINTF("\t PH_COMP_BAL");
break;
case PH_COMP_HAL:
DEBUG_PRINTF("\t PH_COMP_HAL");
break;
case PH_COMP_PAL_ISO14443P3A:
DEBUG_PRINTF("\t PH_COMP_PAL_ISO14443P3A");
break;
case PH_COMP_PAL_ISO14443P3B:
DEBUG_PRINTF("\t PH_COMP_PAL_ISO14443P3B");
break;
case PH_COMP_PAL_ISO14443P4A:
DEBUG_PRINTF("\t PH_COMP_PAL_ISO14443P4A");
break;
case PH_COMP_PAL_ISO14443P4:
DEBUG_PRINTF("\t PH_COMP_PAL_ISO14443P4");
break;
case PH_COMP_PAL_FELICA:
DEBUG_PRINTF("\t PH_COMP_PAL_FELICA");
break;
case PH_COMP_PAL_EPCUID:
DEBUG_PRINTF("\t PH_COMP_PAL_EPCUID");
break;
case PH_COMP_PAL_SLI15693:
DEBUG_PRINTF("\t PH_COMP_PAL_SLI15693");
break;
case PH_COMP_PAL_I18000P3M3:
DEBUG_PRINTF("\t PH_COMP_PAL_I18000P3M3");
break;
case PH_COMP_PAL_I18092MPI:
DEBUG_PRINTF("\t PH_COMP_PAL_I18092MPI");
break;
case PH_COMP_PAL_I18092MT:
DEBUG_PRINTF("\t PH_COMP_PAL_I18092MT");
break;
case PH_COMP_PAL_I14443P4MC:
DEBUG_PRINTF("\t PH_COMP_PAL_I14443P4MC");
break;
case PH_COMP_AC_DISCLOOP:
DEBUG_PRINTF("\t PH_COMP_AC_DISCLOOP");
break;
case PH_COMP_OSAL:
DEBUG_PRINTF("\t PH_COMP_OSAL");
break;
default:
DEBUG_PRINTF("\t 0x%x",(wStatus & PH_COMPID_MASK));
break;
}
DEBUG_PRINTF("\t type:");
switch(wStatus & PH_ERR_MASK)
{
case PH_ERR_SUCCESS_INCOMPLETE_BYTE:
DEBUG_PRINTF("\t PH_ERR_SUCCESS_INCOMPLETE_BYTE");
break;
case PH_ERR_IO_TIMEOUT:
DEBUG_PRINTF("\t PH_ERR_IO_TIMEOUT");
break;
case PH_ERR_INTEGRITY_ERROR:
DEBUG_PRINTF("\t PH_ERR_INTEGRITY_ERROR");
break;
case PH_ERR_COLLISION_ERROR:
DEBUG_PRINTF("\t PH_ERR_COLLISION_ERROR");
break;
case PH_ERR_BUFFER_OVERFLOW:
DEBUG_PRINTF("\t PH_ERR_BUFFER_OVERFLOW");
break;
case PH_ERR_FRAMING_ERROR:
DEBUG_PRINTF("\t PH_ERR_FRAMING_ERROR");
break;
case PH_ERR_PROTOCOL_ERROR:
DEBUG_PRINTF("\t PH_ERR_PROTOCOL_ERROR");
break;
case PH_ERR_RF_ERROR:
DEBUG_PRINTF("\t PH_ERR_RF_ERROR");
break;
case PH_ERR_EXT_RF_ERROR:
DEBUG_PRINTF("\t PH_ERR_EXT_RF_ERROR");
break;
case PH_ERR_NOISE_ERROR:
DEBUG_PRINTF("\t PH_ERR_NOISE_ERROR");
break;
case PH_ERR_ABORTED:
DEBUG_PRINTF("\t PH_ERR_ABORTED");
break;
case PH_ERR_INTERNAL_ERROR:
DEBUG_PRINTF("\t PH_ERR_INTERNAL_ERROR");
break;
case PH_ERR_INVALID_DATA_PARAMS:
DEBUG_PRINTF("\t PH_ERR_INVALID_DATA_PARAMS");
break;
case PH_ERR_INVALID_PARAMETER:
DEBUG_PRINTF("\t PH_ERR_INVALID_PARAMETER");
break;
case PH_ERR_PARAMETER_OVERFLOW:
DEBUG_PRINTF("\t PH_ERR_PARAMETER_OVERFLOW");
break;
case PH_ERR_UNSUPPORTED_PARAMETER:
DEBUG_PRINTF("\t PH_ERR_UNSUPPORTED_PARAMETER");
break;
case PH_ERR_OSAL_ERROR:
DEBUG_PRINTF("\t PH_ERR_OSAL_ERROR");
break;
case PHAC_DISCLOOP_LPCD_NO_TECH_DETECTED:
DEBUG_PRINTF("\t PHAC_DISCLOOP_LPCD_NO_TECH_DETECTED");
break;
case PHAC_DISCLOOP_COLLISION_PENDING:
DEBUG_PRINTF("\t PHAC_DISCLOOP_COLLISION_PENDING");
break;
default:
DEBUG_PRINTF("\t 0x%x",(wStatus & PH_ERR_MASK));
break;
}
}
/******************************************************************************
** End Of File
******************************************************************************/

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/*----------------------------------------------------------------------------*/
/* Copyright 2016-2020,2022 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may only */
/* be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that you */
/* have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*----------------------------------------------------------------------------*/
/** \file
* Example Source abstracting component data structure and code initialization and code specific to HW used in the examples
* This file shall be present in all examples. A customer does not need to touch/modify this file. This file
* purely depends on the phNxpBuild_Lpc.h or phNxpBuild_App.h
* The phAppInit.h externs the component data structures initialized here that is in turn included by the core examples.
* The core example shall not use any other variable defined here except the RdLib component data structures(as explained above)
* The RdLib component initialization requires some user defined data and function pointers.
* These are defined in the respective examples and externed here.
*
* Keystore and Crypto initialization needs to be handled by application.
*
* $Author$
* $Revision$ (v07.10.00)
* $Date$
*
*/
/* Status header */
#include <ph_Status.h>
#include "phApp_Init.h"
/* LLCP header */
#include <phlnLlcp.h>
#include <phOsal.h>
#ifdef PH_PLATFORM_HAS_ICFRONTEND
#include "BoardSelection.h"
#endif /* PH_PLATFORM_HAS_ICFRONTEND */
#ifdef PHDRIVER_KINETIS_K82
#include <fsl_port.h>
#include <fsl_pit.h>
#ifdef DEBUG
#include <fsl_clock.h>
#endif /* DEBUG */
#endif /* PHDRIVER_KINETIS_K82 */
#ifdef PHDRIVER_KINETIS_K82
#ifdef DEBUG
#define KINETIS_K82_DEBUG_UART_CLK_FREQ CLOCK_GetOsc0ErClkFreq()
#define KINETIS_K82_DEBUG_UART_BASEADDR (uint32_t)(LPUART4)
#define KINETIS_K82_DEBUG_UART_INSTANCE 4U
#define KINETIS_K82_DEBUG_UART_BAUDRATE 115200
#define KINETIS_K82_DEBUG_UART_TYPE DEBUG_CONSOLE_DEVICE_TYPE_LPUART
#endif /* DEBUG */
/*! @brief Clock configuration structure. */
typedef struct _clock_config
{
mcg_config_t mcgConfig; /*!< MCG configuration. */
sim_clock_config_t simConfig; /*!< SIM configuration. */
osc_config_t oscConfig; /*!< OSC configuration. */
uint32_t coreClock; /*!< core clock frequency. */
} clock_config_t;
#endif /* PHDRIVER_KINETIS_K82 */
#ifdef PH_OSAL_LINUX
# define PI_IRQ_POLLING_TASK_PRIO 0
# define PI_IRQ_POLLING_TASK_STACK 0x20000
phOsal_ThreadObj_t gphPiThreadObj;
#endif /* PH_OSAL_LINUX */
#if defined(PHDRIVER_LPC1769) && defined(__CC_ARM)
uint32_t SystemCoreClock;
#endif
/*******************************************************************************
** Function Declarations
*******************************************************************************/
#ifdef PHDRIVER_KINETIS_K82
static void phApp_K82_Init(void);
#endif /* PHDRIVER_KINETIS_K82 */
#ifdef PH_OSAL_LINUX
static void phExample_IrqPolling(void* param);
#endif /* PH_OSAL_LINUX */
phStatus_t phApp_Configure_IRQ();
/*******************************************************************************
** Clock configuration of K82 Platform
*******************************************************************************/
#ifdef PHDRIVER_KINETIS_K82
/* Configuration for enter RUN mode. Core clock = 50MHz. */
const clock_config_t g_defaultClockConfigRun = {
.mcgConfig =
{
.mcgMode = kMCG_ModePEE, /* Work in PEE mode. */
.irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enable. */
.ircs = kMCG_IrcSlow, /* Select IRC32k. */
.fcrdiv = 0U, /* FCRDIV is 0. */
.frdiv = 4U,
.drs = kMCG_DrsLow, /* Low frequency range. */
.dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25%. */
.oscsel = kMCG_OscselOsc, /* Select OSC. */
.pll0Config =
{
.enableMode = 0U, .prdiv = 0x01U, .vdiv = 0x01U,
},
},
.simConfig =
{
.pllFllSel = 1U, /* PLLFLLSEL select PLL. */
.pllFllDiv = 0U, /* PLLFLLSEL clock divider divisor. */
.pllFllFrac = 0U, /* PLLFLLSEL clock divider fraction. */
.er32kSrc = 5U, /* ERCLK32K selection, use RTC. */
.clkdiv1 = 0x01140000U, /* SIM_CLKDIV1. */
},
.oscConfig = {.freq = CPU_XTAL_CLK_HZ,
.capLoad = 0,
.workMode = kOSC_ModeOscLowPower,
.oscerConfig =
{
.enableMode = kOSC_ErClkEnable,
#if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER)
.erclkDiv = 0U,
#endif
}},
};
#endif /* PHDRIVER_KINETIS_K82 */
/*******************************************************************************
** Global Variable Declaration
*******************************************************************************/
#ifdef NXPBUILD__PHLN_LLCP_SW
phlnLlcp_Sw_DataParams_t slnLlcp; /* LLCP component */
#endif /* NXPBUILD__PHLN_LLCP_SW */
/* General information bytes to be sent with ATR Request */
#if defined(NXPBUILD__PHPAL_I18092MPI_SW) || defined(NXPBUILD__PHPAL_I18092MT_SW)
uint8_t aLLCPGeneralBytes[36] = { 0x46,0x66,0x6D,
0x01,0x01,0x10, /*VERSION*/
0x03,0x02,0x00,0x01, /*WKS*/
0x04,0x01,0xF1 /*LTO*/
};
uint8_t bLLCPGBLength = 13;
#endif
/* ATR Response or ATS Response holder */
#if defined(NXPBUILD__PHPAL_I14443P4A_SW) || \
defined(NXPBUILD__PHPAL_I18092MPI_SW)
uint8_t aResponseHolder[64];
#endif
/*******************************************************************************
** Function Definitions
*******************************************************************************/
#ifdef PHDRIVER_KINETIS_K82
static void phApp_K82_Init(void)
{
#ifdef DEBUG
uint32_t uartClkSrcFreq;
#endif /* DEBUG */
pit_config_t pitConfig; /* Structure of initialize PIT */
CLOCK_SetSimSafeDivs();
CLOCK_InitOsc0(&g_defaultClockConfigRun.oscConfig);
CLOCK_SetXtal0Freq(CPU_XTAL_CLK_HZ);
CLOCK_BootToPeeMode(g_defaultClockConfigRun.mcgConfig.oscsel, kMCG_PllClkSelPll0,
&g_defaultClockConfigRun.mcgConfig.pll0Config);
CLOCK_SetInternalRefClkConfig(g_defaultClockConfigRun.mcgConfig.irclkEnableMode,
g_defaultClockConfigRun.mcgConfig.ircs, g_defaultClockConfigRun.mcgConfig.fcrdiv);
CLOCK_SetSimConfig(&g_defaultClockConfigRun.simConfig);
SystemCoreClockUpdate();
/*
* pitConfig.enableRunInDebug = false;
*/
PIT_GetDefaultConfig(&pitConfig);
/* Init pit module */
PIT_Init(PIT, &pitConfig);
#ifdef DEBUG
/* Initialize LPUART4 pins below used to Print */
/* Ungate the port clock */
CLOCK_EnableClock(kCLOCK_PortC);
/* Affects PORTC_PCR14 register */
PORT_SetPinMux(PORTC, 14U, kPORT_MuxAlt3);
/* Affects PORTC_PCR15 register */
PORT_SetPinMux(PORTC, 15U, kPORT_MuxAlt3);
/* SIM_SOPT2[27:26]:
* 00: Clock Disabled
* 01: MCGFLLCLK, or MCGPLLCLK, or IRC48M
* 10: OSCERCLK
* 11: MCGIRCCLK
*/
CLOCK_SetLpuartClock(2);
uartClkSrcFreq = KINETIS_K82_DEBUG_UART_CLK_FREQ;
DbgConsole_Init(KINETIS_K82_DEBUG_UART_INSTANCE, KINETIS_K82_DEBUG_UART_BAUDRATE, KINETIS_K82_DEBUG_UART_TYPE, uartClkSrcFreq);
#endif /* DEBUG */
}
#endif /* PHDRIVER_KINETIS_K82 */
#ifdef PH_PLATFORM_HAS_ICFRONTEND
/**
* This function will initialize Host Controller interfaced with NXP Reader IC's.
* Any initialization which is not generic across Platforms, should be done here.
* Note: For NXP NFC Controllers HOST initialization is not required.
*/
void phApp_CPU_Init(void)
{
#if defined PHDRIVER_KINETIS_K82
phApp_K82_Init();
#elif defined(PHDRIVER_LPC1769) && defined(__CC_ARM)
SystemCoreClock = (( unsigned long ) 96000000);
#elif defined(PH_OSAL_LINUX) && defined(NXPBUILD__PHHAL_HW_PN5190)
phStatus_t status;
status = PiGpio_OpenIrq();
if ((status & PH_ERR_MASK) != PH_ERR_SUCCESS)
{
DEBUG_PRINTF("\n PiGpio_OpenIrq failed \n");
DEBUG_PRINTF("\n Couldn't open PN5190 Kernel IRQ Driver.\n Halting here!!FIX IT!!\n");
while(1);
}
#else
/* In case of LPC series, startup file takes care of initializing clock and ports.
* No initialization is required in Linux environment. */
#endif
}
#endif /* PH_PLATFORM_HAS_ICFRONTEND */
/**
* This function will initialize Reader LIbrary Component
*/
phStatus_t phApp_Comp_Init(void * pDiscLoopParams)
{
phStatus_t wStatus = PH_ERR_SUCCESS;
#if defined(NXPBUILD__PHPAL_I18092MPI_SW) || defined(NXPBUILD__PHPAL_I18092MT_SW) || \
defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_P2P_TAGS) || defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_P2P_ACTIVE) || \
defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_I3P4_TAGS) || defined(NXPBUILD__PHAC_DISCLOOP_TYPEF_P2P_TAGS) || \
defined(NXPBUILD__PHAC_DISCLOOP_TYPEF212_P2P_ACTIVE) || defined(NXPBUILD__PHAC_DISCLOOP_TYPEF424_P2P_ACTIVE)
phacDiscLoop_Sw_DataParams_t * pDiscLoop = (phacDiscLoop_Sw_DataParams_t *)pDiscLoopParams;
#endif
/* Initialize the LLCP component */
#ifdef NXPBUILD__PHLN_LLCP_SW
slnLlcp.sLocalLMParams.wMiu = 0x00; /* 128 bytes only */
slnLlcp.sLocalLMParams.wWks = 0x11; /* SNEP & LLCP */
slnLlcp.sLocalLMParams.bLto = 100; /* Maximum LTO */
slnLlcp.sLocalLMParams.bOpt = 0x02;
slnLlcp.sLocalLMParams.bAvailableTlv = PHLN_LLCP_TLV_MIUX_MASK | PHLN_LLCP_TLV_WKS_MASK |
PHLN_LLCP_TLV_LTO_MASK | PHLN_LLCP_TLV_OPT_MASK;
wStatus = phlnLlcp_Sw_Init(
&slnLlcp,
sizeof(phlnLlcp_Sw_DataParams_t),
aLLCPGeneralBytes,
&bLLCPGBLength);
#endif /* NXPBUILD__PHLN_LLCP_SW */
#ifdef NXPBUILD__PHAC_DISCLOOP_SW
#if defined(NXPBUILD__PHPAL_I18092MPI_SW) || defined(NXPBUILD__PHPAL_I18092MT_SW)
/* Assign the GI for Type A */
pDiscLoop->sTypeATargetInfo.sTypeA_P2P.pGi = (uint8_t *)aLLCPGeneralBytes;
pDiscLoop->sTypeATargetInfo.sTypeA_P2P.bGiLength = bLLCPGBLength;
/* Assign the GI for Type F */
pDiscLoop->sTypeFTargetInfo.sTypeF_P2P.pGi = (uint8_t *)aLLCPGeneralBytes;
pDiscLoop->sTypeFTargetInfo.sTypeF_P2P.bGiLength = bLLCPGBLength;
#endif /* NXPBUILD__PHAC_DISCLOOP_SW */
#if defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_P2P_TAGS) || defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_P2P_ACTIVE)
/* Assign ATR response for Type A */
pDiscLoop->sTypeATargetInfo.sTypeA_P2P.pAtrRes = aResponseHolder;
#endif
#if defined(NXPBUILD__PHAC_DISCLOOP_TYPEF_P2P_TAGS) || defined(NXPBUILD__PHAC_DISCLOOP_TYPEF212_P2P_ACTIVE) || \
defined(NXPBUILD__PHAC_DISCLOOP_TYPEF424_P2P_ACTIVE)
/* Assign ATR response for Type F */
pDiscLoop->sTypeFTargetInfo.sTypeF_P2P.pAtrRes = aResponseHolder;
#endif
#ifdef NXPBUILD__PHAC_DISCLOOP_TYPEA_I3P4_TAGS
/* Assign ATS buffer for Type A */
pDiscLoop->sTypeATargetInfo.sTypeA_I3P4.pAts = aResponseHolder;
#endif /* NXPBUILD__PHAC_DISCLOOP_TYPEA_I3P4_TAGS */
#endif /* NXPBUILD__PHAC_DISCLOOP_SW */
return wStatus;
}
phStatus_t phApp_Configure_IRQ()
{
#ifdef PH_OSAL_LINUX
phStatus_t wStatus;
#endif /* PH_OSAL_LINUX */
#ifdef PH_PLATFORM_HAS_ICFRONTEND
#if !(defined(PH_OSAL_LINUX) && defined(NXPBUILD__PHHAL_HW_PN5190))
phDriver_Pin_Config_t pinCfg;
pinCfg.bOutputLogic = PH_DRIVER_SET_LOW;
pinCfg.bPullSelect = PHDRIVER_PIN_IRQ_PULL_CFG;
pinCfg.eInterruptConfig = PIN_IRQ_TRIGGER_TYPE;
phDriver_PinConfig(PHDRIVER_PIN_IRQ, PH_DRIVER_PINFUNC_INTERRUPT, &pinCfg);
#endif
#ifdef PHDRIVER_LPC1769
NVIC_SetPriority(EINT_IRQn, EINT_PRIORITY);
/* Enable interrupt in the NVIC */
NVIC_ClearPendingIRQ(EINT_IRQn);
NVIC_EnableIRQ(EINT_IRQn);
#endif /* PHDRIVER_LPC1769 */
#ifdef PH_OSAL_LINUX
gphPiThreadObj.pTaskName = (uint8_t *) "IrqPolling";
gphPiThreadObj.pStackBuffer = NULL;
gphPiThreadObj.priority = PI_IRQ_POLLING_TASK_PRIO;
gphPiThreadObj.stackSizeInNum = PI_IRQ_POLLING_TASK_STACK;
PH_CHECK_SUCCESS_FCT(wStatus, phOsal_ThreadCreate(&gphPiThreadObj.ThreadHandle, &gphPiThreadObj,
&phExample_IrqPolling, NULL));
#endif /* PH_OSAL_LINUX */
#ifdef PHDRIVER_KINETIS_K82
NVIC_SetPriority(EINT_IRQn, EINT_PRIORITY);
NVIC_ClearPendingIRQ(EINT_IRQn);
EnableIRQ(EINT_IRQn);
#endif /* PHDRIVER_KINETIS_K82 */
#endif /* PH_PLATFORM_HAS_ICFRONTEND */
return PH_ERR_SUCCESS;
}
#ifdef PH_OSAL_LINUX
/*
* \brief: The purpose of this Thread is to detect RF signal from an External Peer .
*/
static void phExample_IrqPolling(void* param)
{
uint8_t bgpioVal = 0;
uint8_t bhighOrLow = 0;
#if defined(NXPBUILD__PHHAL_HW_RC663) || defined(NXPBUILD__PHHAL_HW_PN5180)
if(PIN_IRQ_TRIGGER_TYPE == PH_DRIVER_INTERRUPT_RISINGEDGE)
{
bhighOrLow = 1;
}
while(PiGpio_read(PHDRIVER_PIN_IRQ, &bgpioVal) != PH_ERR_SUCCESS)
{
PiGpio_unexport(PHDRIVER_PIN_IRQ);
PiGpio_export(PHDRIVER_PIN_IRQ);
PiGpio_set_direction(PHDRIVER_PIN_IRQ, false);
if(PIN_IRQ_TRIGGER_TYPE == PH_DRIVER_INTERRUPT_RISINGEDGE)
{
PiGpio_set_edge(PHDRIVER_PIN_IRQ, true, false);
}
else
{
PiGpio_set_edge(PHDRIVER_PIN_IRQ, false, true);
}
}
/* Initial status: If pin is already Active, post an event. */
if(bgpioVal == bhighOrLow)
{
CLIF_IRQHandler();
}
#endif
while(1)
{
/* Block forever for Raising Edge in PHDRIVER_PIN_IRQ. */
#if defined(NXPBUILD__PHHAL_HW_RC663) || defined(NXPBUILD__PHHAL_HW_PN5180)
if(PiGpio_poll(PHDRIVER_PIN_IRQ, bhighOrLow, -1) == PH_ERR_SUCCESS)
#elif defined(NXPBUILD__PHHAL_HW_PN5190)
if(PiGpio_Irq() == PH_ERR_SUCCESS)
#endif
{
CLIF_IRQHandler();
}
else
{
PiGpio_unexport(PHDRIVER_PIN_IRQ);
PiGpio_export(PHDRIVER_PIN_IRQ);
PiGpio_set_direction(PHDRIVER_PIN_IRQ, false);
if(PIN_IRQ_TRIGGER_TYPE == PH_DRIVER_INTERRUPT_RISINGEDGE)
{
PiGpio_set_edge(PHDRIVER_PIN_IRQ, true, false);
}
else
{
PiGpio_set_edge(PHDRIVER_PIN_IRQ, false, true);
}
}
}
}
#endif /* PH_OSAL_LINUX */
/******************************************************************************
** End Of File
******************************************************************************/

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/*----------------------------------------------------------------------------*/
/* Copyright 2020,2023 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may only */
/* be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that you */
/* have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*----------------------------------------------------------------------------*/
/** \file
* Example Source abstracting component data structure and code initialization and code specific to HW used in the examples
* This file shall be present in all examples. A customer does not need to touch/modify this file. This file
* purely depends on the phNxpBuild_Lpc.h or phNxpBuild_App.h
* The phAppInit.h externs the component data structures initialized here that is in turn included by the core examples.
* The core example shall not use any other variable defined here except the RdLib component data structures(as explained above)
* The RdLib component initialization requires some user defined data and function pointers.
* These are defined in the respective examples and externed here.
*
* Keystore and Crypto initialization needs to be handled by application.
*
* $Author$
* $Revision$ (v07.10.00)
* $Date$
*
*/
/* Status header */
#include <ph_Status.h>
#include "phApp_Init.h"
#ifdef NXPBUILD__PHHAL_HW_PN5180
#include "BoardSelection.h"
/* HAL specific headers */
#include <phhalHw_Pn5180_Instr.h>
/*******************************************************************************
** Function Declarations
*******************************************************************************/
/*******************************************************************************
** Global Variable Declaration
*******************************************************************************/
phbalReg_Type_t sBalParams;
phhalHw_Pn5180_DataParams_t * pHal;
#ifdef NXPBUILD__PHHAL_HW_TARGET
/* Parameters for L3 activation during Autocoll */
extern uint8_t sens_res[2] ;
extern uint8_t nfc_id1[3] ;
extern uint8_t sel_res ;
extern uint8_t nfc_id3 ;
extern uint8_t poll_res[18] ;
#endif /* NXPBUILD__PHHAL_HW_TARGET */
/*******************************************************************************
** Function Definitions
*******************************************************************************/
/**
* This function will initialize Hal Target Config
*/
phStatus_t phApp_HALConfigAutoColl(void)
{
#ifdef NXPBUILD__PHHAL_HW_TARGET
phStatus_t wStatus;
uint8_t baDynamicUidConfig[1U] = { 1U };
uint8_t baReadEepromConfig[24U] = { 0U };
/* Read Set Listen Parameters data from EEPROM */
wStatus = phhalHw_Pn5180_Instr_ReadE2Prom(
(phhalHw_Pn5180_DataParams_t *) pHal,
PHHAL_HW_PN5180_SET_LISTEN_E2PROM_ADDR,
baReadEepromConfig,
24U
);
CHECK_SUCCESS(wStatus);
/* Verify EEPROM data and configure Set Listen Parameters if EEPROM data is not correct. */
if ((memcmp(&baReadEepromConfig[0U], sens_res, 2U) != 0x00) ||
(memcmp(&baReadEepromConfig[2U], nfc_id1, 3U) != 0x00) ||
(memcmp(&baReadEepromConfig[5U], &sel_res, 1U) != 0x00) ||
(memcmp(&baReadEepromConfig[6U], poll_res, 18U) != 0x00))
{
/* Configure Set Listen Parameters. */
wStatus = phhalHw_Pn5180_SetListenParameters(
pHal,
&sens_res[0],
&nfc_id1[0],
sel_res,
&poll_res[0],
nfc_id3
);
CHECK_SUCCESS(wStatus);
}
if (pHal->wFirmwareVer < 0x308U)
{
/* With Pn5180 FW version < 3.8, only static UID is supported. */
baDynamicUidConfig[0] = 0x00;
}
/* Read Dynamic UID configuration from EEPROM */
wStatus = phhalHw_Pn5180_Instr_ReadE2Prom(
(phhalHw_Pn5180_DataParams_t *) pHal,
PHHAL_HW_PN5180_DYN_UID_CFG_E2PROM_ADDR,
baReadEepromConfig,
1U
);
CHECK_SUCCESS(wStatus);
/* Verify EEPROM data and perform Dynamic UID configuration if EEPROM data is not correct. */
if (memcmp(baReadEepromConfig, baDynamicUidConfig, 1U) != 0x00)
{
/* Configure Dynamic UID */
wStatus = phhalHw_Pn5180_Instr_WriteE2Prom(
(phhalHw_Pn5180_DataParams_t *) pHal,
PHHAL_HW_PN5180_DYN_UID_CFG_E2PROM_ADDR,
baDynamicUidConfig,
1U
);
CHECK_SUCCESS(wStatus);
}
#endif /* NXPBUILD__PHHAL_HW_TARGET */
return PH_ERR_SUCCESS;
}
/* Configure LPCD (for PN5180) */
phStatus_t phApp_ConfigureLPCD(void)
{
/**
* PHHAL_HW_CONFIG_SET_LPCD_WAKEUPTIME_MS 0x0070U //< Used value for wakeup counter in msecs, i.e. after this amount of time IC will wakes up from standby.
* PHHAL_HW_CONFIG_LPCD_MODE 0x0071U //< Used to set options PHHAL_HW_PN5180_LPCD_MODE_DEFAULT or PHHAL_HW_PN5180_LPCD_MODE_POWERDOWN_GUARDED
* PHHAL_HW_CONFIG_LPCD_REF 0x0072U //< Used to set or get LPCD Ref
*/
phStatus_t status = PH_ERR_SUCCESS;
uint16_t wConfig = PHHAL_HW_CONFIG_LPCD_REF;
uint16_t wValue;
uint8_t bLPCD_Threshold_EEPROMAddress = 0x37;
uint8_t bLPCD_Threshold = 0x10;
wValue = PHHAL_HW_PN5180_LPCD_MODE_POWERDOWN;
wConfig = PHHAL_HW_CONFIG_LPCD_MODE;
//status = phhalHw_Pn5180_Int_LPCD_GetConfig(pHal, wConfig, &wValue);
status = phhalHw_Pn5180_Instr_WriteE2Prom(pHal,bLPCD_Threshold_EEPROMAddress, &bLPCD_Threshold, 1 );
CHECK_SUCCESS(status);
status = phhalHw_Pn5180_Int_LPCD_SetConfig(
pHal,
wConfig,
wValue
);
return status;
}
void CLIF_IRQHandler(void)
{
/* Read the interrupt status of external interrupt attached to the reader IC IRQ pin */
if (phDriver_PinRead(PHDRIVER_PIN_IRQ, PH_DRIVER_PINFUNC_INTERRUPT))
{
phDriver_PinClearIntStatus(PHDRIVER_PIN_IRQ);
/* Call application registered callback. */
if (pHal->pRFISRCallback != NULL)
{
pHal->pRFISRCallback(pHal);
}
}
}
#endif /* NXPBUILD__PHHAL_HW_PN5180 */
/******************************************************************************
** End Of File
******************************************************************************/

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PROJECT(NfcrdlibEx4_MIFAREClassic)
FILE(GLOB NfcrdlibEx4_MIFAREClassic_Sources
*.c
src/*.c
)
include_directories(
intfs
types
)
ADD_EXECUTABLE(NfcrdlibEx4_MIFAREClassic
${NfcrdlibEx4_MIFAREClassic_Sources}
)
TARGET_LINK_LIBRARIES(
NfcrdlibEx4_MIFAREClassic
phOsal
DAL
NxpRdLib_acDiscLoop
NxpRdLib_halHw
NxpRdLib_KeyStore
NxpRdLib_phTools
NxpRdLib_palFelica
NxpRdLib_palI18092mPI
NxpRdLib_palI14443p4a
NxpRdLib_palI14443p4
NxpRdLib_palI14443p4
NxpRdLib_palMifare
NxpRdLib_alFelica
NxpRdLib_alMful
NxpRdLib_alMfdf
NxpRdLib_alT1T
NxpRdLib_alTop
NxpRdLib_alMfc
NxpRdLib_lnLlcp
NxpRdLib_phTools
NxpRdLib_palI18092mT
NxpRdLib_npSnep
NxpRdLib_palI14443p4mC
NxpRdLib_ceT4T
NxpRdLib_palEpcUid
NxpRdLib_alMfNtag42XDna
NxpRdLib_phNfcLib
)

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/*----------------------------------------------------------------------------*/
/* Copyright 2012-2021,2023 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may only */
/* be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that you */
/* have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*----------------------------------------------------------------------------*/
/** \file
* Example Source for NfcrdlibEx4_MIFAREClassic that uses the MIFARE Classic contactless IC implementation.
* This example will load/configure Discovery loop for MIFARE Classic, uses POLL mode to detect the MIFARE Classic card.
* Displays detected MIFARE Classic card information like UID, ATQA, SAK, Sector Authentication, Block Read and Write status.
* Example will activate the device at index zero whenever multiple MIFARE Classic cards are detected.
* Please refer Readme.txt file for Hardware Pin Configuration, Software Configuration and steps to build and
* execute the project which is present in the same project directory.
* $Author: $
* $Revision: $ (v07.10.00)
* $Date: $
*
*/
/**
* Reader Library Headers
*/
#include <phApp_Init.h>
#include "NfcrdlibEx4_MIFAREClassic.h"
/*******************************************************************************
** Definitions
*******************************************************************************/
#define NUMBER_OF_KEYENTRIES 2
#define NUMBER_OF_KEYVERSIONPAIRS 2
#define NUMBER_OF_KUCENTRIES 1
#define DATA_BUFFER_LEN 16 /* Buffer length */
#define MFC_BLOCK_DATA_SIZE 16 /* Block Data size - 16 Bytes */
phacDiscLoop_Sw_DataParams_t * pDiscLoop; /* Discovery loop component */
void *psKeyStore;
void *psalMFC;
/*PAL variables*/
phKeyStore_Sw_KeyEntry_t sKeyEntries[NUMBER_OF_KEYENTRIES]; /* Sw KeyEntry structure */
phKeyStore_Sw_KUCEntry_t sKUCEntries[NUMBER_OF_KUCENTRIES]; /* Sw Key usage counter structure */
phKeyStore_Sw_KeyVersionPair_t sKeyVersionPairs[NUMBER_OF_KEYVERSIONPAIRS * NUMBER_OF_KEYENTRIES]; /* Sw KeyVersionPair structure */
uint8_t bDataBuffer[DATA_BUFFER_LEN]; /* universal data buffer */
uint8_t bSak; /* SAK card type information */
uint16_t wAtqa; /* ATQA card type information */
/* Set the key for the MIFARE (R) Classic cards. */
uint8_t Key[12] = {0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU};
/* Don't change the following line. */
uint8_t Original_Key[12] = {0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU};
#ifdef PHOSAL_FREERTOS_STATIC_MEM_ALLOCATION
uint32_t aMfClassicTaskBuffer[MIFARECLASSIC_TASK_STACK];
#else /* PHOSAL_FREERTOS_STATIC_MEM_ALLOCATION */
#define aMfClassicTaskBuffer NULL
#endif /* PHOSAL_FREERTOS_STATIC_MEM_ALLOCATION */
#ifdef PH_OSAL_FREERTOS
const uint8_t bTaskName[configMAX_TASK_NAME_LEN] = {"MfClassic"};
#else
const uint8_t bTaskName[] = {"MfClassic"};
#endif /* PH_OSAL_FREERTOS */
static volatile uint8_t bInfLoop = 1U;
/*******************************************************************************
** Prototypes
*******************************************************************************/
void NfcrdlibEx4_MIFAREClassic(void *pParams);
static phStatus_t Ex4_NfcRdLibInit(void);
/*******************************************************************************
** Code
*******************************************************************************/
int main(void)
{
do
{
phStatus_t status = PH_ERR_INTERNAL_ERROR;
phNfcLib_Status_t dwStatus;
#ifdef PH_PLATFORM_HAS_ICFRONTEND
phNfcLib_AppContext_t AppContext = {0};
#endif /* PH_PLATFORM_HAS_ICFRONTEND */
#ifndef PH_OSAL_NULLOS
phOsal_ThreadObj_t MfClassic;
#endif /* PH_OSAL_NULLOS */
/* Perform Controller specific initialization. */
phApp_CPU_Init();
/* Perform OSAL Initialization. */
(void)phOsal_Init();
/* Print Example application name */
DEBUG_PRINTF("\n *** MIFARE Classic Example *** \n");
#ifdef PH_PLATFORM_HAS_ICFRONTEND
status = phbalReg_Init(&sBalParams, sizeof(phbalReg_Type_t));
CHECK_STATUS(status);
AppContext.pBalDataparams = &sBalParams;
dwStatus = phNfcLib_SetContext(&AppContext);
CHECK_NFCLIB_STATUS(dwStatus);
#endif /* PH_PLATFORM_HAS_ICFRONTEND */
/* Initialize library */
dwStatus = phNfcLib_Init();
CHECK_NFCLIB_STATUS(dwStatus);
if(dwStatus != PH_NFCLIB_STATUS_SUCCESS) break;
/* Set the generic pointer */
pHal = phNfcLib_GetDataParams(PH_COMP_HAL);
pDiscLoop = phNfcLib_GetDataParams(PH_COMP_AC_DISCLOOP);
psKeyStore = phNfcLib_GetDataParams(PH_COMP_KEYSTORE);
psalMFC = phNfcLib_GetDataParams(PH_COMP_AL_MFC);
/* Initialize other components that are not initialized by NFCLIB and configure Discovery Loop. */
status = phApp_Comp_Init(pDiscLoop);
CHECK_STATUS(status);
if(status != PH_ERR_SUCCESS) break;
/* Perform Platform Init */
status = phApp_Configure_IRQ();
CHECK_STATUS(status);
if(status != PH_ERR_SUCCESS) break;
#ifndef PH_OSAL_NULLOS
MfClassic.pTaskName = (uint8_t *)bTaskName;
MfClassic.pStackBuffer = aMfClassicTaskBuffer;
MfClassic.priority = MIFARECLASSIC_TASK_PRIO;
MfClassic.stackSizeInNum = MIFARECLASSIC_TASK_STACK;
phOsal_ThreadCreate(&MfClassic.ThreadHandle, &MfClassic, &NfcrdlibEx4_MIFAREClassic, NULL);
phOsal_StartScheduler();
/* Print Error info */
DEBUG_PRINTF("RTOS Error : Scheduler exited. \n");
#else
(void)NfcrdlibEx4_MIFAREClassic(pDiscLoop);
#endif /* PH_OSAL_NULLOS */
} while(0);
while(bInfLoop); /* Comes here if initialization failure or scheduler exit due to error */
return 0;
}
/***********************************************************************************************
* \brief This function demonstrates the MIFARE Classic card detection, Block authentication,
* Block Read and Block Write operation.
* \param *pParams
* \return This function will never return
**********************************************************************************************/
void NfcrdlibEx4_MIFAREClassic(void *pParams)
{
phStatus_t status = 0;
uint16_t wTagsDetected = 0;
uint8_t bUid[PHAC_DISCLOOP_I3P3A_MAX_UID_LENGTH];
uint8_t bUidSize;
/* This call shall allocate secure context before calling any secure function,
* when FreeRtos trust zone is enabled.
* */
phOsal_ThreadSecureStack( 512 );
/* Initialize components required by this example. */
status = Ex4_NfcRdLibInit();
while(1) /* Continuous loop */
{
DEBUG_PRINTF("\nReady to detect\n");
do
{
/* Field OFF */
status = phhalHw_FieldOff(pHal);
CHECK_STATUS(status);
status = phhalHw_Wait(pDiscLoop->pHalDataParams,PHHAL_HW_TIME_MICROSECONDS, 5100);
CHECK_STATUS(status);
/* Configure Discovery loop for Poll Mode */
status = phacDiscLoop_SetConfig(pDiscLoop, PHAC_DISCLOOP_CONFIG_NEXT_POLL_STATE, PHAC_DISCLOOP_POLL_STATE_DETECTION);
CHECK_STATUS(status);
/* Run Discovery loop */
status = phacDiscLoop_Run(pDiscLoop, PHAC_DISCLOOP_ENTRY_POINT_POLL);
}while((status & PH_ERR_MASK) != PHAC_DISCLOOP_DEVICE_ACTIVATED); /* Exit on Card detection */
/* Card detected */
/* Get the tag types detected info */
status = phacDiscLoop_GetConfig(pDiscLoop, PHAC_DISCLOOP_CONFIG_TECH_DETECTED, &wTagsDetected);
/* Check for Status */
if ((status & PH_ERR_MASK) == PH_ERR_SUCCESS)
{
/* Check for Type A tag detection */
if (PHAC_DISCLOOP_CHECK_ANDMASK(wTagsDetected, PHAC_DISCLOOP_POS_BIT_MASK_A))
{
/* Check for MIFARE Classic */
if (0x08 == (pDiscLoop->sTypeATargetInfo.aTypeA_I3P3[0].aSak & 0x08))
{
do
{
/* Print UID */
DEBUG_PRINTF ("\nUID: ");
phApp_Print_Buff(pDiscLoop->sTypeATargetInfo.aTypeA_I3P3[0].aUid,
pDiscLoop->sTypeATargetInfo.aTypeA_I3P3[0].bUidSize);
/* Print ATQA and SAK */
DEBUG_PRINTF("\nATQA:");
phApp_Print_Buff(pDiscLoop->sTypeATargetInfo.aTypeA_I3P3[0].aAtqa, 2);
DEBUG_PRINTF ("\nSAK: 0x%x",pDiscLoop->sTypeATargetInfo.aTypeA_I3P3[0].aSak);
/* Print Product type */
DEBUG_PRINTF("\nProduct: MIFARE Classic \n");
bUidSize = pDiscLoop->sTypeATargetInfo.aTypeA_I3P3[0].bUidSize;
memcpy(bUid, pDiscLoop->sTypeATargetInfo.aTypeA_I3P3[0].aUid, bUidSize);
/* Authenticate with the Key
* We can authenticate at any block of a sector and we will get the access to all blocks of the same sector
* For example authenticating at block 5, we will get the access to blocks 4, 5, 6 and 7.
*/
/* Send authentication for block 6 */
status = phalMfc_Authenticate(psalMFC, 6, PHHAL_HW_MFC_KEYA, 1, 0, bUid, bUidSize);
/* Check for Status */
if ((status & PH_ERR_MASK) != PH_ERR_SUCCESS)
{
/* Print Error info */
DEBUG_PRINTF("\nAuthentication Failed!!!");
DEBUG_PRINTF("\nPlease correct the used key");
DEBUG_PRINTF("\nExecution aborted!!!\n");
break;
}
DEBUG_PRINTF("\nAuthentication Successful");
/* Empty the bDataBuffer */
memset(bDataBuffer, '\0', DATA_BUFFER_LEN);
DEBUG_PRINTF("\nRead data from Block 4");
/* Read data from block 4 */
status = phalMfc_Read(psalMFC, 4, bDataBuffer);
/* Check for Status */
if (status != PH_ERR_SUCCESS)
{
/* Print Error info */
DEBUG_PRINTF("\nRead operation failed!!!\n");
DEBUG_PRINTF("\nExecution aborted!!!\n\n");
break; /* Break from the loop*/
}
DEBUG_PRINTF("\nRead Success");
DEBUG_PRINTF("\nThe content of Block 4 is:\n");
phApp_Print_Buff(&bDataBuffer[0], MFC_BLOCK_DATA_SIZE);
DEBUG_PRINTF("\n\n --- End of Read Operation --- \n");
DEBUG_PRINTF("\nWrite data to Block 4");
/* Write data to block 4 */
status = phalMfc_Write(psalMFC, 4, bDataBuffer);
/* Check for Status */
if (status != PH_ERR_SUCCESS)
{
/* Print Error info */
DEBUG_PRINTF("\nWrite operation failed!!!\n");
DEBUG_PRINTF("\nExecution aborted!!!\n");
break; /* Break from the loop*/
}
DEBUG_PRINTF("\nWrite Success");
DEBUG_PRINTF("\n\n --- End of Write Operation --- ");
/* End of example */
DEBUG_PRINTF("\n\n --- End of Example --- \n\n");
}while(0);
DEBUG_PRINTF("\nPlease Remove the Card\n\n");
/* Field RESET */
status = phhalHw_FieldReset(pHal);
CHECK_STATUS(status);
/* Make sure that example application is not detecting the same card continuously */
do
{
/* Send WakeUpA */
status = phpalI14443p3a_WakeUpA(pDiscLoop->pPal1443p3aDataParams,
pDiscLoop->sTypeATargetInfo.aTypeA_I3P3[0].aAtqa);
/* Check for Status */
if (status != PH_ERR_SUCCESS)
{
break; /* Card Removed, break from the loop */
}
/* Send HaltA */
status = phpalI14443p3a_HaltA(pDiscLoop->pPal1443p3aDataParams);
CHECK_STATUS(status);
/* Delay - 5 milli seconds*/
status = phhalHw_Wait(pDiscLoop->pHalDataParams, PHHAL_HW_TIME_MILLISECONDS, 5);
CHECK_STATUS(status);
}while(1);
}
}
}
}
}
/***********************************************************************************************
* \brief Initializes the discovery loop and keystore components required by Example-4
* \param none
* \return status Returns the function status
**********************************************************************************************/
static phStatus_t Ex4_NfcRdLibInit(void)
{
phStatus_t status;
/* Device limit for Type A */
status = phacDiscLoop_SetConfig(pDiscLoop, PHAC_DISCLOOP_CONFIG_TYPEA_DEVICE_LIMIT, 1);
CHECK_STATUS(status);
/* Bailout on Type A detect */
status = phacDiscLoop_SetConfig(pDiscLoop, PHAC_DISCLOOP_CONFIG_BAIL_OUT, PHAC_DISCLOOP_POS_BIT_MASK_A);
CHECK_STATUS(status);
/* Initialize the keystore component */
status = phKeyStore_Sw_Init(
psKeyStore,
sizeof(phKeyStore_Sw_DataParams_t),
&sKeyEntries[0],
NUMBER_OF_KEYENTRIES,
&sKeyVersionPairs[0],
NUMBER_OF_KEYVERSIONPAIRS,
&sKUCEntries[0],
NUMBER_OF_KUCENTRIES
);
CHECK_STATUS(status);
/* load a Key to the Store */
/* Note: If You use Key number 0x00, be aware that in SAM
this Key is the 'Host authentication key' !!! */
status = phKeyStore_FormatKeyEntry(psKeyStore, 1, PH_KEYSTORE_KEY_TYPE_MIFARE);
CHECK_STATUS(status);
/* Set Key Store */
status = phKeyStore_SetKey(psKeyStore, 1, 0, PH_KEYSTORE_KEY_TYPE_MIFARE, &Key[0], 0);
CHECK_STATUS(status);
/* Read the version of the reader IC */
#if defined NXPBUILD__PHHAL_HW_RC663
status = phhalHw_Rc663_ReadRegister(pHal, PHHAL_HW_RC663_REG_VERSION, &bDataBuffer[0]);
CHECK_STATUS(status);
DEBUG_PRINTF("\nReader chip RC663: 0x%02x\n", bDataBuffer[0]);
#endif /* NXPBUILD__PHHAL_HW_RC663 */
/* Return Success */
return PH_ERR_SUCCESS;
}
#ifdef NXPBUILD__PHHAL_HW_TARGET
/* Stubbed definitions in case TARGET is enabled */
uint8_t sens_res[2] = {0x04, 0x00};
uint8_t nfc_id1[3] = {0xA1, 0xA2, 0xA3};
uint8_t sel_res = 0x40;
uint8_t nfc_id3 = 0xFA;
uint8_t poll_res[18] = {0x01, 0xFE, 0xB2, 0xB3, 0xB4, 0xB5,
0xB6, 0xB7, 0xC0, 0xC1, 0xC2, 0xC3,
0xC4, 0xC5, 0xC6, 0xC7, 0x23, 0x45 };
#endif /* NXPBUILD__PHHAL_HW_TARGET */

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__________________________________________________
NXPNFCRDLIB EXAMPLE : NFCRDLIBEX4_MIFARECLASSIC
(V07.10.00)
__________________________________________________
Table of Contents
_________________
1 Document Purpose
2 Description of the NfcrdlibEx4_MIFAREClassic
3 Restrictions on NfcrdlibEx4_MIFAREClassic
4 Package Contents
5 Mandatory materials (not included)
6 Hardware Configuration
7 Software Configuration
8 Steps to build NfcrdlibEx4_MIFAREClassic for LPC1769 with PN5190 using MCUXpresso
9 Steps to build NfcrdlibEx4_MIFAREClassic for LPC1769 with PN5180 using MCUXpresso
10 Steps to build NfcrdlibEx4_MIFAREClassic for LPC1769 with RC663 using MCUXpresso
11 Steps to build NfcrdlibEx4_MIFAREClassic for PN7462AU using MCUXpresso
12 Steps to build NfcrdlibEx4_MIFAREClassic for FRDM-K82F using MCUXpresso
13 Selection of Board / OSAL / Frontend (MCUXpresso)
14 Steps to follow for PI / Linux / CMake
15 Running NfcrdlibEx4_MIFAREClassic
16 List of supported NFC Reader Boards/ICs
17 Reference Documents
1 Document Purpose
==================
This document describes the steps to be followed to execute
NfcrdlibEx4_MIFAREClassic example as well as it's known problems and
restrictions.
2 Description of the NfcrdlibEx4_MIFAREClassic
==============================================
- NfcrdlibEx4_MIFAREClassic will load/configure Discovery loop with
NFC profile via SetConfig.
- By using POLL mode of discovery loop, example will detect the MIFARE
Classic cards and display/print detected tag information like UID,
ATQA, SAK, Sector Authentication status, Block Read and Block Write
status.
- This example will activate device at index zero whenever multiple
cards are detected.
- For successful authentication, this example expects the MIFARE
Classic Cards which has a KeyA value of {0xFF 0xFF 0xFF 0xFF 0xFF
0xFF} for sector 1.
3 Restrictions on NfcrdlibEx4_MIFAREClassic
===========================================
- NfcrdlibEx4_MIFAREClassic is restricted to be run on NFC Reader
Boards/ICs mentioned in Section-16.
- The APIs are intended for NXP contact-less reader ICs only, as such
the APIs are not to be ported to any technology from any other
vendor.
- NXP will not support porting to any other vendor platform.
- This software project requires NxpNfcRdLib v07.10.00 or later.
- **IMPORTANT** The default used MCU Type is K82. When executing
example on LPC1769 or PN7462AU, the MCU Type has to be changed in
the MCUXpresso IDE.
- For switching to MCU Type to PN7462AU, see Section-11
- For switching to MCU Type to LPC1769, see Section-8, Section-9 and
Section-10.
4 Package Contents
==================
- Readme.txt
+ This readme file
- NfcrdlibEx4_MIFAREClassic.c
+ Main example file.
- intfs/NfcrdlibEx4_MIFAREClassic.h
+ Interfaces/Defines specific to the example
- intfs/ph_NxpBuild_App.h
+ Reader library build configuration file
- src/phApp_Helper.c
- src/phApp_PN5180_Init.c
- src/phApp_PN5190_Init.c
- src/phApp_PN7462AU_Init.c
- src/phApp_RC663_Init.c
- src/phApp_Init.c and intfs/phApp_Init.h
+ Common utility functions (common across all examples)
- mcux/.cproject and mcux/.project
+ MCUXpresso project configuration file
- cr_startup_lpc175x_6x.c
+ Startup required to compile example for LPC1769 Micro Controller.
5 Mandatory materials (not included)
====================================
- MCUXpresso IDE. It can be downloaded from
[http://www.nxp.com/products/:MCUXpresso-IDE]
- SDK for Freedom K82 Board
([http://www.nxp.com/products/:FRDM-K82F]). The pre-build SDK can
be downloaded from
[https://mcuxpresso.nxp.com/en/license?hash=9897a8c19a6bc569c3fade7141f0f405&hash_download=true&to_vault=true]
See MCUXpresso User Manual for steps needed to install an SDK.
- Plugin to extend MCUXpresso to support PN7462AU. (Required for
MCUXpresso versions before MCUXpressoIDE_10.0.2)
- LPCXpresso LPC1769 / Freedom K82 development boards For NFC ICs
listed in Section-16 (Note: PN7462AU (Section-16 Bullet-3) does not
need any other other microcontroller).
6 Hardware Configuration
========================
Before starting this application, HW Changes may be required for the
used board. Refer to the following User Manuals / Application notes
before starting with this example.
- AN11211: Quick Start Up Guide RC663 Blueboard
- AN11744: PN5180 Evaluation board quick start guide
- AN11802: NFC Reader Library for Linux Installation Guidelines
- AN12550: PNEV5190B Evaluation board quick start guide
7 Software Configuration
========================
- The Software can be compiled for Cortex M3 LPC1769 micro-controller,
Cortex M4 Freedom K82 and Cortex M0 based PN7462AU from NXP.
- Since this example can be configured to run on various MCU ICs and
various NFC ICs, appropriate changes are required as mentioned in
Section-8, Section-9, Section-10, Section-11 and Section-12.
8 Steps to build NfcrdlibEx4_MIFAREClassic for LPC1769 with PN5190 using MCUXpresso
===================================================================================
See "PNEV5190B Evaluation board quick start guide" in AN12550 (See
Section-17, Bullet-6 below)
9 Steps to build NfcrdlibEx4_MIFAREClassic for LPC1769 with PN5180 using MCUXpresso
===================================================================================
See "Importing provided SW example projects" in AN11908 (See
Section-17, Bullet-2 below)
10 Steps to build NfcrdlibEx4_MIFAREClassic for LPC1769 with RC663 using MCUXpresso
===================================================================================
See "Importing provided SW example projects" in AN11022 (See
Section-17, Bullet-3 below)
11 Steps to build NfcrdlibEx4_MIFAREClassic for PN7462AU using MCUXpresso
=========================================================================
- For MCUXpresso versions before MCUXpressoIDE_10.0.2, See "Adding
PN7462AU Plugin" in UM10883. (See Section-17, Bullet-4 below)
- See "Importing provided SW example projects" in UM10883.
12 Steps to build NfcrdlibEx4_MIFAREClassic for FRDM-K82F using MCUXpresso
==========================================================================
See "Import projects to the MCUXpresso" in AN11908. (See Section-17,
Bullet-2 below)
13 Selection of Board / OSAL / Frontend (MCUXpresso)
====================================================
For MCUXpresso, the selection of Board / OSAL / Frontend has to be
done via -D (Preprocessor defines).
1) To select the board go to "Project Properties" --> "C/C++ Build"
--> "Settings" --> "Preprocessor" --> "Defined symbols (-D)", and
define the relevant PHDRIVER_<BoardNFCCombination>_BOARD macro.
e.g. For using K82 with Pn5190 use PHDRIVER_K82F_PNEV5190B_BOARD
and for LPC1769 with PN5190 use PHDRIVER_LPC1769PN5190_BOARD. For
list of supported boards refer to
Platform\DAL\cfg\BoardSelection.h.
2) To select the osal/os type, go to "Project Properties" --> "C/C++
Build" --> "Settings" --> "Preprocessor" --> "Defined symbols
(-D)".
e.g. For using FreeRTOS use PH_OSAL_FREERTOS. For other options
refer to RTOS\phOsal\inc\phOsal_Config.h.
14 Steps to follow for PI / Linux / CMake
=========================================
The steps are described in AN11802. (See Section-17, Bullet-5 below)
15 Running NfcrdlibEx4_MIFAREClassic
====================================
1) Run the application and when you bring the MIFARE Classic in
proximity, the example application will detect and displays the
detected card information on console.
2) Please use the MIFARE Classic Cards which has a KeyA value of {0xFF
0xFF 0xFF 0xFF 0xFF 0xFF} for sector 1 to get the successful
authentication.
16 List of supported NFC Reader Boards/ICs
==========================================
1) CLEV6630B v2.0 Customer Evaluation Board
2) PNEV5180B v2.0 Customer Evaluation Board
3) PN7462AU v2.1 Customer Evaluation Board
4) PNEV5190B v1.0 Customer Evaluation Board
17 Reference Documents
======================
1) UM10954 : PN5180 SW Quick start guide
[http://www.nxp.com/docs/en/user-guide/UM10954.pdf]
2) AN11908 : NFC Reader Library for FRDM-K82F Board Installation
guidelines
[http://www.nxp.com/docs/en/application-note/AN11908.pdf]
3) AN11022 : CLRC663 Evaluation board quick start guide
[http://www.nxp.com/docs/en/application-note/AN11022.pdf]
4) UM10883 : PN7462AU Quick Start Guide - Development Kit
[http://www.nxp.com/docs/en/user-guide/UM10883.pdf]
5) AN11802 : NFC Reader Library for Linux Installation Guidelines
[http://www.nxp.com/docs/en/application-note/AN11802.pdf]
6) AN12550 : PNEV5190B Evaluation board quick start guide
----------------------------------------------------------------------
For updates of this example, see
[http://www.nxp.com/products/:NFC-READER-LIBRARY]

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/*----------------------------------------------------------------------------*/
/* Copyright 2016-2021 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may only */
/* be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that you */
/* have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*----------------------------------------------------------------------------*/
/** \file
* Example Source Header for NfcrdlibEx4_MIFAREClassic application.
*
* $Author: NXP $
* $Revision: $ (v07.10.00)
* $Date: $
*/
#ifndef INTFS_NFCRDLIBEX4_MIFARECLASSIC_H_
#define INTFS_NFCRDLIBEX4_MIFARECLASSIC_H_
#include <ph_Status.h>
#ifdef PH_OSAL_FREERTOS
#ifdef PHOSAL_FREERTOS_STATIC_MEM_ALLOCATION
#define MIFARECLASSIC_TASK_STACK (1400/4)
#else /* PHOSAL_FREERTOS_STATIC_MEM_ALLOCATION */
#if defined( __PN74XXXX__) || defined(__PN76XX__)
#define MIFARECLASSIC_TASK_STACK (1200/4)
#else /* defined( __PN74XXXX__) || defined(__PN76XX__) */
#define MIFARECLASSIC_TASK_STACK 1250
#endif /* defined( __PN74XXXX__) || defined(__PN76XX__) */
#endif /* PHOSAL_FREERTOS_STATIC_MEM_ALLOCATION */
#define MIFARECLASSIC_TASK_PRIO 4
#endif /* PH_OSAL_FREERTOS */
#ifdef PH_OSAL_LINUX
#define MIFARECLASSIC_TASK_STACK 0x20000
#define MIFARECLASSIC_TASK_PRIO 0
#endif /* PH_OSAL_LINUX */
#endif /* INTFS_NFCRDLIBEX4_MIFARECLASSIC_H_ */

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/*----------------------------------------------------------------------------*/
/* Copyright 2016-2023 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may only */
/* be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that you */
/* have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*----------------------------------------------------------------------------*/
/** \file
* Example Source abstracting component header specific to HW used in the examples
* This file shall be present in all examples. A customer does not need to touch/modify this file. This file
* purely depends on the phNxpBuild_Lpc.h or phNxpBuild_App.h
* The phAppInit.h externs the component data structures initialized here that is in turn included by the core examples.
* The core example shall not use any other variable defined here except the RdLib component data structures(as explained above)
* The RdLib component initialization requires some user defined data and function pointers.
* These are defined in the respective examples and externed here.
*
* Keystore and Crypto initialization needs to be handled by application.
*
* $Author$
* $Revision$ (v07.10.00)
* $Date$
*
*/
#ifndef PHAPP_INIT_H
#define PHAPP_INIT_H
/* Status header */
#include <ph_Status.h>
/* Driver Header */
#include <phDriver.h>
/* NFCLIB Header */
#include <phNfcLib.h>
/* LLCP header */
#include <phlnLlcp.h>
/* SNEP header */
#include <phnpSnep.h>
/* Check for K82 controller based boards. */
#if defined(PHDRIVER_FRDM_K82FPN5180_BOARD) || \
defined(PHDRIVER_FRDM_K82FRC663_BOARD) || \
defined(PHDRIVER_K82F_PNEV5190B_BOARD)
#define PHDRIVER_KINETIS_K82
#endif
/* Check for LPC1769 controller based boards. */
#if defined(PHDRIVER_LPC1769PN5180_BOARD) || \
defined(PHDRIVER_LPC1769RC663_BOARD) || \
defined(PHDRIVER_LPC1769PN5190_BOARD)
#define PHDRIVER_LPC1769
#endif
#if defined(PHDRIVER_PIPN5180_BOARD) || \
defined(PHDRIVER_PIRC663_BOARD) || \
defined(PHDRIVER_PIPN5190_BOARD)
#include <phDriver_Linux_Int.h>
#endif
#ifdef PHDRIVER_KINETIS_K82
# include <fsl_debug_console.h>
# include <stdio.h>
#endif
#if !defined(__PN76XX__)
#ifdef DEBUG
#ifdef PHDRIVER_KINETIS_K82
#if SDK_DEBUGCONSOLE==1
#define DEBUG_PRINTF DbgConsole_Printf
#else
#define DEBUG_PRINTF(...) printf(__VA_ARGS__);
#endif
#else /* PHDRIVER_KINETIS_K82 */
#include <stdio.h>
#define DEBUG_PRINTF(...) printf(__VA_ARGS__); fflush(stdout)
#endif /* PHDRIVER_KINETIS_K82 */
#else /* DEBUG */
#define DEBUG_PRINTF(...)
#define DEBUG_SCANF(...)
#endif /* DEBUG */
#else /* __PN76XX__ */
#if (SEGGER_RTT_ENABLE == 1)
#include "SEGGER_RTT.h"
#define DEBUG_PRINTF(...) SEGGER_RTT_printf(0, __VA_ARGS__);
#define DEBUG_SCANF(Input , data) *data = (SEGGER_RTT_WaitKey() - 0x30); SEGGER_RTT_WaitKey()
#else
#if DEBUG
#include <fsl_debug_console.h>
#define DEBUG_PRINTF(...) PRINTF(__VA_ARGS__);
#define DEBUG_SCANF(...) SCANF(__VA_ARGS__);while ((GETCHAR()) != '\n');
#define DEBUG_GETCHAR GETCHAR
#else
#define DEBUG_PRINTF(...)
#define DEBUG_SCANF(...)
#endif /* DEBUG */
#endif /* (SEGGER_RTT_ENABLE == 1) */
#endif /* __PN76XX__ */
/*******************************************************************************
** Global Variable Declaration
*******************************************************************************/
#define PH_NFCRDLIB_EXAMPLE_LPCD_GUARDTIME 100 /* LPCD Guard time(T4) in milli-seconds configured by application for Rc663. */
#define PH_NFCRDLIB_EXAMPLE_LPCD_RFON_TIME 56 /* LPCD RFON time(T3) in micro-seconds configured by application for Rc663. */
/* HAL & BAL declarations */
#ifdef PH_PLATFORM_HAS_ICFRONTEND
extern phbalReg_Type_t sBalParams;
#endif /* PH_PLATFORM_HAS_ICFRONTEND */
#ifdef NXPBUILD__PHLN_LLCP_SW
extern phlnLlcp_Sw_DataParams_t slnLlcp; /* LLCP component */
#endif /* NXPBUILD__PHLN_LLCP_SW */
#ifdef NXPBUILD__PHHAL_HW_PN5180
extern phhalHw_Pn5180_DataParams_t * pHal;
#endif /* NXPBUILD__PHHAL_HW_PN5180 */
#ifdef NXPBUILD__PHHAL_HW_PN5190
extern phhalHw_Pn5190_DataParams_t * pHal;
#endif /* NXPBUILD__PHHAL_HW_PN5190 */
#ifdef NXPBUILD__PHHAL_HW_RC663
extern phhalHw_Rc663_DataParams_t * pHal;
#endif /* NXPBUILD__PHHAL_HW_RC663 */
#ifdef NXPBUILD__PHHAL_HW_PN7462AU
extern phhalHw_PN7462AU_DataParams_t * pHal;
#endif /* NXPBUILD__PHHAL_HW_PN7462AU */
#ifdef NXPBUILD__PHHAL_HW_PN76XX
extern phhalHw_Pn76xx_DataParams_t * pHal;
#endif /* NXPBUILD__PHHAL_HW_PN76XX */
/**************************************************Prints if error is detected**************************************************************/
/* Enable(1) / Disable(0) printing error/info */
#define DETECT_ERROR 0
#if DETECT_ERROR
#define DEBUG_ERROR_PRINT(x) x
#define PRINT_INFO(...) DEBUG_PRINTF(__VA_ARGS__)
#else
#define DEBUG_ERROR_PRINT(x)
#define PRINT_INFO(...)
#endif
#define CHECK_STATUS(x) \
if ((x) != PH_ERR_SUCCESS) \
{ \
DEBUG_PRINTF("Line: %d Error - (0x%04X) has occurred : 0xCCEE CC-Component ID, EE-Error code. Refer-ph_Status.h\n", __LINE__, (x)); \
}
/* prints if error is detected */
#define CHECK_SUCCESS(x) \
if ((x) != PH_ERR_SUCCESS) \
{ \
DEBUG_PRINTF("\nLine: %d Error - (0x%04X) has occurred : 0xCCEE CC-Component ID, EE-Error code. Refer-ph_Status.h\n ", __LINE__, (x)); \
return (x); \
}
/* prints if error is detected */
#define CHECK_NFCLIB_STATUS(x) \
if ((x) != PH_NFCLIB_STATUS_SUCCESS) \
{ \
DEBUG_PRINTF("\nLine: %d Error - (0x%04X) has occurred in NFCLIB\n ", __LINE__, (x)); \
}
/*********************************************************************************************************************************************/
/*******************************************************************************
** Function Declarations
*******************************************************************************/
extern void phApp_CPU_Init(void);
extern phStatus_t phApp_Comp_Init(void * pDiscLoopParams);
extern phStatus_t phApp_HALConfigAutoColl(void);
extern phStatus_t phApp_ConfigureLPCD(void);
extern void phApp_PrintTagInfo(phacDiscLoop_Sw_DataParams_t *pDataParams, uint16_t wNumberOfTags, uint16_t wTagsDetected);
extern void phApp_PrintTech(uint8_t TechType);
extern void phApp_Print_Buff(uint8_t *pBuff, uint8_t num);
extern void PrintErrorInfo(phStatus_t wStatus);
extern phStatus_t phApp_Configure_IRQ();
#ifdef PH_PLATFORM_HAS_ICFRONTEND
extern void CLIF_IRQHandler(void);
#endif /* PH_PLATFORM_HAS_ICFRONTEND */
#endif /* PHAPP_INIT_H */

View File

@ -0,0 +1,254 @@
/*----------------------------------------------------------------------------*/
/* Copyright 2016-2023 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may only */
/* be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that you */
/* have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*----------------------------------------------------------------------------*/
/** \file
* Application specific selection of Reader Library Components
*
* $Author$
* $Revision$ (v07.10.00)
* $Date$
*
*/
#ifndef PH_NXPBUILD_APP_H_INC
#define PH_NXPBUILD_APP_H_INC
/** \defgroup ph_NxpBuild NXP Build
* \brief Controls the Inclusion of required components, Inclusion SRC/DATA within components and the Build Dependencies between the components
* @{
*/
/* NXPBUILD_DELETE: included code lines should be always removed from code */
/* NXP BUILD DEFINES */
/* use #define to include components */
/* comment out #define to exclude components */
/* DEBUG build mode */
/*#define NXPBUILD__PH_DEBUG*/ /**< DEBUG build definition */
#define NXPRDLIB_REM_GEN_INTFS
/*********************************************************************************************************************************************************************************/
#if defined(__PN74XXXX__) || defined (__PN73XXXX__)
#define NXPBUILD__PHHAL_HW_PN7462AU /**< NFC Controller PN7462AU HAL */
#endif
#ifdef __PN76XX__
#ifdef __PN7642__
#define NXPBUILD__PHHAL_HW_PN7642 /**< NFC Controller PN7642 HAL */
#elif __PN7640__
#define NXPBUILD__PHHAL_HW_PN7640 /**< NFC Controller PN7640 HAL */
#else
#error " PN76 platform definition (__PN7642__ or __PN7640__) missing !!! "
#endif
#if defined(__PN7642__) || defined(__PN7640__)
#define NXPBUILD__PHHAL_HW_PN76XX /**< NFC Controller PN76XX HAL */
#endif
#endif /* __PN76XX__ */
#if defined(PHDRIVER_LPC1769PN5180_BOARD) \
|| defined(PHDRIVER_FRDM_K82FPN5180_BOARD)
# define NXPBUILD__PHHAL_HW_PN5180
#endif
#if defined(PHDRIVER_LPC1769PN5190_BOARD) \
|| defined(PHDRIVER_K82F_PNEV5190B_BOARD)
# define NXPBUILD__PHHAL_HW_PN5190
//# define PH_NXPNFCRDLIB_CONFIG_HIGHER_FSDI /**< Higher FSDI value is used for PN5190. */
#endif
#if defined(PHDRIVER_LPC1769RC663_BOARD) \
|| defined(PHDRIVER_FRDM_K82FRC663_BOARD)
# define NXPBUILD__PHHAL_HW_RC663
#endif
#if defined(NXPBUILD__PHHAL_HW_PN5180) || \
defined(NXPBUILD__PHHAL_HW_PN5190) || \
defined(NXPBUILD__PHHAL_HW_PN76XX) || \
defined(NXPBUILD__PHHAL_HW_PN7462AU)
// #define NXPBUILD__PHHAL_HW_TARGET /**< Dependency checking if target mode macros should be enabled */
#endif
/*********************************************************************************************************************************************************************************/
#define NXPBUILD__PHPAL_I14443P3A_SW /**< PAL ISO 14443-3A SW Component is included. */
//#define NXPBUILD__PHPAL_I14443P3B_SW /**< PAL ISO 14443-3B SW Component is included. */
//#define NXPBUILD__PHPAL_I14443P4A_SW /**< PAL ISO 14443-4A SW Component is included. */
//#define NXPBUILD__PHPAL_I14443P4_SW /**< PAL ISO 14443-4 SW Component is included. */
#define NXPBUILD__PHPAL_MIFARE_SW /**< PAL MIFARE SW Component is included */
//#define NXPBUILD__PHPAL_MIFARE_STUB /**< PAL MIFARE STUB Component is included */
//#define NXPBUILD__PHPAL_FELICA_SW /**< PAL Felica SW Component is included. */
//#define NXPBUILD__PHPAL_SLI15693_SW /**< PAL SLI 15693 Component is included. */
//#define NXPBUILD__PHPAL_I18000P3M3_SW /**< PAL ISO 18000p3m3 Component is included. */
#ifdef NXPBUILD__PHHAL_HW_RC663 /**< If FE HAL is RC663, then include EPC UID PAL as required, otherwise exclude. */
// #define NXPBUILD__PHPAL_EPCUID_SW /**< PAL EPC UID SW Component is included. */
#endif
//#define NXPBUILD__PHPAL_I18092MPI_SW /**< PAL ISO18092 (P2P) SW Component is included. */
#ifndef NXPBUILD__PHHAL_HW_RC663 /**< If FE HAL is RC663, then exclude ISO14443 Card Mode PAL & ISO18092 Target Mode PAL, otherwise include as required. */
// #define NXPBUILD__PHPAL_I14443P4MC_SW /**< PAL ISO 14443-4 Card Mode SW Component is included. */
// #define NXPBUILD__PHPAL_I18092MT_SW /**< PAL ISO 18092 Target Mode SW Component is included. */
#endif /* NXPBUILD__PHHAL_HW_RC663 */
/*********************************************************************************************************************************************************************************/
#define NXPBUILD__PHAC_DISCLOOP_SW /**< Discovery Loop Activity SW Component is included. */
#ifdef NXPBUILD__PHAC_DISCLOOP_SW /**< If DiscLoop SW Component is included, macros( & it's dependencies) to include/exclude SRC/DATA within Discloop is defined. */
#if defined (NXPBUILD__PHHAL_HW_PN5180) || \
defined (NXPBUILD__PHHAL_HW_PN5190) || \
defined (NXPBUILD__PHHAL_HW_RC663) || \
defined (NXPBUILD__PHHAL_HW_PN7462AU) || \
defined (NXPBUILD__PHHAL_HW_PN7642)
// #define NXPBUILD__PHAC_DISCLOOP_LPCD /**< SRC to enable LPCD is included. */
#endif
#ifdef NXPBUILD__PHPAL_I14443P3A_SW
#define NXPBUILD__PHAC_DISCLOOP_TYPEA_I3P3_TAGS /**< SRC/DATA to Detect/CollRes/Activate cards such as MFC, MFUL, MFP SL1 etc is included. */
// #define NXPBUILD__PHAC_DISCLOOP_TYPEA_JEWEL_TAGS /**< SRC/DATA to Detect cards such as NFC Forum T1T, Topaz/Jewel is included. */
#if defined(NXPBUILD__PHPAL_I14443P4A_SW) && defined(NXPBUILD__PHPAL_I14443P4_SW)
#define NXPBUILD__PHAC_DISCLOOP_TYPEA_I3P4_TAGS /**< SRC/DATA to Detect cards such as MFDF, MFP, T4AT NFC Forum Tag or Type A EMVCo is included. */
#endif
#endif /* NXPBUILD__PHPAL_I14443P3A_SW */
#if defined(NXPBUILD__PHPAL_I14443P3A_SW) && defined(NXPBUILD__PHPAL_I18092MPI_SW)
#define NXPBUILD__PHAC_DISCLOOP_TYPEA_P2P_TAGS /**< SRC/DATA to Detect Peer Passive Type A P2P Target mode devices is included. */
#endif
#ifndef NXPBUILD__PHHAL_HW_RC663
#ifdef NXPBUILD__PHPAL_I18092MPI_SW
#define NXPBUILD__PHAC_DISCLOOP_TYPEA_P2P_ACTIVE /**< SRC/DATA to Detect Peer Active Type A P2P Target mode devices is included. */
#define NXPBUILD__PHAC_DISCLOOP_TYPEF212_P2P_ACTIVE/**< SRC/DATA to Detect Peer Active Type F212 P2P Target mode devices is included. */
#define NXPBUILD__PHAC_DISCLOOP_TYPEF424_P2P_ACTIVE/**< SRC/DATA to Detect Peer Active Type F424 P2P Target mode devices is included. */
#endif /* NXPBUILD__PHPAL_I18092MPI_SW */
#endif /* NXPBUILD__PHHAL_HW_RC663 */
#ifdef NXPBUILD__PHPAL_FELICA_SW
#define NXPBUILD__PHAC_DISCLOOP_FELICA_TAGS /**< SRC/DATA to Detect FeliCa Cards is included. */
#ifdef NXPBUILD__PHPAL_I18092MPI_SW
#define NXPBUILD__PHAC_DISCLOOP_TYPEF_P2P_TAGS /**< SRC/DATA to Detect Peer Passive Type F P2P Target mode devices is included. */
#endif /* NXPBUILD__PHPAL_I18092MPI_SW */
#endif /* NXPBUILD__PHPAL_FELICA_SW */
#ifdef NXPBUILD__PHPAL_I14443P3B_SW
#define NXPBUILD__PHAC_DISCLOOP_TYPEB_I3P3B_TAGS /**< SRC/DATA to Detect Type B Cards that operate at Layer3 level is included */
#ifdef NXPBUILD__PHPAL_I14443P4_SW
#define NXPBUILD__PHAC_DISCLOOP_TYPEB_I3P4B_TAGS /**< SRC/DATA to Detect Type B Cards such as NFC Forum Type 4 Tags, EMVCo Type B Cards etc is included */
#endif /* NXPBUILD__PHPAL_I14443P4_SW */
#endif /* NXPBUILD__PHPAL_I14443P3B_SW */
#ifdef NXPBUILD__PHPAL_SLI15693_SW
#define NXPBUILD__PHAC_DISCLOOP_TYPEV_TAGS /**< SRC/DATA to Detect Type V Cards such as ICODE SLI/SLIX/SLI2/Tesa Cards is included*/
#endif /* NXPBUILD__PHPAL_SLI15693_SW */
#ifdef NXPBUILD__PHPAL_I18000P3M3_SW
#define NXPBUILD__PHAC_DISCLOOP_I18000P3M3_TAGS /**< SRC/DATA to Detect ICODE ILT Cards such as SMARTRAC StackIt Cards is included*/
#endif /* NXPBUILD__PHPAL_I18000P3M3_SW */
#ifndef NXPBUILD__PHHAL_HW_RC663 /**< If FE HAL is RC663, target mode is not supported at all, hence exclude those SRC, otherwise include as required */
#ifdef NXPBUILD__PHHAL_HW_TARGET
#define NXPBUILD__PHAC_DISCLOOP_TYPEA_TARGET_PASSIVE /**< SRC to Initialize Type A passive listen config and subsequently call HAL AutoColl is included. */
#define NXPBUILD__PHAC_DISCLOOP_TYPEA_TARGET_ACTIVE /**< SRC to Initialize Type A active listen config and subsequently call HAL AutoColl is included. */
#define NXPBUILD__PHAC_DISCLOOP_TYPEF212_TARGET_PASSIVE/**< SRC to Initialize Type F212 passive listen config and subsequently call HAL AutoColl is included. */
#define NXPBUILD__PHAC_DISCLOOP_TYPEF212_TARGET_ACTIVE /**< SRC to Initialize Type F212 active listen config and subsequently call HAL AutoColl is included. */
#define NXPBUILD__PHAC_DISCLOOP_TYPEF424_TARGET_PASSIVE/**< SRC to Initialize Type F424 passive listen config and subsequently call HAL AutoColl is included. */
#define NXPBUILD__PHAC_DISCLOOP_TYPEF424_TARGET_ACTIVE /**< SRC to Initialize Type F424 active listen config and subsequently call HAL AutoColl is included. */
#endif /* NXPBUILD__PHHAL_HW_TARGET */
#endif
#endif /* NXPBUILD__PHAC_DISCLOOP_SW */
/*********************************************************************************************************************************************************************************/
#define NXPBUILD__PHNFCLIB /**< Simplified API Interface, If enabling this the entry point should be this component in the application */
/*********************************************************************************************************************************************************************************/
//#define NXPBUILD__PH_CIDMANAGER_SW /**< CID Manager SW Component is included. */
#define NXPBUILD__PH_KEYSTORE_SW /**< SW KeyStore Component is included. */
#if defined(NXPBUILD__PHHAL_HW_RC663) && !defined(NXPBUILD__PH_KEYSTORE_SW)
#define NXPBUILD__PH_KEYSTORE_RC663 /**< RC663 KeyStore Component is included. */
#endif
//#define NXPBUILD__PH_NDA_MFDF /**< MIFARE DESFire contactless IC */
//#define NXPBUILD__PH_CRYPTOSYM_SW /**< Crypto Symbols SW Component is included. */
//#define NXPBUILD__PH_CRYPTORNG_SW /**< Crypto RNG SW Component is included. */
/*********************************************************************************************************************************************************************************/
#ifdef NXPBUILD__PHPAL_FELICA_SW
#define NXPBUILD__PHAL_FELICA_SW /**< AL FeliCa SW Component is included */
#endif /* NXPBUILD__PHPAL_FELICA_SW */
#ifdef NXPBUILD__PHPAL_MIFARE_SW
#if defined(NXPBUILD__PH_KEYSTORE_SW) || defined(NXPBUILD__PH_KEYSTORE_RC663)
#define NXPBUILD__PHAL_MFC_SW /**< AL MIFARE Classic contactless IC SW Component is included */
#endif
// #define NXPBUILD__PHAL_MFUL_SW /**< AL Mifare Ultrlight SW Component is included */
// #define NXPBUILD__PHAL_MFDF_SW /**< AL Mifare DesFire SW Component is included */
// #define NXPBUILD__PHAL_MFNTAG42XDNA_SW /**< AL MIFARE Prime Ntag42XDna contactless IC SW Component is included */
#endif /* NXPBUILD__PHPAL_MIFARE_SW */
//#define NXPBUILD__PHAL_T1T_SW /**< AL Type T1 Tag SW Component is included */
#ifdef NXPBUILD__PHPAL_SLI15693_SW
#define NXPBUILD__PHAL_ICODE_SW /**< AL ICODE SW COMPONENT is included */
#endif /* NXPBUILD__PHPAL_SLI15693_SW */
//#define NXPBUILD__PHAL_TOP_SW /**< AL for TagOps Mapping SW Component is included.Required for NDEF operations */
#ifdef NXPBUILD__PHPAL_I18000P3M3_SW
#define NXPBUILD__PHAL_I18000P3M3_SW /**< AL ISO18000p3m3 SW Component is included */
#endif /* NXPBUILD__PHPAL_I18000P3M3_SW */
#ifdef NXPBUILD__PHPAL_I14443P4MC_SW
#if !defined(PH_OSAL_NULLOS)
#define NXPBUILD__PHCE_T4T_SW /**< AL HCE T2AT SW Component is included */
//#define NXPBUILD__PHCE_T4T_PROPRIETARY /**< SRC to handle HCE T4AT Proprietary Commands is included */
/*#define NXPBUILD__PHCE_T4T_EXT_NDEF */ /**< SRC to handle Extended NDEF Support as per T4T spec 3.0 is included */
#endif
#endif /* NXPBUILD__PHPAL_I14443P4MC_SW */
/* LLCP Components */
#if defined(NXPBUILD__PHPAL_I18092MPI_SW) || defined(NXPBUILD__PHPAL_I18092MT_SW)
#if !defined(PH_OSAL_NULLOS)
#define NXPBUILD__PHLN_LLCP_SW /**< Link LLCP SW Component is included */
#endif
#endif
/* SNEP components */
#ifdef NXPBUILD__PHLN_LLCP_SW
#define NXPBUILD__PHNP_SNEP_SW /**< Protocol SNEP SW Component is included */
#endif /* NXPBUILD__PHLN_LLCP_SW */
/* Enable/disable Debugging */
/*#define NXPBUILD__PH_DEBUG*/ /**< TODO: To be checked if required */
/** @}
* end of ph_NxpBuild
*/
#endif /* PH_NXPBUILD_APP_H_INC */

View File

@ -0,0 +1,343 @@
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View File

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<comment></comment>
<projects>
<project>FreeRTOS</project>
<project>lpc_board_nxp_lpcxpresso_1769</project>
<project>lpc_chip_175x_6x</project>
<project>NxpNfcRdLib</project>
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View File

@ -0,0 +1,493 @@
//*****************************************************************************
// LPC175x_6x Microcontroller Startup code for use with LPCXpresso IDE
//
// Version : 140114
//*****************************************************************************
//
// Copyright(C) NXP Semiconductors, 2014
// All rights reserved.
//
// Software that is described herein is for illustrative purposes only
// which provides customers with programming information regarding the
// LPC products. This software is supplied "AS IS" without any warranties of
// any kind, and NXP Semiconductors and its licensor disclaim any and
// all warranties, express or implied, including all implied warranties of
// merchantability, fitness for a particular purpose and non-infringement of
// intellectual property rights. NXP Semiconductors assumes no responsibility
// or liability for the use of the software, conveys no license or rights under any
// patent, copyright, mask work right, or any other intellectual property rights in
// or to any products. NXP Semiconductors reserves the right to make changes
// in the software without notification. NXP Semiconductors also makes no
// representation or warranty that such application will be suitable for the
// specified use without further testing or modification.
//
// Permission to use, copy, modify, and distribute this software and its
// documentation is hereby granted, under NXP Semiconductors' and its
// licensor's relevant copyrights in the software, without fee, provided that it
// is used in conjunction with NXP Semiconductors microcontrollers. This
// copyright, permission, and disclaimer notice must appear in all copies of
// this code.
//*****************************************************************************
#include <ph_Status.h>
#include <cr_section_macros.h>
#include <NXP/crp.h>
#ifdef DEBUG
# define VT_IMAGE_LENGTH 0x76706b64U
#else /* DEBUG */
# define VT_IMAGE_LENGTH 0xFFFFFFFFU
#endif /* DEBUG */
#if defined (__cplusplus)
#ifdef __REDLIB__
#error Redlib does not support C++
#else
//*****************************************************************************
//
// The entry point for the C++ library startup
//
//*****************************************************************************
extern "C" {
extern void __libc_init_array(void);
}
#endif
#endif
#define WEAK __attribute__ ((weak))
#define ALIAS(f) __attribute__ ((weak, alias (#f)))
__CRP const unsigned int CRP_WORD = CRP_NO_CRP;
//*****************************************************************************
#if defined (__cplusplus)
extern "C" {
#endif
//*****************************************************************************
#if defined (__USE_CMSIS) || defined (__USE_LPCOPEN)
// Declaration of external SystemInit function
void SystemInit(void);
extern void Board_SystemInit(void);
extern void Chip_SystemInit(void);
extern void SystemCoreClockUpdate(void);
#endif
//*****************************************************************************
//
// Forward declaration of the default handlers. These are aliased.
// When the application defines a handler (with the same name), this will
// automatically take precedence over these weak definitions
//
//*****************************************************************************
void ResetISR(void);
WEAK void NMI_Handler(void);
//WEAK void HardFault_Handler(void);
WEAK void MemManage_Handler(void);
WEAK void BusFault_Handler(void);
WEAK void UsageFault_Handler(void);
WEAK void SVC_Handler(void);
WEAK void DebugMon_Handler(void);
WEAK void PendSV_Handler(void);
WEAK void SysTick_Handler(void);
WEAK void IntDefaultHandler(void);
/* The prototype shows it is a naked function - in effect this is just an
assembly function. */
void HardFault_Handler( void ) __attribute__( ( naked ) );
//*****************************************************************************
//
// Forward declaration of the specific IRQ handlers. These are aliased
// to the IntDefaultHandler, which is a 'forever' loop. When the application
// defines a handler (with the same name), this will automatically take
// precedence over these weak definitions
//
//*****************************************************************************
void WDT_IRQHandler(void) ALIAS(IntDefaultHandler);
void TIMER0_IRQHandler(void) ALIAS(IntDefaultHandler);
void TIMER1_IRQHandler(void) ALIAS(IntDefaultHandler);
void TIMER2_IRQHandler(void) ALIAS(IntDefaultHandler);
void TIMER3_IRQHandler(void) ALIAS(IntDefaultHandler);
void UART0_IRQHandler(void) ALIAS(IntDefaultHandler);
void UART1_IRQHandler(void) ALIAS(IntDefaultHandler);
void UART2_IRQHandler(void) ALIAS(IntDefaultHandler);
void UART3_IRQHandler(void) ALIAS(IntDefaultHandler);
void PWM1_IRQHandler(void) ALIAS(IntDefaultHandler);
void I2C0_IRQHandler(void) ALIAS(IntDefaultHandler);
void I2C1_IRQHandler(void) ALIAS(IntDefaultHandler);
void I2C2_IRQHandler(void) ALIAS(IntDefaultHandler);
void SPI_IRQHandler(void) ALIAS(IntDefaultHandler);
void SSP0_IRQHandler(void) ALIAS(IntDefaultHandler);
void SSP1_IRQHandler(void) ALIAS(IntDefaultHandler);
void PLL0_IRQHandler(void) ALIAS(IntDefaultHandler);
void RTC_IRQHandler(void) ALIAS(IntDefaultHandler);
void EINT0_IRQHandler(void) ALIAS(IntDefaultHandler);
void EINT1_IRQHandler(void) ALIAS(IntDefaultHandler);
void EINT2_IRQHandler(void) ALIAS(IntDefaultHandler);
void CLIF_IRQHandler(void) ALIAS(IntDefaultHandler);
void ADC_IRQHandler(void) ALIAS(IntDefaultHandler);
void BOD_IRQHandler(void) ALIAS(IntDefaultHandler);
void USB_IRQHandler(void) ALIAS(IntDefaultHandler);
void CAN_IRQHandler(void) ALIAS(IntDefaultHandler);
void DMA_IRQHandler(void) ALIAS(IntDefaultHandler);
void I2S_IRQHandler(void) ALIAS(IntDefaultHandler);
#if defined (__USE_LPCOPEN)
void ETH_IRQHandler(void) ALIAS(IntDefaultHandler);
#else
void ENET_IRQHandler(void) ALIAS(IntDefaultHandler);
#endif
void RIT_IRQHandler(void) ALIAS(IntDefaultHandler);
void MCPWM_IRQHandler(void) ALIAS(IntDefaultHandler);
void QEI_IRQHandler(void) ALIAS(IntDefaultHandler);
void PLL1_IRQHandler(void) ALIAS(IntDefaultHandler);
void USBActivity_IRQHandler(void) ALIAS(IntDefaultHandler);
void CANActivity_IRQHandler(void) ALIAS(IntDefaultHandler);
void UART4_IRQHandler(void) ALIAS(IntDefaultHandler);
void SSP2_IRQHandler(void) ALIAS(IntDefaultHandler);
void LCD_IRQHandler(void) ALIAS(IntDefaultHandler);
void GPIO_IRQHandler(void) ALIAS(IntDefaultHandler);
void PWM0_IRQHandler(void) ALIAS(IntDefaultHandler);
void EEPROM_IRQHandler(void) ALIAS(IntDefaultHandler);
//*****************************************************************************
//
// The entry point for the application.
// __main() is the entry point for Redlib based applications
// main() is the entry point for Newlib based applications
//
//*****************************************************************************
#if defined (__REDLIB__)
extern void __main(void);
#endif
extern int main(void);
//*****************************************************************************
//
// External declaration for the pointer to the stack top from the Linker Script
//
//*****************************************************************************
extern void _vStackTop(void);
//*****************************************************************************
#if defined (__cplusplus)
} // extern "C"
#endif
//*****************************************************************************
//
// The vector table.
// This relies on the linker script to place at correct location in memory.
//
//*****************************************************************************
extern void (* const g_pfnVectors[])(void);
__attribute__ ((section(".isr_vector")))
void (* const g_pfnVectors[])(void) = {
// Core Level - CM3
&_vStackTop, // The initial stack pointer
ResetISR, // The reset handler
NMI_Handler, // The NMI handler
HardFault_Handler, // The hard fault handler
MemManage_Handler, // The MPU fault handler
BusFault_Handler, // The bus fault handler
UsageFault_Handler, // The usage fault handler
0, // Reserved
0, // Reserved
0, // Reserved
0, // Reserved
SVC_Handler, // SVCall handler
DebugMon_Handler, // Debug monitor handler
0, // Reserved
PendSV_Handler, // The PendSV handler
SysTick_Handler, // The SysTick handler
// Chip Level - LPC17
WDT_IRQHandler, // 16, 0x40 - WDT
TIMER0_IRQHandler, // 17, 0x44 - TIMER0
TIMER1_IRQHandler, // 18, 0x48 - TIMER1
TIMER2_IRQHandler, // 19, 0x4c - TIMER2
TIMER3_IRQHandler, // 20, 0x50 - TIMER3
UART0_IRQHandler, // 21, 0x54 - UART0
UART1_IRQHandler, // 22, 0x58 - UART1
UART2_IRQHandler, // 23, 0x5c - UART2
UART3_IRQHandler, // 24, 0x60 - UART3
PWM1_IRQHandler, // 25, 0x64 - PWM1
I2C0_IRQHandler, // 26, 0x68 - I2C0
I2C1_IRQHandler, // 27, 0x6c - I2C1
I2C2_IRQHandler, // 28, 0x70 - I2C2
SPI_IRQHandler, // 29, 0x74 - SPI
SSP0_IRQHandler, // 30, 0x78 - SSP0
SSP1_IRQHandler, // 31, 0x7c - SSP1
PLL0_IRQHandler, // 32, 0x80 - PLL0 (Main PLL)
RTC_IRQHandler, // 33, 0x84 - RTC
EINT0_IRQHandler, // 34, 0x88 - EINT0
EINT1_IRQHandler, // 35, 0x8c - EINT1
EINT2_IRQHandler, // 36, 0x90 - EINT2
CLIF_IRQHandler, // 37, 0x94 - EINT3 (Used for CLIF IRQ)
ADC_IRQHandler, // 38, 0x98 - ADC
BOD_IRQHandler, // 39, 0x9c - BOD
USB_IRQHandler, // 40, 0xA0 - USB
CAN_IRQHandler, // 41, 0xa4 - CAN
DMA_IRQHandler, // 42, 0xa8 - GP DMA
I2S_IRQHandler, // 43, 0xac - I2S
#if defined (__USE_LPCOPEN)
ETH_IRQHandler, // 44, 0xb0 - Ethernet
#else
ENET_IRQHandler, // 44, 0xb0 - Ethernet
#endif
RIT_IRQHandler, // 45, 0xb4 - RITINT
MCPWM_IRQHandler, // 46, 0xb8 - Motor Control PWM
QEI_IRQHandler, // 47, 0xbc - Quadrature Encoder
PLL1_IRQHandler, // 48, 0xc0 - PLL1 (USB PLL)
USBActivity_IRQHandler, // 49, 0xc4 - USB Activity interrupt to wakeup
CANActivity_IRQHandler, // 50, 0xc8 - CAN Activity interrupt to wakeup
UART4_IRQHandler, //; 51 UART4
SSP2_IRQHandler, //; 52 SSP2
LCD_IRQHandler, //; 53 LCD
GPIO_IRQHandler, //; 54 GPIO
PWM0_IRQHandler , //; 55 PWM0
EEPROM_IRQHandler, //; 56 EEPROM
(void *)VT_IMAGE_LENGTH, //; 57 VT Checksum for CRC Check of Vector Table.
};
//*****************************************************************************
// Functions to carry out the initialization of RW and BSS data sections. These
// are written as separate functions rather than being inlined within the
// ResetISR() function in order to cope with MCUs with multiple banks of
// memory.
//*****************************************************************************
__attribute__ ((section(".after_vectors")))
void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
unsigned int *pulDest = (unsigned int*) start;
unsigned int *pulSrc = (unsigned int*) romstart;
unsigned int loop;
for (loop = 0; loop < len; loop = loop + 4)
*pulDest++ = *pulSrc++;
}
__attribute__ ((section(".after_vectors")))
void bss_init(unsigned int start, unsigned int len) {
unsigned int *pulDest = (unsigned int*) start;
unsigned int loop;
for (loop = 0; loop < len; loop = loop + 4)
*pulDest++ = 0;
}
//*****************************************************************************
// The following symbols are constructs generated by the linker, indicating
// the location of various points in the "Global Section Table". This table is
// created by the linker via the Code Red managed linker script mechanism. It
// contains the load address, execution address and length of each RW data
// section and the execution and length of each BSS (zero initialized) section.
//*****************************************************************************
extern unsigned int __data_section_table;
extern unsigned int __data_section_table_end;
extern unsigned int __bss_section_table;
extern unsigned int __bss_section_table_end;
//*****************************************************************************
// Reset entry point for your code.
// Sets up a simple runtime environment and initializes the C/C++
// library.
//*****************************************************************************
__attribute__ ((section(".after_vectors")))
void
ResetISR(void) {
//
// Copy the data sections from flash to SRAM.
//
unsigned int LoadAddr, ExeAddr, SectionLen;
unsigned int *SectionTableAddr;
// Load base address of Global Section Table
SectionTableAddr = &__data_section_table;
// Copy the data sections from flash to SRAM.
while (SectionTableAddr < &__data_section_table_end) {
LoadAddr = *SectionTableAddr++;
ExeAddr = *SectionTableAddr++;
SectionLen = *SectionTableAddr++;
data_init(LoadAddr, ExeAddr, SectionLen);
}
// At this point, SectionTableAddr = &__bss_section_table;
// Zero fill the bss segment
while (SectionTableAddr < &__bss_section_table_end) {
ExeAddr = *SectionTableAddr++;
SectionLen = *SectionTableAddr++;
bss_init(ExeAddr, SectionLen);
}
#if defined (__USE_CMSIS) || defined (__USE_LPCOPEN)
SystemInit();
#endif
#if defined (__cplusplus)
//
// Call C++ library initialisation
//
__libc_init_array();
#endif
#if defined (__REDLIB__)
// Call the Redlib library, which in turn calls main()
__main() ;
#else
main();
#endif
//
// main() shouldn't return, but if it does, we'll just enter an infinite loop
//
while (1) {
;
}
}
/* Set up and initialize hardware prior to call to main */
void SystemInit(void)
{
unsigned int *pSCB_VTOR = (unsigned int *) 0xE000ED08;
#if defined(__IAR_SYSTEMS_ICC__)
extern void *__vector_table;
*pSCB_VTOR = (unsigned int) &__vector_table;
#elif defined(__CODE_RED)
*pSCB_VTOR = (unsigned int) &g_pfnVectors;
#elif defined(__ARMCC_VERSION)
extern void *__Vectors;
*pSCB_VTOR = (unsigned int) &__Vectors;
#endif
#if defined(__FPU_PRESENT) && __FPU_PRESENT == 1
fpuInit();
#endif
#if defined(NO_BOARD_LIB)
/* Chip specific SystemInit */
Chip_SystemInit();
#else
/* Setup system clocking and muxing */
Board_SystemInit();
#endif
/* Update system core clock rate. */
SystemCoreClockUpdate();
}
//*****************************************************************************
// Default exception handlers. Override the ones here by defining your own
// handler routines in your application code.
//*****************************************************************************
__attribute__ ((section(".after_vectors")))
void NMI_Handler(void)
{ while(1) {}
}
/* The fault handler implementation calls a function called
prvGetRegistersFromStack(). */
__attribute__ ((section(".after_vectors")))
void HardFault_Handler(void)
{
/* Use assembly to pick up date, but feed to C Code. */
__asm( ".syntax divided\n"
"MOVS R0, #4 \n"
"MOV R1, LR \n"
"TST R0, R1 \n"
"BEQ _MSP \n"
"MRS R0, PSP \n"
"B HardFault_HandlerC \n"
"_MSP: \n"
"MRS R0, MSP \n"
"B HardFault_HandlerC \n"
".syntax divided\n") ;
__asm(".syntax unified");
}
__attribute__ ((section(".after_vectors")))
void HardFault_HandlerC(
unsigned long *args)
{
volatile unsigned long cm_r0;
volatile unsigned long cm_r1;
volatile unsigned long cm_r2;
volatile unsigned long cm_r3;
volatile unsigned long cm_r12;
volatile unsigned long cm_lr;
volatile unsigned long cm_pc;
volatile unsigned long cm_psr;
//if (((uint32_t) args < PH_RAM_MEM_END)&& ( (uint32_t)args > PH_RAM_MEM_START))
//0x10000000 -- 0x8000
//0x2007c000 -- 0x8000
{
cm_r0 = ((unsigned long)args[0]);
cm_r1 = ((unsigned long)args[1]);
cm_r2 = ((unsigned long)args[2]);
cm_r3 = ((unsigned long)args[3]);
cm_r12 = ((unsigned long)args[4]);
cm_lr = ((unsigned long)args[5]);
cm_pc = ((unsigned long)args[6]);
cm_psr = ((unsigned long)args[7]);
PH_UNUSED_VARIABLE(cm_r0);
PH_UNUSED_VARIABLE(cm_r1);
PH_UNUSED_VARIABLE(cm_r2);
PH_UNUSED_VARIABLE(cm_r3);
PH_UNUSED_VARIABLE(cm_r12);
PH_UNUSED_VARIABLE(cm_lr);
PH_UNUSED_VARIABLE(cm_pc);
PH_UNUSED_VARIABLE(cm_psr);
}
/* Break into the debugger */
__asm("BKPT #0\n");
while (1)
{
__asm("wfi\n");
}
}
__attribute__ ((section(".after_vectors")))
void MemManage_Handler(void)
{ while(1) {}
}
__attribute__ ((section(".after_vectors")))
void BusFault_Handler(void)
{ while(1) {}
}
__attribute__ ((section(".after_vectors")))
void UsageFault_Handler(void)
{ while(1) {}
}
__attribute__ ((section(".after_vectors")))
void SVC_Handler(void)
{ while(1) {}
}
__attribute__ ((section(".after_vectors")))
void DebugMon_Handler(void)
{ while(1) {}
}
__attribute__ ((section(".after_vectors")))
void PendSV_Handler(void)
{ while(1) {}
}
//*****************************************************************************
//
// Processor ends up here if an unexpected interrupt occurs or a specific
// handler is not present in the application code.
//
//*****************************************************************************
__attribute__ ((section(".after_vectors")))
void IntDefaultHandler(void)
{ while(1) {}
}

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/*----------------------------------------------------------------------------*/
/* Copyright 2020 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may only */
/* be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that you */
/* have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*----------------------------------------------------------------------------*/
/** \file
* Example Source abstracting component data structure and code initialization and code specific to HW used in the examples
* This file shall be present in all examples. A customer does not need to touch/modify this file. This file
* purely depends on the phNxpBuild_Lpc.h or phNxpBuild_App.h
* The phAppInit.h externs the component data structures initialized here that is in turn included by the core examples.
* The core example shall not use any other variable defined here except the RdLib component data structures(as explained above)
* The RdLib component initialization requires some user defined data and function pointers.
* These are defined in the respective examples and externed here.
*
* Keystore and Crypto initialization needs to be handled by application.
*
* $Author$
* $Revision$ (v07.10.00)
* $Date$
*
*/
#include "phApp_Init.h"
#include <phOsal.h>
/*******************************************************************************
** Function Declarations
*******************************************************************************/
/*******************************************************************************
** Function Definitions
*******************************************************************************/
/* Print technology being resolved */
void phApp_PrintTech(uint8_t TechType)
{
switch(TechType)
{
case PHAC_DISCLOOP_POS_BIT_MASK_A:
DEBUG_PRINTF ("\tResolving Type A... \n");
break;
case PHAC_DISCLOOP_POS_BIT_MASK_B:
DEBUG_PRINTF ("\tResolving Type B... \n");
break;
case PHAC_DISCLOOP_POS_BIT_MASK_F212:
DEBUG_PRINTF ("\tResolving Type F with baud rate 212... \n");
break;
case PHAC_DISCLOOP_POS_BIT_MASK_F424:
DEBUG_PRINTF ("\tResolving Type F with baud rate 424... \n");
break;
case PHAC_DISCLOOP_POS_BIT_MASK_V:
DEBUG_PRINTF ("\tResolving Type V... \n");
break;
default:
break;
}
}
/**
* This function will print buffer content
* \param *pBuff Buffer Reference
* \param num data size to be print
*/
void phApp_Print_Buff(uint8_t *pBuff, uint8_t num)
{
uint32_t i;
for(i = 0; i < num; i++)
{
DEBUG_PRINTF(" %02X",pBuff[i]);
}
}
/**
* This function will print Tag information
* \param pDataParams The discovery loop data parameters
* \param wNumberOfTags Total number of tags detected
* \param wTagsDetected Technology Detected
*/
void phApp_PrintTagInfo(phacDiscLoop_Sw_DataParams_t *pDataParams, uint16_t wNumberOfTags, uint16_t wTagsDetected)
{
#if defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_TAGS) || \
defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_P2P_ACTIVE) || \
defined(NXPBUILD__PHAC_DISCLOOP_TYPEB_TAGS) || \
defined(NXPBUILD__PHAC_DISCLOOP_TYPEF_TAGS) || \
defined(NXPBUILD__PHAC_DISCLOOP_TYPEV_TAGS) || \
defined(NXPBUILD__PHAC_DISCLOOP_I18000P3M3_TAGS)
uint8_t bIndex;
#endif
#if defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_TAGS) || defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_P2P_ACTIVE)
uint8_t bTagType;
#endif
#if defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_TAGS) || defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_P2P_ACTIVE)
if (PHAC_DISCLOOP_CHECK_ANDMASK(wTagsDetected, PHAC_DISCLOOP_POS_BIT_MASK_A))
{
if(pDataParams->sTypeATargetInfo.bT1TFlag)
{
DEBUG_PRINTF("\tTechnology : Type A");
DEBUG_PRINTF ("\n\t\tUID :");
phApp_Print_Buff( pDataParams->sTypeATargetInfo.aTypeA_I3P3[0].aUid,
pDataParams->sTypeATargetInfo.aTypeA_I3P3[0].bUidSize);
DEBUG_PRINTF ("\n\t\tSAK : 0x%02x",pDataParams->sTypeATargetInfo.aTypeA_I3P3[0].aSak);
DEBUG_PRINTF ("\n\t\tType: Type 1 Tag\n");
}
else
{
DEBUG_PRINTF("\tTechnology : Type A");
for(bIndex = 0; bIndex < wNumberOfTags; bIndex++)
{
DEBUG_PRINTF ("\n\t\tCard: %d",bIndex + 1);
DEBUG_PRINTF ("\n\t\tUID :");
phApp_Print_Buff( pDataParams->sTypeATargetInfo.aTypeA_I3P3[bIndex].aUid,
pDataParams->sTypeATargetInfo.aTypeA_I3P3[bIndex].bUidSize);
DEBUG_PRINTF ("\n\t\tSAK : 0x%02x",pDataParams->sTypeATargetInfo.aTypeA_I3P3[bIndex].aSak);
if ((pDataParams->sTypeATargetInfo.aTypeA_I3P3[bIndex].aSak & (uint8_t) ~0xFB) == 0)
{
/* Bit b3 is set to zero, [Digital] 4.8.2 */
/* Mask out all other bits except for b7 and b6 */
bTagType = (pDataParams->sTypeATargetInfo.aTypeA_I3P3[bIndex].aSak & 0x60);
bTagType = bTagType >> 5;
switch(bTagType)
{
case PHAC_DISCLOOP_TYPEA_TYPE2_TAG_CONFIG_MASK:
DEBUG_PRINTF ("\n\t\tType: Type 2 Tag\n");
break;
case PHAC_DISCLOOP_TYPEA_TYPE4A_TAG_CONFIG_MASK:
DEBUG_PRINTF ("\n\t\tType: Type 4A Tag\n");
break;
case PHAC_DISCLOOP_TYPEA_TYPE_NFC_DEP_TAG_CONFIG_MASK:
DEBUG_PRINTF ("\n\t\tType: P2P\n");
break;
case PHAC_DISCLOOP_TYPEA_TYPE_NFC_DEP_TYPE4A_TAG_CONFIG_MASK:
DEBUG_PRINTF ("\n\t\tType: Type NFC_DEP and 4A Tag\n");
break;
default:
break;
}
}
}
}
}
#endif
#ifdef NXPBUILD__PHAC_DISCLOOP_TYPEB_TAGS
if (PHAC_DISCLOOP_CHECK_ANDMASK(wTagsDetected, PHAC_DISCLOOP_POS_BIT_MASK_B))
{
DEBUG_PRINTF("\tTechnology : Type B");
/* Loop through all the Type B tags detected and print the Pupi */
for (bIndex = 0; bIndex < wNumberOfTags; bIndex++)
{
DEBUG_PRINTF ("\n\t\tCard: %d",bIndex + 1);
DEBUG_PRINTF ("\n\t\tUID :");
/* PUPI Length is always 4 bytes */
phApp_Print_Buff( pDataParams->sTypeBTargetInfo.aTypeB_I3P3[bIndex].aPupi, 0x04);
}
DEBUG_PRINTF("\n");
}
#endif /* NXPBUILD__PHAC_DISCLOOP_TYPEB_TAGS */
#ifdef NXPBUILD__PHAC_DISCLOOP_TYPEF_TAGS
if( PHAC_DISCLOOP_CHECK_ANDMASK(wTagsDetected, PHAC_DISCLOOP_POS_BIT_MASK_F212) ||
PHAC_DISCLOOP_CHECK_ANDMASK(wTagsDetected, PHAC_DISCLOOP_POS_BIT_MASK_F424))
{
DEBUG_PRINTF("\tTechnology : Type F");
/* Loop through all the type F tags and print the IDm */
for (bIndex = 0; bIndex < wNumberOfTags; bIndex++)
{
DEBUG_PRINTF ("\n\t\tCard: %d",bIndex + 1);
DEBUG_PRINTF ("\n\t\tUID :");
phApp_Print_Buff( pDataParams->sTypeFTargetInfo.aTypeFTag[bIndex].aIDmPMm,
PHAC_DISCLOOP_FELICA_IDM_LENGTH );
if ((pDataParams->sTypeFTargetInfo.aTypeFTag[bIndex].aIDmPMm[0] == 0x01) &&
(pDataParams->sTypeFTargetInfo.aTypeFTag[bIndex].aIDmPMm[1] == 0xFE))
{
/* This is Type F tag with P2P capabilities */
DEBUG_PRINTF ("\n\t\tType: P2P");
}
else
{
/* This is Type F T3T tag */
DEBUG_PRINTF ("\n\t\tType: Type 3 Tag");
}
if(pDataParams->sTypeFTargetInfo.aTypeFTag[bIndex].bBaud != PHAC_DISCLOOP_CON_BITR_212)
{
DEBUG_PRINTF ("\n\t\tBit Rate: 424\n");
}
else
{
DEBUG_PRINTF ("\n\t\tBit Rate: 212\n");
}
}
}
#endif /* NXPBUILD__PHAC_DISCLOOP_TYPEF_TAGS */
#ifdef NXPBUILD__PHAC_DISCLOOP_TYPEV_TAGS
if (PHAC_DISCLOOP_CHECK_ANDMASK(wTagsDetected, PHAC_DISCLOOP_POS_BIT_MASK_V))
{
DEBUG_PRINTF("\tTechnology : Type V / ISO 15693 / T5T");
/* Loop through all the Type V tags detected and print the UIDs */
for (bIndex = 0; bIndex < wNumberOfTags; bIndex++)
{
DEBUG_PRINTF ("\n\t\tCard: %d",bIndex + 1);
DEBUG_PRINTF ("\n\t\tUID :");
phApp_Print_Buff( pDataParams->sTypeVTargetInfo.aTypeV[bIndex].aUid, 0x08);
}
DEBUG_PRINTF("\n");
}
#endif /* NXPBUILD__PHAC_DISCLOOP_TYPEV_TAGS */
#ifdef NXPBUILD__PHAC_DISCLOOP_I18000P3M3_TAGS
if (PHAC_DISCLOOP_CHECK_ANDMASK(wTagsDetected, PHAC_DISCLOOP_POS_BIT_MASK_18000P3M3))
{
DEBUG_PRINTF("\tTechnology : ISO 18000p3m3 / EPC Gen2");
/* Loop through all the 18000p3m3 tags detected and print the UII */
for (bIndex = 0; bIndex < wNumberOfTags; bIndex++)
{
DEBUG_PRINTF("\n\t\tCard: %d",bIndex + 1);
DEBUG_PRINTF("\n\t\tUII :");
phApp_Print_Buff(
pDataParams->sI18000p3m3TargetInfo.aI18000p3m3[bIndex].aUii,
(pDataParams->sI18000p3m3TargetInfo.aI18000p3m3[bIndex].wUiiLength / 8));
}
DEBUG_PRINTF("\n");
}
#endif /* NXPBUILD__PHAC_DISCLOOP_I18000P3M3_TAGS */
}
/**
* This function will print Error information received from Reader Lib
* \param wStatus Error status
*/
void PrintErrorInfo(phStatus_t wStatus)
{
DEBUG_PRINTF("\n ErrorInfo Comp:");
switch(wStatus & 0xFF00)
{
case PH_COMP_BAL:
DEBUG_PRINTF("\t PH_COMP_BAL");
break;
case PH_COMP_HAL:
DEBUG_PRINTF("\t PH_COMP_HAL");
break;
case PH_COMP_PAL_ISO14443P3A:
DEBUG_PRINTF("\t PH_COMP_PAL_ISO14443P3A");
break;
case PH_COMP_PAL_ISO14443P3B:
DEBUG_PRINTF("\t PH_COMP_PAL_ISO14443P3B");
break;
case PH_COMP_PAL_ISO14443P4A:
DEBUG_PRINTF("\t PH_COMP_PAL_ISO14443P4A");
break;
case PH_COMP_PAL_ISO14443P4:
DEBUG_PRINTF("\t PH_COMP_PAL_ISO14443P4");
break;
case PH_COMP_PAL_FELICA:
DEBUG_PRINTF("\t PH_COMP_PAL_FELICA");
break;
case PH_COMP_PAL_EPCUID:
DEBUG_PRINTF("\t PH_COMP_PAL_EPCUID");
break;
case PH_COMP_PAL_SLI15693:
DEBUG_PRINTF("\t PH_COMP_PAL_SLI15693");
break;
case PH_COMP_PAL_I18000P3M3:
DEBUG_PRINTF("\t PH_COMP_PAL_I18000P3M3");
break;
case PH_COMP_PAL_I18092MPI:
DEBUG_PRINTF("\t PH_COMP_PAL_I18092MPI");
break;
case PH_COMP_PAL_I18092MT:
DEBUG_PRINTF("\t PH_COMP_PAL_I18092MT");
break;
case PH_COMP_PAL_I14443P4MC:
DEBUG_PRINTF("\t PH_COMP_PAL_I14443P4MC");
break;
case PH_COMP_AC_DISCLOOP:
DEBUG_PRINTF("\t PH_COMP_AC_DISCLOOP");
break;
case PH_COMP_OSAL:
DEBUG_PRINTF("\t PH_COMP_OSAL");
break;
default:
DEBUG_PRINTF("\t 0x%x",(wStatus & PH_COMPID_MASK));
break;
}
DEBUG_PRINTF("\t type:");
switch(wStatus & PH_ERR_MASK)
{
case PH_ERR_SUCCESS_INCOMPLETE_BYTE:
DEBUG_PRINTF("\t PH_ERR_SUCCESS_INCOMPLETE_BYTE");
break;
case PH_ERR_IO_TIMEOUT:
DEBUG_PRINTF("\t PH_ERR_IO_TIMEOUT");
break;
case PH_ERR_INTEGRITY_ERROR:
DEBUG_PRINTF("\t PH_ERR_INTEGRITY_ERROR");
break;
case PH_ERR_COLLISION_ERROR:
DEBUG_PRINTF("\t PH_ERR_COLLISION_ERROR");
break;
case PH_ERR_BUFFER_OVERFLOW:
DEBUG_PRINTF("\t PH_ERR_BUFFER_OVERFLOW");
break;
case PH_ERR_FRAMING_ERROR:
DEBUG_PRINTF("\t PH_ERR_FRAMING_ERROR");
break;
case PH_ERR_PROTOCOL_ERROR:
DEBUG_PRINTF("\t PH_ERR_PROTOCOL_ERROR");
break;
case PH_ERR_RF_ERROR:
DEBUG_PRINTF("\t PH_ERR_RF_ERROR");
break;
case PH_ERR_EXT_RF_ERROR:
DEBUG_PRINTF("\t PH_ERR_EXT_RF_ERROR");
break;
case PH_ERR_NOISE_ERROR:
DEBUG_PRINTF("\t PH_ERR_NOISE_ERROR");
break;
case PH_ERR_ABORTED:
DEBUG_PRINTF("\t PH_ERR_ABORTED");
break;
case PH_ERR_INTERNAL_ERROR:
DEBUG_PRINTF("\t PH_ERR_INTERNAL_ERROR");
break;
case PH_ERR_INVALID_DATA_PARAMS:
DEBUG_PRINTF("\t PH_ERR_INVALID_DATA_PARAMS");
break;
case PH_ERR_INVALID_PARAMETER:
DEBUG_PRINTF("\t PH_ERR_INVALID_PARAMETER");
break;
case PH_ERR_PARAMETER_OVERFLOW:
DEBUG_PRINTF("\t PH_ERR_PARAMETER_OVERFLOW");
break;
case PH_ERR_UNSUPPORTED_PARAMETER:
DEBUG_PRINTF("\t PH_ERR_UNSUPPORTED_PARAMETER");
break;
case PH_ERR_OSAL_ERROR:
DEBUG_PRINTF("\t PH_ERR_OSAL_ERROR");
break;
case PHAC_DISCLOOP_LPCD_NO_TECH_DETECTED:
DEBUG_PRINTF("\t PHAC_DISCLOOP_LPCD_NO_TECH_DETECTED");
break;
case PHAC_DISCLOOP_COLLISION_PENDING:
DEBUG_PRINTF("\t PHAC_DISCLOOP_COLLISION_PENDING");
break;
default:
DEBUG_PRINTF("\t 0x%x",(wStatus & PH_ERR_MASK));
break;
}
}
/******************************************************************************
** End Of File
******************************************************************************/

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/*----------------------------------------------------------------------------*/
/* Copyright 2016-2020,2022 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may only */
/* be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that you */
/* have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*----------------------------------------------------------------------------*/
/** \file
* Example Source abstracting component data structure and code initialization and code specific to HW used in the examples
* This file shall be present in all examples. A customer does not need to touch/modify this file. This file
* purely depends on the phNxpBuild_Lpc.h or phNxpBuild_App.h
* The phAppInit.h externs the component data structures initialized here that is in turn included by the core examples.
* The core example shall not use any other variable defined here except the RdLib component data structures(as explained above)
* The RdLib component initialization requires some user defined data and function pointers.
* These are defined in the respective examples and externed here.
*
* Keystore and Crypto initialization needs to be handled by application.
*
* $Author$
* $Revision$ (v07.10.00)
* $Date$
*
*/
/* Status header */
#include <ph_Status.h>
#include "phApp_Init.h"
/* LLCP header */
#include <phlnLlcp.h>
#include <phOsal.h>
#ifdef PH_PLATFORM_HAS_ICFRONTEND
#include "BoardSelection.h"
#endif
#ifdef PHDRIVER_KINETIS_K82
#include <fsl_port.h>
#include <fsl_pit.h>
#ifdef DEBUG
#include <fsl_clock.h>
#endif /* DEBUG */
#endif /* PHDRIVER_KINETIS_K82 */
#ifdef PHDRIVER_KINETIS_K82
#ifdef DEBUG
#define KINETIS_K82_DEBUG_UART_CLK_FREQ CLOCK_GetOsc0ErClkFreq()
#define KINETIS_K82_DEBUG_UART_BASEADDR (uint32_t)(LPUART4)
#define KINETIS_K82_DEBUG_UART_INSTANCE 4U
#define KINETIS_K82_DEBUG_UART_BAUDRATE 115200
#define KINETIS_K82_DEBUG_UART_TYPE DEBUG_CONSOLE_DEVICE_TYPE_LPUART
#endif /* DEBUG */
/*! @brief Clock configuration structure. */
typedef struct _clock_config
{
mcg_config_t mcgConfig; /*!< MCG configuration. */
sim_clock_config_t simConfig; /*!< SIM configuration. */
osc_config_t oscConfig; /*!< OSC configuration. */
uint32_t coreClock; /*!< core clock frequency. */
} clock_config_t;
#endif /* PHDRIVER_KINETIS_K82 */
#ifdef PH_OSAL_LINUX
# define PI_IRQ_POLLING_TASK_PRIO 0
# define PI_IRQ_POLLING_TASK_STACK 0x20000
phOsal_ThreadObj_t gphPiThreadObj;
#endif /* PH_OSAL_LINUX */
#if defined(PHDRIVER_LPC1769) && defined(__CC_ARM)
uint32_t SystemCoreClock;
#endif
/*******************************************************************************
** Function Declarations
*******************************************************************************/
#ifdef PHDRIVER_KINETIS_K82
static void phApp_K82_Init(void);
#endif /* PHDRIVER_KINETIS_K82 */
#ifdef PH_OSAL_LINUX
static void phExample_IrqPolling(void* param);
#endif /* PH_OSAL_LINUX */
phStatus_t phApp_Configure_IRQ();
/*******************************************************************************
** Clock configuration of K82 Platform
*******************************************************************************/
#ifdef PHDRIVER_KINETIS_K82
/* Configuration for enter RUN mode. Core clock = 50MHz. */
const clock_config_t g_defaultClockConfigRun = {
.mcgConfig =
{
.mcgMode = kMCG_ModePEE, /* Work in PEE mode. */
.irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enable. */
.ircs = kMCG_IrcSlow, /* Select IRC32k. */
.fcrdiv = 0U, /* FCRDIV is 0. */
.frdiv = 4U,
.drs = kMCG_DrsLow, /* Low frequency range. */
.dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25%. */
.oscsel = kMCG_OscselOsc, /* Select OSC. */
.pll0Config =
{
.enableMode = 0U, .prdiv = 0x01U, .vdiv = 0x01U,
},
},
.simConfig =
{
.pllFllSel = 1U, /* PLLFLLSEL select PLL. */
.pllFllDiv = 0U, /* PLLFLLSEL clock divider divisor. */
.pllFllFrac = 0U, /* PLLFLLSEL clock divider fraction. */
.er32kSrc = 5U, /* ERCLK32K selection, use RTC. */
.clkdiv1 = 0x01140000U, /* SIM_CLKDIV1. */
},
.oscConfig = {.freq = CPU_XTAL_CLK_HZ,
.capLoad = 0,
.workMode = kOSC_ModeOscLowPower,
.oscerConfig =
{
.enableMode = kOSC_ErClkEnable,
#if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER)
.erclkDiv = 0U,
#endif
}},
};
#endif /* PHDRIVER_KINETIS_K82 */
/*******************************************************************************
** Global Variable Declaration
*******************************************************************************/
#ifdef NXPBUILD__PHLN_LLCP_SW
phlnLlcp_Sw_DataParams_t slnLlcp; /* LLCP component */
#endif /* NXPBUILD__PHLN_LLCP_SW */
/* General information bytes to be sent with ATR Request */
#if defined(NXPBUILD__PHPAL_I18092MPI_SW) || defined(NXPBUILD__PHPAL_I18092MT_SW)
uint8_t aLLCPGeneralBytes[36] = { 0x46,0x66,0x6D,
0x01,0x01,0x10, /*VERSION*/
0x03,0x02,0x00,0x01, /*WKS*/
0x04,0x01,0xF1 /*LTO*/
};
uint8_t bLLCPGBLength = 13;
#endif
/* ATR Response or ATS Response holder */
#if defined(NXPBUILD__PHPAL_I14443P4A_SW) || \
defined(NXPBUILD__PHPAL_I18092MPI_SW)
uint8_t aResponseHolder[64];
#endif
/* prints if error is detected */
#define CHECK_SUCCESS(x) \
if ((x) != PH_ERR_SUCCESS) \
{ \
DEBUG_PRINTF("\nLine: %d Error - (0x%04X) has occurred : 0xCCEE CC-Component ID, EE-Error code. Refer-ph_Status.h\n ", __LINE__, (x)); \
return (x); \
}
/*******************************************************************************
** Function Definitions
*******************************************************************************/
#ifdef PHDRIVER_KINETIS_K82
static void phApp_K82_Init(void)
{
#ifdef DEBUG
uint32_t uartClkSrcFreq;
#endif /* DEBUG */
pit_config_t pitConfig; /* Structure of initialize PIT */
CLOCK_SetSimSafeDivs();
CLOCK_InitOsc0(&g_defaultClockConfigRun.oscConfig);
CLOCK_SetXtal0Freq(CPU_XTAL_CLK_HZ);
CLOCK_BootToPeeMode(g_defaultClockConfigRun.mcgConfig.oscsel, kMCG_PllClkSelPll0,
&g_defaultClockConfigRun.mcgConfig.pll0Config);
CLOCK_SetInternalRefClkConfig(g_defaultClockConfigRun.mcgConfig.irclkEnableMode,
g_defaultClockConfigRun.mcgConfig.ircs, g_defaultClockConfigRun.mcgConfig.fcrdiv);
CLOCK_SetSimConfig(&g_defaultClockConfigRun.simConfig);
SystemCoreClockUpdate();
/*
* pitConfig.enableRunInDebug = false;
*/
PIT_GetDefaultConfig(&pitConfig);
/* Init pit module */
PIT_Init(PIT, &pitConfig);
#ifdef DEBUG
/* Initialize LPUART4 pins below used to Print */
/* Ungate the port clock */
CLOCK_EnableClock(kCLOCK_PortC);
/* Affects PORTC_PCR14 register */
PORT_SetPinMux(PORTC, 14U, kPORT_MuxAlt3);
/* Affects PORTC_PCR15 register */
PORT_SetPinMux(PORTC, 15U, kPORT_MuxAlt3);
/* SIM_SOPT2[27:26]:
* 00: Clock Disabled
* 01: MCGFLLCLK, or MCGPLLCLK, or IRC48M
* 10: OSCERCLK
* 11: MCGIRCCLK
*/
CLOCK_SetLpuartClock(2);
uartClkSrcFreq = KINETIS_K82_DEBUG_UART_CLK_FREQ;
DbgConsole_Init(KINETIS_K82_DEBUG_UART_INSTANCE, KINETIS_K82_DEBUG_UART_BAUDRATE, KINETIS_K82_DEBUG_UART_TYPE, uartClkSrcFreq);
#endif /* DEBUG */
}
#endif /* PHDRIVER_KINETIS_K82 */
#ifdef PH_PLATFORM_HAS_ICFRONTEND
/**
* This function will initialize Host Controller interfaced with NXP Reader IC's.
* Any initialization which is not generic across Platforms, should be done here.
* Note: For NXP NFC Controllers HOST initialization is not required.
*/
void phApp_CPU_Init(void)
{
#if defined PHDRIVER_KINETIS_K82
phApp_K82_Init();
#elif defined(PHDRIVER_LPC1769) && defined(__CC_ARM)
SystemCoreClock = (( unsigned long ) 96000000);
#elif defined(PH_OSAL_LINUX) && defined(NXPBUILD__PHHAL_HW_PN5190)
phStatus_t status;
status = PiGpio_OpenIrq();
if ((status & PH_ERR_MASK) != PH_ERR_SUCCESS)
{
DEBUG_PRINTF("\n PiGpio_OpenIrq failed \n");
DEBUG_PRINTF("\n Couldn't open PN5190 Kernel IRQ Driver.\n Halting here!!FIX IT!!\n");
while(1);
}
#else
/* In case of LPC series, startup file takes care of initializing clock and ports.
* No initialization is required in Linux environment. */
#endif
}
#endif /* PH_PLATFORM_HAS_ICFRONTEND */
/**
* This function will initialize Reader LIbrary Component
*/
phStatus_t phApp_Comp_Init(void * pDiscLoopParams)
{
phStatus_t wStatus = PH_ERR_SUCCESS;
#if defined(NXPBUILD__PHPAL_I18092MPI_SW) || defined(NXPBUILD__PHPAL_I18092MT_SW) || \
defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_P2P_TAGS) || defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_P2P_ACTIVE) || \
defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_I3P4_TAGS) || defined(NXPBUILD__PHAC_DISCLOOP_TYPEF_P2P_TAGS) || \
defined(NXPBUILD__PHAC_DISCLOOP_TYPEF212_P2P_ACTIVE) || defined(NXPBUILD__PHAC_DISCLOOP_TYPEF424_P2P_ACTIVE)
phacDiscLoop_Sw_DataParams_t * pDiscLoop = (phacDiscLoop_Sw_DataParams_t *)pDiscLoopParams;
#endif
/* Initialize the LLCP component */
#ifdef NXPBUILD__PHLN_LLCP_SW
slnLlcp.sLocalLMParams.wMiu = 0x00; /* 128 bytes only */
slnLlcp.sLocalLMParams.wWks = 0x11; /* SNEP & LLCP */
slnLlcp.sLocalLMParams.bLto = 100; /* Maximum LTO */
slnLlcp.sLocalLMParams.bOpt = 0x02;
slnLlcp.sLocalLMParams.bAvailableTlv = PHLN_LLCP_TLV_MIUX_MASK | PHLN_LLCP_TLV_WKS_MASK |
PHLN_LLCP_TLV_LTO_MASK | PHLN_LLCP_TLV_OPT_MASK;
wStatus = phlnLlcp_Sw_Init(
&slnLlcp,
sizeof(phlnLlcp_Sw_DataParams_t),
aLLCPGeneralBytes,
&bLLCPGBLength);
#endif /* NXPBUILD__PHLN_LLCP_SW */
#ifdef NXPBUILD__PHAC_DISCLOOP_SW
#if defined(NXPBUILD__PHPAL_I18092MPI_SW) || defined(NXPBUILD__PHPAL_I18092MT_SW)
/* Assign the GI for Type A */
pDiscLoop->sTypeATargetInfo.sTypeA_P2P.pGi = (uint8_t *)aLLCPGeneralBytes;
pDiscLoop->sTypeATargetInfo.sTypeA_P2P.bGiLength = bLLCPGBLength;
/* Assign the GI for Type F */
pDiscLoop->sTypeFTargetInfo.sTypeF_P2P.pGi = (uint8_t *)aLLCPGeneralBytes;
pDiscLoop->sTypeFTargetInfo.sTypeF_P2P.bGiLength = bLLCPGBLength;
#endif
#if defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_P2P_TAGS) || defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_P2P_ACTIVE)
/* Assign ATR response for Type A */
pDiscLoop->sTypeATargetInfo.sTypeA_P2P.pAtrRes = aResponseHolder;
#endif
#if defined(NXPBUILD__PHAC_DISCLOOP_TYPEF_P2P_TAGS) || defined(NXPBUILD__PHAC_DISCLOOP_TYPEF212_P2P_ACTIVE) || \
defined(NXPBUILD__PHAC_DISCLOOP_TYPEF424_P2P_ACTIVE)
/* Assign ATR response for Type F */
pDiscLoop->sTypeFTargetInfo.sTypeF_P2P.pAtrRes = aResponseHolder;
#endif
#ifdef NXPBUILD__PHAC_DISCLOOP_TYPEA_I3P4_TAGS
/* Assign ATS buffer for Type A */
pDiscLoop->sTypeATargetInfo.sTypeA_I3P4.pAts = aResponseHolder;
#endif /* NXPBUILD__PHAC_DISCLOOP_TYPEA_I3P4_TAGS */
#endif /* NXPBUILD__PHAC_DISCLOOP_SW */
return wStatus;
}
phStatus_t phApp_Configure_IRQ()
{
#ifdef PH_OSAL_LINUX
phStatus_t wStatus;
#endif /* PH_OSAL_LINUX */
#ifdef PH_PLATFORM_HAS_ICFRONTEND
#if !(defined(PH_OSAL_LINUX) && defined(NXPBUILD__PHHAL_HW_PN5190))
phDriver_Pin_Config_t pinCfg;
pinCfg.bOutputLogic = PH_DRIVER_SET_LOW;
pinCfg.bPullSelect = PHDRIVER_PIN_IRQ_PULL_CFG;
pinCfg.eInterruptConfig = PIN_IRQ_TRIGGER_TYPE;
phDriver_PinConfig(PHDRIVER_PIN_IRQ, PH_DRIVER_PINFUNC_INTERRUPT, &pinCfg);
#endif
#ifdef PHDRIVER_LPC1769
NVIC_SetPriority(EINT_IRQn, EINT_PRIORITY);
/* Enable interrupt in the NVIC */
NVIC_ClearPendingIRQ(EINT_IRQn);
NVIC_EnableIRQ(EINT_IRQn);
#endif /* PHDRIVER_LPC1769 */
#ifdef PH_OSAL_LINUX
gphPiThreadObj.pTaskName = (uint8_t *) "IrqPolling";
gphPiThreadObj.pStackBuffer = NULL;
gphPiThreadObj.priority = PI_IRQ_POLLING_TASK_PRIO;
gphPiThreadObj.stackSizeInNum = PI_IRQ_POLLING_TASK_STACK;
PH_CHECK_SUCCESS_FCT(wStatus, phOsal_ThreadCreate(&gphPiThreadObj.ThreadHandle, &gphPiThreadObj,
&phExample_IrqPolling, NULL));
#endif /* PH_OSAL_LINUX */
#ifdef PHDRIVER_KINETIS_K82
NVIC_SetPriority(EINT_IRQn, EINT_PRIORITY);
NVIC_ClearPendingIRQ(EINT_IRQn);
EnableIRQ(EINT_IRQn);
#endif /* PHDRIVER_KINETIS_K82 */
#endif /* #ifdef PH_PLATFORM_HAS_ICFRONTEND */
return PH_ERR_SUCCESS;
}
#ifdef PH_OSAL_LINUX
/*
* \brief: The purpose of this Thread is to detect RF signal from an External Peer .
*/
static void phExample_IrqPolling(void* param)
{
uint8_t bgpioVal = 0;
uint8_t bhighOrLow = 0;
#if defined(NXPBUILD__PHHAL_HW_RC663) || defined(NXPBUILD__PHHAL_HW_PN5180)
if(PIN_IRQ_TRIGGER_TYPE == PH_DRIVER_INTERRUPT_RISINGEDGE)
{
bhighOrLow = 1;
}
while(PiGpio_read(PHDRIVER_PIN_IRQ, &bgpioVal) != PH_ERR_SUCCESS)
{
PiGpio_unexport(PHDRIVER_PIN_IRQ);
PiGpio_export(PHDRIVER_PIN_IRQ);
PiGpio_set_direction(PHDRIVER_PIN_IRQ, false);
if(PIN_IRQ_TRIGGER_TYPE == PH_DRIVER_INTERRUPT_RISINGEDGE)
{
PiGpio_set_edge(PHDRIVER_PIN_IRQ, true, false);
}
else
{
PiGpio_set_edge(PHDRIVER_PIN_IRQ, false, true);
}
}
/* Initial status: If pin is already Active, post an event. */
if(bgpioVal == bhighOrLow)
{
CLIF_IRQHandler();
}
#endif
while(1)
{
/* Block forever for Raising Edge in PHDRIVER_PIN_IRQ. */
#if defined(NXPBUILD__PHHAL_HW_RC663) || defined(NXPBUILD__PHHAL_HW_PN5180)
if(PiGpio_poll(PHDRIVER_PIN_IRQ, bhighOrLow, -1) == PH_ERR_SUCCESS)
#elif defined(NXPBUILD__PHHAL_HW_PN5190)
if(PiGpio_Irq() == PH_ERR_SUCCESS)
#endif
{
CLIF_IRQHandler();
}
else
{
PiGpio_unexport(PHDRIVER_PIN_IRQ);
PiGpio_export(PHDRIVER_PIN_IRQ);
PiGpio_set_direction(PHDRIVER_PIN_IRQ, false);
if(PIN_IRQ_TRIGGER_TYPE == PH_DRIVER_INTERRUPT_RISINGEDGE)
{
PiGpio_set_edge(PHDRIVER_PIN_IRQ, true, false);
}
else
{
PiGpio_set_edge(PHDRIVER_PIN_IRQ, false, true);
}
}
}
}
#endif /* PH_OSAL_LINUX */
/******************************************************************************
** End Of File
******************************************************************************/

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/*----------------------------------------------------------------------------*/
/* Copyright 2020,2023 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may only */
/* be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that you */
/* have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*----------------------------------------------------------------------------*/
/** \file
* Example Source abstracting component data structure and code initialization and code specific to HW used in the examples
* This file shall be present in all examples. A customer does not need to touch/modify this file. This file
* purely depends on the phNxpBuild_Lpc.h or phNxpBuild_App.h
* The phAppInit.h externs the component data structures initialized here that is in turn included by the core examples.
* The core example shall not use any other variable defined here except the RdLib component data structures(as explained above)
* The RdLib component initialization requires some user defined data and function pointers.
* These are defined in the respective examples and externed here.
*
* Keystore and Crypto initialization needs to be handled by application.
*
* $Author$
* $Revision$ (v07.10.00)
* $Date$
*
*/
/* Status header */
#include <ph_Status.h>
#include "phApp_Init.h"
#ifdef NXPBUILD__PHHAL_HW_PN5180
#include "BoardSelection.h"
/* HAL specific headers */
#include <phhalHw_Pn5180_Instr.h>
/*******************************************************************************
** Function Declarations
*******************************************************************************/
/*******************************************************************************
** Global Variable Declaration
*******************************************************************************/
phbalReg_Type_t sBalParams;
phhalHw_Pn5180_DataParams_t * pHal;
#ifdef NXPBUILD__PHHAL_HW_TARGET
/* Parameters for L3 activation during Autocoll */
extern uint8_t sens_res[2] ;
extern uint8_t nfc_id1[3] ;
extern uint8_t sel_res ;
extern uint8_t nfc_id3 ;
extern uint8_t poll_res[18] ;
#endif /* NXPBUILD__PHHAL_HW_TARGET */
/*******************************************************************************
** Function Definitions
*******************************************************************************/
/**
* This function will initialize Hal Target Config
*/
phStatus_t phApp_HALConfigAutoColl(void)
{
#ifdef NXPBUILD__PHHAL_HW_TARGET
phStatus_t wStatus;
uint8_t baDynamicUidConfig[1U] = { 1U };
uint8_t baReadEepromConfig[24U] = { 0U };
/* Read Set Listen Parameters data from EEPROM */
wStatus = phhalHw_Pn5180_Instr_ReadE2Prom(
(phhalHw_Pn5180_DataParams_t *) pHal,
PHHAL_HW_PN5180_SET_LISTEN_E2PROM_ADDR,
baReadEepromConfig,
24U
);
CHECK_SUCCESS(wStatus);
/* Verify EEPROM data and configure Set Listen Parameters if EEPROM data is not correct. */
if ((memcmp(&baReadEepromConfig[0U], sens_res, 2U) != 0x00) ||
(memcmp(&baReadEepromConfig[2U], nfc_id1, 3U) != 0x00) ||
(memcmp(&baReadEepromConfig[5U], &sel_res, 1U) != 0x00) ||
(memcmp(&baReadEepromConfig[6U], poll_res, 18U) != 0x00))
{
/* Configure Set Listen Parameters. */
wStatus = phhalHw_Pn5180_SetListenParameters(
pHal,
&sens_res[0],
&nfc_id1[0],
sel_res,
&poll_res[0],
nfc_id3
);
CHECK_SUCCESS(wStatus);
}
if (pHal->wFirmwareVer < 0x308U)
{
/* With Pn5180 FW version < 3.8, only static UID is supported. */
baDynamicUidConfig[0] = 0x00;
}
/* Read Dynamic UID configuration from EEPROM */
wStatus = phhalHw_Pn5180_Instr_ReadE2Prom(
(phhalHw_Pn5180_DataParams_t *) pHal,
PHHAL_HW_PN5180_DYN_UID_CFG_E2PROM_ADDR,
baReadEepromConfig,
1U
);
CHECK_SUCCESS(wStatus);
/* Verify EEPROM data and perform Dynamic UID configuration if EEPROM data is not correct. */
if (memcmp(baReadEepromConfig, baDynamicUidConfig, 1U) != 0x00)
{
/* Configure Dynamic UID */
wStatus = phhalHw_Pn5180_Instr_WriteE2Prom(
(phhalHw_Pn5180_DataParams_t *) pHal,
PHHAL_HW_PN5180_DYN_UID_CFG_E2PROM_ADDR,
baDynamicUidConfig,
1U
);
CHECK_SUCCESS(wStatus);
}
#endif /* NXPBUILD__PHHAL_HW_TARGET */
return PH_ERR_SUCCESS;
}
/* Configure LPCD (for PN5180) */
phStatus_t phApp_ConfigureLPCD(void)
{
/**
* PHHAL_HW_CONFIG_SET_LPCD_WAKEUPTIME_MS 0x0070U //< Used value for wakeup counter in msecs, i.e. after this amount of time IC will wakes up from standby.
* PHHAL_HW_CONFIG_LPCD_MODE 0x0071U //< Used to set options PHHAL_HW_PN5180_LPCD_MODE_DEFAULT or PHHAL_HW_PN5180_LPCD_MODE_POWERDOWN_GUARDED
* PHHAL_HW_CONFIG_LPCD_REF 0x0072U //< Used to set or get LPCD Ref
*/
phStatus_t status = PH_ERR_SUCCESS;
uint16_t wConfig = PHHAL_HW_CONFIG_LPCD_REF;
uint16_t wValue;
uint8_t bLPCD_Threshold_EEPROMAddress = 0x37;
uint8_t bLPCD_Threshold = 0x10;
wValue = PHHAL_HW_PN5180_LPCD_MODE_POWERDOWN;
wConfig = PHHAL_HW_CONFIG_LPCD_MODE;
//status = phhalHw_Pn5180_Int_LPCD_GetConfig(pHal, wConfig, &wValue);
status = phhalHw_Pn5180_Instr_WriteE2Prom(pHal,bLPCD_Threshold_EEPROMAddress, &bLPCD_Threshold, 1 );
CHECK_SUCCESS(status);
status = phhalHw_Pn5180_Int_LPCD_SetConfig(
pHal,
wConfig,
wValue
);
return status;
}
void CLIF_IRQHandler(void)
{
/* Read the interrupt status of external interrupt attached to the reader IC IRQ pin */
if (phDriver_PinRead(PHDRIVER_PIN_IRQ, PH_DRIVER_PINFUNC_INTERRUPT))
{
phDriver_PinClearIntStatus(PHDRIVER_PIN_IRQ);
/* Call application registered callback. */
if (pHal->pRFISRCallback != NULL)
{
pHal->pRFISRCallback(pHal);
}
}
}
#endif /* NXPBUILD__PHHAL_HW_PN5180 */
/******************************************************************************
** End Of File
******************************************************************************/

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PROJECT(NfcrdlibEx5_ISO15693)
FILE(GLOB NfcrdlibEx5_ISO15693_Sources
*.c
src/*.c
)
include_directories(
intfs
types
)
ADD_EXECUTABLE(${PROJECT_NAME}
${${PROJECT_NAME}_Sources}
)
TARGET_LINK_LIBRARIES(${PROJECT_NAME}
phOsal
DAL
NxpRdLib_acDiscLoop
NxpRdLib_halHw
NxpRdLib_KeyStore
NxpRdLib_phTools
NxpRdLib_palFelica
NxpRdLib_palI18092mPI
NxpRdLib_palI14443p4a
NxpRdLib_palI14443p4
NxpRdLib_palI14443p4
NxpRdLib_palMifare
NxpRdLib_alFelica
NxpRdLib_alMful
NxpRdLib_alMfdf
NxpRdLib_alT1T
NxpRdLib_alTop
NxpRdLib_alMfc
NxpRdLib_lnLlcp
NxpRdLib_phTools
NxpRdLib_palI18092mT
NxpRdLib_npSnep
NxpRdLib_palI14443p4mC
NxpRdLib_ceT4T
NxpRdLib_palEpcUid
NxpRdLib_alMfNtag42XDna
NxpRdLib_phNfcLib
)

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@ -0,0 +1,592 @@
/*----------------------------------------------------------------------------*/
/* Copyright 2016-2021,2023 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may only */
/* be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that you */
/* have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*----------------------------------------------------------------------------*/
/** \file
* Example Source for NfcrdlibEx5_ISO15693 that uses the ISO15693 implementation.
* This example will load/configure Discovery loop for ISO15693, uses POLL mode to detect the ISO15693 card.
* Displays detected ISO15693 card information like UID, Card Type, Block Read and Block Write operation status.
* Example will activate the device at index zero whenever multiple MIFARE Classic contactless IC cards are detected.
*
* Please refer Readme.txt file for Hardware Pin Configuration, Software Configuration and steps to build and
* execute the project which is present in the same project directory.
* $Author: $
* $Revision: $ (v07.10.00)
* $Date: $
*
*/
/**
* Reader Library Headers
*/
#include <phApp_Init.h>
/* Local headers */
#include "NfcrdlibEx5_ISO15693.h"
/* PAL Headers */
#include <phpalSli15693.h>
/* AL Headers */
#include <phalICode.h>
/*******************************************************************************
** Definitions
*******************************************************************************/
#define ISO15693_NXP_TAG_ID 0x04 /* ISO15693 NXP Cards specific code */
#define ISO15693_UID_NXP_IDPOS 6 /* ISO15693 NXP Cards specific code position (UID6) */
#define ISO15693_UID_SIZE_BITS 64 /* ISO15693 UID Size in Bits */
#define ISO15693_MFGID_CARDSEL_IDPOS 4 /* NXP Card Type detection (UID4) */
#define ISO15693_MFGID_CARDSEL_MSK 0x18 /* NXP Card Type detection Mask value */
#define ISO15693_MFGID_CARDSEL_BITPOS 3 /* NXP Card Type detection Bit position in UID4 */
#define ISO15693_MFGID_DNA_CARDSEL_MSK 0x40 /* NXP DNA Card Type detection Mask value */
#define ISO15693_MFGID_DNA_CARDSEL_BITPOS 6 /* NXP Card Type detection Bit position in UID4 */
/* NXP Card Type(SLI/SLI-S/SLI-L or SLIX/SLIX-S/SLIX-L) detection (UID5) */
#define ISO15693_UID_CARDSEL_IDPOS 5
/* NXP Card Type states */
#define ISO15693_MFGID_SLI_STATE 0
#define ISO15693_MFGID_SLIX_STATE 2
#define ISO15693_MFGID_SLIX2_STATE 1
#define ISO15693_MFGID_DNA_STATE 3
/* SLI Card Type states */
#define ISO15693_UID_SLI_STATE 1
#define ISO15693_UID_SLI_S_STATE 2
#define ISO15693_UID_SLI_L_STATE 3
/* SLIX Card Type states */
#define ISO15693_UID_SLIX_STATE 1
#define ISO15693_UID_SLIX_S_STATE 2
#define ISO15693_UID_SLIX_L_STATE 3
/* ICode DNA and NTag 5 Series Card Types */
#define ISO15693_UID_ICODE_DNA_STATE 0
#define ISO15693_UID_NTAG_5_SERIES 1
phacDiscLoop_Sw_DataParams_t * pDiscLoop; /* Discovery loop component */
void * psalI15693;
#ifdef PHOSAL_FREERTOS_STATIC_MEM_ALLOCATION
uint32_t aIso15693TaskBuffer[ISO15693_DEMO_TASK_STACK];
#else /* PHOSAL_FREERTOS_STATIC_MEM_ALLOCATION */
#define aIso15693TaskBuffer NULL
#endif /* PHOSAL_FREERTOS_STATIC_MEM_ALLOCATION */
/*******************************************************************************
** Prototypes
*******************************************************************************/
void NfcrdlibEx5_ISO15693(void *pParams);
static phStatus_t phExample_Init(void);
static phStatus_t DisplayCardTypeInfo(uint8_t *pUID, uint8_t *pNTag5_State);
static void ReadMultipleBlock_HighDataRate(uint8_t bNTag5_State);
#ifdef PH_OSAL_FREERTOS
const uint8_t bTaskName[configMAX_TASK_NAME_LEN] = {"Ex5_ISO15693"};
#else
const uint8_t bTaskName[] = {"Ex5_ISO15693"};
#endif /* PH_OSAL_FREERTOS */
static volatile uint8_t bInfLoop = 1U;
/*******************************************************************************
** Code
*******************************************************************************/
int main(void)
{
do
{
phStatus_t status = PH_ERR_INTERNAL_ERROR;
phNfcLib_Status_t dwStatus;
#ifdef PH_PLATFORM_HAS_ICFRONTEND
phNfcLib_AppContext_t AppContext = {0};
#endif /* PH_PLATFORM_HAS_ICFRONTEND */
#ifndef PH_OSAL_NULLOS
phOsal_ThreadObj_t Iso15693;
#endif /* PH_OSAL_NULLOS */
/* Perform Controller specific initialization. */
phApp_CPU_Init();
/* Perform OSAL Initialization. */
(void)phOsal_Init();
/* Print Example application name */
DEBUG_PRINTF("\n *** ISO 15693 Example *** \n");
#ifdef PH_PLATFORM_HAS_ICFRONTEND
status = phbalReg_Init(&sBalParams, sizeof(phbalReg_Type_t));
CHECK_STATUS(status);
AppContext.pBalDataparams = &sBalParams;
dwStatus = phNfcLib_SetContext(&AppContext);
CHECK_NFCLIB_STATUS(dwStatus);
#endif /* PH_PLATFORM_HAS_ICFRONTEND */
/* Initialize library */
dwStatus = phNfcLib_Init();
CHECK_NFCLIB_STATUS(dwStatus);
if(dwStatus != PH_NFCLIB_STATUS_SUCCESS) break;
/* Set the generic pointer */
pHal = phNfcLib_GetDataParams(PH_COMP_HAL);
psalI15693 = phNfcLib_GetDataParams(PH_COMP_AL_ICODE);
pDiscLoop = phNfcLib_GetDataParams(PH_COMP_AC_DISCLOOP);
/* Initialize other components that are not initialized by NFCLIB and configure Discovery Loop. */
status = phApp_Comp_Init(pDiscLoop);
CHECK_STATUS(status);
if(status != PH_ERR_SUCCESS) break;
/* Perform Platform Init */
status = phApp_Configure_IRQ();
CHECK_STATUS(status);
if(status != PH_ERR_SUCCESS) break;
#ifndef PH_OSAL_NULLOS
Iso15693.pTaskName = (uint8_t *)bTaskName;
Iso15693.pStackBuffer = aIso15693TaskBuffer;
Iso15693.priority = ISO15693_DEMO_TASK_PRIO;
Iso15693.stackSizeInNum = ISO15693_DEMO_TASK_STACK;
phOsal_ThreadCreate(&Iso15693.ThreadHandle, &Iso15693, &NfcrdlibEx5_ISO15693, pDiscLoop);
phOsal_StartScheduler();
/* Print Error info */
DEBUG_PRINTF("RTOS Error : Scheduler exited. \n");
#else
(void)NfcrdlibEx5_ISO15693(pDiscLoop);
#endif /* PH_OSAL_NULLOS */
} while(0);
while(bInfLoop); /* Comes here if initialization failure or scheduler exit due to error */
return 0;
}
/***********************************************************************************************
* \brief This function demonstrates the Type V (ISO 15693) card detection, Block Read and Write operation.
* \param *pParams
* \return This function will never return
**********************************************************************************************/
void NfcrdlibEx5_ISO15693(void *pParams)
{
phStatus_t status = 0;
uint16_t wTagsDetected = 0;
uint8_t bBlock = 0x03;
uint8_t *pRxbuffer;
uint16_t bDataLength;
uint8_t aTempUid[8];
uint8_t aReceivedUid[8];
uint8_t bDsfid = 0;
uint8_t bNTag5_State;
/* This call shall allocate secure context before calling any secure function,
* when FreeRtos trust zone is enabled.
* */
phOsal_ThreadSecureStack( 512 );
/* Initialize library */
status = phExample_Init();
CHECK_STATUS(status);
while(1) /* Continuous loop */
{
bNTag5_State = 0;
DEBUG_PRINTF("\nReady to detect");
DEBUG_PRINTF("\n");
do
{
/* Field OFF */
status = phhalHw_FieldOff(pHal);
CHECK_STATUS(status);
status = phhalHw_Wait(pDiscLoop->pHalDataParams,PHHAL_HW_TIME_MICROSECONDS, 5100);
CHECK_STATUS(status);
/* Configure Discovery loop for Poll Mode */
status = phacDiscLoop_SetConfig(pDiscLoop, PHAC_DISCLOOP_CONFIG_NEXT_POLL_STATE, PHAC_DISCLOOP_POLL_STATE_DETECTION);
CHECK_STATUS(status);
/* Run Discovery loop */
status = phacDiscLoop_Run(pDiscLoop, PHAC_DISCLOOP_ENTRY_POINT_POLL);
}while((status & PH_ERR_MASK) != PHAC_DISCLOOP_DEVICE_ACTIVATED); /* Exit on Card detection */
/* Card detected */
/* Get the tag types detected info */
status = phacDiscLoop_GetConfig(pDiscLoop, PHAC_DISCLOOP_CONFIG_TECH_DETECTED, &wTagsDetected);
/* Check for Status */
if ((status & PH_ERR_MASK) == PH_ERR_SUCCESS)
{
/* Check for Type V(ISO 15693) tag detection */
if(PHAC_DISCLOOP_CHECK_ANDMASK(wTagsDetected, PHAC_DISCLOOP_POS_BIT_MASK_V))
{
DEBUG_PRINTF("\nType V / ISO 15693 / T5T Detected \n");
/* Print UID */
DEBUG_PRINTF ("\nUID: ");
phApp_Print_Buff(pDiscLoop->sTypeVTargetInfo.aTypeV[0].aUid, 0x08);
/* Copy UID */
memcpy(aReceivedUid, pDiscLoop->sTypeVTargetInfo.aTypeV[0].aUid, 0x08);
/* Check and display Card type info */
if (DisplayCardTypeInfo(pDiscLoop->sTypeVTargetInfo.aTypeV[0].aUid, &bNTag5_State) == PH_ERR_SUCCESS)
{
do
{
/* Data length */
bDataLength = 0x04;
/* Block Read */
DEBUG_PRINTF("\nRead Data from Block %d", bBlock);
/* Read single block */
status = phalICode_ReadSingleBlock(psalI15693,
PHAL_ICODE_OPTION_OFF,
bBlock,
&pRxbuffer,
&bDataLength);
/* Check for Status */
if(status != PH_ERR_SUCCESS)
{
/* Print Error info */
DEBUG_PRINTF ("\nRead operation Failed!!!");
DEBUG_PRINTF("\nExecution aborted!!!\n");
break;
}
/* Read Success */
DEBUG_PRINTF("\nRead Success");
DEBUG_PRINTF("\nThe content of Block %d is:", bBlock);
phApp_Print_Buff (pRxbuffer, bDataLength);
DEBUG_PRINTF("\n\n --- End of Read Operation ---");
/* Block Write */
DEBUG_PRINTF("\n\nWrite data to Block %d", bBlock);
/* Write single block */
status = phalICode_WriteSingleBlock(psalI15693,
PHAL_ICODE_OPTION_OFF,
bBlock,
pRxbuffer,
bDataLength);
/* Check for Status */
if(status != PH_ERR_SUCCESS)
{
/* Print Error info */
DEBUG_PRINTF ("\nWrite operation Failed!!!");
DEBUG_PRINTF("\nExecution aborted!!!\n");
break;
}
/* Write Success */
DEBUG_PRINTF ("\nWrite Success");
DEBUG_PRINTF("\n\n --- End of Write Operation ---");
ReadMultipleBlock_HighDataRate(bNTag5_State);
DEBUG_PRINTF("\n\n --- End of Example ---\n\n");
}while(0);
}
DEBUG_PRINTF("\nPlease Remove the Card\n\n");
/* Field RESET */
status = phhalHw_FieldReset(pHal);
CHECK_STATUS(status);
/* Make sure that example application is not detecting the same card continuously */
do
{
/* Clear UID buffer */
memset(aTempUid, 0x00, 0x08);
/* Inventory request */
status = phpalSli15693_Inventory(pDiscLoop->pPalSli15693DataParams,
(PHPAL_SLI15693_FLAG_NBSLOTS | PHPAL_SLI15693_FLAG_DATA_RATE | PHPAL_SLI15693_FLAG_INVENTORY),
0,
aReceivedUid,
ISO15693_UID_SIZE_BITS,
&bDsfid,
aTempUid);
/* Check for Status */
if (status != PH_ERR_SUCCESS)
{
break; /* Card Removed, break from the loop */
}
/* Delay - 5 milli seconds*/
status = phhalHw_Wait(pDiscLoop->pHalDataParams, PHHAL_HW_TIME_MILLISECONDS, 5);
CHECK_STATUS(status);
}while(1);
}
}
}
}
/***********************************************************************************************
* \brief Initializes the Reader Library
* \param none
* \return status Returns the function status
**********************************************************************************************/
static phStatus_t phExample_Init(void)
{
phStatus_t status;
#if defined NXPBUILD__PHHAL_HW_RC663
uint8_t bChipVersion;
#endif /* NXPBUILD__PHHAL_HW_RC663 */
/* Device limit for Type V (ISO 15693) */
status = phacDiscLoop_SetConfig(pDiscLoop, PHAC_DISCLOOP_CONFIG_TYPEV_DEVICE_LIMIT, 1);
CHECK_STATUS(status);
/* Passive polling Tx Guard times in micro seconds. */
status = phacDiscLoop_SetConfig(pDiscLoop, PHAC_DISCLOOP_CONFIG_GTV_VALUE_US, 5000);
CHECK_STATUS(status);
/* Bailout on Type V (ISO 15693) detect */
status = phacDiscLoop_SetConfig(pDiscLoop, PHAC_DISCLOOP_CONFIG_BAIL_OUT, PHAC_DISCLOOP_POS_BIT_MASK_V);
CHECK_STATUS(status);
/* Read Chip Version */
#if defined NXPBUILD__PHHAL_HW_RC663
status = phhalHw_Rc663_ReadRegister(pHal, PHHAL_HW_RC663_REG_VERSION, &bChipVersion);
CHECK_STATUS(status);
DEBUG_PRINTF("\nReader chip RC663: 0x%02x\n", bChipVersion);
#endif /* NXPBUILD__PHHAL_HW_RC663 */
/* Return Success */
return PH_ERR_SUCCESS;
}
/***********************************************************************************************
* \brief This functions prints the Card type information like SLI, SLIX etc.
* \param *pUID UID Pointer
* \return status Returns the function status
**********************************************************************************************/
static phStatus_t DisplayCardTypeInfo(uint8_t *pUID, uint8_t *pNTag5_State)
{
uint8_t bCardType;
phStatus_t status = PH_ERR_SUCCESS;
/* Check for ISO15693 NXP TAG */
if (pUID[ISO15693_UID_NXP_IDPOS] != ISO15693_NXP_TAG_ID)
{
/* Print Product type */
DEBUG_PRINTF("\nProduct: Non NXP ISO15693 Tag Detected\n");
/* Return Status */
return (PH_COMP_PAL_SLI15693 | PH_ERR_INVALID_DATA_PARAMS);
}
/* Read SLI Card type information from UID (Byte 4) */
bCardType = ((pUID[ISO15693_MFGID_CARDSEL_IDPOS] & ISO15693_MFGID_CARDSEL_MSK) >> ISO15693_MFGID_CARDSEL_BITPOS);
/* Switch based on Card Type(SLI/SLIX/SLIX2) */
switch (bCardType)
{
case ISO15693_MFGID_SLI_STATE: /* SLI Card state */
/* Switch based on Card Type(SLI/SLI-S/SLI-L) */
switch (pUID[ISO15693_UID_CARDSEL_IDPOS])
{
case ISO15693_UID_SLI_STATE: /* SLI Card state */
/* Print Product type */
DEBUG_PRINTF("\nProduct: ICODE SLI\n");
break;
case ISO15693_UID_SLI_S_STATE: /* SLI-S Card state */
/* Print Product type */
DEBUG_PRINTF("\nProduct: ICODE SLI-S\n");
break;
case ISO15693_UID_SLI_L_STATE: /* SLI-L Card state */
/* Print Product type */
DEBUG_PRINTF("\nProduct: ICODE SLI-L\n");
break;
default: /* default */
/* Print Product type */
DEBUG_PRINTF("\nProduct: Unidentified Tag\n");
/* Update status */
status = (PH_COMP_PAL_SLI15693 | PH_ERR_INVALID_DATA_PARAMS);
break;
}
break;
case ISO15693_MFGID_SLIX_STATE: /* SLIX Card state */
/* Switch based on Card Type(SLIX/SLIX-S/SLIX-L) */
switch (pUID[ISO15693_UID_CARDSEL_IDPOS])
{
case ISO15693_UID_SLIX_STATE: /* SLIX Card state */
/* Print Product type */
DEBUG_PRINTF("\nProduct: ICODE SLIX\n");
break;
case ISO15693_UID_SLIX_S_STATE: /* SLIX-S Card state */
/* Print Product type */
DEBUG_PRINTF("\nProduct: ICODE SLIX-S\n");
break;
case ISO15693_UID_SLIX_L_STATE: /* SLIX-L Card state */
/* Print Product type */
DEBUG_PRINTF("\nProduct: ICODE SLIX-L\n");
break;
default: /* default */
/* Print Product type */
DEBUG_PRINTF("\nProduct: Unidentified Tag\n");
/* Update status */
status = (PH_COMP_PAL_SLI15693 | PH_ERR_INVALID_DATA_PARAMS);
break;
}
break;
case ISO15693_MFGID_SLIX2_STATE: /* SLIX2 Card state */
/* Print Product type */
DEBUG_PRINTF("\nProduct: ICODE SLIX2\n");
break;
case ISO15693_MFGID_DNA_STATE:
/* Switch based on Card Type(ICode DNA or NTag 5 Series) */
switch ((pUID[ISO15693_MFGID_CARDSEL_IDPOS] & ISO15693_MFGID_DNA_CARDSEL_MSK) >> ISO15693_MFGID_DNA_CARDSEL_BITPOS)
{
case ISO15693_UID_ICODE_DNA_STATE: /* ICode DNA Card state */
/* Print Product type */
DEBUG_PRINTF("\nProduct: ICODE DNA\n");
break;
case ISO15693_UID_NTAG_5_SERIES: /* NTag 5 Series */
/* Print Product type */
DEBUG_PRINTF("\nProduct: NTag 5 Series\n");
*pNTag5_State = 1;
break;
default: /* default */
/* Print Product type */
DEBUG_PRINTF("\nProduct: Unidentified Tag\n");
/* Update status */
status = (PH_COMP_PAL_SLI15693 | PH_ERR_INVALID_DATA_PARAMS);
break;
}
break;
default: /* default */
/* Print Product type */
DEBUG_PRINTF("\nProduct: Unidentified Tag\n");
/* Update status */
status = (PH_COMP_PAL_SLI15693 | PH_ERR_INVALID_DATA_PARAMS);
break;
}
/* Return Status */
return status;
}
/***********************************************************************************************
* \brief This functions performs Read Multiple Blocks at higher data rates with NTag 5.
* \param *pUID UID Pointer
* \return status Returns the function status
**********************************************************************************************/
static void ReadMultipleBlock_HighDataRate(uint8_t bNTag5_State)
{
#ifdef CUSTOM_HIGH_DATA_RATE_DEMO
phStatus_t status;
uint8_t bBlockNo;
uint8_t bNumOfBlocks;
uint8_t aRxBuf[256];
uint16_t wRxDataLength = 0x00;
uint8_t bTxRxBaudrate;
uint8_t bTiming = PHAL_ICODE_PARAMETERS_TIMING_320_9_US;
if (bNTag5_State == 1)
{
#ifdef CUSTOM_HIGH_DATA_RATE_DEMO_TX106_RX106
bTxRxBaudrate = 0x22;
DEBUG_PRINTF("\nPerform ParameterSelect command exchange to move to Tx and Rx at 106Kbps");
#else
bTxRxBaudrate = 0x44;
DEBUG_PRINTF("\nPerform ParameterSelect command exchange to move to Tx and Rx at 212Kbps");
DEBUG_PRINTF("\n!!!!!!!!!!!!Use NTag 5 Boost supporting Active Load Modulation Feature to operate at 212Kbps data rate!!!!!!!!!!!!");
#endif /* CUSTOM_HIGH_DATA_RATE_DEMO_TX106_RX106 */
/* Switch to higher baudrate */
status = phalICode_ParameterSelect(
psalI15693,
bTxRxBaudrate,
bTiming);
if ((status & PH_ERR_MASK) == PH_ERR_SUCCESS)
{
DEBUG_PRINTF("\nSuccessfully switched to selected higher baud rate using Parameter Select Exchange");
bBlockNo = 3;
bNumOfBlocks = 4;
/* Block Read */
DEBUG_PRINTF("\nExtended Read Multiple Blocks from Block No %d to Block No %d", bBlockNo, (bBlockNo + bNumOfBlocks - 1));
/*Read the the contents of a single block*/
status = phalICode_ExtendedReadMultipleBlocks(
psalI15693,
0,
bBlockNo,
bNumOfBlocks,
&aRxBuf[0],
&wRxDataLength);
CHECK_STATUS(status);
/* Check for Status */
if(status != PH_ERR_SUCCESS)
{
/* Print Error info */
DEBUG_PRINTF ("\nExtended Read Multiple Blocks operation Failed at higher data rates!!!");
}
else
{
/* Read Success */
DEBUG_PRINTF("\nExtended Read Multiple Blocks Success at higher data rates");
DEBUG_PRINTF("\n\n\tThe content from Block %d is:\t", bBlockNo);
phApp_Print_Buff (&aRxBuf[0], wRxDataLength);
DEBUG_PRINTF("\n\n --- End of Extended Read Multiple Blocks Operation ---");
}
}
else
{
DEBUG_PRINTF("\nFailed to switch to selected higher baud rate using Parameter Select Exchange");
DEBUG_PRINTF("\n!!!!!!!!!!!!Try with NTag 5 Cards supporting higer data rates!!!!!!!!!!!!");
}
}
#endif /* CUSTOM_HIGH_DATA_RATE_DEMO */
}
#ifdef NXPBUILD__PHHAL_HW_TARGET
/* Stubbed definitions in case TARGET is enabled */
uint8_t sens_res[2] = {0x04, 0x00};
uint8_t nfc_id1[3] = {0xA1, 0xA2, 0xA3};
uint8_t sel_res = 0x40;
uint8_t nfc_id3 = 0xFA;
uint8_t poll_res[18] = {0x01, 0xFE, 0xB2, 0xB3, 0xB4, 0xB5,
0xB6, 0xB7, 0xC0, 0xC1, 0xC2, 0xC3,
0xC4, 0xC5, 0xC6, 0xC7, 0x23, 0x45 };
#endif /* NXPBUILD__PHHAL_HW_TARGET */

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__________________________________________________
NXPNFCRDLIB EXAMPLE : NFCRDLIBEX5_ISO15693
(V07.10.00)
__________________________________________________
Table of Contents
_________________
1 Document Purpose
2 Description of the NfcrdlibEx5_ISO15693
3 Restrictions on NfcrdlibEx5_ISO15693
4 Package Contents
5 Mandatory materials (not included)
6 Hardware Configuration
7 Software Configuration
8 Steps to build NfcrdlibEx5_ISO15693 for LPC1769 with PN5190 using MCUXpresso
9 Steps to build NfcrdlibEx5_ISO15693 for LPC1769 with PN5180 using MCUXpresso
10 Steps to build NfcrdlibEx5_ISO15693 for LPC1769 with RC663 using MCUXpresso
11 Steps to build NfcrdlibEx5_ISO15693 for PN7462AU using MCUXpresso
12 Steps to build NfcrdlibEx5_ISO15693 for FRDM-K82F using MCUXpresso
13 Selection of Board / OSAL / Frontend (MCUXpresso)
14 Steps to follow for PI / Linux / CMake
15 Running NfcrdlibEx5_ISO15693
16 List of supported NFC Reader Boards/ICs
17 Reference Documents
1 Document Purpose
==================
This document describes the steps to be followed to execute
NfcrdlibEx5_ISO15693 example as well as it's known problems and
restrictions.
2 Description of the NfcrdlibEx5_ISO15693
=========================================
- NfcrdlibEx5_ISO15693 can be run with CLEV663B, PN5180, PN5190 and
PN7462AU. (See Section-16 for supported versions)
- This example will load/configure Discovery loop with NFC profile via
SetConfig.
- By using POLL mode of discovery loop, example will detect the ISO
15693 cards and display/print detected tag information like UID,
Block Read and Block Write status.
- This example will activate device at index zero whenever multiple
cards are detected.
3 Restrictions on NfcrdlibEx5_ISO15693
======================================
- NfcrdlibEx5_ISO15693 is restricted to be run on NFC Reader
Boards/ICs mentioned in Section-16.
- The APIs are intended for NXP contact-less reader ICs only, as such
the APIs are not to be ported to any technology from any other
vendor.
- NXP will not support porting to any other vendor platform.
- This software project requires NxpNfcRdLib v07.10.00 or later.
- **IMPORTANT** The default used MCU Type is K82. When executing
example on LPC1769 or PN7462AU, the MCU Type has to be changed in
the MCUXpresso IDE.
- For switching to MCU Type to PN7462AU, see Section-11
- For switching to MCU Type to LPC1769, see Section-8, Section-9 and
Section-10.
4 Package Contents
==================
- Readme.txt
+ This readme file
- NfcrdlibEx5_ISO15693.c
+ Main example file.
- intfs/NfcrdlibEx5_ISO15693.h
+ Interfaces/Defines specific to the example
- intfs/ph_NxpBuild_App.h
+ Reader library build configuration file
- src/phApp_Helper.c
- src/phApp_PN5180_Init.c
- src/phApp_PN5190_Init.c
- src/phApp_PN7462AU_Init.c
- src/phApp_RC663_Init.c
- src/phApp_Init.c and intfs/phApp_Init.h
+ Common utility functions (common across all examples)
- mcux/.cproject and mcux/.project
+ MCUXpresso project configuration file
- cr_startup_lpc175x_6x.c
+ Startup required to compile example for LPC1769 Micro Controller.
5 Mandatory materials (not included)
====================================
- MCUXpresso IDE. It can be downloaded from
[http://www.nxp.com/products/:MCUXpresso-IDE]
- SDK for Freedom K82 Board
([http://www.nxp.com/products/:FRDM-K82F]). The pre-build SDK can
be downloaded from
[https://mcuxpresso.nxp.com/en/license?hash=9897a8c19a6bc569c3fade7141f0f405&hash_download=true&to_vault=true]
See MCUXpresso User Manual for steps needed to install an SDK.
- Plugin to extend MCUXpresso to support PN7462AU. (Required for
MCUXpresso versions before MCUXpressoIDE_10.0.2)
- LPCXpresso LPC1769 / Freedom K82 development boards For NFC ICs
listed in Section-16 (Note: PN7462AU (Section-16 Bullet-3) does not
need any other other microcontroller).
6 Hardware Configuration
========================
Before starting this application, HW Changes may be required for the
used board. Refer to the following User Manuals / Application notes
before starting with this example.
- AN11211: Quick Start Up Guide RC663 Blueboard
- AN11744: PN5180 Evaluation board quick start guide
- AN11802: NFC Reader Library for Linux Installation Guidelines
- AN12550: PNEV5190B Evaluation board quick start guide
7 Software Configuration
========================
- The Software can be compiled for Cortex M3 LPC1769 micro-controller,
Cortex M4 Freedom K82 and Cortex M0 based PN7462AU from NXP.
- Since this example can be configured to run on various MCU ICs and
various NFC ICs, appropriate changes are required as mentioned in
Section-8, Section-9, Section-10, Section-11 and Section-12.
8 Steps to build NfcrdlibEx5_ISO15693 for LPC1769 with PN5190 using MCUXpresso
==============================================================================
See "PNEV5190B Evaluation board quick start guide" in AN12550 (See
Section-17, Bullet-6 below)
9 Steps to build NfcrdlibEx5_ISO15693 for LPC1769 with PN5180 using MCUXpresso
==============================================================================
See "Importing provided SW example projects" in AN11908 (See
Section-17, Bullet-2 below)
10 Steps to build NfcrdlibEx5_ISO15693 for LPC1769 with RC663 using MCUXpresso
==============================================================================
See "Importing provided SW example projects" in AN11022 (See
Section-17, Bullet-3 below)
11 Steps to build NfcrdlibEx5_ISO15693 for PN7462AU using MCUXpresso
====================================================================
- For MCUXpresso versions before MCUXpressoIDE_10.0.2, See "Adding
PN7462AU Plugin" in UM10883. (See Section-17, Bullet-4 below)
- See "Importing provided SW example projects" in UM10883.
12 Steps to build NfcrdlibEx5_ISO15693 for FRDM-K82F using MCUXpresso
=====================================================================
See "Import projects to the MCUXpresso" in AN11908. (See Section-17,
Bullet-2 below)
13 Selection of Board / OSAL / Frontend (MCUXpresso)
====================================================
For MCUXpresso, the selection of Board / OSAL / Frontend has to be
done via -D (Preprocessor defines).
1) To select the board go to "Project Properties" --> "C/C++ Build"
--> "Settings" --> "Preprocessor" --> "Defined symbols (-D)", and
define the relevant PHDRIVER_<BoardNFCCombination>_BOARD macro.
e.g. For using K82 with Pn5190 use PHDRIVER_K82F_PNEV5190B_BOARD
and for LPC1769 with PN5190 use PHDRIVER_LPC1769PN5190_BOARD. For
list of supported boards refer to
Platform\DAL\cfg\BoardSelection.h.
2) To select the osal/os type, go to "Project Properties" --> "C/C++
Build" --> "Settings" --> "Preprocessor" --> "Defined symbols
(-D)".
e.g. For using FreeRTOS use PH_OSAL_FREERTOS. For other options
refer to RTOS\phOsal\inc\phOsal_Config.h.
14 Steps to follow for PI / Linux / CMake
=========================================
The steps are described in AN11802. (See Section-17, Bullet-5 below)
15 Running NfcrdlibEx5_ISO15693
===============================
Run the application and when you bring the ISO 15693 in proximity, the
example application will detect and displays the detected card
information on console.
16 List of supported NFC Reader Boards/ICs
==========================================
1) CLEV6630B v2.0 Customer Evaluation Board
2) PNEV5180B v2.0 Customer Evaluation Board
3) PN7462AU v2.1 Customer Evaluation Board
4) PNEV5190B v1.0 Customer Evaluation Board
17 Reference Documents
======================
1) UM10954 : PN5180 SW Quick start guide
[http://www.nxp.com/docs/en/user-guide/UM10954.pdf]
2) AN11908 : NFC Reader Library for FRDM-K82F Board Installation
guidelines
[http://www.nxp.com/docs/en/application-note/AN11908.pdf]
3) AN11022 : CLRC663 Evaluation board quick start guide
[http://www.nxp.com/docs/en/application-note/AN11022.pdf]
4) UM10883 : PN7462AU Quick Start Guide - Development Kit
[http://www.nxp.com/docs/en/user-guide/UM10883.pdf]
5) AN11802 : NFC Reader Library for Linux Installation Guidelines
[http://www.nxp.com/docs/en/application-note/AN11802.pdf]
6) AN12550 : PNEV5190B Evaluation board quick start guide
----------------------------------------------------------------------
For updates of this example, see
[http://www.nxp.com/products/:NFC-READER-LIBRARY]

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/*----------------------------------------------------------------------------*/
/* Copyright 2016-2021, 2023 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may only */
/* be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that you */
/* have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*----------------------------------------------------------------------------*/
/** \file
* Example Source Header for NfcrdlibEx5_ISO15693 application.
*
* $Author: NXP $
* $Revision: $ (v07.10.00)
* $Date: $
*/
#ifndef INTFS_NFCRDLIBEX5_ISO15693_H_
#define INTFS_NFCRDLIBEX5_ISO15693_H_
#include <ph_Status.h>
#ifdef PH_OSAL_FREERTOS
#ifdef PHOSAL_FREERTOS_STATIC_MEM_ALLOCATION
#define ISO15693_DEMO_TASK_STACK (1400/4)
#else /* PHOSAL_FREERTOS_STATIC_MEM_ALLOCATION */
#if defined( __PN74XXXX__) || defined(__PN76XX__)
#define ISO15693_DEMO_TASK_STACK (1300/4)
#else /* defined( __PN74XXXX__) || defined(__PN76XX__) */
#define ISO15693_DEMO_TASK_STACK (1250)
#endif /* defined( __PN74XXXX__) || defined(__PN76XX__) */
#endif
#define ISO15693_DEMO_TASK_PRIO 4
#endif /* PH_OSAL_FREERTOS */
#ifdef PH_OSAL_LINUX
#define ISO15693_DEMO_TASK_STACK 0x20000
#define ISO15693_DEMO_TASK_PRIO 0
#endif /* PH_OSAL_LINUX */
#if defined(NXPBUILD__PHHAL_HW_PN5190) || \
defined(NXPBUILD__PHHAL_HW_PN7462AU) || \
defined(NXPBUILD__PHHAL_HW_PN76XX)
#define CUSTOM_HIGH_DATA_RATE_DEMO
#ifdef CUSTOM_HIGH_DATA_RATE_DEMO
#define CUSTOM_HIGH_DATA_RATE_DEMO_TX106_RX106
#ifndef NXPBUILD__PHHAL_HW_PN7462AU
#ifndef CUSTOM_HIGH_DATA_RATE_DEMO_TX106_RX106
#define CUSTOM_HIGH_DATA_RATE_DEMO_TX212_RX212
#endif /* CUSTOM_HIGH_DATA_RATE_DEMO_TX106_RX106 */
#endif /* NXPBUILD__PHHAL_HW_PN7462AU */
#endif /* CUSTOM_HIGH_DATA_RATE_DEMO */
#endif
#endif /* INTFS_NFCRDLIBEX5_ISO15693_H_ */

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/*----------------------------------------------------------------------------*/
/* Copyright 2016-2023 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may only */
/* be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that you */
/* have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*----------------------------------------------------------------------------*/
/** \file
* Example Source abstracting component header specific to HW used in the examples
* This file shall be present in all examples. A customer does not need to touch/modify this file. This file
* purely depends on the phNxpBuild_Lpc.h or phNxpBuild_App.h
* The phAppInit.h externs the component data structures initialized here that is in turn included by the core examples.
* The core example shall not use any other variable defined here except the RdLib component data structures(as explained above)
* The RdLib component initialization requires some user defined data and function pointers.
* These are defined in the respective examples and externed here.
*
* Keystore and Crypto initialization needs to be handled by application.
*
* $Author$
* $Revision$ (v07.10.00)
* $Date$
*
*/
#ifndef PHAPP_INIT_H
#define PHAPP_INIT_H
/* Status header */
#include <ph_Status.h>
/* Driver Header */
#include <phDriver.h>
/* NFCLIB Header */
#include <phNfcLib.h>
/* LLCP header */
#include <phlnLlcp.h>
/* SNEP header */
#include <phnpSnep.h>
/* Check for K82 controller based boards. */
#if defined(PHDRIVER_FRDM_K82FPN5180_BOARD) || \
defined(PHDRIVER_FRDM_K82FRC663_BOARD) || \
defined(PHDRIVER_K82F_PNEV5190B_BOARD)
#define PHDRIVER_KINETIS_K82
#endif
/* Check for LPC1769 controller based boards. */
#if defined(PHDRIVER_LPC1769PN5180_BOARD) || \
defined(PHDRIVER_LPC1769RC663_BOARD) || \
defined(PHDRIVER_LPC1769PN5190_BOARD)
#define PHDRIVER_LPC1769
#endif
#if defined(PHDRIVER_PIPN5180_BOARD) || \
defined(PHDRIVER_PIRC663_BOARD) || \
defined(PHDRIVER_PIPN5190_BOARD)
#include <phDriver_Linux_Int.h>
#endif
#ifdef PHDRIVER_KINETIS_K82
# include <fsl_debug_console.h>
# include <stdio.h>
#endif
#if !defined(__PN76XX__)
#ifdef DEBUG
#ifdef PHDRIVER_KINETIS_K82
#if SDK_DEBUGCONSOLE==1
#define DEBUG_PRINTF DbgConsole_Printf
#else
#define DEBUG_PRINTF(...) printf(__VA_ARGS__);
#endif
#else /* PHDRIVER_KINETIS_K82 */
#include <stdio.h>
#define DEBUG_PRINTF(...) printf(__VA_ARGS__); fflush(stdout)
#endif /* PHDRIVER_KINETIS_K82 */
#else /* DEBUG */
#define DEBUG_PRINTF(...)
#define DEBUG_SCANF(...)
#endif /* DEBUG */
#else /* __PN76XX__ */
#if (SEGGER_RTT_ENABLE == 1)
#include "SEGGER_RTT.h"
#define DEBUG_PRINTF(...) SEGGER_RTT_printf(0, __VA_ARGS__);
#define DEBUG_SCANF(Input , data) *data = (SEGGER_RTT_WaitKey() - 0x30); SEGGER_RTT_WaitKey()
#else
#if DEBUG
#include <fsl_debug_console.h>
#define DEBUG_PRINTF(...) PRINTF(__VA_ARGS__);
#define DEBUG_SCANF(...) SCANF(__VA_ARGS__);while ((GETCHAR()) != '\n');
#define DEBUG_GETCHAR GETCHAR
#else
#define DEBUG_PRINTF(...)
#define DEBUG_SCANF(...)
#endif /* DEBUG */
#endif /* (SEGGER_RTT_ENABLE == 1) */
#endif /* __PN76XX__ */
/*******************************************************************************
** Global Variable Declaration
*******************************************************************************/
#define PH_NFCRDLIB_EXAMPLE_LPCD_GUARDTIME 100 /* LPCD Guard time(T4) in milli-seconds configured by application for Rc663. */
#define PH_NFCRDLIB_EXAMPLE_LPCD_RFON_TIME 56 /* LPCD RFON time(T3) in micro-seconds configured by application for Rc663. */
/* HAL & BAL declarations */
#ifdef PH_PLATFORM_HAS_ICFRONTEND
extern phbalReg_Type_t sBalParams;
#endif /* PH_PLATFORM_HAS_ICFRONTEND */
#ifdef NXPBUILD__PHLN_LLCP_SW
extern phlnLlcp_Sw_DataParams_t slnLlcp; /* LLCP component */
#endif /* NXPBUILD__PHLN_LLCP_SW */
#ifdef NXPBUILD__PHHAL_HW_PN5180
extern phhalHw_Pn5180_DataParams_t * pHal;
#endif /* NXPBUILD__PHHAL_HW_PN5180 */
#ifdef NXPBUILD__PHHAL_HW_PN5190
extern phhalHw_Pn5190_DataParams_t * pHal;
#endif /* NXPBUILD__PHHAL_HW_PN5190 */
#ifdef NXPBUILD__PHHAL_HW_RC663
extern phhalHw_Rc663_DataParams_t * pHal;
#endif /* NXPBUILD__PHHAL_HW_RC663 */
#ifdef NXPBUILD__PHHAL_HW_PN7462AU
extern phhalHw_PN7462AU_DataParams_t * pHal;
#endif /* NXPBUILD__PHHAL_HW_PN7462AU */
#ifdef NXPBUILD__PHHAL_HW_PN76XX
extern phhalHw_Pn76xx_DataParams_t * pHal;
#endif /* NXPBUILD__PHHAL_HW_PN76XX */
/**************************************************Prints if error is detected**************************************************************/
/* Enable(1) / Disable(0) printing error/info */
#define DETECT_ERROR 0
#if DETECT_ERROR
#define DEBUG_ERROR_PRINT(x) x
#define PRINT_INFO(...) DEBUG_PRINTF(__VA_ARGS__)
#else
#define DEBUG_ERROR_PRINT(x)
#define PRINT_INFO(...)
#endif
#define CHECK_STATUS(x) \
if ((x) != PH_ERR_SUCCESS) \
{ \
DEBUG_PRINTF("Line: %d Error - (0x%04X) has occurred : 0xCCEE CC-Component ID, EE-Error code. Refer-ph_Status.h\n", __LINE__, (x)); \
}
/* prints if error is detected */
#define CHECK_SUCCESS(x) \
if ((x) != PH_ERR_SUCCESS) \
{ \
DEBUG_PRINTF("\nLine: %d Error - (0x%04X) has occurred : 0xCCEE CC-Component ID, EE-Error code. Refer-ph_Status.h\n ", __LINE__, (x)); \
return (x); \
}
/* prints if error is detected */
#define CHECK_NFCLIB_STATUS(x) \
if ((x) != PH_NFCLIB_STATUS_SUCCESS) \
{ \
DEBUG_PRINTF("\nLine: %d Error - (0x%04X) has occurred in NFCLIB\n ", __LINE__, (x)); \
}
/*********************************************************************************************************************************************/
/*******************************************************************************
** Function Declarations
*******************************************************************************/
extern void phApp_CPU_Init(void);
extern phStatus_t phApp_Comp_Init(void * pDiscLoopParams);
extern phStatus_t phApp_HALConfigAutoColl(void);
extern phStatus_t phApp_ConfigureLPCD(void);
extern void phApp_PrintTagInfo(phacDiscLoop_Sw_DataParams_t *pDataParams, uint16_t wNumberOfTags, uint16_t wTagsDetected);
extern void phApp_PrintTech(uint8_t TechType);
extern void phApp_Print_Buff(uint8_t *pBuff, uint8_t num);
extern void PrintErrorInfo(phStatus_t wStatus);
extern phStatus_t phApp_Configure_IRQ();
#ifdef PH_PLATFORM_HAS_ICFRONTEND
extern void CLIF_IRQHandler(void);
#endif /* PH_PLATFORM_HAS_ICFRONTEND */
#endif /* PHAPP_INIT_H */

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@ -0,0 +1,253 @@
/*----------------------------------------------------------------------------*/
/* Copyright 2016-2023 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may only */
/* be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that you */
/* have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*----------------------------------------------------------------------------*/
/** \file
* Application specific selection of Reader Library Components
*
* $Author$
* $Revision$ (v07.10.00)
* $Date$
*
*/
#ifndef PH_NXPBUILD_APP_H_INC
#define PH_NXPBUILD_APP_H_INC
/** \defgroup ph_NxpBuild NXP Build
* \brief Controls the Inclusion of required components, Inclusion SRC/DATA within components and the Build Dependencies between the components
* @{
*/
/* NXPBUILD_DELETE: included code lines should be always removed from code */
/* NXP BUILD DEFINES */
/* use #define to include components */
/* comment out #define to exclude components */
/* DEBUG build mode */
/*#define NXPBUILD__PH_DEBUG*/ /**< DEBUG build definition */
#define NXPRDLIB_REM_GEN_INTFS
/*********************************************************************************************************************************************************************************/
#if defined(__PN74XXXX__) || defined (__PN73XXXX__)
#define NXPBUILD__PHHAL_HW_PN7462AU /**< NFC Controller PN7462AU HAL */
#endif
#ifdef __PN76XX__
#ifdef __PN7642__
#define NXPBUILD__PHHAL_HW_PN7642 /**< NFC Controller PN7642 HAL */
#elif __PN7640__
#define NXPBUILD__PHHAL_HW_PN7640 /**< NFC Controller PN7640 HAL */
#else
#error " PN76 platform definition (__PN7642__ or __PN7640__) missing !!! "
#endif
#if defined(__PN7642__) || defined(__PN7640__)
#define NXPBUILD__PHHAL_HW_PN76XX /**< NFC Controller PN76XX HAL */
#endif
#endif /* __PN76XX__ */
#if defined(PHDRIVER_LPC1769PN5180_BOARD) \
|| defined(PHDRIVER_FRDM_K82FPN5180_BOARD)
# define NXPBUILD__PHHAL_HW_PN5180
#endif
#if defined(PHDRIVER_LPC1769PN5190_BOARD) \
|| defined(PHDRIVER_K82F_PNEV5190B_BOARD)
# define NXPBUILD__PHHAL_HW_PN5190
#endif
#if defined(PHDRIVER_LPC1769RC663_BOARD) \
|| defined(PHDRIVER_FRDM_K82FRC663_BOARD)
# define NXPBUILD__PHHAL_HW_RC663
#endif
#if defined(NXPBUILD__PHHAL_HW_PN5180) || \
defined(NXPBUILD__PHHAL_HW_PN5190) || \
defined(NXPBUILD__PHHAL_HW_PN76XX) || \
defined(NXPBUILD__PHHAL_HW_PN7462AU)
// #define NXPBUILD__PHHAL_HW_TARGET /**< Dependency checking if target mode macros should be enabled */
#endif
/*********************************************************************************************************************************************************************************/
//#define NXPBUILD__PHPAL_I14443P3A_SW /**< PAL ISO 14443-3A SW Component is included. */
//#define NXPBUILD__PHPAL_I14443P3B_SW /**< PAL ISO 14443-3B SW Component is included. */
//#define NXPBUILD__PHPAL_I14443P4A_SW /**< PAL ISO 14443-4A SW Component is included. */
//#define NXPBUILD__PHPAL_I14443P4_SW /**< PAL ISO 14443-4 SW Component is included. */
//#define NXPBUILD__PHPAL_MIFARE_SW /**< PAL MIFARE SW Component is included */
//#define NXPBUILD__PHPAL_MIFARE_STUB /**< PAL MIFARE STUB Component is included */
//#define NXPBUILD__PHPAL_FELICA_SW /**< PAL Felica SW Component is included. */
#define NXPBUILD__PHPAL_SLI15693_SW /**< PAL SLI 15693 Component is included. */
//#define NXPBUILD__PHPAL_I18000P3M3_SW /**< PAL ISO 18000p3m3 Component is included. */
#ifdef NXPBUILD__PHHAL_HW_RC663 /**< If FE HAL is RC663, then include EPC UID PAL as required, otherwise exclude. */
// #define NXPBUILD__PHPAL_EPCUID_SW /**< PAL EPC UID SW Component is included. */
#endif
//#define NXPBUILD__PHPAL_I18092MPI_SW /**< PAL ISO18092 (P2P) SW Component is included. */
#ifndef NXPBUILD__PHHAL_HW_RC663 /**< If FE HAL is RC663, then exclude ISO14443 Card Mode PAL & ISO18092 Target Mode PAL, otherwise include as required. */
// #define NXPBUILD__PHPAL_I14443P4MC_SW /**< PAL ISO 14443-4 Card Mode SW Component is included. */
// #define NXPBUILD__PHPAL_I18092MT_SW /**< PAL ISO 18092 Target Mode SW Component is included. */
#endif /* NXPBUILD__PHHAL_HW_RC663 */
/*********************************************************************************************************************************************************************************/
#define NXPBUILD__PHAC_DISCLOOP_SW /**< Discovery Loop Activity SW Component is included. */
#ifdef NXPBUILD__PHAC_DISCLOOP_SW /**< If DiscLoop SW Component is included, macros( & it's dependencies) to include/exclude SRC/DATA within Discloop is defined. */
#if defined (NXPBUILD__PHHAL_HW_PN5180) || \
defined (NXPBUILD__PHHAL_HW_PN5190) || \
defined (NXPBUILD__PHHAL_HW_RC663) || \
defined (NXPBUILD__PHHAL_HW_PN7462AU) || \
defined (NXPBUILD__PHHAL_HW_PN7642)
// #define NXPBUILD__PHAC_DISCLOOP_LPCD /**< SRC to enable LPCD is included. */
#endif
#ifdef NXPBUILD__PHPAL_I14443P3A_SW
#define NXPBUILD__PHAC_DISCLOOP_TYPEA_I3P3_TAGS /**< SRC/DATA to Detect/CollRes/Activate cards such as MFC, MFUL, MFP SL1 etc is included. */
#define NXPBUILD__PHAC_DISCLOOP_TYPEA_JEWEL_TAGS /**< SRC/DATA to Detect cards such as NFC Forum T1T, Topaz/Jewel is included. */
#if defined(NXPBUILD__PHPAL_I14443P4A_SW) && defined(NXPBUILD__PHPAL_I14443P4_SW)
#define NXPBUILD__PHAC_DISCLOOP_TYPEA_I3P4_TAGS /**< SRC/DATA to Detect cards such as MFDF, MFP, T4AT NFC Forum Tag or Type A EMVCo is included. */
#endif
#endif /* NXPBUILD__PHPAL_I14443P3A_SW */
#if defined(NXPBUILD__PHPAL_I14443P3A_SW) && defined(NXPBUILD__PHPAL_I18092MPI_SW)
#define NXPBUILD__PHAC_DISCLOOP_TYPEA_P2P_TAGS /**< SRC/DATA to Detect Peer Passive Type A P2P Target mode devices is included. */
#endif
#ifndef NXPBUILD__PHHAL_HW_RC663
#ifdef NXPBUILD__PHPAL_I18092MPI_SW
#define NXPBUILD__PHAC_DISCLOOP_TYPEA_P2P_ACTIVE /**< SRC/DATA to Detect Peer Active Type A P2P Target mode devices is included. */
#define NXPBUILD__PHAC_DISCLOOP_TYPEF212_P2P_ACTIVE/**< SRC/DATA to Detect Peer Active Type F212 P2P Target mode devices is included. */
#define NXPBUILD__PHAC_DISCLOOP_TYPEF424_P2P_ACTIVE/**< SRC/DATA to Detect Peer Active Type F424 P2P Target mode devices is included. */
#endif /* NXPBUILD__PHPAL_I18092MPI_SW */
#endif /* NXPBUILD__PHHAL_HW_RC663 */
#ifdef NXPBUILD__PHPAL_FELICA_SW
#define NXPBUILD__PHAC_DISCLOOP_FELICA_TAGS /**< SRC/DATA to Detect FeliCa Cards is included. */
#ifdef NXPBUILD__PHPAL_I18092MPI_SW
#define NXPBUILD__PHAC_DISCLOOP_TYPEF_P2P_TAGS /**< SRC/DATA to Detect Peer Passive Type F P2P Target mode devices is included. */
#endif /* NXPBUILD__PHPAL_I18092MPI_SW */
#endif /* NXPBUILD__PHPAL_FELICA_SW */
#ifdef NXPBUILD__PHPAL_I14443P3B_SW
#define NXPBUILD__PHAC_DISCLOOP_TYPEB_I3P3B_TAGS /**< SRC/DATA to Detect Type B Cards that operate at Layer3 level is included */
#ifdef NXPBUILD__PHPAL_I14443P4_SW
#define NXPBUILD__PHAC_DISCLOOP_TYPEB_I3P4B_TAGS /**< SRC/DATA to Detect Type B Cards such as NFC Forum Type 4 Tags, EMVCo Type B Cards etc is included */
#endif /* NXPBUILD__PHPAL_I14443P4_SW */
#endif /* NXPBUILD__PHPAL_I14443P3B_SW */
#ifdef NXPBUILD__PHPAL_SLI15693_SW
#define NXPBUILD__PHAC_DISCLOOP_TYPEV_TAGS /**< SRC/DATA to Detect Type V Cards such as ICODE SLI/SLIX/SLI2/Tesa Cards is included*/
#endif /* NXPBUILD__PHPAL_SLI15693_SW */
#ifdef NXPBUILD__PHPAL_I18000P3M3_SW
#define NXPBUILD__PHAC_DISCLOOP_I18000P3M3_TAGS /**< SRC/DATA to Detect ICODE ILT Cards such as SMARTRAC StackIt Cards is included*/
#endif /* NXPBUILD__PHPAL_I18000P3M3_SW */
#ifndef NXPBUILD__PHHAL_HW_RC663 /**< If FE HAL is RC663, target mode is not supported at all, hence exclude those SRC, otherwise include as required */
#ifdef NXPBUILD__PHHAL_HW_TARGET
#define NXPBUILD__PHAC_DISCLOOP_TYPEA_TARGET_PASSIVE /**< SRC to Initialize Type A passive listen config and subsequently call HAL AutoColl is included. */
#define NXPBUILD__PHAC_DISCLOOP_TYPEA_TARGET_ACTIVE /**< SRC to Initialize Type A active listen config and subsequently call HAL AutoColl is included. */
#define NXPBUILD__PHAC_DISCLOOP_TYPEF212_TARGET_PASSIVE/**< SRC to Initialize Type F212 passive listen config and subsequently call HAL AutoColl is included. */
#define NXPBUILD__PHAC_DISCLOOP_TYPEF212_TARGET_ACTIVE /**< SRC to Initialize Type F212 active listen config and subsequently call HAL AutoColl is included. */
#define NXPBUILD__PHAC_DISCLOOP_TYPEF424_TARGET_PASSIVE/**< SRC to Initialize Type F424 passive listen config and subsequently call HAL AutoColl is included. */
#define NXPBUILD__PHAC_DISCLOOP_TYPEF424_TARGET_ACTIVE /**< SRC to Initialize Type F424 active listen config and subsequently call HAL AutoColl is included. */
#endif /* NXPBUILD__PHHAL_HW_TARGET */
#endif
#endif /* NXPBUILD__PHAC_DISCLOOP_SW */
/*********************************************************************************************************************************************************************************/
#define NXPBUILD__PHNFCLIB /**< Simplified API Interface, If enabling this the entry point should be this component in the application */
/*********************************************************************************************************************************************************************************/
//#define NXPBUILD__PH_CIDMANAGER_SW /**< CID Manager SW Component is included. */
#define NXPBUILD__PH_KEYSTORE_SW /**< SW KeyStore Component is included. */
#if defined(NXPBUILD__PHHAL_HW_RC663) && !defined(NXPBUILD__PH_KEYSTORE_SW)
// #define NXPBUILD__PH_KEYSTORE_RC663 /**< RC663 KeyStore Component is included. */
#endif
//#define NXPBUILD__PH_NDA_MFDF /**< MIFARE DESFire contactless IC */
#define NXPBUILD__PH_CRYPTOSYM_SW /**< Crypto Symbols SW Component is included. */
#define NXPBUILD__PH_CRYPTORNG_SW /**< Crypto RNG SW Component is included. */
/*********************************************************************************************************************************************************************************/
#ifdef NXPBUILD__PHPAL_FELICA_SW
#define NXPBUILD__PHAL_FELICA_SW /**< AL FeliCa SW Component is included */
#endif /* NXPBUILD__PHPAL_FELICA_SW */
#ifdef NXPBUILD__PHPAL_MIFARE_SW
#if defined(NXPBUILD__PH_KEYSTORE_SW) || defined(NXPBUILD__PH_KEYSTORE_RC663)
#define NXPBUILD__PHAL_MFC_SW /**< AL MIFARE Classic contactless IC SW Component is included */
#endif
#define NXPBUILD__PHAL_MFUL_SW /**< AL Mifare Ultrlight SW Component is included */
#define NXPBUILD__PHAL_MFDF_SW /**< AL Mifare DesFire SW Component is included */
// #define NXPBUILD__PHAL_MFNTAG42XDNA_SW /**< AL MIFARE Prime Ntag42XDna contactless IC SW Component is included */
#endif /* NXPBUILD__PHPAL_MIFARE_SW */
//#define NXPBUILD__PHAL_T1T_SW /**< AL Type T1 Tag SW Component is included */
#ifdef NXPBUILD__PHPAL_SLI15693_SW
#define NXPBUILD__PHAL_ICODE_SW /**< AL ICODE SW COMPONENT is included */
#endif /* NXPBUILD__PHPAL_SLI15693_SW */
//#define NXPBUILD__PHAL_TOP_SW /**< AL for TagOps Mapping SW Component is included.Required for NDEF operations */
#ifdef NXPBUILD__PHPAL_I18000P3M3_SW
#define NXPBUILD__PHAL_I18000P3M3_SW /**< AL ISO18000p3m3 SW Component is included */
#endif /* NXPBUILD__PHPAL_I18000P3M3_SW */
#ifdef NXPBUILD__PHPAL_I14443P4MC_SW
#if !defined(PH_OSAL_NULLOS)
#define NXPBUILD__PHCE_T4T_SW /**< AL HCE T2AT SW Component is included */
//#define NXPBUILD__PHCE_T4T_PROPRIETARY /**< SRC to handle HCE T4AT Proprietary Commands is included */
/*#define NXPBUILD__PHCE_T4T_EXT_NDEF */ /**< SRC to handle Extended NDEF Support as per T4T spec 3.0 is included */
#endif
#endif /* NXPBUILD__PHPAL_I14443P4MC_SW */
/* LLCP Components */
#if defined(NXPBUILD__PHPAL_I18092MPI_SW) || defined(NXPBUILD__PHPAL_I18092MT_SW)
#if !defined(PH_OSAL_NULLOS)
#define NXPBUILD__PHLN_LLCP_SW /**< Link LLCP SW Component is included */
#endif
#endif
/* SNEP components */
#ifdef NXPBUILD__PHLN_LLCP_SW
#define NXPBUILD__PHNP_SNEP_SW /**< Protocol SNEP SW Component is included */
#endif /* NXPBUILD__PHLN_LLCP_SW */
/* Enable/disable Debugging */
/*#define NXPBUILD__PH_DEBUG*/ /**< TODO: To be checked if required */
/** @}
* end of ph_NxpBuild
*/
#endif /* PH_NXPBUILD_APP_H_INC */

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<?xml version="1.0" encoding="UTF-8" standalone="no"?><?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
<storageModule moduleId="org.eclipse.cdt.core.settings">
<cconfiguration id="com.crt.advproject.config.exe.debug.738429693">
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.crt.advproject.config.exe.debug.738429693" moduleId="org.eclipse.cdt.core.settings" name="DebugLPC1769">
<externalSettings />
<extensions>
<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser" />
<extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser" />
<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser" />
<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser" />
<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser" />
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<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser" />
</extensions>
</storageModule>
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
<configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="rm -rf" description="Debug build for LPC1769" errorParsers="org.eclipse.cdt.core.CWDLocator;org.eclipse.cdt.core.GmakeErrorParser;org.eclipse.cdt.core.GCCErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.GASErrorParser" id="com.crt.advproject.config.exe.debug.738429693" name="DebugLPC1769" parent="com.crt.advproject.config.exe.debug" postannouncebuildStep="Performing post-build steps" postbuildStep="arm-none-eabi-size &quot;${BuildArtifactFileName}&quot; ; arm-none-eabi-objcopy -O binary &quot;${BuildArtifactFileName}&quot; &quot;${BuildArtifactFileBaseName}.bin&quot; ; #checksum -p ${TargetChip} -d &quot;${BuildArtifactFileBaseName}.bin&quot;" preannouncebuildStep="" prebuildStep="">
<folderInfo id="com.crt.advproject.config.exe.debug.738429693." name="/" resourcePath="">
<toolChain errorParsers="" id="com.crt.advproject.toolchain.exe.debug.1486081712" name="Code Red MCU Tools" superClass="com.crt.advproject.toolchain.exe.debug">
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<comment></comment>
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View File

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//*****************************************************************************
// LPC175x_6x Microcontroller Startup code for use with LPCXpresso IDE
//
// Version : 140114
//*****************************************************************************
//
// Copyright(C) NXP Semiconductors, 2014
// All rights reserved.
//
// Software that is described herein is for illustrative purposes only
// which provides customers with programming information regarding the
// LPC products. This software is supplied "AS IS" without any warranties of
// any kind, and NXP Semiconductors and its licensor disclaim any and
// all warranties, express or implied, including all implied warranties of
// merchantability, fitness for a particular purpose and non-infringement of
// intellectual property rights. NXP Semiconductors assumes no responsibility
// or liability for the use of the software, conveys no license or rights under any
// patent, copyright, mask work right, or any other intellectual property rights in
// or to any products. NXP Semiconductors reserves the right to make changes
// in the software without notification. NXP Semiconductors also makes no
// representation or warranty that such application will be suitable for the
// specified use without further testing or modification.
//
// Permission to use, copy, modify, and distribute this software and its
// documentation is hereby granted, under NXP Semiconductors' and its
// licensor's relevant copyrights in the software, without fee, provided that it
// is used in conjunction with NXP Semiconductors microcontrollers. This
// copyright, permission, and disclaimer notice must appear in all copies of
// this code.
//*****************************************************************************
#include <ph_Status.h>
#include <cr_section_macros.h>
#include <NXP/crp.h>
#ifdef DEBUG
# define VT_IMAGE_LENGTH 0x76706b64U
#else /* DEBUG */
# define VT_IMAGE_LENGTH 0xFFFFFFFFU
#endif /* DEBUG */
#if defined (__cplusplus)
#ifdef __REDLIB__
#error Redlib does not support C++
#else
//*****************************************************************************
//
// The entry point for the C++ library startup
//
//*****************************************************************************
extern "C" {
extern void __libc_init_array(void);
}
#endif
#endif
#define WEAK __attribute__ ((weak))
#define ALIAS(f) __attribute__ ((weak, alias (#f)))
__CRP const unsigned int CRP_WORD = CRP_NO_CRP;
//*****************************************************************************
#if defined (__cplusplus)
extern "C" {
#endif
//*****************************************************************************
#if defined (__USE_CMSIS) || defined (__USE_LPCOPEN)
// Declaration of external SystemInit function
void SystemInit(void);
extern void Board_SystemInit(void);
extern void Chip_SystemInit(void);
extern void SystemCoreClockUpdate(void);
#endif
//*****************************************************************************
//
// Forward declaration of the default handlers. These are aliased.
// When the application defines a handler (with the same name), this will
// automatically take precedence over these weak definitions
//
//*****************************************************************************
void ResetISR(void);
WEAK void NMI_Handler(void);
//WEAK void HardFault_Handler(void);
WEAK void MemManage_Handler(void);
WEAK void BusFault_Handler(void);
WEAK void UsageFault_Handler(void);
WEAK void SVC_Handler(void);
WEAK void DebugMon_Handler(void);
WEAK void PendSV_Handler(void);
WEAK void SysTick_Handler(void);
WEAK void IntDefaultHandler(void);
/* The prototype shows it is a naked function - in effect this is just an
assembly function. */
void HardFault_Handler( void ) __attribute__( ( naked ) );
//*****************************************************************************
//
// Forward declaration of the specific IRQ handlers. These are aliased
// to the IntDefaultHandler, which is a 'forever' loop. When the application
// defines a handler (with the same name), this will automatically take
// precedence over these weak definitions
//
//*****************************************************************************
void WDT_IRQHandler(void) ALIAS(IntDefaultHandler);
void TIMER0_IRQHandler(void) ALIAS(IntDefaultHandler);
void TIMER1_IRQHandler(void) ALIAS(IntDefaultHandler);
void TIMER2_IRQHandler(void) ALIAS(IntDefaultHandler);
void TIMER3_IRQHandler(void) ALIAS(IntDefaultHandler);
void UART0_IRQHandler(void) ALIAS(IntDefaultHandler);
void UART1_IRQHandler(void) ALIAS(IntDefaultHandler);
void UART2_IRQHandler(void) ALIAS(IntDefaultHandler);
void UART3_IRQHandler(void) ALIAS(IntDefaultHandler);
void PWM1_IRQHandler(void) ALIAS(IntDefaultHandler);
void I2C0_IRQHandler(void) ALIAS(IntDefaultHandler);
void I2C1_IRQHandler(void) ALIAS(IntDefaultHandler);
void I2C2_IRQHandler(void) ALIAS(IntDefaultHandler);
void SPI_IRQHandler(void) ALIAS(IntDefaultHandler);
void SSP0_IRQHandler(void) ALIAS(IntDefaultHandler);
void SSP1_IRQHandler(void) ALIAS(IntDefaultHandler);
void PLL0_IRQHandler(void) ALIAS(IntDefaultHandler);
void RTC_IRQHandler(void) ALIAS(IntDefaultHandler);
void EINT0_IRQHandler(void) ALIAS(IntDefaultHandler);
void EINT1_IRQHandler(void) ALIAS(IntDefaultHandler);
void EINT2_IRQHandler(void) ALIAS(IntDefaultHandler);
void CLIF_IRQHandler(void) ALIAS(IntDefaultHandler);
void ADC_IRQHandler(void) ALIAS(IntDefaultHandler);
void BOD_IRQHandler(void) ALIAS(IntDefaultHandler);
void USB_IRQHandler(void) ALIAS(IntDefaultHandler);
void CAN_IRQHandler(void) ALIAS(IntDefaultHandler);
void DMA_IRQHandler(void) ALIAS(IntDefaultHandler);
void I2S_IRQHandler(void) ALIAS(IntDefaultHandler);
#if defined (__USE_LPCOPEN)
void ETH_IRQHandler(void) ALIAS(IntDefaultHandler);
#else
void ENET_IRQHandler(void) ALIAS(IntDefaultHandler);
#endif
void RIT_IRQHandler(void) ALIAS(IntDefaultHandler);
void MCPWM_IRQHandler(void) ALIAS(IntDefaultHandler);
void QEI_IRQHandler(void) ALIAS(IntDefaultHandler);
void PLL1_IRQHandler(void) ALIAS(IntDefaultHandler);
void USBActivity_IRQHandler(void) ALIAS(IntDefaultHandler);
void CANActivity_IRQHandler(void) ALIAS(IntDefaultHandler);
void UART4_IRQHandler(void) ALIAS(IntDefaultHandler);
void SSP2_IRQHandler(void) ALIAS(IntDefaultHandler);
void LCD_IRQHandler(void) ALIAS(IntDefaultHandler);
void GPIO_IRQHandler(void) ALIAS(IntDefaultHandler);
void PWM0_IRQHandler(void) ALIAS(IntDefaultHandler);
void EEPROM_IRQHandler(void) ALIAS(IntDefaultHandler);
//*****************************************************************************
//
// The entry point for the application.
// __main() is the entry point for Redlib based applications
// main() is the entry point for Newlib based applications
//
//*****************************************************************************
#if defined (__REDLIB__)
extern void __main(void);
#endif
extern int main(void);
//*****************************************************************************
//
// External declaration for the pointer to the stack top from the Linker Script
//
//*****************************************************************************
extern void _vStackTop(void);
//*****************************************************************************
#if defined (__cplusplus)
} // extern "C"
#endif
//*****************************************************************************
//
// The vector table.
// This relies on the linker script to place at correct location in memory.
//
//*****************************************************************************
extern void (* const g_pfnVectors[])(void);
__attribute__ ((section(".isr_vector")))
void (* const g_pfnVectors[])(void) = {
// Core Level - CM3
&_vStackTop, // The initial stack pointer
ResetISR, // The reset handler
NMI_Handler, // The NMI handler
HardFault_Handler, // The hard fault handler
MemManage_Handler, // The MPU fault handler
BusFault_Handler, // The bus fault handler
UsageFault_Handler, // The usage fault handler
0, // Reserved
0, // Reserved
0, // Reserved
0, // Reserved
SVC_Handler, // SVCall handler
DebugMon_Handler, // Debug monitor handler
0, // Reserved
PendSV_Handler, // The PendSV handler
SysTick_Handler, // The SysTick handler
// Chip Level - LPC17
WDT_IRQHandler, // 16, 0x40 - WDT
TIMER0_IRQHandler, // 17, 0x44 - TIMER0
TIMER1_IRQHandler, // 18, 0x48 - TIMER1
TIMER2_IRQHandler, // 19, 0x4c - TIMER2
TIMER3_IRQHandler, // 20, 0x50 - TIMER3
UART0_IRQHandler, // 21, 0x54 - UART0
UART1_IRQHandler, // 22, 0x58 - UART1
UART2_IRQHandler, // 23, 0x5c - UART2
UART3_IRQHandler, // 24, 0x60 - UART3
PWM1_IRQHandler, // 25, 0x64 - PWM1
I2C0_IRQHandler, // 26, 0x68 - I2C0
I2C1_IRQHandler, // 27, 0x6c - I2C1
I2C2_IRQHandler, // 28, 0x70 - I2C2
SPI_IRQHandler, // 29, 0x74 - SPI
SSP0_IRQHandler, // 30, 0x78 - SSP0
SSP1_IRQHandler, // 31, 0x7c - SSP1
PLL0_IRQHandler, // 32, 0x80 - PLL0 (Main PLL)
RTC_IRQHandler, // 33, 0x84 - RTC
EINT0_IRQHandler, // 34, 0x88 - EINT0
EINT1_IRQHandler, // 35, 0x8c - EINT1
EINT2_IRQHandler, // 36, 0x90 - EINT2
CLIF_IRQHandler, // 37, 0x94 - EINT3 (Used for CLIF IRQ)
ADC_IRQHandler, // 38, 0x98 - ADC
BOD_IRQHandler, // 39, 0x9c - BOD
USB_IRQHandler, // 40, 0xA0 - USB
CAN_IRQHandler, // 41, 0xa4 - CAN
DMA_IRQHandler, // 42, 0xa8 - GP DMA
I2S_IRQHandler, // 43, 0xac - I2S
#if defined (__USE_LPCOPEN)
ETH_IRQHandler, // 44, 0xb0 - Ethernet
#else
ENET_IRQHandler, // 44, 0xb0 - Ethernet
#endif
RIT_IRQHandler, // 45, 0xb4 - RITINT
MCPWM_IRQHandler, // 46, 0xb8 - Motor Control PWM
QEI_IRQHandler, // 47, 0xbc - Quadrature Encoder
PLL1_IRQHandler, // 48, 0xc0 - PLL1 (USB PLL)
USBActivity_IRQHandler, // 49, 0xc4 - USB Activity interrupt to wakeup
CANActivity_IRQHandler, // 50, 0xc8 - CAN Activity interrupt to wakeup
UART4_IRQHandler, //; 51 UART4
SSP2_IRQHandler, //; 52 SSP2
LCD_IRQHandler, //; 53 LCD
GPIO_IRQHandler, //; 54 GPIO
PWM0_IRQHandler , //; 55 PWM0
EEPROM_IRQHandler, //; 56 EEPROM
(void *)VT_IMAGE_LENGTH, //; 57 VT Checksum for CRC Check of Vector Table.
};
//*****************************************************************************
// Functions to carry out the initialization of RW and BSS data sections. These
// are written as separate functions rather than being inlined within the
// ResetISR() function in order to cope with MCUs with multiple banks of
// memory.
//*****************************************************************************
__attribute__ ((section(".after_vectors")))
void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
unsigned int *pulDest = (unsigned int*) start;
unsigned int *pulSrc = (unsigned int*) romstart;
unsigned int loop;
for (loop = 0; loop < len; loop = loop + 4)
*pulDest++ = *pulSrc++;
}
__attribute__ ((section(".after_vectors")))
void bss_init(unsigned int start, unsigned int len) {
unsigned int *pulDest = (unsigned int*) start;
unsigned int loop;
for (loop = 0; loop < len; loop = loop + 4)
*pulDest++ = 0;
}
//*****************************************************************************
// The following symbols are constructs generated by the linker, indicating
// the location of various points in the "Global Section Table". This table is
// created by the linker via the Code Red managed linker script mechanism. It
// contains the load address, execution address and length of each RW data
// section and the execution and length of each BSS (zero initialized) section.
//*****************************************************************************
extern unsigned int __data_section_table;
extern unsigned int __data_section_table_end;
extern unsigned int __bss_section_table;
extern unsigned int __bss_section_table_end;
//*****************************************************************************
// Reset entry point for your code.
// Sets up a simple runtime environment and initializes the C/C++
// library.
//*****************************************************************************
__attribute__ ((section(".after_vectors")))
void
ResetISR(void) {
//
// Copy the data sections from flash to SRAM.
//
unsigned int LoadAddr, ExeAddr, SectionLen;
unsigned int *SectionTableAddr;
// Load base address of Global Section Table
SectionTableAddr = &__data_section_table;
// Copy the data sections from flash to SRAM.
while (SectionTableAddr < &__data_section_table_end) {
LoadAddr = *SectionTableAddr++;
ExeAddr = *SectionTableAddr++;
SectionLen = *SectionTableAddr++;
data_init(LoadAddr, ExeAddr, SectionLen);
}
// At this point, SectionTableAddr = &__bss_section_table;
// Zero fill the bss segment
while (SectionTableAddr < &__bss_section_table_end) {
ExeAddr = *SectionTableAddr++;
SectionLen = *SectionTableAddr++;
bss_init(ExeAddr, SectionLen);
}
#if defined (__USE_CMSIS) || defined (__USE_LPCOPEN)
SystemInit();
#endif
#if defined (__cplusplus)
//
// Call C++ library initialisation
//
__libc_init_array();
#endif
#if defined (__REDLIB__)
// Call the Redlib library, which in turn calls main()
__main() ;
#else
main();
#endif
//
// main() shouldn't return, but if it does, we'll just enter an infinite loop
//
while (1) {
;
}
}
/* Set up and initialize hardware prior to call to main */
void SystemInit(void)
{
unsigned int *pSCB_VTOR = (unsigned int *) 0xE000ED08;
#if defined(__IAR_SYSTEMS_ICC__)
extern void *__vector_table;
*pSCB_VTOR = (unsigned int) &__vector_table;
#elif defined(__CODE_RED)
*pSCB_VTOR = (unsigned int) &g_pfnVectors;
#elif defined(__ARMCC_VERSION)
extern void *__Vectors;
*pSCB_VTOR = (unsigned int) &__Vectors;
#endif
#if defined(__FPU_PRESENT) && __FPU_PRESENT == 1
fpuInit();
#endif
#if defined(NO_BOARD_LIB)
/* Chip specific SystemInit */
Chip_SystemInit();
#else
/* Setup system clocking and muxing */
Board_SystemInit();
#endif
/* Update system core clock rate. */
SystemCoreClockUpdate();
}
//*****************************************************************************
// Default exception handlers. Override the ones here by defining your own
// handler routines in your application code.
//*****************************************************************************
__attribute__ ((section(".after_vectors")))
void NMI_Handler(void)
{ while(1) {}
}
/* The fault handler implementation calls a function called
prvGetRegistersFromStack(). */
__attribute__ ((section(".after_vectors")))
void HardFault_Handler(void)
{
/* Use assembly to pick up date, but feed to C Code. */
__asm( ".syntax divided\n"
"MOVS R0, #4 \n"
"MOV R1, LR \n"
"TST R0, R1 \n"
"BEQ _MSP \n"
"MRS R0, PSP \n"
"B HardFault_HandlerC \n"
"_MSP: \n"
"MRS R0, MSP \n"
"B HardFault_HandlerC \n"
".syntax divided\n") ;
__asm(".syntax unified");
}
__attribute__ ((section(".after_vectors")))
void HardFault_HandlerC(
unsigned long *args)
{
volatile unsigned long cm_r0;
volatile unsigned long cm_r1;
volatile unsigned long cm_r2;
volatile unsigned long cm_r3;
volatile unsigned long cm_r12;
volatile unsigned long cm_lr;
volatile unsigned long cm_pc;
volatile unsigned long cm_psr;
//if (((uint32_t) args < PH_RAM_MEM_END)&& ( (uint32_t)args > PH_RAM_MEM_START))
//0x10000000 -- 0x8000
//0x2007c000 -- 0x8000
{
cm_r0 = ((unsigned long)args[0]);
cm_r1 = ((unsigned long)args[1]);
cm_r2 = ((unsigned long)args[2]);
cm_r3 = ((unsigned long)args[3]);
cm_r12 = ((unsigned long)args[4]);
cm_lr = ((unsigned long)args[5]);
cm_pc = ((unsigned long)args[6]);
cm_psr = ((unsigned long)args[7]);
PH_UNUSED_VARIABLE(cm_r0);
PH_UNUSED_VARIABLE(cm_r1);
PH_UNUSED_VARIABLE(cm_r2);
PH_UNUSED_VARIABLE(cm_r3);
PH_UNUSED_VARIABLE(cm_r12);
PH_UNUSED_VARIABLE(cm_lr);
PH_UNUSED_VARIABLE(cm_pc);
PH_UNUSED_VARIABLE(cm_psr);
}
/* Break into the debugger */
__asm("BKPT #0\n");
while (1)
{
__asm("wfi\n");
}
}
__attribute__ ((section(".after_vectors")))
void MemManage_Handler(void)
{ while(1) {}
}
__attribute__ ((section(".after_vectors")))
void BusFault_Handler(void)
{ while(1) {}
}
__attribute__ ((section(".after_vectors")))
void UsageFault_Handler(void)
{ while(1) {}
}
__attribute__ ((section(".after_vectors")))
void SVC_Handler(void)
{ while(1) {}
}
__attribute__ ((section(".after_vectors")))
void DebugMon_Handler(void)
{ while(1) {}
}
__attribute__ ((section(".after_vectors")))
void PendSV_Handler(void)
{ while(1) {}
}
//*****************************************************************************
//
// Processor ends up here if an unexpected interrupt occurs or a specific
// handler is not present in the application code.
//
//*****************************************************************************
__attribute__ ((section(".after_vectors")))
void IntDefaultHandler(void)
{ while(1) {}
}

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@ -0,0 +1,375 @@
/*----------------------------------------------------------------------------*/
/* Copyright 2020 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may only */
/* be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that you */
/* have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*----------------------------------------------------------------------------*/
/** \file
* Example Source abstracting component data structure and code initialization and code specific to HW used in the examples
* This file shall be present in all examples. A customer does not need to touch/modify this file. This file
* purely depends on the phNxpBuild_Lpc.h or phNxpBuild_App.h
* The phAppInit.h externs the component data structures initialized here that is in turn included by the core examples.
* The core example shall not use any other variable defined here except the RdLib component data structures(as explained above)
* The RdLib component initialization requires some user defined data and function pointers.
* These are defined in the respective examples and externed here.
*
* Keystore and Crypto initialization needs to be handled by application.
*
* $Author$
* $Revision$ (v07.10.00)
* $Date$
*
*/
#include "phApp_Init.h"
#include <phOsal.h>
/*******************************************************************************
** Function Declarations
*******************************************************************************/
/*******************************************************************************
** Function Definitions
*******************************************************************************/
/* Print technology being resolved */
void phApp_PrintTech(uint8_t TechType)
{
switch(TechType)
{
case PHAC_DISCLOOP_POS_BIT_MASK_A:
DEBUG_PRINTF ("\tResolving Type A... \n");
break;
case PHAC_DISCLOOP_POS_BIT_MASK_B:
DEBUG_PRINTF ("\tResolving Type B... \n");
break;
case PHAC_DISCLOOP_POS_BIT_MASK_F212:
DEBUG_PRINTF ("\tResolving Type F with baud rate 212... \n");
break;
case PHAC_DISCLOOP_POS_BIT_MASK_F424:
DEBUG_PRINTF ("\tResolving Type F with baud rate 424... \n");
break;
case PHAC_DISCLOOP_POS_BIT_MASK_V:
DEBUG_PRINTF ("\tResolving Type V... \n");
break;
default:
break;
}
}
/**
* This function will print buffer content
* \param *pBuff Buffer Reference
* \param num data size to be print
*/
void phApp_Print_Buff(uint8_t *pBuff, uint8_t num)
{
uint32_t i;
for(i = 0; i < num; i++)
{
DEBUG_PRINTF(" %02X",pBuff[i]);
}
}
/**
* This function will print Tag information
* \param pDataParams The discovery loop data parameters
* \param wNumberOfTags Total number of tags detected
* \param wTagsDetected Technology Detected
*/
void phApp_PrintTagInfo(phacDiscLoop_Sw_DataParams_t *pDataParams, uint16_t wNumberOfTags, uint16_t wTagsDetected)
{
#if defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_TAGS) || \
defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_P2P_ACTIVE) || \
defined(NXPBUILD__PHAC_DISCLOOP_TYPEB_TAGS) || \
defined(NXPBUILD__PHAC_DISCLOOP_TYPEF_TAGS) || \
defined(NXPBUILD__PHAC_DISCLOOP_TYPEV_TAGS) || \
defined(NXPBUILD__PHAC_DISCLOOP_I18000P3M3_TAGS)
uint8_t bIndex;
#endif
#if defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_TAGS) || defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_P2P_ACTIVE)
uint8_t bTagType;
#endif
#if defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_TAGS) || defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_P2P_ACTIVE)
if (PHAC_DISCLOOP_CHECK_ANDMASK(wTagsDetected, PHAC_DISCLOOP_POS_BIT_MASK_A))
{
if(pDataParams->sTypeATargetInfo.bT1TFlag)
{
DEBUG_PRINTF("\tTechnology : Type A");
DEBUG_PRINTF ("\n\t\tUID :");
phApp_Print_Buff( pDataParams->sTypeATargetInfo.aTypeA_I3P3[0].aUid,
pDataParams->sTypeATargetInfo.aTypeA_I3P3[0].bUidSize);
DEBUG_PRINTF ("\n\t\tSAK : 0x%02x",pDataParams->sTypeATargetInfo.aTypeA_I3P3[0].aSak);
DEBUG_PRINTF ("\n\t\tType: Type 1 Tag\n");
}
else
{
DEBUG_PRINTF("\tTechnology : Type A");
for(bIndex = 0; bIndex < wNumberOfTags; bIndex++)
{
DEBUG_PRINTF ("\n\t\tCard: %d",bIndex + 1);
DEBUG_PRINTF ("\n\t\tUID :");
phApp_Print_Buff( pDataParams->sTypeATargetInfo.aTypeA_I3P3[bIndex].aUid,
pDataParams->sTypeATargetInfo.aTypeA_I3P3[bIndex].bUidSize);
DEBUG_PRINTF ("\n\t\tSAK : 0x%02x",pDataParams->sTypeATargetInfo.aTypeA_I3P3[bIndex].aSak);
if ((pDataParams->sTypeATargetInfo.aTypeA_I3P3[bIndex].aSak & (uint8_t) ~0xFB) == 0)
{
/* Bit b3 is set to zero, [Digital] 4.8.2 */
/* Mask out all other bits except for b7 and b6 */
bTagType = (pDataParams->sTypeATargetInfo.aTypeA_I3P3[bIndex].aSak & 0x60);
bTagType = bTagType >> 5;
switch(bTagType)
{
case PHAC_DISCLOOP_TYPEA_TYPE2_TAG_CONFIG_MASK:
DEBUG_PRINTF ("\n\t\tType: Type 2 Tag\n");
break;
case PHAC_DISCLOOP_TYPEA_TYPE4A_TAG_CONFIG_MASK:
DEBUG_PRINTF ("\n\t\tType: Type 4A Tag\n");
break;
case PHAC_DISCLOOP_TYPEA_TYPE_NFC_DEP_TAG_CONFIG_MASK:
DEBUG_PRINTF ("\n\t\tType: P2P\n");
break;
case PHAC_DISCLOOP_TYPEA_TYPE_NFC_DEP_TYPE4A_TAG_CONFIG_MASK:
DEBUG_PRINTF ("\n\t\tType: Type NFC_DEP and 4A Tag\n");
break;
default:
break;
}
}
}
}
}
#endif
#ifdef NXPBUILD__PHAC_DISCLOOP_TYPEB_TAGS
if (PHAC_DISCLOOP_CHECK_ANDMASK(wTagsDetected, PHAC_DISCLOOP_POS_BIT_MASK_B))
{
DEBUG_PRINTF("\tTechnology : Type B");
/* Loop through all the Type B tags detected and print the Pupi */
for (bIndex = 0; bIndex < wNumberOfTags; bIndex++)
{
DEBUG_PRINTF ("\n\t\tCard: %d",bIndex + 1);
DEBUG_PRINTF ("\n\t\tUID :");
/* PUPI Length is always 4 bytes */
phApp_Print_Buff( pDataParams->sTypeBTargetInfo.aTypeB_I3P3[bIndex].aPupi, 0x04);
}
DEBUG_PRINTF("\n");
}
#endif /* NXPBUILD__PHAC_DISCLOOP_TYPEB_TAGS */
#ifdef NXPBUILD__PHAC_DISCLOOP_TYPEF_TAGS
if( PHAC_DISCLOOP_CHECK_ANDMASK(wTagsDetected, PHAC_DISCLOOP_POS_BIT_MASK_F212) ||
PHAC_DISCLOOP_CHECK_ANDMASK(wTagsDetected, PHAC_DISCLOOP_POS_BIT_MASK_F424))
{
DEBUG_PRINTF("\tTechnology : Type F");
/* Loop through all the type F tags and print the IDm */
for (bIndex = 0; bIndex < wNumberOfTags; bIndex++)
{
DEBUG_PRINTF ("\n\t\tCard: %d",bIndex + 1);
DEBUG_PRINTF ("\n\t\tUID :");
phApp_Print_Buff( pDataParams->sTypeFTargetInfo.aTypeFTag[bIndex].aIDmPMm,
PHAC_DISCLOOP_FELICA_IDM_LENGTH );
if ((pDataParams->sTypeFTargetInfo.aTypeFTag[bIndex].aIDmPMm[0] == 0x01) &&
(pDataParams->sTypeFTargetInfo.aTypeFTag[bIndex].aIDmPMm[1] == 0xFE))
{
/* This is Type F tag with P2P capabilities */
DEBUG_PRINTF ("\n\t\tType: P2P");
}
else
{
/* This is Type F T3T tag */
DEBUG_PRINTF ("\n\t\tType: Type 3 Tag");
}
if(pDataParams->sTypeFTargetInfo.aTypeFTag[bIndex].bBaud != PHAC_DISCLOOP_CON_BITR_212)
{
DEBUG_PRINTF ("\n\t\tBit Rate: 424\n");
}
else
{
DEBUG_PRINTF ("\n\t\tBit Rate: 212\n");
}
}
}
#endif /* NXPBUILD__PHAC_DISCLOOP_TYPEF_TAGS */
#ifdef NXPBUILD__PHAC_DISCLOOP_TYPEV_TAGS
if (PHAC_DISCLOOP_CHECK_ANDMASK(wTagsDetected, PHAC_DISCLOOP_POS_BIT_MASK_V))
{
DEBUG_PRINTF("\tTechnology : Type V / ISO 15693 / T5T");
/* Loop through all the Type V tags detected and print the UIDs */
for (bIndex = 0; bIndex < wNumberOfTags; bIndex++)
{
DEBUG_PRINTF ("\n\t\tCard: %d",bIndex + 1);
DEBUG_PRINTF ("\n\t\tUID :");
phApp_Print_Buff( pDataParams->sTypeVTargetInfo.aTypeV[bIndex].aUid, 0x08);
}
DEBUG_PRINTF("\n");
}
#endif /* NXPBUILD__PHAC_DISCLOOP_TYPEV_TAGS */
#ifdef NXPBUILD__PHAC_DISCLOOP_I18000P3M3_TAGS
if (PHAC_DISCLOOP_CHECK_ANDMASK(wTagsDetected, PHAC_DISCLOOP_POS_BIT_MASK_18000P3M3))
{
DEBUG_PRINTF("\tTechnology : ISO 18000p3m3 / EPC Gen2");
/* Loop through all the 18000p3m3 tags detected and print the UII */
for (bIndex = 0; bIndex < wNumberOfTags; bIndex++)
{
DEBUG_PRINTF("\n\t\tCard: %d",bIndex + 1);
DEBUG_PRINTF("\n\t\tUII :");
phApp_Print_Buff(
pDataParams->sI18000p3m3TargetInfo.aI18000p3m3[bIndex].aUii,
(pDataParams->sI18000p3m3TargetInfo.aI18000p3m3[bIndex].wUiiLength / 8));
}
DEBUG_PRINTF("\n");
}
#endif /* NXPBUILD__PHAC_DISCLOOP_I18000P3M3_TAGS */
}
/**
* This function will print Error information received from Reader Lib
* \param wStatus Error status
*/
void PrintErrorInfo(phStatus_t wStatus)
{
DEBUG_PRINTF("\n ErrorInfo Comp:");
switch(wStatus & 0xFF00)
{
case PH_COMP_BAL:
DEBUG_PRINTF("\t PH_COMP_BAL");
break;
case PH_COMP_HAL:
DEBUG_PRINTF("\t PH_COMP_HAL");
break;
case PH_COMP_PAL_ISO14443P3A:
DEBUG_PRINTF("\t PH_COMP_PAL_ISO14443P3A");
break;
case PH_COMP_PAL_ISO14443P3B:
DEBUG_PRINTF("\t PH_COMP_PAL_ISO14443P3B");
break;
case PH_COMP_PAL_ISO14443P4A:
DEBUG_PRINTF("\t PH_COMP_PAL_ISO14443P4A");
break;
case PH_COMP_PAL_ISO14443P4:
DEBUG_PRINTF("\t PH_COMP_PAL_ISO14443P4");
break;
case PH_COMP_PAL_FELICA:
DEBUG_PRINTF("\t PH_COMP_PAL_FELICA");
break;
case PH_COMP_PAL_EPCUID:
DEBUG_PRINTF("\t PH_COMP_PAL_EPCUID");
break;
case PH_COMP_PAL_SLI15693:
DEBUG_PRINTF("\t PH_COMP_PAL_SLI15693");
break;
case PH_COMP_PAL_I18000P3M3:
DEBUG_PRINTF("\t PH_COMP_PAL_I18000P3M3");
break;
case PH_COMP_PAL_I18092MPI:
DEBUG_PRINTF("\t PH_COMP_PAL_I18092MPI");
break;
case PH_COMP_PAL_I18092MT:
DEBUG_PRINTF("\t PH_COMP_PAL_I18092MT");
break;
case PH_COMP_PAL_I14443P4MC:
DEBUG_PRINTF("\t PH_COMP_PAL_I14443P4MC");
break;
case PH_COMP_AC_DISCLOOP:
DEBUG_PRINTF("\t PH_COMP_AC_DISCLOOP");
break;
case PH_COMP_OSAL:
DEBUG_PRINTF("\t PH_COMP_OSAL");
break;
default:
DEBUG_PRINTF("\t 0x%x",(wStatus & PH_COMPID_MASK));
break;
}
DEBUG_PRINTF("\t type:");
switch(wStatus & PH_ERR_MASK)
{
case PH_ERR_SUCCESS_INCOMPLETE_BYTE:
DEBUG_PRINTF("\t PH_ERR_SUCCESS_INCOMPLETE_BYTE");
break;
case PH_ERR_IO_TIMEOUT:
DEBUG_PRINTF("\t PH_ERR_IO_TIMEOUT");
break;
case PH_ERR_INTEGRITY_ERROR:
DEBUG_PRINTF("\t PH_ERR_INTEGRITY_ERROR");
break;
case PH_ERR_COLLISION_ERROR:
DEBUG_PRINTF("\t PH_ERR_COLLISION_ERROR");
break;
case PH_ERR_BUFFER_OVERFLOW:
DEBUG_PRINTF("\t PH_ERR_BUFFER_OVERFLOW");
break;
case PH_ERR_FRAMING_ERROR:
DEBUG_PRINTF("\t PH_ERR_FRAMING_ERROR");
break;
case PH_ERR_PROTOCOL_ERROR:
DEBUG_PRINTF("\t PH_ERR_PROTOCOL_ERROR");
break;
case PH_ERR_RF_ERROR:
DEBUG_PRINTF("\t PH_ERR_RF_ERROR");
break;
case PH_ERR_EXT_RF_ERROR:
DEBUG_PRINTF("\t PH_ERR_EXT_RF_ERROR");
break;
case PH_ERR_NOISE_ERROR:
DEBUG_PRINTF("\t PH_ERR_NOISE_ERROR");
break;
case PH_ERR_ABORTED:
DEBUG_PRINTF("\t PH_ERR_ABORTED");
break;
case PH_ERR_INTERNAL_ERROR:
DEBUG_PRINTF("\t PH_ERR_INTERNAL_ERROR");
break;
case PH_ERR_INVALID_DATA_PARAMS:
DEBUG_PRINTF("\t PH_ERR_INVALID_DATA_PARAMS");
break;
case PH_ERR_INVALID_PARAMETER:
DEBUG_PRINTF("\t PH_ERR_INVALID_PARAMETER");
break;
case PH_ERR_PARAMETER_OVERFLOW:
DEBUG_PRINTF("\t PH_ERR_PARAMETER_OVERFLOW");
break;
case PH_ERR_UNSUPPORTED_PARAMETER:
DEBUG_PRINTF("\t PH_ERR_UNSUPPORTED_PARAMETER");
break;
case PH_ERR_OSAL_ERROR:
DEBUG_PRINTF("\t PH_ERR_OSAL_ERROR");
break;
case PHAC_DISCLOOP_LPCD_NO_TECH_DETECTED:
DEBUG_PRINTF("\t PHAC_DISCLOOP_LPCD_NO_TECH_DETECTED");
break;
case PHAC_DISCLOOP_COLLISION_PENDING:
DEBUG_PRINTF("\t PHAC_DISCLOOP_COLLISION_PENDING");
break;
default:
DEBUG_PRINTF("\t 0x%x",(wStatus & PH_ERR_MASK));
break;
}
}
/******************************************************************************
** End Of File
******************************************************************************/

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@ -0,0 +1,438 @@
/*----------------------------------------------------------------------------*/
/* Copyright 2016-2020,2022 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may only */
/* be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that you */
/* have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*----------------------------------------------------------------------------*/
/** \file
* Example Source abstracting component data structure and code initialization and code specific to HW used in the examples
* This file shall be present in all examples. A customer does not need to touch/modify this file. This file
* purely depends on the phNxpBuild_Lpc.h or phNxpBuild_App.h
* The phAppInit.h externs the component data structures initialized here that is in turn included by the core examples.
* The core example shall not use any other variable defined here except the RdLib component data structures(as explained above)
* The RdLib component initialization requires some user defined data and function pointers.
* These are defined in the respective examples and externed here.
*
* Keystore and Crypto initialization needs to be handled by application.
*
* $Author$
* $Revision$ (v07.10.00)
* $Date$
*
*/
/* Status header */
#include <ph_Status.h>
#include "phApp_Init.h"
/* LLCP header */
#include <phlnLlcp.h>
#include <phOsal.h>
#ifdef PH_PLATFORM_HAS_ICFRONTEND
#include "BoardSelection.h"
#endif /* PH_PLATFORM_HAS_ICFRONTEND */
#ifdef PHDRIVER_KINETIS_K82
#include <fsl_port.h>
#include <fsl_pit.h>
#ifdef DEBUG
#include <fsl_clock.h>
#endif /* DEBUG */
#endif /* PHDRIVER_KINETIS_K82 */
#ifdef PHDRIVER_KINETIS_K82
#ifdef DEBUG
#define KINETIS_K82_DEBUG_UART_CLK_FREQ CLOCK_GetOsc0ErClkFreq()
#define KINETIS_K82_DEBUG_UART_BASEADDR (uint32_t)(LPUART4)
#define KINETIS_K82_DEBUG_UART_INSTANCE 4U
#define KINETIS_K82_DEBUG_UART_BAUDRATE 115200
#define KINETIS_K82_DEBUG_UART_TYPE DEBUG_CONSOLE_DEVICE_TYPE_LPUART
#endif /* DEBUG */
/*! @brief Clock configuration structure. */
typedef struct _clock_config
{
mcg_config_t mcgConfig; /*!< MCG configuration. */
sim_clock_config_t simConfig; /*!< SIM configuration. */
osc_config_t oscConfig; /*!< OSC configuration. */
uint32_t coreClock; /*!< core clock frequency. */
} clock_config_t;
#endif /* PHDRIVER_KINETIS_K82 */
#ifdef PH_OSAL_LINUX
# define PI_IRQ_POLLING_TASK_PRIO 0
# define PI_IRQ_POLLING_TASK_STACK 0x20000
phOsal_ThreadObj_t gphPiThreadObj;
#endif /* PH_OSAL_LINUX */
#if defined(PHDRIVER_LPC1769) && defined(__CC_ARM)
uint32_t SystemCoreClock;
#endif
/*******************************************************************************
** Function Declarations
*******************************************************************************/
#ifdef PHDRIVER_KINETIS_K82
static void phApp_K82_Init(void);
#endif /* PHDRIVER_KINETIS_K82 */
#ifdef PH_OSAL_LINUX
static void phExample_IrqPolling(void* param);
#endif /* PH_OSAL_LINUX */
phStatus_t phApp_Configure_IRQ();
/*******************************************************************************
** Clock configuration of K82 Platform
*******************************************************************************/
#ifdef PHDRIVER_KINETIS_K82
/* Configuration for enter RUN mode. Core clock = 50MHz. */
const clock_config_t g_defaultClockConfigRun = {
.mcgConfig =
{
.mcgMode = kMCG_ModePEE, /* Work in PEE mode. */
.irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enable. */
.ircs = kMCG_IrcSlow, /* Select IRC32k. */
.fcrdiv = 0U, /* FCRDIV is 0. */
.frdiv = 4U,
.drs = kMCG_DrsLow, /* Low frequency range. */
.dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25%. */
.oscsel = kMCG_OscselOsc, /* Select OSC. */
.pll0Config =
{
.enableMode = 0U, .prdiv = 0x01U, .vdiv = 0x01U,
},
},
.simConfig =
{
.pllFllSel = 1U, /* PLLFLLSEL select PLL. */
.pllFllDiv = 0U, /* PLLFLLSEL clock divider divisor. */
.pllFllFrac = 0U, /* PLLFLLSEL clock divider fraction. */
.er32kSrc = 5U, /* ERCLK32K selection, use RTC. */
.clkdiv1 = 0x01140000U, /* SIM_CLKDIV1. */
},
.oscConfig = {.freq = CPU_XTAL_CLK_HZ,
.capLoad = 0,
.workMode = kOSC_ModeOscLowPower,
.oscerConfig =
{
.enableMode = kOSC_ErClkEnable,
#if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER)
.erclkDiv = 0U,
#endif
}},
};
#endif /* PHDRIVER_KINETIS_K82 */
/*******************************************************************************
** Global Variable Declaration
*******************************************************************************/
#ifdef NXPBUILD__PHLN_LLCP_SW
phlnLlcp_Sw_DataParams_t slnLlcp; /* LLCP component */
#endif /* NXPBUILD__PHLN_LLCP_SW */
/* General information bytes to be sent with ATR Request */
#if defined(NXPBUILD__PHPAL_I18092MPI_SW) || defined(NXPBUILD__PHPAL_I18092MT_SW)
uint8_t aLLCPGeneralBytes[36] = { 0x46,0x66,0x6D,
0x01,0x01,0x10, /*VERSION*/
0x03,0x02,0x00,0x01, /*WKS*/
0x04,0x01,0xF1 /*LTO*/
};
uint8_t bLLCPGBLength = 13;
#endif
/* ATR Response or ATS Response holder */
#if defined(NXPBUILD__PHPAL_I14443P4A_SW) || \
defined(NXPBUILD__PHPAL_I18092MPI_SW)
uint8_t aResponseHolder[64];
#endif
/* prints if error is detected */
#define CHECK_SUCCESS(x) \
if ((x) != PH_ERR_SUCCESS) \
{ \
DEBUG_PRINTF("\nLine: %d Error - (0x%04X) has occurred : 0xCCEE CC-Component ID, EE-Error code. Refer-ph_Status.h\n ", __LINE__, (x)); \
return (x); \
}
/*******************************************************************************
** Function Definitions
*******************************************************************************/
#ifdef PHDRIVER_KINETIS_K82
static void phApp_K82_Init(void)
{
#ifdef DEBUG
uint32_t uartClkSrcFreq;
#endif /* DEBUG */
pit_config_t pitConfig; /* Structure of initialize PIT */
CLOCK_SetSimSafeDivs();
CLOCK_InitOsc0(&g_defaultClockConfigRun.oscConfig);
CLOCK_SetXtal0Freq(CPU_XTAL_CLK_HZ);
CLOCK_BootToPeeMode(g_defaultClockConfigRun.mcgConfig.oscsel, kMCG_PllClkSelPll0,
&g_defaultClockConfigRun.mcgConfig.pll0Config);
CLOCK_SetInternalRefClkConfig(g_defaultClockConfigRun.mcgConfig.irclkEnableMode,
g_defaultClockConfigRun.mcgConfig.ircs, g_defaultClockConfigRun.mcgConfig.fcrdiv);
CLOCK_SetSimConfig(&g_defaultClockConfigRun.simConfig);
SystemCoreClockUpdate();
/*
* pitConfig.enableRunInDebug = false;
*/
PIT_GetDefaultConfig(&pitConfig);
/* Init pit module */
PIT_Init(PIT, &pitConfig);
#ifdef DEBUG
/* Initialize LPUART4 pins below used to Print */
/* Ungate the port clock */
CLOCK_EnableClock(kCLOCK_PortC);
/* Affects PORTC_PCR14 register */
PORT_SetPinMux(PORTC, 14U, kPORT_MuxAlt3);
/* Affects PORTC_PCR15 register */
PORT_SetPinMux(PORTC, 15U, kPORT_MuxAlt3);
/* SIM_SOPT2[27:26]:
* 00: Clock Disabled
* 01: MCGFLLCLK, or MCGPLLCLK, or IRC48M
* 10: OSCERCLK
* 11: MCGIRCCLK
*/
CLOCK_SetLpuartClock(2);
uartClkSrcFreq = KINETIS_K82_DEBUG_UART_CLK_FREQ;
DbgConsole_Init(KINETIS_K82_DEBUG_UART_INSTANCE, KINETIS_K82_DEBUG_UART_BAUDRATE, KINETIS_K82_DEBUG_UART_TYPE, uartClkSrcFreq);
#endif /* DEBUG */
}
#endif /* PHDRIVER_KINETIS_K82 */
#ifdef PH_PLATFORM_HAS_ICFRONTEND
/**
* This function will initialize Host Controller interfaced with NXP Reader IC's.
* Any initialization which is not generic across Platforms, should be done here.
* Note: For NXP NFC Controllers HOST initialization is not required.
*/
void phApp_CPU_Init(void)
{
#if defined PHDRIVER_KINETIS_K82
phApp_K82_Init();
#elif defined(PHDRIVER_LPC1769) && defined(__CC_ARM)
SystemCoreClock = (( unsigned long ) 96000000);
#elif defined(PH_OSAL_LINUX) && defined(NXPBUILD__PHHAL_HW_PN5190)
phStatus_t status;
status = PiGpio_OpenIrq();
if ((status & PH_ERR_MASK) != PH_ERR_SUCCESS)
{
DEBUG_PRINTF("\n PiGpio_OpenIrq failed \n");
DEBUG_PRINTF("\n Couldn't open PN5190 Kernel IRQ Driver.\n Halting here!!FIX IT!!\n");
while(1);
}
#else
/* In case of LPC series, startup file takes care of initializing clock and ports.
* No initialization is required in Linux environment. */
#endif
}
#endif /* PH_PLATFORM_HAS_ICFRONTEND */
/**
* This function will initialize Reader LIbrary Component
*/
phStatus_t phApp_Comp_Init(void * pDiscLoopParams)
{
phStatus_t wStatus = PH_ERR_SUCCESS;
#if defined(NXPBUILD__PHPAL_I18092MPI_SW) || defined(NXPBUILD__PHPAL_I18092MT_SW) || \
defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_P2P_TAGS) || defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_P2P_ACTIVE) || \
defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_I3P4_TAGS) || defined(NXPBUILD__PHAC_DISCLOOP_TYPEF_P2P_TAGS) || \
defined(NXPBUILD__PHAC_DISCLOOP_TYPEF212_P2P_ACTIVE) || defined(NXPBUILD__PHAC_DISCLOOP_TYPEF424_P2P_ACTIVE)
phacDiscLoop_Sw_DataParams_t * pDiscLoop = (phacDiscLoop_Sw_DataParams_t *)pDiscLoopParams;
#endif
/* Initialize the LLCP component */
#ifdef NXPBUILD__PHLN_LLCP_SW
slnLlcp.sLocalLMParams.wMiu = 0x00; /* 128 bytes only */
slnLlcp.sLocalLMParams.wWks = 0x11; /* SNEP & LLCP */
slnLlcp.sLocalLMParams.bLto = 100; /* Maximum LTO */
slnLlcp.sLocalLMParams.bOpt = 0x02;
slnLlcp.sLocalLMParams.bAvailableTlv = PHLN_LLCP_TLV_MIUX_MASK | PHLN_LLCP_TLV_WKS_MASK |
PHLN_LLCP_TLV_LTO_MASK | PHLN_LLCP_TLV_OPT_MASK;
wStatus = phlnLlcp_Sw_Init(
&slnLlcp,
sizeof(phlnLlcp_Sw_DataParams_t),
aLLCPGeneralBytes,
&bLLCPGBLength);
#endif /* NXPBUILD__PHLN_LLCP_SW */
#ifdef NXPBUILD__PHAC_DISCLOOP_SW
#if defined(NXPBUILD__PHPAL_I18092MPI_SW) || defined(NXPBUILD__PHPAL_I18092MT_SW)
/* Assign the GI for Type A */
pDiscLoop->sTypeATargetInfo.sTypeA_P2P.pGi = (uint8_t *)aLLCPGeneralBytes;
pDiscLoop->sTypeATargetInfo.sTypeA_P2P.bGiLength = bLLCPGBLength;
/* Assign the GI for Type F */
pDiscLoop->sTypeFTargetInfo.sTypeF_P2P.pGi = (uint8_t *)aLLCPGeneralBytes;
pDiscLoop->sTypeFTargetInfo.sTypeF_P2P.bGiLength = bLLCPGBLength;
#endif
#if defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_P2P_TAGS) || defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_P2P_ACTIVE)
/* Assign ATR response for Type A */
pDiscLoop->sTypeATargetInfo.sTypeA_P2P.pAtrRes = aResponseHolder;
#endif
#if defined(NXPBUILD__PHAC_DISCLOOP_TYPEF_P2P_TAGS) || defined(NXPBUILD__PHAC_DISCLOOP_TYPEF212_P2P_ACTIVE) || \
defined(NXPBUILD__PHAC_DISCLOOP_TYPEF424_P2P_ACTIVE)
/* Assign ATR response for Type F */
pDiscLoop->sTypeFTargetInfo.sTypeF_P2P.pAtrRes = aResponseHolder;
#endif
#ifdef NXPBUILD__PHAC_DISCLOOP_TYPEA_I3P4_TAGS
/* Assign ATS buffer for Type A */
pDiscLoop->sTypeATargetInfo.sTypeA_I3P4.pAts = aResponseHolder;
#endif /* NXPBUILD__PHAC_DISCLOOP_TYPEA_I3P4_TAGS */
#endif /* NXPBUILD__PHAC_DISCLOOP_SW */
return wStatus;
}
phStatus_t phApp_Configure_IRQ()
{
#ifdef PH_OSAL_LINUX
phStatus_t wStatus;
#endif /* PH_OSAL_LINUX */
#ifdef PH_PLATFORM_HAS_ICFRONTEND
#if !(defined(PH_OSAL_LINUX) && defined(NXPBUILD__PHHAL_HW_PN5190))
phDriver_Pin_Config_t pinCfg;
pinCfg.bOutputLogic = PH_DRIVER_SET_LOW;
pinCfg.bPullSelect = PHDRIVER_PIN_IRQ_PULL_CFG;
pinCfg.eInterruptConfig = PIN_IRQ_TRIGGER_TYPE;
phDriver_PinConfig(PHDRIVER_PIN_IRQ, PH_DRIVER_PINFUNC_INTERRUPT, &pinCfg);
#endif
#ifdef PHDRIVER_LPC1769
NVIC_SetPriority(EINT_IRQn, EINT_PRIORITY);
/* Enable interrupt in the NVIC */
NVIC_ClearPendingIRQ(EINT_IRQn);
NVIC_EnableIRQ(EINT_IRQn);
#endif /* PHDRIVER_LPC1769 */
#ifdef PH_OSAL_LINUX
gphPiThreadObj.pTaskName = (uint8_t *) "IrqPolling";
gphPiThreadObj.pStackBuffer = NULL;
gphPiThreadObj.priority = PI_IRQ_POLLING_TASK_PRIO;
gphPiThreadObj.stackSizeInNum = PI_IRQ_POLLING_TASK_STACK;
PH_CHECK_SUCCESS_FCT(wStatus, phOsal_ThreadCreate(&gphPiThreadObj.ThreadHandle, &gphPiThreadObj,
&phExample_IrqPolling, NULL));
#endif /* PH_OSAL_LINUX */
#ifdef PHDRIVER_KINETIS_K82
NVIC_SetPriority(EINT_IRQn, EINT_PRIORITY);
NVIC_ClearPendingIRQ(EINT_IRQn);
EnableIRQ(EINT_IRQn);
#endif /* PHDRIVER_KINETIS_K82 */
#endif /* #ifdef PH_PLATFORM_HAS_ICFRONTEND */
return PH_ERR_SUCCESS;
}
#ifdef PH_OSAL_LINUX
/*
* \brief: The purpose of this Thread is to detect RF signal from an External Peer .
*/
static void phExample_IrqPolling(void* param)
{
uint8_t bgpioVal = 0;
uint8_t bhighOrLow = 0;
#if defined(NXPBUILD__PHHAL_HW_RC663) || defined(NXPBUILD__PHHAL_HW_PN5180)
if(PIN_IRQ_TRIGGER_TYPE == PH_DRIVER_INTERRUPT_RISINGEDGE)
{
bhighOrLow = 1;
}
while(PiGpio_read(PHDRIVER_PIN_IRQ, &bgpioVal) != PH_ERR_SUCCESS)
{
PiGpio_unexport(PHDRIVER_PIN_IRQ);
PiGpio_export(PHDRIVER_PIN_IRQ);
PiGpio_set_direction(PHDRIVER_PIN_IRQ, false);
if(PIN_IRQ_TRIGGER_TYPE == PH_DRIVER_INTERRUPT_RISINGEDGE)
{
PiGpio_set_edge(PHDRIVER_PIN_IRQ, true, false);
}
else
{
PiGpio_set_edge(PHDRIVER_PIN_IRQ, false, true);
}
}
/* Initial status: If pin is already Active, post an event. */
if(bgpioVal == bhighOrLow)
{
CLIF_IRQHandler();
}
#endif
while(1)
{
/* Block forever for Raising Edge in PHDRIVER_PIN_IRQ. */
#if defined(NXPBUILD__PHHAL_HW_RC663) || defined(NXPBUILD__PHHAL_HW_PN5180)
if(PiGpio_poll(PHDRIVER_PIN_IRQ, bhighOrLow, -1) == PH_ERR_SUCCESS)
#elif defined(NXPBUILD__PHHAL_HW_PN5190)
if(PiGpio_Irq() == PH_ERR_SUCCESS)
#endif
{
CLIF_IRQHandler();
}
else
{
PiGpio_unexport(PHDRIVER_PIN_IRQ);
PiGpio_export(PHDRIVER_PIN_IRQ);
PiGpio_set_direction(PHDRIVER_PIN_IRQ, false);
if(PIN_IRQ_TRIGGER_TYPE == PH_DRIVER_INTERRUPT_RISINGEDGE)
{
PiGpio_set_edge(PHDRIVER_PIN_IRQ, true, false);
}
else
{
PiGpio_set_edge(PHDRIVER_PIN_IRQ, false, true);
}
}
}
}
#endif /* PH_OSAL_LINUX */
/******************************************************************************
** End Of File
******************************************************************************/

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@ -0,0 +1,179 @@
/*----------------------------------------------------------------------------*/
/* Copyright 2020,2023 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may only */
/* be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that you */
/* have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*----------------------------------------------------------------------------*/
/** \file
* Example Source abstracting component data structure and code initialization and code specific to HW used in the examples
* This file shall be present in all examples. A customer does not need to touch/modify this file. This file
* purely depends on the phNxpBuild_Lpc.h or phNxpBuild_App.h
* The phAppInit.h externs the component data structures initialized here that is in turn included by the core examples.
* The core example shall not use any other variable defined here except the RdLib component data structures(as explained above)
* The RdLib component initialization requires some user defined data and function pointers.
* These are defined in the respective examples and externed here.
*
* Keystore and Crypto initialization needs to be handled by application.
*
* $Author$
* $Revision$ (v07.10.00)
* $Date$
*
*/
/* Status header */
#include <ph_Status.h>
#include "phApp_Init.h"
#ifdef NXPBUILD__PHHAL_HW_PN5180
#include "BoardSelection.h"
/* HAL specific headers */
#include <phhalHw_Pn5180_Instr.h>
/*******************************************************************************
** Function Declarations
*******************************************************************************/
/*******************************************************************************
** Global Variable Declaration
*******************************************************************************/
phbalReg_Type_t sBalParams;
phhalHw_Pn5180_DataParams_t * pHal;
#ifdef NXPBUILD__PHHAL_HW_TARGET
/* Parameters for L3 activation during Autocoll */
extern uint8_t sens_res[2] ;
extern uint8_t nfc_id1[3] ;
extern uint8_t sel_res ;
extern uint8_t nfc_id3 ;
extern uint8_t poll_res[18] ;
#endif /* NXPBUILD__PHHAL_HW_TARGET */
/*******************************************************************************
** Function Definitions
*******************************************************************************/
/**
* This function will initialize Hal Target Config
*/
phStatus_t phApp_HALConfigAutoColl(void)
{
#ifdef NXPBUILD__PHHAL_HW_TARGET
phStatus_t wStatus;
uint8_t baDynamicUidConfig[1U] = { 1U };
uint8_t baReadEepromConfig[24U] = { 0U };
/* Read Set Listen Parameters data from EEPROM */
wStatus = phhalHw_Pn5180_Instr_ReadE2Prom(
(phhalHw_Pn5180_DataParams_t *) pHal,
PHHAL_HW_PN5180_SET_LISTEN_E2PROM_ADDR,
baReadEepromConfig,
24U
);
CHECK_SUCCESS(wStatus);
/* Verify EEPROM data and configure Set Listen Parameters if EEPROM data is not correct. */
if ((memcmp(&baReadEepromConfig[0U], sens_res, 2U) != 0x00) ||
(memcmp(&baReadEepromConfig[2U], nfc_id1, 3U) != 0x00) ||
(memcmp(&baReadEepromConfig[5U], &sel_res, 1U) != 0x00) ||
(memcmp(&baReadEepromConfig[6U], poll_res, 18U) != 0x00))
{
/* Configure Set Listen Parameters. */
wStatus = phhalHw_Pn5180_SetListenParameters(
pHal,
&sens_res[0],
&nfc_id1[0],
sel_res,
&poll_res[0],
nfc_id3
);
CHECK_SUCCESS(wStatus);
}
if (pHal->wFirmwareVer < 0x308U)
{
/* With Pn5180 FW version < 3.8, only static UID is supported. */
baDynamicUidConfig[0] = 0x00;
}
/* Read Dynamic UID configuration from EEPROM */
wStatus = phhalHw_Pn5180_Instr_ReadE2Prom(
(phhalHw_Pn5180_DataParams_t *) pHal,
PHHAL_HW_PN5180_DYN_UID_CFG_E2PROM_ADDR,
baReadEepromConfig,
1U
);
CHECK_SUCCESS(wStatus);
/* Verify EEPROM data and perform Dynamic UID configuration if EEPROM data is not correct. */
if (memcmp(baReadEepromConfig, baDynamicUidConfig, 1U) != 0x00)
{
/* Configure Dynamic UID */
wStatus = phhalHw_Pn5180_Instr_WriteE2Prom(
(phhalHw_Pn5180_DataParams_t *) pHal,
PHHAL_HW_PN5180_DYN_UID_CFG_E2PROM_ADDR,
baDynamicUidConfig,
1U
);
CHECK_SUCCESS(wStatus);
}
#endif /* NXPBUILD__PHHAL_HW_TARGET */
return PH_ERR_SUCCESS;
}
/* Configure LPCD (for PN5180) */
phStatus_t phApp_ConfigureLPCD(void)
{
/**
* PHHAL_HW_CONFIG_SET_LPCD_WAKEUPTIME_MS 0x0070U //< Used value for wakeup counter in msecs, i.e. after this amount of time IC will wakes up from standby.
* PHHAL_HW_CONFIG_LPCD_MODE 0x0071U //< Used to set options PHHAL_HW_PN5180_LPCD_MODE_DEFAULT or PHHAL_HW_PN5180_LPCD_MODE_POWERDOWN_GUARDED
* PHHAL_HW_CONFIG_LPCD_REF 0x0072U //< Used to set or get LPCD Ref
*/
phStatus_t status = PH_ERR_SUCCESS;
uint16_t wConfig = PHHAL_HW_CONFIG_LPCD_REF;
uint16_t wValue;
uint8_t bLPCD_Threshold_EEPROMAddress = 0x37;
uint8_t bLPCD_Threshold = 0x10;
wValue = PHHAL_HW_PN5180_LPCD_MODE_POWERDOWN;
wConfig = PHHAL_HW_CONFIG_LPCD_MODE;
//status = phhalHw_Pn5180_Int_LPCD_GetConfig(pHal, wConfig, &wValue);
status = phhalHw_Pn5180_Instr_WriteE2Prom(pHal,bLPCD_Threshold_EEPROMAddress, &bLPCD_Threshold, 1 );
CHECK_SUCCESS(status);
status = phhalHw_Pn5180_Int_LPCD_SetConfig(
pHal,
wConfig,
wValue
);
return status;
}
void CLIF_IRQHandler(void)
{
/* Read the interrupt status of external interrupt attached to the reader IC IRQ pin */
if (phDriver_PinRead(PHDRIVER_PIN_IRQ, PH_DRIVER_PINFUNC_INTERRUPT))
{
phDriver_PinClearIntStatus(PHDRIVER_PIN_IRQ);
/* Call application registered callback. */
if (pHal->pRFISRCallback != NULL)
{
pHal->pRFISRCallback(pHal);
}
}
}
#endif /* NXPBUILD__PHHAL_HW_PN5180 */
/******************************************************************************
** End Of File
******************************************************************************/

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PROJECT(NfcrdlibEx6_LPCD)
FILE(GLOB NfcrdlibEx6_LPCD_Sources
*.c
src/*.c
)
include_directories(
intfs
types
)
ADD_EXECUTABLE(NfcrdlibEx6_LPCD
${NfcrdlibEx6_LPCD_Sources}
)
TARGET_LINK_LIBRARIES(
NfcrdlibEx6_LPCD
phOsal
DAL
NxpRdLib_acDiscLoop
NxpRdLib_halHw
NxpRdLib_KeyStore
NxpRdLib_phTools
NxpRdLib_palFelica
NxpRdLib_palI18092mPI
NxpRdLib_palI14443p4a
NxpRdLib_palI14443p4
NxpRdLib_palI14443p4
NxpRdLib_palMifare
NxpRdLib_alFelica
NxpRdLib_alMful
NxpRdLib_alMfdf
NxpRdLib_alT1T
NxpRdLib_alTop
NxpRdLib_alMfc
NxpRdLib_lnLlcp
NxpRdLib_phTools
NxpRdLib_palI18092mT
NxpRdLib_npSnep
NxpRdLib_palI14443p4mC
NxpRdLib_ceT4T
NxpRdLib_palEpcUid
NxpRdLib_alMfNtag42XDna
NxpRdLib_phNfcLib
)

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/*----------------------------------------------------------------------------*/
/* Copyright 2020-2021,2023 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may only */
/* be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that you */
/* have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*----------------------------------------------------------------------------*/
/** \file
* Example Source for NfcrdlibEx6_LPCD.
* This application will configure Reader Library to provide demo on LPCD functionality of NXP Reader IC's.
* Please refer Readme.txt file for Hardware Pin Configuration, Software Configuration and steps to build and
* execute the project which is present in the same project directory.
*
* $Author$
* $Revision$ (v07.10.00)
* $Date$
*/
/**
* Reader Library Headers
*/
#include <phApp_Init.h>
#ifdef NXPBUILD__PHHAL_HW_PN5190
#include <phhalHw_Pn5190_Instr.h>
#endif /* NXPBUILD__PHHAL_HW_PN5190 */
/* Local headers */
#include "NfcrdlibEx6_LPCD.h"
/*******************************************************************************
** Definitions
*******************************************************************************/
#ifdef NXPBUILD__PHHAL_HW_PN7640
# warning "This example is not supported for PN7640"
int main() {
DEBUG_PRINTF("This example is not supported for PN7640.");
while (1){
}
return 0;
}
/* Actual main defined below has no purpose in this example and hence over-riding it. */
# define main dummy_main
#endif /* NXPBUILD__PHHAL_HW_RC663 */
#ifdef PHOSAL_FREERTOS_STATIC_MEM_ALLOCATION
uint32_t aLPCDTaskBuffer[LPCD_TASK_STACK];
#else /* PHOSAL_FREERTOS_STATIC_MEM_ALLOCATION */
#define aLPCDTaskBuffer NULL
#endif /* PHOSAL_FREERTOS_STATIC_MEM_ALLOCATION */
#ifdef PH_OSAL_FREERTOS
const uint8_t bTaskName[configMAX_TASK_NAME_LEN] = {"LPCDTask"};
#else
const uint8_t bTaskName[] = {"LPCDTask"};
#endif /* PH_OSAL_FREERTOS */
/*******************************************************************************
** Static Defines
*******************************************************************************/
static volatile uint8_t bInfLoop = 1U;
/*******************************************************************************
** Prototypes
*******************************************************************************/
void LPCD_Demo(void * pHalParams);
/*******************************************************************************
** Code
*******************************************************************************/
int main (void)
{
do
{
phStatus_t wStatus = PH_ERR_INTERNAL_ERROR;
phNfcLib_Status_t dwStatus;
#ifdef PH_PLATFORM_HAS_ICFRONTEND
phNfcLib_AppContext_t AppContext = {0};
#endif /* PH_PLATFORM_HAS_ICFRONTEND */
#ifndef PH_OSAL_NULLOS
phOsal_ThreadObj_t LPCDTask;
#endif /* PH_OSAL_NULLOS */
/* Perform Controller specific initialization. */
phApp_CPU_Init();
/* Perform OSAL Initialization. */
(void)phOsal_Init();
DEBUG_PRINTF("\n LPCD Example: ");
#ifdef PH_PLATFORM_HAS_ICFRONTEND
wStatus = phbalReg_Init(&sBalParams, sizeof(phbalReg_Type_t));
CHECK_STATUS(wStatus);
AppContext.pBalDataparams = &sBalParams;
dwStatus = phNfcLib_SetContext(&AppContext);
CHECK_NFCLIB_STATUS(dwStatus);
#endif /* PH_PLATFORM_HAS_ICFRONTEND */
/* Initialize library */
dwStatus = phNfcLib_Init();
CHECK_NFCLIB_STATUS(dwStatus);
if(dwStatus != PH_NFCLIB_STATUS_SUCCESS) break;
/* Set the generic pointer */
pHal = phNfcLib_GetDataParams(PH_COMP_HAL);
/* Perform Platform Init */
wStatus = phApp_Configure_IRQ();
CHECK_STATUS(wStatus);
if(wStatus != PH_ERR_SUCCESS) break;
#ifndef PH_OSAL_NULLOS
LPCDTask.pTaskName = (uint8_t *)bTaskName;
LPCDTask.pStackBuffer = aLPCDTaskBuffer;
LPCDTask.priority = LPCD_TASK_PRIO;
LPCDTask.stackSizeInNum = LPCD_TASK_STACK;
phOsal_ThreadCreate(&LPCDTask.ThreadHandle, &LPCDTask, &LPCD_Demo, pHal);
phOsal_StartScheduler();
DEBUG_PRINTF("RTOS Error : Scheduler exited. \n");
#else
LPCD_Demo(pHal);
#endif /* PH_OSAL_NULLOS */
} while(0);
while(bInfLoop); /* Comes here if initialization failure or scheduler exit due to error */
return 0;
}
void LPCD_Demo(void * pHalParams)
{
phStatus_t wStatus;
uint32_t dwLPCDCalibrateOption;
uint32_t dwLPCDDemoOption;
uint32_t dwLPCDRefValue;
uint16_t wLPCDWakeUpTime = LPCD_POWERDOWN_TIME;
/* This call shall allocate secure context before calling any secure function,
* when FreeRtos trust zone is enabled.
* */
phOsal_ThreadSecureStack( 512 );
/* Perform LPCD Calibration */
wStatus = Configure_LPCD(&dwLPCDCalibrateOption, &dwLPCDDemoOption);
CHECK_STATUS(wStatus);
/* Perform LPCD Calibration */
wStatus = Calibrate_LPCD(dwLPCDDemoOption, &dwLPCDRefValue);
CHECK_STATUS(wStatus);
do
{
/* Perform LPCD Call */
wStatus = DemoLPCD(dwLPCDDemoOption, dwLPCDRefValue, wLPCDWakeUpTime);
CHECK_STATUS(wStatus);
if (dwLPCDCalibrateOption == 1U)
{
/* Perform LPCD Calibration */
wStatus = Calibrate_LPCD(dwLPCDDemoOption, &dwLPCDRefValue);
CHECK_STATUS(wStatus);
}
}while(bInfLoop);
}

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__________________________________________________
NXPNFCRDLIB EXAMPLE : NFCRDLIBEX6_LPCD
(V07.10.00)
__________________________________________________
Table of Contents
_________________
1 Document Purpose
2 Description of the NfcrdlibEx6_LPCD
3 Restrictions on NfcrdlibEx6_LPCD
4 Configurations of NfcrdlibEx6_LPCD
5 Package Contents
6 Mandatory materials (not included)
7 Hardware Configuration
8 Software Configuration
9 Steps to build NfcrdlibEx6_LPCD for LPC1769 with PN5190 using MCUXpresso
10 Steps to build NfcrdlibEx6_LPCD for LPC1769 with PN5180 using MCUXpresso
11 Steps to build NfcrdlibEx6_LPCD for LPC1769 with RC663 using MCUXpresso
12 Steps to build NfcrdlibEx6_LPCD for PN7462AU using MCUXpresso
13 Steps to build NfcrdlibEx6_LPCD for FRDM-K82F using MCUXpresso
14 Selection of Board / OSAL / Frontend (MCUXpresso)
15 Running NfcrdlibEx6_LPCD
16 List of supported NFC Reader Boards/ICs
17 Reference Documents
1 Document Purpose
==================
This document describes the steps to be followed to execute
NfcrdlibEx6_LPCD example as well as it's known problems and
restrictions.
2 Description of the NfcrdlibEx6_LPCD
=====================================
- NfcrdlibEx6_LPCD can be run with CLEV663B, PN5180, PN5190 and
PN7462AU. (See Section-16 for supported versions)
- This example performs the LPCD Demonstartion of all the different
LPCD Options available with different NXP Reader IC's.
- LPCD Calibration and LPCD Card Detection Loops are separated to
shown the LPCD Capabilities of different NXP Reader IC's.
3 Restrictions on NfcrdlibEx6_LPCD
==================================
- NfcrdlibEx6_LPCD is restricted to be run on NFC Reader Boards/ICs
mentioned in Section-16.
- The APIs are intended for NXP contact-less reader ICs only, as such
the APIs are not to be ported to any technology from any other
vendor.
- NXP will not support porting to any other vendor platform.
- This software project requires NxpNfcRdLib v07.10.00 or later.
- **IMPORTANT** The default used MCU Type is K82. When executing
example on LPC1769 or PN7462AU, the MCU Type has to be changed in
the MCUXpresso IDE.
- For switching to MCU Type to PN7462AU, see Section-12
- For switching to MCU Type to LPC1769, see Section-9, Section-10 and
Section-11.
4 Configurations of NfcrdlibEx6_LPCD
====================================
- The example application is written to demonstrate LPCD functionality
of all NXP Reader IC's.
5 Package Contents
==================
- Readme.txt
+ This readme file
- NfcrdlibEx6_LPCD.c
+ Main example file.
- intfs/NfcrdlibEx6_LPCD.h
+ Interfaces/Defines specific to the example
- intfs/ph_NxpBuild_App.h
+ Reader library build configuration file
- src/phApp_Helper.c
- src/NfcrdlibEx6_Pn5180_LPCD_Demo.c
- src/NfcrdlibEx6_Pn5190_LPCD_Demo.c
- src/NfcrdlibEx6_Pn7462AU_LPCD_Demo.c
- src/NfcrdlibEx6_Rc663_LPCD_Demo.c
- src/phApp_Init.c and intfs/phApp_Init.h
+ Common utility functions (common across all examples)
- mcux/.cproject and mcux/.project
+ MCUXpresso project configuration file
- cr_startup_lpc175x_6x.c
+ Startup required to compile example for LPC1769 Micro Controller.
6 Mandatory materials (not included)
====================================
- MCUXpresso IDE. It can be downloaded from
[http://www.nxp.com/products/:MCUXpresso-IDE]
- SDK for Freedom K82 Board
([http://www.nxp.com/products/:FRDM-K82F]). The pre-build SDK can
be downloaded from
[https://mcuxpresso.nxp.com/en/license?hash=9897a8c19a6bc569c3fade7141f0f405&hash_download=true&to_vault=true]
See MCUXpresso User Manual for steps needed to install an SDK.
- Plugin to extend MCUXpresso to support PN7462AU. (Required for
MCUXpresso versions before MCUXpressoIDE_10.0.2)
- LPCXpresso LPC1769 / Freedom K82 development boards For NFC ICs
listed in Section-16 (Note: PN7462AU (Section-16 Bullet-3) does not
need any other other microcontroller).
7 Hardware Configuration
========================
Before starting this application, HW Changes may be required for the
used board. Refer to the following User Manuals / Application notes
before starting with this example.
- AN11211: Quick Start Up Guide RC663 Blueboard
- AN11744: PN5180 Evaluation board quick start guide
- AN11802: NFC Reader Library for Linux Installation Guidelines
- AN12550: PNEV5190B Evaluation board quick start guide
8 Software Configuration
========================
- The Software can be compiled for Cortex M3 LPC1769 micro-controller,
Cortex M4 Freedom K82 and Cortex M0 based PN7462AU from NXP.
- Since this example can be configured to run on various MCU ICs and
various NFC ICs, appropriate changes are required as mentioned in
Section-9, Section-10, Section-11, Section-12 and Section-13.
9 Steps to build NfcrdlibEx6_LPCD for LPC1769 with PN5190 using MCUXpresso
==========================================================================
See "PNEV5190B Evaluation board quick start guide" in AN12550 (See
Section-17, Bullet-6 below)
10 Steps to build NfcrdlibEx6_LPCD for LPC1769 with PN5180 using MCUXpresso
===========================================================================
See "Importing provided SW example projects" in AN11908 (See
Section-17, Bullet-2 below)
11 Steps to build NfcrdlibEx6_LPCD for LPC1769 with RC663 using MCUXpresso
==========================================================================
See "Importing provided SW example projects" in AN11022 (See
Section-17, Bullet-3 below)
12 Steps to build NfcrdlibEx6_LPCD for PN7462AU using MCUXpresso
================================================================
- For MCUXpresso versions before MCUXpressoIDE_10.0.2, See "Adding
PN7462AU Plugin" in UM10883. (See Section-17, Bullet-4 below)
- See "Importing provided SW example projects" in UM10883.
13 Steps to build NfcrdlibEx6_LPCD for FRDM-K82F using MCUXpresso
=================================================================
See "Import projects to the MCUXpresso" in AN11908. (See Section-17,
Bullet-2 below)
14 Selection of Board / OSAL / Frontend (MCUXpresso)
====================================================
For MCUXpresso, the selection of Board / OSAL / Frontend has to be
done via -D (Preprocessor defines).
1) To select the board go to "Project Properties" --> "C/C++ Build"
--> "Settings" --> "Preprocessor" --> "Defined symbols (-D)", and
define the relevant PHDRIVER_<BoardNFCCombination>_BOARD macro.
e.g. For using K82 with Pn5190 use PHDRIVER_K82F_PNEV5190B_BOARD
and for LPC1769 with PN5190 use PHDRIVER_LPC1769PN5190_BOARD. For
list of supported boards refer to
Platform\DAL\cfg\BoardSelection.h.
2) To select the osal/os type, go to "Project Properties" --> "C/C++
Build" --> "Settings" --> "Preprocessor" --> "Defined symbols
(-D)".
e.g. For using FreeRTOS use PH_OSAL_FREERTOS. For other options
refer to RTOS\phOsal\inc\phOsal_Config.h.
15 Running NfcrdlibEx6_LPCD
===========================
The example application is written to demonstrate LPCD functionality
of NXP Reader IC's.
16 List of supported NFC Reader Boards/ICs
==========================================
1) CLEV6630B v2.0 Customer Evaluation Board
2) PNEV5180B v2.0 Customer Evaluation Board
3) PN7462AU v2.1 Customer Evaluation Board
4) PNEV5190B v1.0 Customer Evaluation Board
17 Reference Documents
======================
1) UM10954 : PN5180 SW Quick start guide
[http://www.nxp.com/docs/en/user-guide/UM10954.pdf]
2) AN11908 : NFC Reader Library for FRDM-K82F Board Installation
guidelines
[http://www.nxp.com/docs/en/application-note/AN11908.pdf]
3) AN11022 : CLRC663 Evaluation board quick start guide
[http://www.nxp.com/docs/en/application-note/AN11022.pdf]
4) UM10883 : PN7462AU Quick Start Guide - Development Kit
[http://www.nxp.com/docs/en/user-guide/UM10883.pdf]
5) AN11802 : NFC Reader Library for Linux Installation Guidelines
[http://www.nxp.com/docs/en/application-note/AN11802.pdf]
6) AN12550 : PNEV5190B Evaluation board quick start guide
----------------------------------------------------------------------
For updates of this example, see
[http://www.nxp.com/products/:NFC-READER-LIBRARY]

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/*----------------------------------------------------------------------------*/
/* Copyright 2021 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may only */
/* be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that you */
/* have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*----------------------------------------------------------------------------*/
/** \file
* Example Source header for NfcrdlibEx6_LPCD.
* This application will configure Reader Library to provide demo on LPCD functionality of NXP Reader IC's.
* Please refer Readme.txt file for Hardware Pin Configuration, Software Configuration and steps to build and
* execute the project which is present in the same project directory.
*
* $Author: NXP $
* $Revision: $ (v07.10.00)
* $Date: $
*/
#ifndef INTFS_NFCRDLIBEX6_LPCD_H_
#define INTFS_NFCRDLIBEX6_LPCD_H_
#include <ph_Status.h>
#define PRETTY_PRINTING /**< Enable pretty printing */
#define MiN_VALID_DATA_SIZE 6
#ifdef PH_OSAL_FREERTOS
#ifdef PHOSAL_FREERTOS_STATIC_MEM_ALLOCATION
#define LPCD_TASK_STACK (2200/4)
#else /* PHOSAL_FREERTOS_STATIC_MEM_ALLOCATION */
#if defined(__PN74XXXX__) || defined(__PN76XX__)
#define LPCD_TASK_STACK (2000/4)
#else /* __PN74XXXX__ || __PN76XX__ */
#define LPCD_TASK_STACK (2050)
#endif /* __PN74XXXX__*/
#endif /* PHOSAL_FREERTOS_STATIC_MEM_ALLOCATION*/
#define LPCD_TASK_PRIO 4
#endif /* PH_OSAL_FREERTOS */
#ifdef PH_OSAL_LINUX
#define LPCD_TASK_STACK 0x20000
#define LPCD_TASK_PRIO 0
#endif /* PH_OSAL_LINUX */
/*******************************************************************************
** Global Defines
*******************************************************************************/
/* User can use suitable PowerDown Time between successive Field ON cycle used for measurement and comparison with reference values */
#define LPCD_POWERDOWN_TIME 330U
/* User can use suitable Field ON time in micro seconds used for measurement of Load Change values.
* NOTE : This value is suitable for all NXP NFC Reader IC's and should not be reduced to a lesser value
* than the default value provided here, as this is leads to false LPCD detection cycles. */
#define LPCD_FIELD_ON_DURATION 102U
/*******************************************************************************
** Function Declarations
*******************************************************************************/
phStatus_t Configure_LPCD(uint32_t *pdwLPCDCalibrateOption, uint32_t *pdwLPCDDemoOption);
phStatus_t Calibrate_LPCD(uint32_t dwLPCDDemo, uint32_t *pdwLPCDRefValue);
phStatus_t DemoLPCD(uint32_t dwLPCDDemo, uint32_t dwLPCDRefValue, uint16_t wLPCDWakeUpTime);
#endif /* INTFS_NFCRDLIBEX6_LPCD_H_ */

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/*----------------------------------------------------------------------------*/
/* Copyright 2016-2023 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may only */
/* be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that you */
/* have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*----------------------------------------------------------------------------*/
/** \file
* Example Source abstracting component header specific to HW used in the examples
* This file shall be present in all examples. A customer does not need to touch/modify this file. This file
* purely depends on the phNxpBuild_Lpc.h or phNxpBuild_App.h
* The phAppInit.h externs the component data structures initialized here that is in turn included by the core examples.
* The core example shall not use any other variable defined here except the RdLib component data structures(as explained above)
* The RdLib component initialization requires some user defined data and function pointers.
* These are defined in the respective examples and externed here.
*
* Keystore and Crypto initialization needs to be handled by application.
*
* $Author$
* $Revision$ (v07.10.00)
* $Date$
*
*/
#ifndef PHAPP_INIT_H
#define PHAPP_INIT_H
/* Status header */
#include <ph_Status.h>
/* Driver Header */
#include <phDriver.h>
/* NFCLIB Header */
#include <phNfcLib.h>
/* LLCP header */
#include <phlnLlcp.h>
/* SNEP header */
#include <phnpSnep.h>
/* Check for K82 controller based boards. */
#if defined(PHDRIVER_FRDM_K82FPN5180_BOARD) || \
defined(PHDRIVER_FRDM_K82FRC663_BOARD) || \
defined(PHDRIVER_K82F_PNEV5190B_BOARD)
#define PHDRIVER_KINETIS_K82
#endif
/* Check for LPC1769 controller based boards. */
#if defined(PHDRIVER_LPC1769PN5180_BOARD) || \
defined(PHDRIVER_LPC1769RC663_BOARD) || \
defined(PHDRIVER_LPC1769PN5190_BOARD)
#define PHDRIVER_LPC1769
#endif
#if defined(PHDRIVER_PIPN5180_BOARD) || \
defined(PHDRIVER_PIRC663_BOARD) || \
defined(PHDRIVER_PIPN5190_BOARD)
#include <phDriver_Linux_Int.h>
#endif
#ifdef PHDRIVER_KINETIS_K82
# include <fsl_debug_console.h>
# include <stdio.h>
#endif
#if !defined(__PN76XX__)
#ifdef DEBUG
#ifdef PHDRIVER_KINETIS_K82
#if SDK_DEBUGCONSOLE==1
#define DEBUG_PRINTF DbgConsole_Printf
#define DEBUG_SCAN(...) DbgConsole_Scanf(__VA_ARGS__)
#else
#define DEBUG_PRINTF(...) printf(__VA_ARGS__);
#define DEBUG_SCAN(...) scanf(__VA_ARGS__);
#endif
#else /* PHDRIVER_KINETIS_K82 */
#include <stdio.h>
#define DEBUG_PRINTF(...) printf(__VA_ARGS__); fflush(stdout)
#define DEBUG_SCAN(...) scanf(__VA_ARGS__);while ((getchar()) != '\n');
#endif /* PHDRIVER_KINETIS_K82 */
#else /* DEBUG */
#define DEBUG_PRINTF(...)
#define DEBUG_SCAN(...)
#endif /* DEBUG */
#else /* __PN76XX__ */
#if (SEGGER_RTT_ENABLE == 1)
#include "SEGGER_RTT.h"
#define DEBUG_PRINTF(...) SEGGER_RTT_printf(0, __VA_ARGS__);
#define DEBUG_SCANF(Input , data) *data = (SEGGER_RTT_WaitKey() - 0x30); SEGGER_RTT_WaitKey()
#else
#if DEBUG
#include <fsl_debug_console.h>
#define DEBUG_PRINTF(...) PRINTF(__VA_ARGS__);
#define DEBUG_SCANF(...) SCANF(__VA_ARGS__);while ((GETCHAR()) != '\n');
#define DEBUG_GETCHAR GETCHAR
#else
#define DEBUG_PRINTF(...)
#define DEBUG_SCANF(...)
#endif /* DEBUG */
#endif /* (SEGGER_RTT_ENABLE == 1) */
#endif /* __PN76XX__ */
/*******************************************************************************
** Global Variable Declaration
*******************************************************************************/
#define PH_NFCRDLIB_EXAMPLE_LPCD_GUARDTIME 100 /* LPCD Guard time(T4) in milli-seconds configured by application for Rc663. */
#define PH_NFCRDLIB_EXAMPLE_LPCD_RFON_TIME 56 /* LPCD RFON time(T3) in micro-seconds configured by application for Rc663. */
/* HAL & BAL declarations */
#ifdef PH_PLATFORM_HAS_ICFRONTEND
extern phbalReg_Type_t sBalParams;
#endif /* PH_PLATFORM_HAS_ICFRONTEND */
#ifdef NXPBUILD__PHLN_LLCP_SW
extern phlnLlcp_Sw_DataParams_t slnLlcp; /* LLCP component */
#endif /* NXPBUILD__PHLN_LLCP_SW */
#ifdef NXPBUILD__PHHAL_HW_PN5180
extern phhalHw_Pn5180_DataParams_t * pHal;
#endif /* NXPBUILD__PHHAL_HW_PN5180 */
#ifdef NXPBUILD__PHHAL_HW_PN5190
extern phhalHw_Pn5190_DataParams_t * pHal;
#endif /* NXPBUILD__PHHAL_HW_PN5190 */
#ifdef NXPBUILD__PHHAL_HW_RC663
extern phhalHw_Rc663_DataParams_t * pHal;
#endif /* NXPBUILD__PHHAL_HW_RC663 */
#ifdef NXPBUILD__PHHAL_HW_PN7462AU
extern phhalHw_PN7462AU_DataParams_t * pHal;
#endif /* NXPBUILD__PHHAL_HW_PN7462AU */
#ifdef NXPBUILD__PHHAL_HW_PN76XX
extern phhalHw_Pn76xx_DataParams_t * pHal;
#endif /* NXPBUILD__PHHAL_HW_PN76XX */
/**************************************************Prints if error is detected**************************************************************/
/* Enable(1) / Disable(0) printing error/info */
#define DETECT_ERROR 0
#if DETECT_ERROR
#define DEBUG_ERROR_PRINT(x) x
#define PRINT_INFO(...) DEBUG_PRINTF(__VA_ARGS__)
#else
#define DEBUG_ERROR_PRINT(x)
#define PRINT_INFO(...)
#endif
#define CHECK_STATUS(x) \
if ((x) != PH_ERR_SUCCESS) \
{ \
DEBUG_PRINTF("Line: %d Error - (0x%04X) has occurred : 0xCCEE CC-Component ID, EE-Error code. Refer-ph_Status.h\n", __LINE__, (x)); \
}
/* prints if error is detected */
#define CHECK_SUCCESS(x) \
if ((x) != PH_ERR_SUCCESS) \
{ \
DEBUG_PRINTF("\nLine: %d Error - (0x%04X) has occurred : 0xCCEE CC-Component ID, EE-Error code. Refer-ph_Status.h\n ", __LINE__, (x)); \
return (x); \
}
/* prints if error is detected */
#define CHECK_NFCLIB_STATUS(x) \
if ((x) != PH_NFCLIB_STATUS_SUCCESS) \
{ \
DEBUG_PRINTF("\nLine: %d Error - (0x%04X) has occurred in NFCLIB\n ", __LINE__, (x)); \
}
/*********************************************************************************************************************************************/
/*******************************************************************************
** Function Declarations
*******************************************************************************/
extern void phApp_CPU_Init(void);
extern phStatus_t phApp_Comp_Init(void * pDiscLoopParams);
extern phStatus_t phApp_HALConfigAutoColl(void);
extern phStatus_t phApp_ConfigureLPCD(void);
extern void phApp_PrintTagInfo(phacDiscLoop_Sw_DataParams_t *pDataParams, uint16_t wNumberOfTags, uint16_t wTagsDetected);
extern void phApp_PrintTech(uint8_t TechType);
extern void phApp_Print_Buff(uint8_t *pBuff, uint8_t num);
extern void PrintErrorInfo(phStatus_t wStatus);
extern phStatus_t phApp_Configure_IRQ();
#ifdef PH_PLATFORM_HAS_ICFRONTEND
extern void CLIF_IRQHandler(void);
#endif /* PH_PLATFORM_HAS_ICFRONTEND */
#endif /* PHAPP_INIT_H */

View File

@ -0,0 +1,254 @@
/*----------------------------------------------------------------------------*/
/* Copyright 2016-2021,2023 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may only */
/* be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that you */
/* have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*----------------------------------------------------------------------------*/
/** \file
* Application specific selection of Reader Library Components
*
*
* $Author$
* $Revision$ (v07.10.00)
* $Date$
*/
#ifndef PH_NXPBUILD_APP_H_INC
#define PH_NXPBUILD_APP_H_INC
/** \defgroup ph_NxpBuild NXP Build
* \brief Controls the Inclusion of required components, Inclusion SRC/DATA within components and the Build Dependencies between the components
* @{
*/
/* NXPBUILD_DELETE: included code lines should be always removed from code */
/* NXP BUILD DEFINES */
/* use #define to include components */
/* comment out #define to exclude components */
/* DEBUG build mode */
/*#define NXPBUILD__PH_DEBUG*/ /**< DEBUG build definition */
#define NXPRDLIB_REM_GEN_INTFS
/*********************************************************************************************************************************************************************************/
#if defined(__PN74XXXX__) || defined (__PN73XXXX__)
#define NXPBUILD__PHHAL_HW_PN7462AU /**< NFC Controller PN7462AU HAL */
#endif
#ifdef __PN76XX__
#ifdef __PN7642__
#define NXPBUILD__PHHAL_HW_PN7642 /**< NFC Controller PN7642 HAL */
#elif __PN7640__
#define NXPBUILD__PHHAL_HW_PN7640 /**< NFC Controller PN7640 HAL */
#else
#error " PN76 platform definition (__PN7642__ or __PN7640__) missing !!! "
#endif
#if defined(__PN7642__) || defined(__PN7640__)
#define NXPBUILD__PHHAL_HW_PN76XX /**< NFC Controller PN76XX HAL */
#endif
#endif /* __PN76XX__ */
#if defined(PHDRIVER_LPC1769PN5180_BOARD) \
|| defined(PHDRIVER_FRDM_K82FPN5180_BOARD)
# define NXPBUILD__PHHAL_HW_PN5180
#endif
#if defined(PHDRIVER_LPC1769PN5190_BOARD) \
|| defined(PHDRIVER_K82F_PNEV5190B_BOARD)
# define NXPBUILD__PHHAL_HW_PN5190
#endif
#if defined(PHDRIVER_LPC1769RC663_BOARD) \
|| defined(PHDRIVER_FRDM_K82FRC663_BOARD)
# define NXPBUILD__PHHAL_HW_RC663
#endif
#if defined(NXPBUILD__PHHAL_HW_PN5180) || \
defined(NXPBUILD__PHHAL_HW_PN5190) || \
defined(NXPBUILD__PHHAL_HW_PN7462AU)
// #define NXPBUILD__PHHAL_HW_TARGET /**< Dependency checking if target mode macros should be enabled */
#endif
/*********************************************************************************************************************************************************************************/
#define NXPBUILD__PHPAL_I14443P3A_SW /**< PAL ISO 14443-3A SW Component is included. */
//#define NXPBUILD__PHPAL_I14443P3B_SW /**< PAL ISO 14443-3B SW Component is included. */
//#define NXPBUILD__PHPAL_I14443P4A_SW /**< PAL ISO 14443-4A SW Component is included. */
//#define NXPBUILD__PHPAL_I14443P4_SW /**< PAL ISO 14443-4 SW Component is included. */
//#define NXPBUILD__PHPAL_MIFARE_SW /**< PAL MIFARE SW Component is included */
//#define NXPBUILD__PHPAL_MIFARE_STUB /**< PAL MIFARE STUB Component is included */
//#define NXPBUILD__PHPAL_FELICA_SW /**< PAL Felica SW Component is included. */
// #define NXPBUILD__PHPAL_SLI15693_SW /**< PAL SLI 15693 Component is included. */
// #define NXPBUILD__PHPAL_I18000P3M3_SW /**< PAL ISO 18000p3m3 Component is included. */
#ifdef NXPBUILD__PHHAL_HW_RC663 /**< If FE HAL is RC663, then include EPC UID PAL as required, otherwise exclude. */
// #define NXPBUILD__PHPAL_EPCUID_SW /**< PAL EPC UID SW Component is included. */
#endif
//#define NXPBUILD__PHPAL_I18092MPI_SW /**< PAL ISO18092 (P2P) SW Component is included. */
#ifndef NXPBUILD__PHHAL_HW_RC663 /**< If FE HAL is RC663, then exclude ISO14443 Card Mode PAL & ISO18092 Target Mode PAL, otherwise include as required. */
// #define NXPBUILD__PHPAL_I14443P4MC_SW /**< PAL ISO 14443-4 Card Mode SW Component is included. */
// #define NXPBUILD__PHPAL_I18092MT_SW /**< PAL ISO 18092 Target Mode SW Component is included. */
#endif /* NXPBUILD__PHHAL_HW_RC663 */
/*********************************************************************************************************************************************************************************/
#define NXPBUILD__PHAC_DISCLOOP_SW /**< Discovery Loop Activity SW Component is included. */
#ifdef NXPBUILD__PHAC_DISCLOOP_SW /**< If DiscLoop SW Component is included, macros( & it's dependencies) to include/exclude SRC/DATA within Discloop is defined. */
#if defined (NXPBUILD__PHHAL_HW_PN5180) || \
defined (NXPBUILD__PHHAL_HW_PN5190) || \
defined (NXPBUILD__PHHAL_HW_RC663) || \
defined (NXPBUILD__PHHAL_HW_PN7462AU) || \
defined (NXPBUILD__PHHAL_HW_PN7642)
// #define NXPBUILD__PHAC_DISCLOOP_LPCD /**< SRC to enable LPCD is included. */
#endif
#ifdef NXPBUILD__PHPAL_I14443P3A_SW
#define NXPBUILD__PHAC_DISCLOOP_TYPEA_I3P3_TAGS /**< SRC/DATA to Detect/CollRes/Activate cards such as MFC, MFUL, MFP SL1 etc is included. */
// #define NXPBUILD__PHAC_DISCLOOP_TYPEA_JEWEL_TAGS /**< SRC/DATA to Detect cards such as NFC Forum T1T, Topaz/Jewel is included. */
#if defined(NXPBUILD__PHPAL_I14443P4A_SW) && defined(NXPBUILD__PHPAL_I14443P4_SW)
#define NXPBUILD__PHAC_DISCLOOP_TYPEA_I3P4_TAGS /**< SRC/DATA to Detect cards such as MFDF, MFP, T4AT NFC Forum Tag or Type A EMVCo is included. */
#endif
#endif /* NXPBUILD__PHPAL_I14443P3A_SW */
#if defined(NXPBUILD__PHPAL_I14443P3A_SW) && defined(NXPBUILD__PHPAL_I18092MPI_SW)
#define NXPBUILD__PHAC_DISCLOOP_TYPEA_P2P_TAGS /**< SRC/DATA to Detect Peer Passive Type A P2P Target mode devices is included. */
#endif
#ifndef NXPBUILD__PHHAL_HW_RC663
#ifdef NXPBUILD__PHPAL_I18092MPI_SW
#define NXPBUILD__PHAC_DISCLOOP_TYPEA_P2P_ACTIVE /**< SRC/DATA to Detect Peer Active Type A P2P Target mode devices is included. */
#define NXPBUILD__PHAC_DISCLOOP_TYPEF212_P2P_ACTIVE/**< SRC/DATA to Detect Peer Active Type F212 P2P Target mode devices is included. */
#define NXPBUILD__PHAC_DISCLOOP_TYPEF424_P2P_ACTIVE/**< SRC/DATA to Detect Peer Active Type F424 P2P Target mode devices is included. */
#endif /* NXPBUILD__PHPAL_I18092MPI_SW */
#endif /* NXPBUILD__PHHAL_HW_RC663 */
#ifdef NXPBUILD__PHPAL_FELICA_SW
#define NXPBUILD__PHAC_DISCLOOP_FELICA_TAGS /**< SRC/DATA to Detect FeliCa Cards is included. */
#ifdef NXPBUILD__PHPAL_I18092MPI_SW
#define NXPBUILD__PHAC_DISCLOOP_TYPEF_P2P_TAGS /**< SRC/DATA to Detect Peer Passive Type F P2P Target mode devices is included. */
#endif /* NXPBUILD__PHPAL_I18092MPI_SW */
#endif /* NXPBUILD__PHPAL_FELICA_SW */
#ifdef NXPBUILD__PHPAL_I14443P3B_SW
#define NXPBUILD__PHAC_DISCLOOP_TYPEB_I3P3B_TAGS /**< SRC/DATA to Detect Type B Cards that operate at Layer3 level is included */
#ifdef NXPBUILD__PHPAL_I14443P4_SW
#define NXPBUILD__PHAC_DISCLOOP_TYPEB_I3P4B_TAGS /**< SRC/DATA to Detect Type B Cards such as NFC Forum Type 4 Tags, EMVCo Type B Cards etc is included */
#endif /* NXPBUILD__PHPAL_I14443P4_SW */
#endif /* NXPBUILD__PHPAL_I14443P3B_SW */
#ifdef NXPBUILD__PHPAL_SLI15693_SW
#define NXPBUILD__PHAC_DISCLOOP_TYPEV_TAGS /**< SRC/DATA to Detect Type V Cards such as ICODE SLI/SLIX/SLI2/Tesa Cards is included*/
#endif /* NXPBUILD__PHPAL_SLI15693_SW */
#ifdef NXPBUILD__PHPAL_I18000P3M3_SW
#define NXPBUILD__PHAC_DISCLOOP_I18000P3M3_TAGS /**< SRC/DATA to Detect ICODE ILT Cards such as SMARTRAC StackIt Cards is included*/
#endif /* NXPBUILD__PHPAL_I18000P3M3_SW */
#ifndef NXPBUILD__PHHAL_HW_RC663 /**< If FE HAL is RC663, target mode is not supported at all, hence exclude those SRC, otherwise include as required */
#ifdef NXPBUILD__PHHAL_HW_TARGET
#define NXPBUILD__PHAC_DISCLOOP_TYPEA_TARGET_PASSIVE /**< SRC to Initialize Type A passive listen config and subsequently call HAL AutoColl is included. */
#ifndef NXPBUILD__PHHAL_HW_PN76XX
#define NXPBUILD__PHAC_DISCLOOP_TYPEA_TARGET_ACTIVE /**< SRC to Initialize Type A active listen config and subsequently call HAL AutoColl is included. */
#define NXPBUILD__PHAC_DISCLOOP_TYPEF212_TARGET_PASSIVE/**< SRC to Initialize Type F212 passive listen config and subsequently call HAL AutoColl is included. */
#define NXPBUILD__PHAC_DISCLOOP_TYPEF212_TARGET_ACTIVE /**< SRC to Initialize Type F212 active listen config and subsequently call HAL AutoColl is included. */
#define NXPBUILD__PHAC_DISCLOOP_TYPEF424_TARGET_PASSIVE/**< SRC to Initialize Type F424 passive listen config and subsequently call HAL AutoColl is included. */
#define NXPBUILD__PHAC_DISCLOOP_TYPEF424_TARGET_ACTIVE /**< SRC to Initialize Type F424 active listen config and subsequently call HAL AutoColl is included. */
#endif /* NXPBUILD__PHHAL_HW_PN76XX */
#endif /* NXPBUILD__PHHAL_HW_TARGET */
#endif
#endif /* NXPBUILD__PHAC_DISCLOOP_SW */
/*********************************************************************************************************************************************************************************/
#define NXPBUILD__PHNFCLIB /**< Simplified API Interface, If enabling this the entry point should be this component in the application */
/*********************************************************************************************************************************************************************************/
//#define NXPBUILD__PH_CIDMANAGER_SW /**< CID Manager SW Component is included. */
//#define NXPBUILD__PH_KEYSTORE_SW /**< SW KeyStore Component is included. */
#if defined(NXPBUILD__PHHAL_HW_RC663) && !defined(NXPBUILD__PH_KEYSTORE_SW)
// #define NXPBUILD__PH_KEYSTORE_RC663 /**< RC663 KeyStore Component is included. */
#endif
//#define NXPBUILD__PH_NDA_MFDF /**< MIFARE DESFire contactless IC */
//#define NXPBUILD__PH_CRYPTOSYM_SW /**< Crypto Symbols SW Component is included. */
//#define NXPBUILD__PH_CRYPTORNG_SW /**< Crypto RNG SW Component is included. */
/*********************************************************************************************************************************************************************************/
#ifdef NXPBUILD__PHPAL_FELICA_SW
#define NXPBUILD__PHAL_FELICA_SW /**< AL FeliCa SW Component is included */
#endif /* NXPBUILD__PHPAL_FELICA_SW */
#ifdef NXPBUILD__PHPAL_MIFARE_SW
#if defined(NXPBUILD__PH_KEYSTORE_SW) || defined(NXPBUILD__PH_KEYSTORE_RC663)
#define NXPBUILD__PHAL_MFC_SW /**< AL MIFARE Classic contactless IC SW Component is included */
#endif
#define NXPBUILD__PHAL_MFUL_SW /**< AL Mifare Ultrlight SW Component is included */
#define NXPBUILD__PHAL_MFDF_SW /**< AL Mifare DesFire SW Component is included */
// #define NXPBUILD__PHAL_MFNTAG42XDNA_SW /**< AL MIFARE Prime Ntag42XDna contactless IC SW Component is included */
#endif /* NXPBUILD__PHPAL_MIFARE_SW */
//#define NXPBUILD__PHAL_T1T_SW /**< AL Type T1 Tag SW Component is included */
#ifdef NXPBUILD__PHPAL_SLI15693_SW
#define NXPBUILD__PHAL_ICODE_SW /**< AL ICODE SW COMPONENT is included */
#endif /* NXPBUILD__PHPAL_SLI15693_SW */
//#define NXPBUILD__PHAL_TOP_SW /**< AL for TagOps Mapping SW Component is included.Required for NDEF operations */
#ifdef NXPBUILD__PHPAL_I18000P3M3_SW
#define NXPBUILD__PHAL_I18000P3M3_SW /**< AL ISO18000p3m3 SW Component is included */
#endif /* NXPBUILD__PHPAL_I18000P3M3_SW */
#ifdef NXPBUILD__PHPAL_I14443P4MC_SW
#if !defined(PH_OSAL_NULLOS)
#define NXPBUILD__PHCE_T4T_SW /**< AL HCE T2AT SW Component is included */
//#define NXPBUILD__PHCE_T4T_PROPRIETARY /**< SRC to handle HCE T4AT Proprietary Commands is included */
/*#define NXPBUILD__PHCE_T4T_EXT_NDEF */ /**< SRC to handle Extended NDEF Support as per T4T spec 3.0 is included */
#endif
#endif /* NXPBUILD__PHPAL_I14443P4MC_SW */
/* LLCP Components */
#if defined(NXPBUILD__PHPAL_I18092MPI_SW) || defined(NXPBUILD__PHPAL_I18092MT_SW)
#if !defined(PH_OSAL_NULLOS)
#define NXPBUILD__PHLN_LLCP_SW /**< Link LLCP SW Component is included */
#endif
#endif
/* SNEP components */
#ifdef NXPBUILD__PHLN_LLCP_SW
#define NXPBUILD__PHNP_SNEP_SW /**< Protocol SNEP SW Component is included */
#endif /* NXPBUILD__PHLN_LLCP_SW */
/* Enable/disable Debugging */
/*#define NXPBUILD__PH_DEBUG*/ /**< TODO: To be checked if required */
/** @}
* end of ph_NxpBuild
*/
#endif /* PH_NXPBUILD_APP_H_INC */

View File

@ -0,0 +1,352 @@
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<projectDescription>
<name>NfcrdlibEx6_LPCD_mcux</name>
<comment></comment>
<projects>
<project>FreeRTOS</project>
<project>lpc_board_nxp_lpcxpresso_1769</project>
<project>lpc_chip_175x_6x</project>
<project>NxpNfcRdLib</project>
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View File

@ -0,0 +1,493 @@
//*****************************************************************************
// LPC175x_6x Microcontroller Startup code for use with LPCXpresso IDE
//
// Version : 140114
//*****************************************************************************
//
// Copyright(C) NXP Semiconductors, 2014
// All rights reserved.
//
// Software that is described herein is for illustrative purposes only
// which provides customers with programming information regarding the
// LPC products. This software is supplied "AS IS" without any warranties of
// any kind, and NXP Semiconductors and its licensor disclaim any and
// all warranties, express or implied, including all implied warranties of
// merchantability, fitness for a particular purpose and non-infringement of
// intellectual property rights. NXP Semiconductors assumes no responsibility
// or liability for the use of the software, conveys no license or rights under any
// patent, copyright, mask work right, or any other intellectual property rights in
// or to any products. NXP Semiconductors reserves the right to make changes
// in the software without notification. NXP Semiconductors also makes no
// representation or warranty that such application will be suitable for the
// specified use without further testing or modification.
//
// Permission to use, copy, modify, and distribute this software and its
// documentation is hereby granted, under NXP Semiconductors' and its
// licensor's relevant copyrights in the software, without fee, provided that it
// is used in conjunction with NXP Semiconductors microcontrollers. This
// copyright, permission, and disclaimer notice must appear in all copies of
// this code.
//*****************************************************************************
#include <ph_Status.h>
#include <cr_section_macros.h>
#include <NXP/crp.h>
#ifdef DEBUG
# define VT_IMAGE_LENGTH 0x76706b64U
#else /* DEBUG */
# define VT_IMAGE_LENGTH 0xFFFFFFFFU
#endif /* DEBUG */
#if defined (__cplusplus)
#ifdef __REDLIB__
#error Redlib does not support C++
#else
//*****************************************************************************
//
// The entry point for the C++ library startup
//
//*****************************************************************************
extern "C" {
extern void __libc_init_array(void);
}
#endif
#endif
#define WEAK __attribute__ ((weak))
#define ALIAS(f) __attribute__ ((weak, alias (#f)))
__CRP const unsigned int CRP_WORD = CRP_NO_CRP;
//*****************************************************************************
#if defined (__cplusplus)
extern "C" {
#endif
//*****************************************************************************
#if defined (__USE_CMSIS) || defined (__USE_LPCOPEN)
// Declaration of external SystemInit function
void SystemInit(void);
extern void Board_SystemInit(void);
extern void Chip_SystemInit(void);
extern void SystemCoreClockUpdate(void);
#endif
//*****************************************************************************
//
// Forward declaration of the default handlers. These are aliased.
// When the application defines a handler (with the same name), this will
// automatically take precedence over these weak definitions
//
//*****************************************************************************
void ResetISR(void);
WEAK void NMI_Handler(void);
//WEAK void HardFault_Handler(void);
WEAK void MemManage_Handler(void);
WEAK void BusFault_Handler(void);
WEAK void UsageFault_Handler(void);
WEAK void SVC_Handler(void);
WEAK void DebugMon_Handler(void);
WEAK void PendSV_Handler(void);
WEAK void SysTick_Handler(void);
WEAK void IntDefaultHandler(void);
/* The prototype shows it is a naked function - in effect this is just an
assembly function. */
void HardFault_Handler( void ) __attribute__( ( naked ) );
//*****************************************************************************
//
// Forward declaration of the specific IRQ handlers. These are aliased
// to the IntDefaultHandler, which is a 'forever' loop. When the application
// defines a handler (with the same name), this will automatically take
// precedence over these weak definitions
//
//*****************************************************************************
void WDT_IRQHandler(void) ALIAS(IntDefaultHandler);
void TIMER0_IRQHandler(void) ALIAS(IntDefaultHandler);
void TIMER1_IRQHandler(void) ALIAS(IntDefaultHandler);
void TIMER2_IRQHandler(void) ALIAS(IntDefaultHandler);
void TIMER3_IRQHandler(void) ALIAS(IntDefaultHandler);
void UART0_IRQHandler(void) ALIAS(IntDefaultHandler);
void UART1_IRQHandler(void) ALIAS(IntDefaultHandler);
void UART2_IRQHandler(void) ALIAS(IntDefaultHandler);
void UART3_IRQHandler(void) ALIAS(IntDefaultHandler);
void PWM1_IRQHandler(void) ALIAS(IntDefaultHandler);
void I2C0_IRQHandler(void) ALIAS(IntDefaultHandler);
void I2C1_IRQHandler(void) ALIAS(IntDefaultHandler);
void I2C2_IRQHandler(void) ALIAS(IntDefaultHandler);
void SPI_IRQHandler(void) ALIAS(IntDefaultHandler);
void SSP0_IRQHandler(void) ALIAS(IntDefaultHandler);
void SSP1_IRQHandler(void) ALIAS(IntDefaultHandler);
void PLL0_IRQHandler(void) ALIAS(IntDefaultHandler);
void RTC_IRQHandler(void) ALIAS(IntDefaultHandler);
void EINT0_IRQHandler(void) ALIAS(IntDefaultHandler);
void EINT1_IRQHandler(void) ALIAS(IntDefaultHandler);
void EINT2_IRQHandler(void) ALIAS(IntDefaultHandler);
void CLIF_IRQHandler(void) ALIAS(IntDefaultHandler);
void ADC_IRQHandler(void) ALIAS(IntDefaultHandler);
void BOD_IRQHandler(void) ALIAS(IntDefaultHandler);
void USB_IRQHandler(void) ALIAS(IntDefaultHandler);
void CAN_IRQHandler(void) ALIAS(IntDefaultHandler);
void DMA_IRQHandler(void) ALIAS(IntDefaultHandler);
void I2S_IRQHandler(void) ALIAS(IntDefaultHandler);
#if defined (__USE_LPCOPEN)
void ETH_IRQHandler(void) ALIAS(IntDefaultHandler);
#else
void ENET_IRQHandler(void) ALIAS(IntDefaultHandler);
#endif
void RIT_IRQHandler(void) ALIAS(IntDefaultHandler);
void MCPWM_IRQHandler(void) ALIAS(IntDefaultHandler);
void QEI_IRQHandler(void) ALIAS(IntDefaultHandler);
void PLL1_IRQHandler(void) ALIAS(IntDefaultHandler);
void USBActivity_IRQHandler(void) ALIAS(IntDefaultHandler);
void CANActivity_IRQHandler(void) ALIAS(IntDefaultHandler);
void UART4_IRQHandler(void) ALIAS(IntDefaultHandler);
void SSP2_IRQHandler(void) ALIAS(IntDefaultHandler);
void LCD_IRQHandler(void) ALIAS(IntDefaultHandler);
void GPIO_IRQHandler(void) ALIAS(IntDefaultHandler);
void PWM0_IRQHandler(void) ALIAS(IntDefaultHandler);
void EEPROM_IRQHandler(void) ALIAS(IntDefaultHandler);
//*****************************************************************************
//
// The entry point for the application.
// __main() is the entry point for Redlib based applications
// main() is the entry point for Newlib based applications
//
//*****************************************************************************
#if defined (__REDLIB__)
extern void __main(void);
#endif
extern int main(void);
//*****************************************************************************
//
// External declaration for the pointer to the stack top from the Linker Script
//
//*****************************************************************************
extern void _vStackTop(void);
//*****************************************************************************
#if defined (__cplusplus)
} // extern "C"
#endif
//*****************************************************************************
//
// The vector table.
// This relies on the linker script to place at correct location in memory.
//
//*****************************************************************************
extern void (* const g_pfnVectors[])(void);
__attribute__ ((section(".isr_vector")))
void (* const g_pfnVectors[])(void) = {
// Core Level - CM3
&_vStackTop, // The initial stack pointer
ResetISR, // The reset handler
NMI_Handler, // The NMI handler
HardFault_Handler, // The hard fault handler
MemManage_Handler, // The MPU fault handler
BusFault_Handler, // The bus fault handler
UsageFault_Handler, // The usage fault handler
0, // Reserved
0, // Reserved
0, // Reserved
0, // Reserved
SVC_Handler, // SVCall handler
DebugMon_Handler, // Debug monitor handler
0, // Reserved
PendSV_Handler, // The PendSV handler
SysTick_Handler, // The SysTick handler
// Chip Level - LPC17
WDT_IRQHandler, // 16, 0x40 - WDT
TIMER0_IRQHandler, // 17, 0x44 - TIMER0
TIMER1_IRQHandler, // 18, 0x48 - TIMER1
TIMER2_IRQHandler, // 19, 0x4c - TIMER2
TIMER3_IRQHandler, // 20, 0x50 - TIMER3
UART0_IRQHandler, // 21, 0x54 - UART0
UART1_IRQHandler, // 22, 0x58 - UART1
UART2_IRQHandler, // 23, 0x5c - UART2
UART3_IRQHandler, // 24, 0x60 - UART3
PWM1_IRQHandler, // 25, 0x64 - PWM1
I2C0_IRQHandler, // 26, 0x68 - I2C0
I2C1_IRQHandler, // 27, 0x6c - I2C1
I2C2_IRQHandler, // 28, 0x70 - I2C2
SPI_IRQHandler, // 29, 0x74 - SPI
SSP0_IRQHandler, // 30, 0x78 - SSP0
SSP1_IRQHandler, // 31, 0x7c - SSP1
PLL0_IRQHandler, // 32, 0x80 - PLL0 (Main PLL)
RTC_IRQHandler, // 33, 0x84 - RTC
EINT0_IRQHandler, // 34, 0x88 - EINT0
EINT1_IRQHandler, // 35, 0x8c - EINT1
EINT2_IRQHandler, // 36, 0x90 - EINT2
CLIF_IRQHandler, // 37, 0x94 - EINT3 (Used for CLIF IRQ)
ADC_IRQHandler, // 38, 0x98 - ADC
BOD_IRQHandler, // 39, 0x9c - BOD
USB_IRQHandler, // 40, 0xA0 - USB
CAN_IRQHandler, // 41, 0xa4 - CAN
DMA_IRQHandler, // 42, 0xa8 - GP DMA
I2S_IRQHandler, // 43, 0xac - I2S
#if defined (__USE_LPCOPEN)
ETH_IRQHandler, // 44, 0xb0 - Ethernet
#else
ENET_IRQHandler, // 44, 0xb0 - Ethernet
#endif
RIT_IRQHandler, // 45, 0xb4 - RITINT
MCPWM_IRQHandler, // 46, 0xb8 - Motor Control PWM
QEI_IRQHandler, // 47, 0xbc - Quadrature Encoder
PLL1_IRQHandler, // 48, 0xc0 - PLL1 (USB PLL)
USBActivity_IRQHandler, // 49, 0xc4 - USB Activity interrupt to wakeup
CANActivity_IRQHandler, // 50, 0xc8 - CAN Activity interrupt to wakeup
UART4_IRQHandler, //; 51 UART4
SSP2_IRQHandler, //; 52 SSP2
LCD_IRQHandler, //; 53 LCD
GPIO_IRQHandler, //; 54 GPIO
PWM0_IRQHandler , //; 55 PWM0
EEPROM_IRQHandler, //; 56 EEPROM
(void *)VT_IMAGE_LENGTH, //; 57 VT Checksum for CRC Check of Vector Table.
};
//*****************************************************************************
// Functions to carry out the initialization of RW and BSS data sections. These
// are written as separate functions rather than being inlined within the
// ResetISR() function in order to cope with MCUs with multiple banks of
// memory.
//*****************************************************************************
__attribute__ ((section(".after_vectors")))
void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
unsigned int *pulDest = (unsigned int*) start;
unsigned int *pulSrc = (unsigned int*) romstart;
unsigned int loop;
for (loop = 0; loop < len; loop = loop + 4)
*pulDest++ = *pulSrc++;
}
__attribute__ ((section(".after_vectors")))
void bss_init(unsigned int start, unsigned int len) {
unsigned int *pulDest = (unsigned int*) start;
unsigned int loop;
for (loop = 0; loop < len; loop = loop + 4)
*pulDest++ = 0;
}
//*****************************************************************************
// The following symbols are constructs generated by the linker, indicating
// the location of various points in the "Global Section Table". This table is
// created by the linker via the Code Red managed linker script mechanism. It
// contains the load address, execution address and length of each RW data
// section and the execution and length of each BSS (zero initialized) section.
//*****************************************************************************
extern unsigned int __data_section_table;
extern unsigned int __data_section_table_end;
extern unsigned int __bss_section_table;
extern unsigned int __bss_section_table_end;
//*****************************************************************************
// Reset entry point for your code.
// Sets up a simple runtime environment and initializes the C/C++
// library.
//*****************************************************************************
__attribute__ ((section(".after_vectors")))
void
ResetISR(void) {
//
// Copy the data sections from flash to SRAM.
//
unsigned int LoadAddr, ExeAddr, SectionLen;
unsigned int *SectionTableAddr;
// Load base address of Global Section Table
SectionTableAddr = &__data_section_table;
// Copy the data sections from flash to SRAM.
while (SectionTableAddr < &__data_section_table_end) {
LoadAddr = *SectionTableAddr++;
ExeAddr = *SectionTableAddr++;
SectionLen = *SectionTableAddr++;
data_init(LoadAddr, ExeAddr, SectionLen);
}
// At this point, SectionTableAddr = &__bss_section_table;
// Zero fill the bss segment
while (SectionTableAddr < &__bss_section_table_end) {
ExeAddr = *SectionTableAddr++;
SectionLen = *SectionTableAddr++;
bss_init(ExeAddr, SectionLen);
}
#if defined (__USE_CMSIS) || defined (__USE_LPCOPEN)
SystemInit();
#endif
#if defined (__cplusplus)
//
// Call C++ library initialisation
//
__libc_init_array();
#endif
#if defined (__REDLIB__)
// Call the Redlib library, which in turn calls main()
__main() ;
#else
main();
#endif
//
// main() shouldn't return, but if it does, we'll just enter an infinite loop
//
while (1) {
;
}
}
/* Set up and initialize hardware prior to call to main */
void SystemInit(void)
{
unsigned int *pSCB_VTOR = (unsigned int *) 0xE000ED08;
#if defined(__IAR_SYSTEMS_ICC__)
extern void *__vector_table;
*pSCB_VTOR = (unsigned int) &__vector_table;
#elif defined(__CODE_RED)
*pSCB_VTOR = (unsigned int) &g_pfnVectors;
#elif defined(__ARMCC_VERSION)
extern void *__Vectors;
*pSCB_VTOR = (unsigned int) &__Vectors;
#endif
#if defined(__FPU_PRESENT) && __FPU_PRESENT == 1
fpuInit();
#endif
#if defined(NO_BOARD_LIB)
/* Chip specific SystemInit */
Chip_SystemInit();
#else
/* Setup system clocking and muxing */
Board_SystemInit();
#endif
/* Update system core clock rate. */
SystemCoreClockUpdate();
}
//*****************************************************************************
// Default exception handlers. Override the ones here by defining your own
// handler routines in your application code.
//*****************************************************************************
__attribute__ ((section(".after_vectors")))
void NMI_Handler(void)
{ while(1) {}
}
/* The fault handler implementation calls a function called
prvGetRegistersFromStack(). */
__attribute__ ((section(".after_vectors")))
void HardFault_Handler(void)
{
/* Use assembly to pick up date, but feed to C Code. */
__asm( ".syntax divided\n"
"MOVS R0, #4 \n"
"MOV R1, LR \n"
"TST R0, R1 \n"
"BEQ _MSP \n"
"MRS R0, PSP \n"
"B HardFault_HandlerC \n"
"_MSP: \n"
"MRS R0, MSP \n"
"B HardFault_HandlerC \n"
".syntax divided\n") ;
__asm(".syntax unified");
}
__attribute__ ((section(".after_vectors")))
void HardFault_HandlerC(
unsigned long *args)
{
volatile unsigned long cm_r0;
volatile unsigned long cm_r1;
volatile unsigned long cm_r2;
volatile unsigned long cm_r3;
volatile unsigned long cm_r12;
volatile unsigned long cm_lr;
volatile unsigned long cm_pc;
volatile unsigned long cm_psr;
//if (((uint32_t) args < PH_RAM_MEM_END)&& ( (uint32_t)args > PH_RAM_MEM_START))
//0x10000000 -- 0x8000
//0x2007c000 -- 0x8000
{
cm_r0 = ((unsigned long)args[0]);
cm_r1 = ((unsigned long)args[1]);
cm_r2 = ((unsigned long)args[2]);
cm_r3 = ((unsigned long)args[3]);
cm_r12 = ((unsigned long)args[4]);
cm_lr = ((unsigned long)args[5]);
cm_pc = ((unsigned long)args[6]);
cm_psr = ((unsigned long)args[7]);
PH_UNUSED_VARIABLE(cm_r0);
PH_UNUSED_VARIABLE(cm_r1);
PH_UNUSED_VARIABLE(cm_r2);
PH_UNUSED_VARIABLE(cm_r3);
PH_UNUSED_VARIABLE(cm_r12);
PH_UNUSED_VARIABLE(cm_lr);
PH_UNUSED_VARIABLE(cm_pc);
PH_UNUSED_VARIABLE(cm_psr);
}
/* Break into the debugger */
__asm("BKPT #0\n");
while (1)
{
__asm("wfi\n");
}
}
__attribute__ ((section(".after_vectors")))
void MemManage_Handler(void)
{ while(1) {}
}
__attribute__ ((section(".after_vectors")))
void BusFault_Handler(void)
{ while(1) {}
}
__attribute__ ((section(".after_vectors")))
void UsageFault_Handler(void)
{ while(1) {}
}
__attribute__ ((section(".after_vectors")))
void SVC_Handler(void)
{ while(1) {}
}
__attribute__ ((section(".after_vectors")))
void DebugMon_Handler(void)
{ while(1) {}
}
__attribute__ ((section(".after_vectors")))
void PendSV_Handler(void)
{ while(1) {}
}
//*****************************************************************************
//
// Processor ends up here if an unexpected interrupt occurs or a specific
// handler is not present in the application code.
//
//*****************************************************************************
__attribute__ ((section(".after_vectors")))
void IntDefaultHandler(void)
{ while(1) {}
}

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/*----------------------------------------------------------------------------*/
/* Copyright 2020 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may only */
/* be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that you */
/* have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*----------------------------------------------------------------------------*/
/** \file
* Example Source header for NfcrdlibEx6_LPCD.
* This application will configure Reader Library to provide demo on LPCD functionality of PN5180 Reader IC's.
* Please refer Readme.txt file for Hardware Pin Configuration, Software Configuration and steps to build and
* execute the project which is present in the same project directory.
*
* $Author$
* $Revision$ (v07.10.00)
* $Date$
*/
#include <NfcrdlibEx6_LPCD.h>
#ifdef NXPBUILD__PHHAL_HW_PN5180
#include <phApp_Init.h>
#include "BoardSelection.h"
/* HAL specific headers */
#include <phhalHw_Pn5180_Instr.h>
#include <phhalHw_Pn5180_Reg.h>
#define NXPBUILD__PHHAL_HW_PN5180_LPCD_SELF_CALIBRATION
#ifndef NXPBUILD__PHHAL_HW_PN5180_LPCD_SELF_CALIBRATION
#define NXPBUILD__PHHAL_HW_PN5180_LPCD_AUTO_CALIBRATION
#endif /* NXPBUILD__PHHAL_HW_PN5180_LPCD_SELF_CALIBRATION */
/* This macro will enable Calibration before every LPCD Detection Cycle. */
#define NXPBUILD__PHHAL_HW_PN5180_LPCD_CALIBRATE_ONCE
#define PN5180_LPCD_FIELD_ON_EEPROM_VALUE (LPCD_FIELD_ON_DURATION - 62U) / 8U
/**
LPCD_FIELD_ON_TIME address in E2PROM to configure the FIELD ON Time during LPCD
*/
#define PHHAL_HW_PN5180_LPCD_FIELD_ON_TIME_ADDR 0x36U
/**
LPCD_THRESHOLD address in E2PROM to configure the FIELD ON Time during LPCD
*/
#define PHHAL_HW_PN5180_LPCD_THRESHOLD_ADDR 0x37U
/*******************************************************************************
** Global Defines
*******************************************************************************/
/*******************************************************************************
** Global Variable Declaration
*******************************************************************************/
phbalReg_Type_t sBalParams;
phhalHw_Pn5180_DataParams_t * pHal;
/*******************************************************************************
** Static Defines
*******************************************************************************/
/*******************************************************************************
** Function Declaration
*******************************************************************************/
/*******************************************************************************
** Function Definitions
*******************************************************************************/
uint32_t dwLPCDCalibrateOption = 1;
phStatus_t Configure_LPCD(uint32_t *pdwLPCDCalibrateOption, uint32_t *pdwLPCDDemoOption)
{
phStatus_t wStatus = PH_ERR_SUCCESS;
uint8_t bEPromData[5];
uint8_t bEPromDPCControl;
// uint16_t wLPCDRefVal;
uint8_t bLPCDFieldONTime = PN5180_LPCD_FIELD_ON_EEPROM_VALUE;
uint8_t bLPCDThreshold = 0x10;
uint8_t bLPCD_Control;
uint32_t dwScanOption = 1;
#ifdef DEBUG
/* Prompt user to either select SW LPCD or ULPCD */
DEBUG_PRINTF("\nChoose below LPCD Demo Option ");
DEBUG_PRINTF("\nLPCD with self calibration always => 1 ");
DEBUG_PRINTF("\nLPCD with Auto calibration => 2 ");
DEBUG_PRINTF("\nEnter LPCD Demo Option : ");
DEBUG_SCAN("%X",&dwScanOption);
#else
#ifdef NXPBUILD__PHHAL_HW_PN5180_LPCD_SELF_CALIBRATION
#ifndef NXPBUILD__PHHAL_HW_PN5180_LPCD_CALIBRATE_ONCE
/* Calibration before every LPCD Cycle */
dwScanOption = 0x01U;
#else
/* Calibration before every LPCD Cycle */
dwScanOption = 0x02U;
#endif /* NXPBUILD__PHHAL_HW_PN5180_LPCD_CALIBRATE_ONCE */
#else
/* Auto Calibration before LPCD Cycle */
dwScanOption = 0x03U;
#endif /* NXPBUILD__PHHAL_HW_PN5180_LPCD_SELF_CALIBRATION */
#endif /* DEBUG */
/* Configure the LPCD Mode in EEPROM based on the Auto/Self Calibration mechanism */
/* Read LPCD Configuration settings and values from EEPROM */
wStatus = phhalHw_Pn5180_Instr_ReadE2Prom(pHal, PHHAL_HW_PN5180_LPCD_REFERENCE_VALUE_ADDR, bEPromData, 5U);
CHECK_SUCCESS(wStatus);
wStatus = phhalHw_Pn5180_Instr_ReadE2Prom(pHal, PHHAL_HW_PN5180_OCPROT_CONTROL_ADDR, &bEPromDPCControl, 1U);
CHECK_SUCCESS(wStatus);
// wLPCDRefVal = (bEPromData[0] | (bEPromData[1] < 8));
bLPCD_Control = bEPromData[4];
if (dwScanOption != 2)
{
if ((bLPCD_Control & LPCD_REFVAL_CONTROL_MASK) != 0x01U)
{
bLPCD_Control = ((bLPCD_Control & (uint8_t)~LPCD_REFVAL_CONTROL_MASK) | 0x01U);
}
if ((bEPromDPCControl & 0x01U) != 0U)
{
bEPromDPCControl = (bEPromDPCControl & (uint8_t)~0x01U);
wStatus = phhalHw_Pn5180_Instr_WriteE2Prom(pHal, PHHAL_HW_PN5180_OCPROT_CONTROL_ADDR, &bEPromDPCControl, 1U);
CHECK_SUCCESS(wStatus);
}
}
else
{
if ((bLPCD_Control & LPCD_REFVAL_CONTROL_MASK) != 0x00U)
{
bLPCD_Control = (bLPCD_Control & (uint8_t)~LPCD_REFVAL_CONTROL_MASK);
}
}
/* Configuring LPCD_GPO_REFVAL_CONTROL_ADDR to either configure Self or Auto Calibration.
* Based on user input. */
if (bLPCD_Control != bEPromData[4])
{
/* Write LPCD_REFVAL_GPO_CONTROL setting to SELF Calibration in EEPROM */
wStatus = phhalHw_Pn5180_Instr_WriteE2Prom(pHal, PHHAL_HW_PN5180_LPCD_GPO_REFVAL_CONTROL_ADDR, &bLPCD_Control, 1U);
CHECK_SUCCESS(wStatus);
}
/* Configuring Higher Field ON time leads to higher Power consumption.
* This values needs to configured to achieve best power requirement of User. */
if (bLPCDFieldONTime != bEPromData[2])
{
/* Configure required LPCD FIELD ON Time in EEPROM used during LPCD Calibration and Detection cycle. */
wStatus = phhalHw_Pn5180_Instr_WriteE2Prom(pHal, PHHAL_HW_PN5180_LPCD_FIELD_ON_TIME_ADDR, &bLPCDFieldONTime, 1U);
CHECK_SUCCESS(wStatus);
}
/* Configuring Higher Threshold requires higher Antenna De-tuning to exit LPCD Detection Cycle.
* Lower the values needs to configured to achieve best power requirement of User. */
if (bLPCDThreshold != bEPromData[3])
{
/* Configure required LPCD threshold in EEPROM based on the required range */
wStatus = phhalHw_Pn5180_Instr_WriteE2Prom(pHal, PHHAL_HW_PN5180_LPCD_THRESHOLD_ADDR, &bLPCDThreshold, 1U);
CHECK_SUCCESS(wStatus);
}
dwLPCDCalibrateOption = dwScanOption;
*pdwLPCDCalibrateOption = dwScanOption;
*pdwLPCDDemoOption = 0;
return PH_ERR_SUCCESS;
}
/* Perform LPCD Calibration */
phStatus_t Calibrate_LPCD(uint32_t dwLPCDDemo, uint32_t *pdwLPCDRefValue)
{
phStatus_t wStatus = PH_ERR_SUCCESS;
uint32_t dwAgcRefReg;
if (dwLPCDCalibrateOption != 2U)
{
/* Read the current AGC Gear and AGC measurement */
wStatus = phhalHw_Pn5180_Instr_ReadRegister(pHal, AGC_REF_CONFIG, &dwAgcRefReg);
CHECK_SUCCESS(wStatus);
/* Write back AGC Gear and AGC measurement */
wStatus = phhalHw_Pn5180_Instr_WriteRegister(pHal, AGC_REF_CONFIG, dwAgcRefReg);
CHECK_SUCCESS(wStatus);
DEBUG_PRINTF("\nLPCD Calibration Successful. ");
}
else
{
DEBUG_PRINTF("\nLPCD Calibration not required as Self Calibration is been selected. ");
}
return wStatus;
}
/**
*/
phStatus_t DemoLPCD(uint32_t dwLPCDDemo, uint32_t dwLPCDRefValue, uint16_t wLPCDWakeUpTime)
{
phStatus_t wStatus = PH_ERR_SUCCESS;
wStatus = phhalHw_Pn5180_Int_LPCD_SetConfig(pHal, PHHAL_HW_CONFIG_SET_LPCD_WAKEUPTIME_MS, wLPCDWakeUpTime);
CHECK_SUCCESS(wStatus);
wStatus = phhalHw_Pn5180_Int_LPCD_SetConfig(pHal, PHHAL_HW_CONFIG_LPCD_MODE, PHHAL_HW_PN5180_LPCD_MODE_POWERDOWN);
CHECK_SUCCESS(wStatus);
/* Perform LPCD Detection Cycle */
wStatus = phhalHw_Lpcd(pHal);
if(wStatus == PH_ERR_SUCCESS)
{
DEBUG_PRINTF("\n!!!!!!!!!!!!!!!!!!!!!!!!!LPCD Exited due to Load Change.!!!!!!!!!!!!!!!!!!!!!!!!!\n\n");
}
else
{
DEBUG_PRINTF("\n!!!!!!!!!!!!!!!!!!!!!!!!!LPCD Exited due to error.!!!!!!!!!!!!!!!!!!!!!!!!!\n\n");
}
return wStatus;
}
/*******************************************************************************
** CLIF ISR Handler
*******************************************************************************/
void CLIF_IRQHandler(void)
{
/* Read the interrupt status of external interrupt attached to the reader IC IRQ pin */
if (phDriver_PinRead(PHDRIVER_PIN_IRQ, PH_DRIVER_PINFUNC_INTERRUPT))
{
phDriver_PinClearIntStatus(PHDRIVER_PIN_IRQ);
/* Call application registered callback. */
if (pHal->pRFISRCallback != NULL)
{
pHal->pRFISRCallback(pHal);
}
}
}
#endif /* NXPBUILD__PHHAL_HW_PN5180 */

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/*----------------------------------------------------------------------------*/
/* Copyright 2020,2022-2023 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may only */
/* be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that you */
/* have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*----------------------------------------------------------------------------*/
/** \file
* Example Source header for NfcrdlibEx6_LPCD.
* This application will configure Reader Library to provide demo on LPCD functionality of PN5190 Reader IC's.
* Please refer Readme.txt file for Hardware Pin Configuration, Software Configuration and steps to build and
* execute the project which is present in the same project directory.
*
* $Author$
* $Revision$ (v07.10.00)
* $Date$
*/
#include <NfcrdlibEx6_LPCD.h>
#ifdef NXPBUILD__PHHAL_HW_PN5190
#include <phApp_Init.h>
#include "BoardSelection.h"
/* HAL specific headers */
#include <phhalHw_Pn5190_Instr.h>
#include <phhalHw_Pn5190_Reg.h>
#define NXPBUILD__PHHAL_HW_PN5190_ENABLE_SW_LPCD
#ifndef NXPBUILD__PHHAL_HW_PN5190_ENABLE_SW_LPCD
#define NXPBUILD__PHHAL_HW_PN5190_ENABLE_ULPCD
#endif /* NXPBUILD__PHHAL_HW_PN5190_ENABLE_SW_LPCD */
/* Release Build Configuration to work with different Calibration options in Example */
#define NXPBUILD__PHHAL_HW_PN5190_LPCD_CALIBRATE_ONCE
/*******************************************************************************
** Global Variable Declaration
*******************************************************************************/
phbalReg_Type_t sBalParams;
phhalHw_Pn5190_DataParams_t * pHal;
#ifdef DEBUG_PRINT_RAW_DATA
#define MAX_RAW_DATA_LENGTH (1100)
uint8_t g_Raw_Data[MAX_RAW_DATA_LENGTH];
uint32_t g_Raw_Data_Index = 0;
#endif /* DEBUG_PRINT_RAW_DATA */
#define PN5190_DIRECTION_BYTE_LEN 0x01U
#define PN5190_TYPE_FIELD_LEN 0x01U
#define PN5190_LENGTH_FIELD_LEN 0x02U
#define PN5190_STATUS_FIELD_LEN 0x01U
/*******************************************************************************
** Global Defines
*******************************************************************************/
#define PHHAL_HW_PN5190_PWR_CONFIG_ADDR 0x00U
#define PHHAL_HW_PN5190_TX_LDO_VDDPA_HIGH_ADDR 0x06U
#define PHHAL_HW_PN5190_TX_LDO_VDDPA_LOW_ADDR 0x07U
#define PHHAL_HW_PN5190_DPC_CONFIG_ADDR 0x76U
#define PHHAL_HW_PN5190_GPIO3_ABORT_POLARITY_ADDR 0x4CCU
/* Configure the required VDDPA Voltage Value that should be used to work with ULPCD. */
#define PHHAL_HW_PN5190_TX_LDO_VDDPA_V2_7_VALUE 0x0CU
/*******************************************************************************
** Static Defines
*******************************************************************************/
static phStatus_t SW_LPCD_Calib(uint32_t * pdwRefValue);
static phStatus_t SW_LPCD_Demo(uint32_t dwLPCDRefValue, uint16_t wLPCDWakeUpTime);
static phStatus_t ULPCD_Get_HFATT_Value();
static phStatus_t ULPCD_Configure_GPIO3();
static phStatus_t ULPCD_Calib(uint32_t * pdwRefValue);
static phStatus_t ULPCD_Demo(uint32_t dwLPCDRefValue, uint16_t wLPCDWakeUpTime);
/*******************************************************************************
** Function Declarations
*******************************************************************************/
void CLIF_IRQHandler(void);
/*******************************************************************************
** Function Definitions
*******************************************************************************/
static phStatus_t SW_LPCD_Calib(uint32_t * pdwRefValue)
{
phStatus_t wStatus;
/* Configure the Wake-up time to Turn ON the RF Field to measure reference values for SW LPCD Cycle */
wStatus = phhalHw_Pn5190_Instr_LPCD_SetConfig(pHal, PHHAL_HW_CONFIG_SET_LPCD_WAKEUPTIME_MS, 330U);
CHECK_SUCCESS(wStatus);
/* Configure the LPCD Mode to Default to perform SW LPCD Calibration Cycle */
wStatus = phhalHw_Pn5190_Instr_LPCD_SetConfig(pHal, PHHAL_HW_CONFIG_LPCD_MODE, PHHAL_HW_PN5190_LPCD_MODE_DEFAULT);
CHECK_SUCCESS(wStatus);
/* Configure the LPCD Mode for SW LPCD Calibration */
wStatus = phhalHw_Pn5190_Instr_LPCD_SetConfig(pHal, PHHAL_HW_CONFIG_LPCD_CONFIG, PHHAL_HW_PN5190_LPCD_CTRL_LPCD_CALIB);
CHECK_SUCCESS(wStatus);
/* Perform LPCD Calibration Cycle */
wStatus = phhalHw_Lpcd(pHal);
CHECK_SUCCESS(wStatus);
/* Get the Calibration value obtained during LPCD Calibration Cycle */
return phhalHw_Pn5190_Instr_LPCD_GetConfig(pHal, PHHAL_HW_CONFIG_LPCD_REF_VAL, pdwRefValue);
}
static phStatus_t SW_LPCD_Demo(uint32_t dwLPCDRefValue, uint16_t wLPCDWakeUpTime)
{
phStatus_t wStatus;
/* Configure the Wake-up time between successive RF Field ON to measure and compare against the reference value
* during SW LPCD Cycle. This can be fine tuned by User to obtain required Power efficiency. */
wStatus = phhalHw_Pn5190_Instr_LPCD_SetConfig(pHal, PHHAL_HW_CONFIG_SET_LPCD_WAKEUPTIME_MS, wLPCDWakeUpTime);
CHECK_SUCCESS(wStatus);
/* Configure the LPCD Mode to Power-down to perform SW LPCD Detection Cycle */
wStatus = phhalHw_Pn5190_Instr_LPCD_SetConfig(pHal, PHHAL_HW_CONFIG_LPCD_MODE, PHHAL_HW_PN5190_LPCD_MODE_POWERDOWN);
CHECK_SUCCESS(wStatus);
/* Configure the LPCD Mode for SW LPCD Detection Cycle */
wStatus = phhalHw_Pn5190_Instr_LPCD_SetConfig(pHal, PHHAL_HW_CONFIG_LPCD_CONFIG, PHHAL_HW_PN5190_LPCD_CTRL_LPCD);
CHECK_SUCCESS(wStatus);
/* Set the Calibration value obtained during last LPCD Calibration Cycle */
wStatus = phhalHw_Pn5190_Instr_LPCD_SetConfig(pHal, PHHAL_HW_CONFIG_LPCD_REF_VAL, dwLPCDRefValue);
CHECK_SUCCESS(wStatus);
/* Perform LPCD Detection Cycle */
return phhalHw_Lpcd(pHal);
}
static phStatus_t ULPCD_Get_HFATT_Value()
{
phStatus_t wStatus = PH_ERR_INTERNAL_ERROR;
uint8_t bReadEEPROM_Val;
uint8_t bHFATT_Val;
uint32_t dwReadReg_Val;
uint8_t bVddpa_Val = PHHAL_HW_PN5190_TX_LDO_VDDPA_V2_7_VALUE;
uint8_t bDPC_EEPROM_Val;
/* Read EEPROM Power Configuration value. */
wStatus = phhalHw_Pn5190_Instr_ReadE2Prom(pHal, PHHAL_HW_PN5190_PWR_CONFIG_ADDR, &bReadEEPROM_Val, 0x01U);
CHECK_SUCCESS(wStatus);
if (bReadEEPROM_Val != 0x21U)
{
/* Update the EEPROM Power Configuration value to VUP connected to VBat. */
bReadEEPROM_Val = 0x21U;
wStatus = phhalHw_Pn5190_Instr_WriteE2Prom(pHal, PHHAL_HW_PN5190_PWR_CONFIG_ADDR, &bReadEEPROM_Val, 0x01U);
CHECK_SUCCESS(wStatus);
}
wStatus = phhalHw_Pn5190_Instr_ReadE2Prom(pHal, PHHAL_HW_PN5190_TX_LDO_VDDPA_HIGH_ADDR, &bReadEEPROM_Val, 0x01U);
CHECK_SUCCESS(wStatus);
/* VDDPA High EEPROM Configuration is updated to work with VDDPA value of 2.7V.
* This can be different based on user configuration to use PN5190 Reader IC. */
if (bReadEEPROM_Val != bVddpa_Val)
{
wStatus = phhalHw_Pn5190_Instr_WriteE2Prom(pHal, PHHAL_HW_PN5190_TX_LDO_VDDPA_HIGH_ADDR, &bVddpa_Val, 0x01U);
CHECK_SUCCESS(wStatus);
}
wStatus = phhalHw_Pn5190_Instr_ReadE2Prom(pHal, PHHAL_HW_PN5190_TX_LDO_VDDPA_LOW_ADDR, &bReadEEPROM_Val, 0x01U);
CHECK_SUCCESS(wStatus);
/* VDDPA High EEPROM Configuration is updated to work with VDDPA value of 2.7V.
* This can be different based on user configuration to use PN5190 Reader IC. */
if (bReadEEPROM_Val != bVddpa_Val)
{
wStatus = phhalHw_Pn5190_Instr_WriteE2Prom(pHal, PHHAL_HW_PN5190_TX_LDO_VDDPA_LOW_ADDR, &bVddpa_Val, 0x01U);
CHECK_SUCCESS(wStatus);
}
/* Read DPC Configuration value. */
wStatus = phhalHw_Pn5190_Instr_ReadE2Prom(pHal, PHHAL_HW_PN5190_DPC_CONFIG_ADDR, &bDPC_EEPROM_Val, 0x01U);
CHECK_SUCCESS(wStatus);
if (bDPC_EEPROM_Val != 0x00U)
{
bReadEEPROM_Val = 0x00U;
/* Disable DPC to get HFATT value by turning ON the RF Field. */
wStatus = phhalHw_Pn5190_Instr_WriteE2Prom(pHal, PHHAL_HW_PN5190_DPC_CONFIG_ADDR, &bReadEEPROM_Val, 0x01U);
CHECK_SUCCESS(wStatus);
}
/* Apply Reader Mode Type A settings. */
wStatus = phhalHw_ApplyProtocolSettings(pHal, PHHAL_HW_CARDTYPE_ISO14443A);
CHECK_SUCCESS(wStatus);
/* Turn ON the RF Field. */
wStatus = phhalHw_FieldOn(pHal);
CHECK_SUCCESS(wStatus);
/* Wait for sometime to stabilize RF ON before reading HF ATT value. */
wStatus = phhalHw_Wait(pHal, PHHAL_HW_TIME_MICROSECONDS, 1500);
CHECK_SUCCESS(wStatus);
/* Read HF ATT value. */
wStatus = phhalHw_Pn5190_Instr_ReadRegister(pHal, CLIF_RXCTRL_STATUS, &dwReadReg_Val);
CHECK_SUCCESS(wStatus);
/* Get the HF ATT Value */
bHFATT_Val = (uint8_t)((dwReadReg_Val & CLIF_RXCTRL_STATUS_RXCTRL_HF_ATT_VAL_MASK) >> CLIF_RXCTRL_STATUS_RXCTRL_HF_ATT_VAL_POS);
/* Configure the HF ATT value that should be used with ULPCD Calib and Detection cycle. */
wStatus = phhalHw_Pn5190_Instr_LPCD_SetConfig(pHal, PHHAL_HW_CONFIG_LPCD_HFATT_VAL, (uint16_t)bHFATT_Val);
CHECK_SUCCESS(wStatus);
if (bDPC_EEPROM_Val != 0x77U)
{
bReadEEPROM_Val = 0x77U;
/* Enable DPC. */
wStatus = phhalHw_Pn5190_Instr_WriteE2Prom(pHal, PHHAL_HW_PN5190_DPC_CONFIG_ADDR, &bReadEEPROM_Val, 0x01U);
CHECK_SUCCESS(wStatus);
}
/* Turn OFF the RF Field. */
wStatus = phhalHw_FieldOff(pHal);
CHECK_SUCCESS(wStatus);
return wStatus;
}
static phStatus_t ULPCD_Configure_GPIO3()
{
phStatus_t wStatus = PH_ERR_INTERNAL_ERROR;
uint8_t bGPIO3PolarityVal;
/* Read EEPROM GPIO3 abort polarity value. */
wStatus = phhalHw_Pn5190_Instr_ReadE2Prom(pHal, PHHAL_HW_PN5190_GPIO3_ABORT_POLARITY_ADDR, &bGPIO3PolarityVal, 0x01);
CHECK_SUCCESS(wStatus);
if(bGPIO3PolarityVal == 0x00U)
{
/* Update EEPROM GPIO3 abort polarity value to high.
* For K82-PN5190, No external connection is required from NFC_GPIO3 to TP7 of K82.
* For LPC1769_PN5190, Jumper 7-8 of j12 which connects Triton GPIO3 to LPC GPIO3 should be removed. */
bGPIO3PolarityVal = 0x01U;
wStatus = phhalHw_Pn5190_Instr_WriteE2Prom(pHal, PHHAL_HW_PN5190_GPIO3_ABORT_POLARITY_ADDR, &bGPIO3PolarityVal, 0x01);
CHECK_SUCCESS(wStatus);
}
return wStatus;
}
static phStatus_t ULPCD_Calib(uint32_t * pdwRefValue)
{
phStatus_t wStatus;
/* Configure EEPROM GPIO3 abort polarity value */
wStatus = ULPCD_Configure_GPIO3();
CHECK_SUCCESS(wStatus);
/* Get the HF ATT value. */
wStatus = ULPCD_Get_HFATT_Value();
CHECK_SUCCESS(wStatus);
/* Configure the Wake-up time to Turn ON the RF Field to measure reference values for ULPCD Cycle */
wStatus = phhalHw_Pn5190_Instr_LPCD_SetConfig(pHal, PHHAL_HW_CONFIG_SET_LPCD_WAKEUPTIME_MS, 330U);
CHECK_SUCCESS(wStatus);
/* Configure the LPCD Mode to Default to perform ULPCD Calibration Cycle */
wStatus = phhalHw_Pn5190_Instr_LPCD_SetConfig(pHal, PHHAL_HW_CONFIG_LPCD_MODE, PHHAL_HW_PN5190_LPCD_MODE_DEFAULT);
CHECK_SUCCESS(wStatus);
/* Configure the LPCD Mode for ULPCD Calibration */
wStatus = phhalHw_Pn5190_Instr_LPCD_SetConfig(pHal, PHHAL_HW_CONFIG_LPCD_CONFIG, PHHAL_HW_PN5190_LPCD_CTRL_ULPCD_CALIB);
CHECK_SUCCESS(wStatus);
/* Perform LPCD Calibration Cycle */
wStatus = phhalHw_Lpcd(pHal);
CHECK_SUCCESS(wStatus);
/* Get the Calibration value obtained during LPCD Calibration Cycle */
return phhalHw_Pn5190_Instr_LPCD_GetConfig(pHal, PHHAL_HW_CONFIG_LPCD_REF_VAL, pdwRefValue);
}
static phStatus_t ULPCD_Demo(uint32_t dwLPCDRefValue, uint16_t wLPCDWakeUpTime)
{
phStatus_t wStatus;
/* Configure the Wake-up time between successive RF Field ON to measure and compare against the reference value
* during SW LPCD Cycle. This can be fine tuned by User to obtain required Power efficiency. */
wStatus = phhalHw_Pn5190_Instr_LPCD_SetConfig(pHal, PHHAL_HW_CONFIG_SET_LPCD_WAKEUPTIME_MS, wLPCDWakeUpTime);
CHECK_SUCCESS(wStatus);
/* Configure the LPCD Mode to Power-down to perform SW LPCD Detection Cycle */
wStatus = phhalHw_Pn5190_Instr_LPCD_SetConfig(pHal, PHHAL_HW_CONFIG_LPCD_MODE, PHHAL_HW_PN5190_LPCD_MODE_POWERDOWN);
CHECK_SUCCESS(wStatus);
/* Configure the LPCD Mode for SW LPCD Detection Cycle */
wStatus = phhalHw_Pn5190_Instr_LPCD_SetConfig(pHal, PHHAL_HW_CONFIG_LPCD_CONFIG, PHHAL_HW_PN5190_LPCD_CTRL_ULPCD);
CHECK_SUCCESS(wStatus);
/* Set the Calibration value obtained during last LPCD Calibration Cycle */
wStatus = phhalHw_Pn5190_Instr_LPCD_SetConfig(pHal, PHHAL_HW_CONFIG_LPCD_REF_VAL, dwLPCDRefValue);
CHECK_SUCCESS(wStatus);
/* Perform LPCD Detection Cycle */
return phhalHw_Lpcd(pHal);
}
void PrintLPCDExitReason()
{
uint32_t dwLPCDEventStatus;
(void)phhalHw_Pn5190_Instr_LPCD_GetConfig(pHal, PHHAL_HW_CONFIG_LPCD_RETRIEVE_EVENT_STATUS, &dwLPCDEventStatus);
switch(dwLPCDEventStatus)
{
case PHHAL_HW_LPCD_EVT_STATUS_GPIO3_ABORT:
DEBUG_PRINTF("\n!!!!!!!!!!!!!!!!!!!!!!!!!LPCD Exited due to GPIO3 Toggle.!!!!!!!!!!!!!!!!!!!!!!!!!\n\n");
break;
case PHHAL_HW_LPCD_EVT_STATUS_EXTERNALRF_FIELD:
DEBUG_PRINTF("\n!!!!!!!!!!!!!!!!!!!!!!!!!LPCD Exited due to External RF field.!!!!!!!!!!!!!!!!!!!!!!!!!\n\n");
break;
case PHHAL_HW_LPCD_EVT_STATUS_HIF_ACTIVITY:
DEBUG_PRINTF("\n!!!!!!!!!!!!!!!!!!!!!!!!!LPCD Exited due to HIF Activity.!!!!!!!!!!!!!!!!!!!!!!!!!\n\n");
break;
case PHHAL_HW_LPCD_EVT_STATUS_VDDPA_LDO_OVERCURRENT:
case PHHAL_HW_LPCD_EVT_STATUS_XTAL_TIMEOUT:
case PHHAL_HW_LPCD_EVT_STATUS_CLKDET_ERROR:
default:
DEBUG_PRINTF("\n!!!!!!!!!!!!!!!!!!!!!!!!!LPCD Exited due to event = %X.!!!!!!!!!!!!!!!!!!!!!!!!!\n\n", dwLPCDEventStatus);
break;
}
}
uint32_t dwLPCDCalibrateOption = 1;
uint32_t dwLPCDDemoOption = 1;
uint32_t dwLPCDRefValue;
phStatus_t Configure_LPCD(uint32_t *pdwLPCDCalibrateOption, uint32_t *pdwLPCDDemoOption)
{
#ifdef DEBUG
uint32_t dwScanOption = 1;
/* Prompt user to either select SW LPCD or ULPCD */
DEBUG_PRINTF("\nChoose below LPCD Demo Option ");
DEBUG_PRINTF("\nSW LPCD with calibration always => 11 ");
DEBUG_PRINTF("\nSW LPCD with calibration once => 12 ");
DEBUG_PRINTF("\nULPCD with calibration always => 21 ");
DEBUG_PRINTF("\nULPCD with calibration once => 22 ");
DEBUG_PRINTF("\nTry Turn ON and OFF of RF Field => 30 ");
DEBUG_PRINTF("\nEnter LPCD Demo Option : ");
DEBUG_SCAN("%X",&dwScanOption);
*pdwLPCDCalibrateOption = dwScanOption & 0xF;
*pdwLPCDDemoOption = (dwScanOption >> 4);
#else
#ifdef NXPBUILD__PHHAL_HW_PN5190_ENABLE_SW_LPCD
/* Demo of SW LPCD Feature of PN5190 */
*pdwLPCDDemoOption = 0x01U;
#endif /* NXPBUILD__PHHAL_HW_PN5190_ENABLE_SW_LPCD */
#ifdef NXPBUILD__PHHAL_HW_PN5190_ENABLE_ULPCD
/* Demo of ULPCD Feature of PN5190 */
*pdwLPCDDemoOption = 0x02U;
#endif /* NXPBUILD__PHHAL_HW_PN5190_ENABLE_ULPCD */
#ifdef NXPBUILD__PHHAL_HW_PN5190_LPCD_CALIBRATE_ONCE
/* Calibration before every LPCD Cycle */
*pdwLPCDCalibrateOption = 0x02U;
#else
/* Calibration Once before first LPCD Cycle */
*pdwLPCDCalibrateOption = 0x01U;
#endif /* NXPBUILD__PHHAL_HW_PN5190_LPCD_CALIBRATE_ONCE */
#endif
/* TODO : Configuration of LPCD Threshold to vary the LPCD Range */
return PH_ERR_SUCCESS;
}
/* Perform LPCD Calibration */
phStatus_t Calibrate_LPCD(uint32_t dwLPCDDemo, uint32_t *pdwLPCDRefValue)
{
phStatus_t wStatus = PH_ERR_SUCCESS;
switch(dwLPCDDemo)
{
case 1:
/* Software LPCD feature that can be used with any Power Configuration of PN5190 Reader IC. */
wStatus = SW_LPCD_Calib(pdwLPCDRefValue);
if(wStatus == PH_ERR_SUCCESS)
{
DEBUG_PRINTF("\nSW LPCD Calibration Successful. ");
}
else
{
DEBUG_PRINTF("\nSW LPCD Calibration Failed. ");
}
break;
case 2:
/* Hardware LPCD feature that can be used with only VBat Power Configuration of PN5190 Reader IC. */
wStatus = ULPCD_Calib(pdwLPCDRefValue);
if(wStatus == PH_ERR_SUCCESS)
{
DEBUG_PRINTF("\nULPCD Calibration Successful. ");
}
else
{
DEBUG_PRINTF("\nULPCD Calibration Failed. ");
}
break;
case 3:
default:
break;
}
return wStatus;
}
/**
*/
phStatus_t DemoLPCD(uint32_t dwLPCDDemo, uint32_t dwLPCDRefValue, uint16_t wLPCDWakeUpTime)
{
phStatus_t wStatus = PH_ERR_SUCCESS;
switch(dwLPCDDemo)
{
case 1:
/* SW LPCD Demo */
wStatus = SW_LPCD_Demo(dwLPCDRefValue, wLPCDWakeUpTime);
if(wStatus == PH_ERR_SUCCESS)
{
DEBUG_PRINTF("\n!!!!!!!!!!!!!!!!!!!!!!!!!SW LPCD Exited due to Load Change.!!!!!!!!!!!!!!!!!!!!!!!!!\n\n");
}
else
{
PrintLPCDExitReason();
}
break;
case 2:
/* ULPCD Demo */
wStatus = ULPCD_Demo(dwLPCDRefValue, wLPCDWakeUpTime);
if(wStatus == PH_ERR_SUCCESS)
{
DEBUG_PRINTF("\n!!!!!!!!!!!!!!!!!!!!!!!!!ULPCD Exited due to Load Change.!!!!!!!!!!!!!!!!!!!!!!!!!\n\n");
}
else
{
PrintLPCDExitReason();
}
break;
case 3:
wStatus = phhalHw_FieldOff(pHal);
CHECK_SUCCESS(wStatus);
wStatus = phhalHw_ApplyProtocolSettings(pHal, PHHAL_HW_CARDTYPE_ISO14443A);
CHECK_SUCCESS(wStatus);
wStatus = phhalHw_FieldOn(pHal);
CHECK_SUCCESS(wStatus);
wStatus = phhalHw_Wait(pHal, PHHAL_HW_TIME_MILLISECONDS, 500);
CHECK_SUCCESS(wStatus);
wStatus = phhalHw_FieldOff(pHal);
CHECK_SUCCESS(wStatus);
wStatus = phhalHw_Wait(pHal, PHHAL_HW_TIME_MILLISECONDS, 500);
CHECK_SUCCESS(wStatus);
break;
default:
DEBUG_PRINTF("\nWrong Input is been provided, please enter correct option once again. ");
DEBUG_PRINTF("\nRestart to provide correct input. ");
while(1);
break;
}
DEBUG_PRINTF("\n---------------Restart to try another option.---------------\n\n");
return wStatus;
}
/*******************************************************************************
** BAL Exchange
*******************************************************************************/
/* Read the data over SPI */
phStatus_t phApp_Pn5190_SPIRead(uint8_t * pRxBuffer,
uint16_t wRxLength)
{
phStatus_t PH_MEMLOC_REM status = PH_ERR_SUCCESS;
uint16_t PH_MEMLOC_REM wResponseLen = 0U;
/* Enable chip select connected to reader IC (NSS low). */
phDriver_PinWrite(PHDRIVER_PIN_SSEL, PH_DRIVER_SET_LOW);
/* Read back response */
status = phbalReg_Exchange(
&sBalParams,
PH_EXCHANGE_DEFAULT,
NULL,
0U,
wRxLength,
pRxBuffer,
&wResponseLen);
/* Disable chip select connected to reader IC (NSS high). */
phDriver_PinWrite(PHDRIVER_PIN_SSEL, PH_DRIVER_SET_HIGH);
if(wResponseLen != wRxLength)
{
status = PH_ERR_INTERNAL_ERROR;
}
#ifdef DEBUG_PRINT_RAW_DATA
uint16_t cnt = 0;
if((g_Raw_Data_Index + wRxLength+4) < MAX_RAW_DATA_LENGTH)
{
g_Raw_Data[g_Raw_Data_Index++] = 'C';
g_Raw_Data[g_Raw_Data_Index++] = 'C';
for(cnt=0; cnt < wRxLength; cnt++)
{
g_Raw_Data[g_Raw_Data_Index++] = pRxBuffer[cnt];
}
g_Raw_Data[g_Raw_Data_Index++] = 'D';
g_Raw_Data[g_Raw_Data_Index++] = 'D';
}
uint16_t cnt = 0;
printf("\nRX: ");
for(cnt=0; cnt < wRxLength; cnt++)
{
printf("%02X ", pRxBuffer[cnt]);
}
#endif /* DEBUG_PRINT_RAW_DATA */
return status;
}
volatile uint8_t bSkipEventPost = 0x0U;
/* Application callback to handle Asynchronous events which cannot be processed by RdLib */
void phApp_CallBack(void)
{
uint32_t dwEventStatusReg = 0x0U;
uint16_t wEventLen = 0x0U;
uint8_t bBackUp = 0U;
uint8_t bSPIReadLen = 0U;
/* Event length is of 2 byte @bIndex 2 and 3 */
wEventLen = (uint16_t) pHal->sIrqResp.pIsrEvtBuffPtr[2];
wEventLen <<= 8;
wEventLen |= ((uint16_t) pHal->sIrqResp.pIsrEvtBuffPtr[3]);
dwEventStatusReg = (uint32_t) pHal->sIrqResp.pIsrEvtBuffPtr[4];
dwEventStatusReg |= ((uint32_t) pHal->sIrqResp.pIsrEvtBuffPtr[5]) << 8U ;
dwEventStatusReg |= ((uint32_t) pHal->sIrqResp.pIsrEvtBuffPtr[6]) << 16U;
dwEventStatusReg |= ((uint32_t) pHal->sIrqResp.pIsrEvtBuffPtr[7]) << 24U;
if ((dwEventStatusReg & PH_PN5190_EVT_TX_OVERCURRENT_ERROR) != 0U)
{
DEBUG_PRINTF ("\n\tReceived TX Over Current Event... \n");
(void)phhalHw_AsyncAbort(pHal);
}
if ((dwEventStatusReg & PH_PN5190_EVT_CTS) != 0U)
{
DEBUG_PRINTF ("\n\tReceived CTS Event... \n");
(void)phhalHw_SetConfig(pHal, PHHAL_HW_PN5190_CONFIG_CTS_EVENT_STATUS, PH_ON);
}
if ((dwEventStatusReg & PH_PN5190_EVT_RFON_DETECT) != 0U)
{
(void)phhalHw_SetConfig(pHal, PHHAL_HW_PN5190_CONFIG_RF_ON_EVENT_STATUS, PH_ON);
bSkipEventPost = 0x1U;
bSPIReadLen = (pHal->sIrqResp.bIsrBytesRead -
(PN5190_DIRECTION_BYTE_LEN + PN5190_TYPE_FIELD_LEN + PN5190_LENGTH_FIELD_LEN));
if (wEventLen > bSPIReadLen)
{
bBackUp = pHal->sIrqResp.pIsrEvtBuffPtr[wEventLen - 1];
phApp_Pn5190_SPIRead(&pHal->sIrqResp.pIsrEvtBuffPtr[wEventLen - 1],
(uint16_t) (wEventLen - bSPIReadLen + PN5190_DIRECTION_BYTE_LEN));
pHal->sIrqResp.pIsrEvtBuffPtr[wEventLen - 1] = bBackUp;
}
}
if ((dwEventStatusReg & (0xFFFFFFFF << 0x0C)) != 0U)
{
DEBUG_PRINTF ("\n\tReceived Unexpected Event that should not be reported by PN5190... \n");
}
}
/*******************************************************************************
** CLIF ISR Handler
*******************************************************************************/
void CLIF_IRQHandler(void)
{
/* Read the interrupt status of external interrupt attached to the reader IC IRQ pin */
#ifndef PH_OSAL_LINUX
if (phDriver_PinRead(PHDRIVER_PIN_IRQ, PH_DRIVER_PINFUNC_INTERRUPT))
#endif /* PH_OSAL_LINUX */
{
phDriver_PinClearIntStatus(PHDRIVER_PIN_IRQ);
/* Call application registered callback. */
if ((pHal->wId == (PH_COMP_HAL | PHHAL_HW_PN5190_ID)) && (pHal->pRFISRCallback != NULL))
{
/* Read the data over SPI */
phApp_Pn5190_SPIRead(pHal->sIrqResp.pHandlerModeBuffPtr,
(uint16_t) pHal->sIrqResp.bIsrBytesRead);
/* Handle events triggered by PN5190 for previous command execution */
if( pHal->sIrqResp.pHandlerModeBuffPtr[1] == PH_PN5190_EVT_RSP )
{
pHal->sIrqResp.pIsrEvtBuffPtr = pHal->sIrqResp.pHandlerModeBuffPtr;
/* Call application registered callback to handle PN5190 Asynchronous events */
phApp_CallBack();
if (bSkipEventPost == 0x0U)
{
/* Call application RF callback to handle PN5190 synchronous events */
pHal->pRFISRCallback(pHal);
}
bSkipEventPost = 0x0U;
}
else
{
pHal->sIrqResp.pIsrBuffPtr = pHal->sIrqResp.pHandlerModeBuffPtr;
pHal->pRFISRCallback(pHal);
}
if (pHal->sIrqResp.pHandlerModeBuffPtr == &pHal->sIrqResp.aISRReadBuf[0])
{
pHal->sIrqResp.pHandlerModeBuffPtr = &pHal->sIrqResp.aISRReadBuf2[0];
}
else
{
pHal->sIrqResp.pHandlerModeBuffPtr = &pHal->sIrqResp.aISRReadBuf[0];
}
}
}
}
#endif /* NXPBUILD__PHHAL_HW_PN5190 */

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/*----------------------------------------------------------------------------*/
/* Copyright 2020 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may only */
/* be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that you */
/* have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*----------------------------------------------------------------------------*/
/** \file
* Example Source header for NfcrdlibEx6_LPCD.
* This application will configure Reader Library to provide demo on LPCD functionality of PN5180 Reader IC's.
* Please refer Readme.txt file for Hardware Pin Configuration, Software Configuration and steps to build and
* execute the project which is present in the same project directory.
*
* $Author$
* $Revision$ (v07.10.00)
* $Date$
*/
#include <NfcrdlibEx6_LPCD.h>
#ifdef NXPBUILD__PHHAL_HW_PN7462AU
#include <phApp_Init.h>
#include <phFlashBoot.h>
#include <phhalTimer.h>
#include <PN7462AU_pcr.h>
#include <ph_Reg.h>
/* This macro will enable Calibration before every LPCD Detection Cycle. */
#define NXPBUILD__PHHAL_HW_PN7462AU_LPCD_CALIBRATE_ONCE
#ifdef NXPBUILD__PHHAL_HW_PN7462AU
/*******************************************************************************
** Function Declarations
*******************************************************************************/
void phApp_CPU_Init(void);
/*******************************************************************************
** Global Variable Declaration
*******************************************************************************/
phhalHw_PN7462AU_DataParams_t * pHal;
/*******************************************************************************
** Initialize PN74XX NFC Controller
*******************************************************************************/
/**
* This function will initialize NXP NFC Controller.
*/
void phApp_CPU_Init(void)
{
phFlashBoot_Main();
phhalTimer_Init();
}
#endif /* NXPBUILD__PHHAL_HW_PN7462AU */
/*******************************************************************************
** Global Defines
*******************************************************************************/
/*******************************************************************************
** Static Defines
*******************************************************************************/
/*******************************************************************************
** Function Definitions
*******************************************************************************/
phStatus_t Configure_LPCD(uint32_t *pdwLPCDCalibrateOption, uint32_t *pdwLPCDDemoOption)
{
phStatus_t wStatus = PH_ERR_SUCCESS;
uint8_t bLPCDThreshold = 10U;
uint32_t dwScanOption = 1;
#ifdef DEBUG
/* Prompt user to either select LPCD Calibration once or always before LPCD Detection Cycle. */
DEBUG_PRINTF("\nChoose below LPCD Demo Option ");
DEBUG_PRINTF("\nLPCD with self calibration always => 1 ");
DEBUG_PRINTF("\nLPCD with self calibration once => 2 ");
DEBUG_PRINTF("\nEnter LPCD Demo Option : ");
DEBUG_SCAN("%X",&dwScanOption);
#else
#ifndef NXPBUILD__PHHAL_HW_PN7462AU_LPCD_CALIBRATE_ONCE
/* Calibration before every LPCD Cycle */
dwScanOption = 0x01U;
#else
/* Calibration before every LPCD Cycle */
dwScanOption = 0x02U;
#endif /* NXPBUILD__PHHAL_HW_PN7462AU_LPCD_CALIBRATE_ONCE */
#endif /* DEBUG */
/* Configure the required Threshold required based on the changes in environment.
* Lesser the Threshold, better the sensitivity.
* But Higher the value results in less false detections. */
wStatus = phhalHw_SetConfig(pHal, PHHAL_HW_CONFIG_PN7462AU_LPCD_THRESHOLD, bLPCDThreshold);
CHECK_SUCCESS(wStatus);
*pdwLPCDCalibrateOption = dwScanOption;
*pdwLPCDDemoOption = 0;
return PH_ERR_SUCCESS;
}
/* Perform LPCD Calibration and get LPCD reference value */
phStatus_t Calibrate_LPCD(uint32_t dwLPCDDemo, uint32_t *pdwLPCDRefValue)
{
phStatus_t wStatus = PH_ERR_SUCCESS;
uint32_t dwGetLpcdRef = 0;
uint32_t dwLPCDRefValue;
uint16_t wLpcdValue;
/* Provide LPCD Reference Value of 0 to LPCD API to perform LPCD Calibration
* and get the LPCD Calibration Value. */
dwLPCDRefValue = 0;
wStatus = phhalRf_LPCD(0xFFFFU, dwLPCDRefValue, &dwGetLpcdRef);
CHECK_SUCCESS(wStatus);
wLpcdValue = (uint16_t)dwGetLpcdRef;
if (wLpcdValue != 0x00)
{
/* Configure the LPCD Calibration value as a Reference value to perform LPCD Detection cycle. */
wStatus = phhalHw_SetConfig(pHal, PHHAL_HW_CONFIG_PN7462AU_LPCD_REF_VALUE, wLpcdValue);
CHECK_SUCCESS(wStatus);
}
DEBUG_PRINTF("\nLPCD Calibration Successful. ");
return wStatus;
}
/**
* With previous LPCD Calibration value, perform LPCD Detection cycle.
*/
phStatus_t DemoLPCD(uint32_t dwLPCDDemo, uint32_t dwLPCDRefValue, uint16_t wLPCDWakeUpTime)
{
phStatus_t wStatus = PH_ERR_SUCCESS;
do
{
/* Configure the required Wait time before performing LPCD detection cycle once again
* based on the power saving required by the User. */
(void)phhalHw_Wait(pHal, PHHAL_HW_TIME_MILLISECONDS, wLPCDWakeUpTime);
/* Perform LPCD Detection Cycle.
* Unlike other Reader HAL's, PN7462AU will return immediately if the LPCD Detection cycle
* is successful or not. In case the API returns an ERROR, we need to call the API once
* again, until the API return success indicating Card Detection. */
wStatus = phhalHw_Lpcd(pHal);
}while(wStatus != PH_ERR_SUCCESS);
DEBUG_PRINTF("\n!!!!!!!!!!!!!!!!!!!!!!!!!LPCD Exited due to Load Change.!!!!!!!!!!!!!!!!!!!!!!!!!\n\n");
return wStatus;
}
#endif /* NXPBUILD__PHHAL_HW_PN7462AU */

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/*----------------------------------------------------------------------------*/
/* Copyright 2022-2023 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may only */
/* be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that you */
/* have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*----------------------------------------------------------------------------*/
/** \file
* Example Source header for NfcrdlibEx6_LPCD.
* This application will configure Reader Library to provide demo on LPCD functionality of PN76XX NFC controller.
* Please refer Readme.txt file for Hardware Pin Configuration, Software Configuration and steps to build and
* execute the project which is present in the same project directory.
*
* $Author$
* $Revision$ (v07.10.00)
* $Date$
*/
#include <NfcrdlibEx6_LPCD.h>
#ifdef NXPBUILD__PHHAL_HW_PN76XX
#include <phApp_Init.h>
#include "Clif.h"
#include "PN76xx.h"
/* Release Build Configuration to work with different Calibration options in Example */
#define NXPBUILD__PHHAL_HW_PN76XX_LPCD_CALIBRATE_ONCE
/*******************************************************************************
** Global Variable Declaration
*******************************************************************************/
phhalHw_Pn76xx_DataParams_t * pHal;
uint32_t dwLPCDCalibrateOption = 1;
uint32_t dwLPCDDemoOption = 1;
uint32_t dwLPCDRefValue;
/*******************************************************************************
** Global Defines
*******************************************************************************/
/*******************************************************************************
** Static Defines
*******************************************************************************/
static phStatus_t SW_LPCD_Calib(uint32_t * pdwRefValue);
static phStatus_t SW_LPCD_Demo(uint32_t dwLPCDRefValue, uint16_t wLPCDWakeUpTime);
/*******************************************************************************
** Function Declarations
*******************************************************************************/
/*******************************************************************************
** Function Definitions
*******************************************************************************/
/**
* This function will initialize NXP NFC Controller.
*/
void phApp_CPU_Init(void)
{
#ifdef SEGGER_RTT_ENABLE
/* SEGGER RTT Init */
memset((uint8_t *)PN76_SEGGER_RTT_MEMORY_ALLOCATION_ADDRESS, 0, 0x4b8);
SEGGER_RTT_ConfigUpBuffer(0, NULL, NULL, 0, SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL);
#endif
/* To enable NS RF IRQ */
NVIC_EnableIRQ(CLIF_RF_IRQn);
/* To enable NS TIMER IRQ */
NVIC_EnableIRQ(TIMER_IRQn);
/* Initialize PMU */
PMU_Init();
/* Initialize SMU */
Smu_Init();
/* Initialize CLKGEN */
CLKGEN_Init();
}
static phStatus_t SW_LPCD_Calib(uint32_t * pdwRefValue)
{
phStatus_t wStatus;
/* Configure the Wake-up time to Turn ON the RF Field to measure reference values for SW LPCD Cycle */
wStatus = phhalHw_Pn76xx_LPCD_SetConfig(pHal, PHHAL_HW_CONFIG_SET_LPCD_WAKEUPTIME_MS, 330U);
CHECK_SUCCESS(wStatus);
/* Configure the LPCD Mode to Default to perform SW LPCD Calibration Cycle */
wStatus = phhalHw_Pn76xx_LPCD_SetConfig(pHal, PHHAL_HW_CONFIG_LPCD_MODE, PHHAL_HW_PN76XX_LPCD_MODE_DEFAULT);
CHECK_SUCCESS(wStatus);
/* Perform LPCD Calibration Cycle */
wStatus = phhalHw_Lpcd(pHal);
CHECK_SUCCESS(wStatus);
/* Get the Calibration value obtained during LPCD Calibration Cycle */
return phhalHw_Pn76xx_LPCD_GetConfig(pHal, PHHAL_HW_CONFIG_LPCD_REF_VAL, pdwRefValue);
}
static phStatus_t SW_LPCD_Demo(uint32_t dwLPCDRefValue, uint16_t wLPCDWakeUpTime)
{
phStatus_t wStatus;
/* Configure the Wake-up time between successive RF Field ON to measure and compare against the reference value
* during SW LPCD Cycle. This can be fine tuned by User to obtain required Power efficiency. */
wStatus = phhalHw_Pn76xx_LPCD_SetConfig(pHal, PHHAL_HW_CONFIG_SET_LPCD_WAKEUPTIME_MS, wLPCDWakeUpTime);
CHECK_SUCCESS(wStatus);
/* Configure the LPCD Mode to Power-down to perform SW LPCD Detection Cycle */
wStatus = phhalHw_Pn76xx_LPCD_SetConfig(pHal, PHHAL_HW_CONFIG_LPCD_MODE, PHHAL_HW_PN76XX_LPCD_MODE_POWERDOWN);
CHECK_SUCCESS(wStatus);
/* Perform LPCD Detection Cycle */
return phhalHw_Lpcd(pHal);
}
phStatus_t Configure_LPCD(uint32_t *pdwLPCDCalibrateOption, uint32_t *pdwLPCDDemoOption)
{
#ifdef DEBUG
uint32_t iChoice = 0;
/* Prompt user to either select SW LPCD or ULPCD */
DEBUG_PRINTF("\nChoose below LPCD Demo Option ");
DEBUG_PRINTF("\nSW LPCD with calibration always => 1 ");
DEBUG_PRINTF("\nSW LPCD with calibration once => 2 ");
DEBUG_PRINTF("\nEnter LPCD Demo Option : ");
DEBUG_SCANF("%X", &iChoice);
*pdwLPCDCalibrateOption = (uint32_t)(iChoice & 0xF);
#else /* DEBUG */
#ifndef NXPBUILD__PHHAL_HW_PN76XX_LPCD_CALIBRATE_ONCE
/* Calibration before every LPCD Cycle */
*pdwLPCDCalibrateOption = 0x01U;
#else /* NXPBUILD__PHHAL_HW_PN76XX_LPCD_CALIBRATE_ONCE */
/* Calibration Once before first LPCD Cycle */
*pdwLPCDCalibrateOption = 0x02U;
#endif /* NXPBUILD__PHHAL_HW_PN76XX_LPCD_CALIBRATE_ONCE */
#endif /* DEBUG */
return PH_ERR_SUCCESS;
}
/* Perform LPCD Calibration */
phStatus_t Calibrate_LPCD(uint32_t dwLPCDDemo, uint32_t *pdwLPCDRefValue)
{
phStatus_t wStatus = PH_ERR_SUCCESS;
/* Software LPCD Calibration */
wStatus = SW_LPCD_Calib(pdwLPCDRefValue);
if(wStatus == PH_ERR_SUCCESS)
{
DEBUG_PRINTF("\nSW LPCD Calibration Successful. ");
}
else
{
DEBUG_PRINTF("\nSW LPCD Calibration Failed. ");
}
return wStatus;
}
/**
* With previous LPCD Calibration value, perform LPCD Detection cycle.
*/
phStatus_t DemoLPCD(uint32_t dwLPCDDemo, uint32_t dwLPCDRefValue, uint16_t wLPCDWakeUpTime)
{
phStatus_t wStatus = PH_ERR_SUCCESS;
/* SW LPCD Demo */
wStatus = SW_LPCD_Demo(dwLPCDRefValue, wLPCDWakeUpTime);
if(wStatus == PH_ERR_SUCCESS)
{
DEBUG_PRINTF("\n!!!!!!!!!!!!!!!!!!!!!!!!!SW LPCD Exited due to Load Change.!!!!!!!!!!!!!!!!!!!!!!!!!\n\n");
}
DEBUG_PRINTF("\n---------------Restart to try another option.---------------\n\n");
return wStatus;
}
#endif /* NXPBUILD__PHHAL_HW_PN76XX */

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@ -0,0 +1,195 @@
/*----------------------------------------------------------------------------*/
/* Copyright 2020 - 2022 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may only */
/* be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that you */
/* have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*----------------------------------------------------------------------------*/
/** \file
* Example Source header for NfcrdlibEx6_LPCD.
* This application will configure Reader Library to provide demo on LPCD functionality of RC663 Reader IC's.
* Please refer Readme.txt file for Hardware Pin Configuration, Software Configuration and steps to build and
* execute the project which is present in the same project directory.
*
* $Author$
* $Revision$ (v07.10.00)
* $Date$
*/
#include <NfcrdlibEx6_LPCD.h>
#ifdef NXPBUILD__PHHAL_HW_RC663
#include <phApp_Init.h>
#include "BoardSelection.h"
#define NXPBUILD__PHHAL_HW_RC663_LPCD_CALIBRATE_ONCE
#define NXPBUILD__PHHAL_HW_RC663_LPCD_ENABLE_USER_OPTION
/*******************************************************************************
** Global Variable Declaration
*******************************************************************************/
phbalReg_Type_t sBalParams;
phhalHw_Rc663_DataParams_t * pHal;
/*******************************************************************************
** Global Defines
*******************************************************************************/
#define PHHAL_HW_CLRC663PLUS_VERSION 0x1AU /**< Version of RC66303 (RC663 Plus). Refer VERSION Register (Address : 0x7F) for more information. */
/*******************************************************************************
** Function Declarations
*******************************************************************************/
void CLIF_IRQHandler(void);
/*******************************************************************************
** Function Definitions
*******************************************************************************/
uint32_t dwLPCDCalibrateOption = 1;
uint32_t dwLPCDDemoOption = 1;
uint32_t dwLPCDRefValue;
phStatus_t Configure_LPCD(uint32_t *pdwLPCDCalibrateOption, uint32_t *pdwLPCDDemoOption)
{
#ifdef DEBUG
uint32_t dwScanOption = 1;
#ifdef NXPBUILD__PHHAL_HW_RC663_LPCD_ENABLE_USER_OPTION
/* Prompt user to either select SW LPCD or ULPCD */
DEBUG_PRINTF("\nChoose below LPCD Demo Option ");
DEBUG_PRINTF("\nLPCD with calibration always => 1 ");
DEBUG_PRINTF("\nLPCD with calibration once => 2 ");
DEBUG_PRINTF("\nEnter LPCD Demo Option : ");
DEBUG_SCAN("%X",&dwScanOption);
#endif /* NXPBUILD__PHHAL_HW_RC663_LPCD_ENABLE_USER_OPTION */
*pdwLPCDCalibrateOption = dwScanOption;
*pdwLPCDDemoOption = 0;
#else /* DEBUG */
#ifdef NXPBUILD__PHHAL_HW_RC663_LPCD_CALIBRATE_ONCE
/* Calibration Once before first LPCD Cycle */
*pdwLPCDCalibrateOption = 0x02U;
#else
/* Calibration before every LPCD Cycle */
*pdwLPCDCalibrateOption = 0x01U;
#endif /* NXPBUILD__PHHAL_HW_RC663_LPCD_CALIBRATE_ONCE */
#endif /* DEBUG */
return PH_ERR_SUCCESS;
}
/* Perform LPCD Calibration */
phStatus_t Calibrate_LPCD(uint32_t dwLPCDDemo, uint32_t *pdwLPCDRefValue)
{
phStatus_t wStatus;
uint8_t bValueI = 0;
uint8_t bValueQ = 0;
uint8_t bVersion = 0;
uint8_t bDigitalFilter = PH_ON;
uint16_t wDetectionOption = PHHAL_HW_RC663_FILTER_OPTION1;
uint16_t wPowerDownTimeMs = LPCD_POWERDOWN_TIME;
uint16_t wDetectionTimeUs = LPCD_FIELD_ON_DURATION;
/* Configure the LPCD Mode Default to perform LPCD Calibration cycle.
* Provide Input Reference I and Q value of Zero and provide the Detection time to
* turn ON RF for this duration to measure the Load change using I and Q Channel Values.
* Configure suitable Power Down time to save power consumed by RC663 Reader IC. */
wStatus = phhalHw_Rc663_Cmd_Lpcd_SetConfig(pHal, PHHAL_HW_RC663_CMD_LPCD_MODE_DEFAULT,
bValueI, bValueQ, wPowerDownTimeMs, wDetectionTimeUs);
CHECK_STATUS(wStatus);
/* Read the Version register to differentiate between RC663 Old(RC66301, RC66302) and RC663 Plus (RC66303). */
wStatus = phhalHw_Rc663_ReadRegister(pHal, PHHAL_HW_RC663_REG_VERSION, &bVersion);
CHECK_STATUS(wStatus);
if (bVersion == PHHAL_HW_CLRC663PLUS_VERSION)
{
/* Configure the Charge Pump to have high detection range.
* Enabling the charge pump increases the power level during the detection phase increasing
* the detection range. This leads to increase in average current consumption. */
wStatus = phhalHw_SetConfig(pHal, PHHAL_HW_RC663_CONFIG_LPCD_CHARGEPUMP, PH_ON);
CHECK_STATUS(wStatus);
/* Configuring the Digital Filter triggers the RC663 Plus algorithm to get average of multiple
* samples to detect change in I and Q values. This increases the RF ON time duration in turn
* increasing the average current consumption. */
wStatus = phhalHw_SetConfig(pHal, PHHAL_HW_RC663_CONFIG_LPCD_FILTER,
((uint16_t)(bDigitalFilter) | wDetectionOption));
CHECK_STATUS(wStatus);
}
/* Perform LPCD Calibration cycle and get the LPCD reference I and Q Values. */
wStatus = phhalHw_Rc663_Cmd_Lpcd_GetConfig(pHal, &bValueI, &bValueQ);
CHECK_STATUS(wStatus);
*pdwLPCDRefValue = ((bValueI) | (bValueQ << 0x8));
DEBUG_PRINTF("\nLPCD Calibration Successful. ");
return PH_ERR_SUCCESS;
}
/**
*/
phStatus_t DemoLPCD(uint32_t dwLPCDDemo, uint32_t dwLPCDRefValue, uint16_t wLPCDWakeUpTime)
{
phStatus_t wStatus = PH_ERR_SUCCESS;
uint16_t wPowerDownTimeMs = wLPCDWakeUpTime;
uint16_t wDetectionTimeUs = LPCD_FIELD_ON_DURATION;
uint8_t bValueI, bValueQ;
bValueI = (dwLPCDRefValue & 0xFF);
bValueQ = ((dwLPCDRefValue >> 0x8) & 0xFF);
/* Configure the LPCD Mode Powerdown mode to perform LPCD detection cycle.
* Provide Input Reference I and Q value either obtained using previous LPCD Calibration phase
* or provided by use.
* Provide the Detection time to turn ON RF for this duration to measure the
* Load change using I and Q Channel Values.
* Configure suitable Power Down time to save power consumed by RC663 Reader IC. */
wStatus = phhalHw_Rc663_Cmd_Lpcd_SetConfig(pHal, PHHAL_HW_RC663_CMD_LPCD_MODE_POWERDOWN,
bValueI, bValueQ, wPowerDownTimeMs, wDetectionTimeUs);
CHECK_STATUS(wStatus);
/* Perform LPCD Detection Cycle */
wStatus = phhalHw_Lpcd(pHal);
if(wStatus == PH_ERR_SUCCESS)
{
DEBUG_PRINTF("\n!!!!!!!!!!!!!!!!!!!!!!!!!LPCD Exited due to Load Change.!!!!!!!!!!!!!!!!!!!!!!!!!\n\n");
}
else
{
DEBUG_PRINTF("\n!!!!!!!!!!!!!!!!!!!!!!!!!LPCD Exited due to issue.!!!!!!!!!!!!!!!!!!!!!!!!!\n\n");
}
wStatus = phhalHw_Wait(pHal, PHHAL_HW_TIME_MILLISECONDS, 500);
CHECK_STATUS(wStatus);
return wStatus;
}
/*******************************************************************************
** CLIF ISR Handler
*******************************************************************************/
void CLIF_IRQHandler(void)
{
/* Read the interrupt status of external interrupt attached to the reader IC IRQ pin */
if (phDriver_PinRead(PHDRIVER_PIN_IRQ, PH_DRIVER_PINFUNC_INTERRUPT))
{
phDriver_PinClearIntStatus(PHDRIVER_PIN_IRQ);
/* Call application registered callback. */
if (pHal->pRFISRCallback != NULL)
{
pHal->pRFISRCallback(pHal);
}
}
}
#endif /* NXPBUILD__PHHAL_HW_RC663 */

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/*----------------------------------------------------------------------------*/
/* Copyright 2020-2021 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may only */
/* be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that you */
/* have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*----------------------------------------------------------------------------*/
/** \file
* Example Source abstracting component data structure and code initialization and code specific to HW used in the examples
* This file shall be present in all examples. A customer does not need to touch/modify this file. This file
* purely depends on the phNxpBuild_Lpc.h or phNxpBuild_App.h
* The phAppInit.h externs the component data structures initialized here that is in turn included by the core examples.
* The core example shall not use any other variable defined here except the RdLib component data structures(as explained above)
* The RdLib component initialization requires some user defined data and function pointers.
* These are defined in the respective examples and externed here.
*
* Keystore and Crypto initialization needs to be handled by application.
*
* $Author$
* $Revision$ (v07.10.00)
* $Date$
*
*/
#include "phApp_Init.h"
#include <phOsal.h>
/*******************************************************************************
** Function Declarations
*******************************************************************************/
/*******************************************************************************
** Function Definitions
*******************************************************************************/
/* Print technology being resolved */
void phApp_PrintTech(uint8_t TechType)
{
switch(TechType)
{
case PHAC_DISCLOOP_POS_BIT_MASK_A:
DEBUG_PRINTF ("\tResolving Type A... \n");
break;
case PHAC_DISCLOOP_POS_BIT_MASK_B:
DEBUG_PRINTF ("\tResolving Type B... \n");
break;
case PHAC_DISCLOOP_POS_BIT_MASK_F212:
DEBUG_PRINTF ("\tResolving Type F with baud rate 212... \n");
break;
case PHAC_DISCLOOP_POS_BIT_MASK_F424:
DEBUG_PRINTF ("\tResolving Type F with baud rate 424... \n");
break;
case PHAC_DISCLOOP_POS_BIT_MASK_V:
DEBUG_PRINTF ("\tResolving Type V... \n");
break;
default:
break;
}
}
/**
* This function will print buffer content
* \param *pBuff Buffer Reference
* \param num data size to be print
*/
void phApp_Print_Buff(uint8_t *pBuff, uint8_t num)
{
uint32_t i;
for(i = 0; i < num; i++)
{
DEBUG_PRINTF(" %02X",pBuff[i]);
}
}
/**
* This function will print Tag information
* \param pDataParams The discovery loop data parameters
* \param wNumberOfTags Total number of tags detected
* \param wTagsDetected Technology Detected
*/
void phApp_PrintTagInfo(phacDiscLoop_Sw_DataParams_t *pDataParams, uint16_t wNumberOfTags, uint16_t wTagsDetected)
{
#if defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_TAGS) || \
defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_P2P_ACTIVE) || \
defined(NXPBUILD__PHAC_DISCLOOP_TYPEB_TAGS) || \
defined(NXPBUILD__PHAC_DISCLOOP_TYPEF_TAGS) || \
defined(NXPBUILD__PHAC_DISCLOOP_TYPEV_TAGS) || \
defined(NXPBUILD__PHAC_DISCLOOP_I18000P3M3_TAGS)
uint8_t bIndex;
#endif
#if defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_TAGS) || defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_P2P_ACTIVE)
uint8_t bTagType;
#endif
#if defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_TAGS) || defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_P2P_ACTIVE)
if (PHAC_DISCLOOP_CHECK_ANDMASK(wTagsDetected, PHAC_DISCLOOP_POS_BIT_MASK_A))
{
if(pDataParams->sTypeATargetInfo.bT1TFlag)
{
DEBUG_PRINTF("\tTechnology : Type A");
DEBUG_PRINTF ("\n\t\tUID :");
phApp_Print_Buff( pDataParams->sTypeATargetInfo.aTypeA_I3P3[0].aUid,
pDataParams->sTypeATargetInfo.aTypeA_I3P3[0].bUidSize);
DEBUG_PRINTF ("\n\t\tSAK : 0x%02x",pDataParams->sTypeATargetInfo.aTypeA_I3P3[0].aSak);
DEBUG_PRINTF ("\n\t\tType: Type 1 Tag\n");
}
else
{
DEBUG_PRINTF("\tTechnology : Type A");
for(bIndex = 0; bIndex < wNumberOfTags; bIndex++)
{
DEBUG_PRINTF ("\n\t\tCard: %d",bIndex + 1);
DEBUG_PRINTF ("\n\t\tUID :");
phApp_Print_Buff( pDataParams->sTypeATargetInfo.aTypeA_I3P3[bIndex].aUid,
pDataParams->sTypeATargetInfo.aTypeA_I3P3[bIndex].bUidSize);
DEBUG_PRINTF ("\n\t\tSAK : 0x%02x",pDataParams->sTypeATargetInfo.aTypeA_I3P3[bIndex].aSak);
if ((pDataParams->sTypeATargetInfo.aTypeA_I3P3[bIndex].aSak & (uint8_t) ~0xFB) == 0)
{
/* Bit b3 is set to zero, [Digital] 4.8.2 */
/* Mask out all other bits except for b7 and b6 */
bTagType = (pDataParams->sTypeATargetInfo.aTypeA_I3P3[bIndex].aSak & 0x60);
bTagType = bTagType >> 5;
switch(bTagType)
{
case PHAC_DISCLOOP_TYPEA_TYPE2_TAG_CONFIG_MASK:
DEBUG_PRINTF ("\n\t\tType: Type 2 Tag\n");
break;
case PHAC_DISCLOOP_TYPEA_TYPE4A_TAG_CONFIG_MASK:
DEBUG_PRINTF ("\n\t\tType: Type 4A Tag\n");
break;
case PHAC_DISCLOOP_TYPEA_TYPE_NFC_DEP_TAG_CONFIG_MASK:
DEBUG_PRINTF ("\n\t\tType: P2P\n");
break;
case PHAC_DISCLOOP_TYPEA_TYPE_NFC_DEP_TYPE4A_TAG_CONFIG_MASK:
DEBUG_PRINTF ("\n\t\tType: Type NFC_DEP and 4A Tag\n");
break;
default:
break;
}
}
}
}
}
#endif
#ifdef NXPBUILD__PHAC_DISCLOOP_TYPEB_TAGS
if (PHAC_DISCLOOP_CHECK_ANDMASK(wTagsDetected, PHAC_DISCLOOP_POS_BIT_MASK_B))
{
DEBUG_PRINTF("\tTechnology : Type B");
/* Loop through all the Type B tags detected and print the Pupi */
for (bIndex = 0; bIndex < wNumberOfTags; bIndex++)
{
DEBUG_PRINTF ("\n\t\tCard: %d",bIndex + 1);
DEBUG_PRINTF ("\n\t\tUID :");
/* PUPI Length is always 4 bytes */
phApp_Print_Buff( pDataParams->sTypeBTargetInfo.aTypeB_I3P3[bIndex].aPupi, 0x04);
}
DEBUG_PRINTF("\n");
}
#endif /* NXPBUILD__PHAC_DISCLOOP_TYPEB_TAGS */
#ifdef NXPBUILD__PHAC_DISCLOOP_TYPEF_TAGS
if( PHAC_DISCLOOP_CHECK_ANDMASK(wTagsDetected, PHAC_DISCLOOP_POS_BIT_MASK_F212) ||
PHAC_DISCLOOP_CHECK_ANDMASK(wTagsDetected, PHAC_DISCLOOP_POS_BIT_MASK_F424))
{
DEBUG_PRINTF("\tTechnology : Type F");
/* Loop through all the type F tags and print the IDm */
for (bIndex = 0; bIndex < wNumberOfTags; bIndex++)
{
DEBUG_PRINTF ("\n\t\tCard: %d",bIndex + 1);
DEBUG_PRINTF ("\n\t\tUID :");
phApp_Print_Buff( pDataParams->sTypeFTargetInfo.aTypeFTag[bIndex].aIDmPMm,
PHAC_DISCLOOP_FELICA_IDM_LENGTH );
if ((pDataParams->sTypeFTargetInfo.aTypeFTag[bIndex].aIDmPMm[0] == 0x01) &&
(pDataParams->sTypeFTargetInfo.aTypeFTag[bIndex].aIDmPMm[1] == 0xFE))
{
/* This is Type F tag with P2P capabilities */
DEBUG_PRINTF ("\n\t\tType: P2P");
}
else
{
/* This is Type F T3T tag */
DEBUG_PRINTF ("\n\t\tType: Type 3 Tag");
}
if(pDataParams->sTypeFTargetInfo.aTypeFTag[bIndex].bBaud != PHAC_DISCLOOP_CON_BITR_212)
{
DEBUG_PRINTF ("\n\t\tBit Rate: 424\n");
}
else
{
DEBUG_PRINTF ("\n\t\tBit Rate: 212\n");
}
}
}
#endif /* NXPBUILD__PHAC_DISCLOOP_TYPEF_TAGS */
#ifdef NXPBUILD__PHAC_DISCLOOP_TYPEV_TAGS
if (PHAC_DISCLOOP_CHECK_ANDMASK(wTagsDetected, PHAC_DISCLOOP_POS_BIT_MASK_V))
{
DEBUG_PRINTF("\tTechnology : Type V / ISO 15693 / T5T");
/* Loop through all the Type V tags detected and print the UIDs */
for (bIndex = 0; bIndex < wNumberOfTags; bIndex++)
{
DEBUG_PRINTF ("\n\t\tCard: %d",bIndex + 1);
DEBUG_PRINTF ("\n\t\tUID :");
phApp_Print_Buff( pDataParams->sTypeVTargetInfo.aTypeV[bIndex].aUid, 0x08);
}
DEBUG_PRINTF("\n");
}
#endif /* NXPBUILD__PHAC_DISCLOOP_TYPEV_TAGS */
#ifdef NXPBUILD__PHAC_DISCLOOP_I18000P3M3_TAGS
if (PHAC_DISCLOOP_CHECK_ANDMASK(wTagsDetected, PHAC_DISCLOOP_POS_BIT_MASK_18000P3M3))
{
DEBUG_PRINTF("\tTechnology : ISO 18000p3m3 / EPC Gen2");
/* Loop through all the 18000p3m3 tags detected and print the UII */
for (bIndex = 0; bIndex < wNumberOfTags; bIndex++)
{
DEBUG_PRINTF("\n\t\tCard: %d",bIndex + 1);
DEBUG_PRINTF("\n\t\tUII :");
phApp_Print_Buff(
pDataParams->sI18000p3m3TargetInfo.aI18000p3m3[bIndex].aUii,
(pDataParams->sI18000p3m3TargetInfo.aI18000p3m3[bIndex].wUiiLength / 8));
}
DEBUG_PRINTF("\n");
}
#endif /* NXPBUILD__PHAC_DISCLOOP_I18000P3M3_TAGS */
}
/**
* This function will print Error information received from Reader Lib
* \param wStatus Error status
*/
void PrintErrorInfo(phStatus_t wStatus)
{
DEBUG_PRINTF("\n ErrorInfo Comp:");
switch(wStatus & 0xFF00)
{
case PH_COMP_BAL:
DEBUG_PRINTF("\t PH_COMP_BAL");
break;
case PH_COMP_HAL:
DEBUG_PRINTF("\t PH_COMP_HAL");
break;
case PH_COMP_PAL_ISO14443P3A:
DEBUG_PRINTF("\t PH_COMP_PAL_ISO14443P3A");
break;
case PH_COMP_PAL_ISO14443P3B:
DEBUG_PRINTF("\t PH_COMP_PAL_ISO14443P3B");
break;
case PH_COMP_PAL_ISO14443P4A:
DEBUG_PRINTF("\t PH_COMP_PAL_ISO14443P4A");
break;
case PH_COMP_PAL_ISO14443P4:
DEBUG_PRINTF("\t PH_COMP_PAL_ISO14443P4");
break;
case PH_COMP_PAL_FELICA:
DEBUG_PRINTF("\t PH_COMP_PAL_FELICA");
break;
case PH_COMP_PAL_EPCUID:
DEBUG_PRINTF("\t PH_COMP_PAL_EPCUID");
break;
case PH_COMP_PAL_SLI15693:
DEBUG_PRINTF("\t PH_COMP_PAL_SLI15693");
break;
case PH_COMP_PAL_I18000P3M3:
DEBUG_PRINTF("\t PH_COMP_PAL_I18000P3M3");
break;
case PH_COMP_PAL_I18092MPI:
DEBUG_PRINTF("\t PH_COMP_PAL_I18092MPI");
break;
case PH_COMP_PAL_I18092MT:
DEBUG_PRINTF("\t PH_COMP_PAL_I18092MT");
break;
case PH_COMP_PAL_I14443P4MC:
DEBUG_PRINTF("\t PH_COMP_PAL_I14443P4MC");
break;
case PH_COMP_AC_DISCLOOP:
DEBUG_PRINTF("\t PH_COMP_AC_DISCLOOP");
break;
case PH_COMP_OSAL:
DEBUG_PRINTF("\t PH_COMP_OSAL");
break;
default:
DEBUG_PRINTF("\t 0x%x",(wStatus & PH_COMPID_MASK));
break;
}
DEBUG_PRINTF("\t type:");
switch(wStatus & PH_ERR_MASK)
{
case PH_ERR_SUCCESS_INCOMPLETE_BYTE:
DEBUG_PRINTF("\t PH_ERR_SUCCESS_INCOMPLETE_BYTE");
break;
case PH_ERR_IO_TIMEOUT:
DEBUG_PRINTF("\t PH_ERR_IO_TIMEOUT");
break;
case PH_ERR_INTEGRITY_ERROR:
DEBUG_PRINTF("\t PH_ERR_INTEGRITY_ERROR");
break;
case PH_ERR_COLLISION_ERROR:
DEBUG_PRINTF("\t PH_ERR_COLLISION_ERROR");
break;
case PH_ERR_BUFFER_OVERFLOW:
DEBUG_PRINTF("\t PH_ERR_BUFFER_OVERFLOW");
break;
case PH_ERR_FRAMING_ERROR:
DEBUG_PRINTF("\t PH_ERR_FRAMING_ERROR");
break;
case PH_ERR_PROTOCOL_ERROR:
DEBUG_PRINTF("\t PH_ERR_PROTOCOL_ERROR");
break;
case PH_ERR_RF_ERROR:
DEBUG_PRINTF("\t PH_ERR_RF_ERROR");
break;
case PH_ERR_EXT_RF_ERROR:
DEBUG_PRINTF("\t PH_ERR_EXT_RF_ERROR");
break;
case PH_ERR_NOISE_ERROR:
DEBUG_PRINTF("\t PH_ERR_NOISE_ERROR");
break;
case PH_ERR_ABORTED:
DEBUG_PRINTF("\t PH_ERR_ABORTED");
break;
case PH_ERR_INTERNAL_ERROR:
DEBUG_PRINTF("\t PH_ERR_INTERNAL_ERROR");
break;
case PH_ERR_INVALID_DATA_PARAMS:
DEBUG_PRINTF("\t PH_ERR_INVALID_DATA_PARAMS");
break;
case PH_ERR_INVALID_PARAMETER:
DEBUG_PRINTF("\t PH_ERR_INVALID_PARAMETER");
break;
case PH_ERR_PARAMETER_OVERFLOW:
DEBUG_PRINTF("\t PH_ERR_PARAMETER_OVERFLOW");
break;
case PH_ERR_UNSUPPORTED_PARAMETER:
DEBUG_PRINTF("\t PH_ERR_UNSUPPORTED_PARAMETER");
break;
case PH_ERR_OSAL_ERROR:
DEBUG_PRINTF("\t PH_ERR_OSAL_ERROR");
break;
case PHAC_DISCLOOP_LPCD_NO_TECH_DETECTED:
DEBUG_PRINTF("\t PHAC_DISCLOOP_LPCD_NO_TECH_DETECTED");
break;
case PHAC_DISCLOOP_COLLISION_PENDING:
DEBUG_PRINTF("\t PHAC_DISCLOOP_COLLISION_PENDING");
break;
default:
DEBUG_PRINTF("\t 0x%x",(wStatus & PH_ERR_MASK));
break;
}
}
/******************************************************************************
** End Of File
******************************************************************************/

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/*----------------------------------------------------------------------------*/
/* Copyright 2016-2022 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may only */
/* be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that you */
/* have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*----------------------------------------------------------------------------*/
/** \file
* Example Source abstracting component data structure and code initialization and code specific to HW used in the examples
* This file shall be present in all examples. A customer does not need to touch/modify this file. This file
* purely depends on the phNxpBuild_Lpc.h or phNxpBuild_App.h
* The phAppInit.h externs the component data structures initialized here that is in turn included by the core examples.
* The core example shall not use any other variable defined here except the RdLib component data structures(as explained above)
* The RdLib component initialization requires some user defined data and function pointers.
* These are defined in the respective examples and externed here.
*
* Keystore and Crypto initialization needs to be handled by application.
*
* $Author$
* $Revision$ (v07.10.00)
* $Date$
*
*/
/* Status header */
#include <ph_Status.h>
#include "phApp_Init.h"
/* LLCP header */
#include <phlnLlcp.h>
#include <phOsal.h>
#ifdef PH_PLATFORM_HAS_ICFRONTEND
#include "BoardSelection.h"
#endif /* PH_PLATFORM_HAS_ICFRONTEND */
#ifdef PHDRIVER_KINETIS_K82
#include <fsl_port.h>
#include <fsl_pit.h>
#ifdef DEBUG
#include <fsl_clock.h>
#endif /* DEBUG */
#endif /* PHDRIVER_KINETIS_K82 */
#ifdef PHDRIVER_KINETIS_K82
#ifdef DEBUG
#define KINETIS_K82_DEBUG_UART_CLK_FREQ CLOCK_GetOsc0ErClkFreq()
#define KINETIS_K82_DEBUG_UART_BASEADDR (uint32_t)(LPUART4)
#define KINETIS_K82_DEBUG_UART_INSTANCE 4U
#define KINETIS_K82_DEBUG_UART_BAUDRATE 115200
#define KINETIS_K82_DEBUG_UART_TYPE DEBUG_CONSOLE_DEVICE_TYPE_LPUART
#endif /* DEBUG */
/*! @brief Clock configuration structure. */
typedef struct _clock_config
{
mcg_config_t mcgConfig; /*!< MCG configuration. */
sim_clock_config_t simConfig; /*!< SIM configuration. */
osc_config_t oscConfig; /*!< OSC configuration. */
uint32_t coreClock; /*!< core clock frequency. */
} clock_config_t;
#endif /* PHDRIVER_KINETIS_K82 */
#ifdef PH_OSAL_LINUX
# define PI_IRQ_POLLING_TASK_PRIO 0
# define PI_IRQ_POLLING_TASK_STACK 0x20000
phOsal_ThreadObj_t gphPiThreadObj;
#endif /* PH_OSAL_LINUX */
#if defined(PHDRIVER_LPC1769) && defined(__CC_ARM)
uint32_t SystemCoreClock;
#endif
/*******************************************************************************
** Function Declarations
*******************************************************************************/
#ifdef PHDRIVER_KINETIS_K82
static void phApp_K82_Init(void);
#endif /* PHDRIVER_KINETIS_K82 */
#ifdef PH_OSAL_LINUX
static void phExample_IrqPolling(void* param);
#endif /* PH_OSAL_LINUX */
phStatus_t phApp_Configure_IRQ();
/*******************************************************************************
** Clock configuration of K82 Platform
*******************************************************************************/
#ifdef PHDRIVER_KINETIS_K82
/* Configuration for enter RUN mode. Core clock = 50MHz. */
const clock_config_t g_defaultClockConfigRun = {
.mcgConfig =
{
.mcgMode = kMCG_ModePEE, /* Work in PEE mode. */
.irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enable. */
.ircs = kMCG_IrcSlow, /* Select IRC32k. */
.fcrdiv = 0U, /* FCRDIV is 0. */
.frdiv = 4U,
.drs = kMCG_DrsLow, /* Low frequency range. */
.dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25%. */
.oscsel = kMCG_OscselOsc, /* Select OSC. */
.pll0Config =
{
.enableMode = 0U, .prdiv = 0x01U, .vdiv = 0x01U,
},
},
.simConfig =
{
.pllFllSel = 1U, /* PLLFLLSEL select PLL. */
.pllFllDiv = 0U, /* PLLFLLSEL clock divider divisor. */
.pllFllFrac = 0U, /* PLLFLLSEL clock divider fraction. */
.er32kSrc = 5U, /* ERCLK32K selection, use RTC. */
.clkdiv1 = 0x01140000U, /* SIM_CLKDIV1. */
},
.oscConfig = {.freq = CPU_XTAL_CLK_HZ,
.capLoad = 0,
.workMode = kOSC_ModeOscLowPower,
.oscerConfig =
{
.enableMode = kOSC_ErClkEnable,
#if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER)
.erclkDiv = 0U,
#endif
}},
};
#endif /* PHDRIVER_KINETIS_K82 */
/*******************************************************************************
** Global Variable Declaration
*******************************************************************************/
#ifdef NXPBUILD__PHLN_LLCP_SW
phlnLlcp_Sw_DataParams_t slnLlcp; /* LLCP component */
#endif /* NXPBUILD__PHLN_LLCP_SW */
/* General information bytes to be sent with ATR Request */
#if defined(NXPBUILD__PHPAL_I18092MPI_SW) || defined(NXPBUILD__PHPAL_I18092MT_SW)
uint8_t aLLCPGeneralBytes[36] = { 0x46,0x66,0x6D,
0x01,0x01,0x10, /*VERSION*/
0x03,0x02,0x00,0x01, /*WKS*/
0x04,0x01,0xF1 /*LTO*/
};
uint8_t bLLCPGBLength = 13;
#endif
/* ATR Response or ATS Response holder */
#if defined(NXPBUILD__PHPAL_I14443P4A_SW) || \
defined(NXPBUILD__PHPAL_I18092MPI_SW)
uint8_t aResponseHolder[64];
#endif
/* prints if error is detected */
#define CHECK_SUCCESS(x) \
if ((x) != PH_ERR_SUCCESS) \
{ \
DEBUG_PRINTF("\nLine: %d Error - (0x%04X) has occurred : 0xCCEE CC-Component ID, EE-Error code. Refer-ph_Status.h\n ", __LINE__, (x)); \
return (x); \
}
/*******************************************************************************
** Function Definitions
*******************************************************************************/
#ifdef PHDRIVER_KINETIS_K82
static void phApp_K82_Init(void)
{
#ifdef DEBUG
uint32_t uartClkSrcFreq;
#endif /* DEBUG */
pit_config_t pitConfig; /* Structure of initialize PIT */
CLOCK_SetSimSafeDivs();
CLOCK_InitOsc0(&g_defaultClockConfigRun.oscConfig);
CLOCK_SetXtal0Freq(CPU_XTAL_CLK_HZ);
CLOCK_BootToPeeMode(g_defaultClockConfigRun.mcgConfig.oscsel, kMCG_PllClkSelPll0,
&g_defaultClockConfigRun.mcgConfig.pll0Config);
CLOCK_SetInternalRefClkConfig(g_defaultClockConfigRun.mcgConfig.irclkEnableMode,
g_defaultClockConfigRun.mcgConfig.ircs, g_defaultClockConfigRun.mcgConfig.fcrdiv);
CLOCK_SetSimConfig(&g_defaultClockConfigRun.simConfig);
SystemCoreClockUpdate();
/*
* pitConfig.enableRunInDebug = false;
*/
PIT_GetDefaultConfig(&pitConfig);
/* Init pit module */
PIT_Init(PIT, &pitConfig);
#ifdef DEBUG
/* Initialize LPUART4 pins below used to Print */
/* Ungate the port clock */
CLOCK_EnableClock(kCLOCK_PortC);
/* Affects PORTC_PCR14 register */
PORT_SetPinMux(PORTC, 14U, kPORT_MuxAlt3);
/* Affects PORTC_PCR15 register */
PORT_SetPinMux(PORTC, 15U, kPORT_MuxAlt3);
/* SIM_SOPT2[27:26]:
* 00: Clock Disabled
* 01: MCGFLLCLK, or MCGPLLCLK, or IRC48M
* 10: OSCERCLK
* 11: MCGIRCCLK
*/
CLOCK_SetLpuartClock(2);
uartClkSrcFreq = KINETIS_K82_DEBUG_UART_CLK_FREQ;
DbgConsole_Init(KINETIS_K82_DEBUG_UART_INSTANCE, KINETIS_K82_DEBUG_UART_BAUDRATE, KINETIS_K82_DEBUG_UART_TYPE, uartClkSrcFreq);
#endif /* DEBUG */
}
#endif /* PHDRIVER_KINETIS_K82 */
#ifdef PH_PLATFORM_HAS_ICFRONTEND
/**
* This function will initialize Host Controller interfaced with NXP Reader IC's.
* Any initialization which is not generic across Platforms, should be done here.
* Note: For NXP NFC Controllers HOST initialization is not required.
*/
void phApp_CPU_Init(void)
{
#if defined PHDRIVER_KINETIS_K82
phApp_K82_Init();
#elif defined(PHDRIVER_LPC1769) && defined(__CC_ARM)
SystemCoreClock = (( unsigned long ) 96000000);
#elif defined(PH_OSAL_LINUX) && defined(NXPBUILD__PHHAL_HW_PN5190)
phStatus_t status;
status = PiGpio_OpenIrq();
if ((status & PH_ERR_MASK) != PH_ERR_SUCCESS)
{
DEBUG_PRINTF("\n PiGpio_OpenIrq failed \n");
DEBUG_PRINTF("\n Couldn't open PN5190 Kernel IRQ Driver.\n Halting here!!FIX IT!!\n");
while(1);
}
#else
/* In case of LPC series, startup file takes care of initializing clock and ports.
* No initialization is required in Linux environment. */
#endif /* PHDRIVER_KINETIS_K82 */
}
#endif /* PH_PLATFORM_HAS_ICFRONTEND */
/**
* This function will initialize Reader LIbrary Component
*/
phStatus_t phApp_Comp_Init(void * pDiscLoopParams)
{
phStatus_t wStatus = PH_ERR_SUCCESS;
#if defined(NXPBUILD__PHPAL_I18092MPI_SW) || defined(NXPBUILD__PHPAL_I18092MT_SW) || \
defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_P2P_TAGS) || defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_P2P_ACTIVE) || \
defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_I3P4_TAGS) || defined(NXPBUILD__PHAC_DISCLOOP_TYPEF_P2P_TAGS) || \
defined(NXPBUILD__PHAC_DISCLOOP_TYPEF212_P2P_ACTIVE) || defined(NXPBUILD__PHAC_DISCLOOP_TYPEF424_P2P_ACTIVE)
phacDiscLoop_Sw_DataParams_t * pDiscLoop = (phacDiscLoop_Sw_DataParams_t *)pDiscLoopParams;
#endif
/* Initialize the LLCP component */
#ifdef NXPBUILD__PHLN_LLCP_SW
slnLlcp.sLocalLMParams.wMiu = 0x00; /* 128 bytes only */
slnLlcp.sLocalLMParams.wWks = 0x11; /* SNEP & LLCP */
slnLlcp.sLocalLMParams.bLto = 100; /* Maximum LTO */
slnLlcp.sLocalLMParams.bOpt = 0x02;
slnLlcp.sLocalLMParams.bAvailableTlv = PHLN_LLCP_TLV_MIUX_MASK | PHLN_LLCP_TLV_WKS_MASK |
PHLN_LLCP_TLV_LTO_MASK | PHLN_LLCP_TLV_OPT_MASK;
wStatus = phlnLlcp_Sw_Init(
&slnLlcp,
sizeof(phlnLlcp_Sw_DataParams_t),
aLLCPGeneralBytes,
&bLLCPGBLength);
#endif /* NXPBUILD__PHLN_LLCP_SW */
#ifdef NXPBUILD__PHAC_DISCLOOP_SW
#if defined(NXPBUILD__PHPAL_I18092MPI_SW) || defined(NXPBUILD__PHPAL_I18092MT_SW)
/* Assign the GI for Type A */
pDiscLoop->sTypeATargetInfo.sTypeA_P2P.pGi = (uint8_t *)aLLCPGeneralBytes;
pDiscLoop->sTypeATargetInfo.sTypeA_P2P.bGiLength = bLLCPGBLength;
/* Assign the GI for Type F */
pDiscLoop->sTypeFTargetInfo.sTypeF_P2P.pGi = (uint8_t *)aLLCPGeneralBytes;
pDiscLoop->sTypeFTargetInfo.sTypeF_P2P.bGiLength = bLLCPGBLength;
#endif
#if defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_P2P_TAGS) || defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_P2P_ACTIVE)
/* Assign ATR response for Type A */
pDiscLoop->sTypeATargetInfo.sTypeA_P2P.pAtrRes = aResponseHolder;
#endif
#if defined(NXPBUILD__PHAC_DISCLOOP_TYPEF_P2P_TAGS) || defined(NXPBUILD__PHAC_DISCLOOP_TYPEF212_P2P_ACTIVE) || \
defined(NXPBUILD__PHAC_DISCLOOP_TYPEF424_P2P_ACTIVE)
/* Assign ATR response for Type F */
pDiscLoop->sTypeFTargetInfo.sTypeF_P2P.pAtrRes = aResponseHolder;
#endif
#ifdef NXPBUILD__PHAC_DISCLOOP_TYPEA_I3P4_TAGS
/* Assign ATS buffer for Type A */
pDiscLoop->sTypeATargetInfo.sTypeA_I3P4.pAts = aResponseHolder;
#endif /* NXPBUILD__PHAC_DISCLOOP_TYPEA_I3P4_TAGS */
#endif /* NXPBUILD__PHAC_DISCLOOP_SW */
return wStatus;
}
phStatus_t phApp_Configure_IRQ()
{
#ifdef PH_OSAL_LINUX
phStatus_t wStatus;
#endif /* PH_OSAL_LINUX */
#ifdef PH_PLATFORM_HAS_ICFRONTEND
#if !(defined(PH_OSAL_LINUX) && defined(NXPBUILD__PHHAL_HW_PN5190))
phDriver_Pin_Config_t pinCfg;
pinCfg.bOutputLogic = PH_DRIVER_SET_LOW;
pinCfg.bPullSelect = PHDRIVER_PIN_IRQ_PULL_CFG;
pinCfg.eInterruptConfig = PIN_IRQ_TRIGGER_TYPE;
phDriver_PinConfig(PHDRIVER_PIN_IRQ, PH_DRIVER_PINFUNC_INTERRUPT, &pinCfg);
#endif
#ifdef PHDRIVER_LPC1769
NVIC_SetPriority(EINT_IRQn, EINT_PRIORITY);
/* Enable interrupt in the NVIC */
NVIC_ClearPendingIRQ(EINT_IRQn);
NVIC_EnableIRQ(EINT_IRQn);
#endif /* PHDRIVER_LPC1769 */
#ifdef PH_OSAL_LINUX
gphPiThreadObj.pTaskName = (uint8_t *) "IrqPolling";
gphPiThreadObj.pStackBuffer = NULL;
gphPiThreadObj.priority = PI_IRQ_POLLING_TASK_PRIO;
gphPiThreadObj.stackSizeInNum = PI_IRQ_POLLING_TASK_STACK;
PH_CHECK_SUCCESS_FCT(wStatus, phOsal_ThreadCreate(&gphPiThreadObj.ThreadHandle, &gphPiThreadObj,
&phExample_IrqPolling, NULL));
#endif /* PH_OSAL_LINUX */
#ifdef PHDRIVER_KINETIS_K82
NVIC_SetPriority(EINT_IRQn, EINT_PRIORITY);
NVIC_ClearPendingIRQ(EINT_IRQn);
EnableIRQ(EINT_IRQn);
#endif /* PHDRIVER_KINETIS_K82 */
#endif /* #ifdef PH_PLATFORM_HAS_ICFRONTEND */
return PH_ERR_SUCCESS;
}
#ifdef PH_OSAL_LINUX
/*
* \brief: The purpose of this Thread is to detect RF signal from an External Peer .
*/
static void phExample_IrqPolling(void* param)
{
uint8_t bgpioVal = 0;
uint8_t bhighOrLow = 0;
#if defined(NXPBUILD__PHHAL_HW_RC663) || defined(NXPBUILD__PHHAL_HW_PN5180)
if(PIN_IRQ_TRIGGER_TYPE == PH_DRIVER_INTERRUPT_RISINGEDGE)
{
bhighOrLow = 1;
}
while(PiGpio_read(PHDRIVER_PIN_IRQ, &bgpioVal) != PH_ERR_SUCCESS)
{
PiGpio_unexport(PHDRIVER_PIN_IRQ);
PiGpio_export(PHDRIVER_PIN_IRQ);
PiGpio_set_direction(PHDRIVER_PIN_IRQ, false);
if(PIN_IRQ_TRIGGER_TYPE == PH_DRIVER_INTERRUPT_RISINGEDGE)
{
PiGpio_set_edge(PHDRIVER_PIN_IRQ, true, false);
}
else
{
PiGpio_set_edge(PHDRIVER_PIN_IRQ, false, true);
}
}
/* Initial status: If pin is already Active, post an event. */
if(bgpioVal == bhighOrLow)
{
CLIF_IRQHandler();
}
#endif
while(1)
{
/* Block forever for Raising Edge in PHDRIVER_PIN_IRQ. */
#if defined(NXPBUILD__PHHAL_HW_RC663) || defined(NXPBUILD__PHHAL_HW_PN5180)
if(PiGpio_poll(PHDRIVER_PIN_IRQ, bhighOrLow, -1) == PH_ERR_SUCCESS)
#elif defined(NXPBUILD__PHHAL_HW_PN5190)
if(PiGpio_Irq() == PH_ERR_SUCCESS)
#endif
{
CLIF_IRQHandler();
}
else
{
PiGpio_unexport(PHDRIVER_PIN_IRQ);
PiGpio_export(PHDRIVER_PIN_IRQ);
PiGpio_set_direction(PHDRIVER_PIN_IRQ, false);
if(PIN_IRQ_TRIGGER_TYPE == PH_DRIVER_INTERRUPT_RISINGEDGE)
{
PiGpio_set_edge(PHDRIVER_PIN_IRQ, true, false);
}
else
{
PiGpio_set_edge(PHDRIVER_PIN_IRQ, false, true);
}
}
}
}
#endif /* PH_OSAL_LINUX */
/******************************************************************************
** End Of File
******************************************************************************/

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PROJECT(NfcrdlibEx8_HCE_T4T)
FILE(GLOB NfcrdlibEx8_HCE_T4T_Sources
*.c
src/*.c
)
include_directories(
intfs
types
)
ADD_EXECUTABLE(NfcrdlibEx8_HCE_T4T
${NfcrdlibEx8_HCE_T4T_Sources}
)
TARGET_LINK_LIBRARIES(
NfcrdlibEx8_HCE_T4T
phOsal
DAL
NxpRdLib_acDiscLoop
NxpRdLib_halHw
NxpRdLib_KeyStore
NxpRdLib_phTools
NxpRdLib_palFelica
NxpRdLib_palI18092mPI
NxpRdLib_palI14443p4a
NxpRdLib_palI14443p4
NxpRdLib_palI14443p4
NxpRdLib_palMifare
NxpRdLib_alFelica
NxpRdLib_alMful
NxpRdLib_alMfdf
NxpRdLib_alT1T
NxpRdLib_alTop
NxpRdLib_alMfc
NxpRdLib_palSli15693
NxpRdLib_palI18000p3m3
NxpRdLib_alICode
NxpRdLib_alI18000p3m3
NxpRdLib_alICode
NxpRdLib_palEpcUid
NxpRdLib_lnLlcp
NxpRdLib_palI14443p4mC
NxpRdLib_palI18092mT
NxpRdLib_ceT4T
NxpRdLib_palEpcUid
NxpRdLib_alMfNtag42XDna
NxpRdLib_phNfcLib
)

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/*----------------------------------------------------------------------------*/
/* Copyright 2016-2023 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may only */
/* be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that you */
/* have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*----------------------------------------------------------------------------*/
/** \file
* NFC Type 4A Card Emulation application.
* $Author: NXP $
* $Revision: $ (v07.10.00)
* $Date: $
*/
/**
* Reader Library Headers
*/
#include <phApp_Init.h>
/* Local headers */
#include "NfcrdlibEx8_HCE_T4T.h"
#ifdef NXPBUILD__PHHAL_HW_PN7462AU
#include "phhalRng.h"
#endif /* NXPBUILD__PHHAL_HW_PN7462AU */
/*******************************************************************************
** Definitions
*******************************************************************************/
#ifdef NXPBUILD__PHHAL_HW_RC663
# warning "This example is not supported for RC663"
int main() {
DEBUG_PRINTF("This example is not supported for RC663.");
while (1){
}
return 0;
}
/* Actual main defined below has no purpose in this example and hence over-riding it. */
# define main dummy_main
#endif
/* Check if all required reader library layers are enabled. */
#if NXPBUILD_EX8_MANDATORY_LAYERS
phacDiscLoop_Sw_DataParams_t * pDiscLoop; /* Pointer to Discovery loop data-params */
phpalI14443p4mC_Sw_DataParams_t * ppalI14443p4mC; /* Pointer to PAL 14443-4mC data-params */
phceT4T_Sw_DataParams_t * pceT4T; /* Pointer to HCE data-params */
/**
* Parameters for L3 activation during AUTOCOLL (used in
* phhalHw_Rc523_SetListenParameters)
* */
uint8_t sens_res[2] = {0x04, 0x00}; /* ATQ bytes - needed for anti-collision */
uint8_t nfc_id1[3] = {0xA1, 0xA2, 0xA3}; /* UID bytes (one byte defined by HW) */
uint8_t sel_res = 0x20; /* SAK (ISO14443P4 Card) */
uint8_t nfc_id3 = 0xFA; /* NFCID3 byte */
uint8_t poll_res[18] = {0x01, 0xFE, 0xB2, 0xB3, 0xB4, 0xB5,
0xB6, 0xB7, 0xC0, 0xC1, 0xC2, 0xC3,
0xC4, 0xC5, 0xC6, 0xC7, 0x23, 0x45};
#ifdef PHOSAL_FREERTOS_STATIC_MEM_ALLOCATION
uint32_t aRdLibTaskBuffer[RDLIB_TASK_STACK];
uint32_t aHceAppTaskBuffer[APPLICATION_TASK_STACK];
#else /* PHOSAL_FREERTOS_STATIC_MEM_ALLOCATION */
#define aRdLibTaskBuffer NULL
#define aHceAppTaskBuffer NULL
#endif /* PHOSAL_FREERTOS_STATIC_MEM_ALLOCATION */
#ifdef PH_OSAL_FREERTOS
const uint8_t bTaskNameMain[configMAX_TASK_NAME_LEN] = {"RdLib"};
const uint8_t bTaskNameHce[configMAX_TASK_NAME_LEN] = {"HceApp"};
#else
const uint8_t bTaskNameMain[] = {"RdLib"};
const uint8_t bTaskNameHce[] = {"HceApp"};
#endif /* PH_OSAL_FREERTOS */
const phOsal_TimerPeriodObj_t abs_timeout= {OS_TIMER_UNIT_MSEC, PHOSAL_MAX_DELAY};
static volatile uint8_t bInfLoop = 1U;
/**
* Parameters for PAL 14443p4mC ATS configuration (Activation).
* Refer phpalI14443p4mC_Activate for more info.
* Used in listen mode / card emulation.
* */
uint8_t aAtsRes[5] = {0x05, 0x75, 0x00, 0x88, 0x00}; /* ATS Response send for
* RATS: |TL|T0|TA|TB|TC|
*/
uint16_t wAtsLength = 5; /* ATS length */
/**
* Parameters for T4T CE (card emulation layer)
* */
/* Mandatory Capability Container (CC) file. It's set using
* phceT4T_SetElementaryFile. */
uint8_t aCcFile[23] = {0};
/* Mandatory NDEF file. It's set using phceT4T_SetElementaryFile. */
uint8_t aNdefFile[1024] = {0x00, 0x0C, 0xD1, 0x01, 0x08, 0x55, 0x02,
0x6E, 0x78, 0x70, 0x2E, 0x63, 0x6F, 0x6D};
#ifdef NXPBUILD__PHCE_T4T_PROPRIETARY
/* Optional proprietary file (not used in this example. Added to demonstrate
* support). It's set using phceT4T_SetElementaryFile. */
uint8_t aProprietaryFile[100] = {0};
#endif /* NXPBUILD__PHCE_T4T_PROPRIETARY */
/**
* RTOS objects.
* Semaphores for synchronization between application thread and reader library
* thread.
* */
phOsal_SemObj_t appstart; /* Used to synchronize start of one
cycle of application processing */
phOsal_SemObj_t appexit; /* Used to synchronize end of one
cycle of application processing */
#if ISO_10373_6_PICC_TEST_BENCH
phOsal_SemObj_t timerwtx; /* Used in PICC ISO 10373-6 test bench
to create WTX */
#endif /* ISO_10373_6_PICC_TEST_BENCH */
#endif /* NXPBUILD_EX8_MANDATORY_LAYERS */
/*******************************************************************************
** Prototypes
*******************************************************************************/
void pWtoxCallBck(void);
/*******************************************************************************
** Code
*******************************************************************************/
int main(void)
{
do
{
#if NXPBUILD_EX8_MANDATORY_LAYERS
phStatus_t status = PH_ERR_INTERNAL_ERROR;
phNfcLib_Status_t dwStatus;
phNfcLib_AppContext_t AppContext = {0};
phOsal_ThreadObj_t RdLib;
/* Perform Controller specific initialization. */
phApp_CPU_Init();
/* Perform OSAL Initialization. */
(void)phOsal_Init();
#ifdef PH_PLATFORM_HAS_ICFRONTEND
status = phbalReg_Init(&sBalParams, sizeof(phbalReg_Type_t));
CHECK_STATUS(status);
AppContext.pBalDataparams = &sBalParams;
#endif /* PH_PLATFORM_HAS_ICFRONTEND */
AppContext.pWtxCallback = (void *)pWtoxCallBck;
dwStatus = phNfcLib_SetContext(&AppContext);
CHECK_NFCLIB_STATUS(dwStatus);
/* Initialize library */
dwStatus = phNfcLib_Init();
CHECK_NFCLIB_STATUS(dwStatus);
if(dwStatus != PH_NFCLIB_STATUS_SUCCESS) break;
/* Set the generic pointer */
pHal = phNfcLib_GetDataParams(PH_COMP_HAL);
pDiscLoop = (phacDiscLoop_Sw_DataParams_t *) phNfcLib_GetDataParams(PH_COMP_AC_DISCLOOP);
ppalI14443p4mC = (phpalI14443p4mC_Sw_DataParams_t *) phNfcLib_GetDataParams(PH_COMP_PAL_I14443P4MC);
pceT4T = (phceT4T_Sw_DataParams_t *) phNfcLib_GetDataParams(PH_COMP_CE_T4T);
/* Initialize other components that are not initialized by NFCLIB and configure Discovery Loop. */
status = phApp_Comp_Init(pDiscLoop);
CHECK_STATUS(status);
if(status != PH_ERR_SUCCESS) break;
/* Perform Platform Init */
status = phApp_Configure_IRQ();
CHECK_STATUS(status);
if(status != PH_ERR_SUCCESS) break;
/* Initialize/Configure components required by this Example */
phApp_Initialize();
DEBUG_PRINTF("\nCard Emulation Application...\n");
RdLib.pTaskName = (uint8_t *)bTaskNameMain;
RdLib.pStackBuffer = aRdLibTaskBuffer;
RdLib.priority = RDLIB_TASK_PRIO;
RdLib.stackSizeInNum = RDLIB_TASK_STACK;
phOsal_ThreadCreate(&RdLib.ThreadHandle, &RdLib, &TReaderLibrary, NULL);
phOsal_ThreadObj_t HceApp;
/* Create application thread (to handle UPDATE_BINARY and proprietary
* commands) */
HceApp.pTaskName = (uint8_t *)bTaskNameHce;
HceApp.pStackBuffer = aHceAppTaskBuffer;
HceApp.priority = APPLICATION_TASK_PRIO;
HceApp.stackSizeInNum = APPLICATION_TASK_STACK;
phOsal_ThreadCreate(&HceApp.ThreadHandle, &HceApp, &TApplication, NULL);
phOsal_StartScheduler();
/* Scheduler exit hook */
ERROR_CRITICAL("Error...Scheduler exited...\n");
#else /* NXPBUILD_EX8_MANDATORY_LAYERS */
DEBUG_PRINTF("\n\tERROR: Missing required reader library components in build...");
#endif /* NXPBUILD_EX8_MANDATORY_LAYERS */
} while(0);
while(bInfLoop); /* Comes here if initialization failure or scheduler exit due to error */
return 0;
}
#if NXPBUILD_EX8_MANDATORY_LAYERS
/**
* Reader library thread. This is the main thread which starts discovery loop
* in listen mode and poll mode (one at a time) and manages switching between
* both listen and poll modes.
* */
void TReaderLibrary(
void *pParams
)
{
phStatus_t status;
/* This call shall allocate secure context before calling any secure function,
* when FreeRtos trust zone is enabled.
* */
phOsal_ThreadSecureStack( 512 );
PRINT_INFO("Reader Library thread started...\n");
/* Configure target mode HAL parameters */
status = phApp_HALConfigAutoColl();
CHECK_STATUS(status);
/* Be in card emulation mode */
while(bInfLoop)
{
/* T4T Card Emulation mode */
T4TCardEmulation();
}
}
/**
* Do card emulation by starting discovery loop in listen mode and activating
* ISO 14443p4mC.
* This function calls phceT4T_Activate() to do T4T emulation.
* Refer phceT4T_Activate() in phceT4T.h for more info.
* */
void T4TCardEmulation(void)
{
phStatus_t status = 0;
phStatus_t wDiscLoop_status = 0;
#if ISO_10373_6_PICC_TEST_BENCH
#ifdef NXPBUILD__PHHAL_HW_PN7462AU
uint16_t wCMAState = 0;
#endif /* NXPBUILD__PHHAL_HW_PN7462AU */
#endif /* ISO_10373_6_PICC_TEST_BENCH */
/* Start discovery loop in listen mode */
wDiscLoop_status = phacDiscLoop_Run(
pDiscLoop,
PHAC_DISCLOOP_ENTRY_POINT_LISTEN);
if((wDiscLoop_status & PH_ERR_MASK) == PHAC_DISCLOOP_EXTERNAL_RFOFF)
{
/* Reset SLEEP_AF state (Respond to WupA ("52")/ReqA ("26")) as Field
* Off is observed.*/
status = phhalHw_SetConfig(
pHal,
PHHAL_HW_CONFIG_MFHALTED,
PH_OFF);
CHECK_STATUS(status);
#ifdef NXPBUILD__PHHAL_HW_PN7462AU
phhalRng_GenerateRng(&((phhalHw_PN7462AU_DataParams_t*)pDiscLoop->pHalDataParams)->pAutocoll.pNfcId1[0], 3);
#endif /* NXPBUILD__PHHAL_HW_PN7462AU*/
}
if((wDiscLoop_status & PH_ERR_MASK) == PHAC_DISCLOOP_ACTIVATED_BY_PEER)
{
/* Validate RATS and send ATS */
status = phpalI14443p4mC_Activate(
ppalI14443p4mC,
pDiscLoop->sTargetParams.pRxBuffer,
(uint8_t)pDiscLoop->sTargetParams.wRxBufferLen,
aAtsRes,
wAtsLength);
if((status & PH_ERR_MASK) != PH_ERR_SUCCESS)
{
if(status == (PH_COMP_PAL_I14443P4MC | PH_ERR_PROTOCOL_ERROR))
{
/* Invalid RATS: Set to SLEEP_AF state if needed. */
#if ISO_10373_6_PICC_TEST_BENCH
#ifdef NXPBUILD__PHHAL_HW_PN7462AU /* This is required for PN640 for the G.11 test case, where the Card state has to be put to MUTE for scenario */
status = phhalHw_GetConfig(pHal, PHHAL_HW_CONFIG_MFHALTED, &wCMAState);
CHECK_STATUS(status);
status = phhalHw_SetConfig (pHal, PHHAL_HW_CONFIG_MFHALTED, wCMAState);
CHECK_STATUS(status);
#endif /* NXPBUILD__PHHAL_HW_PN7462AU */
#endif /* ISO_10373_6_PICC_TEST_BENCH */
}
else if(status == (PH_COMP_PAL_I14443P4MC | PH_ERR_INVALID_PARAMETER))
{
/* Invalid ATS */
ERROR_CRITICAL("ATS configured is invalid...\n");
}
else
{
DEBUG_ERROR_PRINT(status);
}
}
else
{
/* Trigger AppProcessCmd in Application thread to start */
status = phOsal_SemPost(&appstart.SemHandle, E_OS_SEM_OPT_NONE);
if(status != PH_ERR_SUCCESS)
{
ERROR_CRITICAL("ReaderLibThread: Releasing Semaphore failed...\n");
}
/* Activates HCE. This handles all the main functionalities of
* card emulation...receive request from reader...process
* received request...pass UPDATE BINARY/proprietary commands to
* application thread if enabled...and send the response back
* to reader. */
status = phceT4T_Activate(pceT4T);
if ((status & PH_ERR_MASK) == PH_ERR_SUCCESS_DESELECTED)
{
/* Set SLEEP_AF state (Respond only to WupA ("52"), not to
* ReqA ("26")), so set MFHalted bit. After this setting is
* done "phhalHw_Autocoll" should be called immediately from
* Application so that HAL will know if there is any Field
* reset in "phhalHw_Autocoll" API and reset this setting. */
status = phhalHw_SetConfig(
pHal,
PHHAL_HW_CONFIG_MFHALTED,
PH_ON);
CHECK_STATUS(status);
}
/* Wait for AppProcessCmd in Application thread to exit */
status = phOsal_SemPend(&appexit.SemHandle, abs_timeout);
if(status != PH_ERR_SUCCESS)
{
ERROR_CRITICAL("ReaderLibThread: Getting Semaphore failed...\n");
}
}
/* Reset Reader library layers */
status = phpalI14443p4mC_ResetProtocol(ppalI14443p4mC);
DEBUG_ERROR_PRINT(status);
status = phceT4T_Reset(pceT4T);
DEBUG_ERROR_PRINT(status);
}
status = phOsal_EventClear(
&pceT4T->T4TEventObj.EventHandle,
E_OS_EVENT_OPT_NONE,
(E_PH_OSAL_EVT_RXDATA_AVAILABLE | E_PH_OSAL_EVT_TXDATA_AVAILABLE |
E_PH_OSAL_EVT_ABORT | E_PH_OSAL_EVT_ERROR | E_PH_OSAL_EVT_RTO_TIMEOUT),
NULL);
DEBUG_ERROR_PRINT(status);
}
/**
* Application thread. This calls phceT4T_AppProcessCmd() to handle update
* binary and proprietary commands.
* Refer phceT4T_AppProcessCmd in phceT4T.h for more info.
* APIs which does PAL or HAL exchange should not be called from application
* thread.
* */
void TApplication(
void *pParams
)
{
phStatus_t status;
/* This call shall allocate secure context before calling any secure function,
* when FreeRtos trust zone is enabled.
* */
phOsal_ThreadSecureStack( 100 );
PRINT_INFO("Application thread started...\n");
while(bInfLoop)
{
/* Wait for trigger from reader library thread to start */
status = phOsal_SemPend(&appstart.SemHandle, abs_timeout);
if(status != PH_ERR_SUCCESS)
{
ERROR_CRITICAL("AppThread: Getting Semaphore failed...\n");
}
/* Start Application processing of HCE */
#if USE_APP_CALLBACK
/* Use application callback to handle UPDATE_BINARY and proprietary
* commands. */
status = phceT4T_AppProcessCmd(
pceT4T,
AppProcessCmdCallback);
#else /* USE_APP_CALLBACK */
/* Application callback not used. Proprietary commands are not handled
* (unsupported command is returned as status) and UPDATE BINARY will be
* handled internally by AppProcessCmd. */
status = phceT4T_AppProcessCmd(
pceT4T,
NULL);
#endif /* USE_APP_CALLBACK */
/* Trigger reader library thread about the phceT4T_AppProcessCmd exit */
status = phOsal_SemPost(&appexit.SemHandle, E_OS_SEM_OPT_NONE);
if(status != PH_ERR_SUCCESS)
{
ERROR_CRITICAL("AppThread: Releasing Semaphore failed...\n");
}
}
}
#if USE_APP_CALLBACK
/**
* Application callback to handle UPDATE BINARY and proprietary commands.
* Refer phceT4T_AppCallback_t in phceT4T.h for more info.
* */
phStatus_t AppProcessCmdCallback(
uint8_t bState,
uint16_t wRxOption,
uint8_t *pRxData,
uint16_t wRxDataLen,
uint16_t *pStatusWord,
uint8_t **ppTxData,
uint16_t *pTxDataLen
)
{
phStatus_t status;
uint16_t wSelectedFileId;
uint8_t *pSelectedFile;
uint32_t dwSelectedFileSize;
uint8_t bWriteAccess;
uint32_t dwFileOffset;
#if ISO_10373_6_PICC_TEST_BENCH
phOsal_TimerPeriodObj_t timePeriodToWait;
/* Command to create WTX while running 10373-6 PICC test bench. */
uint8_t aWaitForWtx[4] = {0xDE, 0xAD, 0xFE, 0xED};
#endif /* ISO_10373_6_PICC_TEST_BENCH */
if(bState == PHCE_T4T_STATE_FILE_UPDATE)
{
/* Get Selected file info */
status = phceT4T_GetSelectedFileInfo(
pceT4T,
&wSelectedFileId,
&pSelectedFile,
&dwSelectedFileSize,
&bWriteAccess,
&dwFileOffset);
if((status & PH_ERR_MASK) == PH_ERR_SUCCESS)
{
/* Update file */
(void)memcpy(&pSelectedFile[dwFileOffset], pRxData, wRxDataLen);
/* File update success */
*pStatusWord = 0x9000;
*ppTxData = NULL;
*pTxDataLen = 0;
}
/* This condition shall never come */
else
{
DEBUG_PRINTF("Application Callback: Getting file Info failed...\n");
/* Could not update file */
*pStatusWord = 0x6A82;
*ppTxData = NULL;
*pTxDataLen = 0;
/* Return same error back */
return (status & PH_ERR_MASK);
}
}
else
{
/* ---Do the proprietary command handling here--- */
#if ISO_10373_6_PICC_TEST_BENCH
/* Create WTX while running 10373-6 PICC test bench. Waits for WTX
* timer expire, if received "DEADFEED..." */
if(memcmp(&pRxData[1], aWaitForWtx, 4) == 0)
{
/* Wait for trigger from WTX callback */
timePeriodToWait.unitPeriod = OS_TIMER_UNIT_MSEC;
timePeriodToWait.period = 0xFFFFFFFF;
status = phOsal_SemPend(&timerwtx.SemHandle, timePeriodToWait);
if(status != PH_ERR_SUCCESS)
{
DEBUG_PRINTF("Application Callback: Getting WTX Semaphore failed...\n");
while(bInfLoop);
}
}
#endif /* ISO_10373_6_PICC_TEST_BENCH */
/* No proprietary support */
*pStatusWord = 0x6D00;
*ppTxData = NULL;
*pTxDataLen = 0;
}
return PH_ERR_SUCCESS;
}
#endif /* USE_APP_CALLBACK */
/*
* Initialize/Configure components required by this Example.
*/
void phApp_Initialize(void)
{
phStatus_t status;
int ret;
/* Configure Card Emulation parameters */
status = ConfigureCardEmulation();
if((status & PH_ERR_MASK) != PH_ERR_SUCCESS)
{
ERROR_CRITICAL("Configuring card emulation failed...\n");
}
/* Create semaphore for sync. between threads */
ret = phOsal_SemCreate(&appexit.SemHandle, &appexit, E_OS_SEM_OPT_SIGNALLING_SEM);
if (ret != 0)
{
ERROR_CRITICAL("Semaphore creation failed...\n");
}
/* Create semaphore for sync. between threads */
ret = phOsal_SemCreate(&appstart.SemHandle, &appstart, E_OS_SEM_OPT_SIGNALLING_SEM);
if (ret != 0)
{
ERROR_CRITICAL("Semaphore creation failed...\n");
}
#if ISO_10373_6_PICC_TEST_BENCH
/* Create semaphore for testing WTX */
ret = phOsal_SemCreate(&timerwtx.SemHandle, &timerwtx, E_OS_SEM_OPT_SIGNALLING_SEM);
if(timerwtx.SemHandle == NULL)
{
DEBUG_PRINTF("Semaphore creation failed...\n");
while(bInfLoop);
}
#endif /* ISO_10373_6_PICC_TEST_BENCH */
}
/**
* Configure 14443p4mC and ceT4T parameters.
* */
phStatus_t ConfigureCardEmulation(void)
{
phStatus_t status = PH_ERR_SUCCESS;
uint32_t dwContentLen = 0;
uint8_t aDataBuff[20];
/* Configure CET4T NDEF message mapping version to 2.0, default version is 3.0 */
status = phceT4T_SetConfig(
pceT4T,
PHCE_T4T_CONFIG_VNO,
NXPBUILD_EX8_CET4T_NDEF_VERSION);
CHECK_SUCCESS(status);
/* Set CC File */
status = phceT4T_SetElementaryFile(
pceT4T,
PHCE_T4T_FILE_CC,
aCcFile,
0xE103,
sizeof(aCcFile),
GET_CCFILE_CONTENT_LEN(aCcFile));
CHECK_SUCCESS(status);
dwContentLen = GET_FILE_CONTENT_LEN(aNdefFile);
/* Backup NdefFile buffer */
(void)memcpy(aDataBuff, aNdefFile, dwContentLen);
if(pceT4T ->bVno == PHCE_T4T_NDEF_SUPPORTED_VNO)
{
for(uint8_t bIndex = 0; bIndex < dwContentLen; bIndex++)
{
aNdefFile[bIndex + 2] = aDataBuff[bIndex];
}
aNdefFile[0] = 0x00;
aNdefFile[1] = 0x00;
dwContentLen = GET_EXT_FILE_CONTENT_LEN(aNdefFile);
}
/* Set NDEF File */
status = phceT4T_SetElementaryFile(
pceT4T,
PHCE_T4T_FILE_NDEF,
aNdefFile,
0xE104,
sizeof(aNdefFile),
dwContentLen);
CHECK_SUCCESS(status);
#ifdef NXPBUILD__PHCE_T4T_PROPRIETARY
/* Set Proprietary File */
status = phceT4T_SetElementaryFile(
pceT4T,
PHCE_T4T_FILE_PROPRIETARY,
aProprietaryFile,
0xE105,
sizeof(aProprietaryFile),
GET_FILE_CONTENT_LEN(aProprietaryFile));
CHECK_SUCCESS(status);
#endif /* NXPBUILD__PHCE_T4T_PROPRIETARY */
#if USE_APP_CALLBACK
/* Enable support for proprietary command handling by application
* callback. */
status = phceT4T_SetConfig(
pceT4T,
PHCE_T4T_CONFIG_RECEIVE_PROPRIETARY,
PH_ON);
CHECK_SUCCESS(status);
#endif /* USE_APP_CALLBACK */
/* Configure MLe (This is optional; default MLe is 255) */
status = phceT4T_SetConfig(
pceT4T,
PHCE_T4T_CONFIG_MLE,
0x3B);
CHECK_SUCCESS(status);
/* Configure MLc (This is optional; default MLc is 255) */
status = phceT4T_SetConfig(
pceT4T,
PHCE_T4T_CONFIG_MLC,
0x34);
CHECK_SUCCESS(status);
/* Configure WTX time (WTX will be triggered after this much % of FWT) */
status = phpalI14443p4mC_SetConfig(
ppalI14443p4mC,
PHPAL_I14443P4MC_CONFIG_WT_PERCENTAGE,
40);
CHECK_SUCCESS(status);
#ifdef PH_OSAL_LINUX
/* Disable WTX for Linux Build */
status = phpalI14443p4mC_SetConfig(
ppalI14443p4mC,
PHPAL_I14443P4MC_CONFIG_WTX,
PH_OFF);
CHECK_SUCCESS(status);
#endif
return PH_ERR_SUCCESS;
}
/*
* WTX Callback called from WTX timer of 14443p3mC PAL.
*/
void pWtoxCallBck(void)
{
phOsal_EventPost(&pceT4T->T4TEventObj.EventHandle, E_OS_EVENT_OPT_POST_ISR, E_PH_OSAL_EVT_RTO_TIMEOUT, NULL);
#if ISO_10373_6_PICC_TEST_BENCH
/* Trigger Application callback (AppProcessCmdCallback) about WTX for ISO
* 10373-6 test bench.*/
phOsal_SemPost(&timerwtx.SemHandle, E_OS_SEM_OPT_POST_FROM_ISR);
#endif /* ISO_10373_6_PICC_TEST_BENCH */
}
#endif /* NXPBUILD_EX8_MANDATORY_LAYERS */

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@ -0,0 +1,248 @@
__________________________________________________
NXPNFCRDLIB EXAMPLE : NFCRDLIBEX8_HCE_T4T
(V07.10.00)
__________________________________________________
Table of Contents
_________________
1 Document Purpose
2 Description of the NfcrdlibEx8_HCE_T4T
3 Restrictions on NfcrdlibEx8_HCE_T4T
4 Configurations of NfcrdlibEx8_HCE_T4T
5 Package Contents
6 Mandatory materials (not included)
7 Hardware Configuration
8 Software Configuration
9 Steps to build NfcrdlibEx8_HCE_T4T for LPC1769 with PN5190 using MCUXpresso
10 Steps to build NfcrdlibEx8_HCE_T4T for LPC1769 with PN5180 using MCUXpresso
11 Steps to build NfcrdlibEx8_HCE_T4T for PN7462AU using MCUXpresso
12 Steps to build NfcrdlibEx8_HCE_T4T for FRDM-K82F using MCUXpresso
13 Selection of Board / OSAL / Frontend (MCUXpresso)
14 Steps to follow for PI / Linux / CMake
15 Running NfcrdlibEx8_HCE_T4T
16 List of supported NFC Reader Boards/ICs
17 Reference Documents
1 Document Purpose
==================
This document describes the steps to be followed to execute
NfcrdlibEx8_HCE_T4T example as well as it's known problems and
restrictions.
2 Description of the NfcrdlibEx8_HCE_T4T
========================================
- NfcrdlibEx8_HCE_T4T can be run with PN5180, PN5190 and PN7462AU.
(See Section-16 for supported versions).
- This example will demonstrate card emulation of type 4A tag (T4AT).
- If any reader device is brought in proximity then this example will
go into card emulation mode.
- In card emulation mode this allows both reading and writing of NDEF
message by reader.
- By default the configured NDEF message is "www.nxp.com".
- The maximum NDEF length the reader can write is limited by NDEF file
size used in example (default configured as 1024 bytes).
- By default CET4T NDEF message mapping version configured to 2.0.
User need to update this macro to PHCE_T4T_NDEF_SUPPORTED_VNO to
configure NDEF message mapping version to 3.0.
3 Restrictions on NfcrdlibEx8_HCE_T4T
=====================================
- NfcrdlibEx8_HCE_T4T is restricted to be run on NFC Reader Boards/ICs
mentioned in Section-16.
- The APIs are intended for NXP contact-less reader ICs only, as such
the APIs are not to be ported to any technology from any other
vendor.
- NXP will not support porting to any other vendor platform.
- This software project requires NxpNfcRdLib v07.10.00 or later.
- **IMPORTANT** The default used MCU Type is K82. When executing
example on LPC1769 or PN7462AU, the MCU Type has to be changed in
the MCUXpresso IDE.
- For switching to MCU Type to PN7462AU, see Section-11
- For switching to MCU Type to LPC1769, see Section-9, Section-10 and
Section-.
4 Configurations of NfcrdlibEx8_HCE_T4T
=======================================
- This example is written to demonstrate Host Card Emulation feature
in Passive Type 4A.
5 Package Contents
==================
- Readme.txt
+ This readme file
- NfcrdlibEx8_HCE_T4T.c
+ Main example file.
- intfs/NfcrdlibEx8_HCE_T4T.h
+ Interfaces/Defines specific to the example
- intfs/ph_NxpBuild_App.h
+ Reader library build configuration file
- src/phApp_Helper.c
- src/phApp_PN5180_Init.c
- src/phApp_PN5190_Init.c
- src/phApp_PN7462AU_Init.c
- src/phApp_RC663_Init.c
- src/phApp_Init.c and intfs/phApp_Init.h
+ Common utility functions (common across all examples)
- mcux/.cproject and mcux/.project
+ MCUXpresso project configuration file
- cr_startup_lpc175x_6x.c
+ Startup required to compile example for LPC1769 Micro Controller.
6 Mandatory materials (not included)
====================================
- MCUXpresso IDE. It can be downloaded from
[http://www.nxp.com/products/:MCUXpresso-IDE]
- SDK for Freedom K82 Board
([http://www.nxp.com/products/:FRDM-K82F]). The pre-build SDK can
be downloaded from
[https://mcuxpresso.nxp.com/en/license?hash=9897a8c19a6bc569c3fade7141f0f405&hash_download=true&to_vault=true]
See MCUXpresso User Manual for steps needed to install an SDK.
- Plugin to extend MCUXpresso to support PN7462AU. (Required for
MCUXpresso versions before MCUXpressoIDE_10.0.2)
- LPCXpresso LPC1769 / Freedom K82 development boards For NFC ICs
listed in Section-16 (Note: PN7462AU (Section-16 Bullet-2) does not
need any other other microcontroller).
7 Hardware Configuration
========================
Before starting this application, HW Changes may be required for the
used board. Refer to the following User Manuals / Application notes
before starting with this example.
- AN11744: PN5180 Evaluation board quick start guide
- AN11802: NFC Reader Library for Linux Installation Guidelines
- AN12550: PNEV5190B Evaluation board quick start guide
8 Software Configuration
========================
- The Software can be compiled for Cortex M3 LPC1769 micro-controller,
Cortex M4 Freedom K82 and Cortex M0 based PN7462AU from NXP.
- Since this example can be configured to run on various MCU ICs and
various NFC ICs, appropriate changes are required as mentioned in
Section-9, Section-10, Section-11 and Section-12.
- Listen Mode: In discovery loop listen mode, active listen is
disabled and only passive listen is enabled to support Type 4A card
emulation. Poll mode is not used.
9 Steps to build NfcrdlibEx8_HCE_T4T for LPC1769 with PN5190 using MCUXpresso
=============================================================================
See "PNEV5190B Evaluation board quick start guide" in AN12550 (See
Section-17, Bullet-5 below)
10 Steps to build NfcrdlibEx8_HCE_T4T for LPC1769 with PN5180 using MCUXpresso
==============================================================================
See "Importing provided SW example projects" in AN11908 (See
Section-17, Bullet-2 below)
11 Steps to build NfcrdlibEx8_HCE_T4T for PN7462AU using MCUXpresso
===================================================================
- For MCUXpresso versions before MCUXpressoIDE_10.0.2, See "Adding
PN7462AU Plugin" in UM10883. (See Section-17, Bullet-3 below)
- See "Importing provided SW example projects" in UM10883.
12 Steps to build NfcrdlibEx8_HCE_T4T for FRDM-K82F using MCUXpresso
====================================================================
See "Import projects to the MCUXpresso" in AN11908. (See Section-17,
Bullet-2 below)
13 Selection of Board / OSAL / Frontend (MCUXpresso)
====================================================
For MCUXpresso, the selection of Board / OSAL / Frontend has to be
done via -D (Preprocessor defines).
1) To select the board go to "Project Properties" --> "C/C++ Build"
--> "Settings" --> "Preprocessor" --> "Defined symbols (-D)", and
define the relevant PHDRIVER_<BoardNFCCombination>_BOARD macro.
e.g. For using LPC1769 with Pn5180 use
PHDRIVER_LPC1769PN5180_BOARD. For list of supported boards refer
to Platform\DAL\cfg\BoardSelection.h.
2) To select the osal/os type, go to "Project Properties" --> "C/C++
Build" --> "Settings" --> "Preprocessor" --> "Defined symbols
(-D)".
e.g. For using FreeRTOS use PH_OSAL_FREERTOS. For other options
refer to RTOS\phOsal\inc\phOsal_Config.h.
14 Steps to follow for PI / Linux / CMake
=========================================
The steps are described in AN11802. (See Section-17, Bullet-4 below)
15 Running NfcrdlibEx8_HCE_T4T
==============================
1) When the application is running, if any reader device is brought in
proximity then this example will behave like a Type 4A tag (in card
emulation mode).
2) In card emulation mode this allows both reading and writing of NDEF
message by reader.
16 List of supported NFC Reader Boards/ICs
==========================================
1) PNEV5180B v2.0 Customer Evaluation Board
2) PN7462AU v2.1 Customer Evaluation Board
3) PNEV5190B v1.0 Customer Evaluation Board
17 Reference Documents
======================
1) UM10954 : PN5180 SW Quick start guide
[http://www.nxp.com/docs/en/user-guide/UM10954.pdf]
2) AN11908 : NFC Reader Library for FRDM-K82F Board Installation
guidelines
[http://www.nxp.com/docs/en/application-note/AN11908.pdf]
3) UM10883 : PN7462AU Quick Start Guide - Development Kit
[http://www.nxp.com/docs/en/user-guide/UM10883.pdf]
4) AN11802 : NFC Reader Library for Linux Installation Guidelines
[http://www.nxp.com/docs/en/application-note/AN11802.pdf]
5) AN12550 : PNEV5190B Evaluation board quick start guide
----------------------------------------------------------------------
For updates of this example, see
[http://www.nxp.com/products/:NFC-READER-LIBRARY]

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/*----------------------------------------------------------------------------*/
/* Copyright 2016-2023 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may only */
/* be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that you */
/* have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*----------------------------------------------------------------------------*/
/** \file
* Example Source Header for NFC Type 4A Card Emulation application.
* $Author: NXP $
* $Revision: $ (v07.10.00)
* $Date: $
*/
#ifndef EX8_HCE_T4T_H
#define EX8_HCE_T4T_H
/* Reader library layers required for this example */
#if (defined(NXPBUILD__PHHAL_HW_PN5180) \
|| defined(NXPBUILD__PHHAL_HW_PN5190) \
|| defined(NXPBUILD__PHHAL_HW_PN76XX) \
|| defined(NXPBUILD__PHHAL_HW_PN7462AU)) \
&& defined(NXPBUILD__PHHAL_HW) \
&& defined(NXPBUILD__PHPAL_I14443P4MC_SW) \
&& defined(NXPBUILD__PHAC_DISCLOOP_SW) \
&& defined(NXPBUILD__PHAC_DISCLOOP_TARGET) \
&& (defined(PH_OSAL_FREERTOS) \
|| defined (PH_OSAL_LINUX)) \
&& defined(NXPBUILD__PHCE_T4T_SW)
#define NXPBUILD_EX8_MANDATORY_LAYERS 1U
#else
#define NXPBUILD_EX8_MANDATORY_LAYERS 0U
#endif
/* Check if all required reader library layers are enabled. */
#if NXPBUILD_EX8_MANDATORY_LAYERS
/*******************************************************************************
** Macros
*******************************************************************************/
/* Set this to 1 for running ISO 10373-6 PICC test bench. When set to 1, code
* for creating WTX (for TEST_COMMAND3) in ISO test bench will be enabled. */
#define ISO_10373_6_PICC_TEST_BENCH 0
/* Use application callback for processing UPDATE BINARY and proprietary
* commands */
#define USE_APP_CALLBACK 1
/* Default CET4T NDEF message mapping version configured to 2.0
* Note: User need to update this macro to PHCE_T4T_NDEF_SUPPORTED_VNO to configure NDEF message mapping version to 3.0
* */
#define NXPBUILD_EX8_CET4T_NDEF_VERSION PHCE_T4T_NDEF_SUPPORTED_VNO_20
/* Get content length from CC file. Initial content length is 0. */
#define GET_CCFILE_CONTENT_LEN(x) ((((uint16_t)(x[0]) << 8) & 0xFF00) | (x[1]))
/* Get content length specified in file (first 2 bytes of file) for NDEF and
* proprietary files */
#define GET_EXT_FILE_CONTENT_LEN(x) ((((((uint32_t)(x[0]) << 24) & 0xFF000000) | (((uint32_t)(x[1]) << 16) & 0xFF0000) | (((uint32_t)(x[2]) << 8) & 0xFF00) | (x[3])) > 0)? \
(((((uint32_t)(x[0]) << 24) & 0xFF000000) | (((uint32_t)(x[1]) << 16) & 0xFF0000) | (((uint32_t)(x[2]) << 8) & 0xFF00) | (x[3])) + 4) : 0)
#define GET_FILE_CONTENT_LEN(x) ((((((uint16_t)(x[0]) << 8) & 0xFF00) | (x[1])) > 0)? \
(((((uint16_t)(x[0]) << 8) & 0xFF00) | (x[1])) + 2) : 0)
/* Enable(1) / Disable(0) printing error/info */
#define DETECT_ERROR 0
#if DETECT_ERROR
#define DEBUG_ERROR_PRINT CHECK_STATUS
#define PRINT_INFO(...) DEBUG_PRINTF(__VA_ARGS__)
#else /* DETECT_ERROR */
#define DEBUG_ERROR_PRINT(x)
#define PRINT_INFO(...)
#endif /* DETECT_ERROR */
/* Print system critical errors (with which execution can't proceed further)
* and halt the execution. */
#define ERROR_CRITICAL(...) DEBUG_PRINTF(__VA_ARGS__); while(1) { /* Nothing to do */ }
#ifdef PH_OSAL_FREERTOS
#ifdef PHOSAL_FREERTOS_STATIC_MEM_ALLOCATION
#define RDLIB_TASK_STACK (1800/4)
#define APPLICATION_TASK_STACK (600/4)
#else /* PHOSAL_FREERTOS_STATIC_MEM_ALLOCATION */
#if defined( __PN74XXXX__) || defined(__PN76XX__)
#define RDLIB_TASK_STACK (1600/4)
#define APPLICATION_TASK_STACK (600/4)
#else /* #if defined( __PN74XXXX__) || defined(__PN76XX__) */
#define RDLIB_TASK_STACK (1650)
#define APPLICATION_TASK_STACK (600)
#endif /* #if defined( __PN74XXXX__) || defined(__PN76XX__) */
#endif /* PHOSAL_FREERTOS_STATIC_MEM_ALLOCATION */
#define RDLIB_TASK_PRIO 2
#define APPLICATION_TASK_PRIO 1
#endif /* PH_OSAL_FREERTOS */
#ifdef PH_OSAL_LINUX
#define RDLIB_TASK_STACK 0x20000
#define APPLICATION_TASK_STACK 0x20000
#define RDLIB_TASK_PRIO 0
#define APPLICATION_TASK_PRIO 0
#endif /* PH_OSAL_LINUX */
/*******************************************************************************
** Forward declarations
*******************************************************************************/
/*
* WTX Callback called from WTX timer of 14443p3mC PAL.
*/
void pWtoxCallBck(void);
#if USE_APP_CALLBACK
/**
* Application callback to handle UPDATE BINARY and proprietary commands.
* Refer phceT4T_AppCallback_t in phceT4T.h for more info.
* */
phStatus_t AppProcessCmdCallback(
uint8_t bState, /* [in] Tag State indicating received command type */
uint16_t wRxOption, /* [in] Indicating received data is partial or not */
uint8_t *pRxData, /* [in] Received Data */
uint16_t wRxDataLen, /* [in] Length of received data */
uint16_t *pStatusWord, /* [out] Status Word to be sent (part of R-APDU) */
uint8_t **ppTxData, /* [out] Data to be transmitted (part of R-APDU) */
uint16_t *pTxDataLen /* [out] Length of data to be transmitted */
);
#endif /* USE_APP_CALLBACK */
/**
* Application thread. This calls phceT4T_AppProcessCmd() to handle update
* binary and proprietary commands.
* Refer phceT4T_AppProcessCmd in phceT4T.h for more info.
* APIs which does PAL or HAL exchange should not be called from application
* thread.
* */
void TApplication(
void *pParams); /* [in] Input parameter to thread (not used here) */
/**
* Do card emulation by starting discovery loop in listen mode and activating
* ISO 14443p4mC.
* Refer phceT4T_Activate() in phceT4T.h for info.
* */
void T4TCardEmulation(void);
/**
* Reader library thread. This is the main thread which starts discovery loop
* in listen mode.
* */
void TReaderLibrary(
void *pParams); /* [in] Input parameter to thread (not used here) */
/**
* Initialize/Configure components required by this Example.
* */
void phApp_Initialize(void);
/**
* Configure discovery loop parameters.
* */
phStatus_t ConfigureCardEmulation(void);
#endif /* NXPBUILD_EX8_MANDATORY_LAYERS */
#endif /* EX8_HCE_T4T_H */

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/*----------------------------------------------------------------------------*/
/* Copyright 2016-2023 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may only */
/* be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that you */
/* have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*----------------------------------------------------------------------------*/
/** \file
* Example Source abstracting component header specific to HW used in the examples
* This file shall be present in all examples. A customer does not need to touch/modify this file. This file
* purely depends on the phNxpBuild_Lpc.h or phNxpBuild_App.h
* The phAppInit.h externs the component data structures initialized here that is in turn included by the core examples.
* The core example shall not use any other variable defined here except the RdLib component data structures(as explained above)
* The RdLib component initialization requires some user defined data and function pointers.
* These are defined in the respective examples and externed here.
*
* Keystore and Crypto initialization needs to be handled by application.
*
* $Author$
* $Revision$ (v07.10.00)
* $Date$
*
*/
#ifndef PHAPP_INIT_H
#define PHAPP_INIT_H
/* Status header */
#include <ph_Status.h>
/* Driver Header */
#include <phDriver.h>
/* NFCLIB Header */
#include <phNfcLib.h>
/* LLCP header */
#include <phlnLlcp.h>
/* SNEP header */
#include <phnpSnep.h>
/* Check for K82 controller based boards. */
#if defined(PHDRIVER_FRDM_K82FPN5180_BOARD) || \
defined(PHDRIVER_FRDM_K82FRC663_BOARD) || \
defined(PHDRIVER_K82F_PNEV5190B_BOARD)
#define PHDRIVER_KINETIS_K82
#endif
/* Check for LPC1769 controller based boards. */
#if defined(PHDRIVER_LPC1769PN5180_BOARD) || \
defined(PHDRIVER_LPC1769RC663_BOARD) || \
defined(PHDRIVER_LPC1769PN5190_BOARD)
#define PHDRIVER_LPC1769
#endif
#if defined(PHDRIVER_PIPN5180_BOARD) || \
defined(PHDRIVER_PIRC663_BOARD) || \
defined(PHDRIVER_PIPN5190_BOARD)
#include <phDriver_Linux_Int.h>
#endif
#ifdef PHDRIVER_KINETIS_K82
# include <fsl_debug_console.h>
# include <stdio.h>
#endif
#if !defined(__PN76XX__)
#ifdef DEBUG
#ifdef PHDRIVER_KINETIS_K82
#if SDK_DEBUGCONSOLE==1
#define DEBUG_PRINTF DbgConsole_Printf
#else
#define DEBUG_PRINTF(...) printf(__VA_ARGS__);
#endif
#else /* PHDRIVER_KINETIS_K82 */
#include <stdio.h>
#define DEBUG_PRINTF(...) printf(__VA_ARGS__); fflush(stdout)
#endif /* PHDRIVER_KINETIS_K82 */
#else /* DEBUG */
#define DEBUG_PRINTF(...)
#define DEBUG_SCANF(...)
#endif /* DEBUG */
#else /* __PN76XX__ */
#if (SEGGER_RTT_ENABLE == 1)
#include "SEGGER_RTT.h"
#define DEBUG_PRINTF(...) SEGGER_RTT_printf(0, __VA_ARGS__);
#define DEBUG_SCANF(Input , data) *data = (SEGGER_RTT_WaitKey() - 0x30); SEGGER_RTT_WaitKey()
#else
#if DEBUG
#include <fsl_debug_console.h>
#define DEBUG_PRINTF(...) PRINTF(__VA_ARGS__);
#define DEBUG_SCANF(...) SCANF(__VA_ARGS__);while ((GETCHAR()) != '\n');
#define DEBUG_GETCHAR GETCHAR
#else
#define DEBUG_PRINTF(...)
#define DEBUG_SCANF(...)
#endif /* DEBUG */
#endif /* (SEGGER_RTT_ENABLE == 1) */
#endif /* __PN76XX__ */
/*******************************************************************************
** Global Variable Declaration
*******************************************************************************/
#define PH_NFCRDLIB_EXAMPLE_LPCD_GUARDTIME 100 /* LPCD Guard time(T4) in milli-seconds configured by application for Rc663. */
#define PH_NFCRDLIB_EXAMPLE_LPCD_RFON_TIME 56 /* LPCD RFON time(T3) in micro-seconds configured by application for Rc663. */
/* HAL & BAL declarations */
#ifdef PH_PLATFORM_HAS_ICFRONTEND
extern phbalReg_Type_t sBalParams;
#endif /* PH_PLATFORM_HAS_ICFRONTEND */
#ifdef NXPBUILD__PHLN_LLCP_SW
extern phlnLlcp_Sw_DataParams_t slnLlcp; /* LLCP component */
#endif /* NXPBUILD__PHLN_LLCP_SW */
#ifdef NXPBUILD__PHHAL_HW_PN5180
extern phhalHw_Pn5180_DataParams_t * pHal;
#endif /* NXPBUILD__PHHAL_HW_PN5180 */
#ifdef NXPBUILD__PHHAL_HW_PN5190
extern phhalHw_Pn5190_DataParams_t * pHal;
#endif /* NXPBUILD__PHHAL_HW_PN5190 */
#ifdef NXPBUILD__PHHAL_HW_RC663
extern phhalHw_Rc663_DataParams_t * pHal;
#endif /* NXPBUILD__PHHAL_HW_RC663 */
#ifdef NXPBUILD__PHHAL_HW_PN7462AU
extern phhalHw_PN7462AU_DataParams_t * pHal;
#endif /* NXPBUILD__PHHAL_HW_PN7462AU */
#ifdef NXPBUILD__PHHAL_HW_PN76XX
extern phhalHw_Pn76xx_DataParams_t * pHal;
#endif /* NXPBUILD__PHHAL_HW_PN76XX */
/**************************************************Prints if error is detected**************************************************************/
/* Enable(1) / Disable(0) printing error/info */
#define DETECT_ERROR 0
#if DETECT_ERROR
#define DEBUG_ERROR_PRINT(x) x
#define PRINT_INFO(...) DEBUG_PRINTF(__VA_ARGS__)
#else
#define DEBUG_ERROR_PRINT(x)
#define PRINT_INFO(...)
#endif
#define CHECK_STATUS(x) \
if ((x) != PH_ERR_SUCCESS) \
{ \
DEBUG_PRINTF("Line: %d Error - (0x%04X) has occurred : 0xCCEE CC-Component ID, EE-Error code. Refer-ph_Status.h\n", __LINE__, (x)); \
}
/* prints if error is detected */
#define CHECK_SUCCESS(x) \
if ((x) != PH_ERR_SUCCESS) \
{ \
DEBUG_PRINTF("\nLine: %d Error - (0x%04X) has occurred : 0xCCEE CC-Component ID, EE-Error code. Refer-ph_Status.h\n ", __LINE__, (x)); \
return (x); \
}
/* prints if error is detected */
#define CHECK_NFCLIB_STATUS(x) \
if ((x) != PH_NFCLIB_STATUS_SUCCESS) \
{ \
DEBUG_PRINTF("\nLine: %d Error - (0x%04X) has occurred in NFCLIB\n ", __LINE__, (x)); \
}
/*********************************************************************************************************************************************/
/*******************************************************************************
** Function Declarations
*******************************************************************************/
extern void phApp_CPU_Init(void);
extern phStatus_t phApp_Comp_Init(void * pDiscLoopParams);
extern phStatus_t phApp_HALConfigAutoColl(void);
extern phStatus_t phApp_ConfigureLPCD(void);
extern void phApp_PrintTagInfo(phacDiscLoop_Sw_DataParams_t *pDataParams, uint16_t wNumberOfTags, uint16_t wTagsDetected);
extern void phApp_PrintTech(uint8_t TechType);
extern void phApp_Print_Buff(uint8_t *pBuff, uint8_t num);
extern void PrintErrorInfo(phStatus_t wStatus);
extern phStatus_t phApp_Configure_IRQ();
#ifdef PH_PLATFORM_HAS_ICFRONTEND
extern void CLIF_IRQHandler(void);
#endif /* PH_PLATFORM_HAS_ICFRONTEND */
#endif /* PHAPP_INIT_H */

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/*----------------------------------------------------------------------------*/
/* Copyright 2016-2023 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may only */
/* be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that you */
/* have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*----------------------------------------------------------------------------*/
/** \file
* Application specific selection of Reader Library Components
*
* $Author: NXP $
* $Revision: $ (v07.10.00)
* $Date: $
*/
#ifndef PH_NXPBUILD_APP_H_INC
#define PH_NXPBUILD_APP_H_INC
/** \defgroup ph_NxpBuild NXP Build
* \brief Controls the Inclusion of required components, Inclusion SRC/DATA within components and the Build Dependencies between the components
* @{
*/
/* NXPBUILD_DELETE: included code lines should be always removed from code */
/* NXP BUILD DEFINES */
/* use #define to include components */
/* comment out #define to exclude components */
/* DEBUG build mode */
/*#define NXPBUILD__PH_DEBUG*/ /**< DEBUG build definition */
//#define NXPRDLIB_REM_GEN_INTFS
/*********************************************************************************************************************************************************************************/
#if defined(__PN74XXXX__) || defined (__PN73XXXX__)
#define NXPBUILD__PHHAL_HW_PN7462AU /**< NFC Controller PN7462AU HAL */
#endif
#ifdef __PN76XX__
#ifdef __PN7642__
#define NXPBUILD__PHHAL_HW_PN7642 /**< NFC Controller PN7642 HAL */
#elif __PN7640__
#define NXPBUILD__PHHAL_HW_PN7640 /**< NFC Controller PN7640 HAL */
#else
#error " PN76 platform definition (__PN7642__ or __PN7640__) missing !!! "
#endif
#if defined(__PN7642__) || defined(__PN7640__)
#define NXPBUILD__PHHAL_HW_PN76XX /**< NFC Controller PN76XX HAL */
#endif
#endif /* __PN76XX__ */
#if defined(PHDRIVER_LPC1769PN5180_BOARD) \
|| defined(PHDRIVER_FRDM_K82FPN5180_BOARD)
# define NXPBUILD__PHHAL_HW_PN5180
#endif
#if defined(PHDRIVER_LPC1769PN5190_BOARD) \
|| defined(PHDRIVER_K82F_PNEV5190B_BOARD)
# define NXPBUILD__PHHAL_HW_PN5190
#endif
#if defined(PHDRIVER_LPC1769RC663_BOARD) \
|| defined(PHDRIVER_FRDM_K82FRC663_BOARD)
/* WARNING: This example is not supported for RC663 */
# define NXPBUILD__PHHAL_HW_RC663
#endif
#if defined(NXPBUILD__PHHAL_HW_PN5180) || \
defined(NXPBUILD__PHHAL_HW_PN7462AU) || \
defined(NXPBUILD__PHHAL_HW_PN76XX) || \
defined(NXPBUILD__PHHAL_HW_PN5190)
#define NXPBUILD__PHHAL_HW_TARGET /**< Dependency checking if target mode macros should be enabled */
#endif
/*********************************************************************************************************************************************************************************/
//#define NXPBUILD__PHPAL_I14443P3A_SW /**< PAL ISO 14443-3A SW Component is included. */
//#define NXPBUILD__PHPAL_I14443P3B_SW /**< PAL ISO 14443-3B SW Component is included. */
//#define NXPBUILD__PHPAL_I14443P4A_SW /**< PAL ISO 14443-4A SW Component is included. */
//#define NXPBUILD__PHPAL_I14443P4_SW /**< PAL ISO 14443-4 SW Component is included. */
//#define NXPBUILD__PHPAL_MIFARE_SW /**< PAL MIFARE SW Component is included */
//#define NXPBUILD__PHPAL_MIFARE_STUB /**< PAL MIFARE STUB Component is included */
//#define NXPBUILD__PHPAL_FELICA_SW /**< PAL Felica SW Component is included. */
//#define NXPBUILD__PHPAL_SLI15693_SW /**< PAL SLI 15693 Component is included. */
//#define NXPBUILD__PHPAL_I18000P3M3_SW /**< PAL ISO 18000p3m3 Component is included. */
#ifdef NXPBUILD__PHHAL_HW_RC663 /**< If FE HAL is RC663, then include EPC UID PAL as required, otherwise exclude. */
// #define NXPBUILD__PHPAL_EPCUID_SW /**< PAL EPC UID SW Component is included. */
#endif
//#define NXPBUILD__PHPAL_I18092MPI_SW /**< PAL ISO18092 (P2P) SW Component is included. */
#ifndef NXPBUILD__PHHAL_HW_RC663 /**< If FE HAL is RC663, then exclude ISO14443 Card Mode PAL & ISO18092 Target Mode PAL, otherwise include as required. */
#define NXPBUILD__PHPAL_I14443P4MC_SW /**< PAL ISO 14443-4 Card Mode SW Component is included. */
// #define NXPBUILD__PHPAL_I18092MT_SW /**< PAL ISO 18092 Target Mode SW Component is included. */
#endif /* NXPBUILD__PHHAL_HW_RC663 */
/*********************************************************************************************************************************************************************************/
#define NXPBUILD__PHAC_DISCLOOP_SW /**< Discovery Loop Activity SW Component is included. */
#ifdef NXPBUILD__PHAC_DISCLOOP_SW /**< If DiscLoop SW Component is included, macros( & it's dependencies) to include/exclude SRC/DATA within Discloop is defined. */
#if defined (NXPBUILD__PHHAL_HW_PN5180) || \
defined (NXPBUILD__PHHAL_HW_PN5190) || \
defined (NXPBUILD__PHHAL_HW_RC663) || \
defined (NXPBUILD__PHHAL_HW_PN7462AU) || \
defined (NXPBUILD__PHHAL_HW_PN7642)
// #define NXPBUILD__PHAC_DISCLOOP_LPCD /**< SRC to enable LPCD is included. */
#endif
#ifdef NXPBUILD__PHPAL_I14443P3A_SW
#define NXPBUILD__PHAC_DISCLOOP_TYPEA_I3P3_TAGS /**< SRC/DATA to Detect/CollRes/Activate cards such as MFC, MFUL, MFP SL1 etc is included. */
#define NXPBUILD__PHAC_DISCLOOP_TYPEA_JEWEL_TAGS /**< SRC/DATA to Detect cards such as NFC Forum T1T, Topaz/Jewel is included. */
#if defined(NXPBUILD__PHPAL_I14443P4A_SW) && defined(NXPBUILD__PHPAL_I14443P4_SW)
#define NXPBUILD__PHAC_DISCLOOP_TYPEA_I3P4_TAGS /**< SRC/DATA to Detect cards such as MFDF, MFP, T4AT NFC Forum Tag or Type A EMVCo is included. */
#endif
#endif /* NXPBUILD__PHPAL_I14443P3A_SW */
#if defined(NXPBUILD__PHPAL_I14443P3A_SW) && defined(NXPBUILD__PHPAL_I18092MPI_SW)
#define NXPBUILD__PHAC_DISCLOOP_TYPEA_P2P_TAGS /**< SRC/DATA to Detect Peer Passive Type A P2P Target mode devices is included. */
#endif
#ifndef NXPBUILD__PHHAL_HW_RC663
#ifdef NXPBUILD__PHPAL_I18092MPI_SW
#define NXPBUILD__PHAC_DISCLOOP_TYPEA_P2P_ACTIVE /**< SRC/DATA to Detect Peer Active Type A P2P Target mode devices is included. */
#define NXPBUILD__PHAC_DISCLOOP_TYPEF212_P2P_ACTIVE/**< SRC/DATA to Detect Peer Active Type F212 P2P Target mode devices is included. */
#define NXPBUILD__PHAC_DISCLOOP_TYPEF424_P2P_ACTIVE/**< SRC/DATA to Detect Peer Active Type F424 P2P Target mode devices is included. */
#endif /* NXPBUILD__PHPAL_I18092MPI_SW */
#endif /* NXPBUILD__PHHAL_HW_RC663 */
#ifdef NXPBUILD__PHPAL_FELICA_SW
#define NXPBUILD__PHAC_DISCLOOP_FELICA_TAGS /**< SRC/DATA to Detect FeliCa Cards is included. */
#ifdef NXPBUILD__PHPAL_I18092MPI_SW
#define NXPBUILD__PHAC_DISCLOOP_TYPEF_P2P_TAGS /**< SRC/DATA to Detect Peer Passive Type F P2P Target mode devices is included. */
#endif /* NXPBUILD__PHPAL_I18092MPI_SW */
#endif /* NXPBUILD__PHPAL_FELICA_SW */
#ifdef NXPBUILD__PHPAL_I14443P3B_SW
#define NXPBUILD__PHAC_DISCLOOP_TYPEB_I3P3B_TAGS /**< SRC/DATA to Detect Type B Cards that operate at Layer3 level is included */
#ifdef NXPBUILD__PHPAL_I14443P4_SW
#define NXPBUILD__PHAC_DISCLOOP_TYPEB_I3P4B_TAGS /**< SRC/DATA to Detect Type B Cards such as NFC Forum Type 4 Tags, EMVCo Type B Cards etc is included */
#endif /* NXPBUILD__PHPAL_I14443P4_SW */
#endif /* NXPBUILD__PHPAL_I14443P3B_SW */
#ifdef NXPBUILD__PHPAL_SLI15693_SW
#define NXPBUILD__PHAC_DISCLOOP_TYPEV_TAGS /**< SRC/DATA to Detect Type V Cards such as ICODE SLI/SLIX/SLI2/Tesa Cards is included*/
#endif /* NXPBUILD__PHPAL_SLI15693_SW */
#ifdef NXPBUILD__PHPAL_I18000P3M3_SW
#define NXPBUILD__PHAC_DISCLOOP_I18000P3M3_TAGS /**< SRC/DATA to Detect ICODE ILT Cards such as SMARTRAC StackIt Cards is included*/
#endif /* NXPBUILD__PHPAL_I18000P3M3_SW */
#ifndef NXPBUILD__PHHAL_HW_RC663 /**< If FE HAL is RC663, target mode is not supported at all, hence exclude those SRC, otherwise include as required */
#ifdef NXPBUILD__PHHAL_HW_TARGET
#define NXPBUILD__PHAC_DISCLOOP_TYPEA_TARGET_PASSIVE /**< SRC to Initialize Type A passive listen config and subsequently call HAL AutoColl is included. */
// #define NXPBUILD__PHAC_DISCLOOP_TYPEA_TARGET_ACTIVE /**< SRC to Initialize Type A active listen config and subsequently call HAL AutoColl is included. */
// #define NXPBUILD__PHAC_DISCLOOP_TYPEF212_TARGET_PASSIVE/**< SRC to Initialize Type F212 passive listen config and subsequently call HAL AutoColl is included. */
// #define NXPBUILD__PHAC_DISCLOOP_TYPEF212_TARGET_ACTIVE /**< SRC to Initialize Type F212 active listen config and subsequently call HAL AutoColl is included. */
// #define NXPBUILD__PHAC_DISCLOOP_TYPEF424_TARGET_PASSIVE/**< SRC to Initialize Type F424 passive listen config and subsequently call HAL AutoColl is included. */
// #define NXPBUILD__PHAC_DISCLOOP_TYPEF424_TARGET_ACTIVE /**< SRC to Initialize Type F424 active listen config and subsequently call HAL AutoColl is included. */
#endif /* NXPBUILD__PHHAL_HW_TARGET */
#endif
#endif /* NXPBUILD__PHAC_DISCLOOP_SW */
/*********************************************************************************************************************************************************************************/
#define NXPBUILD__PHNFCLIB /**< Simplified API Interface, If enabling this the entry point should be this component in the application */
/*********************************************************************************************************************************************************************************/
//#define NXPBUILD__PH_CIDMANAGER_SW /**< CID Manager SW Component is included. */
//#define NXPBUILD__PH_KEYSTORE_SW /**< SW KeyStore Component is included. */
#if defined(NXPBUILD__PHHAL_HW_RC663) && !defined(NXPBUILD__PH_KEYSTORE_SW)
#define NXPBUILD__PH_KEYSTORE_RC663 /**< RC663 KeyStore Component is included. */
#endif
//#define NXPBUILD__PH_NDA_MFDF /**< MIFARE DESFire contactless IC */
//#define NXPBUILD__PH_CRYPTOSYM_SW /**< Crypto Symbols SW Component is included. */
//#define NXPBUILD__PH_CRYPTORNG_SW /**< Crypto RNG SW Component is included. */
/*********************************************************************************************************************************************************************************/
#ifdef NXPBUILD__PHPAL_FELICA_SW
#define NXPBUILD__PHAL_FELICA_SW /**< AL FeliCa SW Component is included */
#endif /* NXPBUILD__PHPAL_FELICA_SW */
#ifdef NXPBUILD__PHPAL_MIFARE_SW
#if defined(NXPBUILD__PH_KEYSTORE_SW) || defined(NXPBUILD__PH_KEYSTORE_RC663)
#define NXPBUILD__PHAL_MFC_SW /**< AL MIFARE Classic contactless IC SW Component is included */
#endif
#define NXPBUILD__PHAL_MFUL_SW /**< AL Mifare Ultrlight SW Component is included */
#define NXPBUILD__PHAL_MFDF_SW /**< AL Mifare DesFire SW Component is included */
// #define NXPBUILD__PHAL_MFNTAG42XDNA_SW /**< AL MIFARE Prime Ntag42XDna contactless IC SW Component is included */
#endif /* NXPBUILD__PHPAL_MIFARE_SW */
//#define NXPBUILD__PHAL_T1T_SW /**< AL Type T1 Tag SW Component is included */
#ifdef NXPBUILD__PHPAL_SLI15693_SW
#define NXPBUILD__PHAL_ICODE_SW /**< AL ICODE SW COMPONENT is included */
#endif /* NXPBUILD__PHPAL_SLI15693_SW */
//#define NXPBUILD__PHAL_TOP_SW /**< AL for TagOps Mapping SW Component is included.Required for NDEF operations */
#ifdef NXPBUILD__PHPAL_I18000P3M3_SW
#define NXPBUILD__PHAL_I18000P3M3_SW /**< AL ISO18000p3m3 SW Component is included */
#endif /* NXPBUILD__PHPAL_I18000P3M3_SW */
#ifdef NXPBUILD__PHPAL_I14443P4MC_SW
#if !defined(PH_OSAL_NULLOS)
#define NXPBUILD__PHCE_T4T_SW /**< AL HCE T2AT SW Component is included */
//#define NXPBUILD__PHCE_T4T_PROPRIETARY /**< SRC to handle HCE T4AT Proprietary Commands is included */
#endif
#endif /* NXPBUILD__PHPAL_I14443P4MC_SW */
/* LLCP Components */
#if defined(NXPBUILD__PHPAL_I18092MPI_SW) || defined(NXPBUILD__PHPAL_I18092MT_SW)
#if !defined(PH_OSAL_NULLOS)
#define NXPBUILD__PHLN_LLCP_SW /**< Link LLCP SW Component is included */
#endif
#endif
/* SNEP components */
#ifdef NXPBUILD__PHLN_LLCP_SW
#define NXPBUILD__PHNP_SNEP_SW /**< Protocol SNEP SW Component is included */
#endif /* NXPBUILD__PHLN_LLCP_SW */
/* Enable/disable Debugging */
/*#define NXPBUILD__PH_DEBUG*/ /**< TODO: To be checked if required */
/** @}
* end of ph_NxpBuild
*/
#endif /* PH_NXPBUILD_APP_H_INC */

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</storageModule>
<storageModule moduleId="com.nxp.mcuxpresso.core.datamodels">
<sdkName>SDK_2.x_FRDM-K82F</sdkName>
<sdkVersion>2.6.0</sdkVersion>
</storageModule>
</cproject>

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@ -0,0 +1,89 @@
<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>NfcrdlibEx8_HCE_T4T_mcux</name>
<comment></comment>
<projects>
<project>FreeRTOS</project>
<project>lpc_board_nxp_lpcxpresso_1769</project>
<project>lpc_chip_175x_6x</project>
<project>NxpNfcRdLib</project>
<project>SDK_2.x_FRDM-K82F</project>
</projects>
<buildSpec>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
<triggers>full,incremental,</triggers>
<arguments>
</arguments>
</buildCommand>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
<triggers>full,incremental,</triggers>
<arguments>
</arguments>
</buildCommand>
</buildSpec>
<natures>
<nature>org.eclipse.cdt.core.cnature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
<nature>com.nxp.mcuxpresso.core.datamodels.sdkNature</nature>
</natures>
<linkedResources>
<link>
<name>DAL</name>
<type>2</type>
<locationURI>PARENT-3-PROJECT_LOC/Platform/DAL</locationURI>
</link>
<link>
<name>FreeRTOS</name>
<type>2</type>
<locationURI>PARENT-3-PROJECT_LOC/RTOS/FreeRTOS</locationURI>
</link>
<link>
<name>NfcrdlibEx8_HCE_T4T.c</name>
<type>1</type>
<locationURI>PARENT-1-PROJECT_LOC/NfcrdlibEx8_HCE_T4T.c</locationURI>
</link>
<link>
<name>NxpNfcRdLib</name>
<type>2</type>
<locationURI>PARENT-3-PROJECT_LOC/NxpNfcRdLib</locationURI>
</link>
<link>
<name>PN7462AU</name>
<type>2</type>
<locationURI>PARENT-3-PROJECT_LOC/Platform/PN7462AU</locationURI>
</link>
<link>
<name>Readme.txt</name>
<type>1</type>
<locationURI>PARENT-1-PROJECT_LOC/Readme.txt</locationURI>
</link>
<link>
<name>intfs</name>
<type>2</type>
<locationURI>PARENT-1-PROJECT_LOC/intfs</locationURI>
</link>
<link>
<name>phOsal</name>
<type>2</type>
<locationURI>virtual:/virtual</locationURI>
</link>
<link>
<name>src</name>
<type>2</type>
<locationURI>PARENT-1-PROJECT_LOC/src</locationURI>
</link>
<link>
<name>phOsal/inc</name>
<type>2</type>
<locationURI>PARENT-3-PROJECT_LOC/RTOS/phOsal/inc</locationURI>
</link>
<link>
<name>phOsal/src</name>
<type>2</type>
<locationURI>PARENT-3-PROJECT_LOC/RTOS/phOsal/src</locationURI>
</link>
</linkedResources>
</projectDescription>

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@ -0,0 +1,493 @@
//*****************************************************************************
// LPC175x_6x Microcontroller Startup code for use with LPCXpresso IDE
//
// Version : 140114
//*****************************************************************************
//
// Copyright(C) NXP Semiconductors, 2014
// All rights reserved.
//
// Software that is described herein is for illustrative purposes only
// which provides customers with programming information regarding the
// LPC products. This software is supplied "AS IS" without any warranties of
// any kind, and NXP Semiconductors and its licensor disclaim any and
// all warranties, express or implied, including all implied warranties of
// merchantability, fitness for a particular purpose and non-infringement of
// intellectual property rights. NXP Semiconductors assumes no responsibility
// or liability for the use of the software, conveys no license or rights under any
// patent, copyright, mask work right, or any other intellectual property rights in
// or to any products. NXP Semiconductors reserves the right to make changes
// in the software without notification. NXP Semiconductors also makes no
// representation or warranty that such application will be suitable for the
// specified use without further testing or modification.
//
// Permission to use, copy, modify, and distribute this software and its
// documentation is hereby granted, under NXP Semiconductors' and its
// licensor's relevant copyrights in the software, without fee, provided that it
// is used in conjunction with NXP Semiconductors microcontrollers. This
// copyright, permission, and disclaimer notice must appear in all copies of
// this code.
//*****************************************************************************
#include <ph_Status.h>
#include <cr_section_macros.h>
#include <NXP/crp.h>
#ifdef DEBUG
# define VT_IMAGE_LENGTH 0x76706b64U
#else /* DEBUG */
# define VT_IMAGE_LENGTH 0xFFFFFFFFU
#endif /* DEBUG */
#if defined (__cplusplus)
#ifdef __REDLIB__
#error Redlib does not support C++
#else
//*****************************************************************************
//
// The entry point for the C++ library startup
//
//*****************************************************************************
extern "C" {
extern void __libc_init_array(void);
}
#endif
#endif
#define WEAK __attribute__ ((weak))
#define ALIAS(f) __attribute__ ((weak, alias (#f)))
__CRP const unsigned int CRP_WORD = CRP_NO_CRP;
//*****************************************************************************
#if defined (__cplusplus)
extern "C" {
#endif
//*****************************************************************************
#if defined (__USE_CMSIS) || defined (__USE_LPCOPEN)
// Declaration of external SystemInit function
void SystemInit(void);
extern void Board_SystemInit(void);
extern void Chip_SystemInit(void);
extern void SystemCoreClockUpdate(void);
#endif
//*****************************************************************************
//
// Forward declaration of the default handlers. These are aliased.
// When the application defines a handler (with the same name), this will
// automatically take precedence over these weak definitions
//
//*****************************************************************************
void ResetISR(void);
WEAK void NMI_Handler(void);
//WEAK void HardFault_Handler(void);
WEAK void MemManage_Handler(void);
WEAK void BusFault_Handler(void);
WEAK void UsageFault_Handler(void);
WEAK void SVC_Handler(void);
WEAK void DebugMon_Handler(void);
WEAK void PendSV_Handler(void);
WEAK void SysTick_Handler(void);
WEAK void IntDefaultHandler(void);
/* The prototype shows it is a naked function - in effect this is just an
assembly function. */
void HardFault_Handler( void ) __attribute__( ( naked ) );
//*****************************************************************************
//
// Forward declaration of the specific IRQ handlers. These are aliased
// to the IntDefaultHandler, which is a 'forever' loop. When the application
// defines a handler (with the same name), this will automatically take
// precedence over these weak definitions
//
//*****************************************************************************
void WDT_IRQHandler(void) ALIAS(IntDefaultHandler);
void TIMER0_IRQHandler(void) ALIAS(IntDefaultHandler);
void TIMER1_IRQHandler(void) ALIAS(IntDefaultHandler);
void TIMER2_IRQHandler(void) ALIAS(IntDefaultHandler);
void TIMER3_IRQHandler(void) ALIAS(IntDefaultHandler);
void UART0_IRQHandler(void) ALIAS(IntDefaultHandler);
void UART1_IRQHandler(void) ALIAS(IntDefaultHandler);
void UART2_IRQHandler(void) ALIAS(IntDefaultHandler);
void UART3_IRQHandler(void) ALIAS(IntDefaultHandler);
void PWM1_IRQHandler(void) ALIAS(IntDefaultHandler);
void I2C0_IRQHandler(void) ALIAS(IntDefaultHandler);
void I2C1_IRQHandler(void) ALIAS(IntDefaultHandler);
void I2C2_IRQHandler(void) ALIAS(IntDefaultHandler);
void SPI_IRQHandler(void) ALIAS(IntDefaultHandler);
void SSP0_IRQHandler(void) ALIAS(IntDefaultHandler);
void SSP1_IRQHandler(void) ALIAS(IntDefaultHandler);
void PLL0_IRQHandler(void) ALIAS(IntDefaultHandler);
void RTC_IRQHandler(void) ALIAS(IntDefaultHandler);
void EINT0_IRQHandler(void) ALIAS(IntDefaultHandler);
void EINT1_IRQHandler(void) ALIAS(IntDefaultHandler);
void EINT2_IRQHandler(void) ALIAS(IntDefaultHandler);
void CLIF_IRQHandler(void) ALIAS(IntDefaultHandler);
void ADC_IRQHandler(void) ALIAS(IntDefaultHandler);
void BOD_IRQHandler(void) ALIAS(IntDefaultHandler);
void USB_IRQHandler(void) ALIAS(IntDefaultHandler);
void CAN_IRQHandler(void) ALIAS(IntDefaultHandler);
void DMA_IRQHandler(void) ALIAS(IntDefaultHandler);
void I2S_IRQHandler(void) ALIAS(IntDefaultHandler);
#if defined (__USE_LPCOPEN)
void ETH_IRQHandler(void) ALIAS(IntDefaultHandler);
#else
void ENET_IRQHandler(void) ALIAS(IntDefaultHandler);
#endif
void RIT_IRQHandler(void) ALIAS(IntDefaultHandler);
void MCPWM_IRQHandler(void) ALIAS(IntDefaultHandler);
void QEI_IRQHandler(void) ALIAS(IntDefaultHandler);
void PLL1_IRQHandler(void) ALIAS(IntDefaultHandler);
void USBActivity_IRQHandler(void) ALIAS(IntDefaultHandler);
void CANActivity_IRQHandler(void) ALIAS(IntDefaultHandler);
void UART4_IRQHandler(void) ALIAS(IntDefaultHandler);
void SSP2_IRQHandler(void) ALIAS(IntDefaultHandler);
void LCD_IRQHandler(void) ALIAS(IntDefaultHandler);
void GPIO_IRQHandler(void) ALIAS(IntDefaultHandler);
void PWM0_IRQHandler(void) ALIAS(IntDefaultHandler);
void EEPROM_IRQHandler(void) ALIAS(IntDefaultHandler);
//*****************************************************************************
//
// The entry point for the application.
// __main() is the entry point for Redlib based applications
// main() is the entry point for Newlib based applications
//
//*****************************************************************************
#if defined (__REDLIB__)
extern void __main(void);
#endif
extern int main(void);
//*****************************************************************************
//
// External declaration for the pointer to the stack top from the Linker Script
//
//*****************************************************************************
extern void _vStackTop(void);
//*****************************************************************************
#if defined (__cplusplus)
} // extern "C"
#endif
//*****************************************************************************
//
// The vector table.
// This relies on the linker script to place at correct location in memory.
//
//*****************************************************************************
extern void (* const g_pfnVectors[])(void);
__attribute__ ((section(".isr_vector")))
void (* const g_pfnVectors[])(void) = {
// Core Level - CM3
&_vStackTop, // The initial stack pointer
ResetISR, // The reset handler
NMI_Handler, // The NMI handler
HardFault_Handler, // The hard fault handler
MemManage_Handler, // The MPU fault handler
BusFault_Handler, // The bus fault handler
UsageFault_Handler, // The usage fault handler
0, // Reserved
0, // Reserved
0, // Reserved
0, // Reserved
SVC_Handler, // SVCall handler
DebugMon_Handler, // Debug monitor handler
0, // Reserved
PendSV_Handler, // The PendSV handler
SysTick_Handler, // The SysTick handler
// Chip Level - LPC17
WDT_IRQHandler, // 16, 0x40 - WDT
TIMER0_IRQHandler, // 17, 0x44 - TIMER0
TIMER1_IRQHandler, // 18, 0x48 - TIMER1
TIMER2_IRQHandler, // 19, 0x4c - TIMER2
TIMER3_IRQHandler, // 20, 0x50 - TIMER3
UART0_IRQHandler, // 21, 0x54 - UART0
UART1_IRQHandler, // 22, 0x58 - UART1
UART2_IRQHandler, // 23, 0x5c - UART2
UART3_IRQHandler, // 24, 0x60 - UART3
PWM1_IRQHandler, // 25, 0x64 - PWM1
I2C0_IRQHandler, // 26, 0x68 - I2C0
I2C1_IRQHandler, // 27, 0x6c - I2C1
I2C2_IRQHandler, // 28, 0x70 - I2C2
SPI_IRQHandler, // 29, 0x74 - SPI
SSP0_IRQHandler, // 30, 0x78 - SSP0
SSP1_IRQHandler, // 31, 0x7c - SSP1
PLL0_IRQHandler, // 32, 0x80 - PLL0 (Main PLL)
RTC_IRQHandler, // 33, 0x84 - RTC
EINT0_IRQHandler, // 34, 0x88 - EINT0
EINT1_IRQHandler, // 35, 0x8c - EINT1
EINT2_IRQHandler, // 36, 0x90 - EINT2
CLIF_IRQHandler, // 37, 0x94 - EINT3 (Used for CLIF IRQ)
ADC_IRQHandler, // 38, 0x98 - ADC
BOD_IRQHandler, // 39, 0x9c - BOD
USB_IRQHandler, // 40, 0xA0 - USB
CAN_IRQHandler, // 41, 0xa4 - CAN
DMA_IRQHandler, // 42, 0xa8 - GP DMA
I2S_IRQHandler, // 43, 0xac - I2S
#if defined (__USE_LPCOPEN)
ETH_IRQHandler, // 44, 0xb0 - Ethernet
#else
ENET_IRQHandler, // 44, 0xb0 - Ethernet
#endif
RIT_IRQHandler, // 45, 0xb4 - RITINT
MCPWM_IRQHandler, // 46, 0xb8 - Motor Control PWM
QEI_IRQHandler, // 47, 0xbc - Quadrature Encoder
PLL1_IRQHandler, // 48, 0xc0 - PLL1 (USB PLL)
USBActivity_IRQHandler, // 49, 0xc4 - USB Activity interrupt to wakeup
CANActivity_IRQHandler, // 50, 0xc8 - CAN Activity interrupt to wakeup
UART4_IRQHandler, //; 51 UART4
SSP2_IRQHandler, //; 52 SSP2
LCD_IRQHandler, //; 53 LCD
GPIO_IRQHandler, //; 54 GPIO
PWM0_IRQHandler , //; 55 PWM0
EEPROM_IRQHandler, //; 56 EEPROM
(void *)VT_IMAGE_LENGTH, //; 57 VT Checksum for CRC Check of Vector Table.
};
//*****************************************************************************
// Functions to carry out the initialization of RW and BSS data sections. These
// are written as separate functions rather than being inlined within the
// ResetISR() function in order to cope with MCUs with multiple banks of
// memory.
//*****************************************************************************
__attribute__ ((section(".after_vectors")))
void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
unsigned int *pulDest = (unsigned int*) start;
unsigned int *pulSrc = (unsigned int*) romstart;
unsigned int loop;
for (loop = 0; loop < len; loop = loop + 4)
*pulDest++ = *pulSrc++;
}
__attribute__ ((section(".after_vectors")))
void bss_init(unsigned int start, unsigned int len) {
unsigned int *pulDest = (unsigned int*) start;
unsigned int loop;
for (loop = 0; loop < len; loop = loop + 4)
*pulDest++ = 0;
}
//*****************************************************************************
// The following symbols are constructs generated by the linker, indicating
// the location of various points in the "Global Section Table". This table is
// created by the linker via the Code Red managed linker script mechanism. It
// contains the load address, execution address and length of each RW data
// section and the execution and length of each BSS (zero initialized) section.
//*****************************************************************************
extern unsigned int __data_section_table;
extern unsigned int __data_section_table_end;
extern unsigned int __bss_section_table;
extern unsigned int __bss_section_table_end;
//*****************************************************************************
// Reset entry point for your code.
// Sets up a simple runtime environment and initializes the C/C++
// library.
//*****************************************************************************
__attribute__ ((section(".after_vectors")))
void
ResetISR(void) {
//
// Copy the data sections from flash to SRAM.
//
unsigned int LoadAddr, ExeAddr, SectionLen;
unsigned int *SectionTableAddr;
// Load base address of Global Section Table
SectionTableAddr = &__data_section_table;
// Copy the data sections from flash to SRAM.
while (SectionTableAddr < &__data_section_table_end) {
LoadAddr = *SectionTableAddr++;
ExeAddr = *SectionTableAddr++;
SectionLen = *SectionTableAddr++;
data_init(LoadAddr, ExeAddr, SectionLen);
}
// At this point, SectionTableAddr = &__bss_section_table;
// Zero fill the bss segment
while (SectionTableAddr < &__bss_section_table_end) {
ExeAddr = *SectionTableAddr++;
SectionLen = *SectionTableAddr++;
bss_init(ExeAddr, SectionLen);
}
#if defined (__USE_CMSIS) || defined (__USE_LPCOPEN)
SystemInit();
#endif
#if defined (__cplusplus)
//
// Call C++ library initialisation
//
__libc_init_array();
#endif
#if defined (__REDLIB__)
// Call the Redlib library, which in turn calls main()
__main() ;
#else
main();
#endif
//
// main() shouldn't return, but if it does, we'll just enter an infinite loop
//
while (1) {
;
}
}
/* Set up and initialize hardware prior to call to main */
void SystemInit(void)
{
unsigned int *pSCB_VTOR = (unsigned int *) 0xE000ED08;
#if defined(__IAR_SYSTEMS_ICC__)
extern void *__vector_table;
*pSCB_VTOR = (unsigned int) &__vector_table;
#elif defined(__CODE_RED)
*pSCB_VTOR = (unsigned int) &g_pfnVectors;
#elif defined(__ARMCC_VERSION)
extern void *__Vectors;
*pSCB_VTOR = (unsigned int) &__Vectors;
#endif
#if defined(__FPU_PRESENT) && __FPU_PRESENT == 1
fpuInit();
#endif
#if defined(NO_BOARD_LIB)
/* Chip specific SystemInit */
Chip_SystemInit();
#else
/* Setup system clocking and muxing */
Board_SystemInit();
#endif
/* Update system core clock rate. */
SystemCoreClockUpdate();
}
//*****************************************************************************
// Default exception handlers. Override the ones here by defining your own
// handler routines in your application code.
//*****************************************************************************
__attribute__ ((section(".after_vectors")))
void NMI_Handler(void)
{ while(1) {}
}
/* The fault handler implementation calls a function called
prvGetRegistersFromStack(). */
__attribute__ ((section(".after_vectors")))
void HardFault_Handler(void)
{
/* Use assembly to pick up date, but feed to C Code. */
__asm( ".syntax divided\n"
"MOVS R0, #4 \n"
"MOV R1, LR \n"
"TST R0, R1 \n"
"BEQ _MSP \n"
"MRS R0, PSP \n"
"B HardFault_HandlerC \n"
"_MSP: \n"
"MRS R0, MSP \n"
"B HardFault_HandlerC \n"
".syntax divided\n") ;
__asm(".syntax unified");
}
__attribute__ ((section(".after_vectors")))
void HardFault_HandlerC(
unsigned long *args)
{
volatile unsigned long cm_r0;
volatile unsigned long cm_r1;
volatile unsigned long cm_r2;
volatile unsigned long cm_r3;
volatile unsigned long cm_r12;
volatile unsigned long cm_lr;
volatile unsigned long cm_pc;
volatile unsigned long cm_psr;
//if (((uint32_t) args < PH_RAM_MEM_END)&& ( (uint32_t)args > PH_RAM_MEM_START))
//0x10000000 -- 0x8000
//0x2007c000 -- 0x8000
{
cm_r0 = ((unsigned long)args[0]);
cm_r1 = ((unsigned long)args[1]);
cm_r2 = ((unsigned long)args[2]);
cm_r3 = ((unsigned long)args[3]);
cm_r12 = ((unsigned long)args[4]);
cm_lr = ((unsigned long)args[5]);
cm_pc = ((unsigned long)args[6]);
cm_psr = ((unsigned long)args[7]);
PH_UNUSED_VARIABLE(cm_r0);
PH_UNUSED_VARIABLE(cm_r1);
PH_UNUSED_VARIABLE(cm_r2);
PH_UNUSED_VARIABLE(cm_r3);
PH_UNUSED_VARIABLE(cm_r12);
PH_UNUSED_VARIABLE(cm_lr);
PH_UNUSED_VARIABLE(cm_pc);
PH_UNUSED_VARIABLE(cm_psr);
}
/* Break into the debugger */
__asm("BKPT #0\n");
while (1)
{
__asm("wfi\n");
}
}
__attribute__ ((section(".after_vectors")))
void MemManage_Handler(void)
{ while(1) {}
}
__attribute__ ((section(".after_vectors")))
void BusFault_Handler(void)
{ while(1) {}
}
__attribute__ ((section(".after_vectors")))
void UsageFault_Handler(void)
{ while(1) {}
}
__attribute__ ((section(".after_vectors")))
void SVC_Handler(void)
{ while(1) {}
}
__attribute__ ((section(".after_vectors")))
void DebugMon_Handler(void)
{ while(1) {}
}
__attribute__ ((section(".after_vectors")))
void PendSV_Handler(void)
{ while(1) {}
}
//*****************************************************************************
//
// Processor ends up here if an unexpected interrupt occurs or a specific
// handler is not present in the application code.
//
//*****************************************************************************
__attribute__ ((section(".after_vectors")))
void IntDefaultHandler(void)
{ while(1) {}
}

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@ -0,0 +1,375 @@
/*----------------------------------------------------------------------------*/
/* Copyright 2020 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may only */
/* be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that you */
/* have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*----------------------------------------------------------------------------*/
/** \file
* Example Source abstracting component data structure and code initialization and code specific to HW used in the examples
* This file shall be present in all examples. A customer does not need to touch/modify this file. This file
* purely depends on the phNxpBuild_Lpc.h or phNxpBuild_App.h
* The phAppInit.h externs the component data structures initialized here that is in turn included by the core examples.
* The core example shall not use any other variable defined here except the RdLib component data structures(as explained above)
* The RdLib component initialization requires some user defined data and function pointers.
* These are defined in the respective examples and externed here.
*
* Keystore and Crypto initialization needs to be handled by application.
*
* $Author$
* $Revision$ (v07.10.00)
* $Date$
*
*/
#include "phApp_Init.h"
#include <phOsal.h>
/*******************************************************************************
** Function Declarations
*******************************************************************************/
/*******************************************************************************
** Function Definitions
*******************************************************************************/
/* Print technology being resolved */
void phApp_PrintTech(uint8_t TechType)
{
switch(TechType)
{
case PHAC_DISCLOOP_POS_BIT_MASK_A:
DEBUG_PRINTF ("\tResolving Type A... \n");
break;
case PHAC_DISCLOOP_POS_BIT_MASK_B:
DEBUG_PRINTF ("\tResolving Type B... \n");
break;
case PHAC_DISCLOOP_POS_BIT_MASK_F212:
DEBUG_PRINTF ("\tResolving Type F with baud rate 212... \n");
break;
case PHAC_DISCLOOP_POS_BIT_MASK_F424:
DEBUG_PRINTF ("\tResolving Type F with baud rate 424... \n");
break;
case PHAC_DISCLOOP_POS_BIT_MASK_V:
DEBUG_PRINTF ("\tResolving Type V... \n");
break;
default:
break;
}
}
/**
* This function will print buffer content
* \param *pBuff Buffer Reference
* \param num data size to be print
*/
void phApp_Print_Buff(uint8_t *pBuff, uint8_t num)
{
uint32_t i;
for(i = 0; i < num; i++)
{
DEBUG_PRINTF(" %02X",pBuff[i]);
}
}
/**
* This function will print Tag information
* \param pDataParams The discovery loop data parameters
* \param wNumberOfTags Total number of tags detected
* \param wTagsDetected Technology Detected
*/
void phApp_PrintTagInfo(phacDiscLoop_Sw_DataParams_t *pDataParams, uint16_t wNumberOfTags, uint16_t wTagsDetected)
{
#if defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_TAGS) || \
defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_P2P_ACTIVE) || \
defined(NXPBUILD__PHAC_DISCLOOP_TYPEB_TAGS) || \
defined(NXPBUILD__PHAC_DISCLOOP_TYPEF_TAGS) || \
defined(NXPBUILD__PHAC_DISCLOOP_TYPEV_TAGS) || \
defined(NXPBUILD__PHAC_DISCLOOP_I18000P3M3_TAGS)
uint8_t bIndex;
#endif
#if defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_TAGS) || defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_P2P_ACTIVE)
uint8_t bTagType;
#endif
#if defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_TAGS) || defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_P2P_ACTIVE)
if (PHAC_DISCLOOP_CHECK_ANDMASK(wTagsDetected, PHAC_DISCLOOP_POS_BIT_MASK_A))
{
if(pDataParams->sTypeATargetInfo.bT1TFlag)
{
DEBUG_PRINTF("\tTechnology : Type A");
DEBUG_PRINTF ("\n\t\tUID :");
phApp_Print_Buff( pDataParams->sTypeATargetInfo.aTypeA_I3P3[0].aUid,
pDataParams->sTypeATargetInfo.aTypeA_I3P3[0].bUidSize);
DEBUG_PRINTF ("\n\t\tSAK : 0x%02x",pDataParams->sTypeATargetInfo.aTypeA_I3P3[0].aSak);
DEBUG_PRINTF ("\n\t\tType: Type 1 Tag\n");
}
else
{
DEBUG_PRINTF("\tTechnology : Type A");
for(bIndex = 0; bIndex < wNumberOfTags; bIndex++)
{
DEBUG_PRINTF ("\n\t\tCard: %d",bIndex + 1);
DEBUG_PRINTF ("\n\t\tUID :");
phApp_Print_Buff( pDataParams->sTypeATargetInfo.aTypeA_I3P3[bIndex].aUid,
pDataParams->sTypeATargetInfo.aTypeA_I3P3[bIndex].bUidSize);
DEBUG_PRINTF ("\n\t\tSAK : 0x%02x",pDataParams->sTypeATargetInfo.aTypeA_I3P3[bIndex].aSak);
if ((pDataParams->sTypeATargetInfo.aTypeA_I3P3[bIndex].aSak & (uint8_t) ~0xFB) == 0)
{
/* Bit b3 is set to zero, [Digital] 4.8.2 */
/* Mask out all other bits except for b7 and b6 */
bTagType = (pDataParams->sTypeATargetInfo.aTypeA_I3P3[bIndex].aSak & 0x60);
bTagType = bTagType >> 5;
switch(bTagType)
{
case PHAC_DISCLOOP_TYPEA_TYPE2_TAG_CONFIG_MASK:
DEBUG_PRINTF ("\n\t\tType: Type 2 Tag\n");
break;
case PHAC_DISCLOOP_TYPEA_TYPE4A_TAG_CONFIG_MASK:
DEBUG_PRINTF ("\n\t\tType: Type 4A Tag\n");
break;
case PHAC_DISCLOOP_TYPEA_TYPE_NFC_DEP_TAG_CONFIG_MASK:
DEBUG_PRINTF ("\n\t\tType: P2P\n");
break;
case PHAC_DISCLOOP_TYPEA_TYPE_NFC_DEP_TYPE4A_TAG_CONFIG_MASK:
DEBUG_PRINTF ("\n\t\tType: Type NFC_DEP and 4A Tag\n");
break;
default:
break;
}
}
}
}
}
#endif
#ifdef NXPBUILD__PHAC_DISCLOOP_TYPEB_TAGS
if (PHAC_DISCLOOP_CHECK_ANDMASK(wTagsDetected, PHAC_DISCLOOP_POS_BIT_MASK_B))
{
DEBUG_PRINTF("\tTechnology : Type B");
/* Loop through all the Type B tags detected and print the Pupi */
for (bIndex = 0; bIndex < wNumberOfTags; bIndex++)
{
DEBUG_PRINTF ("\n\t\tCard: %d",bIndex + 1);
DEBUG_PRINTF ("\n\t\tUID :");
/* PUPI Length is always 4 bytes */
phApp_Print_Buff( pDataParams->sTypeBTargetInfo.aTypeB_I3P3[bIndex].aPupi, 0x04);
}
DEBUG_PRINTF("\n");
}
#endif /* NXPBUILD__PHAC_DISCLOOP_TYPEB_TAGS */
#ifdef NXPBUILD__PHAC_DISCLOOP_TYPEF_TAGS
if( PHAC_DISCLOOP_CHECK_ANDMASK(wTagsDetected, PHAC_DISCLOOP_POS_BIT_MASK_F212) ||
PHAC_DISCLOOP_CHECK_ANDMASK(wTagsDetected, PHAC_DISCLOOP_POS_BIT_MASK_F424))
{
DEBUG_PRINTF("\tTechnology : Type F");
/* Loop through all the type F tags and print the IDm */
for (bIndex = 0; bIndex < wNumberOfTags; bIndex++)
{
DEBUG_PRINTF ("\n\t\tCard: %d",bIndex + 1);
DEBUG_PRINTF ("\n\t\tUID :");
phApp_Print_Buff( pDataParams->sTypeFTargetInfo.aTypeFTag[bIndex].aIDmPMm,
PHAC_DISCLOOP_FELICA_IDM_LENGTH );
if ((pDataParams->sTypeFTargetInfo.aTypeFTag[bIndex].aIDmPMm[0] == 0x01) &&
(pDataParams->sTypeFTargetInfo.aTypeFTag[bIndex].aIDmPMm[1] == 0xFE))
{
/* This is Type F tag with P2P capabilities */
DEBUG_PRINTF ("\n\t\tType: P2P");
}
else
{
/* This is Type F T3T tag */
DEBUG_PRINTF ("\n\t\tType: Type 3 Tag");
}
if(pDataParams->sTypeFTargetInfo.aTypeFTag[bIndex].bBaud != PHAC_DISCLOOP_CON_BITR_212)
{
DEBUG_PRINTF ("\n\t\tBit Rate: 424\n");
}
else
{
DEBUG_PRINTF ("\n\t\tBit Rate: 212\n");
}
}
}
#endif /* NXPBUILD__PHAC_DISCLOOP_TYPEF_TAGS */
#ifdef NXPBUILD__PHAC_DISCLOOP_TYPEV_TAGS
if (PHAC_DISCLOOP_CHECK_ANDMASK(wTagsDetected, PHAC_DISCLOOP_POS_BIT_MASK_V))
{
DEBUG_PRINTF("\tTechnology : Type V / ISO 15693 / T5T");
/* Loop through all the Type V tags detected and print the UIDs */
for (bIndex = 0; bIndex < wNumberOfTags; bIndex++)
{
DEBUG_PRINTF ("\n\t\tCard: %d",bIndex + 1);
DEBUG_PRINTF ("\n\t\tUID :");
phApp_Print_Buff( pDataParams->sTypeVTargetInfo.aTypeV[bIndex].aUid, 0x08);
}
DEBUG_PRINTF("\n");
}
#endif /* NXPBUILD__PHAC_DISCLOOP_TYPEV_TAGS */
#ifdef NXPBUILD__PHAC_DISCLOOP_I18000P3M3_TAGS
if (PHAC_DISCLOOP_CHECK_ANDMASK(wTagsDetected, PHAC_DISCLOOP_POS_BIT_MASK_18000P3M3))
{
DEBUG_PRINTF("\tTechnology : ISO 18000p3m3 / EPC Gen2");
/* Loop through all the 18000p3m3 tags detected and print the UII */
for (bIndex = 0; bIndex < wNumberOfTags; bIndex++)
{
DEBUG_PRINTF("\n\t\tCard: %d",bIndex + 1);
DEBUG_PRINTF("\n\t\tUII :");
phApp_Print_Buff(
pDataParams->sI18000p3m3TargetInfo.aI18000p3m3[bIndex].aUii,
(pDataParams->sI18000p3m3TargetInfo.aI18000p3m3[bIndex].wUiiLength / 8));
}
DEBUG_PRINTF("\n");
}
#endif /* NXPBUILD__PHAC_DISCLOOP_I18000P3M3_TAGS */
}
/**
* This function will print Error information received from Reader Lib
* \param wStatus Error status
*/
void PrintErrorInfo(phStatus_t wStatus)
{
DEBUG_PRINTF("\n ErrorInfo Comp:");
switch(wStatus & 0xFF00)
{
case PH_COMP_BAL:
DEBUG_PRINTF("\t PH_COMP_BAL");
break;
case PH_COMP_HAL:
DEBUG_PRINTF("\t PH_COMP_HAL");
break;
case PH_COMP_PAL_ISO14443P3A:
DEBUG_PRINTF("\t PH_COMP_PAL_ISO14443P3A");
break;
case PH_COMP_PAL_ISO14443P3B:
DEBUG_PRINTF("\t PH_COMP_PAL_ISO14443P3B");
break;
case PH_COMP_PAL_ISO14443P4A:
DEBUG_PRINTF("\t PH_COMP_PAL_ISO14443P4A");
break;
case PH_COMP_PAL_ISO14443P4:
DEBUG_PRINTF("\t PH_COMP_PAL_ISO14443P4");
break;
case PH_COMP_PAL_FELICA:
DEBUG_PRINTF("\t PH_COMP_PAL_FELICA");
break;
case PH_COMP_PAL_EPCUID:
DEBUG_PRINTF("\t PH_COMP_PAL_EPCUID");
break;
case PH_COMP_PAL_SLI15693:
DEBUG_PRINTF("\t PH_COMP_PAL_SLI15693");
break;
case PH_COMP_PAL_I18000P3M3:
DEBUG_PRINTF("\t PH_COMP_PAL_I18000P3M3");
break;
case PH_COMP_PAL_I18092MPI:
DEBUG_PRINTF("\t PH_COMP_PAL_I18092MPI");
break;
case PH_COMP_PAL_I18092MT:
DEBUG_PRINTF("\t PH_COMP_PAL_I18092MT");
break;
case PH_COMP_PAL_I14443P4MC:
DEBUG_PRINTF("\t PH_COMP_PAL_I14443P4MC");
break;
case PH_COMP_AC_DISCLOOP:
DEBUG_PRINTF("\t PH_COMP_AC_DISCLOOP");
break;
case PH_COMP_OSAL:
DEBUG_PRINTF("\t PH_COMP_OSAL");
break;
default:
DEBUG_PRINTF("\t 0x%x",(wStatus & PH_COMPID_MASK));
break;
}
DEBUG_PRINTF("\t type:");
switch(wStatus & PH_ERR_MASK)
{
case PH_ERR_SUCCESS_INCOMPLETE_BYTE:
DEBUG_PRINTF("\t PH_ERR_SUCCESS_INCOMPLETE_BYTE");
break;
case PH_ERR_IO_TIMEOUT:
DEBUG_PRINTF("\t PH_ERR_IO_TIMEOUT");
break;
case PH_ERR_INTEGRITY_ERROR:
DEBUG_PRINTF("\t PH_ERR_INTEGRITY_ERROR");
break;
case PH_ERR_COLLISION_ERROR:
DEBUG_PRINTF("\t PH_ERR_COLLISION_ERROR");
break;
case PH_ERR_BUFFER_OVERFLOW:
DEBUG_PRINTF("\t PH_ERR_BUFFER_OVERFLOW");
break;
case PH_ERR_FRAMING_ERROR:
DEBUG_PRINTF("\t PH_ERR_FRAMING_ERROR");
break;
case PH_ERR_PROTOCOL_ERROR:
DEBUG_PRINTF("\t PH_ERR_PROTOCOL_ERROR");
break;
case PH_ERR_RF_ERROR:
DEBUG_PRINTF("\t PH_ERR_RF_ERROR");
break;
case PH_ERR_EXT_RF_ERROR:
DEBUG_PRINTF("\t PH_ERR_EXT_RF_ERROR");
break;
case PH_ERR_NOISE_ERROR:
DEBUG_PRINTF("\t PH_ERR_NOISE_ERROR");
break;
case PH_ERR_ABORTED:
DEBUG_PRINTF("\t PH_ERR_ABORTED");
break;
case PH_ERR_INTERNAL_ERROR:
DEBUG_PRINTF("\t PH_ERR_INTERNAL_ERROR");
break;
case PH_ERR_INVALID_DATA_PARAMS:
DEBUG_PRINTF("\t PH_ERR_INVALID_DATA_PARAMS");
break;
case PH_ERR_INVALID_PARAMETER:
DEBUG_PRINTF("\t PH_ERR_INVALID_PARAMETER");
break;
case PH_ERR_PARAMETER_OVERFLOW:
DEBUG_PRINTF("\t PH_ERR_PARAMETER_OVERFLOW");
break;
case PH_ERR_UNSUPPORTED_PARAMETER:
DEBUG_PRINTF("\t PH_ERR_UNSUPPORTED_PARAMETER");
break;
case PH_ERR_OSAL_ERROR:
DEBUG_PRINTF("\t PH_ERR_OSAL_ERROR");
break;
case PHAC_DISCLOOP_LPCD_NO_TECH_DETECTED:
DEBUG_PRINTF("\t PHAC_DISCLOOP_LPCD_NO_TECH_DETECTED");
break;
case PHAC_DISCLOOP_COLLISION_PENDING:
DEBUG_PRINTF("\t PHAC_DISCLOOP_COLLISION_PENDING");
break;
default:
DEBUG_PRINTF("\t 0x%x",(wStatus & PH_ERR_MASK));
break;
}
}
/******************************************************************************
** End Of File
******************************************************************************/

View File

@ -0,0 +1,438 @@
/*----------------------------------------------------------------------------*/
/* Copyright 2016-2022 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may only */
/* be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that you */
/* have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*----------------------------------------------------------------------------*/
/** \file
* Example Source abstracting component data structure and code initialization and code specific to HW used in the examples
* This file shall be present in all examples. A customer does not need to touch/modify this file. This file
* purely depends on the phNxpBuild_Lpc.h or phNxpBuild_App.h
* The phAppInit.h externs the component data structures initialized here that is in turn included by the core examples.
* The core example shall not use any other variable defined here except the RdLib component data structures(as explained above)
* The RdLib component initialization requires some user defined data and function pointers.
* These are defined in the respective examples and externed here.
*
* Keystore and Crypto initialization needs to be handled by application.
*
* $Author: NXP$
* $Revision: $ (v07.10.00)
* $Date: $
*
*/
/* Status header */
#include <ph_Status.h>
#include "phApp_Init.h"
/* LLCP header */
#include <phlnLlcp.h>
#include <phOsal.h>
#ifdef PH_PLATFORM_HAS_ICFRONTEND
#include "BoardSelection.h"
#endif /* PH_PLATFORM_HAS_ICFRONTEND */
#ifdef PHDRIVER_KINETIS_K82
#include <fsl_port.h>
#include <fsl_pit.h>
#ifdef DEBUG
#include <fsl_clock.h>
#endif /* DEBUG */
#endif /* PHDRIVER_KINETIS_K82 */
#ifdef PHDRIVER_KINETIS_K82
#ifdef DEBUG
#define KINETIS_K82_DEBUG_UART_CLK_FREQ CLOCK_GetOsc0ErClkFreq()
#define KINETIS_K82_DEBUG_UART_BASEADDR (uint32_t)(LPUART4)
#define KINETIS_K82_DEBUG_UART_INSTANCE 4U
#define KINETIS_K82_DEBUG_UART_BAUDRATE 115200
#define KINETIS_K82_DEBUG_UART_TYPE DEBUG_CONSOLE_DEVICE_TYPE_LPUART
#endif /* DEBUG */
/*! @brief Clock configuration structure. */
typedef struct _clock_config
{
mcg_config_t mcgConfig; /*!< MCG configuration. */
sim_clock_config_t simConfig; /*!< SIM configuration. */
osc_config_t oscConfig; /*!< OSC configuration. */
uint32_t coreClock; /*!< core clock frequency. */
} clock_config_t;
#endif /* PHDRIVER_KINETIS_K82 */
#ifdef PH_OSAL_LINUX
# define PI_IRQ_POLLING_TASK_PRIO 0
# define PI_IRQ_POLLING_TASK_STACK 0x20000
phOsal_ThreadObj_t gphPiThreadObj;
#endif /* PH_OSAL_LINUX */
#if defined(PHDRIVER_LPC1769) && defined(__CC_ARM)
uint32_t SystemCoreClock;
#endif
/*******************************************************************************
** Function Declarations
*******************************************************************************/
#ifdef PHDRIVER_KINETIS_K82
static void phApp_K82_Init(void);
#endif /* PHDRIVER_KINETIS_K82 */
#ifdef PH_OSAL_LINUX
static void phExample_IrqPolling(void* param);
#endif /* PH_OSAL_LINUX */
phStatus_t phApp_Configure_IRQ();
/*******************************************************************************
** Clock configuration of K82 Platform
*******************************************************************************/
#ifdef PHDRIVER_KINETIS_K82
/* Configuration for enter RUN mode. Core clock = 50MHz. */
const clock_config_t g_defaultClockConfigRun = {
.mcgConfig =
{
.mcgMode = kMCG_ModePEE, /* Work in PEE mode. */
.irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enable. */
.ircs = kMCG_IrcSlow, /* Select IRC32k. */
.fcrdiv = 0U, /* FCRDIV is 0. */
.frdiv = 4U,
.drs = kMCG_DrsLow, /* Low frequency range. */
.dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25%. */
.oscsel = kMCG_OscselOsc, /* Select OSC. */
.pll0Config =
{
.enableMode = 0U, .prdiv = 0x01U, .vdiv = 0x01U,
},
},
.simConfig =
{
.pllFllSel = 1U, /* PLLFLLSEL select PLL. */
.pllFllDiv = 0U, /* PLLFLLSEL clock divider divisor. */
.pllFllFrac = 0U, /* PLLFLLSEL clock divider fraction. */
.er32kSrc = 5U, /* ERCLK32K selection, use RTC. */
.clkdiv1 = 0x01140000U, /* SIM_CLKDIV1. */
},
.oscConfig = {.freq = CPU_XTAL_CLK_HZ,
.capLoad = 0,
.workMode = kOSC_ModeOscLowPower,
.oscerConfig =
{
.enableMode = kOSC_ErClkEnable,
#if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER)
.erclkDiv = 0U,
#endif
}},
};
#endif /* PHDRIVER_KINETIS_K82 */
/*******************************************************************************
** Global Variable Declaration
*******************************************************************************/
#ifdef NXPBUILD__PHLN_LLCP_SW
phlnLlcp_Sw_DataParams_t slnLlcp; /* LLCP component */
#endif /* NXPBUILD__PHLN_LLCP_SW */
/* General information bytes to be sent with ATR Request */
#if defined(NXPBUILD__PHPAL_I18092MPI_SW) || defined(NXPBUILD__PHPAL_I18092MT_SW)
uint8_t aLLCPGeneralBytes[36] = { 0x46,0x66,0x6D,
0x01,0x01,0x10, /*VERSION*/
0x03,0x02,0x00,0x01, /*WKS*/
0x04,0x01,0xF1 /*LTO*/
};
uint8_t bLLCPGBLength = 13;
#endif
/* ATR Response or ATS Response holder */
#if defined(NXPBUILD__PHPAL_I14443P4A_SW) || \
defined(NXPBUILD__PHPAL_I18092MPI_SW)
uint8_t aResponseHolder[64];
#endif
/* prints if error is detected */
#define CHECK_SUCCESS(x) \
if ((x) != PH_ERR_SUCCESS) \
{ \
DEBUG_PRINTF("\nLine: %d Error - (0x%04X) has occurred : 0xCCEE CC-Component ID, EE-Error code. Refer-ph_Status.h\n ", __LINE__, (x)); \
return (x); \
}
/*******************************************************************************
** Function Definitions
*******************************************************************************/
#ifdef PHDRIVER_KINETIS_K82
static void phApp_K82_Init(void)
{
#ifdef DEBUG
uint32_t uartClkSrcFreq;
#endif /* DEBUG */
pit_config_t pitConfig; /* Structure of initialize PIT */
CLOCK_SetSimSafeDivs();
CLOCK_InitOsc0(&g_defaultClockConfigRun.oscConfig);
CLOCK_SetXtal0Freq(CPU_XTAL_CLK_HZ);
CLOCK_BootToPeeMode(g_defaultClockConfigRun.mcgConfig.oscsel, kMCG_PllClkSelPll0,
&g_defaultClockConfigRun.mcgConfig.pll0Config);
CLOCK_SetInternalRefClkConfig(g_defaultClockConfigRun.mcgConfig.irclkEnableMode,
g_defaultClockConfigRun.mcgConfig.ircs, g_defaultClockConfigRun.mcgConfig.fcrdiv);
CLOCK_SetSimConfig(&g_defaultClockConfigRun.simConfig);
SystemCoreClockUpdate();
/*
* pitConfig.enableRunInDebug = false;
*/
PIT_GetDefaultConfig(&pitConfig);
/* Init pit module */
PIT_Init(PIT, &pitConfig);
#ifdef DEBUG
/* Initialize LPUART4 pins below used to Print */
/* Ungate the port clock */
CLOCK_EnableClock(kCLOCK_PortC);
/* Affects PORTC_PCR14 register */
PORT_SetPinMux(PORTC, 14U, kPORT_MuxAlt3);
/* Affects PORTC_PCR15 register */
PORT_SetPinMux(PORTC, 15U, kPORT_MuxAlt3);
/* SIM_SOPT2[27:26]:
* 00: Clock Disabled
* 01: MCGFLLCLK, or MCGPLLCLK, or IRC48M
* 10: OSCERCLK
* 11: MCGIRCCLK
*/
CLOCK_SetLpuartClock(2);
uartClkSrcFreq = KINETIS_K82_DEBUG_UART_CLK_FREQ;
DbgConsole_Init(KINETIS_K82_DEBUG_UART_INSTANCE, KINETIS_K82_DEBUG_UART_BAUDRATE, KINETIS_K82_DEBUG_UART_TYPE, uartClkSrcFreq);
#endif /* DEBUG */
}
#endif /* PHDRIVER_KINETIS_K82 */
#ifdef PH_PLATFORM_HAS_ICFRONTEND
/**
* This function will initialize Host Controller interfaced with NXP Reader IC's.
* Any initialization which is not generic across Platforms, should be done here.
* Note: For NXP NFC Controllers HOST initialization is not required.
*/
void phApp_CPU_Init(void)
{
#if defined PHDRIVER_KINETIS_K82
phApp_K82_Init();
#elif defined(PHDRIVER_LPC1769) && defined(__CC_ARM)
SystemCoreClock = (( unsigned long ) 96000000);
#elif defined(PH_OSAL_LINUX) && defined(NXPBUILD__PHHAL_HW_PN5190)
phStatus_t status;
status = PiGpio_OpenIrq();
if ((status & PH_ERR_MASK) != PH_ERR_SUCCESS)
{
DEBUG_PRINTF("\n PiGpio_OpenIrq failed \n");
DEBUG_PRINTF("\n Couldn't open PN5190 Kernel IRQ Driver.\n Halting here!!FIX IT!!\n");
while(1);
}
#else
/* In case of LPC series, startup file takes care of initializing clock and ports.
* No initialization is required in Linux environment. */
#endif /* PHDRIVER_KINETIS_K82 */
}
#endif /* PH_PLATFORM_HAS_ICFRONTEND */
/**
* This function will initialize Reader LIbrary Component
*/
phStatus_t phApp_Comp_Init(void * pDiscLoopParams)
{
phStatus_t wStatus = PH_ERR_SUCCESS;
#if defined(NXPBUILD__PHPAL_I18092MPI_SW) || defined(NXPBUILD__PHPAL_I18092MT_SW) || \
defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_P2P_TAGS) || defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_P2P_ACTIVE) || \
defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_I3P4_TAGS) || defined(NXPBUILD__PHAC_DISCLOOP_TYPEF_P2P_TAGS) || \
defined(NXPBUILD__PHAC_DISCLOOP_TYPEF212_P2P_ACTIVE) || defined(NXPBUILD__PHAC_DISCLOOP_TYPEF424_P2P_ACTIVE)
phacDiscLoop_Sw_DataParams_t * pDiscLoop = (phacDiscLoop_Sw_DataParams_t *)pDiscLoopParams;
#endif
/* Initialize the LLCP component */
#ifdef NXPBUILD__PHLN_LLCP_SW
slnLlcp.sLocalLMParams.wMiu = 0x00; /* 128 bytes only */
slnLlcp.sLocalLMParams.wWks = 0x11; /* SNEP & LLCP */
slnLlcp.sLocalLMParams.bLto = 100; /* Maximum LTO */
slnLlcp.sLocalLMParams.bOpt = 0x02;
slnLlcp.sLocalLMParams.bAvailableTlv = PHLN_LLCP_TLV_MIUX_MASK | PHLN_LLCP_TLV_WKS_MASK |
PHLN_LLCP_TLV_LTO_MASK | PHLN_LLCP_TLV_OPT_MASK;
wStatus = phlnLlcp_Sw_Init(
&slnLlcp,
sizeof(phlnLlcp_Sw_DataParams_t),
aLLCPGeneralBytes,
&bLLCPGBLength);
#endif /* NXPBUILD__PHLN_LLCP_SW */
#ifdef NXPBUILD__PHAC_DISCLOOP_SW
#if defined(NXPBUILD__PHPAL_I18092MPI_SW) || defined(NXPBUILD__PHPAL_I18092MT_SW)
/* Assign the GI for Type A */
pDiscLoop->sTypeATargetInfo.sTypeA_P2P.pGi = (uint8_t *)aLLCPGeneralBytes;
pDiscLoop->sTypeATargetInfo.sTypeA_P2P.bGiLength = bLLCPGBLength;
/* Assign the GI for Type F */
pDiscLoop->sTypeFTargetInfo.sTypeF_P2P.pGi = (uint8_t *)aLLCPGeneralBytes;
pDiscLoop->sTypeFTargetInfo.sTypeF_P2P.bGiLength = bLLCPGBLength;
#endif /* NXPBUILD__PHAC_DISCLOOP_SW */
#if defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_P2P_TAGS) || defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_P2P_ACTIVE)
/* Assign ATR response for Type A */
pDiscLoop->sTypeATargetInfo.sTypeA_P2P.pAtrRes = aResponseHolder;
#endif
#if defined(NXPBUILD__PHAC_DISCLOOP_TYPEF_P2P_TAGS) || defined(NXPBUILD__PHAC_DISCLOOP_TYPEF212_P2P_ACTIVE) || \
defined(NXPBUILD__PHAC_DISCLOOP_TYPEF424_P2P_ACTIVE)
/* Assign ATR response for Type F */
pDiscLoop->sTypeFTargetInfo.sTypeF_P2P.pAtrRes = aResponseHolder;
#endif
#ifdef NXPBUILD__PHAC_DISCLOOP_TYPEA_I3P4_TAGS
/* Assign ATS buffer for Type A */
pDiscLoop->sTypeATargetInfo.sTypeA_I3P4.pAts = aResponseHolder;
#endif /* NXPBUILD__PHAC_DISCLOOP_TYPEA_I3P4_TAGS */
#endif /* NXPBUILD__PHAC_DISCLOOP_SW */
return wStatus;
}
phStatus_t phApp_Configure_IRQ()
{
#ifdef PH_OSAL_LINUX
phStatus_t wStatus;
#endif /* PH_OSAL_LINUX */
#ifdef PH_PLATFORM_HAS_ICFRONTEND
#if !(defined(PH_OSAL_LINUX) && defined(NXPBUILD__PHHAL_HW_PN5190))
phDriver_Pin_Config_t pinCfg;
pinCfg.bOutputLogic = PH_DRIVER_SET_LOW;
pinCfg.bPullSelect = PHDRIVER_PIN_IRQ_PULL_CFG;
pinCfg.eInterruptConfig = PIN_IRQ_TRIGGER_TYPE;
phDriver_PinConfig(PHDRIVER_PIN_IRQ, PH_DRIVER_PINFUNC_INTERRUPT, &pinCfg);
#endif
#ifdef PHDRIVER_LPC1769
NVIC_SetPriority(EINT_IRQn, EINT_PRIORITY);
/* Enable interrupt in the NVIC */
NVIC_ClearPendingIRQ(EINT_IRQn);
NVIC_EnableIRQ(EINT_IRQn);
#endif /* PHDRIVER_LPC1769 */
#ifdef PH_OSAL_LINUX
gphPiThreadObj.pTaskName = (uint8_t *) "IrqPolling";
gphPiThreadObj.pStackBuffer = NULL;
gphPiThreadObj.priority = PI_IRQ_POLLING_TASK_PRIO;
gphPiThreadObj.stackSizeInNum = PI_IRQ_POLLING_TASK_STACK;
PH_CHECK_SUCCESS_FCT(wStatus, phOsal_ThreadCreate(&gphPiThreadObj.ThreadHandle, &gphPiThreadObj,
&phExample_IrqPolling, NULL));
#endif /* PH_OSAL_LINUX */
#ifdef PHDRIVER_KINETIS_K82
NVIC_SetPriority(EINT_IRQn, EINT_PRIORITY);
NVIC_ClearPendingIRQ(EINT_IRQn);
EnableIRQ(EINT_IRQn);
#endif /* PHDRIVER_KINETIS_K82 */
#endif /* #ifdef PH_PLATFORM_HAS_ICFRONTEND */
return PH_ERR_SUCCESS;
}
#ifdef PH_OSAL_LINUX
/*
* \brief: The purpose of this Thread is to detect RF signal from an External Peer .
*/
static void phExample_IrqPolling(void* param)
{
uint8_t bgpioVal = 0;
uint8_t bhighOrLow = 0;
#if defined(NXPBUILD__PHHAL_HW_RC663) || defined(NXPBUILD__PHHAL_HW_PN5180)
if(PIN_IRQ_TRIGGER_TYPE == PH_DRIVER_INTERRUPT_RISINGEDGE)
{
bhighOrLow = 1;
}
while(PiGpio_read(PHDRIVER_PIN_IRQ, &bgpioVal) != PH_ERR_SUCCESS)
{
PiGpio_unexport(PHDRIVER_PIN_IRQ);
PiGpio_export(PHDRIVER_PIN_IRQ);
PiGpio_set_direction(PHDRIVER_PIN_IRQ, false);
if(PIN_IRQ_TRIGGER_TYPE == PH_DRIVER_INTERRUPT_RISINGEDGE)
{
PiGpio_set_edge(PHDRIVER_PIN_IRQ, true, false);
}
else
{
PiGpio_set_edge(PHDRIVER_PIN_IRQ, false, true);
}
}
/* Initial status: If pin is already Active, post an event. */
if(bgpioVal == bhighOrLow)
{
CLIF_IRQHandler();
}
#endif
while(1)
{
/* Block forever for Raising Edge in PHDRIVER_PIN_IRQ. */
#if defined(NXPBUILD__PHHAL_HW_RC663) || defined(NXPBUILD__PHHAL_HW_PN5180)
if(PiGpio_poll(PHDRIVER_PIN_IRQ, bhighOrLow, -1) == PH_ERR_SUCCESS)
#elif defined(NXPBUILD__PHHAL_HW_PN5190)
if(PiGpio_Irq() == PH_ERR_SUCCESS)
#endif
{
CLIF_IRQHandler();
}
else
{
PiGpio_unexport(PHDRIVER_PIN_IRQ);
PiGpio_export(PHDRIVER_PIN_IRQ);
PiGpio_set_direction(PHDRIVER_PIN_IRQ, false);
if(PIN_IRQ_TRIGGER_TYPE == PH_DRIVER_INTERRUPT_RISINGEDGE)
{
PiGpio_set_edge(PHDRIVER_PIN_IRQ, true, false);
}
else
{
PiGpio_set_edge(PHDRIVER_PIN_IRQ, false, true);
}
}
}
}
#endif /* PH_OSAL_LINUX */
/******************************************************************************
** End Of File
******************************************************************************/

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/*----------------------------------------------------------------------------*/
/* Copyright 2020,2023 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may only */
/* be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that you */
/* have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*----------------------------------------------------------------------------*/
/** \file
* Example Source abstracting component data structure and code initialization and code specific to HW used in the examples
* This file shall be present in all examples. A customer does not need to touch/modify this file. This file
* purely depends on the phNxpBuild_Lpc.h or phNxpBuild_App.h
* The phAppInit.h externs the component data structures initialized here that is in turn included by the core examples.
* The core example shall not use any other variable defined here except the RdLib component data structures(as explained above)
* The RdLib component initialization requires some user defined data and function pointers.
* These are defined in the respective examples and externed here.
*
* Keystore and Crypto initialization needs to be handled by application.
*
* $Author$
* $Revision$ (v07.10.00)
* $Date$
*
*/
/* Status header */
#include <ph_Status.h>
#include "phApp_Init.h"
#ifdef NXPBUILD__PHHAL_HW_PN5180
#include "BoardSelection.h"
/* HAL specific headers */
#include <phhalHw_Pn5180_Instr.h>
/*******************************************************************************
** Function Declarations
*******************************************************************************/
/*******************************************************************************
** Global Variable Declaration
*******************************************************************************/
phbalReg_Type_t sBalParams;
phhalHw_Pn5180_DataParams_t * pHal;
#ifdef NXPBUILD__PHHAL_HW_TARGET
/* Parameters for L3 activation during Autocoll */
extern uint8_t sens_res[2U] ;
extern uint8_t nfc_id1[3U] ;
extern uint8_t sel_res ;
extern uint8_t nfc_id3 ;
extern uint8_t poll_res[18U] ;
#endif /* NXPBUILD__PHHAL_HW_TARGET */
/*******************************************************************************
** Function Definitions
*******************************************************************************/
/**
* This function will initialize Hal Target Config
*/
phStatus_t phApp_HALConfigAutoColl(void)
{
#ifdef NXPBUILD__PHHAL_HW_TARGET
phStatus_t wStatus;
uint8_t baDynamicUidConfig[1U] = { 1U };
uint8_t baReadEepromConfig[24U] = { 0U };
/* Read Set Listen Parameters data from EEPROM */
wStatus = phhalHw_Pn5180_Instr_ReadE2Prom(
pHal,
PHHAL_HW_PN5180_SET_LISTEN_E2PROM_ADDR,
baReadEepromConfig,
24U
);
CHECK_SUCCESS(wStatus);
/* Verify EEPROM data and configure Set Listen Parameters if EEPROM data is not correct. */
if ((memcmp(&baReadEepromConfig[0U], sens_res, 2U) != 0x00) ||
(memcmp(&baReadEepromConfig[2U], nfc_id1, 3U) != 0x00) ||
(memcmp(&baReadEepromConfig[5U], &sel_res, 1U) != 0x00) ||
(memcmp(&baReadEepromConfig[6U], poll_res, 18U) != 0x00))
{
/* Configure Set Listen Parameters. */
wStatus = phhalHw_Pn5180_SetListenParameters(
pHal,
&sens_res[0],
&nfc_id1[0],
sel_res,
&poll_res[0],
nfc_id3
);
CHECK_SUCCESS(wStatus);
}
if (pHal->wFirmwareVer < 0x308U)
{
/* With Pn5180 FW version < 3.8, only static UID is supported. */
baDynamicUidConfig[0] = 0x00;
}
/* Read Dynamic UID configuration from EEPROM */
wStatus = phhalHw_Pn5180_Instr_ReadE2Prom(
pHal,
PHHAL_HW_PN5180_DYN_UID_CFG_E2PROM_ADDR,
baReadEepromConfig,
1U
);
CHECK_SUCCESS(wStatus);
/* Verify EEPROM data and perform Dynamic UID configuration if EEPROM data is not correct. */
if (memcmp(baReadEepromConfig, baDynamicUidConfig, 1U) != 0x00)
{
/* Configure Dynamic UID */
wStatus = phhalHw_Pn5180_Instr_WriteE2Prom(
pHal,
PHHAL_HW_PN5180_DYN_UID_CFG_E2PROM_ADDR,
baDynamicUidConfig,
1U
);
CHECK_SUCCESS(wStatus);
}
#endif /* NXPBUILD__PHHAL_HW_TARGET */
return PH_ERR_SUCCESS;
}
/* Configure LPCD (for PN5180) */
phStatus_t phApp_ConfigureLPCD(void)
{
/**
* PHHAL_HW_CONFIG_SET_LPCD_WAKEUPTIME_MS 0x0070U //< Used value for wakeup counter in msecs, i.e. after this amount of time IC will wakes up from standby.
* PHHAL_HW_CONFIG_LPCD_MODE 0x0071U //< Used to set options PHHAL_HW_PN5180_LPCD_MODE_DEFAULT or PHHAL_HW_PN5180_LPCD_MODE_POWERDOWN_GUARDED
* PHHAL_HW_CONFIG_LPCD_REF 0x0072U //< Used to set or get LPCD Ref
*/
phStatus_t status = PH_ERR_SUCCESS;
uint16_t wConfig = PHHAL_HW_CONFIG_LPCD_REF;
uint16_t wValue;
uint8_t bLPCD_Threshold_EEPROMAddress = 0x37;
uint8_t bLPCD_Threshold = 0x10;
wValue = PHHAL_HW_PN5180_LPCD_MODE_POWERDOWN;
wConfig = PHHAL_HW_CONFIG_LPCD_MODE;
//status = phhalHw_Pn5180_Int_LPCD_GetConfig(pHal, wConfig, &wValue);
status = phhalHw_Pn5180_Instr_WriteE2Prom(pHal,bLPCD_Threshold_EEPROMAddress, &bLPCD_Threshold, 1 );
CHECK_SUCCESS(status);
status = phhalHw_Pn5180_Int_LPCD_SetConfig(
pHal,
wConfig,
wValue
);
return status;
}
void CLIF_IRQHandler(void)
{
/* Read the interrupt status of external interrupt attached to the reader IC IRQ pin */
if (phDriver_PinRead(PHDRIVER_PIN_IRQ, PH_DRIVER_PINFUNC_INTERRUPT))
{
phDriver_PinClearIntStatus(PHDRIVER_PIN_IRQ);
/* Call application registered callback. */
if (pHal->pRFISRCallback != NULL)
{
pHal->pRFISRCallback(pHal);
}
}
}
#endif /* NXPBUILD__PHHAL_HW_PN5180 */
/******************************************************************************
** End Of File
******************************************************************************/

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PROJECT(NfcrdlibEx9_NTagI2C)
FILE(GLOB NfcrdlibEx9_NTagI2C_Sources
*.c
src/*.c
)
include_directories(
intfs
types
)
ADD_EXECUTABLE(NfcrdlibEx9_NTagI2C
${NfcrdlibEx9_NTagI2C_Sources}
)
TARGET_LINK_LIBRARIES(
NfcrdlibEx9_NTagI2C
phOsal
DAL
NxpRdLib_acDiscLoop
NxpRdLib_halHw
NxpRdLib_KeyStore
NxpRdLib_phTools
NxpRdLib_palFelica
NxpRdLib_palI18092mPI
NxpRdLib_palI14443p4a
NxpRdLib_palI14443p4
NxpRdLib_palI14443p4
NxpRdLib_palMifare
NxpRdLib_alFelica
NxpRdLib_alMful
NxpRdLib_alMfdf
NxpRdLib_alT1T
NxpRdLib_alTop
NxpRdLib_alMfc
NxpRdLib_palSli15693
NxpRdLib_palI18000p3m3
NxpRdLib_alICode
NxpRdLib_alI18000p3m3
NxpRdLib_alICode
NxpRdLib_palEpcUid
NxpRdLib_lnLlcp
NxpRdLib_palI14443p4mC
NxpRdLib_palI18092mT
NxpRdLib_ceT4T
NxpRdLib_alMfNtag42XDna
NxpRdLib_phNfcLib
)

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@ -0,0 +1,472 @@
/*----------------------------------------------------------------------------*/
/* Copyright 2016-2023 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may only */
/* be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that you */
/* have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*----------------------------------------------------------------------------*/
/** \file
* Example Source for NfcrdlibEx9_NTagI2c that uses the NTag I2C implementation.
* This example will load/configure Discovery loop for NTag I2C, uses POLL mode to detect the NTag I2C card.
* Displays detected NTag I2C card information like UID, ATQA, SAK, Product, Version Info, Page Read and Write status.
* Example will activate the device at index zero whenever multiple NTag I2C cards are detected.
* Please refer Readme.txt file for Hardware Pin Configuration, Software Configuration and steps to build and
* execute the project which is present in the same project directory.
* $Author: $
* $Revision: $ (v07.10.00)
* $Date: $
*
*/
/**
* Reader Library Headers
*/
#include <phApp_Init.h>
/* Local headers */
#include "NfcrdlibEx9_NTagI2C.h"
/*******************************************************************************
** Definitions
*******************************************************************************/
phacDiscLoop_Sw_DataParams_t * pDiscLoop; /* Pointer to Discovery loop data-params */
phalMful_Sw_DataParams_t * palMful; /* Pointer to AL MFUL data-params */
uint8_t bDataBuffer[DATA_BUFFER_LEN]; /* universal data buffer */
#ifdef PHOSAL_FREERTOS_STATIC_MEM_ALLOCATION
uint32_t aNTagI2CTaskBuffer[NTAGI2C_TASK_STACK];
#else /* PHOSAL_FREERTOS_STATIC_MEM_ALLOCATION */
#define aNTagI2CTaskBuffer NULL
#endif /* PHOSAL_FREERTOS_STATIC_MEM_ALLOCATION */
#ifdef PH_OSAL_FREERTOS
const uint8_t bTaskName[configMAX_TASK_NAME_LEN] = {"NTagI2C"};
#else
const uint8_t bTaskName[] = {"NTagI2C"};
#endif /* PH_OSAL_FREERTOS */
static volatile uint8_t bInfLoop = 1U;
/*******************************************************************************
** Prototypes
*******************************************************************************/
void NfcrdlibEx9_NTagI2C(void *pParams);
phStatus_t phExample_Init(void);
/*******************************************************************************
** Code
*******************************************************************************/
int main(void)
{
do
{
phStatus_t status = PH_ERR_INTERNAL_ERROR;
phNfcLib_Status_t dwStatus;
#ifdef PH_PLATFORM_HAS_ICFRONTEND
phNfcLib_AppContext_t AppContext = {0};
#endif /* PH_PLATFORM_HAS_ICFRONTEND */
#ifndef PH_OSAL_NULLOS
phOsal_ThreadObj_t NTagI2C;
#endif /* PH_OSAL_NULLOS */
/* Perform Controller specific initialization. */
phApp_CPU_Init();
/* Perform OSAL Initialization. */
(void)phOsal_Init();
/* Print Example application name */
DEBUG_PRINTF("\n *** NTag I2C Example *** \n");
#ifdef PH_PLATFORM_HAS_ICFRONTEND
status = phbalReg_Init(&sBalParams, sizeof(phbalReg_Type_t));
CHECK_STATUS(status);
AppContext.pBalDataparams = &sBalParams;
dwStatus = phNfcLib_SetContext(&AppContext);
CHECK_NFCLIB_STATUS(dwStatus);
#endif
/* Initialize library */
dwStatus = phNfcLib_Init();
CHECK_NFCLIB_STATUS(dwStatus);
if(dwStatus != PH_NFCLIB_STATUS_SUCCESS) break;
/* Set the generic pointer */
pHal = phNfcLib_GetDataParams(PH_COMP_HAL);
pDiscLoop = (phacDiscLoop_Sw_DataParams_t *) phNfcLib_GetDataParams(PH_COMP_AC_DISCLOOP);
palMful = (phalMful_Sw_DataParams_t *) phNfcLib_GetDataParams(PH_COMP_AL_MFUL);
/* Configure the IRQ */
status = phApp_Configure_IRQ();
CHECK_STATUS(status);
if(status != PH_ERR_SUCCESS) break;
#ifndef PH_OSAL_NULLOS
NTagI2C.pTaskName = (uint8_t *)bTaskName;
NTagI2C.pStackBuffer = aNTagI2CTaskBuffer;
NTagI2C.priority = NTAGI2C_TASK_PRIO;
NTagI2C.stackSizeInNum = NTAGI2C_TASK_STACK;
phOsal_ThreadCreate(&NTagI2C.ThreadHandle, &NTagI2C, &NfcrdlibEx9_NTagI2C, pDiscLoop);
phOsal_StartScheduler();
/* Print Error info */
DEBUG_PRINTF("RTOS Error : Scheduler exited. \n");
#else
(void)NfcrdlibEx9_NTagI2C(pDiscLoop);
#endif /* PH_OSAL_NULLOS */
} while(0);
while(bInfLoop); /* Comes here if initialization failure or scheduler exit due to error */
return 0;
}
/***********************************************************************************************
* \brief This function demonstrates the NTag I2C application as mentioned
* Performs Type A Card detection and Activation and displays Tag UID, ATQA and SAK info.
* Performs Read Tag Version info to confirm that the detected Tag is NTag I2C.
* Performs Read Session Registers to check the Tag Mode. We can perform Sector/Page Read Write only in non pass-through mode.
* Performs Read operation and Displays content of Sector 0 Pages 5 to 8 Data.
* Performs Write operation i.e. writes back the sector 0 Pages 5 to 8 Data.
* \param *pParams
* \return This function will never return
**********************************************************************************************/
void NfcrdlibEx9_NTagI2C(void *pParams)
{
phStatus_t status = 0;
uint16_t wTagsDetected = 0;
uint8_t bTagType;
uint8_t *pBuff;
uint16_t numOfBytes;
uint8_t bSectorNum;
uint8_t bMoreCardsAvailable;
/* This call shall allocate secure context before calling any secure function,
* when FreeRtos trust zone is enabled.
* */
phOsal_ThreadSecureStack( 512 );
/* Initialize library */
status = phExample_Init();
CHECK_STATUS(status);
while(bInfLoop) /* Continuous loop */
{
DEBUG_PRINTF("\nReady to detect");
DEBUG_PRINTF("\n");
do
{
/* Field OFF */
status = phhalHw_FieldOff(pHal);
CHECK_STATUS(status);
status = phhalHw_Wait(pHal, PHHAL_HW_TIME_MICROSECONDS, 5100);
CHECK_STATUS(status);
/* Configure Discovery loop for Poll Mode */
status = phacDiscLoop_SetConfig(pDiscLoop, PHAC_DISCLOOP_CONFIG_NEXT_POLL_STATE, PHAC_DISCLOOP_POLL_STATE_DETECTION);
CHECK_STATUS(status);
/* Run Discovery loop */
status = phacDiscLoop_Run(pDiscLoop, PHAC_DISCLOOP_ENTRY_POINT_POLL);
}while((status & PH_ERR_MASK) != PHAC_DISCLOOP_DEVICE_ACTIVATED); /* Exit on Card detection */
/* Card detected */
/* Get the tag types detected info */
status = phacDiscLoop_GetConfig(pDiscLoop, PHAC_DISCLOOP_CONFIG_TECH_DETECTED, &wTagsDetected);
/* Check for Status */
if ((status & PH_ERR_MASK) == PH_ERR_SUCCESS)
{
/* Check for Type A tag detection */
if (PHAC_DISCLOOP_CHECK_ANDMASK(wTagsDetected, PHAC_DISCLOOP_POS_BIT_MASK_A))
{
/* Bit b3 is set to zero, [Digital] 4.8.2 */
/* Mask out all other bits except for b7 and b6 */
bTagType = (pDiscLoop->sTypeATargetInfo.aTypeA_I3P3[0].aSak & 0x60);
bTagType = bTagType >> 5;
/* Check for Type 2 Tag */
if (bTagType == PHAC_DISCLOOP_TYPEA_TYPE2_TAG_CONFIG_MASK)
{
/* Check for NTAG I2C */
if ((pDiscLoop->sTypeATargetInfo.aTypeA_I3P3[0].aAtqa[0] == 0x44)&&
(pDiscLoop->sTypeATargetInfo.aTypeA_I3P3[0].aAtqa[1] == 0x00)&&
(pDiscLoop->sTypeATargetInfo.aTypeA_I3P3[0].aSak == 0x00))
{
do
{
/* Print UID */
DEBUG_PRINTF ("\nUID: ");
phApp_Print_Buff(pDiscLoop->sTypeATargetInfo.aTypeA_I3P3[0].aUid,
pDiscLoop->sTypeATargetInfo.aTypeA_I3P3[0].bUidSize);
/* Print ATQA and SAK */
DEBUG_PRINTF("\nATQA:");
phApp_Print_Buff(pDiscLoop->sTypeATargetInfo.aTypeA_I3P3[0].aAtqa, 2);
DEBUG_PRINTF ("\nSAK: 0x%x",pDiscLoop->sTypeATargetInfo.aTypeA_I3P3[0].aSak);
/* Print Tag info */
DEBUG_PRINTF ("\n\nType A T2-tag detected ");
/* Read Tag Version
* Byte 0: Fixed Header(0x00)
* Byte 1: Vendor ID(NXP Semiconductor: 0x04)
* Byte 2: Product Type(NTag: 0x04)
* Byte 6: Storage size(1k: 0x13 and 2k: 0x15)
*/
status = phalMful_GetVersion(palMful, &bDataBuffer[0]);
/* Check for Error */
if ((status & PH_ERR_MASK) != PH_ERR_SUCCESS)
{
DEBUG_PRINTF ("\nUnable to Read Tag Version information");
DEBUG_PRINTF("\n\nExecution aborted!!!\n");
break;
}
/* Check for Tag Info */
if((bDataBuffer[0] == 0x00) && (bDataBuffer[1] == 0x04) && (bDataBuffer[2] == 0x04))
{
DEBUG_PRINTF ("\nProduct: NTag I2C ");
if(bDataBuffer[6] == NTAG_I2C_1K_VERSION)
{
DEBUG_PRINTF ("1k Version ");
}
else if(bDataBuffer[6] == NTAG_I2C_2K_VERSION)
{
DEBUG_PRINTF ("2k Version ");
}
else
{
DEBUG_PRINTF ("\nInvalid Tag Version");
DEBUG_PRINTF("\n\nExecution aborted!!!\n");
break;
}
}
/* Read Tag Mode */
/* Select Sector 3 to Read Session Registers */
status = phalMful_SectorSelect(palMful, 3);
if ((status & PH_ERR_MASK) != PH_ERR_SUCCESS)
{
DEBUG_PRINTF ("\nSector 3 selection Failed");
DEBUG_PRINTF ("\nUnable to Read Tag Mode");
DEBUG_PRINTF("\n\nExecution aborted!!!\n");
break;
}
/* Read Session registers */
status = phalMful_Read(palMful, 0xF8, bDataBuffer);
/* check for Error */
if ((status & PH_ERR_MASK) != PH_ERR_SUCCESS)
{
DEBUG_PRINTF ("\nSession Registers Read Failed");
DEBUG_PRINTF ("\nUnable to Read Tag Mode");
DEBUG_PRINTF("\n\nExecution aborted!!!\n");
break;
}
/* check for Pass-through mode */
if ((bDataBuffer[0] & PTHRU_ON_OFF))
{
DEBUG_PRINTF ("\nTag is Configured in Pass-through Mode");
DEBUG_PRINTF ("\nCan not perform Sector/Page Read Write Operation");
DEBUG_PRINTF("\n\nExecution aborted!!!\n");
break;
}
/* --- Read Operation --- */
/* Select Sector 0 */
status = phalMful_SectorSelect(palMful, 0);
/* check for Success */
if ((status & PH_ERR_MASK) == PH_ERR_SUCCESS)
{
/* Read Sector 0 Page 5 to 8 Data */
status = phalMful_FastRead(palMful, 5, 8, &pBuff, &numOfBytes);
/* check for Success */
if ((status & PH_ERR_MASK) == PH_ERR_SUCCESS)
{
DEBUG_PRINTF ("\n\nRead Success");
/* Copy Sector0 Page 5 to 6 Data */
memcpy(bDataBuffer, pBuff, numOfBytes);
/* Display contents of Sector 0 Pages 5 to 6 Data */
for (bSectorNum = 5; bSectorNum <= 8; bSectorNum++)
{
DEBUG_PRINTF ("\nSector 0 Page %d Data: ", bSectorNum);
phApp_Print_Buff(&bDataBuffer[0 + ((bSectorNum - 5) * 4)], 4);
}
}
}
/* Check for Error */
if ((status & PH_ERR_MASK) != PH_ERR_SUCCESS)
{
DEBUG_PRINTF ("\nRead Operation Failed!!!");
DEBUG_PRINTF("\n\nExecution aborted!!!\n");
break;
}
/* End of Read Operation */
DEBUG_PRINTF("\n\n --- End of Read Operation --- \n");
/* --- Write Operation --- */
DEBUG_PRINTF("\nInitiation of Write operation to write back the Sector 0 Pages 5 to 8 Data \n");
/* Select Sector 0 */
status = phalMful_SectorSelect(palMful, 0);
/* check for Success */
if ((status & PH_ERR_MASK) == PH_ERR_SUCCESS)
{
/* Write data to Sector 0 Page 5 to 8 */
for (bSectorNum = 5; bSectorNum <= 8; bSectorNum++)
{
/* Page Write */
status = phalMful_Write(palMful, bSectorNum, &bDataBuffer[0 + ((bSectorNum - 5) * 4)]);
/* Check for Success */
if ((status & PH_ERR_MASK) == PH_ERR_SUCCESS)
{
DEBUG_PRINTF("\nWrite Success: Sector 0 Page %d", bSectorNum);
}
else
{
DEBUG_PRINTF ("\nWrite Failed: Sector 0 Page %d ", bSectorNum);
break;
}
}
}
/* Check for Error */
if ((status & PH_ERR_MASK) != PH_ERR_SUCCESS)
{
DEBUG_PRINTF ("\nWrite Operation Failed!!! ");
DEBUG_PRINTF("\n\nExecution aborted!!!\n");
break;
}
/* End of Write Operation */
DEBUG_PRINTF("\n\n --- End of Write Operation --- \n");
/* End of example */
DEBUG_PRINTF("\n\n --- End of Example --- \n\n");
DEBUG_PRINTF("\nPlease Remove the Card\n\n");
}while(0);
/* Field RESET */
status = phhalHw_FieldReset(pHal);
CHECK_STATUS(status);
/* Make sure that example application is not detecting the same card continuously */
do
{
/* Activate Card */
status = phpalI14443p3a_ActivateCard(
pDiscLoop->pPal1443p3aDataParams,
pDiscLoop->sTypeATargetInfo.aTypeA_I3P3[0].aUid,
pDiscLoop->sTypeATargetInfo.aTypeA_I3P3[0].bUidSize,
pDiscLoop->sTypeATargetInfo.aTypeA_I3P3[0].aUid,
&pDiscLoop->sTypeATargetInfo.aTypeA_I3P3[0].bUidSize,
&pDiscLoop->sTypeATargetInfo.aTypeA_I3P3[0].aSak,
&bMoreCardsAvailable);
/* Check for Status */
if (status != PH_ERR_SUCCESS)
{
break; /* Card Removed, break from the loop */
}
/* Send HaltA */
phpalI14443p3a_HaltA(pDiscLoop->pPal1443p3aDataParams);
/* Delay - 5 milli seconds*/
status = phhalHw_Wait(pHal, PHHAL_HW_TIME_MILLISECONDS, 5);
CHECK_STATUS(status);
}while(bInfLoop);
}
}
}
}
}
}
/***********************************************************************************************
* \brief Application initialization
* \param none
* \return status Returns the function status
**********************************************************************************************/
phStatus_t phExample_Init(void)
{
phStatus_t status = 0;
/* Bailout on Type A detect */
status = phacDiscLoop_SetConfig(pDiscLoop, PHAC_DISCLOOP_CONFIG_BAIL_OUT, PHAC_DISCLOOP_POS_BIT_MASK_A);
CHECK_STATUS(status);
/* Read the version of the reader IC */
#if defined NXPBUILD__PHHAL_HW_RC663
status = phhalHw_Rc663_ReadRegister(pHal, PHHAL_HW_RC663_REG_VERSION, &bDataBuffer[0]);
CHECK_STATUS(status);
DEBUG_PRINTF("\nReader chip RC663 Version: 0x%02x\n", bDataBuffer[0]);
#endif /* NXPBUILD__PHHAL_HW_RC663 */
/* Return Success */
return PH_ERR_SUCCESS;
}
/* Stubs, in case the phApp_Init.c expects these implementations */
#ifdef NXPBUILD__PHPAL_I14443P4MC_SW
/*
* WTX Callback called from WTX timer of 14443p3mC PAL.
*/
void pWtoxCallBck()
{
/* Dummy */
}
#endif /* NXPBUILD__PHPAL_I14443P4MC_SW */
#ifdef NXPBUILD__PHPAL_I18092MT_SW
void pRtoxCallBck()
{
/* Dummy */
}
#endif /* NXPBUILD__PHPAL_I18092MT_SW */
#ifdef NXPBUILD__PHHAL_HW_TARGET
/* Stubbed definitions in case TARGET is enabled */
uint8_t sens_res[2] = {0x04, 0x00};
uint8_t nfc_id1[3] = {0xA1, 0xA2, 0xA3};
uint8_t sel_res = 0x40;
uint8_t nfc_id3 = 0xFA;
uint8_t poll_res[18] = {0x01, 0xFE, 0xB2, 0xB3, 0xB4, 0xB5,
0xB6, 0xB7, 0xC0, 0xC1, 0xC2, 0xC3,
0xC4, 0xC5, 0xC6, 0xC7, 0x23, 0x45 };
#endif /* NXPBUILD__PHHAL_HW_TARGET */

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__________________________________________________
NXPNFCRDLIB EXAMPLE : NFCRDLIBEX9_NTAGI2C
(V07.10.00)
__________________________________________________
Table of Contents
_________________
1 Document Purpose
2 Description of the NfcrdlibEx9_NTagI2C
3 Restrictions on NfcrdlibEx9_NTagI2C
4 Package Contents
5 Mandatory materials (not included)
6 Hardware Configuration
7 Software Configuration
8 Steps to build NfcrdlibEx9_NTagI2C for LPC1769 with PN5190 using MCUXpresso
9 Steps to build NfcrdlibEx9_NTagI2C for LPC1769 with PN5180 using MCUXpresso
10 Steps to build NfcrdlibEx9_NTagI2C for LPC1769 with RC663 using MCUXpresso
11 Steps to build NfcrdlibEx9_NTagI2C for PN7462AU using MCUXpresso
12 Steps to build NfcrdlibEx9_NTagI2C for FRDM-K82F using MCUXpresso
13 Selection of Board / OSAL / Frontend (MCUXpresso)
14 Steps to follow for PI / Linux / CMake
15 Running NfcrdlibEx9_NTagI2C
16 List of supported NFC Reader Boards/ICs
17 Reference Documents
1 Document Purpose
==================
This document describes the steps to be followed to execute
NfcrdlibEx9_NTagI2C example as well as it's known problems and
restrictions.
2 Description of the NfcrdlibEx9_NTagI2C
========================================
- NfcrdlibEx9_NTagI2C can be run with CLEV663B, PN5180, PN5190 and
PN7462AU. (See Section-16 for supported versions)
- This example will load/configure Discovery loop with NFC profile via
SetConfig.
- By using POLL mode of discovery loop, example will detect the NTag
I2C cards and displays detected tag information like UID, ATQA, SAK,
Version info, Page Read and Page Write status.
- This example will activate device at index zero whenever multiple
cards are detected.
3 Restrictions on NfcrdlibEx9_NTagI2C
=====================================
- NfcrdlibEx9_NTagI2C is restricted to be run on NFC Reader Boards/ICs
mentioned in Section-16.
- The APIs are intended for NXP contact-less reader ICs only, as such
the APIs are not to be ported to any technology from any other
vendor.
- NXP will not support porting to any other vendor platform.
- This software project requires NxpNfcRdLib v07.10.00 or later.
- **IMPORTANT** The default used MCU Type is K82. When executing
example on LPC1769 or PN7462AU, the MCU Type has to be changed in
the MCUXpresso IDE.
- For switching to MCU Type to PN7462AU, see Section-11
- For switching to MCU Type to LPC1769, see Section-8, Section-9 and
Section-10.
4 Package Contents
==================
- Readme.txt
+ This readme file
- NfcrdlibEx9_NTagI2C.c
+ Main example file.
- intfs/NfcrdlibEx9_NTagI2C.h
+ Interfaces/Defines specific to the example
- intfs/ph_NxpBuild_App.h
+ Reader library build configuration file
- src/phApp_Helper.c
- src/phApp_PN5180_Init.c
- src/phApp_PN5190_Init.c
- src/phApp_PN7462AU_Init.c
- src/phApp_RC663_Init.c
- src/phApp_Init.c and intfs/phApp_Init.h
+ Common utility functions (common across all examples)
- mcux/.cproject and mcux/.project
+ MCUXpresso project configuration file
- cr_startup_lpc175x_6x.c
+ Startup required to compile example for LPC1769 Micro Controller.
5 Mandatory materials (not included)
====================================
- MCUXpresso IDE. It can be downloaded from
[http://www.nxp.com/products/:MCUXpresso-IDE]
- SDK for Freedom K82 Board
([http://www.nxp.com/products/:FRDM-K82F]). The pre-build SDK can
be downloaded from
[https://mcuxpresso.nxp.com/en/license?hash=9897a8c19a6bc569c3fade7141f0f405&hash_download=true&to_vault=true]
See MCUXpresso User Manual for steps needed to install an SDK.
- Plugin to extend MCUXpresso to support PN7462AU. (Required for
MCUXpresso versions before MCUXpressoIDE_10.0.2)
- LPCXpresso LPC1769 / Freedom K82 development boards For NFC ICs
listed in Section-16 (Note: PN7462AU (Section-16 Bullet-3) does not
need any other other microcontroller).
6 Hardware Configuration
========================
Before starting this application, HW Changes may be required for the
used board. Refer to the following User Manuals / Application notes
before starting with this example.
- AN11211: Quick Start Up Guide RC663 Blueboard
- AN11744: PN5180 Evaluation board quick start guide
- AN11802: NFC Reader Library for Linux Installation Guidelines
- AN12550: PNEV5190B Evaluation board quick start guide
7 Software Configuration
========================
- The Software can be compiled for Cortex M3 LPC1769 micro-controller,
Cortex M4 Freedom K82 and Cortex M0 based PN7462AU from NXP.
- Since this example can be configured to run on various MCU ICs and
various NFC ICs, appropriate changes are required as mentioned in
Section-8, Section-9, Section-10, Section-11 and Section-12.
8 Steps to build NfcrdlibEx9_NTagI2C for LPC1769 with PN5190 using MCUXpresso
=============================================================================
See "PNEV5190B Evaluation board quick start guide" in AN12550 (See
Section-17, Bullet-6 below)
9 Steps to build NfcrdlibEx9_NTagI2C for LPC1769 with PN5180 using MCUXpresso
=============================================================================
See "Importing provided SW example projects" in AN11908 (See
Section-17, Bullet-2 below)
10 Steps to build NfcrdlibEx9_NTagI2C for LPC1769 with RC663 using MCUXpresso
=============================================================================
See "Importing provided SW example projects" in AN11022 (See
Section-17, Bullet-3 below)
11 Steps to build NfcrdlibEx9_NTagI2C for PN7462AU using MCUXpresso
===================================================================
- For MCUXpresso versions before MCUXpressoIDE_10.0.2, See "Adding
PN7462AU Plugin" in UM10883. (See Section-17, Bullet-4 below)
- See "Importing provided SW example projects" in UM10883.
12 Steps to build NfcrdlibEx9_NTagI2C for FRDM-K82F using MCUXpresso
====================================================================
See "Import projects to the MCUXpresso" in AN11908. (See Section-17,
Bullet-2 below)
13 Selection of Board / OSAL / Frontend (MCUXpresso)
====================================================
For MCUXpresso, the selection of Board / OSAL / Frontend has to be
done via -D (Preprocessor defines).
1) To select the board go to "Project Properties" --> "C/C++ Build"
--> "Settings" --> "Preprocessor" --> "Defined symbols (-D)", and
define the relevant PHDRIVER_<BoardNFCCombination>_BOARD macro.
e.g. For using K82 with Pn5190 use PHDRIVER_K82F_PNEV5190B_BOARD
and for LPC1769 with PN5190 use PHDRIVER_LPC1769PN5190_BOARD. For
list of supported boards refer to
Platform\DAL\cfg\BoardSelection.h.
2) To select the osal/os type, go to "Project Properties" --> "C/C++
Build" --> "Settings" --> "Preprocessor" --> "Defined symbols
(-D)".
e.g. For using FreeRTOS use PH_OSAL_FREERTOS. For other options
refer to RTOS\phOsal\inc\phOsal_Config.h.
14 Steps to follow for PI / Linux / CMake
=========================================
The steps are described in AN11802. (See Section-17, Bullet-5 below)
15 Running NfcrdlibEx9_NTagI2C
==============================
Run the application and when you bring the NTag I2C in proximity, the
example application will detect and displays the detected card
information on console.
16 List of supported NFC Reader Boards/ICs
==========================================
1) CLEV6630B v2.0 Customer Evaluation Board
2) PNEV5180B v2.0 Customer Evaluation Board
3) PN7462AU v2.1 Customer Evaluation Board
4) PNEV5190B v1.0 Customer Evaluation Board
17 Reference Documents
======================
1) UM10954 : PN5180 SW Quick start guide
[http://www.nxp.com/docs/en/user-guide/UM10954.pdf]
2) AN11908 : NFC Reader Library for FRDM-K82F Board Installation
guidelines
[http://www.nxp.com/docs/en/application-note/AN11908.pdf]
3) AN11022 : CLRC663 Evaluation board quick start guide
[http://www.nxp.com/docs/en/application-note/AN11022.pdf]
4) UM10883 : PN7462AU Quick Start Guide - Development Kit
[http://www.nxp.com/docs/en/user-guide/UM10883.pdf]
5) AN11802 : NFC Reader Library for Linux Installation Guidelines
[http://www.nxp.com/docs/en/application-note/AN11802.pdf]
6) AN12550 : PNEV5190B Evaluation board quick start guide
----------------------------------------------------------------------
For updates of this example, see
[http://www.nxp.com/products/:NFC-READER-LIBRARY]

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/*----------------------------------------------------------------------------*/
/* Copyright 2016-2021 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may only */
/* be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that you */
/* have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*----------------------------------------------------------------------------*/
/** \file
* Example Source Header for NTag I2C application.
*
* $Author: NXP $
* $Revision: $ (v07.10.00)
* $Date: $
*/
#ifndef INTFS_NFCRDLIBEX9_NTAGI2C_H_
#define INTFS_NFCRDLIBEX9_NTAGI2C_H_
#include <ph_Status.h>
#define DATA_BUFFER_LEN 16 /* Buffer length */
/* Tag Version info macros */
#define NTAG_I2C_1K_VERSION 0x13 /* Tag Version: 1k */
#define NTAG_I2C_2K_VERSION 0x15 /* Tag Version: 2k */
#define PTHRU_ON_OFF (1 << 6) /* NC_REG Pass-through bit */
#ifdef PH_OSAL_FREERTOS
#ifdef PHOSAL_FREERTOS_STATIC_MEM_ALLOCATION
#define NTAGI2C_TASK_STACK (1400/4)
#else /* PHOSAL_FREERTOS_STATIC_MEM_ALLOCATION */
#if defined( __PN74XXXX__) || defined(__PN76XX__)
#define NTAGI2C_TASK_STACK (1200/4)
#else /* defined( __PN74XXXX__) || defined(__PN76XX__) */
#define NTAGI2C_TASK_STACK (1250)
#endif /* defined( __PN74XXXX__) || defined(__PN76XX__) */
#endif /* PHOSAL_FREERTOS_STATIC_MEM_ALLOCATION */
#define NTAGI2C_TASK_PRIO 4
#endif /* PH_OSAL_FREERTOS */
#ifdef PH_OSAL_LINUX
#define NTAGI2C_TASK_STACK 0x20000
#define NTAGI2C_TASK_PRIO 0
#endif /* PH_OSAL_LINUX */
#endif /* INTFS_NFCRDLIBEX9_NTAGI2C_H_ */

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/*----------------------------------------------------------------------------*/
/* Copyright 2016-2023 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may only */
/* be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that you */
/* have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*----------------------------------------------------------------------------*/
/** \file
* Example Source abstracting component header specific to HW used in the examples
* This file shall be present in all examples. A customer does not need to touch/modify this file. This file
* purely depends on the phNxpBuild_Lpc.h or phNxpBuild_App.h
* The phAppInit.h externs the component data structures initialized here that is in turn included by the core examples.
* The core example shall not use any other variable defined here except the RdLib component data structures(as explained above)
* The RdLib component initialization requires some user defined data and function pointers.
* These are defined in the respective examples and externed here.
*
* Keystore and Crypto initialization needs to be handled by application.
*
* $Author$
* $Revision$ (v07.10.00)
* $Date$
*
*/
#ifndef PHAPP_INIT_H
#define PHAPP_INIT_H
/* Status header */
#include <ph_Status.h>
/* Driver Header */
#include <phDriver.h>
/* NFCLIB Header */
#include <phNfcLib.h>
/* LLCP header */
#include <phlnLlcp.h>
/* SNEP header */
#include <phnpSnep.h>
/* Check for K82 controller based boards. */
#if defined(PHDRIVER_FRDM_K82FPN5180_BOARD) || \
defined(PHDRIVER_FRDM_K82FRC663_BOARD) || \
defined(PHDRIVER_K82F_PNEV5190B_BOARD)
#define PHDRIVER_KINETIS_K82
#endif
/* Check for LPC1769 controller based boards. */
#if defined(PHDRIVER_LPC1769PN5180_BOARD) || \
defined(PHDRIVER_LPC1769RC663_BOARD) || \
defined(PHDRIVER_LPC1769PN5190_BOARD)
#define PHDRIVER_LPC1769
#endif
#if defined(PHDRIVER_PIPN5180_BOARD) || \
defined(PHDRIVER_PIRC663_BOARD) || \
defined(PHDRIVER_PIPN5190_BOARD)
#include <phDriver_Linux_Int.h>
#endif
#ifdef PHDRIVER_KINETIS_K82
# include <fsl_debug_console.h>
# include <stdio.h>
#endif
#if !defined(__PN76XX__)
#ifdef DEBUG
#ifdef PHDRIVER_KINETIS_K82
#if SDK_DEBUGCONSOLE==1
#define DEBUG_PRINTF DbgConsole_Printf
#else
#define DEBUG_PRINTF(...) printf(__VA_ARGS__);
#endif
#else /* PHDRIVER_KINETIS_K82 */
#include <stdio.h>
#define DEBUG_PRINTF(...) printf(__VA_ARGS__); fflush(stdout)
#endif /* PHDRIVER_KINETIS_K82 */
#else /* DEBUG */
#define DEBUG_PRINTF(...)
#define DEBUG_SCANF(...)
#endif /* DEBUG */
#else /* __PN76XX__ */
#if (SEGGER_RTT_ENABLE == 1)
#include "SEGGER_RTT.h"
#define DEBUG_PRINTF(...) SEGGER_RTT_printf(0, __VA_ARGS__);
#define DEBUG_SCANF(Input , data) *data = (SEGGER_RTT_WaitKey() - 0x30); SEGGER_RTT_WaitKey()
#else
#if DEBUG
#include <fsl_debug_console.h>
#define DEBUG_PRINTF(...) PRINTF(__VA_ARGS__);
#define DEBUG_SCANF(...) SCANF(__VA_ARGS__);while ((GETCHAR()) != '\n');
#define DEBUG_GETCHAR GETCHAR
#else
#define DEBUG_PRINTF(...)
#define DEBUG_SCANF(...)
#endif /* DEBUG */
#endif /* (SEGGER_RTT_ENABLE == 1) */
#endif /* __PN76XX__ */
/*******************************************************************************
** Global Variable Declaration
*******************************************************************************/
#define PH_NFCRDLIB_EXAMPLE_LPCD_GUARDTIME 100 /* LPCD Guard time(T4) in milli-seconds configured by application for Rc663. */
#define PH_NFCRDLIB_EXAMPLE_LPCD_RFON_TIME 56 /* LPCD RFON time(T3) in micro-seconds configured by application for Rc663. */
/* HAL & BAL declarations */
#ifdef PH_PLATFORM_HAS_ICFRONTEND
extern phbalReg_Type_t sBalParams;
#endif /* PH_PLATFORM_HAS_ICFRONTEND */
#ifdef NXPBUILD__PHLN_LLCP_SW
extern phlnLlcp_Sw_DataParams_t slnLlcp; /* LLCP component */
#endif /* NXPBUILD__PHLN_LLCP_SW */
#ifdef NXPBUILD__PHHAL_HW_PN5180
extern phhalHw_Pn5180_DataParams_t * pHal;
#endif /* NXPBUILD__PHHAL_HW_PN5180 */
#ifdef NXPBUILD__PHHAL_HW_PN5190
extern phhalHw_Pn5190_DataParams_t * pHal;
#endif /* NXPBUILD__PHHAL_HW_PN5190 */
#ifdef NXPBUILD__PHHAL_HW_RC663
extern phhalHw_Rc663_DataParams_t * pHal;
#endif /* NXPBUILD__PHHAL_HW_RC663 */
#ifdef NXPBUILD__PHHAL_HW_PN7462AU
extern phhalHw_PN7462AU_DataParams_t * pHal;
#endif /* NXPBUILD__PHHAL_HW_PN7462AU */
#ifdef NXPBUILD__PHHAL_HW_PN76XX
extern phhalHw_Pn76xx_DataParams_t * pHal;
#endif /* NXPBUILD__PHHAL_HW_PN76XX */
/**************************************************Prints if error is detected**************************************************************/
/* Enable(1) / Disable(0) printing error/info */
#define DETECT_ERROR 0
#if DETECT_ERROR
#define DEBUG_ERROR_PRINT(x) x
#define PRINT_INFO(...) DEBUG_PRINTF(__VA_ARGS__)
#else
#define DEBUG_ERROR_PRINT(x)
#define PRINT_INFO(...)
#endif
#define CHECK_STATUS(x) \
if ((x) != PH_ERR_SUCCESS) \
{ \
DEBUG_PRINTF("Line: %d Error - (0x%04X) has occurred : 0xCCEE CC-Component ID, EE-Error code. Refer-ph_Status.h\n", __LINE__, (x)); \
}
/* prints if error is detected */
#define CHECK_SUCCESS(x) \
if ((x) != PH_ERR_SUCCESS) \
{ \
DEBUG_PRINTF("\nLine: %d Error - (0x%04X) has occurred : 0xCCEE CC-Component ID, EE-Error code. Refer-ph_Status.h\n ", __LINE__, (x)); \
return (x); \
}
/* prints if error is detected */
#define CHECK_NFCLIB_STATUS(x) \
if ((x) != PH_NFCLIB_STATUS_SUCCESS) \
{ \
DEBUG_PRINTF("\nLine: %d Error - (0x%04X) has occurred in NFCLIB\n ", __LINE__, (x)); \
}
/*********************************************************************************************************************************************/
/*******************************************************************************
** Function Declarations
*******************************************************************************/
extern void phApp_CPU_Init(void);
extern phStatus_t phApp_Comp_Init(void * pDiscLoopParams);
extern phStatus_t phApp_HALConfigAutoColl(void);
extern phStatus_t phApp_ConfigureLPCD(void);
extern void phApp_PrintTagInfo(phacDiscLoop_Sw_DataParams_t *pDataParams, uint16_t wNumberOfTags, uint16_t wTagsDetected);
extern void phApp_PrintTech(uint8_t TechType);
extern void phApp_Print_Buff(uint8_t *pBuff, uint8_t num);
extern void PrintErrorInfo(phStatus_t wStatus);
extern phStatus_t phApp_Configure_IRQ();
#ifdef PH_PLATFORM_HAS_ICFRONTEND
extern void CLIF_IRQHandler(void);
#endif /* PH_PLATFORM_HAS_ICFRONTEND */
#endif /* PHAPP_INIT_H */

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/*----------------------------------------------------------------------------*/
/* Copyright 2016-2023 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may only */
/* be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that you */
/* have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*----------------------------------------------------------------------------*/
/** \file
* Application specific selection of Reader Library Components
*
* $Author$
* $Revision$ (v07.10.00)
* $Date$
*
*/
#ifndef PH_NXPBUILD_APP_H_INC
#define PH_NXPBUILD_APP_H_INC
/** \defgroup ph_NxpBuild NXP Build
* \brief Controls the Inclusion of required components, Inclusion SRC/DATA within components and the Build Dependencies between the components
* @{
*/
/* NXPBUILD_DELETE: included code lines should be always removed from code */
/* NXP BUILD DEFINES */
/* use #define to include components */
/* comment out #define to exclude components */
/* DEBUG build mode */
/*#define NXPBUILD__PH_DEBUG*/ /**< DEBUG build definition */
#define NXPRDLIB_REM_GEN_INTFS
/*********************************************************************************************************************************************************************************/
#if defined(__PN74XXXX__) || defined (__PN73XXXX__)
#define NXPBUILD__PHHAL_HW_PN7462AU /**< NFC Controller PN7462AU HAL */
#endif
#ifdef __PN76XX__
#ifdef __PN7642__
#define NXPBUILD__PHHAL_HW_PN7642 /**< NFC Controller PN7642 HAL */
#elif __PN7640__
#define NXPBUILD__PHHAL_HW_PN7640 /**< NFC Controller PN7640 HAL */
#else
#error " PN76 platform definition (__PN7642__ or __PN7640__) missing !!! "
#endif
#if defined(__PN7642__) || defined(__PN7640__)
#define NXPBUILD__PHHAL_HW_PN76XX /**< NFC Controller PN76XX HAL */
#endif
#endif /* __PN76XX__ */
#if defined(PHDRIVER_LPC1769PN5180_BOARD) \
|| defined(PHDRIVER_FRDM_K82FPN5180_BOARD)
# define NXPBUILD__PHHAL_HW_PN5180
#endif
#if defined(PHDRIVER_LPC1769PN5190_BOARD) \
|| defined(PHDRIVER_K82F_PNEV5190B_BOARD)
# define NXPBUILD__PHHAL_HW_PN5190
#endif
#if defined(PHDRIVER_LPC1769RC663_BOARD) \
|| defined(PHDRIVER_FRDM_K82FRC663_BOARD)
# define NXPBUILD__PHHAL_HW_RC663
#endif
#if defined(NXPBUILD__PHHAL_HW_PN5180) || \
defined(NXPBUILD__PHHAL_HW_PN5190) || \
defined(NXPBUILD__PHHAL_HW_PN76XX) || \
defined(NXPBUILD__PHHAL_HW_PN7462AU)
// #define NXPBUILD__PHHAL_HW_TARGET /**< Dependency checking if target mode macros should be enabled */
#endif
/*********************************************************************************************************************************************************************************/
#define NXPBUILD__PHPAL_I14443P3A_SW /**< PAL ISO 14443-3A SW Component is included. */
//#define NXPBUILD__PHPAL_I14443P3B_SW /**< PAL ISO 14443-3B SW Component is included. */
//#define NXPBUILD__PHPAL_I14443P4A_SW /**< PAL ISO 14443-4A SW Component is included. */
//#define NXPBUILD__PHPAL_I14443P4_SW /**< PAL ISO 14443-4 SW Component is included. */
#define NXPBUILD__PHPAL_MIFARE_SW /**< PAL MIFARE SW Component is included */
//#define NXPBUILD__PHPAL_MIFARE_STUB /**< PAL MIFARE STUB Component is included */
//#define NXPBUILD__PHPAL_FELICA_SW /**< PAL Felica SW Component is included. */
//#define NXPBUILD__PHPAL_SLI15693_SW /**< PAL SLI 15693 Component is included. */
//#define NXPBUILD__PHPAL_I18000P3M3_SW /**< PAL ISO 18000p3m3 Component is included. */
#ifdef NXPBUILD__PHHAL_HW_RC663 /**< If FE HAL is RC663, then include EPC UID PAL as required, otherwise exclude. */
// #define NXPBUILD__PHPAL_EPCUID_SW /**< PAL EPC UID SW Component is included. */
#endif
//#define NXPBUILD__PHPAL_I18092MPI_SW /**< PAL ISO18092 (P2P) SW Component is included. */
#ifndef NXPBUILD__PHHAL_HW_RC663 /**< If FE HAL is RC663, then exclude ISO14443 Card Mode PAL & ISO18092 Target Mode PAL, otherwise include as required. */
// #define NXPBUILD__PHPAL_I14443P4MC_SW /**< PAL ISO 14443-4 Card Mode SW Component is included. */
// #define NXPBUILD__PHPAL_I18092MT_SW /**< PAL ISO 18092 Target Mode SW Component is included. */
#endif /* NXPBUILD__PHHAL_HW_RC663 */
/*********************************************************************************************************************************************************************************/
#define NXPBUILD__PHAC_DISCLOOP_SW /**< Discovery Loop Activity SW Component is included. */
#ifdef NXPBUILD__PHAC_DISCLOOP_SW /**< If DiscLoop SW Component is included, macros( & it's dependencies) to include/exclude SRC/DATA within Discloop is defined. */
#if defined (NXPBUILD__PHHAL_HW_PN5180) || \
defined (NXPBUILD__PHHAL_HW_PN5190) || \
defined (NXPBUILD__PHHAL_HW_RC663) || \
defined (NXPBUILD__PHHAL_HW_PN7462AU) || \
defined (NXPBUILD__PHHAL_HW_PN7642)
// #define NXPBUILD__PHAC_DISCLOOP_LPCD /**< SRC to enable LPCD is included. */
#endif
#ifdef NXPBUILD__PHPAL_I14443P3A_SW
#define NXPBUILD__PHAC_DISCLOOP_TYPEA_I3P3_TAGS /**< SRC/DATA to Detect/CollRes/Activate cards such as MFC, MFUL, MFP SL1 etc is included. */
// #define NXPBUILD__PHAC_DISCLOOP_TYPEA_JEWEL_TAGS /**< SRC/DATA to Detect cards such as NFC Forum T1T, Topaz/Jewel is included. */
#if defined(NXPBUILD__PHPAL_I14443P4A_SW) && defined(NXPBUILD__PHPAL_I14443P4_SW)
#define NXPBUILD__PHAC_DISCLOOP_TYPEA_I3P4_TAGS /**< SRC/DATA to Detect cards such as MFDF, MFP, T4AT NFC Forum Tag or Type A EMVCo is included. */
#endif
#endif /* NXPBUILD__PHPAL_I14443P3A_SW */
#if defined(NXPBUILD__PHPAL_I14443P3A_SW) && defined(NXPBUILD__PHPAL_I18092MPI_SW)
#define NXPBUILD__PHAC_DISCLOOP_TYPEA_P2P_TAGS /**< SRC/DATA to Detect Peer Passive Type A P2P Target mode devices is included. */
#endif
#ifndef NXPBUILD__PHHAL_HW_RC663
#ifdef NXPBUILD__PHPAL_I18092MPI_SW
#define NXPBUILD__PHAC_DISCLOOP_TYPEA_P2P_ACTIVE /**< SRC/DATA to Detect Peer Active Type A P2P Target mode devices is included. */
#define NXPBUILD__PHAC_DISCLOOP_TYPEF212_P2P_ACTIVE/**< SRC/DATA to Detect Peer Active Type F212 P2P Target mode devices is included. */
#define NXPBUILD__PHAC_DISCLOOP_TYPEF424_P2P_ACTIVE/**< SRC/DATA to Detect Peer Active Type F424 P2P Target mode devices is included. */
#endif /* NXPBUILD__PHPAL_I18092MPI_SW */
#endif /* NXPBUILD__PHHAL_HW_RC663 */
#ifdef NXPBUILD__PHPAL_FELICA_SW
#define NXPBUILD__PHAC_DISCLOOP_FELICA_TAGS /**< SRC/DATA to Detect FeliCa Cards is included. */
#ifdef NXPBUILD__PHPAL_I18092MPI_SW
#define NXPBUILD__PHAC_DISCLOOP_TYPEF_P2P_TAGS /**< SRC/DATA to Detect Peer Passive Type F P2P Target mode devices is included. */
#endif /* NXPBUILD__PHPAL_I18092MPI_SW */
#endif /* NXPBUILD__PHPAL_FELICA_SW */
#ifdef NXPBUILD__PHPAL_I14443P3B_SW
#define NXPBUILD__PHAC_DISCLOOP_TYPEB_I3P3B_TAGS /**< SRC/DATA to Detect Type B Cards that operate at Layer3 level is included */
#ifdef NXPBUILD__PHPAL_I14443P4_SW
#define NXPBUILD__PHAC_DISCLOOP_TYPEB_I3P4B_TAGS /**< SRC/DATA to Detect Type B Cards such as NFC Forum Type 4 Tags, EMVCo Type B Cards etc is included */
#endif /* NXPBUILD__PHPAL_I14443P4_SW */
#endif /* NXPBUILD__PHPAL_I14443P3B_SW */
#ifdef NXPBUILD__PHPAL_SLI15693_SW
#define NXPBUILD__PHAC_DISCLOOP_TYPEV_TAGS /**< SRC/DATA to Detect Type V Cards such as ICODE SLI/SLIX/SLI2/Tesa Cards is included*/
#endif /* NXPBUILD__PHPAL_SLI15693_SW */
#ifdef NXPBUILD__PHPAL_I18000P3M3_SW
#define NXPBUILD__PHAC_DISCLOOP_I18000P3M3_TAGS /**< SRC/DATA to Detect ICODE ILT Cards such as SMARTRAC StackIt Cards is included*/
#endif /* NXPBUILD__PHPAL_I18000P3M3_SW */
#ifndef NXPBUILD__PHHAL_HW_RC663 /**< If FE HAL is RC663, target mode is not supported at all, hence exclude those SRC, otherwise include as required */
#ifdef NXPBUILD__PHHAL_HW_TARGET
#define NXPBUILD__PHAC_DISCLOOP_TYPEA_TARGET_PASSIVE /**< SRC to Initialize Type A passive listen config and subsequently call HAL AutoColl is included. */
#define NXPBUILD__PHAC_DISCLOOP_TYPEA_TARGET_ACTIVE /**< SRC to Initialize Type A active listen config and subsequently call HAL AutoColl is included. */
#define NXPBUILD__PHAC_DISCLOOP_TYPEF212_TARGET_PASSIVE/**< SRC to Initialize Type F212 passive listen config and subsequently call HAL AutoColl is included. */
#define NXPBUILD__PHAC_DISCLOOP_TYPEF212_TARGET_ACTIVE /**< SRC to Initialize Type F212 active listen config and subsequently call HAL AutoColl is included. */
#define NXPBUILD__PHAC_DISCLOOP_TYPEF424_TARGET_PASSIVE/**< SRC to Initialize Type F424 passive listen config and subsequently call HAL AutoColl is included. */
#define NXPBUILD__PHAC_DISCLOOP_TYPEF424_TARGET_ACTIVE /**< SRC to Initialize Type F424 active listen config and subsequently call HAL AutoColl is included. */
#endif /* NXPBUILD__PHHAL_HW_TARGET */
#endif
#endif /* NXPBUILD__PHAC_DISCLOOP_SW */
/*********************************************************************************************************************************************************************************/
#define NXPBUILD__PHNFCLIB /**< Simplified API Interface, If enabling this the entry point should be this component in the application */
/*********************************************************************************************************************************************************************************/
//#define NXPBUILD__PH_CIDMANAGER_SW /**< CID Manager SW Component is included. */
#define NXPBUILD__PH_KEYSTORE_SW /**< SW KeyStore Component is included. */
#if defined(NXPBUILD__PHHAL_HW_RC663) && !defined(NXPBUILD__PH_KEYSTORE_SW)
#define NXPBUILD__PH_KEYSTORE_RC663 /**< RC663 KeyStore Component is included. */
#endif
//#define NXPBUILD__PH_NDA_MFDF /**< MIFARE DESFire contactless IC */
#define NXPBUILD__PH_CRYPTOSYM_SW /**< Crypto Symbols SW Component is included. */
#define NXPBUILD__PH_CRYPTORNG_SW /**< Crypto RNG SW Component is included. */
/*********************************************************************************************************************************************************************************/
#ifdef NXPBUILD__PHPAL_FELICA_SW
#define NXPBUILD__PHAL_FELICA_SW /**< AL FeliCa SW Component is included */
#endif /* NXPBUILD__PHPAL_FELICA_SW */
#ifdef NXPBUILD__PHPAL_MIFARE_SW
#if defined(NXPBUILD__PH_KEYSTORE_SW) || defined(NXPBUILD__PH_KEYSTORE_RC663)
// #define NXPBUILD__PHAL_MFC_SW /**< AL MIFARE Classic contactless IC SW Component is included */
#endif
#define NXPBUILD__PHAL_MFUL_SW /**< AL Mifare Ultrlight SW Component is included */
// #define NXPBUILD__PHAL_MFDF_SW /**< AL Mifare DesFire SW Component is included */
// #define NXPBUILD__PHAL_MFNTAG42XDNA_SW /**< AL MIFARE Prime Ntag42XDna contactless IC SW Component is included */
#endif /* NXPBUILD__PHPAL_MIFARE_SW */
//#define NXPBUILD__PHAL_T1T_SW /**< AL Type T1 Tag SW Component is included */
#ifdef NXPBUILD__PHPAL_SLI15693_SW
#define NXPBUILD__PHAL_ICODE_SW /**< AL ICODE SW COMPONENT is included */
#endif /* NXPBUILD__PHPAL_SLI15693_SW */
//#define NXPBUILD__PHAL_TOP_SW /**< AL for TagOps Mapping SW Component is included.Required for NDEF operations */
#ifdef NXPBUILD__PHPAL_I18000P3M3_SW
#define NXPBUILD__PHAL_I18000P3M3_SW /**< AL ISO18000p3m3 SW Component is included */
#endif /* NXPBUILD__PHPAL_I18000P3M3_SW */
#ifdef NXPBUILD__PHPAL_I14443P4MC_SW
#if !defined(PH_OSAL_NULLOS)
#define NXPBUILD__PHCE_T4T_SW /**< AL HCE T2AT SW Component is included */
//#define NXPBUILD__PHCE_T4T_PROPRIETARY /**< SRC to handle HCE T4AT Proprietary Commands is included */
/*#define NXPBUILD__PHCE_T4T_EXT_NDEF */ /**< SRC to handle Extended NDEF Support as per T4T spec 3.0 is included */
#endif
#endif /* NXPBUILD__PHPAL_I14443P4MC_SW */
/* LLCP Components */
#if defined(NXPBUILD__PHPAL_I18092MPI_SW) || defined(NXPBUILD__PHPAL_I18092MT_SW)
#if !defined(PH_OSAL_NULLOS)
#define NXPBUILD__PHLN_LLCP_SW /**< Link LLCP SW Component is included */
#endif
#endif
/* SNEP components */
#ifdef NXPBUILD__PHLN_LLCP_SW
#define NXPBUILD__PHNP_SNEP_SW /**< Protocol SNEP SW Component is included */
#endif /* NXPBUILD__PHLN_LLCP_SW */
/* Enable/disable Debugging */
/*#define NXPBUILD__PH_DEBUG*/ /**< TODO: To be checked if required */
/** @}
* end of ph_NxpBuild
*/
#endif /* PH_NXPBUILD_APP_H_INC */

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<sdkVersion>2.6.0</sdkVersion>
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@ -0,0 +1,89 @@
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<projectDescription>
<name>NfcrdlibEx9_NTagI2C_mcux</name>
<comment></comment>
<projects>
<project>FreeRTOS</project>
<project>lpc_board_nxp_lpcxpresso_1769</project>
<project>lpc_chip_175x_6x</project>
<project>NxpNfcRdLib</project>
<project>SDK_2.x_FRDM-K82F</project>
</projects>
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<link>
<name>DAL</name>
<type>2</type>
<locationURI>PARENT-3-PROJECT_LOC/Platform/DAL</locationURI>
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<name>FreeRTOS</name>
<type>2</type>
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<name>NfcrdlibEx9_NTagI2C.c</name>
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<name>NxpNfcRdLib</name>
<type>2</type>
<locationURI>PARENT-3-PROJECT_LOC/NxpNfcRdLib</locationURI>
</link>
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<name>PN7462AU</name>
<type>2</type>
<locationURI>PARENT-3-PROJECT_LOC/Platform/PN7462AU</locationURI>
</link>
<link>
<name>Readme.txt</name>
<type>1</type>
<locationURI>PARENT-1-PROJECT_LOC/Readme.txt</locationURI>
</link>
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<name>intfs</name>
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@ -0,0 +1,493 @@
//*****************************************************************************
// LPC175x_6x Microcontroller Startup code for use with LPCXpresso IDE
//
// Version : 140114
//*****************************************************************************
//
// Copyright(C) NXP Semiconductors, 2014
// All rights reserved.
//
// Software that is described herein is for illustrative purposes only
// which provides customers with programming information regarding the
// LPC products. This software is supplied "AS IS" without any warranties of
// any kind, and NXP Semiconductors and its licensor disclaim any and
// all warranties, express or implied, including all implied warranties of
// merchantability, fitness for a particular purpose and non-infringement of
// intellectual property rights. NXP Semiconductors assumes no responsibility
// or liability for the use of the software, conveys no license or rights under any
// patent, copyright, mask work right, or any other intellectual property rights in
// or to any products. NXP Semiconductors reserves the right to make changes
// in the software without notification. NXP Semiconductors also makes no
// representation or warranty that such application will be suitable for the
// specified use without further testing or modification.
//
// Permission to use, copy, modify, and distribute this software and its
// documentation is hereby granted, under NXP Semiconductors' and its
// licensor's relevant copyrights in the software, without fee, provided that it
// is used in conjunction with NXP Semiconductors microcontrollers. This
// copyright, permission, and disclaimer notice must appear in all copies of
// this code.
//*****************************************************************************
#include <ph_Status.h>
#include <cr_section_macros.h>
#include <NXP/crp.h>
#ifdef DEBUG
# define VT_IMAGE_LENGTH 0x76706b64U
#else /* DEBUG */
# define VT_IMAGE_LENGTH 0xFFFFFFFFU
#endif /* DEBUG */
#if defined (__cplusplus)
#ifdef __REDLIB__
#error Redlib does not support C++
#else
//*****************************************************************************
//
// The entry point for the C++ library startup
//
//*****************************************************************************
extern "C" {
extern void __libc_init_array(void);
}
#endif
#endif
#define WEAK __attribute__ ((weak))
#define ALIAS(f) __attribute__ ((weak, alias (#f)))
__CRP const unsigned int CRP_WORD = CRP_NO_CRP;
//*****************************************************************************
#if defined (__cplusplus)
extern "C" {
#endif
//*****************************************************************************
#if defined (__USE_CMSIS) || defined (__USE_LPCOPEN)
// Declaration of external SystemInit function
void SystemInit(void);
extern void Board_SystemInit(void);
extern void Chip_SystemInit(void);
extern void SystemCoreClockUpdate(void);
#endif
//*****************************************************************************
//
// Forward declaration of the default handlers. These are aliased.
// When the application defines a handler (with the same name), this will
// automatically take precedence over these weak definitions
//
//*****************************************************************************
void ResetISR(void);
WEAK void NMI_Handler(void);
//WEAK void HardFault_Handler(void);
WEAK void MemManage_Handler(void);
WEAK void BusFault_Handler(void);
WEAK void UsageFault_Handler(void);
WEAK void SVC_Handler(void);
WEAK void DebugMon_Handler(void);
WEAK void PendSV_Handler(void);
WEAK void SysTick_Handler(void);
WEAK void IntDefaultHandler(void);
/* The prototype shows it is a naked function - in effect this is just an
assembly function. */
void HardFault_Handler( void ) __attribute__( ( naked ) );
//*****************************************************************************
//
// Forward declaration of the specific IRQ handlers. These are aliased
// to the IntDefaultHandler, which is a 'forever' loop. When the application
// defines a handler (with the same name), this will automatically take
// precedence over these weak definitions
//
//*****************************************************************************
void WDT_IRQHandler(void) ALIAS(IntDefaultHandler);
void TIMER0_IRQHandler(void) ALIAS(IntDefaultHandler);
void TIMER1_IRQHandler(void) ALIAS(IntDefaultHandler);
void TIMER2_IRQHandler(void) ALIAS(IntDefaultHandler);
void TIMER3_IRQHandler(void) ALIAS(IntDefaultHandler);
void UART0_IRQHandler(void) ALIAS(IntDefaultHandler);
void UART1_IRQHandler(void) ALIAS(IntDefaultHandler);
void UART2_IRQHandler(void) ALIAS(IntDefaultHandler);
void UART3_IRQHandler(void) ALIAS(IntDefaultHandler);
void PWM1_IRQHandler(void) ALIAS(IntDefaultHandler);
void I2C0_IRQHandler(void) ALIAS(IntDefaultHandler);
void I2C1_IRQHandler(void) ALIAS(IntDefaultHandler);
void I2C2_IRQHandler(void) ALIAS(IntDefaultHandler);
void SPI_IRQHandler(void) ALIAS(IntDefaultHandler);
void SSP0_IRQHandler(void) ALIAS(IntDefaultHandler);
void SSP1_IRQHandler(void) ALIAS(IntDefaultHandler);
void PLL0_IRQHandler(void) ALIAS(IntDefaultHandler);
void RTC_IRQHandler(void) ALIAS(IntDefaultHandler);
void EINT0_IRQHandler(void) ALIAS(IntDefaultHandler);
void EINT1_IRQHandler(void) ALIAS(IntDefaultHandler);
void EINT2_IRQHandler(void) ALIAS(IntDefaultHandler);
void CLIF_IRQHandler(void) ALIAS(IntDefaultHandler);
void ADC_IRQHandler(void) ALIAS(IntDefaultHandler);
void BOD_IRQHandler(void) ALIAS(IntDefaultHandler);
void USB_IRQHandler(void) ALIAS(IntDefaultHandler);
void CAN_IRQHandler(void) ALIAS(IntDefaultHandler);
void DMA_IRQHandler(void) ALIAS(IntDefaultHandler);
void I2S_IRQHandler(void) ALIAS(IntDefaultHandler);
#if defined (__USE_LPCOPEN)
void ETH_IRQHandler(void) ALIAS(IntDefaultHandler);
#else
void ENET_IRQHandler(void) ALIAS(IntDefaultHandler);
#endif
void RIT_IRQHandler(void) ALIAS(IntDefaultHandler);
void MCPWM_IRQHandler(void) ALIAS(IntDefaultHandler);
void QEI_IRQHandler(void) ALIAS(IntDefaultHandler);
void PLL1_IRQHandler(void) ALIAS(IntDefaultHandler);
void USBActivity_IRQHandler(void) ALIAS(IntDefaultHandler);
void CANActivity_IRQHandler(void) ALIAS(IntDefaultHandler);
void UART4_IRQHandler(void) ALIAS(IntDefaultHandler);
void SSP2_IRQHandler(void) ALIAS(IntDefaultHandler);
void LCD_IRQHandler(void) ALIAS(IntDefaultHandler);
void GPIO_IRQHandler(void) ALIAS(IntDefaultHandler);
void PWM0_IRQHandler(void) ALIAS(IntDefaultHandler);
void EEPROM_IRQHandler(void) ALIAS(IntDefaultHandler);
//*****************************************************************************
//
// The entry point for the application.
// __main() is the entry point for Redlib based applications
// main() is the entry point for Newlib based applications
//
//*****************************************************************************
#if defined (__REDLIB__)
extern void __main(void);
#endif
extern int main(void);
//*****************************************************************************
//
// External declaration for the pointer to the stack top from the Linker Script
//
//*****************************************************************************
extern void _vStackTop(void);
//*****************************************************************************
#if defined (__cplusplus)
} // extern "C"
#endif
//*****************************************************************************
//
// The vector table.
// This relies on the linker script to place at correct location in memory.
//
//*****************************************************************************
extern void (* const g_pfnVectors[])(void);
__attribute__ ((section(".isr_vector")))
void (* const g_pfnVectors[])(void) = {
// Core Level - CM3
&_vStackTop, // The initial stack pointer
ResetISR, // The reset handler
NMI_Handler, // The NMI handler
HardFault_Handler, // The hard fault handler
MemManage_Handler, // The MPU fault handler
BusFault_Handler, // The bus fault handler
UsageFault_Handler, // The usage fault handler
0, // Reserved
0, // Reserved
0, // Reserved
0, // Reserved
SVC_Handler, // SVCall handler
DebugMon_Handler, // Debug monitor handler
0, // Reserved
PendSV_Handler, // The PendSV handler
SysTick_Handler, // The SysTick handler
// Chip Level - LPC17
WDT_IRQHandler, // 16, 0x40 - WDT
TIMER0_IRQHandler, // 17, 0x44 - TIMER0
TIMER1_IRQHandler, // 18, 0x48 - TIMER1
TIMER2_IRQHandler, // 19, 0x4c - TIMER2
TIMER3_IRQHandler, // 20, 0x50 - TIMER3
UART0_IRQHandler, // 21, 0x54 - UART0
UART1_IRQHandler, // 22, 0x58 - UART1
UART2_IRQHandler, // 23, 0x5c - UART2
UART3_IRQHandler, // 24, 0x60 - UART3
PWM1_IRQHandler, // 25, 0x64 - PWM1
I2C0_IRQHandler, // 26, 0x68 - I2C0
I2C1_IRQHandler, // 27, 0x6c - I2C1
I2C2_IRQHandler, // 28, 0x70 - I2C2
SPI_IRQHandler, // 29, 0x74 - SPI
SSP0_IRQHandler, // 30, 0x78 - SSP0
SSP1_IRQHandler, // 31, 0x7c - SSP1
PLL0_IRQHandler, // 32, 0x80 - PLL0 (Main PLL)
RTC_IRQHandler, // 33, 0x84 - RTC
EINT0_IRQHandler, // 34, 0x88 - EINT0
EINT1_IRQHandler, // 35, 0x8c - EINT1
EINT2_IRQHandler, // 36, 0x90 - EINT2
CLIF_IRQHandler, // 37, 0x94 - EINT3 (Used for CLIF IRQ)
ADC_IRQHandler, // 38, 0x98 - ADC
BOD_IRQHandler, // 39, 0x9c - BOD
USB_IRQHandler, // 40, 0xA0 - USB
CAN_IRQHandler, // 41, 0xa4 - CAN
DMA_IRQHandler, // 42, 0xa8 - GP DMA
I2S_IRQHandler, // 43, 0xac - I2S
#if defined (__USE_LPCOPEN)
ETH_IRQHandler, // 44, 0xb0 - Ethernet
#else
ENET_IRQHandler, // 44, 0xb0 - Ethernet
#endif
RIT_IRQHandler, // 45, 0xb4 - RITINT
MCPWM_IRQHandler, // 46, 0xb8 - Motor Control PWM
QEI_IRQHandler, // 47, 0xbc - Quadrature Encoder
PLL1_IRQHandler, // 48, 0xc0 - PLL1 (USB PLL)
USBActivity_IRQHandler, // 49, 0xc4 - USB Activity interrupt to wakeup
CANActivity_IRQHandler, // 50, 0xc8 - CAN Activity interrupt to wakeup
UART4_IRQHandler, //; 51 UART4
SSP2_IRQHandler, //; 52 SSP2
LCD_IRQHandler, //; 53 LCD
GPIO_IRQHandler, //; 54 GPIO
PWM0_IRQHandler , //; 55 PWM0
EEPROM_IRQHandler, //; 56 EEPROM
(void *)VT_IMAGE_LENGTH, //; 57 VT Checksum for CRC Check of Vector Table.
};
//*****************************************************************************
// Functions to carry out the initialization of RW and BSS data sections. These
// are written as separate functions rather than being inlined within the
// ResetISR() function in order to cope with MCUs with multiple banks of
// memory.
//*****************************************************************************
__attribute__ ((section(".after_vectors")))
void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
unsigned int *pulDest = (unsigned int*) start;
unsigned int *pulSrc = (unsigned int*) romstart;
unsigned int loop;
for (loop = 0; loop < len; loop = loop + 4)
*pulDest++ = *pulSrc++;
}
__attribute__ ((section(".after_vectors")))
void bss_init(unsigned int start, unsigned int len) {
unsigned int *pulDest = (unsigned int*) start;
unsigned int loop;
for (loop = 0; loop < len; loop = loop + 4)
*pulDest++ = 0;
}
//*****************************************************************************
// The following symbols are constructs generated by the linker, indicating
// the location of various points in the "Global Section Table". This table is
// created by the linker via the Code Red managed linker script mechanism. It
// contains the load address, execution address and length of each RW data
// section and the execution and length of each BSS (zero initialized) section.
//*****************************************************************************
extern unsigned int __data_section_table;
extern unsigned int __data_section_table_end;
extern unsigned int __bss_section_table;
extern unsigned int __bss_section_table_end;
//*****************************************************************************
// Reset entry point for your code.
// Sets up a simple runtime environment and initializes the C/C++
// library.
//*****************************************************************************
__attribute__ ((section(".after_vectors")))
void
ResetISR(void) {
//
// Copy the data sections from flash to SRAM.
//
unsigned int LoadAddr, ExeAddr, SectionLen;
unsigned int *SectionTableAddr;
// Load base address of Global Section Table
SectionTableAddr = &__data_section_table;
// Copy the data sections from flash to SRAM.
while (SectionTableAddr < &__data_section_table_end) {
LoadAddr = *SectionTableAddr++;
ExeAddr = *SectionTableAddr++;
SectionLen = *SectionTableAddr++;
data_init(LoadAddr, ExeAddr, SectionLen);
}
// At this point, SectionTableAddr = &__bss_section_table;
// Zero fill the bss segment
while (SectionTableAddr < &__bss_section_table_end) {
ExeAddr = *SectionTableAddr++;
SectionLen = *SectionTableAddr++;
bss_init(ExeAddr, SectionLen);
}
#if defined (__USE_CMSIS) || defined (__USE_LPCOPEN)
SystemInit();
#endif
#if defined (__cplusplus)
//
// Call C++ library initialisation
//
__libc_init_array();
#endif
#if defined (__REDLIB__)
// Call the Redlib library, which in turn calls main()
__main() ;
#else
main();
#endif
//
// main() shouldn't return, but if it does, we'll just enter an infinite loop
//
while (1) {
;
}
}
/* Set up and initialize hardware prior to call to main */
void SystemInit(void)
{
unsigned int *pSCB_VTOR = (unsigned int *) 0xE000ED08;
#if defined(__IAR_SYSTEMS_ICC__)
extern void *__vector_table;
*pSCB_VTOR = (unsigned int) &__vector_table;
#elif defined(__CODE_RED)
*pSCB_VTOR = (unsigned int) &g_pfnVectors;
#elif defined(__ARMCC_VERSION)
extern void *__Vectors;
*pSCB_VTOR = (unsigned int) &__Vectors;
#endif
#if defined(__FPU_PRESENT) && __FPU_PRESENT == 1
fpuInit();
#endif
#if defined(NO_BOARD_LIB)
/* Chip specific SystemInit */
Chip_SystemInit();
#else
/* Setup system clocking and muxing */
Board_SystemInit();
#endif
/* Update system core clock rate. */
SystemCoreClockUpdate();
}
//*****************************************************************************
// Default exception handlers. Override the ones here by defining your own
// handler routines in your application code.
//*****************************************************************************
__attribute__ ((section(".after_vectors")))
void NMI_Handler(void)
{ while(1) {}
}
/* The fault handler implementation calls a function called
prvGetRegistersFromStack(). */
__attribute__ ((section(".after_vectors")))
void HardFault_Handler(void)
{
/* Use assembly to pick up date, but feed to C Code. */
__asm( ".syntax divided\n"
"MOVS R0, #4 \n"
"MOV R1, LR \n"
"TST R0, R1 \n"
"BEQ _MSP \n"
"MRS R0, PSP \n"
"B HardFault_HandlerC \n"
"_MSP: \n"
"MRS R0, MSP \n"
"B HardFault_HandlerC \n"
".syntax divided\n") ;
__asm(".syntax unified");
}
__attribute__ ((section(".after_vectors")))
void HardFault_HandlerC(
unsigned long *args)
{
volatile unsigned long cm_r0;
volatile unsigned long cm_r1;
volatile unsigned long cm_r2;
volatile unsigned long cm_r3;
volatile unsigned long cm_r12;
volatile unsigned long cm_lr;
volatile unsigned long cm_pc;
volatile unsigned long cm_psr;
//if (((uint32_t) args < PH_RAM_MEM_END)&& ( (uint32_t)args > PH_RAM_MEM_START))
//0x10000000 -- 0x8000
//0x2007c000 -- 0x8000
{
cm_r0 = ((unsigned long)args[0]);
cm_r1 = ((unsigned long)args[1]);
cm_r2 = ((unsigned long)args[2]);
cm_r3 = ((unsigned long)args[3]);
cm_r12 = ((unsigned long)args[4]);
cm_lr = ((unsigned long)args[5]);
cm_pc = ((unsigned long)args[6]);
cm_psr = ((unsigned long)args[7]);
PH_UNUSED_VARIABLE(cm_r0);
PH_UNUSED_VARIABLE(cm_r1);
PH_UNUSED_VARIABLE(cm_r2);
PH_UNUSED_VARIABLE(cm_r3);
PH_UNUSED_VARIABLE(cm_r12);
PH_UNUSED_VARIABLE(cm_lr);
PH_UNUSED_VARIABLE(cm_pc);
PH_UNUSED_VARIABLE(cm_psr);
}
/* Break into the debugger */
__asm("BKPT #0\n");
while (1)
{
__asm("wfi\n");
}
}
__attribute__ ((section(".after_vectors")))
void MemManage_Handler(void)
{ while(1) {}
}
__attribute__ ((section(".after_vectors")))
void BusFault_Handler(void)
{ while(1) {}
}
__attribute__ ((section(".after_vectors")))
void UsageFault_Handler(void)
{ while(1) {}
}
__attribute__ ((section(".after_vectors")))
void SVC_Handler(void)
{ while(1) {}
}
__attribute__ ((section(".after_vectors")))
void DebugMon_Handler(void)
{ while(1) {}
}
__attribute__ ((section(".after_vectors")))
void PendSV_Handler(void)
{ while(1) {}
}
//*****************************************************************************
//
// Processor ends up here if an unexpected interrupt occurs or a specific
// handler is not present in the application code.
//
//*****************************************************************************
__attribute__ ((section(".after_vectors")))
void IntDefaultHandler(void)
{ while(1) {}
}

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/*----------------------------------------------------------------------------*/
/* Copyright 2020 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may only */
/* be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that you */
/* have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*----------------------------------------------------------------------------*/
/** \file
* Example Source abstracting component data structure and code initialization and code specific to HW used in the examples
* This file shall be present in all examples. A customer does not need to touch/modify this file. This file
* purely depends on the phNxpBuild_Lpc.h or phNxpBuild_App.h
* The phAppInit.h externs the component data structures initialized here that is in turn included by the core examples.
* The core example shall not use any other variable defined here except the RdLib component data structures(as explained above)
* The RdLib component initialization requires some user defined data and function pointers.
* These are defined in the respective examples and externed here.
*
* Keystore and Crypto initialization needs to be handled by application.
*
* $Author$
* $Revision$ (v07.10.00)
* $Date$
*
*/
#include "phApp_Init.h"
#include <phOsal.h>
/*******************************************************************************
** Function Declarations
*******************************************************************************/
/*******************************************************************************
** Function Definitions
*******************************************************************************/
/* Print technology being resolved */
void phApp_PrintTech(uint8_t TechType)
{
switch(TechType)
{
case PHAC_DISCLOOP_POS_BIT_MASK_A:
DEBUG_PRINTF ("\tResolving Type A... \n");
break;
case PHAC_DISCLOOP_POS_BIT_MASK_B:
DEBUG_PRINTF ("\tResolving Type B... \n");
break;
case PHAC_DISCLOOP_POS_BIT_MASK_F212:
DEBUG_PRINTF ("\tResolving Type F with baud rate 212... \n");
break;
case PHAC_DISCLOOP_POS_BIT_MASK_F424:
DEBUG_PRINTF ("\tResolving Type F with baud rate 424... \n");
break;
case PHAC_DISCLOOP_POS_BIT_MASK_V:
DEBUG_PRINTF ("\tResolving Type V... \n");
break;
default:
break;
}
}
/**
* This function will print buffer content
* \param *pBuff Buffer Reference
* \param num data size to be print
*/
void phApp_Print_Buff(uint8_t *pBuff, uint8_t num)
{
uint32_t i;
for(i = 0; i < num; i++)
{
DEBUG_PRINTF(" %02X",pBuff[i]);
}
}
/**
* This function will print Tag information
* \param pDataParams The discovery loop data parameters
* \param wNumberOfTags Total number of tags detected
* \param wTagsDetected Technology Detected
*/
void phApp_PrintTagInfo(phacDiscLoop_Sw_DataParams_t *pDataParams, uint16_t wNumberOfTags, uint16_t wTagsDetected)
{
#if defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_TAGS) || \
defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_P2P_ACTIVE) || \
defined(NXPBUILD__PHAC_DISCLOOP_TYPEB_TAGS) || \
defined(NXPBUILD__PHAC_DISCLOOP_TYPEF_TAGS) || \
defined(NXPBUILD__PHAC_DISCLOOP_TYPEV_TAGS) || \
defined(NXPBUILD__PHAC_DISCLOOP_I18000P3M3_TAGS)
uint8_t bIndex;
#endif
#if defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_TAGS) || defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_P2P_ACTIVE)
uint8_t bTagType;
#endif
#if defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_TAGS) || defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_P2P_ACTIVE)
if (PHAC_DISCLOOP_CHECK_ANDMASK(wTagsDetected, PHAC_DISCLOOP_POS_BIT_MASK_A))
{
if(pDataParams->sTypeATargetInfo.bT1TFlag)
{
DEBUG_PRINTF("\tTechnology : Type A");
DEBUG_PRINTF ("\n\t\tUID :");
phApp_Print_Buff( pDataParams->sTypeATargetInfo.aTypeA_I3P3[0].aUid,
pDataParams->sTypeATargetInfo.aTypeA_I3P3[0].bUidSize);
DEBUG_PRINTF ("\n\t\tSAK : 0x%02x",pDataParams->sTypeATargetInfo.aTypeA_I3P3[0].aSak);
DEBUG_PRINTF ("\n\t\tType: Type 1 Tag\n");
}
else
{
DEBUG_PRINTF("\tTechnology : Type A");
for(bIndex = 0; bIndex < wNumberOfTags; bIndex++)
{
DEBUG_PRINTF ("\n\t\tCard: %d",bIndex + 1);
DEBUG_PRINTF ("\n\t\tUID :");
phApp_Print_Buff( pDataParams->sTypeATargetInfo.aTypeA_I3P3[bIndex].aUid,
pDataParams->sTypeATargetInfo.aTypeA_I3P3[bIndex].bUidSize);
DEBUG_PRINTF ("\n\t\tSAK : 0x%02x",pDataParams->sTypeATargetInfo.aTypeA_I3P3[bIndex].aSak);
if ((pDataParams->sTypeATargetInfo.aTypeA_I3P3[bIndex].aSak & (uint8_t) ~0xFB) == 0)
{
/* Bit b3 is set to zero, [Digital] 4.8.2 */
/* Mask out all other bits except for b7 and b6 */
bTagType = (pDataParams->sTypeATargetInfo.aTypeA_I3P3[bIndex].aSak & 0x60);
bTagType = bTagType >> 5;
switch(bTagType)
{
case PHAC_DISCLOOP_TYPEA_TYPE2_TAG_CONFIG_MASK:
DEBUG_PRINTF ("\n\t\tType: Type 2 Tag\n");
break;
case PHAC_DISCLOOP_TYPEA_TYPE4A_TAG_CONFIG_MASK:
DEBUG_PRINTF ("\n\t\tType: Type 4A Tag\n");
break;
case PHAC_DISCLOOP_TYPEA_TYPE_NFC_DEP_TAG_CONFIG_MASK:
DEBUG_PRINTF ("\n\t\tType: P2P\n");
break;
case PHAC_DISCLOOP_TYPEA_TYPE_NFC_DEP_TYPE4A_TAG_CONFIG_MASK:
DEBUG_PRINTF ("\n\t\tType: Type NFC_DEP and 4A Tag\n");
break;
default:
break;
}
}
}
}
}
#endif
#ifdef NXPBUILD__PHAC_DISCLOOP_TYPEB_TAGS
if (PHAC_DISCLOOP_CHECK_ANDMASK(wTagsDetected, PHAC_DISCLOOP_POS_BIT_MASK_B))
{
DEBUG_PRINTF("\tTechnology : Type B");
/* Loop through all the Type B tags detected and print the Pupi */
for (bIndex = 0; bIndex < wNumberOfTags; bIndex++)
{
DEBUG_PRINTF ("\n\t\tCard: %d",bIndex + 1);
DEBUG_PRINTF ("\n\t\tUID :");
/* PUPI Length is always 4 bytes */
phApp_Print_Buff( pDataParams->sTypeBTargetInfo.aTypeB_I3P3[bIndex].aPupi, 0x04);
}
DEBUG_PRINTF("\n");
}
#endif /* NXPBUILD__PHAC_DISCLOOP_TYPEB_TAGS */
#ifdef NXPBUILD__PHAC_DISCLOOP_TYPEF_TAGS
if( PHAC_DISCLOOP_CHECK_ANDMASK(wTagsDetected, PHAC_DISCLOOP_POS_BIT_MASK_F212) ||
PHAC_DISCLOOP_CHECK_ANDMASK(wTagsDetected, PHAC_DISCLOOP_POS_BIT_MASK_F424))
{
DEBUG_PRINTF("\tTechnology : Type F");
/* Loop through all the type F tags and print the IDm */
for (bIndex = 0; bIndex < wNumberOfTags; bIndex++)
{
DEBUG_PRINTF ("\n\t\tCard: %d",bIndex + 1);
DEBUG_PRINTF ("\n\t\tUID :");
phApp_Print_Buff( pDataParams->sTypeFTargetInfo.aTypeFTag[bIndex].aIDmPMm,
PHAC_DISCLOOP_FELICA_IDM_LENGTH );
if ((pDataParams->sTypeFTargetInfo.aTypeFTag[bIndex].aIDmPMm[0] == 0x01) &&
(pDataParams->sTypeFTargetInfo.aTypeFTag[bIndex].aIDmPMm[1] == 0xFE))
{
/* This is Type F tag with P2P capabilities */
DEBUG_PRINTF ("\n\t\tType: P2P");
}
else
{
/* This is Type F T3T tag */
DEBUG_PRINTF ("\n\t\tType: Type 3 Tag");
}
if(pDataParams->sTypeFTargetInfo.aTypeFTag[bIndex].bBaud != PHAC_DISCLOOP_CON_BITR_212)
{
DEBUG_PRINTF ("\n\t\tBit Rate: 424\n");
}
else
{
DEBUG_PRINTF ("\n\t\tBit Rate: 212\n");
}
}
}
#endif /* NXPBUILD__PHAC_DISCLOOP_TYPEF_TAGS */
#ifdef NXPBUILD__PHAC_DISCLOOP_TYPEV_TAGS
if (PHAC_DISCLOOP_CHECK_ANDMASK(wTagsDetected, PHAC_DISCLOOP_POS_BIT_MASK_V))
{
DEBUG_PRINTF("\tTechnology : Type V / ISO 15693 / T5T");
/* Loop through all the Type V tags detected and print the UIDs */
for (bIndex = 0; bIndex < wNumberOfTags; bIndex++)
{
DEBUG_PRINTF ("\n\t\tCard: %d",bIndex + 1);
DEBUG_PRINTF ("\n\t\tUID :");
phApp_Print_Buff( pDataParams->sTypeVTargetInfo.aTypeV[bIndex].aUid, 0x08);
}
DEBUG_PRINTF("\n");
}
#endif /* NXPBUILD__PHAC_DISCLOOP_TYPEV_TAGS */
#ifdef NXPBUILD__PHAC_DISCLOOP_I18000P3M3_TAGS
if (PHAC_DISCLOOP_CHECK_ANDMASK(wTagsDetected, PHAC_DISCLOOP_POS_BIT_MASK_18000P3M3))
{
DEBUG_PRINTF("\tTechnology : ISO 18000p3m3 / EPC Gen2");
/* Loop through all the 18000p3m3 tags detected and print the UII */
for (bIndex = 0; bIndex < wNumberOfTags; bIndex++)
{
DEBUG_PRINTF("\n\t\tCard: %d",bIndex + 1);
DEBUG_PRINTF("\n\t\tUII :");
phApp_Print_Buff(
pDataParams->sI18000p3m3TargetInfo.aI18000p3m3[bIndex].aUii,
(pDataParams->sI18000p3m3TargetInfo.aI18000p3m3[bIndex].wUiiLength / 8));
}
DEBUG_PRINTF("\n");
}
#endif /* NXPBUILD__PHAC_DISCLOOP_I18000P3M3_TAGS */
}
/**
* This function will print Error information received from Reader Lib
* \param wStatus Error status
*/
void PrintErrorInfo(phStatus_t wStatus)
{
DEBUG_PRINTF("\n ErrorInfo Comp:");
switch(wStatus & 0xFF00)
{
case PH_COMP_BAL:
DEBUG_PRINTF("\t PH_COMP_BAL");
break;
case PH_COMP_HAL:
DEBUG_PRINTF("\t PH_COMP_HAL");
break;
case PH_COMP_PAL_ISO14443P3A:
DEBUG_PRINTF("\t PH_COMP_PAL_ISO14443P3A");
break;
case PH_COMP_PAL_ISO14443P3B:
DEBUG_PRINTF("\t PH_COMP_PAL_ISO14443P3B");
break;
case PH_COMP_PAL_ISO14443P4A:
DEBUG_PRINTF("\t PH_COMP_PAL_ISO14443P4A");
break;
case PH_COMP_PAL_ISO14443P4:
DEBUG_PRINTF("\t PH_COMP_PAL_ISO14443P4");
break;
case PH_COMP_PAL_FELICA:
DEBUG_PRINTF("\t PH_COMP_PAL_FELICA");
break;
case PH_COMP_PAL_EPCUID:
DEBUG_PRINTF("\t PH_COMP_PAL_EPCUID");
break;
case PH_COMP_PAL_SLI15693:
DEBUG_PRINTF("\t PH_COMP_PAL_SLI15693");
break;
case PH_COMP_PAL_I18000P3M3:
DEBUG_PRINTF("\t PH_COMP_PAL_I18000P3M3");
break;
case PH_COMP_PAL_I18092MPI:
DEBUG_PRINTF("\t PH_COMP_PAL_I18092MPI");
break;
case PH_COMP_PAL_I18092MT:
DEBUG_PRINTF("\t PH_COMP_PAL_I18092MT");
break;
case PH_COMP_PAL_I14443P4MC:
DEBUG_PRINTF("\t PH_COMP_PAL_I14443P4MC");
break;
case PH_COMP_AC_DISCLOOP:
DEBUG_PRINTF("\t PH_COMP_AC_DISCLOOP");
break;
case PH_COMP_OSAL:
DEBUG_PRINTF("\t PH_COMP_OSAL");
break;
default:
DEBUG_PRINTF("\t 0x%x",(wStatus & PH_COMPID_MASK));
break;
}
DEBUG_PRINTF("\t type:");
switch(wStatus & PH_ERR_MASK)
{
case PH_ERR_SUCCESS_INCOMPLETE_BYTE:
DEBUG_PRINTF("\t PH_ERR_SUCCESS_INCOMPLETE_BYTE");
break;
case PH_ERR_IO_TIMEOUT:
DEBUG_PRINTF("\t PH_ERR_IO_TIMEOUT");
break;
case PH_ERR_INTEGRITY_ERROR:
DEBUG_PRINTF("\t PH_ERR_INTEGRITY_ERROR");
break;
case PH_ERR_COLLISION_ERROR:
DEBUG_PRINTF("\t PH_ERR_COLLISION_ERROR");
break;
case PH_ERR_BUFFER_OVERFLOW:
DEBUG_PRINTF("\t PH_ERR_BUFFER_OVERFLOW");
break;
case PH_ERR_FRAMING_ERROR:
DEBUG_PRINTF("\t PH_ERR_FRAMING_ERROR");
break;
case PH_ERR_PROTOCOL_ERROR:
DEBUG_PRINTF("\t PH_ERR_PROTOCOL_ERROR");
break;
case PH_ERR_RF_ERROR:
DEBUG_PRINTF("\t PH_ERR_RF_ERROR");
break;
case PH_ERR_EXT_RF_ERROR:
DEBUG_PRINTF("\t PH_ERR_EXT_RF_ERROR");
break;
case PH_ERR_NOISE_ERROR:
DEBUG_PRINTF("\t PH_ERR_NOISE_ERROR");
break;
case PH_ERR_ABORTED:
DEBUG_PRINTF("\t PH_ERR_ABORTED");
break;
case PH_ERR_INTERNAL_ERROR:
DEBUG_PRINTF("\t PH_ERR_INTERNAL_ERROR");
break;
case PH_ERR_INVALID_DATA_PARAMS:
DEBUG_PRINTF("\t PH_ERR_INVALID_DATA_PARAMS");
break;
case PH_ERR_INVALID_PARAMETER:
DEBUG_PRINTF("\t PH_ERR_INVALID_PARAMETER");
break;
case PH_ERR_PARAMETER_OVERFLOW:
DEBUG_PRINTF("\t PH_ERR_PARAMETER_OVERFLOW");
break;
case PH_ERR_UNSUPPORTED_PARAMETER:
DEBUG_PRINTF("\t PH_ERR_UNSUPPORTED_PARAMETER");
break;
case PH_ERR_OSAL_ERROR:
DEBUG_PRINTF("\t PH_ERR_OSAL_ERROR");
break;
case PHAC_DISCLOOP_LPCD_NO_TECH_DETECTED:
DEBUG_PRINTF("\t PHAC_DISCLOOP_LPCD_NO_TECH_DETECTED");
break;
case PHAC_DISCLOOP_COLLISION_PENDING:
DEBUG_PRINTF("\t PHAC_DISCLOOP_COLLISION_PENDING");
break;
default:
DEBUG_PRINTF("\t 0x%x",(wStatus & PH_ERR_MASK));
break;
}
}
/******************************************************************************
** End Of File
******************************************************************************/

View File

@ -0,0 +1,437 @@
/*----------------------------------------------------------------------------*/
/* Copyright 2016-2020,2022 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may only */
/* be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that you */
/* have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*----------------------------------------------------------------------------*/
/** \file
* Example Source abstracting component data structure and code initialization and code specific to HW used in the examples
* This file shall be present in all examples. A customer does not need to touch/modify this file. This file
* purely depends on the phNxpBuild_Lpc.h or phNxpBuild_App.h
* The phAppInit.h externs the component data structures initialized here that is in turn included by the core examples.
* The core example shall not use any other variable defined here except the RdLib component data structures(as explained above)
* The RdLib component initialization requires some user defined data and function pointers.
* These are defined in the respective examples and externed here.
*
* Keystore and Crypto initialization needs to be handled by application.
*
* $Author$
* $Revision$ (v07.10.00)
* $Date$
*
*/
/* Status header */
#include <ph_Status.h>
#include "phApp_Init.h"
/* NFCLIB Header */
#include <phNfcLib.h>
#include <phOsal.h>
#ifdef PH_PLATFORM_HAS_ICFRONTEND
#include "BoardSelection.h"
#endif /* PH_PLATFORM_HAS_ICFRONTEND */
#ifdef PHDRIVER_KINETIS_K82
#include <fsl_port.h>
#include <fsl_pit.h>
#ifdef DEBUG
#include <fsl_clock.h>
#endif /* DEBUG */
#endif /* PHDRIVER_KINETIS_K82 */
#ifdef PHDRIVER_KINETIS_K82
#ifdef DEBUG
#define KINETIS_K82_DEBUG_UART_CLK_FREQ CLOCK_GetOsc0ErClkFreq()
#define KINETIS_K82_DEBUG_UART_BASEADDR (uint32_t)(LPUART4)
#define KINETIS_K82_DEBUG_UART_INSTANCE 4U
#define KINETIS_K82_DEBUG_UART_BAUDRATE 115200
#define KINETIS_K82_DEBUG_UART_TYPE DEBUG_CONSOLE_DEVICE_TYPE_LPUART
#endif /* DEBUG */
/*! @brief Clock configuration structure. */
typedef struct _clock_config
{
mcg_config_t mcgConfig; /*!< MCG configuration. */
sim_clock_config_t simConfig; /*!< SIM configuration. */
osc_config_t oscConfig; /*!< OSC configuration. */
uint32_t coreClock; /*!< core clock frequency. */
} clock_config_t;
#endif /* PHDRIVER_KINETIS_K82 */
#ifdef PH_OSAL_LINUX
# define PI_IRQ_POLLING_TASK_PRIO 0
# define PI_IRQ_POLLING_TASK_STACK 0x20000
phOsal_ThreadObj_t gphPiThreadObj;
#endif /* PH_OSAL_LINUX */
#if defined(PHDRIVER_LPC1769) && defined(__CC_ARM)
uint32_t SystemCoreClock;
#endif
/*******************************************************************************
** Function Declarations
*******************************************************************************/
#ifdef PHDRIVER_KINETIS_K82
static void phApp_K82_Init(void);
#endif /* PHDRIVER_KINETIS_K82 */
#ifdef PH_OSAL_LINUX
static void phExample_IrqPolling(void* param);
#endif /* PH_OSAL_LINUX */
phStatus_t phApp_Configure_IRQ();
/*******************************************************************************
** Clock configuration of K82 Platform
*******************************************************************************/
#ifdef PHDRIVER_KINETIS_K82
/* Configuration for enter RUN mode. Core clock = 50MHz. */
const clock_config_t g_defaultClockConfigRun = {
.mcgConfig =
{
.mcgMode = kMCG_ModePEE, /* Work in PEE mode. */
.irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enable. */
.ircs = kMCG_IrcSlow, /* Select IRC32k. */
.fcrdiv = 0U, /* FCRDIV is 0. */
.frdiv = 4U,
.drs = kMCG_DrsLow, /* Low frequency range. */
.dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25%. */
.oscsel = kMCG_OscselOsc, /* Select OSC. */
.pll0Config =
{
.enableMode = 0U, .prdiv = 0x01U, .vdiv = 0x01U,
},
},
.simConfig =
{
.pllFllSel = 1U, /* PLLFLLSEL select PLL. */
.pllFllDiv = 0U, /* PLLFLLSEL clock divider divisor. */
.pllFllFrac = 0U, /* PLLFLLSEL clock divider fraction. */
.er32kSrc = 5U, /* ERCLK32K selection, use RTC. */
.clkdiv1 = 0x01140000U, /* SIM_CLKDIV1. */
},
.oscConfig = {.freq = CPU_XTAL_CLK_HZ,
.capLoad = 0,
.workMode = kOSC_ModeOscLowPower,
.oscerConfig =
{
.enableMode = kOSC_ErClkEnable,
#if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER)
.erclkDiv = 0U,
#endif
}},
};
#endif /* PHDRIVER_KINETIS_K82 */
/*******************************************************************************
** Global Variable Declaration
*******************************************************************************/
#ifdef NXPBUILD__PHLN_LLCP_SW
phlnLlcp_Sw_DataParams_t slnLlcp; /* LLCP component */
#endif /* NXPBUILD__PHLN_LLCP_SW */
/* General information bytes to be sent with ATR Request */
#if defined(NXPBUILD__PHPAL_I18092MPI_SW) || defined(NXPBUILD__PHPAL_I18092MT_SW)
uint8_t aLLCPGeneralBytes[36] = { 0x46,0x66,0x6D,
0x01,0x01,0x10, /*VERSION*/
0x03,0x02,0x00,0x01, /*WKS*/
0x04,0x01,0xF1 /*LTO*/
};
uint8_t bLLCPGBLength = 13;
#endif
/* ATR Response or ATS Response holder */
#if defined(NXPBUILD__PHPAL_I14443P4A_SW) || \
defined(NXPBUILD__PHPAL_I18092MPI_SW)
uint8_t aResponseHolder[64];
#endif
/* prints if error is detected */
#define CHECK_SUCCESS(x) \
if ((x) != PH_ERR_SUCCESS) \
{ \
DEBUG_PRINTF("\nLine: %d Error - (0x%04X) has occurred : 0xCCEE CC-Component ID, EE-Error code. Refer-ph_Status.h\n ", __LINE__, (x)); \
return (x); \
}
/*******************************************************************************
** Function Definitions
*******************************************************************************/
#ifdef PHDRIVER_KINETIS_K82
static void phApp_K82_Init(void)
{
#ifdef DEBUG
uint32_t uartClkSrcFreq;
#endif /* DEBUG */
pit_config_t pitConfig; /* Structure of initialize PIT */
CLOCK_SetSimSafeDivs();
CLOCK_InitOsc0(&g_defaultClockConfigRun.oscConfig);
CLOCK_SetXtal0Freq(CPU_XTAL_CLK_HZ);
CLOCK_BootToPeeMode(g_defaultClockConfigRun.mcgConfig.oscsel, kMCG_PllClkSelPll0,
&g_defaultClockConfigRun.mcgConfig.pll0Config);
CLOCK_SetInternalRefClkConfig(g_defaultClockConfigRun.mcgConfig.irclkEnableMode,
g_defaultClockConfigRun.mcgConfig.ircs, g_defaultClockConfigRun.mcgConfig.fcrdiv);
CLOCK_SetSimConfig(&g_defaultClockConfigRun.simConfig);
SystemCoreClockUpdate();
/*
* pitConfig.enableRunInDebug = false;
*/
PIT_GetDefaultConfig(&pitConfig);
/* Init pit module */
PIT_Init(PIT, &pitConfig);
#ifdef DEBUG
/* Initialize LPUART4 pins below used to Print */
/* Ungate the port clock */
CLOCK_EnableClock(kCLOCK_PortC);
/* Affects PORTC_PCR14 register */
PORT_SetPinMux(PORTC, 14U, kPORT_MuxAlt3);
/* Affects PORTC_PCR15 register */
PORT_SetPinMux(PORTC, 15U, kPORT_MuxAlt3);
/* SIM_SOPT2[27:26]:
* 00: Clock Disabled
* 01: MCGFLLCLK, or MCGPLLCLK, or IRC48M
* 10: OSCERCLK
* 11: MCGIRCCLK
*/
CLOCK_SetLpuartClock(2);
uartClkSrcFreq = KINETIS_K82_DEBUG_UART_CLK_FREQ;
DbgConsole_Init(KINETIS_K82_DEBUG_UART_INSTANCE, KINETIS_K82_DEBUG_UART_BAUDRATE, KINETIS_K82_DEBUG_UART_TYPE, uartClkSrcFreq);
#endif /* DEBUG */
}
#endif /* PHDRIVER_KINETIS_K82 */
#ifdef PH_PLATFORM_HAS_ICFRONTEND
/**
* This function will initialize Host Controller interfaced with NXP Reader IC's.
* Any initialization which is not generic across Platforms, should be done here.
* Note: For NXP NFC Controllers HOST initialization is not required.
*/
void phApp_CPU_Init(void)
{
#if defined PHDRIVER_KINETIS_K82
phApp_K82_Init();
#elif defined(PHDRIVER_LPC1769) && defined(__CC_ARM)
SystemCoreClock = (( unsigned long ) 96000000);
#elif defined(PH_OSAL_LINUX) && defined(NXPBUILD__PHHAL_HW_PN5190)
phStatus_t status;
status = PiGpio_OpenIrq();
if ((status & PH_ERR_MASK) != PH_ERR_SUCCESS)
{
DEBUG_PRINTF("\n PiGpio_OpenIrq failed \n");
DEBUG_PRINTF("\n Couldn't open PN5190 Kernel IRQ Driver.\n Halting here!!FIX IT!!\n");
while(1);
}
#else
/* In case of LPC series, startup file takes care of initializing clock and ports.
* No initialization is required in Linux environment. */
#endif
}
#endif /* PH_PLATFORM_HAS_ICFRONTEND */
/**
* This function will initialize Reader LIbrary Component
*/
phStatus_t phApp_Comp_Init(void * pDiscLoopParams)
{
phStatus_t wStatus = PH_ERR_SUCCESS;
#if defined(NXPBUILD__PHPAL_I18092MPI_SW) || defined(NXPBUILD__PHPAL_I18092MT_SW) || \
defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_P2P_TAGS) || defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_P2P_ACTIVE) || \
defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_I3P4_TAGS) || defined(NXPBUILD__PHAC_DISCLOOP_TYPEF_P2P_TAGS) || \
defined(NXPBUILD__PHAC_DISCLOOP_TYPEF212_P2P_ACTIVE) || defined(NXPBUILD__PHAC_DISCLOOP_TYPEF424_P2P_ACTIVE)
phacDiscLoop_Sw_DataParams_t * pDiscLoop = (phacDiscLoop_Sw_DataParams_t *)pDiscLoopParams;
#endif
/* Initialize the LLCP component */
#ifdef NXPBUILD__PHLN_LLCP_SW
slnLlcp.sLocalLMParams.wMiu = 0x00; /* 128 bytes only */
slnLlcp.sLocalLMParams.wWks = 0x11; /* SNEP & LLCP */
slnLlcp.sLocalLMParams.bLto = 100; /* Maximum LTO */
slnLlcp.sLocalLMParams.bOpt = 0x02;
slnLlcp.sLocalLMParams.bAvailableTlv = PHLN_LLCP_TLV_MIUX_MASK | PHLN_LLCP_TLV_WKS_MASK |
PHLN_LLCP_TLV_LTO_MASK | PHLN_LLCP_TLV_OPT_MASK;
wStatus = phlnLlcp_Sw_Init(
&slnLlcp,
sizeof(phlnLlcp_Sw_DataParams_t),
aLLCPGeneralBytes,
&bLLCPGBLength);
#endif /* NXPBUILD__PHLN_LLCP_SW */
#ifdef NXPBUILD__PHAC_DISCLOOP_SW
#if defined(NXPBUILD__PHPAL_I18092MPI_SW) || defined(NXPBUILD__PHPAL_I18092MT_SW)
/* Assign the GI for Type A */
pDiscLoop->sTypeATargetInfo.sTypeA_P2P.pGi = (uint8_t *)aLLCPGeneralBytes;
pDiscLoop->sTypeATargetInfo.sTypeA_P2P.bGiLength = bLLCPGBLength;
/* Assign the GI for Type F */
pDiscLoop->sTypeFTargetInfo.sTypeF_P2P.pGi = (uint8_t *)aLLCPGeneralBytes;
pDiscLoop->sTypeFTargetInfo.sTypeF_P2P.bGiLength = bLLCPGBLength;
#endif
#if defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_P2P_TAGS) || defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_P2P_ACTIVE)
/* Assign ATR response for Type A */
pDiscLoop->sTypeATargetInfo.sTypeA_P2P.pAtrRes = aResponseHolder;
#endif
#if defined(NXPBUILD__PHAC_DISCLOOP_TYPEF_P2P_TAGS) || defined(NXPBUILD__PHAC_DISCLOOP_TYPEF212_P2P_ACTIVE) || \
defined(NXPBUILD__PHAC_DISCLOOP_TYPEF424_P2P_ACTIVE)
/* Assign ATR response for Type F */
pDiscLoop->sTypeFTargetInfo.sTypeF_P2P.pAtrRes = aResponseHolder;
#endif
#ifdef NXPBUILD__PHAC_DISCLOOP_TYPEA_I3P4_TAGS
/* Assign ATS buffer for Type A */
pDiscLoop->sTypeATargetInfo.sTypeA_I3P4.pAts = aResponseHolder;
#endif /* NXPBUILD__PHAC_DISCLOOP_TYPEA_I3P4_TAGS */
#endif /* NXPBUILD__PHAC_DISCLOOP_SW */
return wStatus;
}
phStatus_t phApp_Configure_IRQ()
{
#ifdef PH_OSAL_LINUX
phStatus_t wStatus;
#endif /* PH_OSAL_LINUX */
#ifdef PH_PLATFORM_HAS_ICFRONTEND
#if !(defined(PH_OSAL_LINUX) && defined(NXPBUILD__PHHAL_HW_PN5190))
phDriver_Pin_Config_t pinCfg;
pinCfg.bOutputLogic = PH_DRIVER_SET_LOW;
pinCfg.bPullSelect = PHDRIVER_PIN_IRQ_PULL_CFG;
pinCfg.eInterruptConfig = PIN_IRQ_TRIGGER_TYPE;
phDriver_PinConfig(PHDRIVER_PIN_IRQ, PH_DRIVER_PINFUNC_INTERRUPT, &pinCfg);
#endif
#ifdef PHDRIVER_LPC1769
NVIC_SetPriority(EINT_IRQn, EINT_PRIORITY);
/* Enable interrupt in the NVIC */
NVIC_ClearPendingIRQ(EINT_IRQn);
NVIC_EnableIRQ(EINT_IRQn);
#endif /* PHDRIVER_LPC1769 */
#ifdef PH_OSAL_LINUX
gphPiThreadObj.pTaskName = (uint8_t *) "IrqPolling";
gphPiThreadObj.pStackBuffer = NULL;
gphPiThreadObj.priority = PI_IRQ_POLLING_TASK_PRIO;
gphPiThreadObj.stackSizeInNum = PI_IRQ_POLLING_TASK_STACK;
PH_CHECK_SUCCESS_FCT(wStatus, phOsal_ThreadCreate(&gphPiThreadObj.ThreadHandle, &gphPiThreadObj,
&phExample_IrqPolling, NULL));
#endif /* PH_OSAL_LINUX */
#ifdef PHDRIVER_KINETIS_K82
NVIC_SetPriority(EINT_IRQn, EINT_PRIORITY);
NVIC_ClearPendingIRQ(EINT_IRQn);
EnableIRQ(EINT_IRQn);
#endif /* PHDRIVER_KINETIS_K82 */
#endif /* #ifdef PH_PLATFORM_HAS_ICFRONTEND */
return PH_ERR_SUCCESS;
}
#ifdef PH_OSAL_LINUX
/*
* \brief: The purpose of this Thread is to detect RF signal from an External Peer .
*/
static void phExample_IrqPolling(void* param)
{
uint8_t bgpioVal = 0;
uint8_t bhighOrLow = 0;
#if defined(NXPBUILD__PHHAL_HW_RC663) || defined(NXPBUILD__PHHAL_HW_PN5180)
if(PIN_IRQ_TRIGGER_TYPE == PH_DRIVER_INTERRUPT_RISINGEDGE)
{
bhighOrLow = 1;
}
while(PiGpio_read(PHDRIVER_PIN_IRQ, &bgpioVal) != PH_ERR_SUCCESS)
{
PiGpio_unexport(PHDRIVER_PIN_IRQ);
PiGpio_export(PHDRIVER_PIN_IRQ);
PiGpio_set_direction(PHDRIVER_PIN_IRQ, false);
if(PIN_IRQ_TRIGGER_TYPE == PH_DRIVER_INTERRUPT_RISINGEDGE)
{
PiGpio_set_edge(PHDRIVER_PIN_IRQ, true, false);
}
else
{
PiGpio_set_edge(PHDRIVER_PIN_IRQ, false, true);
}
}
/* Initial status: If pin is already Active, post an event. */
if(bgpioVal == bhighOrLow)
{
CLIF_IRQHandler();
}
#endif
while(1)
{
/* Block forever for Raising Edge in PHDRIVER_PIN_IRQ. */
#if defined(NXPBUILD__PHHAL_HW_RC663) || defined(NXPBUILD__PHHAL_HW_PN5180)
if(PiGpio_poll(PHDRIVER_PIN_IRQ, bhighOrLow, -1) == PH_ERR_SUCCESS)
#elif defined(NXPBUILD__PHHAL_HW_PN5190)
if(PiGpio_Irq() == PH_ERR_SUCCESS)
#endif
{
CLIF_IRQHandler();
}
else
{
PiGpio_unexport(PHDRIVER_PIN_IRQ);
PiGpio_export(PHDRIVER_PIN_IRQ);
PiGpio_set_direction(PHDRIVER_PIN_IRQ, false);
if(PIN_IRQ_TRIGGER_TYPE == PH_DRIVER_INTERRUPT_RISINGEDGE)
{
PiGpio_set_edge(PHDRIVER_PIN_IRQ, true, false);
}
else
{
PiGpio_set_edge(PHDRIVER_PIN_IRQ, false, true);
}
}
}
}
#endif /* PH_OSAL_LINUX */
/******************************************************************************
** End Of File
******************************************************************************/

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/*----------------------------------------------------------------------------*/
/* Copyright 2020,2023 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may only */
/* be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that you */
/* have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*----------------------------------------------------------------------------*/
/** \file
* Example Source abstracting component data structure and code initialization and code specific to HW used in the examples
* This file shall be present in all examples. A customer does not need to touch/modify this file. This file
* purely depends on the phNxpBuild_Lpc.h or phNxpBuild_App.h
* The phAppInit.h externs the component data structures initialized here that is in turn included by the core examples.
* The core example shall not use any other variable defined here except the RdLib component data structures(as explained above)
* The RdLib component initialization requires some user defined data and function pointers.
* These are defined in the respective examples and externed here.
*
* Keystore and Crypto initialization needs to be handled by application.
*
* $Author$
* $Revision$ (v07.10.00)
* $Date$
*
*/
/* Status header */
#include <ph_Status.h>
#include "phApp_Init.h"
#ifdef NXPBUILD__PHHAL_HW_PN5180
#include "BoardSelection.h"
/* HAL specific headers */
#include <phhalHw_Pn5180_Instr.h>
/*******************************************************************************
** Function Declarations
*******************************************************************************/
/*******************************************************************************
** Global Variable Declaration
*******************************************************************************/
phbalReg_Type_t sBalParams;
phhalHw_Pn5180_DataParams_t * pHal;
#ifdef NXPBUILD__PHHAL_HW_TARGET
/* Parameters for L3 activation during Autocoll */
extern uint8_t sens_res[2] ;
extern uint8_t nfc_id1[3] ;
extern uint8_t sel_res ;
extern uint8_t nfc_id3 ;
extern uint8_t poll_res[18] ;
#endif /* NXPBUILD__PHHAL_HW_TARGET */
/*******************************************************************************
** Function Definitions
*******************************************************************************/
/**
* This function will initialize Hal Target Config
*/
phStatus_t phApp_HALConfigAutoColl(void)
{
#ifdef NXPBUILD__PHHAL_HW_TARGET
phStatus_t wStatus;
uint8_t baDynamicUidConfig[1U] = { 1U };
uint8_t baReadEepromConfig[24U] = { 0U };
/* Read Set Listen Parameters data from EEPROM */
wStatus = phhalHw_Pn5180_Instr_ReadE2Prom(
(phhalHw_Pn5180_DataParams_t *) pHal,
PHHAL_HW_PN5180_SET_LISTEN_E2PROM_ADDR,
baReadEepromConfig,
24U
);
CHECK_SUCCESS(wStatus);
/* Verify EEPROM data and configure Set Listen Parameters if EEPROM data is not correct. */
if ((memcmp(&baReadEepromConfig[0U], sens_res, 2U) != 0x00) ||
(memcmp(&baReadEepromConfig[2U], nfc_id1, 3U) != 0x00) ||
(memcmp(&baReadEepromConfig[5U], &sel_res, 1U) != 0x00) ||
(memcmp(&baReadEepromConfig[6U], poll_res, 18U) != 0x00))
{
/* Configure Set Listen Parameters. */
wStatus = phhalHw_Pn5180_SetListenParameters(
pHal,
&sens_res[0],
&nfc_id1[0],
sel_res,
&poll_res[0],
nfc_id3
);
CHECK_SUCCESS(wStatus);
}
if (pHal->wFirmwareVer < 0x308U)
{
/* With Pn5180 FW version < 3.8, only static UID is supported. */
baDynamicUidConfig[0] = 0x00;
}
/* Read Dynamic UID configuration from EEPROM */
wStatus = phhalHw_Pn5180_Instr_ReadE2Prom(
(phhalHw_Pn5180_DataParams_t *) pHal,
PHHAL_HW_PN5180_DYN_UID_CFG_E2PROM_ADDR,
baReadEepromConfig,
1U
);
CHECK_SUCCESS(wStatus);
/* Verify EEPROM data and perform Dynamic UID configuration if EEPROM data is not correct. */
if (memcmp(baReadEepromConfig, baDynamicUidConfig, 1U) != 0x00)
{
/* Configure Dynamic UID */
wStatus = phhalHw_Pn5180_Instr_WriteE2Prom(
(phhalHw_Pn5180_DataParams_t *) pHal,
PHHAL_HW_PN5180_DYN_UID_CFG_E2PROM_ADDR,
baDynamicUidConfig,
1U
);
CHECK_SUCCESS(wStatus);
}
#endif /* NXPBUILD__PHHAL_HW_TARGET */
return PH_ERR_SUCCESS;
}
/* Configure LPCD (for PN5180) */
phStatus_t phApp_ConfigureLPCD(void)
{
/**
* PHHAL_HW_CONFIG_SET_LPCD_WAKEUPTIME_MS 0x0070U //< Used value for wakeup counter in msecs, i.e. after this amount of time IC will wakes up from standby.
* PHHAL_HW_CONFIG_LPCD_MODE 0x0071U //< Used to set options PHHAL_HW_PN5180_LPCD_MODE_DEFAULT or PHHAL_HW_PN5180_LPCD_MODE_POWERDOWN_GUARDED
* PHHAL_HW_CONFIG_LPCD_REF 0x0072U //< Used to set or get LPCD Ref
*/
phStatus_t status = PH_ERR_SUCCESS;
uint16_t wConfig = PHHAL_HW_CONFIG_LPCD_REF;
uint16_t wValue;
uint8_t bLPCD_Threshold_EEPROMAddress = 0x37;
uint8_t bLPCD_Threshold = 0x10;
wValue = PHHAL_HW_PN5180_LPCD_MODE_POWERDOWN;
wConfig = PHHAL_HW_CONFIG_LPCD_MODE;
//status = phhalHw_Pn5180_Int_LPCD_GetConfig(pHal, wConfig, &wValue);
status = phhalHw_Pn5180_Instr_WriteE2Prom(pHal,bLPCD_Threshold_EEPROMAddress, &bLPCD_Threshold, 1 );
CHECK_SUCCESS(status);
status = phhalHw_Pn5180_Int_LPCD_SetConfig(
pHal,
wConfig,
wValue
);
return status;
}
void CLIF_IRQHandler(void)
{
/* Read the interrupt status of external interrupt attached to the reader IC IRQ pin */
if (phDriver_PinRead(PHDRIVER_PIN_IRQ, PH_DRIVER_PINFUNC_INTERRUPT))
{
phDriver_PinClearIntStatus(PHDRIVER_PIN_IRQ);
/* Call application registered callback. */
if (pHal->pRFISRCallback != NULL)
{
pHal->pRFISRCallback(pHal);
}
}
}
#endif /* NXPBUILD__PHHAL_HW_PN5180 */
/******************************************************************************
** End Of File
******************************************************************************/

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PROJECT(Nfcrdlib_SimplifiedAPI_ISO)
FILE(GLOB Nfcrdlib_SimplifiedAPI_ISO_Sources
*.c
src/*.c
)
include_directories(
intfs
types
)
ADD_EXECUTABLE(Nfcrdlib_SimplifiedAPI_ISO
${Nfcrdlib_SimplifiedAPI_ISO_Sources}
)
TARGET_LINK_LIBRARIES(
Nfcrdlib_SimplifiedAPI_ISO
phOsal
DAL
NxpRdLib_acDiscLoop
NxpRdLib_halHw
NxpRdLib_KeyStore
NxpRdLib_phTools
NxpRdLib_palFelica
NxpRdLib_palI18092mPI
NxpRdLib_palI14443p4a
NxpRdLib_palI14443p4
NxpRdLib_palI14443p4
NxpRdLib_palMifare
NxpRdLib_alFelica
NxpRdLib_alMful
NxpRdLib_alMfdf
NxpRdLib_alT1T
NxpRdLib_alTop
NxpRdLib_alMfc
NxpRdLib_lnLlcp
NxpRdLib_phTools
NxpRdLib_palI18092mT
NxpRdLib_npSnep
NxpRdLib_alMfNtag42XDna
NxpRdLib_phNfcLib
NxpRdLib_palEpcUid
)

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/*----------------------------------------------------------------------------*/
/* Copyright 2017-2021,2023 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may only */
/* be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that you */
/* have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*----------------------------------------------------------------------------*/
/** \file
*
* $Author$
* $Revision$ (v07.10.00)
* $Date$
*
*/
/**
* Reader Library Headers
*/
#include <Nfcrdlib_SimplifiedApi_ISO.h>
/*******************************************************************************
** Definitions
*******************************************************************************/
#define DATA_BUFFER_LEN 256 /* Buffer length */
uint8_t bMoreDataAvailable = 0;
uint16_t wNumberofBytes = 256;
phNfcLib_Transmit_t phNfcLib_TransmitInput;
phNfcLib_PeerInfo_t PeerInfo = {0};
uint8_t bDataBuffer[DATA_BUFFER_LEN]; /* universal data buffer */
#ifdef PHOSAL_FREERTOS_STATIC_MEM_ALLOCATION
uint32_t aSimplifiedTaskBuffer[SIMPLIFIED_ISO_STACK];
#else /* PHOSAL_FREERTOS_STATIC_MEM_ALLOCATION */
#define aSimplifiedTaskBuffer NULL
#endif /* PHOSAL_FREERTOS_STATIC_MEM_ALLOCATION */
#ifdef PH_OSAL_FREERTOS
const uint8_t bTaskName[configMAX_TASK_NAME_LEN] = {"SimplifiedApi"};
#else
const uint8_t bTaskName[] = {"SimplifiedApi"};
#endif /* PH_OSAL_FREERTOS */
/*******************************************************************************
** Static Defines
*******************************************************************************/
static volatile uint8_t bInfLoop = 1U;
/*******************************************************************************
** Prototypes
*******************************************************************************/
void SimplifiedApiDemo (void* pParams);
/*******************************************************************************
** Code
*******************************************************************************/
int main(void)
{
do
{
phStatus_t status;
phNfcLib_Status_t dwStatus;
#ifdef PH_PLATFORM_HAS_ICFRONTEND
phNfcLib_AppContext_t AppContext = {0};
#endif /* PH_PLATFORM_HAS_ICFRONTEND */
#ifndef PH_OSAL_NULLOS
phOsal_ThreadObj_t SimplifiedApi;
#endif /* PH_OSAL_NULLOS */
#ifndef MCUXPRESSO_SDK
/* Perform Controller specific initialization. */
phApp_CPU_Init();
#endif
/* Perform OSAL Initialization. */
(void)phOsal_Init();
#ifdef PH_PLATFORM_HAS_ICFRONTEND
status = phbalReg_Init(&sBalParams, sizeof(phbalReg_Type_t));
CHECK_STATUS(status);
AppContext.pBalDataparams = &sBalParams;
dwStatus = phNfcLib_SetContext(&AppContext);
CHECK_NFCLIB_STATUS(dwStatus);
#endif /* PH_PLATFORM_HAS_ICFRONTEND */
/* Initialize library */
dwStatus = phNfcLib_Init();
CHECK_NFCLIB_STATUS(dwStatus);
if(dwStatus != PH_NFCLIB_STATUS_SUCCESS) break;
/* Set the generic pointer */
pHal = phNfcLib_GetDataParams(PH_COMP_HAL);
/* IRQ configuration for different HOST environments */
status = phApp_Configure_IRQ();
CHECK_STATUS(status);
if(status != PH_ERR_SUCCESS) break;
DEBUG_PRINTF("\n Simplified API ISO example: ");
#ifndef PH_OSAL_NULLOS
SimplifiedApi.pTaskName = (uint8_t *)bTaskName;
SimplifiedApi.pStackBuffer = aSimplifiedTaskBuffer;
SimplifiedApi.priority = SIMPLIFIED_ISO_PRIO;
SimplifiedApi.stackSizeInNum = SIMPLIFIED_ISO_STACK;
phOsal_ThreadCreate(&SimplifiedApi.ThreadHandle, &SimplifiedApi, &SimplifiedApiDemo, NULL);
phOsal_StartScheduler();
DEBUG_PRINTF("RTOS Error : Scheduler exited. \n");
#else
SimplifiedApiDemo(NULL);
#endif /* PH_OSAL_NULLOS */
} while(0);
while(bInfLoop); /* Comes here if initialization failure or scheduler exit due to error */
return 0;
}
void SimplifiedApiDemo (void* pParams)
{
uint32_t dwStatus = 0;
uint16_t wStatus = 0;
uint16_t wTechnologyMask = 0x1B;
uint8_t bAtqb[13] = {0x00};
uint8_t bAtqbLen = 0;
uint8_t bGetParamDemo = 0;
/* This call shall allocate secure context before calling any secure function,
* when FreeRtos trust zone is enabled.
* */
phOsal_ThreadSecureStack( 512 );
while(1)
{
do
{
/* Configuring the activation profile as ISO */
phNfcLib_SetConfig_Value(PH_NFCLIB_CONFIG_ACTIVATION_PROFILE, PH_NFCLIB_ACTIVATION_PROFILE_ISO);
if(dwStatus != PH_NFCLIB_STATUS_SUCCESS)
{
break;
}
/* Activating the card with blocking activation mode */
dwStatus = phNfcLib_Activate(wTechnologyMask, &PeerInfo, NULL);
if(dwStatus != PH_NFCLIB_STATUS_PEER_ACTIVATION_DONE)
{
break;
}
bGetParamDemo = 0;
switch(PeerInfo.dwActivatedType)
{
/* Reference application for the particular tech type will divert form here */
case E_PH_NFCLIB_MIFARE_CLASSIC_1K:
DEBUG_PRINTF (" \nMIFARE Classic contactless IC 1K detected... \n");
dwStatus = NfcLib_MifareClassic_1k_Reference_app();
break;
case E_PH_NFCLIB_MIFARE_CLASSIC_4K:
DEBUG_PRINTF (" \nMifare Classic 4K detected... \n");
dwStatus = NfcLib_MifareClassic_1k_Reference_app();
break;
case E_PH_NFCLIB_MIFARE_ULTRALIGHT:
DEBUG_PRINTF (" \nMIFARE Ultralight contactless IC detected... \n");
dwStatus = NfcLib_MifareUltralight_Reference_app();
break;
case E_PH_NFCLIB_MIFARE_DESFIRE:
DEBUG_PRINTF (" \nMIFARE DESFire contactless IC detected... \n");
DEBUG_PRINTF (" \nMifare Desfire not supported in simplified api... \n");
break;
case E_PH_NFCLIB_TYPEB_LAYER3:
DEBUG_PRINTF (" \nType B Layer 3 card detected... \n");
DEBUG_PRINTF (" \nThis application contains nothing for only layer 3 Type B card... \n");
break;
case E_PH_NFCLIB_TYPEA_LAYER3:
DEBUG_PRINTF (" \nType A Layer 3 card or Mifare Classic/ultralight with merged atqa detected... \n");
DEBUG_PRINTF (" \nThis application contains nothing for only layer 3 Type A card... \n");
break;
case E_PH_NFCLIB_TYPEA_LAYER4:
DEBUG_PRINTF (" \nType A Layer 4 card or Mifare desfire with merged atqa detected... \n");
dwStatus = NfcLib_Layer4TypeA_Reference_app();
break;
case E_PH_NFCLIB_TYPEB_LAYER4:
DEBUG_PRINTF (" \nType B Layer 4 card detected... \n");
DEBUG_PRINTF (" \n Do not remove the card ..\n");
DEBUG_PRINTF (" \n Wait till operation completes... \n");
dwStatus = NfcLib_TypeB_Reference_app();
bGetParamDemo = 1;
break;
case E_PH_NFCLIB_ISO15693:
DEBUG_PRINTF (" \nType ISO 15693 compatible card detected... \n");
dwStatus = NfcLib_ISO15693_Reference_app();
break;
case E_PH_NFCLIB_ISO18000p3m3:
DEBUG_PRINTF (" \nType ISO 18000 compatible card detected... \n");
dwStatus = NfcLib_ISO18000p3m3_Reference_app();
break;
default:
break;
}
dwStatus = phNfcLib_Deactivate(PH_NFCLIB_DEACTIVATION_MODE_RELEASE,
&PeerInfo
);
DEBUG_PRINTF("\n Please remove the card\n");
if(bGetParamDemo)
{
(void)phhalHw_SetConfig(phNfcLib_GetDataParams(PH_COMP_HAL),
PHHAL_HW_CONFIG_SET_EMD,
PH_OFF);
(void)phhalHw_Wait(phNfcLib_GetDataParams(PH_COMP_HAL),
PHHAL_HW_TIME_MILLISECONDS,
5);
wStatus = phpalI14443p3b_WakeUpB(phNfcLib_GetDataParams(PH_COMP_PAL_ISO14443P3B),
0x00, 0x00,
0x00, &bAtqb[0], &bAtqbLen);
wStatus = wStatus & PH_ERR_MASK;
while(((wStatus == PH_ERR_SUCCESS) || (wStatus == PH_ERR_COLLISION_ERROR)))
{
(void)phpalI14443p3b_HaltB(phNfcLib_GetDataParams(PH_COMP_PAL_ISO14443P3B));
(void)phhalHw_Wait(phNfcLib_GetDataParams(PH_COMP_HAL),
PHHAL_HW_TIME_MILLISECONDS,
5);
wStatus = phpalI14443p3b_WakeUpB(phNfcLib_GetDataParams(PH_COMP_PAL_ISO14443P3B), 0x00, 0x00,
0x00, &bAtqb[0], &bAtqbLen);
wStatus = wStatus & PH_ERR_MASK;
}
}
if(dwStatus != PH_NFCLIB_STATUS_SUCCESS)
{
DEBUG_PRINTF (" \nDeactivate with Release Mode failed, card was removed from vicinity... \n");
DEBUG_PRINTF (" \n Thus Performing Deactivate with RF OFF mode... \n");
dwStatus = phNfcLib_Deactivate(PH_NFCLIB_DEACTIVATION_MODE_RF_OFF,
&PeerInfo
);
}
if(bGetParamDemo)
{
(void)phhalHw_Wait(phNfcLib_GetDataParams(PH_COMP_HAL), PHHAL_HW_TIME_MILLISECONDS, 1000);
}
} while(0);
}
}
#ifdef NXPBUILD__PHHAL_HW_TARGET
/* Stubbed definitions in case TARGET is enabled */
uint8_t sens_res[2] = {0x04, 0x00};
uint8_t nfc_id1[3] = {0xA1, 0xA2, 0xA3};
uint8_t sel_res = 0x40;
uint8_t nfc_id3 = 0xFA;
uint8_t poll_res[18] = {0x01, 0xFE, 0xB2, 0xB3, 0xB4, 0xB5,
0xB6, 0xB7, 0xC0, 0xC1, 0xC2, 0xC3,
0xC4, 0xC5, 0xC6, 0xC7, 0x23, 0x45 };
#endif /* NXPBUILD__PHHAL_HW_TARGET */

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__________________________________________________
NXPNFCRDLIB EXAMPLE : NFCRDLIB_SIMPLIFIEDAPI_ISO
(V07.10.00)
__________________________________________________
Table of Contents
_________________
1 Document Purpose
2 Description of the Nfcrdlib_SimplifiedAPI_ISO
3 Restrictions on Nfcrdlib_SimplifiedAPI_ISO
4 Package Contents
5 Mandatory materials (not included)
6 Hardware Configuration
7 Software Configuration
8 Steps to build Nfcrdlib_SimplifiedAPI_ISO for LPC1769 with PN5190 using MCUXpresso
9 Steps to build Nfcrdlib_SimplifiedAPI_ISO for LPC1769 with PN5180 using MCUXpresso
10 Steps to build Nfcrdlib_SimplifiedAPI_ISO for LPC1769 with RC663 using MCUXpresso
11 Steps to build Nfcrdlib_SimplifiedAPI_ISO for PN7462AU using MCUXpresso
12 Steps to build Nfcrdlib_SimplifiedAPI_ISO for FRDM-K82F using MCUXpresso
13 Selection of Board / OSAL / Frontend (MCUXpresso)
14 Steps to follow for PI / Linux / CMake
15 Running Nfcrdlib_SimplifiedAPI_ISO
16 List of supported NFC Reader Boards/ICs
17 Reference Documents
1 Document Purpose
==================
This document describes the steps to be followed to execute
Nfcrdlib_SimplifiedAPI_ISO example as well as it's known problems and
restrictions.
2 Description of the Nfcrdlib_SimplifiedAPI_ISO
===============================================
This example is a Reference Application to demonstrate the usage of
Simplified API with ISO profile. Application contains example of Type
A Layer 4, Type B Layer 4, Mifare UltraLight, Mifare Classic, ISO
15693 and ISO 18000p3m3.
3 Restrictions on Nfcrdlib_SimplifiedAPI_ISO
============================================
- Nfcrdlib_SimplifiedAPI_ISO is restricted to be run on NFC Reader
Boards/ICs mentioned in Section-16.
- The APIs are intended for NXP contact-less reader ICs only, as such
the APIs are not to be ported to any technology from any other
vendor.
- NXP will not support porting to any other vendor platform.
- This software project requires NxpNfcRdLib v07.10.00 or later.
- **IMPORTANT** The default used MCU Type is K82. When executing
example on LPC1769 or PN7462AU, the MCU Type has to be changed in
the MCUXpresso IDE.
- For switching to MCU Type to PN7462AU, see Section-11
- For switching to MCU Type to LPC1769, see Section-8, Section-9 and
Section-10.
4 Package Contents
==================
- Readme.txt
+ This readme file
- Nfcrdlib_SimplifiedAPI_ISO.c
+ Main example file.
- intfs/Nfcrdlib_SimplifiedAPI_ISO.h
+ Interfaces/Defines specific to the example
- intfs/ph_NxpBuild_App.h
+ Reader library build configuration file
- src/phApp_Helper.c
- src/phApp_PN5180_Init.c
- src/phApp_PN5190_Init.c
- src/phApp_PN7462AU_Init.c
- src/phApp_RC663_Init.c
- src/phApp_Init.c and intfs/phApp_Init.h
+ Common utility functions (common across all examples)
- src/Nfcrdlib_SimplifiedApi_ISO_15693.c
- src/Nfcrdlib_SimplifiedApi_ISO_18000.c
- src/Nfcrdlib_SimplifiedApi_ISO_Layer4TypeA.c
- src/Nfcrdlib_SimplifiedApi_ISO_MFC.c
- src/Nfcrdlib_SimplifiedApi_ISO_MFUL.c
- src/Nfcrdlib_SimplifiedApi_ISO_TypeB.c
+ Reference Functionality for the component of corresponding
protocol
- intfs/Nfcrdlib_SimplifiedApi_ISO.h
- intfs/Nfcrdlib_SimplifiedApi_ISO_15693.h
- intfs/Nfcrdlib_SimplifiedApi_ISO_18000.h
- intfs/Nfcrdlib_SimplifiedApi_ISO_MFC.h
- intfs/Nfcrdlib_SimplifiedApi_ISO_MFUL.h
+ Function Macros to create the command for the component of
corresponding protocol
- mcux/.cproject and mcux/.project
+ MCUXpresso project configuration file
- cr_startup_lpc175x_6x.c
+ Startup required to compile example for LPC1769 Micro Controller.
5 Mandatory materials (not included)
====================================
- MCUXpresso IDE. It can be downloaded from
[http://www.nxp.com/products/:MCUXpresso-IDE]
- SDK for Freedom K82 Board
([http://www.nxp.com/products/:FRDM-K82F]). The pre-build SDK can
be downloaded from
[https://mcuxpresso.nxp.com/en/license?hash=9897a8c19a6bc569c3fade7141f0f405&hash_download=true&to_vault=true]
See MCUXpresso User Manual for steps needed to install an SDK.
- Plugin to extend MCUXpresso to support PN7462AU. (Required for
MCUXpresso versions before MCUXpressoIDE_10.0.2)
- LPCXpresso LPC1769 / Freedom K82 development boards For NFC ICs
listed in Section-16 (Note: PN7462AU (Section-16 Bullet-3) does not
need any other other microcontroller).
6 Hardware Configuration
========================
Before starting this application, HW Changes may be required for the
used board. Refer to the following User Manuals / Application notes
before starting with this example.
- AN11211: Quick Start Up Guide RC663 Blueboard
- AN11744: PN5180 Evaluation board quick start guide
- AN11802: NFC Reader Library for Linux Installation Guidelines
- AN12550: PNEV5190B Evaluation board quick start guide
7 Software Configuration
========================
- The Software can be compiled for Cortex M3 LPC1769 micro-controller,
Cortex M4 Freedom K82 and Cortex M0 based PN7462AU from NXP.
- Since this example can be configured to run on various MCU ICs and
various NFC ICs, appropriate changes are required as mentioned in
Section-8, Section-9, Section-10, Section-11 and Section-12.
8 Steps to build Nfcrdlib_SimplifiedAPI_ISO for LPC1769 with PN5190 using MCUXpresso
====================================================================================
See "PNEV5190B Evaluation board quick start guide" in AN12550 (See
Section-17, Bullet-6 below)
9 Steps to build Nfcrdlib_SimplifiedAPI_ISO for LPC1769 with PN5180 using MCUXpresso
====================================================================================
See "Importing provided SW example projects" in AN11908 (See
Section-17, Bullet-2 below)
10 Steps to build Nfcrdlib_SimplifiedAPI_ISO for LPC1769 with RC663 using MCUXpresso
====================================================================================
See "Importing provided SW example projects" in AN11022 (See
Section-17, Bullet-3 below)
11 Steps to build Nfcrdlib_SimplifiedAPI_ISO for PN7462AU using MCUXpresso
==========================================================================
- For MCUXpresso versions before MCUXpressoIDE_10.0.2, See "Adding
PN7462AU Plugin" in UM10883. (See Section-17, Bullet-4 below)
- See "Importing provided SW example projects" in UM10883.
12 Steps to build Nfcrdlib_SimplifiedAPI_ISO for FRDM-K82F using MCUXpresso
===========================================================================
See "Import projects to the MCUXpresso" in AN11908. (See Section-17,
Bullet-2 below)
13 Selection of Board / OSAL / Frontend (MCUXpresso)
====================================================
For MCUXpresso, the selection of Board / OSAL / Frontend has to be
done via -D (Preprocessor defines).
1) To select the board go to "Project Properties" --> "C/C++ Build"
--> "Settings" --> "Preprocessor" --> "Defined symbols (-D)", and
define the relevant PHDRIVER_<BoardNFCCombination>_BOARD macro.
e.g. For using LPC1769 with Pn5180 use
PHDRIVER_LPC1769PN5180_BOARD. For list of supported boards refer
to Platform\DAL\cfg\BoardSelection.h.
2) To select the osal/os type, go to "Project Properties" --> "C/C++
Build" --> "Settings" --> "Preprocessor" --> "Defined symbols
(-D)".
e.g. For using FreeRTOS use PH_OSAL_FREERTOS. For other options
refer to RTOS\phOsal\inc\phOsal_Config.h.
14 Steps to follow for PI / Linux / CMake
=========================================
The steps are described in AN11802. (See Section-17, Bullet-5 below)
15 Running Nfcrdlib_SimplifiedAPI_ISO
=====================================
The running application can now be used for EMVCo Test case
validation.
16 List of supported NFC Reader Boards/ICs
==========================================
1) CLEV6630B v2.0 Customer Evaluation Board
2) PNEV5180B v2.0 Customer Evaluation Board
3) PN7462AU v2.1 Customer Evaluation Board
4) PNEV5190B v1.0 Customer Evaluation Board
17 Reference Documents
======================
1) UM10954 : PN5180 SW Quick start guide
[http://www.nxp.com/docs/en/user-guide/UM10954.pdf]
2) AN11908 : NFC Reader Library for FRDM-K82F Board Installation
guidelines
[http://www.nxp.com/docs/en/application-note/AN11908.pdf]
3) AN11022 : CLRC663 Evaluation board quick start guide
[http://www.nxp.com/docs/en/application-note/AN11022.pdf]
4) UM10883 : PN7462AU Quick Start Guide - Development Kit
[http://www.nxp.com/docs/en/user-guide/UM10883.pdf]
5) AN11802 : NFC Reader Library for Linux Installation Guidelines
[http://www.nxp.com/docs/en/application-note/AN11802.pdf]
6) AN12550 : PNEV5190B Evaluation board quick start guide
----------------------------------------------------------------------
For updates of this example, see
[http://www.nxp.com/products/:NFC-READER-LIBRARY]

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/*----------------------------------------------------------------------------*/
/* Copyright 2017-2021 NXP */
/* */
/* NXP Confidential. This software is owned or controlled by NXP and may only */
/* be used strictly in accordance with the applicable license terms. */
/* By expressly accepting such terms or by downloading, installing, */
/* activating and/or otherwise using the software, you are agreeing that you */
/* have read, and that you agree to comply with and are bound by, such */
/* license terms. If you do not agree to be bound by the applicable license */
/* terms, then you may not retain, install, activate or otherwise use the */
/* software. */
/*----------------------------------------------------------------------------*/
/** \file
* Example Source Header for Nfcrdlib_SimplifiedApi_ISO application.
*
* $Author: NXP $
* $Revision: $ (v07.10.00)
* $Date: $
*/
#ifndef INTFS_NFCRDLIB_SIMPLIFIEDAPI_ISO_H_
#define INTFS_NFCRDLIB_SIMPLIFIEDAPI_ISO_H_
#include <phApp_Init.h>
#include <Nfcrdlib_SimplifiedApi_ISO_15693.h>
#include <Nfcrdlib_SimplifiedApi_ISO_18000.h>
#include <Nfcrdlib_SimplifiedApi_ISO_MFUL.h>
#include <Nfcrdlib_SimplifiedApi_ISO_MFC.h>
uint32_t NfcLib_MifareClassic_1k_Reference_app(void);
uint32_t NfcLib_ISO18000p3m3_Reference_app(void);
uint32_t NfcLib_ISO15693_Reference_app(void);
uint32_t NfcLib_MifareDesfire_Reference_app(void);
uint32_t NfcLib_MifareUltralight_Reference_app(void);
uint32_t NfcLib_TypeB_Reference_app(void);
uint32_t NfcLib_Layer4TypeA_Reference_app(void);
#ifdef PH_OSAL_FREERTOS
#ifdef PHOSAL_FREERTOS_STATIC_MEM_ALLOCATION
#define SIMPLIFIED_ISO_STACK (2200/4)
#else /* PHOSAL_FREERTOS_STATIC_MEM_ALLOCATION */
#if defined( __PN74XXXX__) || defined(__PN76XX__)
#define SIMPLIFIED_ISO_STACK (2000/4)
#else /* defined( __PN74XXXX__) || defined(__PN76XX__) */
#define SIMPLIFIED_ISO_STACK (2050)
#endif /* defined( __PN74XXXX__) || defined(__PN76XX__) */
#endif /* PHOSAL_FREERTOS_STATIC_MEM_ALLOCATION*/
#define SIMPLIFIED_ISO_PRIO 4
#endif /* PH_OSAL_FREERTOS */
#ifdef PH_OSAL_LINUX
#define SIMPLIFIED_ISO_PRIO 0
#define SIMPLIFIED_ISO_STACK 0x20000
#endif /* PH_OSAL_LINUX*/
#endif /* INTFS_NFCRDLIB_SIMPLIFIEDAPI_ISO_H_ */

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/*
* Copyright 2017-2020, NXP
*
* All rights are reserved. Reproduction in whole or in part is
* prohibited without the written consent of the copyright owner.
* NXP reserves the right to make changes without notice at any time.
* NXP makes no warranty, expressed, implied or statutory, including but
* not limited to any implied warranty of merchantability or fitness for any
*particular purpose, or that the use will not infringe any third party patent,
* copyright or trademark. NXP must not be liable for any loss or damage
* arising from its use.
*/
/** \file
* Simplified API ISO15693.
*
* $Author$
* $Revision$ (v07.10.00)
* $Date$
*
*/
#ifndef EX11_SIMPLIFIEDAPI_15693_H
#define EX11_SIMPLIFIEDAPI_15693_H
/* Read Single Block takes the option and block num to read */
/* bOpt can be #PH_ON or #PH_OFF, bBlockNo can be 0x00 - 0xFF */
#define READ_SINGLEBLOCK(bOpt, bBlockNo) { \
phNfcLib_TransmitInput.phNfcLib_ISO15693.bOption = bOpt; \
phNfcLib_TransmitInput.phNfcLib_ISO15693.wBlockNumber = bBlockNo; \
phNfcLib_TransmitInput.phNfcLib_ISO15693.bCommand = ISO15693_ReadSingleBlock; \
}
/* Extended Read Single Block takes the option and block num to read the extended memory card*/
/* bOpt can be #PH_ON or #PH_OFF, wBlockNo can be 0x00 - 0xFFFF */
#define EXTENDEDREAD_SINGLEBLOCK(bOpt, wBlockNo) { \
phNfcLib_TransmitInput.phNfcLib_ISO15693.bOption = bOpt; \
phNfcLib_TransmitInput.phNfcLib_ISO15693.wBlockNumber = wBlockNo; \
phNfcLib_TransmitInput.phNfcLib_ISO15693.bCommand = ISO15693_Extended_ReadSingleBlock; \
}
/* Read Multiple Block takes the option, block num and num of Blocks to Read*/
/* Option can be #PH_ON or #PH_OFF, block bBlockNo can be 0x00 - 0xFF, wNumBlock can be 0x01 - 0x100 */
#define READ_MULTIPLEBLOCK(bOpt, bBlockNo, wNumBlock) { \
phNfcLib_TransmitInput.phNfcLib_ISO15693.bOption = bOpt; \
phNfcLib_TransmitInput.phNfcLib_ISO15693.wBlockNumber = bBlockNo; \
phNfcLib_TransmitInput.phNfcLib_ISO15693.wNumBlocks = wNumBlock; \
phNfcLib_TransmitInput.phNfcLib_ISO15693.bCommand = ISO15693_ReadMultipleBlocks; \
}
/* Read Multiple Block takes the option, block num and num of Blocks to Read from the extended memory card */
/* Option can be #PH_ON or #PH_OFF, block bBlockNo can be 0x00 - 0xFFFF, wNumBlock can be 0x01 - 0xFFFF */
#define EXTENDEDREAD_MULTIPLEBLOCK(bOpt, wBlockNo, wNumBlock) { \
phNfcLib_TransmitInput.phNfcLib_ISO15693.bOption = bOpt; \
phNfcLib_TransmitInput.phNfcLib_ISO15693.wBlockNumber = wBlockNo; \
phNfcLib_TransmitInput.phNfcLib_ISO15693.wNumBlocks = wNumBlock; \
phNfcLib_TransmitInput.phNfcLib_ISO15693.bCommand = ISO15693_Extended_ReadMultipleBlocks; \
}
/* Get System Information takes no parameter and gets the system information */
#define GET_SYSTEMINFORMATION() { \
phNfcLib_TransmitInput.phNfcLib_ISO15693.bCommand = ISO15693_GetSystemInformation; \
}
/* Extended Get System Information takes no parameter and gets the system information for extended memory card */
#define EXTENDEDGET_SYSTEMINFORMATION() { \
phNfcLib_TransmitInput.phNfcLib_ISO15693.bCommand = ISO15693_ExtendedGetSystemInformation; \
}
/* Get Multiple Block Security status takes the Block no and num of blocks whose security status to be read */
/* bBlockNo can be 0x00 - 0xFF and wNumBlock can be 0x01 - 0x100 */
#define GET_MULTIPLEBLOCKSECURITYSTATUS(bBlockNo, wNumBlock) { \
phNfcLib_TransmitInput.phNfcLib_ISO15693.wBlockNumber = bBlockNo; \
phNfcLib_TransmitInput.phNfcLib_ISO15693.wNumBlocks = wNumBlock; \
phNfcLib_TransmitInput.phNfcLib_ISO15693.bCommand = ISO15693_GetMultipleBlockSecurityStatus; \
}
/* Extended Get Multiple Block Security status takes the Block no and num of blocks for extended memory whose security status to be read */
/* wBlockNo can be 0x00 - 0xFFFF and wNumBlock can be 0x01 - 0xFFFF */
#define EXTENDEDGET_MULTIPLEBLOCKSECURITYSTATUS(wBlockNo, wNumBlock) { \
phNfcLib_TransmitInput.phNfcLib_ISO15693.wBlockNumber = wBlockNo; \
phNfcLib_TransmitInput.phNfcLib_ISO15693.wNumBlocks = wNumBlock; \
phNfcLib_TransmitInput.phNfcLib_ISO15693.bCommand = ISO15693_Extended_GetMultipleBlockSecurityStatus; \
}
/* Write Single Block takes the option , block number and data to write */
/* bOpt can be #PH_ON or #PH_OFF, bBlockNo can be 0x00 - 0xFF, pData takes the pointer to the start of the data */
#define WRITE_SINGLEBLOCK(bOpt, bBlockNo, pData) { \
phNfcLib_TransmitInput.phNfcLib_ISO15693.bOption = bOpt; \
phNfcLib_TransmitInput.phNfcLib_ISO15693.wBlockNumber = bBlockNo; \
phNfcLib_TransmitInput.phNfcLib_ISO15693.bCommand = ISO15693_WriteSingleBlock; \
phNfcLib_TransmitInput.phNfcLib_ISO15693.pBuffer = pData; \
}
/* Extended Write Single Block takes the option , block number and data to write to a extended memory card */
/* bOpt can be #PH_ON or #PH_OFF, wBlockNo can be 0x00 - 0xFFFF, pData takes the pointer to the start of the data */
#define EXTENDEDWRITE_SINGLEBLOCK(bOpt, wBlockNo, pData) { \
phNfcLib_TransmitInput.phNfcLib_ISO15693.bOption = bOpt; \
phNfcLib_TransmitInput.phNfcLib_ISO15693.wBlockNumber = wBlockNo; \
phNfcLib_TransmitInput.phNfcLib_ISO15693.bCommand = ISO15693_Extended_WriteSingleBlock; \
phNfcLib_TransmitInput.phNfcLib_ISO15693.pBuffer = pData; \
}
/* Write Multiple Block takes the option , block number, number of blocks and data to write */
/* bOpt can be #PH_ON or #PH_OFF, bBlockNo can be 0x00 - 0xFF, wNumBlock can be 0x01 - 0x100, pData takes the pointer to the start of the data */
#define WRITE_MULTIPLEBLOCK(bOpt, bBlockNo, wNumBlock, pData) { \
phNfcLib_TransmitInput.phNfcLib_ISO15693.bOption = bOpt; \
phNfcLib_TransmitInput.phNfcLib_ISO15693.wBlockNumber = bBlockNo; \
phNfcLib_TransmitInput.phNfcLib_ISO15693.wNumBlocks = wNumBlock; \
phNfcLib_TransmitInput.phNfcLib_ISO15693.bCommand = ISO15693_WriteMultipleBlocks; \
phNfcLib_TransmitInput.phNfcLib_ISO15693.pBuffer = pData; \
}
/* Extended Write Multiple Block takes the option , block number, number of blocks and data to write to a extended memory card */
/* bOpt can be #PH_ON or #PH_OFF, wBlockNo can be 0x00 - 0xFFFF, wNumBlock can be 0x01 - 0xFFFF, pData takes the pointer to the start of the data */
#define EXTENDEDWRITE_MULTIPLEBLOCK(bOpt, wBlockNo, wNumBlock, pData) { \
phNfcLib_TransmitInput.phNfcLib_ISO15693.bOption = bOpt; \
phNfcLib_TransmitInput.phNfcLib_ISO15693.wBlockNumber = wBlockNo; \
phNfcLib_TransmitInput.phNfcLib_ISO15693.wNumBlocks = wNumBlock; \
phNfcLib_TransmitInput.phNfcLib_ISO15693.bCommand = ISO15693_Extended_WriteMultipleBlocks; \
phNfcLib_TransmitInput.phNfcLib_ISO15693.pBuffer = pData; \
}
/* Lock Block takes the option and block number to Lock */
/* bOpt can be #PH_ON or #PH_OFF, bBlockNo can be 0x00 - 0xFF */
#define LOCK_BLOCK(bOpt, bBlockNo) { \
phNfcLib_TransmitInput.phNfcLib_ISO15693.bOption = bOpt; \
phNfcLib_TransmitInput.phNfcLib_ISO15693.wBlockNumber = bBlockNo; \
phNfcLib_TransmitInput.phNfcLib_ISO15693.bCommand = ISO15693_LockBlock; \
}
/* Extended Lock Block takes the option and block number of Extended Memory Card to Lock */
/* bOpt can be #PH_ON or #PH_OFF, wBlockNo can be 0x00 - 0xFFFF */
#define EXTENDEDLOCK_BLOCK(bOpt, wBlockNo) { \
phNfcLib_TransmitInput.phNfcLib_ISO15693.bOption = bOpt; \
phNfcLib_TransmitInput.phNfcLib_ISO15693.wBlockNumber = wBlockNo; \
phNfcLib_TransmitInput.phNfcLib_ISO15693.bCommand = ISO15693_Extended_LockBlock; \
}
/* Write AFI takes the option and AFI to write */
/* bOpt can be #PH_ON or #PH_OFF, bAFI can be any valid AFI value */
#define WRITE_AFI(bOpt, bAFI) { \
phNfcLib_TransmitInput.phNfcLib_ISO15693.bOption = bOpt; \
phNfcLib_TransmitInput.phNfcLib_ISO15693.bAfi = bAFI; \
phNfcLib_TransmitInput.phNfcLib_ISO15693.bCommand = ISO15693_WriteAFI; \
}
/* Lock AFI takes the option with which to lock the AFI */
/* bOpt can be #PH_ON or #PH_OFF */
#define LOCK_AFI(bOpt) { \
phNfcLib_TransmitInput.phNfcLib_ISO15693.bOption = bOpt; \
phNfcLib_TransmitInput.phNfcLib_ISO15693.bCommand = ISO15693_LockAFI; \
}
/* Write DSFID takes the option and DSFID to write */
/* bOpt can be #PH_ON or #PH_OFF and bDSFID can be any valid DSFID value */
#define WRITE_DSFID(bOpt, bDSFID) { \
phNfcLib_TransmitInput.phNfcLib_ISO15693.bOption = bOpt; \
phNfcLib_TransmitInput.phNfcLib_ISO15693.bDsfid = bDSFID; \
phNfcLib_TransmitInput.phNfcLib_ISO15693.bCommand = ISO15693_WriteDSFID; \
}
/* Lock DSFID takes the option with which to lock the DSFID */
/* bOpt can be #PH_ON or #PH_OFF */
#define LOCK_DSFID(bOpt) { \
phNfcLib_TransmitInput.phNfcLib_ISO15693.bOption = bOpt; \
phNfcLib_TransmitInput.phNfcLib_ISO15693.bCommand = ISO15693_LockDSFID; \
}
#endif /* EX11_SIMPLIFIEDAPI_15693_H */

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/*
* Copyright 2017-2020, NXP
*
* All rights are reserved. Reproduction in whole or in part is
* prohibited without the written consent of the copyright owner.
* NXP reserves the right to make changes without notice at any time.
* NXP makes no warranty, expressed, implied or statutory, including but
* not limited to any implied warranty of merchantability or fitness for any
*particular purpose, or that the use will not infringe any third party patent,
* copyright or trademark. NXP must not be liable for any loss or damage
* arising from its use.
*/
/** \file
* Simplified API ISO 18000.
*
* $Author$
* $Revision$ (v07.10.00)
* $Date$
*
*/
#ifndef EX11_SIMPLIFIEDAPI_ISO_18000_H
#define EX11_SIMPLIFIEDAPI_ISO_18000_H
/* ACK does not take any parameter and uses the handle present in context */
#define I18000_ACK() { \
phNfcLib_TransmitInput.phNfcLib_ISO18000.bCommand = ISO18000_Ack; \
}
/* REQRN takes the option with which to perform the REQRn Command */
/* bOpt can be only PHAL_I18000P3M3_REQRN_USE_HANDLE here */
#define I18000_REQRN(bOpt) { \
phNfcLib_TransmitInput.phNfcLib_ISO18000.bOption = bOpt; \
phNfcLib_TransmitInput.phNfcLib_ISO18000.bCommand = ISO18000_ReqRn; \
}
/* READ takes the Memory Bank to read, address of the word to read, length of the word ptr and No of words to read */
/* bMembank can be 0x00 - 0x03 , pWordptr is user choice limited to tag memory size */
/* bWordPtrLength can be 0x00 - 0x03 and depends on the TAG memory size , bWordcount is the number of words to read */
#define I18000_READ(bMembank, pWordptr, bWordPtrlength, bWordcount) { \
phNfcLib_TransmitInput.phNfcLib_ISO18000.bMemBank = bMembank; \
phNfcLib_TransmitInput.phNfcLib_ISO18000.pWordPtr = pWordptr; \
phNfcLib_TransmitInput.phNfcLib_ISO18000.bWordPtrLength = bWordPtrlength; \
phNfcLib_TransmitInput.phNfcLib_ISO18000.bWordCount = bWordcount; \
phNfcLib_TransmitInput.phNfcLib_ISO18000.bCommand = ISO18000_Read; \
}
/* WRITE takes the option, Memory Bank to write, address of the word to write, length of the word ptr and Data to write */
/* bOpt can be #PH_NFCLIB_18000P3M3_AC_NO_COVER_CODING or #PH_NFCLIB_18000P3M3_AC_USE_COVER_CODING, bMembank can be 0x00 - 0x03 */
/* pWordptr is user choice limited to tag memory size, bWordPtrLength can be 0x00 - 0x03 and depends on the TAG memory size */
/* pData is a 2 byte word to write */
#define I18000_WRITE(bOpt, bMembank, pWordptr, bWordPtrlength, pData) { \
phNfcLib_TransmitInput.phNfcLib_ISO18000.bOption = bOpt; \
phNfcLib_TransmitInput.phNfcLib_ISO18000.bMemBank = bMembank; \
phNfcLib_TransmitInput.phNfcLib_ISO18000.pWordPtr = pWordptr; \
phNfcLib_TransmitInput.phNfcLib_ISO18000.bWordPtrLength = bWordPtrlength; \
phNfcLib_TransmitInput.phNfcLib_ISO18000.pBuffer = pData; \
phNfcLib_TransmitInput.phNfcLib_ISO18000.bCommand = ISO18000_Write; \
}
/* KILL takes the option , the password for the kill and recommissioning option */
/* bOpt can be #PH_NFCLIB_18000P3M3_AC_NO_COVER_CODING or #PH_NFCLIB_18000P3M3_AC_USE_COVER_CODING, pPassWord is a 4 byte password */
/* bReCom can be any optional or mandatory support Recom option, value 0x04 is a mandatory support */
#define I18000_KILL(bOpt, pPassWord, bReCom) { \
phNfcLib_TransmitInput.phNfcLib_ISO18000.bOption = bOpt; \
phNfcLib_TransmitInput.phNfcLib_ISO18000.pPassword = pPassWord; \
phNfcLib_TransmitInput.phNfcLib_ISO18000.bRecom = bReCom; \
phNfcLib_TransmitInput.phNfcLib_ISO18000.bCommand = ISO18000_Kill; \
}
/* LOCK takes the Mask on which and the action with which to perform the Lock */
/* pLockMask and pLockAction both are a 10-bit field please refer ISO 18000-3M3 for detailed value */
#define I18000_LOCK(pLockMask, pLockAction) { \
phNfcLib_TransmitInput.phNfcLib_ISO18000.pMask = pLockMask; \
phNfcLib_TransmitInput.phNfcLib_ISO18000.pAction = pLockAction; \
phNfcLib_TransmitInput.phNfcLib_ISO18000.bCommand = ISO18000_Lock; \
}
/* ACCESS takes the option and password for the Access */
/* bOpt can be #PH_NFCLIB_18000P3M3_AC_NO_COVER_CODING or #PH_NFCLIB_18000P3M3_AC_USE_COVER_CODING, pPassWord is a 4 byte password */
#define I18000_ACCESS(bOpt, pPassWord) { \
phNfcLib_TransmitInput.phNfcLib_ISO18000.bOption = bOpt; \
phNfcLib_TransmitInput.phNfcLib_ISO18000.pPassword = pPassWord; \
phNfcLib_TransmitInput.phNfcLib_ISO18000.bCommand = ISO18000_Access; \
}
/* BLOCKWRITE takes the Memory Bank to write ,address of the word,length of the word ptr, No of words and Data to write */
/* bMembank can be 0x00 - 0x03, pWordptr is user choice limited to tag memory size, bWordPtrLen can be 0x00 - 0x03 and depends on the TAG memory size */
/* bWordcount is the no of words to write and is card support specific, pData takes the data to write */
#define I18000_BLOCKWRITE(bMembank, pWordptr, bWordPtrLen, bWordcount, pData) { \
phNfcLib_TransmitInput.phNfcLib_ISO18000.bMemBank = bMembank; \
phNfcLib_TransmitInput.phNfcLib_ISO18000.pWordPtr = pWordptr; \
phNfcLib_TransmitInput.phNfcLib_ISO18000.bWordPtrLength = bWordPtrLen; \
phNfcLib_TransmitInput.phNfcLib_ISO18000.bWordCount = bWordcount; \
phNfcLib_TransmitInput.phNfcLib_ISO18000.pBuffer = pData; \
phNfcLib_TransmitInput.phNfcLib_ISO18000.bCommand = ISO18000_BlockWrite; \
}
/* BLOCKERASE takes the Memory Bank to write ,address of the word,length of the word ptr and No of words to erase */
/* bMembank can be 0x00 - 0x03, pWordptr is user choice limited to tag memory size */
/* bWordPtrLen can be 0x00 - 0x03 and depends on the TAG memory size and No of words to erase is card support specific*/
#define I18000_BLOCKERASE(bMembank, pWordptr, bWordPtrLen, bWordcount) { \
phNfcLib_TransmitInput.phNfcLib_ISO18000.bMemBank = bMembank; \
phNfcLib_TransmitInput.phNfcLib_ISO18000.pWordPtr = pWordptr; \
phNfcLib_TransmitInput.phNfcLib_ISO18000.bWordPtrLength = bWordPtrLen; \
phNfcLib_TransmitInput.phNfcLib_ISO18000.bWordCount = bWordcount; \
phNfcLib_TransmitInput.phNfcLib_ISO18000.bCommand = ISO18000_BlockErase; \
}
/* BLOCKPERMALOCK takes the RFU, READ/LOCK choice, Memory Bank to PermaLock, starting address of the block and length of the block ptr, range of the block mask, and MemMask */
/* bRFU is to be kept 0, bReadlock can be 0/1, bMembank can be 0x00 - 0x03, pBlockptr is user choice limited to tag memory size */
/* bBlockPtrLen can be 0x00 - 0x03, bBlockrange depends on Tag Memory and pMemMask along with ReadLock depend upon 0/1 */
#define I18000_BLOCKPERMALOCK(bRfu, bReadlock, bMembank, pBlockptr, bBlockPtrLen, bBlockrange, pMemMask) { \
phNfcLib_TransmitInput.phNfcLib_ISO18000.bRFU = bRfu; \
phNfcLib_TransmitInput.phNfcLib_ISO18000.bReadLock = bReadlock; \
phNfcLib_TransmitInput.phNfcLib_ISO18000.bMemBank = bMembank; \
phNfcLib_TransmitInput.phNfcLib_ISO18000.pBlockPtr = pBlockptr; \
phNfcLib_TransmitInput.phNfcLib_ISO18000.bBlockPtrLength = bBlockPtrLen; \
phNfcLib_TransmitInput.phNfcLib_ISO18000.bBlockRange = bBlockrange; \
phNfcLib_TransmitInput.phNfcLib_ISO18000.pMask = pMemMask; \
phNfcLib_TransmitInput.phNfcLib_ISO18000.bCommand = ISO18000_BlockPermaLock; \
}
/* SETHANDLE takes the pointer to the handle */
/* pHandlePtr is a 2 byte Handle return by the REQRN command */
#define I18000_SETHANDLE(pHandlePtr) { \
phNfcLib_TransmitInput.phNfcLib_ISO18000.pHandle = pHandlePtr; \
phNfcLib_TransmitInput.phNfcLib_ISO18000.bCommand = ISO18000_SetHandle; \
}
#endif /* EX11_SIMPLIFIEDAPI_ISO_18000_H */

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/*
* Copyright 2017-2020, NXP
*
* All rights are reserved. Reproduction in whole or in part is
* prohibited without the written consent of the copyright owner.
* NXP reserves the right to make changes without notice at any time.
* NXP makes no warranty, expressed, implied or statutory, including but
* not limited to any implied warranty of merchantability or fitness for any
*particular purpose, or that the use will not infringe any third party patent,
* copyright or trademark. NXP must not be liable for any loss or damage
* arising from its use.
*/
/** \file
* Simplified API ISO MIFARE Classic contactless IC.
*
* $Author$
* $Revision$ (v07.10.00)
* $Date$
*
*/
#ifndef EX11_SIMPLIFIEDAPI_MFC_H
#define EX11_SIMPLIFIEDAPI_MFC_H
/* READ takes the block number to Read */
/* bBlockNo can take any value between 0x00-0xFF depending upon card size */
#define MFC_READ(bBlockNo) { \
phNfcLib_TransmitInput.phNfcLib_MifareClassic.bBlockNumber = bBlockNo; \
phNfcLib_TransmitInput.phNfcLib_MifareClassic.bCommand = Read; \
}
/* WRITE takes the block number and data to Write */
/* bBlockNo can take any value between 0x00-0xFF depending upon card size and the pBlockData is the pointer to 16 bytes data */
#define MFC_WRITE(bBlockNo, pBlockData) {\
phNfcLib_TransmitInput.phNfcLib_MifareClassic.bBlockNumber = bBlockNo; \
phNfcLib_TransmitInput.phNfcLib_MifareClassic.pBuffer = pBlockData; \
phNfcLib_TransmitInput.phNfcLib_MifareClassic.bCommand = Write; \
}
/* INCREMENT takes the block number of the value block and the value with which to increment the block */
/* bBlockNo can take any value between 0x00-0xFF depending upon card size and should be value block*/
/* pValue takes pointer to a 4 byte value data */
#define MFC_INCREMENT(bBlockNo, pValue) { \
phNfcLib_TransmitInput.phNfcLib_MifareClassic.bBlockNumber = bBlockNo; \
phNfcLib_TransmitInput.phNfcLib_MifareClassic.pBuffer = pValue; \
phNfcLib_TransmitInput.phNfcLib_MifareClassic.bCommand = Increment; \
}
/* DECREMENT takes the block number of the value block and the value with which to decrement the block */
/* bBlockNo can take any value between 0x00-0xFF depending upon card size and should be value block*/
/* pValue takes pointer to a 4 byte value data */
#define MFC_DECREMENT(bBlockNo, pValue) { \
phNfcLib_TransmitInput.phNfcLib_MifareClassic.bBlockNumber = bBlockNo; \
phNfcLib_TransmitInput.phNfcLib_MifareClassic.pBuffer = pValue; \
phNfcLib_TransmitInput.phNfcLib_MifareClassic.bCommand = Decrement; \
}
/* TRANSFER takes the block number of the value block where the transfer buffer should be transferred */
/* bBlockNo can take any value between 0x00-0xFF depending upon card size and should be value block*/
#define MFC_TRANSFER(bBlockNo) { \
phNfcLib_TransmitInput.phNfcLib_MifareClassic.bBlockNumber = bBlockNo; \
phNfcLib_TransmitInput.phNfcLib_MifareClassic.bCommand = Transfer; \
}
/* RESTORE takes the block number of the value block the transfer buffer shall be restored from*/
/* bBlockNo can take any value between 0x00-0xFF depending upon card size and should be value block*/
#define MFC_RESTORE(bBlockNo) {\
phNfcLib_TransmitInput.phNfcLib_MifareClassic.bBlockNumber = bBlockNo; \
phNfcLib_TransmitInput.phNfcLib_MifareClassic.bCommand = Restore; \
}
/* AUTHENTICATE takes the block number, key type, key number and key version of the Key with which to authenticate */
/* bBlockNo can take any value between 0x00-0xFF constraint to card memory, bKeyType can be #PHAL_MFC_KEYA or #PHAL_MFC_KEYB */
/* bKeyNumber and wKeyVersion of the Keystore depends upon the size of keystore and size is 2 for current settings */
#define MFC_AUTHENTICATE(bBlockNo, bKeytype, bKeyNo, wKeyVersion) { \
phNfcLib_TransmitInput.phNfcLib_MifareClassic.bBlockNumber = bBlockNo; \
phNfcLib_TransmitInput.phNfcLib_MifareClassic.bKeyType = bKeytype; \
phNfcLib_TransmitInput.phNfcLib_MifareClassic.bKeyNumber = bKeyNo; \
phNfcLib_TransmitInput.phNfcLib_MifareClassic.bKeyVersion = wKeyVersion; \
phNfcLib_TransmitInput.phNfcLib_MifareClassic.bCommand = Authenticate; \
}
/* PERSONALIZEUID takes the UID type with which to personalize the presented card */
/* bUidType can be PHAL_MFC_UID_TYPE_UIDF0 or PHAL_MFC_UID_TYPE_UIDF1 or PHAL_MFC_UID_TYPE_UIDF2 or PHAL_MFC_UID_TYPE_UIDF3 */
#define MFC_PERSONALIZEUID(bUidType) { \
}
#endif /* EX11_SIMPLIFIEDAPI_MFC_H */

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