262 lines
9.6 KiB
Plaintext
262 lines
9.6 KiB
Plaintext
/*
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* Copyright (c) 2015, Freescale Semiconductor, Inc.
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* Copyright 2016-2017 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef _FSL_SDRAMC_H_
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#define _FSL_SDRAMC_H_
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#include "fsl_common.h"
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/*!
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* @addtogroup sdramc
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* @{
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*/
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/*! @name Driver version */
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/*@{*/
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/*! @brief SDRAMC driver version 2.1.0. */
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#define FSL_SDRAMC_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
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/*@}*/
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/*! @brief SDRAM controller auto-refresh timing. */
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typedef enum _sdramc_refresh_time
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{
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kSDRAMC_RefreshThreeClocks = 0x0U, /*!< The refresh timing with three bus clocks. */
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kSDRAMC_RefreshSixClocks, /*!< The refresh timing with six bus clocks. */
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kSDRAMC_RefreshNineClocks /*!< The refresh timing with nine bus clocks. */
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} sdramc_refresh_time_t;
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/*!
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* @brief Setting latency for SDRAM controller timing specifications.
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*
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* The latency setting affects the following SDRAM timing specifications:
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* - trcd: SRAS assertion to SCAS assertion \n
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* - tcasl: SCAS assertion to data out \n
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* - tras: ACTV command to Precharge command \n
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* - trp: Precharge command to ACTV command \n
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* - trwl, trdl: Last data input to Precharge command \n
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* - tep: Last data out to Precharge command \n
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* The details of the latency setting and timing specifications are shown in the following table list. \n
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* latency trcd: tcasl tras trp trwl,trdl tep \n
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* 0 1 bus clock 1 bus clock 2 bus clocks 1 bus clock 1 bus clock 1 bus clock \n
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* 1 2 bus clock 2 bus clock 4 bus clocks 2 bus clock 1 bus clock 1 bus clock \n
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* 2 3 bus clock 3 bus clock 6 bus clocks 3 bus clock 1 bus clock 1 bus clock \n
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* 3 3 bus clock 3 bus clock 6 bus clocks 3 bus clock 1 bus clock 1 bus clock \n
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*/
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typedef enum _sdramc_latency
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{
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kSDRAMC_LatencyZero = 0x0U, /*!< Latency 0. */
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kSDRAMC_LatencyOne, /*!< Latency 1. */
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kSDRAMC_LatencyTwo, /*!< Latency 2. */
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kSDRAMC_LatencyThree, /*!< Latency 3. */
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} sdramc_latency_t;
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/*! @brief SDRAM controller command bit location. */
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typedef enum _sdramc_command_bit_location
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{
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kSDRAMC_Commandbit17 = 0x0U, /*!< Command bit location is bit 17. */
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kSDRAMC_Commandbit18, /*!< Command bit location is bit 18. */
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kSDRAMC_Commandbit19, /*!< Command bit location is bit 19. */
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kSDRAMC_Commandbit20, /*!< Command bit location is bit 20. */
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kSDRAMC_Commandbit21, /*!< Command bit location is bit 21. */
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kSDRAMC_Commandbit22, /*!< Command bit location is bit 22. */
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kSDRAMC_Commandbit23, /*!< Command bit location is bit 23. */
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kSDRAMC_Commandbit24 /*!< Command bit location is bit 24. */
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} sdramc_command_bit_location_t;
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/*! @brief SDRAM controller command. */
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typedef enum _sdramc_command
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{
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kSDRAMC_ImrsCommand = 0x0U, /*!< Initiate MRS command. */
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kSDRAMC_PrechargeCommand, /*!< Initiate precharge command. */
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kSDRAMC_SelfrefreshEnterCommand, /*!< Enter self-refresh command. */
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kSDRAMC_SelfrefreshExitCommand, /*!< Exit self-refresh command. */
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kSDRAMC_AutoRefreshEnableCommand, /*!< Enable Auto refresh command. */
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kSDRAMC_AutoRefreshDisableCommand, /*!< Disable Auto refresh command. */
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} sdramc_command_t;
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/*! @brief SDRAM port size. */
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typedef enum _sdramc_port_size
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{
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kSDRAMC_PortSize32Bit = 0x0U, /*!< 32-Bit port size. */
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kSDRAMC_PortSize8Bit, /*!< 8-Bit port size. */
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kSDRAMC_PortSize16Bit /*!< 16-Bit port size. */
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} sdramc_port_size_t;
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/*! @brief SDRAM controller block selection. */
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typedef enum _sdramc_block_selection
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{
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kSDRAMC_Block0 = 0x0U, /*!< Select SDRAM block 0. */
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kSDRAMC_Block1, /*!< Select SDRAM block 1. */
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} sdramc_block_selection_t;
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/*! @brief SDRAM controller block control configuration structure. */
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typedef struct _sdramc_blockctl_config
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{
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sdramc_block_selection_t block; /*!< The block number. */
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sdramc_port_size_t portSize; /*!< The port size of the associated SDRAM block. */
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sdramc_command_bit_location_t location; /*!< The command bit location. */
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sdramc_latency_t latency; /*!< The latency for some timing specifications. */
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uint32_t address; /*!< The base address of the SDRAM block. */
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uint32_t addressMask; /*!< The base address mask of the SDRAM block. */
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} sdramc_blockctl_config_t;
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/*! @brief SDRAM controller refresh timing configuration structure. */
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typedef struct _sdramc_refresh_config
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{
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sdramc_refresh_time_t refreshTime; /*!< Trc:The number of bus clocks inserted
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between a REF and next ACTIVE command. */
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uint32_t sdramRefreshRow; /*!< The SDRAM refresh time each row: ns/row. */
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uint32_t busClock_Hz; /*!< The bus clock for SDRAMC. */
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} sdramc_refresh_config_t;
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/*!
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* @brief SDRAM controller configuration structure.
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*
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* Defines a configure structure and uses the SDRAMC_Configure() function to make necessary
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* initializations.
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*/
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typedef struct _sdramc_config_t
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{
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sdramc_refresh_config_t *refreshConfig; /*!< Refresh timing configure structure pointer. */
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sdramc_blockctl_config_t *blockConfig; /*!< Block configure structure pointer. If both SDRAM
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blocks are used, use the two continuous blockConfig. */
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uint8_t numBlockConfig; /*!< SDRAM block numbers for configuration. */
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} sdramc_config_t;
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/*******************************************************************************
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* API
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******************************************************************************/
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#if defined(__cplusplus)
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extern "C" {
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#endif
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/*!
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* @name SDRAM Controller Initialization and De-initialization
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* @{
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*/
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/*!
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* @brief Initializes the SDRAM controller.
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* This function ungates the SDRAM controller clock and initializes the SDRAM controller.
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* This function must be called before calling any other SDRAM controller driver functions.
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* Example
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@code
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sdramc_refresh_config_t refreshConfig;
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sdramc_blockctl_config_t blockConfig;
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sdramc_config_t config;
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refreshConfig.refreshTime = kSDRAM_RefreshThreeClocks;
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refreshConfig.sdramRefreshRow = 15625;
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refreshConfig.busClock = 60000000;
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blockConfig.block = kSDRAMC_Block0;
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blockConfig.portSize = kSDRAMC_PortSize16Bit;
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blockConfig.location = kSDRAMC_Commandbit19;
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blockConfig.latency = kSDRAMC_RefreshThreeClocks;
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blockConfig.address = SDRAM_START_ADDRESS;
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blockConfig.addressMask = 0x7c0000;
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config.refreshConfig = &refreshConfig,
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config.blockConfig = &blockConfig,
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config.totalBlocks = 1;
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SDRAMC_Init(SDRAM, &config);
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@endcode
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*
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* @param base SDRAM controller peripheral base address.
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* @param configure The SDRAM configuration structure pointer.
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*/
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void SDRAMC_Init(SDRAM_Type *base, sdramc_config_t *configure);
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/*!
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* @brief Deinitializes the SDRAM controller module and gates the clock.
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* This function gates the SDRAM controller clock. As a result, the SDRAM
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* controller module doesn't work after calling this function.
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*
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* @param base SDRAM controller peripheral base address.
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*/
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void SDRAMC_Deinit(SDRAM_Type *base);
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/* @} */
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/*!
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* @name SDRAM Controller Basic Operation
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* @{
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*/
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/*!
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* @brief Sends the SDRAM command.
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* This function sends commands to SDRAM. The commands are precharge command, initialization MRS command,
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* auto-refresh enable/disable command, and self-refresh enter/exit commands.
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* Note that the self-refresh enter/exit commands are all blocks setting and "block"
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* is ignored. Ensure to set the correct "block" when send other commands.
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*
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* @param base SDRAM controller peripheral base address.
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* @param block The block selection.
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* @param command The SDRAM command, see "sdramc_command_t".
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* kSDRAMC_ImrsCommand - Initialize MRS command \n
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* kSDRAMC_PrechargeCommand - Initialize precharge command \n
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* kSDRAMC_SelfrefreshEnterCommand - Enter self-refresh command \n
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* kSDRAMC_SelfrefreshExitCommand - Exit self-refresh command \n
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* kSDRAMC_AutoRefreshEnableCommand - Enable auto refresh command \n
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* kSDRAMC_AutoRefreshDisableCommand - Disable auto refresh command
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*/
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void SDRAMC_SendCommand(SDRAM_Type *base, sdramc_block_selection_t block, sdramc_command_t command);
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/*!
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* @brief Enables/disables the write protection.
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*
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* @param base SDRAM peripheral base address.
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* @param block The block which is selected.
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* @param enable True enable write protection, false disable write protection.
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*/
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static inline void SDRAMC_EnableWriteProtect(SDRAM_Type *base, sdramc_block_selection_t block, bool enable)
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{
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if (enable)
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{
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base->BLOCK[block].CM |= SDRAM_CM_WP_MASK;
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}
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else
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{
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base->BLOCK[block].CM &= ~SDRAM_CM_WP_MASK;
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}
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}
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/*!
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* @brief Enables/disables the valid operation.
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*
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* @param base SDRAM peripheral base address.
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* @param block The block which is selected.
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* @param enable True enable the valid operation; false disable the valid operation.
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*/
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static inline void SDRAMC_EnableOperateValid(SDRAM_Type *base, sdramc_block_selection_t block, bool enable)
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{
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if (enable)
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{
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base->BLOCK[block].CM |= SDRAM_CM_V_MASK;
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}
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else
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{
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base->BLOCK[block].CM &= ~SDRAM_CM_V_MASK;
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}
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}
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/* @} */
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#if defined(__cplusplus)
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}
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#endif
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/*! @}*/
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#endif /* _FSL_SDRAMC_H_*/
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