439 lines
15 KiB
Plaintext
439 lines
15 KiB
Plaintext
/*----------------------------------------------------------------------------*/
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/* Copyright 2016-2022 NXP */
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/* */
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/* NXP Confidential. This software is owned or controlled by NXP and may only */
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/* be used strictly in accordance with the applicable license terms. */
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/* By expressly accepting such terms or by downloading, installing, */
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/* activating and/or otherwise using the software, you are agreeing that you */
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/* have read, and that you agree to comply with and are bound by, such */
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/* license terms. If you do not agree to be bound by the applicable license */
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/* terms, then you may not retain, install, activate or otherwise use the */
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/* software. */
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/*----------------------------------------------------------------------------*/
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/** \file
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* Example Source abstracting component data structure and code initialization and code specific to HW used in the examples
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* This file shall be present in all examples. A customer does not need to touch/modify this file. This file
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* purely depends on the phNxpBuild_Lpc.h or phNxpBuild_App.h
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* The phAppInit.h externs the component data structures initialized here that is in turn included by the core examples.
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* The core example shall not use any other variable defined here except the RdLib component data structures(as explained above)
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* The RdLib component initialization requires some user defined data and function pointers.
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* These are defined in the respective examples and externed here.
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*
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* Keystore and Crypto initialization needs to be handled by application.
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*
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* $Author: NXP$
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* $Revision: $ (v07.10.00)
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* $Date: $
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*
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*/
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/* Status header */
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#include <ph_Status.h>
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#include "phApp_Init.h"
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/* LLCP header */
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#include <phlnLlcp.h>
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#include <phOsal.h>
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#ifdef PH_PLATFORM_HAS_ICFRONTEND
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#include "BoardSelection.h"
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#endif /* PH_PLATFORM_HAS_ICFRONTEND */
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#ifdef PHDRIVER_KINETIS_K82
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#include <fsl_port.h>
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#include <fsl_pit.h>
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#ifdef DEBUG
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#include <fsl_clock.h>
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#endif /* DEBUG */
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#endif /* PHDRIVER_KINETIS_K82 */
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#ifdef PHDRIVER_KINETIS_K82
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#ifdef DEBUG
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#define KINETIS_K82_DEBUG_UART_CLK_FREQ CLOCK_GetOsc0ErClkFreq()
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#define KINETIS_K82_DEBUG_UART_BASEADDR (uint32_t)(LPUART4)
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#define KINETIS_K82_DEBUG_UART_INSTANCE 4U
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#define KINETIS_K82_DEBUG_UART_BAUDRATE 115200
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#define KINETIS_K82_DEBUG_UART_TYPE DEBUG_CONSOLE_DEVICE_TYPE_LPUART
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#endif /* DEBUG */
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/*! @brief Clock configuration structure. */
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typedef struct _clock_config
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{
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mcg_config_t mcgConfig; /*!< MCG configuration. */
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sim_clock_config_t simConfig; /*!< SIM configuration. */
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osc_config_t oscConfig; /*!< OSC configuration. */
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uint32_t coreClock; /*!< core clock frequency. */
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} clock_config_t;
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#endif /* PHDRIVER_KINETIS_K82 */
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#ifdef PH_OSAL_LINUX
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# define PI_IRQ_POLLING_TASK_PRIO 0
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# define PI_IRQ_POLLING_TASK_STACK 0x20000
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phOsal_ThreadObj_t gphPiThreadObj;
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#endif /* PH_OSAL_LINUX */
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#if defined(PHDRIVER_LPC1769) && defined(__CC_ARM)
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uint32_t SystemCoreClock;
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#endif
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/*******************************************************************************
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** Function Declarations
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*******************************************************************************/
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#ifdef PHDRIVER_KINETIS_K82
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static void phApp_K82_Init(void);
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#endif /* PHDRIVER_KINETIS_K82 */
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#ifdef PH_OSAL_LINUX
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static void phExample_IrqPolling(void* param);
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#endif /* PH_OSAL_LINUX */
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phStatus_t phApp_Configure_IRQ();
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/*******************************************************************************
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** Clock configuration of K82 Platform
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*******************************************************************************/
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#ifdef PHDRIVER_KINETIS_K82
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/* Configuration for enter RUN mode. Core clock = 50MHz. */
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const clock_config_t g_defaultClockConfigRun = {
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.mcgConfig =
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{
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.mcgMode = kMCG_ModePEE, /* Work in PEE mode. */
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.irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enable. */
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.ircs = kMCG_IrcSlow, /* Select IRC32k. */
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.fcrdiv = 0U, /* FCRDIV is 0. */
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.frdiv = 4U,
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.drs = kMCG_DrsLow, /* Low frequency range. */
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.dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25%. */
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.oscsel = kMCG_OscselOsc, /* Select OSC. */
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.pll0Config =
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{
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.enableMode = 0U, .prdiv = 0x01U, .vdiv = 0x01U,
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},
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},
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.simConfig =
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{
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.pllFllSel = 1U, /* PLLFLLSEL select PLL. */
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.pllFllDiv = 0U, /* PLLFLLSEL clock divider divisor. */
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.pllFllFrac = 0U, /* PLLFLLSEL clock divider fraction. */
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.er32kSrc = 5U, /* ERCLK32K selection, use RTC. */
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.clkdiv1 = 0x01140000U, /* SIM_CLKDIV1. */
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},
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.oscConfig = {.freq = CPU_XTAL_CLK_HZ,
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.capLoad = 0,
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.workMode = kOSC_ModeOscLowPower,
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.oscerConfig =
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{
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.enableMode = kOSC_ErClkEnable,
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#if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER)
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.erclkDiv = 0U,
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#endif
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}},
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};
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#endif /* PHDRIVER_KINETIS_K82 */
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/*******************************************************************************
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** Global Variable Declaration
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*******************************************************************************/
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#ifdef NXPBUILD__PHLN_LLCP_SW
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phlnLlcp_Sw_DataParams_t slnLlcp; /* LLCP component */
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#endif /* NXPBUILD__PHLN_LLCP_SW */
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/* General information bytes to be sent with ATR Request */
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#if defined(NXPBUILD__PHPAL_I18092MPI_SW) || defined(NXPBUILD__PHPAL_I18092MT_SW)
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uint8_t aLLCPGeneralBytes[36] = { 0x46,0x66,0x6D,
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0x01,0x01,0x10, /*VERSION*/
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0x03,0x02,0x00,0x01, /*WKS*/
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0x04,0x01,0xF1 /*LTO*/
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};
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uint8_t bLLCPGBLength = 13;
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#endif
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/* ATR Response or ATS Response holder */
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#if defined(NXPBUILD__PHPAL_I14443P4A_SW) || \
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defined(NXPBUILD__PHPAL_I18092MPI_SW)
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uint8_t aResponseHolder[64];
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#endif
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/* prints if error is detected */
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#define CHECK_SUCCESS(x) \
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if ((x) != PH_ERR_SUCCESS) \
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{ \
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DEBUG_PRINTF("\nLine: %d Error - (0x%04X) has occurred : 0xCCEE CC-Component ID, EE-Error code. Refer-ph_Status.h\n ", __LINE__, (x)); \
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return (x); \
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}
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/*******************************************************************************
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** Function Definitions
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*******************************************************************************/
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#ifdef PHDRIVER_KINETIS_K82
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static void phApp_K82_Init(void)
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{
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#ifdef DEBUG
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uint32_t uartClkSrcFreq;
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#endif /* DEBUG */
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pit_config_t pitConfig; /* Structure of initialize PIT */
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CLOCK_SetSimSafeDivs();
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CLOCK_InitOsc0(&g_defaultClockConfigRun.oscConfig);
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CLOCK_SetXtal0Freq(CPU_XTAL_CLK_HZ);
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CLOCK_BootToPeeMode(g_defaultClockConfigRun.mcgConfig.oscsel, kMCG_PllClkSelPll0,
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&g_defaultClockConfigRun.mcgConfig.pll0Config);
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CLOCK_SetInternalRefClkConfig(g_defaultClockConfigRun.mcgConfig.irclkEnableMode,
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g_defaultClockConfigRun.mcgConfig.ircs, g_defaultClockConfigRun.mcgConfig.fcrdiv);
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CLOCK_SetSimConfig(&g_defaultClockConfigRun.simConfig);
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SystemCoreClockUpdate();
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/*
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* pitConfig.enableRunInDebug = false;
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*/
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PIT_GetDefaultConfig(&pitConfig);
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/* Init pit module */
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PIT_Init(PIT, &pitConfig);
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#ifdef DEBUG
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/* Initialize LPUART4 pins below used to Print */
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/* Ungate the port clock */
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CLOCK_EnableClock(kCLOCK_PortC);
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/* Affects PORTC_PCR14 register */
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PORT_SetPinMux(PORTC, 14U, kPORT_MuxAlt3);
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/* Affects PORTC_PCR15 register */
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PORT_SetPinMux(PORTC, 15U, kPORT_MuxAlt3);
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/* SIM_SOPT2[27:26]:
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* 00: Clock Disabled
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* 01: MCGFLLCLK, or MCGPLLCLK, or IRC48M
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* 10: OSCERCLK
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* 11: MCGIRCCLK
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*/
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CLOCK_SetLpuartClock(2);
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uartClkSrcFreq = KINETIS_K82_DEBUG_UART_CLK_FREQ;
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DbgConsole_Init(KINETIS_K82_DEBUG_UART_INSTANCE, KINETIS_K82_DEBUG_UART_BAUDRATE, KINETIS_K82_DEBUG_UART_TYPE, uartClkSrcFreq);
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#endif /* DEBUG */
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}
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#endif /* PHDRIVER_KINETIS_K82 */
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#ifdef PH_PLATFORM_HAS_ICFRONTEND
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/**
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* This function will initialize Host Controller interfaced with NXP Reader IC's.
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* Any initialization which is not generic across Platforms, should be done here.
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* Note: For NXP NFC Controllers HOST initialization is not required.
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*/
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void phApp_CPU_Init(void)
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{
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#if defined PHDRIVER_KINETIS_K82
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phApp_K82_Init();
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#elif defined(PHDRIVER_LPC1769) && defined(__CC_ARM)
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SystemCoreClock = (( unsigned long ) 96000000);
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#elif defined(PH_OSAL_LINUX) && defined(NXPBUILD__PHHAL_HW_PN5190)
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phStatus_t status;
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status = PiGpio_OpenIrq();
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if ((status & PH_ERR_MASK) != PH_ERR_SUCCESS)
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{
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DEBUG_PRINTF("\n PiGpio_OpenIrq failed \n");
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DEBUG_PRINTF("\n Couldn't open PN5190 Kernel IRQ Driver.\n Halting here!!FIX IT!!\n");
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while(1);
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}
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#else
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/* In case of LPC series, startup file takes care of initializing clock and ports.
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* No initialization is required in Linux environment. */
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#endif /* PHDRIVER_KINETIS_K82 */
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}
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#endif /* PH_PLATFORM_HAS_ICFRONTEND */
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/**
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* This function will initialize Reader LIbrary Component
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*/
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phStatus_t phApp_Comp_Init(void * pDiscLoopParams)
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{
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phStatus_t wStatus = PH_ERR_SUCCESS;
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#if defined(NXPBUILD__PHPAL_I18092MPI_SW) || defined(NXPBUILD__PHPAL_I18092MT_SW) || \
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defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_P2P_TAGS) || defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_P2P_ACTIVE) || \
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defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_I3P4_TAGS) || defined(NXPBUILD__PHAC_DISCLOOP_TYPEF_P2P_TAGS) || \
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defined(NXPBUILD__PHAC_DISCLOOP_TYPEF212_P2P_ACTIVE) || defined(NXPBUILD__PHAC_DISCLOOP_TYPEF424_P2P_ACTIVE)
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phacDiscLoop_Sw_DataParams_t * pDiscLoop = (phacDiscLoop_Sw_DataParams_t *)pDiscLoopParams;
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#endif
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/* Initialize the LLCP component */
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#ifdef NXPBUILD__PHLN_LLCP_SW
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slnLlcp.sLocalLMParams.wMiu = 0x00; /* 128 bytes only */
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slnLlcp.sLocalLMParams.wWks = 0x11; /* SNEP & LLCP */
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slnLlcp.sLocalLMParams.bLto = 100; /* Maximum LTO */
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slnLlcp.sLocalLMParams.bOpt = 0x02;
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slnLlcp.sLocalLMParams.bAvailableTlv = PHLN_LLCP_TLV_MIUX_MASK | PHLN_LLCP_TLV_WKS_MASK |
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PHLN_LLCP_TLV_LTO_MASK | PHLN_LLCP_TLV_OPT_MASK;
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wStatus = phlnLlcp_Sw_Init(
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&slnLlcp,
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sizeof(phlnLlcp_Sw_DataParams_t),
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aLLCPGeneralBytes,
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&bLLCPGBLength);
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#endif /* NXPBUILD__PHLN_LLCP_SW */
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#ifdef NXPBUILD__PHAC_DISCLOOP_SW
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#if defined(NXPBUILD__PHPAL_I18092MPI_SW) || defined(NXPBUILD__PHPAL_I18092MT_SW)
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/* Assign the GI for Type A */
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pDiscLoop->sTypeATargetInfo.sTypeA_P2P.pGi = (uint8_t *)aLLCPGeneralBytes;
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pDiscLoop->sTypeATargetInfo.sTypeA_P2P.bGiLength = bLLCPGBLength;
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/* Assign the GI for Type F */
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pDiscLoop->sTypeFTargetInfo.sTypeF_P2P.pGi = (uint8_t *)aLLCPGeneralBytes;
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pDiscLoop->sTypeFTargetInfo.sTypeF_P2P.bGiLength = bLLCPGBLength;
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#endif /* NXPBUILD__PHAC_DISCLOOP_SW */
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#if defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_P2P_TAGS) || defined(NXPBUILD__PHAC_DISCLOOP_TYPEA_P2P_ACTIVE)
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/* Assign ATR response for Type A */
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pDiscLoop->sTypeATargetInfo.sTypeA_P2P.pAtrRes = aResponseHolder;
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#endif
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#if defined(NXPBUILD__PHAC_DISCLOOP_TYPEF_P2P_TAGS) || defined(NXPBUILD__PHAC_DISCLOOP_TYPEF212_P2P_ACTIVE) || \
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defined(NXPBUILD__PHAC_DISCLOOP_TYPEF424_P2P_ACTIVE)
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/* Assign ATR response for Type F */
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pDiscLoop->sTypeFTargetInfo.sTypeF_P2P.pAtrRes = aResponseHolder;
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#endif
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#ifdef NXPBUILD__PHAC_DISCLOOP_TYPEA_I3P4_TAGS
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/* Assign ATS buffer for Type A */
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pDiscLoop->sTypeATargetInfo.sTypeA_I3P4.pAts = aResponseHolder;
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#endif /* NXPBUILD__PHAC_DISCLOOP_TYPEA_I3P4_TAGS */
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#endif /* NXPBUILD__PHAC_DISCLOOP_SW */
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return wStatus;
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}
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phStatus_t phApp_Configure_IRQ()
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{
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#ifdef PH_OSAL_LINUX
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phStatus_t wStatus;
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#endif /* PH_OSAL_LINUX */
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#ifdef PH_PLATFORM_HAS_ICFRONTEND
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#if !(defined(PH_OSAL_LINUX) && defined(NXPBUILD__PHHAL_HW_PN5190))
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phDriver_Pin_Config_t pinCfg;
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pinCfg.bOutputLogic = PH_DRIVER_SET_LOW;
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pinCfg.bPullSelect = PHDRIVER_PIN_IRQ_PULL_CFG;
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pinCfg.eInterruptConfig = PIN_IRQ_TRIGGER_TYPE;
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phDriver_PinConfig(PHDRIVER_PIN_IRQ, PH_DRIVER_PINFUNC_INTERRUPT, &pinCfg);
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#endif
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#ifdef PHDRIVER_LPC1769
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NVIC_SetPriority(EINT_IRQn, EINT_PRIORITY);
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/* Enable interrupt in the NVIC */
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NVIC_ClearPendingIRQ(EINT_IRQn);
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NVIC_EnableIRQ(EINT_IRQn);
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#endif /* PHDRIVER_LPC1769 */
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#ifdef PH_OSAL_LINUX
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gphPiThreadObj.pTaskName = (uint8_t *) "IrqPolling";
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gphPiThreadObj.pStackBuffer = NULL;
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gphPiThreadObj.priority = PI_IRQ_POLLING_TASK_PRIO;
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gphPiThreadObj.stackSizeInNum = PI_IRQ_POLLING_TASK_STACK;
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PH_CHECK_SUCCESS_FCT(wStatus, phOsal_ThreadCreate(&gphPiThreadObj.ThreadHandle, &gphPiThreadObj,
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&phExample_IrqPolling, NULL));
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#endif /* PH_OSAL_LINUX */
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#ifdef PHDRIVER_KINETIS_K82
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NVIC_SetPriority(EINT_IRQn, EINT_PRIORITY);
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NVIC_ClearPendingIRQ(EINT_IRQn);
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EnableIRQ(EINT_IRQn);
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#endif /* PHDRIVER_KINETIS_K82 */
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#endif /* #ifdef PH_PLATFORM_HAS_ICFRONTEND */
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return PH_ERR_SUCCESS;
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}
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#ifdef PH_OSAL_LINUX
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/*
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* \brief: The purpose of this Thread is to detect RF signal from an External Peer .
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*/
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static void phExample_IrqPolling(void* param)
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{
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uint8_t bgpioVal = 0;
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uint8_t bhighOrLow = 0;
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#if defined(NXPBUILD__PHHAL_HW_RC663) || defined(NXPBUILD__PHHAL_HW_PN5180)
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if(PIN_IRQ_TRIGGER_TYPE == PH_DRIVER_INTERRUPT_RISINGEDGE)
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{
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bhighOrLow = 1;
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}
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while(PiGpio_read(PHDRIVER_PIN_IRQ, &bgpioVal) != PH_ERR_SUCCESS)
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{
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PiGpio_unexport(PHDRIVER_PIN_IRQ);
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PiGpio_export(PHDRIVER_PIN_IRQ);
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PiGpio_set_direction(PHDRIVER_PIN_IRQ, false);
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if(PIN_IRQ_TRIGGER_TYPE == PH_DRIVER_INTERRUPT_RISINGEDGE)
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{
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PiGpio_set_edge(PHDRIVER_PIN_IRQ, true, false);
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}
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else
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{
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PiGpio_set_edge(PHDRIVER_PIN_IRQ, false, true);
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}
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}
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/* Initial status: If pin is already Active, post an event. */
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if(bgpioVal == bhighOrLow)
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{
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CLIF_IRQHandler();
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}
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#endif
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while(1)
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{
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/* Block forever for Raising Edge in PHDRIVER_PIN_IRQ. */
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#if defined(NXPBUILD__PHHAL_HW_RC663) || defined(NXPBUILD__PHHAL_HW_PN5180)
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if(PiGpio_poll(PHDRIVER_PIN_IRQ, bhighOrLow, -1) == PH_ERR_SUCCESS)
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#elif defined(NXPBUILD__PHHAL_HW_PN5190)
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if(PiGpio_Irq() == PH_ERR_SUCCESS)
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#endif
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{
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CLIF_IRQHandler();
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}
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else
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{
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PiGpio_unexport(PHDRIVER_PIN_IRQ);
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PiGpio_export(PHDRIVER_PIN_IRQ);
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PiGpio_set_direction(PHDRIVER_PIN_IRQ, false);
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if(PIN_IRQ_TRIGGER_TYPE == PH_DRIVER_INTERRUPT_RISINGEDGE)
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{
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PiGpio_set_edge(PHDRIVER_PIN_IRQ, true, false);
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}
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else
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{
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PiGpio_set_edge(PHDRIVER_PIN_IRQ, false, true);
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}
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}
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}
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}
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#endif /* PH_OSAL_LINUX */
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/******************************************************************************
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** End Of File
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******************************************************************************/
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