745 lines
27 KiB
Plaintext
745 lines
27 KiB
Plaintext
/*
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* Copyright (c) 2015, Freescale Semiconductor, Inc.
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* Copyright 2016-2017 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef _FSL_QSPI_H_
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#define _FSL_QSPI_H_
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#include "fsl_common.h"
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/*!
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* @addtogroup qspi_driver
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* @{
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*/
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/*! @name Driver version */
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/*@{*/
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/*! @brief QSPI driver version 2.2.0. */
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#define FSL_QSPI_DRIVER_VERSION (MAKE_VERSION(2, 2, 0))
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/*@}*/
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/*! @brief Macro functions for LUT table */
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#define QSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \
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(QuadSPI_LUT_INSTR0(cmd0) | QuadSPI_LUT_PAD0(pad0) | QuadSPI_LUT_OPRND0(op0) | QuadSPI_LUT_INSTR1(cmd1) | \
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QuadSPI_LUT_PAD1(pad1) | QuadSPI_LUT_OPRND1(op1))
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/*! @brief Macro for QSPI LUT command */
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#define QSPI_CMD (0x1U)
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#define QSPI_ADDR (0x2U)
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#define QSPI_DUMMY (0x3U)
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#define QSPI_MODE (0x4U)
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#define QSPI_MODE2 (0x5U)
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#define QSPI_MODE4 (0x6U)
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#define QSPI_READ (0x7U)
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#define QSPI_WRITE (0x8U)
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#define QSPI_JMP_ON_CS (0x9U)
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#define QSPI_ADDR_DDR (0xAU)
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#define QSPI_MODE_DDR (0xBU)
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#define QSPI_MODE2_DDR (0xCU)
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#define QSPI_MODE4_DDR (0xDU)
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#define QSPI_READ_DDR (0xEU)
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#define QSPI_WRITE_DDR (0xFU)
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#define QSPI_DATA_LEARN (0x10U)
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#define QSPI_CMD_DDR (0x11U)
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#define QSPI_CADDR (0x12U)
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#define QSPI_CADDR_DDR (0x13U)
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#define QSPI_STOP (0x0U)
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/*! @brief Macro for QSPI PAD */
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#define QSPI_PAD_1 (0x0U)
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#define QSPI_PAD_2 (0x1U)
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#define QSPI_PAD_4 (0x2U)
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#define QSPI_PAD_8 (0x3U)
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/*! @brief Status structure of QSPI.*/
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enum _status_t
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{
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kStatus_QSPI_Idle = MAKE_STATUS(kStatusGroup_QSPI, 0), /*!< QSPI is in idle state */
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kStatus_QSPI_Busy = MAKE_STATUS(kStatusGroup_QSPI, 1), /*!< QSPI is busy */
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kStatus_QSPI_Error = MAKE_STATUS(kStatusGroup_QSPI, 2), /*!< Error occurred during QSPI transfer */
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};
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/*! @brief QSPI read data area, from IP FIFO or AHB buffer.*/
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typedef enum _qspi_read_area
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{
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kQSPI_ReadAHB = 0x0U, /*!< QSPI read from AHB buffer. */
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kQSPI_ReadIP /*!< QSPI read from IP FIFO. */
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} qspi_read_area_t;
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/*! @brief QSPI command sequence type */
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typedef enum _qspi_command_seq
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{
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kQSPI_IPSeq = QuadSPI_SPTRCLR_IPPTRC_MASK, /*!< IP command sequence */
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kQSPI_BufferSeq = QuadSPI_SPTRCLR_BFPTRC_MASK, /*!< Buffer command sequence */
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kQSPI_AllSeq = QuadSPI_SPTRCLR_IPPTRC_MASK | QuadSPI_SPTRCLR_BFPTRC_MASK /* All command sequence */
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} qspi_command_seq_t;
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/*! @brief QSPI buffer type */
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typedef enum _qspi_fifo
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{
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kQSPI_TxFifo = QuadSPI_MCR_CLR_TXF_MASK, /*!< QSPI Tx FIFO */
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kQSPI_RxFifo = QuadSPI_MCR_CLR_RXF_MASK, /*!< QSPI Rx FIFO */
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kQSPI_AllFifo = QuadSPI_MCR_CLR_TXF_MASK | QuadSPI_MCR_CLR_RXF_MASK /*!< QSPI all FIFO, including Tx and Rx */
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} qspi_fifo_t;
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/*! @brief QSPI transfer endianess*/
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typedef enum _qspi_endianness
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{
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kQSPI_64BigEndian = 0x0U, /*!< 64 bits big endian */
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kQSPI_32LittleEndian, /*!< 32 bit little endian */
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kQSPI_32BigEndian, /*!< 32 bit big endian */
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kQSPI_64LittleEndian /*!< 64 bit little endian */
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} qspi_endianness_t;
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/*! @brief QSPI error flags */
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enum _qspi_error_flags
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{
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kQSPI_DataLearningFail = (int)QuadSPI_FR_DLPFF_MASK, /*!< Data learning pattern failure flag */
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kQSPI_TxBufferFill = QuadSPI_FR_TBFF_MASK, /*!< Tx buffer fill flag */
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kQSPI_TxBufferUnderrun = QuadSPI_FR_TBUF_MASK, /*!< Tx buffer underrun flag */
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kQSPI_IllegalInstruction = QuadSPI_FR_ILLINE_MASK, /*!< Illegal instruction error flag */
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kQSPI_RxBufferOverflow = QuadSPI_FR_RBOF_MASK, /*!< Rx buffer overflow flag */
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kQSPI_RxBufferDrain = QuadSPI_FR_RBDF_MASK, /*!< Rx buffer drain flag */
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kQSPI_AHBSequenceError = QuadSPI_FR_ABSEF_MASK, /*!< AHB sequence error flag */
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#if !defined(FSL_FEATURE_QSPI_HAS_NO_AITEF) || (!FSL_FEATURE_QSPI_HAS_NO_AITEF)
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kQSPI_AHBIllegalTransaction = QuadSPI_FR_AITEF_MASK, /*!< AHB illegal transaction error flag */
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#endif /* FSL_FEATURE_QSPI_HAS_NO_AITEF */
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#if !defined(FSL_FEATURE_QSPI_HAS_NO_AIBSEF) || (!FSL_FEATURE_QSPI_HAS_NO_AIBSEF)
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kQSPI_AHBIllegalBurstSize = QuadSPI_FR_AIBSEF_MASK, /*!< AHB illegal burst error flag */
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#endif /* FSL_FEATURE_QSPI_HAS_NO_AIBSEF */
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kQSPI_AHBBufferOverflow = QuadSPI_FR_ABOF_MASK, /*!< AHB buffer overflow flag */
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#if defined(FSL_FEATURE_QSPI_HAS_IP_COMMAND_USAGE_ERROR) && (FSL_FEATURE_QSPI_HAS_IP_COMMAND_USAGE_ERROR)
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kQSPI_IPCommandUsageError = QuadSPI_FR_IUEF_MASK, /*!< IP command usage error flag */
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#endif /* FSL_FEATURE_QSPI_HAS_IP_COMMAND_USAGE_ERROR */
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kQSPI_IPCommandTriggerDuringAHBAccess = QuadSPI_FR_IPAEF_MASK, /*!< IP command trigger during AHB access error */
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kQSPI_IPCommandTriggerDuringIPAccess = QuadSPI_FR_IPIEF_MASK, /*!< IP command trigger cannot be executed */
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kQSPI_IPCommandTriggerDuringAHBGrant = QuadSPI_FR_IPGEF_MASK, /*!< IP command trigger during AHB grant error */
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kQSPI_IPCommandTransactionFinished = QuadSPI_FR_TFF_MASK, /*!< IP command transaction finished flag */
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kQSPI_FlagAll = (int)0x8C83F8D1U /*!< All error flag */
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};
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/*! @brief QSPI state bit */
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enum _qspi_flags
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{
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kQSPI_DataLearningSamplePoint = (int)QuadSPI_SR_DLPSMP_MASK, /*!< Data learning sample point */
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kQSPI_TxBufferFull = QuadSPI_SR_TXFULL_MASK, /*!< Tx buffer full flag */
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#if !defined(FSL_FEATURE_QSPI_HAS_NO_TXDMA) || (!FSL_FEATURE_QSPI_HAS_NO_TXDMA)
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kQSPI_TxDMA = QuadSPI_SR_TXDMA_MASK, /*!< Tx DMA is requested or running */
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kQSPI_TxWatermark = QuadSPI_SR_TXWA_MASK, /*!< Tx buffer watermark available */
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#endif /* FSL_FEATURE_QSPI_HAS_NO_TXDMA */
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kQSPI_TxBufferEnoughData = QuadSPI_SR_TXEDA_MASK, /*!< Tx buffer enough data available */
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kQSPI_RxDMA = QuadSPI_SR_RXDMA_MASK, /*!< Rx DMA is requesting or running */
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kQSPI_RxBufferFull = QuadSPI_SR_RXFULL_MASK, /*!< Rx buffer full */
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kQSPI_RxWatermark = QuadSPI_SR_RXWE_MASK, /*!< Rx buffer watermark exceeded */
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kQSPI_AHB3BufferFull = QuadSPI_SR_AHB3FUL_MASK, /*!< AHB buffer 3 full*/
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kQSPI_AHB2BufferFull = QuadSPI_SR_AHB2FUL_MASK, /*!< AHB buffer 2 full */
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kQSPI_AHB1BufferFull = QuadSPI_SR_AHB1FUL_MASK, /*!< AHB buffer 1 full */
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kQSPI_AHB0BufferFull = QuadSPI_SR_AHB0FUL_MASK, /*!< AHB buffer 0 full */
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kQSPI_AHB3BufferNotEmpty = QuadSPI_SR_AHB3NE_MASK, /*!< AHB buffer 3 not empty */
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kQSPI_AHB2BufferNotEmpty = QuadSPI_SR_AHB2NE_MASK, /*!< AHB buffer 2 not empty */
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kQSPI_AHB1BufferNotEmpty = QuadSPI_SR_AHB1NE_MASK, /*!< AHB buffer 1 not empty */
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kQSPI_AHB0BufferNotEmpty = QuadSPI_SR_AHB0NE_MASK, /*!< AHB buffer 0 not empty */
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kQSPI_AHBTransactionPending = QuadSPI_SR_AHBTRN_MASK, /*!< AHB access transaction pending */
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kQSPI_AHBCommandPriorityGranted = QuadSPI_SR_AHBGNT_MASK, /*!< AHB command priority granted */
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kQSPI_AHBAccess = QuadSPI_SR_AHB_ACC_MASK, /*!< AHB access */
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kQSPI_IPAccess = QuadSPI_SR_IP_ACC_MASK, /*!< IP access */
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kQSPI_Busy = QuadSPI_SR_BUSY_MASK, /*!< Module busy */
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kQSPI_StateAll = (int)0xEF897FE7U /*!< All flags */
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};
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/*! @brief QSPI interrupt enable */
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enum _qspi_interrupt_enable
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{
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kQSPI_DataLearningFailInterruptEnable =
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(int)QuadSPI_RSER_DLPFIE_MASK, /*!< Data learning pattern failure interrupt enable */
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kQSPI_TxBufferFillInterruptEnable = QuadSPI_RSER_TBFIE_MASK, /*!< Tx buffer fill interrupt enable */
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kQSPI_TxBufferUnderrunInterruptEnable = QuadSPI_RSER_TBUIE_MASK, /*!< Tx buffer underrun interrupt enable */
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kQSPI_IllegalInstructionInterruptEnable =
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QuadSPI_RSER_ILLINIE_MASK, /*!< Illegal instruction error interrupt enable */
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kQSPI_RxBufferOverflowInterruptEnable = QuadSPI_RSER_RBOIE_MASK, /*!< Rx buffer overflow interrupt enable */
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kQSPI_RxBufferDrainInterruptEnable = QuadSPI_RSER_RBDIE_MASK, /*!< Rx buffer drain interrupt enable */
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kQSPI_AHBSequenceErrorInterruptEnable = QuadSPI_RSER_ABSEIE_MASK, /*!< AHB sequence error interrupt enable */
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#if !defined(FSL_FEATURE_QSPI_HAS_NO_AITEF) || (!FSL_FEATURE_QSPI_HAS_NO_AITEF)
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kQSPI_AHBIllegalTransactionInterruptEnable =
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QuadSPI_RSER_AITIE_MASK, /*!< AHB illegal transaction error interrupt enable */
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#endif /* FSL_FEATURE_QSPI_HAS_NO_AITEF */
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#if !defined(FSL_FEATURE_QSPI_HAS_NO_AIBSEF) || (!FSL_FEATURE_QSPI_HAS_NO_AIBSEF)
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kQSPI_AHBIllegalBurstSizeInterruptEnable =
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QuadSPI_RSER_AIBSIE_MASK, /*!< AHB illegal burst error interrupt enable */
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#endif /* FSL_FEATURE_QSPI_HAS_NO_AIBSEF */
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kQSPI_AHBBufferOverflowInterruptEnable = QuadSPI_RSER_ABOIE_MASK, /*!< AHB buffer overflow interrupt enable */
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#if defined(FSL_FEATURE_QSPI_HAS_IP_COMMAND_USAGE_ERROR) && (FSL_FEATURE_QSPI_HAS_IP_COMMAND_USAGE_ERROR)
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kQSPI_IPCommandUsageErrorInterruptEnable = QuadSPI_RSER_IUEIE_MASK, /*!< IP command usage error interrupt enable */
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#endif /* FSL_FEATURE_QSPI_HAS_IP_COMMAND_USAGE_ERROR */
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kQSPI_IPCommandTriggerDuringAHBAccessInterruptEnable =
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QuadSPI_RSER_IPAEIE_MASK, /*!< IP command trigger during AHB access error */
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kQSPI_IPCommandTriggerDuringIPAccessInterruptEnable =
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QuadSPI_RSER_IPIEIE_MASK, /*!< IP command trigger cannot be executed */
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kQSPI_IPCommandTriggerDuringAHBGrantInterruptEnable =
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QuadSPI_RSER_IPGEIE_MASK, /*!< IP command trigger during AHB grant error */
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kQSPI_IPCommandTransactionFinishedInterruptEnable =
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QuadSPI_RSER_TFIE_MASK, /*!< IP command transaction finished interrupt enable */
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kQSPI_AllInterruptEnable = (int)0x8C83F8D1U /*!< All error interrupt enable */
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};
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/*! @brief QSPI DMA request flag */
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enum _qspi_dma_enable
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{
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#if !defined(FSL_FEATURE_QSPI_HAS_NO_TXDMA) || (!FSL_FEATURE_QSPI_HAS_NO_TXDMA)
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kQSPI_TxBufferFillDMAEnable = QuadSPI_RSER_TBFDE_MASK, /*!< Tx buffer fill DMA */
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#endif /* FSL_FEATURE_QSPI_HAS_NO_TXDMA */
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kQSPI_RxBufferDrainDMAEnable = QuadSPI_RSER_RBDDE_MASK, /*!< Rx buffer drain DMA */
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#if !defined(FSL_FEATURE_QSPI_HAS_NO_TXDMA) || (!FSL_FEATURE_QSPI_HAS_NO_TXDMA)
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kQSPI_AllDDMAEnable = QuadSPI_RSER_TBFDE_MASK | QuadSPI_RSER_RBDDE_MASK /*!< All DMA source */
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#else
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kQSPI_AllDDMAEnable = QuadSPI_RSER_RBDDE_MASK /* All DMA source */
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#endif /* FSL_FEATURE_QSPI_HAS_NO_TXDMA */
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};
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/*! @brief Phrase shift number for DQS mode. */
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typedef enum _qspi_dqs_phrase_shift
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{
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kQSPI_DQSNoPhraseShift = 0x0U, /*!< No phase shift */
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kQSPI_DQSPhraseShift45Degree, /*!< Select 45 degree phase shift*/
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kQSPI_DQSPhraseShift90Degree, /*!< Select 90 degree phase shift */
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kQSPI_DQSPhraseShift135Degree /*!< Select 135 degree phase shift */
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} qspi_dqs_phrase_shift_t;
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/*! @brief Qspi read sampling option. */
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typedef enum _qspi_dqs_read_sample_clock
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{
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kQSPI_ReadSampleClkInternalLoopback = 0x0U, /*!< Read sample clock adopts internal loopback mode. */
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kQSPI_ReadSampleClkLoopbackFromDqsPad = 0x1U, /*!< Dummy Read strobe generated by QSPI Controller
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and loopback from DQS pad. */
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kQSPI_ReadSampleClkExternalInputFromDqsPad = 0x2U, /*!< Flash provided Read strobe and input from DQS pad. */
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} qspi_dqs_read_sample_clock_t;
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/*! @brief DQS configure features*/
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typedef struct QspiDQSConfig
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{
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uint32_t portADelayTapNum; /*!< Delay chain tap number selection for QSPI port A DQS */
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#if defined(QuadSPI_SOCCR_DQS_IFB_DELAY_CHAIN_SEL_MASK)
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uint32_t portBDelayTapNum; /*!< Delay chain tap number selection for QSPI port B DQS*/
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#endif
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qspi_dqs_phrase_shift_t shift; /*!< Phase shift for internal DQS generation */
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qspi_dqs_read_sample_clock_t rxSampleClock; /*!< Read sample clock for Dqs. */
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bool enableDQSClkInverse; /*!< Enable inverse clock for internal DQS generation */
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} qspi_dqs_config_t;
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/*! @brief Flash timing configuration. */
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typedef struct QspiFlashTiming
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{
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uint32_t dataHoldTime; /*!< Serial flash data in hold time */
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uint32_t CSHoldTime; /*!< Serial flash CS hold time in terms of serial flash clock cycles */
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uint32_t CSSetupTime; /*!< Serial flash CS setup time in terms of serial flash clock cycles */
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} qspi_flash_timing_t;
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/*! @brief QSPI configuration structure*/
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typedef struct QspiConfig
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{
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uint32_t clockSource; /*!< Clock source for QSPI module */
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uint32_t baudRate; /*!< Serial flash clock baud rate */
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uint8_t txWatermark; /*!< QSPI transmit watermark value */
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uint8_t rxWatermark; /*!< QSPI receive watermark value. */
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uint32_t AHBbufferSize[FSL_FEATURE_QSPI_AHB_BUFFER_COUNT]; /*!< AHB buffer size. */
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uint8_t AHBbufferMaster[FSL_FEATURE_QSPI_AHB_BUFFER_COUNT]; /*!< AHB buffer master. */
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bool enableAHBbuffer3AllMaster; /*!< Is AHB buffer3 for all master.*/
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qspi_read_area_t area; /*!< Which area Rx data readout */
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bool enableQspi; /*!< Enable QSPI after initialization */
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} qspi_config_t;
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/*! @brief External flash configuration items*/
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typedef struct _qspi_flash_config
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{
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uint32_t flashA1Size; /*!< Flash A1 size */
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uint32_t flashA2Size; /*!< Flash A2 size */
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#if defined(FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE) && (FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE)
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uint32_t flashB1Size; /*!< Flash B1 size */
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uint32_t flashB2Size; /*!< Flash B2 size */
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#endif /* FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE */
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uint32_t lookuptable[FSL_FEATURE_QSPI_LUT_DEPTH]; /*!< Flash command in LUT */
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#if !defined(FSL_FEATURE_QSPI_HAS_NO_TDH) || (!FSL_FEATURE_QSPI_HAS_NO_TDH)
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uint32_t dataHoldTime; /*!< Data line hold time. */
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#endif /* FSL_FEATURE_QSPI_HAS_NO_TDH */
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uint32_t CSHoldTime; /*!< CS line hold time */
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uint32_t CSSetupTime; /*!< CS line setup time*/
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uint32_t cloumnspace; /*!< Column space size */
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uint32_t dataLearnValue; /*!< Data Learn value if enable data learn */
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qspi_endianness_t endian; /*!< Flash data endianess. */
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bool enableWordAddress; /*!< If enable word address.*/
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} qspi_flash_config_t;
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/*! @brief Transfer structure for QSPI */
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typedef struct _qspi_transfer
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{
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uint32_t *data; /*!< Pointer to data to transmit */
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size_t dataSize; /*!< Bytes to be transmit */
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} qspi_transfer_t;
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/*! @brief 16-bit access reg for IPCR register */
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typedef struct _ip_command_config
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{
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union
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{
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__IO uint32_t IPCR; /*!< IP Configuration Register */
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struct
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{
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__IO uint16_t IDATZ; /*!< 16-bit access for IDATZ field in IPCR register */
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__IO uint8_t RESERVED_0; /*!< 8-bit access for RESERVED_0 field in IPCR register */
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__IO uint8_t SEQID; /*!< 8-bit access for SEQID field in IPCR register */
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} BITFIELD;
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} IPCR_REG;
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} ip_command_config_t;
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/******************************************************************************
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* API
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*****************************************************************************/
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#if defined(__cplusplus)
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extern "C" {
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#endif
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/*!
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* @name Initialization and deinitialization
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* @{
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*/
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/*!
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* @brief Get the instance number for QSPI.
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*
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* @param base QSPI base pointer.
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*/
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uint32_t QSPI_GetInstance(QuadSPI_Type *base);
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/*!
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* @brief Initializes the QSPI module and internal state.
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*
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* This function enables the clock for QSPI and also configures the QSPI with the
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* input configure parameters. Users should call this function before any QSPI operations.
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*
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* @param base Pointer to QuadSPI Type.
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* @param config QSPI configure structure.
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* @param srcClock_Hz QSPI source clock frequency in Hz.
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*/
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void QSPI_Init(QuadSPI_Type *base, qspi_config_t *config, uint32_t srcClock_Hz);
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/*!
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* @brief Gets default settings for QSPI.
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*
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* @param config QSPI configuration structure.
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*/
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void QSPI_GetDefaultQspiConfig(qspi_config_t *config);
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/*!
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* @brief Deinitializes the QSPI module.
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*
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* Clears the QSPI state and QSPI module registers.
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* @param base Pointer to QuadSPI Type.
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*/
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void QSPI_Deinit(QuadSPI_Type *base);
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/*!
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* @brief Configures the serial flash parameter.
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*
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* This function configures the serial flash relevant parameters, such as the size, command, and so on.
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* The flash configuration value cannot have a default value. The user needs to configure it according to the
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* QSPI features.
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*
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* @param base Pointer to QuadSPI Type.
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* @param config Flash configuration parameters.
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*/
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void QSPI_SetFlashConfig(QuadSPI_Type *base, qspi_flash_config_t *config);
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#if (!defined(FSL_FEATURE_QSPI_HAS_NO_SOCCR_REG)) || !FSL_FEATURE_QSPI_HAS_NO_SOCCR_REG
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/*!
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* @brief Configures the serial flash DQS parameter.
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*
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* This function configures the serial flash DQS relevant parameters, such as the delay chain tap number, .
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* DQS shift phase, whether need to inverse and the rxc sample clock selection.
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*
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* @param base Pointer to QuadSPI Type.
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* @param config Dqs configuration parameters.
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|
*/
|
|
void QSPI_SetDqsConfig(QuadSPI_Type *base, qspi_dqs_config_t *config);
|
|
#endif
|
|
|
|
/*!
|
|
* @brief Software reset for the QSPI logic.
|
|
*
|
|
* This function sets the software reset flags for both AHB and buffer domain and
|
|
* resets both AHB buffer and also IP FIFOs.
|
|
*
|
|
* @param base Pointer to QuadSPI Type.
|
|
*/
|
|
void QSPI_SoftwareReset(QuadSPI_Type *base);
|
|
|
|
/*!
|
|
* @brief Enables or disables the QSPI module.
|
|
*
|
|
* @param base Pointer to QuadSPI Type.
|
|
* @param enable True means enable QSPI, false means disable.
|
|
*/
|
|
static inline void QSPI_Enable(QuadSPI_Type *base, bool enable)
|
|
{
|
|
if (enable)
|
|
{
|
|
base->MCR &= ~QuadSPI_MCR_MDIS_MASK;
|
|
}
|
|
else
|
|
{
|
|
base->MCR |= QuadSPI_MCR_MDIS_MASK;
|
|
}
|
|
}
|
|
|
|
/*! @} */
|
|
|
|
/*!
|
|
* @name Status
|
|
* @{
|
|
*/
|
|
|
|
/*!
|
|
* @brief Gets the state value of QSPI.
|
|
*
|
|
* @param base Pointer to QuadSPI Type.
|
|
* @return status flag, use status flag to AND #_qspi_flags could get the related status.
|
|
*/
|
|
static inline uint32_t QSPI_GetStatusFlags(QuadSPI_Type *base)
|
|
{
|
|
return base->SR;
|
|
}
|
|
|
|
/*!
|
|
* @brief Gets QSPI error status flags.
|
|
*
|
|
* @param base Pointer to QuadSPI Type.
|
|
* @return status flag, use status flag to AND #_qspi_error_flags could get the related status.
|
|
*/
|
|
static inline uint32_t QSPI_GetErrorStatusFlags(QuadSPI_Type *base)
|
|
{
|
|
return base->FR;
|
|
}
|
|
|
|
/*! @brief Clears the QSPI error flags.
|
|
*
|
|
* @param base Pointer to QuadSPI Type.
|
|
* @param mask Which kind of QSPI flags to be cleared, a combination of _qspi_error_flags.
|
|
*/
|
|
static inline void QSPI_ClearErrorFlag(QuadSPI_Type *base, uint32_t mask)
|
|
{
|
|
base->FR = mask;
|
|
}
|
|
|
|
/*! @} */
|
|
|
|
/*!
|
|
* @name Interrupts
|
|
* @{
|
|
*/
|
|
|
|
/*!
|
|
* @brief Enables the QSPI interrupts.
|
|
*
|
|
* @param base Pointer to QuadSPI Type.
|
|
* @param mask QSPI interrupt source.
|
|
*/
|
|
static inline void QSPI_EnableInterrupts(QuadSPI_Type *base, uint32_t mask)
|
|
{
|
|
base->RSER |= mask;
|
|
}
|
|
|
|
/*!
|
|
* @brief Disables the QSPI interrupts.
|
|
*
|
|
* @param base Pointer to QuadSPI Type.
|
|
* @param mask QSPI interrupt source.
|
|
*/
|
|
static inline void QSPI_DisableInterrupts(QuadSPI_Type *base, uint32_t mask)
|
|
{
|
|
base->RSER &= ~mask;
|
|
}
|
|
|
|
/*! @} */
|
|
|
|
/*!
|
|
* @name DMA Control
|
|
* @{
|
|
*/
|
|
|
|
/*!
|
|
* @brief Enables the QSPI DMA source.
|
|
*
|
|
* @param base Pointer to QuadSPI Type.
|
|
* @param mask QSPI DMA source.
|
|
* @param enable True means enable DMA, false means disable.
|
|
*/
|
|
static inline void QSPI_EnableDMA(QuadSPI_Type *base, uint32_t mask, bool enable)
|
|
{
|
|
if (enable)
|
|
{
|
|
base->RSER |= mask;
|
|
}
|
|
else
|
|
{
|
|
base->RSER &= ~mask;
|
|
}
|
|
}
|
|
|
|
/*!
|
|
* @brief Gets the Tx data register address. It is used for DMA operation.
|
|
*
|
|
* @param base Pointer to QuadSPI Type.
|
|
* @return QSPI Tx data register address.
|
|
*/
|
|
static inline uint32_t QSPI_GetTxDataRegisterAddress(QuadSPI_Type *base)
|
|
{
|
|
return (uint32_t)(&base->TBDR);
|
|
}
|
|
|
|
/*!
|
|
* @brief Gets the Rx data register address used for DMA operation.
|
|
*
|
|
* This function returns the Rx data register address or Rx buffer address
|
|
* according to the Rx read area settings.
|
|
*
|
|
* @param base Pointer to QuadSPI Type.
|
|
* @return QSPI Rx data register address.
|
|
*/
|
|
uint32_t QSPI_GetRxDataRegisterAddress(QuadSPI_Type *base);
|
|
|
|
/* @} */
|
|
|
|
/*!
|
|
* @name Bus Operations
|
|
* @{
|
|
*/
|
|
|
|
/*! @brief Sets the IP command address.
|
|
*
|
|
* @param base Pointer to QuadSPI Type.
|
|
* @param addr IP command address.
|
|
*/
|
|
static inline void QSPI_SetIPCommandAddress(QuadSPI_Type *base, uint32_t addr)
|
|
{
|
|
base->SFAR = addr;
|
|
}
|
|
|
|
/*! @brief Sets the IP command size.
|
|
*
|
|
* @param base Pointer to QuadSPI Type.
|
|
* @param size IP command size.
|
|
*/
|
|
static inline void QSPI_SetIPCommandSize(QuadSPI_Type *base, uint32_t size)
|
|
{
|
|
ip_command_config_t *ipCommand = (ip_command_config_t *)(&(base->IPCR));
|
|
ipCommand->IPCR_REG.BITFIELD.IDATZ = QuadSPI_IPCR_IDATSZ(size);
|
|
}
|
|
|
|
/*! @brief Executes IP commands located in LUT table.
|
|
*
|
|
* @param base Pointer to QuadSPI Type.
|
|
* @param index IP command located in which LUT table index.
|
|
*/
|
|
void QSPI_ExecuteIPCommand(QuadSPI_Type *base, uint32_t index);
|
|
|
|
/*! @brief Executes AHB commands located in LUT table.
|
|
*
|
|
* @param base Pointer to QuadSPI Type.
|
|
* @param index AHB command located in which LUT table index.
|
|
*/
|
|
void QSPI_ExecuteAHBCommand(QuadSPI_Type *base, uint32_t index);
|
|
|
|
#if defined(FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE) && (FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE)
|
|
/*! @brief Enables/disables the QSPI IP command parallel mode.
|
|
*
|
|
* @param base Pointer to QuadSPI Type.
|
|
* @param enable True means enable parallel mode, false means disable parallel mode.
|
|
*/
|
|
static inline void QSPI_EnableIPParallelMode(QuadSPI_Type *base, bool enable)
|
|
{
|
|
if (enable)
|
|
{
|
|
base->IPCR |= QuadSPI_IPCR_PAR_EN_MASK;
|
|
}
|
|
else
|
|
{
|
|
base->IPCR &= ~QuadSPI_IPCR_PAR_EN_MASK;
|
|
}
|
|
}
|
|
|
|
/*! @brief Enables/disables the QSPI AHB command parallel mode.
|
|
*
|
|
* @param base Pointer to QuadSPI Type.
|
|
* @param enable True means enable parallel mode, false means disable parallel mode.
|
|
*/
|
|
static inline void QSPI_EnableAHBParallelMode(QuadSPI_Type *base, bool enable)
|
|
{
|
|
if (enable)
|
|
{
|
|
base->BFGENCR |= QuadSPI_BFGENCR_PAR_EN_MASK;
|
|
}
|
|
else
|
|
{
|
|
base->BFGENCR &= ~QuadSPI_BFGENCR_PAR_EN_MASK;
|
|
}
|
|
}
|
|
#endif /* FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE */
|
|
|
|
/*! @brief Updates the LUT table.
|
|
*
|
|
* @param base Pointer to QuadSPI Type.
|
|
* @param index Which LUT index needs to be located. It should be an integer divided by 4.
|
|
* @param cmd Command sequence array.
|
|
*/
|
|
void QSPI_UpdateLUT(QuadSPI_Type *base, uint32_t index, uint32_t *cmd);
|
|
|
|
/*! @brief Clears the QSPI FIFO logic.
|
|
*
|
|
* @param base Pointer to QuadSPI Type.
|
|
* @param mask Which kind of QSPI FIFO to be cleared.
|
|
*/
|
|
static inline void QSPI_ClearFifo(QuadSPI_Type *base, uint32_t mask)
|
|
{
|
|
base->MCR |= mask;
|
|
}
|
|
|
|
/*!@ brief Clears the command sequence for the IP/buffer command.
|
|
*
|
|
* This function can reset the command sequence.
|
|
* @param base QSPI base address.
|
|
* @param seq Which command sequence need to reset, IP command, buffer command or both.
|
|
*/
|
|
static inline void QSPI_ClearCommandSequence(QuadSPI_Type *base, qspi_command_seq_t seq)
|
|
{
|
|
base->SPTRCLR = seq;
|
|
}
|
|
|
|
/*!
|
|
* @brief Enable or disable DDR mode.
|
|
*
|
|
* @param base QSPI base pointer
|
|
* @param eanble True means enable DDR mode, false means disable DDR mode.
|
|
*/
|
|
static inline void QSPI_EnableDDRMode(QuadSPI_Type *base, bool enable)
|
|
{
|
|
if (enable)
|
|
{
|
|
base->MCR |= QuadSPI_MCR_DDR_EN_MASK;
|
|
}
|
|
else
|
|
{
|
|
base->MCR &= ~QuadSPI_MCR_DDR_EN_MASK;
|
|
}
|
|
}
|
|
|
|
#if defined(FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) && (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC)
|
|
|
|
/*! @brief Clears the QSPI cache.
|
|
*
|
|
* @param base Pointer to QuadSPI Type.
|
|
*/
|
|
void QSPI_ClearCache(QuadSPI_Type *base);
|
|
#endif
|
|
|
|
/*!@ brief Set the RX buffer readout area.
|
|
*
|
|
* This function can set the RX buffer readout, from AHB bus or IP Bus.
|
|
* @param base QSPI base address.
|
|
* @param area QSPI Rx buffer readout area. AHB bus buffer or IP bus buffer.
|
|
*/
|
|
void QSPI_SetReadDataArea(QuadSPI_Type *base, qspi_read_area_t area);
|
|
|
|
/*!
|
|
* @brief Sends a buffer of data bytes using a blocking method.
|
|
* @note This function blocks via polling until all bytes have been sent.
|
|
* @param base QSPI base pointer
|
|
* @param buffer The data bytes to send
|
|
* @param size The number of data bytes to send
|
|
*/
|
|
void QSPI_WriteBlocking(QuadSPI_Type *base, uint32_t *buffer, size_t size);
|
|
|
|
/*!
|
|
* @brief Writes data into FIFO.
|
|
*
|
|
* @param base QSPI base pointer
|
|
* @param data The data bytes to send
|
|
*/
|
|
static inline void QSPI_WriteData(QuadSPI_Type *base, uint32_t data)
|
|
{
|
|
base->TBDR = data;
|
|
}
|
|
|
|
/*!
|
|
* @brief Receives a buffer of data bytes using a blocking method.
|
|
* @note This function blocks via polling until all bytes have been sent. Users shall notice that
|
|
* this receive size shall not bigger than 64 bytes. As this interface is used to read flash status registers.
|
|
* For flash contents read, please use AHB bus read, this is much more efficiency.
|
|
*
|
|
* @param base QSPI base pointer
|
|
* @param buffer The data bytes to send
|
|
* @param size The number of data bytes to receive
|
|
*/
|
|
void QSPI_ReadBlocking(QuadSPI_Type *base, uint32_t *buffer, size_t size);
|
|
|
|
/*!
|
|
* @brief Receives data from data FIFO.
|
|
*
|
|
* @param base QSPI base pointer
|
|
* @return The data in the FIFO.
|
|
*/
|
|
uint32_t QSPI_ReadData(QuadSPI_Type *base);
|
|
|
|
/*! @} */
|
|
|
|
/*!
|
|
* @name Transactional
|
|
* @{
|
|
*/
|
|
|
|
/*!
|
|
* @brief Writes data to the QSPI transmit buffer.
|
|
*
|
|
* This function writes a continuous data to the QSPI transmit FIFO. This function is a block function
|
|
* and can return only when finished. This function uses polling methods.
|
|
*
|
|
* @param base Pointer to QuadSPI Type.
|
|
* @param xfer QSPI transfer structure.
|
|
*/
|
|
static inline void QSPI_TransferSendBlocking(QuadSPI_Type *base, qspi_transfer_t *xfer)
|
|
{
|
|
QSPI_WriteBlocking(base, xfer->data, xfer->dataSize);
|
|
}
|
|
|
|
/*!
|
|
* @brief Reads data from the QSPI receive buffer in polling way.
|
|
*
|
|
* This function reads continuous data from the QSPI receive buffer/FIFO. This function is a blocking
|
|
* function and can return only when finished. This function uses polling methods. Users shall notice that
|
|
* this receive size shall not bigger than 64 bytes. As this interface is used to read flash status registers.
|
|
* For flash contents read, please use AHB bus read, this is much more efficiency.
|
|
*
|
|
* @param base Pointer to QuadSPI Type.
|
|
* @param xfer QSPI transfer structure.
|
|
*/
|
|
static inline void QSPI_TransferReceiveBlocking(QuadSPI_Type *base, qspi_transfer_t *xfer)
|
|
{
|
|
QSPI_ReadBlocking(base, xfer->data, xfer->dataSize);
|
|
}
|
|
|
|
/*! @} */
|
|
|
|
#if defined(__cplusplus)
|
|
}
|
|
#endif
|
|
|
|
/* @}*/
|
|
|
|
#endif /* _FSL_QSPI_H_*/
|