584 lines
21 KiB
Plaintext
584 lines
21 KiB
Plaintext
/*
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* @brief LPC17xx/40xx SD Card Interface driver
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*
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* @note
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* Copyright(C) NXP Semiconductors, 2014
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* All rights reserved.
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*
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* @par
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* LPC products. This software is supplied "AS IS" without any warranties of
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* any kind, and NXP Semiconductors and its licensor disclaim any and
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* all warranties, express or implied, including all implied warranties of
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* merchantability, fitness for a particular purpose and non-infringement of
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* intellectual property rights. NXP Semiconductors assumes no responsibility
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* or liability for the use of the software, conveys no license or rights under any
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* patent, copyright, mask work right, or any other intellectual property rights in
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* or to any products. NXP Semiconductors reserves the right to make changes
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* in the software without notification. NXP Semiconductors also makes no
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* representation or warranty that such application will be suitable for the
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* specified use without further testing or modification.
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*
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* @par
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors' and its
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* licensor's relevant copyrights in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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*/
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#ifndef __SDC_17XX_40XX_H_
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#define __SDC_17XX_40XX_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** @defgroup SDC_17XX_40XX CHIP: LPC17xx/40xx SD Card Interafce driver
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* @ingroup CHIP_17XX_40XX_Drivers
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* SD/MMC card Interface
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* @{
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*/
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#if defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX)
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/**
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* @brief SD/MMC card Interface (SDC) register block structure
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*/
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typedef struct {
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__IO uint32_t POWER; /*!< Power Control register */
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__IO uint32_t CLOCK; /*!< Clock control regsiter */
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__IO uint32_t ARGUMENT; /*!< Command argument register */
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__IO uint32_t COMMAND; /*!< Command register */
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__I uint32_t RESPCMD; /*!< Command response register */
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__I uint32_t RESPONSE[4]; /*!< Response registers */
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__IO uint32_t DATATIMER; /*!< Data timer register */
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__IO uint32_t DATALENGTH; /*!< Data length register */
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__IO uint32_t DATACTRL; /*!< Data control register */
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__I uint32_t DATACNT; /*!< Data count register */
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__I uint32_t STATUS; /*!< Status register */
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__O uint32_t CLEAR; /*!< Clear register */
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__IO uint32_t MASK0; /*!< Mask 0 register */
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uint32_t RESERVED0[2];
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__I uint32_t FIFOCNT; /*!< FIFO count register */
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uint32_t RESERVED1[13];
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__IO uint32_t FIFO[16]; /*!< FIFO registers */
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} LPC_SDC_T;
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/**
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* @brief SDC Power Control Register bit definitions
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*/
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/** SDC Power Control Register Bitmask */
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#define SDC_PWR_BITMASK ((uint32_t) 0xC3)
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/** SDC Power Control Bit Mask */
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#define SDC_PWR_CTRL_BITMASK (((uint32_t) 0x03) << 0)
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/** SDC Power Control */
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#define SDC_PWR_CTRL(n) (((uint32_t) (n & 0x03)) << 0)
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/** SD_CMD Output Control */
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#define SDC_PWR_OPENDRAIN (((uint32_t) 1) << 6)
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/** Rod Control */
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#define SDC_PWR_ROD (((uint32_t) 1) << 7)
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/**
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* @brief SDC Clock Control Register bit definitions
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*/
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/** SDC Clock Control Register Bitmask */
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#define SDC_CLOCK_BITMASK ((uint32_t) 0xFFF)
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/** SDC Clock Divider Bitmask */
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#define SDC_CLOCK_CLKDIV_BITMASK (((uint32_t) 0xFF ) << 0)
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/** Set SDC Clock Divide value */
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#define SDC_CLOCK_CLKDIV(n) (((uint32_t) (n & 0x0FF)) << 0)
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/**
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* @brief SDC Command Register bit definitions
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*/
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/** SDC Command Register Bitmask */
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#define SDC_COMMAND_BITMASK ((uint32_t) 0x7FF)
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/** SDC Command Index Bitmask */
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#define SDC_COMMAND_INDEX_BITMASK ((uint32_t) 0x3F)
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/** Set SDC Command Index */
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#define SDC_COMMAND_INDEX(n) ((uint32_t) n & 0x3F)
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/** No response is expected */
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#define SDC_COMMAND_NO_RSP (((uint32_t) 0 ) << 6)
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/** Short response is expected */
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#define SDC_COMMAND_SHORT_RSP (((uint32_t) 1 ) << 6)
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/** Long response is expected */
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#define SDC_COMMAND_LONG_RSP (((uint32_t) 3 ) << 6)
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/** Response bit mask */
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#define SDC_COMMAND_RSP_BITMASK (((uint32_t) 3 ) << 6)
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/** Mark that command timer is disabled and CPSM waits for interrupt request */
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#define SDC_COMMAND_INTERRUPT (((uint32_t) 1 ) << 8)
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/** Mark that CPSM waits for CmdPend before starting sending a command*/
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#define SDC_COMMAND_PENDING (((uint32_t) 1 ) << 9)
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/** Enable CPSM */
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#define SDC_COMMAND_ENABLE (((uint32_t) 1 ) << 10)
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/**
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* @brief SDC Command Response Register bit definitions
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*/
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/** SDC Command Response value */
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#define SDC_RESPCOMMAND_VAL(n) ((uint32_t) n & 0x3F)
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/**
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* @brief SDC Data Length Register bit definitions
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*/
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/** SDC Data Length set */
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#define SDC_DATALENGTH_LEN(n) ((uint32_t) n & 0xFFFF)
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/**
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* @brief SDC Data Control Register bit definitions
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*/
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/** SDC Data Control Register Bitmask */
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#define SDC_DATACTRL_BITMASK ((uint32_t) 0xFF)
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/** Enable Data Transfer */
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#define SDC_DATACTRL_ENABLE (((uint32_t) 1 ) << 0)
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/** Mark that Data is transfer from card to controller */
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#define SDC_DATACTRL_DIR_FROMCARD (((uint32_t) 1 ) << 1)
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/** Mark that Data is transfer from controller to card */
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#define SDC_DATACTRL_DIR_TOCARD ((uint32_t) 0)
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/** Mark that the transfer mode is Stream Data Transfer */
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#define SDC_DATACTRL_XFER_MODE_STREAM (((uint32_t) 1 ) << 2)
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/** Mark that the transfer mode is Block Data Transfer */
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#define SDC_DATACTRL_XFER_MODE_BLOCK ((uint32_t) 0)
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/** Enable DMA */
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#define SDC_DATACTRL_DMA_ENABLE (((uint32_t) 1 ) << 3)
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/** Set Data Block size */
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#define SDC_DATACTRL_BLOCKSIZE(n) (((uint32_t) (n & 0x0F) ) << 4)
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/** Get Data Block size value */
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#define SDC_DATACTRL_BLOCKSIZE_VAL(n) (((uint32_t) 1) << n)
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/**
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* @brief SDC Data Counter Register bit definitions
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*/
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#define SDC_DATACNT_VAL(n) ((uint32_t) n & 0xFFFF)
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/**
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* @brief SDC Status Register bit definitions
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*/
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/** Command Response received (CRC check failed) */
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#define SDC_STATUS_CMDCRCFAIL (((uint32_t) 1 ) << 0)
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/** Data block sent/received (CRC check failed). */
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#define SDC_STATUS_DATACRCFAIL (((uint32_t) 1 ) << 1)
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/** Command response timeout.. */
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#define SDC_STATUS_CMDTIMEOUT (((uint32_t) 1 ) << 2)
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/** Data timeout. */
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#define SDC_STATUS_DATATIMEOUT (((uint32_t) 1 ) << 3)
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/** Transmit FIFO underrun error. */
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#define SDC_STATUS_TXUNDERRUN (((uint32_t) 1 ) << 4)
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/** Receive FIFO overrun error. */
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#define SDC_STATUS_RXOVERRUN (((uint32_t) 1 ) << 5)
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/** Command response received (CRC check passed). */
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#define SDC_STATUS_CMDRESPEND (((uint32_t) 1 ) << 6)
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/** Command sent (no response required).*/
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#define SDC_STATUS_CMDSENT (((uint32_t) 1 ) << 7)
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/** Data end (data counter is zero).*/
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#define SDC_STATUS_DATAEND (((uint32_t) 1 ) << 8)
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/** Start bit not detected on all data signals in wide bus mode..*/
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#define SDC_STATUS_STARTBITERR (((uint32_t) 1 ) << 9)
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/** Data block sent/received (CRC check passed).*/
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#define SDC_STATUS_DATABLOCKEND (((uint32_t) 1 ) << 10)
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/** Command transfer in progress.*/
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#define SDC_STATUS_CMDACTIVE (((uint32_t) 1 ) << 11)
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/** Data transmit in progress.*/
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#define SDC_STATUS_TXACTIVE (((uint32_t) 1 ) << 12)
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/** Data receive in progress.*/
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#define SDC_STATUS_RXACTIVE (((uint32_t) 1 ) << 13)
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/** Transmit FIFO half empty.*/
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#define SDC_STATUS_TXFIFOHALFEMPTY (((uint32_t) 1 ) << 14)
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/** Receive FIFO half full.*/
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#define SDC_STATUS_RXFIFOHALFFULL (((uint32_t) 1 ) << 15)
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/** Transmit FIFO full.*/
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#define SDC_STATUS_TXFIFOFULL (((uint32_t) 1 ) << 16)
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/** Receive FIFO full.*/
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#define SDC_STATUS_RXFIFOFULL (((uint32_t) 1 ) << 17)
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/** Transmit FIFO empty.*/
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#define SDC_STATUS_TXFIFOEMPTY (((uint32_t) 1 ) << 18)
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/** Receive FIFO empty.*/
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#define SDC_STATUS_RXFIFOEMPTY (((uint32_t) 1 ) << 19)
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/** Data available in transmit FIFO.*/
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#define SDC_STATUS_TXDATAAVLBL (((uint32_t) 1 ) << 20)
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/** Data available in receive FIFO.*/
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#define SDC_STATUS_RXDATAAVLBL (((uint32_t) 1 ) << 21)
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/** Command Error Status */
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#define SDC_STATUS_CMDERR (SDC_STATUS_CMDCRCFAIL | SDC_STATUS_CMDTIMEOUT | SDC_STATUS_STARTBITERR)
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/** Data Error Status */
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#define SDC_STATUS_DATAERR (SDC_STATUS_DATACRCFAIL | SDC_STATUS_DATATIMEOUT | SDC_STATUS_TXUNDERRUN \
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| SDC_STATUS_RXOVERRUN | SDC_STATUS_STARTBITERR)
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/** FIFO Status*/
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#define SDC_STATUS_FIFO (SDC_STATUS_TXFIFOHALFEMPTY | SDC_STATUS_RXFIFOHALFFULL \
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| SDC_STATUS_TXFIFOFULL | SDC_STATUS_RXFIFOFULL \
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| SDC_STATUS_TXFIFOEMPTY | SDC_STATUS_RXFIFOEMPTY \
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| SDC_STATUS_DATABLOCKEND)
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/** Data Transfer Status*/
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#define SDC_STATUS_DATA (SDC_STATUS_DATAEND )
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/**
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* @brief SDC Clear Register bit definitions
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*/
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/** Clear all status flag*/
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#define SDC_CLEAR_ALL ((uint32_t) 0x7FF)
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/** Clears CmdCrcFail flag.*/
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#define SDC_CLEAR_CMDCRCFAIL (((uint32_t) 1 ) << 0)
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/** Clears DataCrcFail flag. */
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#define SDC_CLEAR_DATACRCFAIL (((uint32_t) 1 ) << 1)
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/** Clears CmdTimeOut flag. */
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#define SDC_CLEAR_CMDTIMEOUT (((uint32_t) 1 ) << 2)
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/** Clears DataTimeOut flag. */
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#define SDC_CLEAR_DATATIMEOUT (((uint32_t) 1 ) << 3)
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/** Clears TxUnderrun flag. */
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#define SDC_CLEAR_TXUNDERRUN (((uint32_t) 1 ) << 4)
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/**Clears RxOverrun flag. */
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#define SDC_CLEAR_RXOVERRUN (((uint32_t) 1 ) << 5)
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/** Clears CmdRespEnd flag. */
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#define SDC_CLEAR_CMDRESPEND (((uint32_t) 1 ) << 6)
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/** Clears CmdSent flag.*/
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#define SDC_CLEAR_CMDSENT (((uint32_t) 1 ) << 7)
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/**Clears DataEnd flag.*/
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#define SDC_CLEAR_DATAEND (((uint32_t) 1 ) << 8)
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/** Clears StartBitErr flag.*/
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#define SDC_CLEAR_STARTBITERR (((uint32_t) 1 ) << 9)
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/** Clears DataBlockEnd flag.*/
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#define SDC_CLEAR_DATABLOCKEND (((uint32_t) 1 ) << 10)
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/**
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* @brief SDC Interrupt Mask Register bit definitions
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*/
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/** Mask CmdCrcFail flag.*/
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#define SDC_MASK0_CMDCRCFAIL (((uint32_t) 1 ) << 0)
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/** Mask DataCrcFail flag. */
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#define SDC_MASK0_DATACRCFAIL (((uint32_t) 1 ) << 1)
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/** Mask CmdTimeOut flag. */
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#define SDC_MASK0_CMDTIMEOUT (((uint32_t) 1 ) << 2)
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/** Mask DataTimeOut flag. */
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#define SDC_MASK0_DATATIMEOUT (((uint32_t) 1 ) << 3)
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/** Mask TxUnderrun flag. */
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#define SDC_MASK0_TXUNDERRUN (((uint32_t) 1 ) << 4)
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/** Mask RxOverrun flag. */
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#define SDC_MASK0_RXOVERRUN (((uint32_t) 1 ) << 5)
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/** Mask CmdRespEnd flag. */
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#define SDC_MASK0_CMDRESPEND (((uint32_t) 1 ) << 6)
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/** Mask CmdSent flag.*/
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#define SDC_MASK0_CMDSENT (((uint32_t) 1 ) << 7)
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/** Mask DataEnd flag.*/
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#define SDC_MASK0_DATAEND (((uint32_t) 1 ) << 8)
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/** Mask StartBitErr flag.*/
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#define SDC_MASK0_STARTBITERR (((uint32_t) 1 ) << 9)
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/** Mask DataBlockEnd flag.*/
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#define SDC_MASK0_DATABLOCKEND (((uint32_t) 1 ) << 10)
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/** Mask CmdActive flag.*/
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#define SDC_MASK0_CMDACTIVE (((uint32_t) 1 ) << 11)
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/** Mask TxActive flag.*/
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#define SDC_MASK0_TXACTIVE (((uint32_t) 1 ) << 12)
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/** Mask RxActive flag.*/
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#define SDC_MASK0_RXACTIVE (((uint32_t) 1 ) << 13)
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/** Mask TxFifoHalfEmpty flag.*/
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#define SDC_MASK0_TXFIFOHALFEMPTY (((uint32_t) 1 ) << 14)
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/** Mask RxFifoHalfFull flag.*/
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#define SDC_MASK0_RXFIFOHALFFULL (((uint32_t) 1 ) << 15)
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/** Mask TxFifoFull flag.*/
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#define SDC_MASK0_TXFIFOFULL (((uint32_t) 1 ) << 16)
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/** Mask RxFifoFull flag.*/
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#define SDC_MASK0_RXFIFOFULL (((uint32_t) 1 ) << 17)
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/** Mask TxFifoEmpty flag.*/
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#define SDC_MASK0_TXFIFOEMPTY (((uint32_t) 1 ) << 18)
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/** Mask RxFifoEmpty flag.*/
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#define SDC_MASK0_RXFIFOEMPTY (((uint32_t) 1 ) << 19)
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/** Mask TxDataAvlbl flag.*/
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#define SDC_MASK0_TXDATAAVLBL (((uint32_t) 1 ) << 20)
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/** Mask RxDataAvlbl flag.*/
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#define SDC_MASK0_RXDATAAVLBL (((uint32_t) 1 ) << 21)
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/** CMD error interrupt mask */
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#define SDC_MASK0_CMDERR (SDC_MASK0_CMDCRCFAIL | SDC_MASK0_CMDTIMEOUT | SDC_MASK0_STARTBITERR)
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/** Data Transmit Error interrupt mask */
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#define SDC_MASK0_TXDATAERR (SDC_MASK0_DATACRCFAIL | SDC_MASK0_DATATIMEOUT | SDC_MASK0_TXUNDERRUN | \
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SDC_MASK0_STARTBITERR)
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/** Data Receive Error interrupt mask */
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#define SDC_MASK0_RXDATAERR (SDC_MASK0_DATACRCFAIL | SDC_MASK0_DATATIMEOUT | SDC_MASK0_RXOVERRUN | \
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SDC_MASK0_STARTBITERR)
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/** TX FIFO interrupt mask*/
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#define SDC_MASK0_TXFIFO (SDC_MASK0_TXFIFOHALFEMPTY | SDC_MASK0_DATABLOCKEND )
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/** RX FIFO interrupt mask*/
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#define SDC_MASK0_RXFIFO (SDC_MASK0_RXFIFOHALFFULL | SDC_MASK0_DATABLOCKEND )
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/** Data Transfer interrupt mask*/
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#define SDC_MASK0_DATA (SDC_MASK0_DATAEND | SDC_MASK0_DATABLOCKEND )
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/**
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* @brief SDC FIFO Counter Register bit definitions
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*/
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#define SDC_FIFOCNT_VAL(n) ((uint32_t) n & 0x7FFF)
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/* The number of bytes used to store card status*/
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#define SDC_CARDSTATUS_BYTENUM ((uint32_t) 4)
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/**
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* @brief SDC Card bus clock rate definitions
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*/
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/* Card bus clock in Card Identification Mode */
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#define SDC_IDENT_CLOCK_RATE (400000) /* 400KHz */
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/* Card bus clock in Data Transfer Mode */
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#define SDC_TRAN_CLOCK_RATE (20000000) /* 20MHz */
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/**
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* @brief SDC Power Control Options
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*/
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typedef enum SDC_PWR_CTRL {
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SDC_POWER_OFF = 0, /*!< Power-off */
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SDC_POWER_UP = 2, /*!< Power-up */
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SDC_POWER_ON = 3, /*!< Power-on */
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} SDC_PWR_CTRL_T;
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/**
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* @brief SDC Clock Control Options
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*/
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typedef enum SDC_CLOCK_CTRL {
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SDC_CLOCK_ENABLE = 8, /*!< Enable SD Card Bus Clock */
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SDC_CLOCK_POWER_SAVE = 9, /*!< Disable SD_CLK output when bus is idle */
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SDC_CLOCK_DIVIDER_BYPASS = 10, /*!< Enable bypass of clock divide logic */
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SDC_CLOCK_WIDEBUS_MODE = 11, /*!< Enable wide bus mode (SD_DAT[3:0] is used instead of SD_DAT[0]) */
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} SDC_CLOCK_CTRL_T;
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/**
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* @brief SDC Response type
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*/
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typedef enum SDC_RESPONSE {
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SDC_NO_RESPONSE = SDC_COMMAND_NO_RSP, /*!< No response */
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SDC_SHORT_RESPONSE = SDC_COMMAND_SHORT_RSP, /*!< Short response */
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SDC_LONG_RESPONSE = SDC_COMMAND_LONG_RSP, /*!< Long response */
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} SDC_RESPONSE_T;
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/**
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* @brief SDC Data Transfer Direction definitions
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*/
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typedef enum SDC_TRANSFER_DIR {
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SDC_TRANSFER_DIR_FROMCARD = SDC_DATACTRL_DIR_FROMCARD, /*!< Transfer from card */
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SDC_TRANSFER_DIR_TOCARD = SDC_DATACTRL_DIR_TOCARD, /*!< Transfer to card */
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} SDC_TRANSFER_DIR_T;
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/**
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* @brief SDC Data Transfer Mode definitions
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*/
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typedef enum SDC_TRANSFER_MODE {
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SDC_TRANSFER_MODE_STREAM = SDC_DATACTRL_XFER_MODE_STREAM, /*!< Stream transfer mode */
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SDC_TRANSFER_MODE_BLOCK = SDC_DATACTRL_XFER_MODE_BLOCK, /*!< Block transfer mode */
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} SDC_TRANSFER_MODE_T;
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/**
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* @brief SDC Data Block size definitions (in bytes)
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*/
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typedef enum SDC_BLOCK_SIZE {
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SDC_BLOCK_SIZE_1 = 0, /*!< Block size - 1 byte */
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SDC_BLOCK_SIZE_2, /*!< Block size - 2 bytes */
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SDC_BLOCK_SIZE_4, /*!< Block size - 4 bytes */
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SDC_BLOCK_SIZE_8, /*!< Block size - 8 bytes */
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SDC_BLOCK_SIZE_16, /*!< Block size - 16 bytes */
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SDC_BLOCK_SIZE_32, /*!< Block size - 32 bytes */
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SDC_BLOCK_SIZE_64, /*!< Block size - 64 bytes */
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SDC_BLOCK_SIZE_128, /*!< Block size - 128 bytes */
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SDC_BLOCK_SIZE_256, /*!< Block size - 256 bytes */
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SDC_BLOCK_SIZE_512, /*!< Block size - 512 bytes */
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SDC_BLOCK_SIZE_1024, /*!< Block size - 1024 bytes */
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SDC_BLOCK_SIZE_2048, /*!< Block size - 2048 bytes */
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} SDC_BLOCK_SIZE_T;
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/**
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* @brief SDC Return code definitions
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*/
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typedef enum CHIP_SDC_RET_CODE {
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SDC_RET_OK = 0,
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SDC_RET_CMD_FAILED = -1,
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SDC_RET_BAD_PARAMETERS = -2,
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SDC_RET_BUS_NOT_IDLE = -3,
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SDC_RET_TIMEOUT = -4,
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SDC_RET_ERR_STATE = -5,
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SDC_RET_NOT_READY = -6,
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SDC_RET_FAILED = -7,
|
|
} CHIP_SDC_RET_CODE_T;
|
|
|
|
/**
|
|
* @brief SDC Command Response structure
|
|
*/
|
|
typedef struct {
|
|
uint8_t CmdIndex; /*!< Command Index of the command response received */
|
|
uint32_t Data[SDC_CARDSTATUS_BYTENUM]; /* Card Status which can be stored in 1 or 4 bytes */
|
|
} SDC_RESP_T;
|
|
|
|
/**
|
|
* @brief SDC Data Transfer Setup structure
|
|
*/
|
|
typedef struct {
|
|
uint16_t BlockNum; /*!< The number of block which will be transfered */
|
|
SDC_BLOCK_SIZE_T BlockSize; /*!< Data Block Length */
|
|
SDC_TRANSFER_DIR_T Dir; /*!< Direction */
|
|
SDC_TRANSFER_MODE_T Mode; /*!< Mode */
|
|
bool DMAUsed; /*!< true: DMA used */
|
|
uint32_t Timeout; /*!< Data Transfer timeout periods (in Card Bus Clock)*/
|
|
} SDC_DATA_TRANSFER_T;
|
|
|
|
/**
|
|
* @brief Set the power state of SDC peripheral
|
|
* @param pSDC : Pointer to SDC register block
|
|
* @param pwrMode : Power mode
|
|
* @param flag : Output control flag
|
|
* @return Nothing
|
|
* @note When the external power supply is switched on, the software first enters the power-up
|
|
* state, and waits until the supply output is stable before moving to the power-on state.
|
|
* During the power-up state, SD_PWR is set HIGH. The card bus outlets are disabled
|
|
* during both states.
|
|
* flag is or-ed bit value of SDC_PWR_OPENDRAIN and SDC_PWR_ROD
|
|
*/
|
|
void Chip_SDC_PowerControl(LPC_SDC_T *pSDC, SDC_PWR_CTRL_T pwrMode, uint32_t flag);
|
|
|
|
/**
|
|
* @brief Set clock divider value for SDC peripheral
|
|
* @param pSDC : Pointer to SDC register block
|
|
* @param div : clock divider
|
|
* @return Nothing
|
|
* @note While the SD card interface is in identification mode, the SD_CLK frequency must be less
|
|
* than 400 kHz. The clock frequency can be changed to the maximum card bus frequency
|
|
* when relative card addresses are assigned to all cards.
|
|
* SD_CLK frequency = MCLK / [2x(ClkDiv+1)].
|
|
*/
|
|
void Chip_SDC_SetClockDiv(LPC_SDC_T *pSDC, uint8_t div);
|
|
|
|
/**
|
|
* @brief Set or Reset clock control of SDC peripheral
|
|
* @param pSDC : Pointer to SDC register block
|
|
* @param ctrlType : Clock Control type
|
|
* @param NewState : New State to set
|
|
* @return Nothing
|
|
*/
|
|
void Chip_SDC_ClockControl(LPC_SDC_T *pSDC, SDC_CLOCK_CTRL_T ctrlType,
|
|
FunctionalState NewState);
|
|
|
|
/**
|
|
* @brief Set the clock frequency for SDC peripheral
|
|
* @param pSDC : Pointer to SDC peripheral base address
|
|
* @param freq : Expected clock frequency
|
|
* @return None
|
|
*/
|
|
void Chip_SDC_SetClock(LPC_SDC_T *pSDC, uint32_t freq);
|
|
|
|
/**
|
|
* @brief Set SDC Command Information
|
|
* @param pSDC : Pointer to SDC register block
|
|
* @param Cmd : Command value
|
|
* @param Arg : Argument for the command
|
|
* @return Nothing
|
|
*/
|
|
void Chip_SDC_SetCommand(LPC_SDC_T *pSDC, uint32_t Cmd, uint32_t Arg);
|
|
|
|
/**
|
|
* @brief Reset SDC Command Information
|
|
* @param pSDC : Pointer to SDC register block
|
|
* @return Nothing
|
|
*/
|
|
void Chip_SDC_ResetCommand(LPC_SDC_T *pSDC);
|
|
|
|
/**
|
|
* @brief Get SDC Response
|
|
* @param pSDC : Pointer to SDC register block
|
|
* @param pResp : Pointer to buffer storing response data
|
|
* @return Nothing
|
|
*/
|
|
void Chip_SDC_GetResp(LPC_SDC_T *pSDC, SDC_RESP_T *pResp);
|
|
|
|
/**
|
|
* @brief Set SDC Data Timeout Period
|
|
* @param pSDC : Pointer to SDC register block
|
|
* @param timeout : Data timeout value in card bus clock periods
|
|
* @return Nothing
|
|
*/
|
|
STATIC INLINE void Chip_SDC_SetDataTimer(LPC_SDC_T *pSDC, uint32_t timeout)
|
|
{
|
|
pSDC->DATATIMER = timeout;
|
|
}
|
|
|
|
/**
|
|
* @brief Set SDC Data Transfer Information
|
|
* @param pSDC : Pointer to SDC register block
|
|
* @param pTransfer : Pointer to Data Transfer structure
|
|
* @return Nothing
|
|
*/
|
|
void Chip_SDC_SetDataTransfer(LPC_SDC_T *pSDC, SDC_DATA_TRANSFER_T *pTransfer);
|
|
|
|
/**
|
|
* @brief Write Data to FIFO
|
|
* @param pSDC : Pointer to SDC register block
|
|
* @param pSrc : Pointer to data buffer
|
|
* @param bFirstHalf : true (write to the first half of FIFO) false (write to the second half of FIFO)
|
|
* @return Nothing
|
|
*/
|
|
void Chip_SDC_WriteFIFO(LPC_SDC_T *pSDC, uint32_t *pSrc, bool bFirstHalf);
|
|
|
|
/**
|
|
* @brief Write Data to FIFO
|
|
* @param pSDC : Pointer to SDC register block
|
|
* @param pDst : The buffer hold the data read
|
|
* @param bFirstHalf : true (read the first half of FIFO) false (read the second half of FIFO)
|
|
* @return Nothing
|
|
*/
|
|
void Chip_SDC_ReadFIFO(LPC_SDC_T *pSDC, uint32_t *pDst, bool bFirstHalf);
|
|
|
|
/**
|
|
* @brief Get status of SDC Peripheral
|
|
* @param pSDC : Pointer to SDC register block
|
|
* @return Status (Or-ed bit value of SDC_STATUS_*)
|
|
*/
|
|
STATIC INLINE uint32_t Chip_SDC_GetStatus(LPC_SDC_T *pSDC)
|
|
{
|
|
return pSDC->STATUS;
|
|
}
|
|
|
|
/**
|
|
* @brief Clear status of SDC Peripheral
|
|
* @param pSDC : Pointer to SDC register block
|
|
* @param flag : Status flag(s) to be cleared (Or-ed bit value of SDC_CLEAR_*)
|
|
* @return None
|
|
*/
|
|
STATIC INLINE void Chip_SDC_ClearStatus(LPC_SDC_T *pSDC, uint32_t flag)
|
|
{
|
|
pSDC->CLEAR = flag;
|
|
}
|
|
|
|
/**
|
|
* @brief Set interrupt mask for SDC Peripheral
|
|
* @param pSDC : Pointer to SDC register block
|
|
* @param mask : Interrupt mask (Or-ed bit value of SDC_MASK0_*)
|
|
* @return None
|
|
*/
|
|
STATIC INLINE void Chip_SDC_SetIntMask(LPC_SDC_T *pSDC, uint32_t mask)
|
|
{
|
|
pSDC->MASK0 = mask;
|
|
}
|
|
|
|
/**
|
|
* @brief Initialize the SDC card controller
|
|
* @param pSDC : Pointer to SDC register block
|
|
* @return None
|
|
*/
|
|
void Chip_SDC_Init(LPC_SDC_T *pSDC);
|
|
|
|
/**
|
|
* @brief Deinitialise SDC peripheral
|
|
* @param pSDC : Pointer to SDC peripheral base address
|
|
* @return None
|
|
*/
|
|
void Chip_SDC_DeInit(LPC_SDC_T *pSDC);
|
|
|
|
#endif /* defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX) */
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* __SDC_17XX_40XX_H_ */
|