/*
 * Copyright (C) Cvitek Co., Ltd. 2019-2020. All rights reserved.
 *
 * File Name: cv182x-clock.h
 * Description:
 */

#ifndef __DT_BINDINGS_CLK_CV182X_H__
#define __DT_BINDINGS_CLK_CV182X_H__

#define CV182X_CLK_MPLL				0
#define CV182X_CLK_TPLL				1
#define CV182X_CLK_FPLL				2
#define CV182X_CLK_MIPIMPLL			3
#define CV182X_CLK_A0PLL			4
#define CV182X_CLK_DISPPLL			5
#define CV182X_CLK_CAM0PLL			6
#define CV182X_CLK_CAM1PLL			7
#define CV182X_CLK_XTAL_A53			8

#define CV182X_CLK_AHB_ROM			9
#define CV182X_CLK_DDR_AXI_REG			10
#define CV182X_CLK_RTC_25M			11
#define CV182X_CLK_TEMPSEN			12
#define CV182X_CLK_SARADC			13
#define CV182X_CLK_EFUSE			14
#define CV182X_CLK_APB_EFUSE			15
#define CV182X_CLK_XTAL_MISC			16
#define CV182X_CLK_AXI4_EMMC			17
#define CV182X_CLK_AXI4_SD0			18
#define CV182X_CLK_AXI4_SD1			19
#define CV182X_CLK_AXI4_ETH0			20
#define CV182X_CLK_AXI4_ETH1			21
#define CV182X_CLK_APB_GPIO			22
#define CV182X_CLK_APB_GPIO_INTR		23
#define CV182X_CLK_AHB_SF			24
#define CV182X_CLK_SDMA_AXI			25
#define CV182X_CLK_APB_I2C			26
#define CV182X_CLK_APB_WDT			27
#define CV182X_CLK_APB_SPI0			28
#define CV182X_CLK_APB_SPI1			29
#define CV182X_CLK_APB_SPI2			30
#define CV182X_CLK_APB_SPI3			31
#define CV182X_CLK_187P5M			32
#define CV182X_CLK_APB_UART0			33
#define CV182X_CLK_APB_UART1			34
#define CV182X_CLK_APB_UART2			35
#define CV182X_CLK_APB_UART3			36
#define CV182X_CLK_APB_UART4			37
#define CV182X_CLK_APB_I2S0			38
#define CV182X_CLK_APB_I2S1			39
#define CV182X_CLK_APB_I2S2			40
#define CV182X_CLK_APB_I2S3			41
#define CV182X_CLK_AXI4_USB			42
#define CV182X_CLK_APB_USB			43
#define CV182X_CLK_AXI4				44
#define CV182X_CLK_AXI6				45
#define CV182X_CLK_H264C			46
#define CV182X_CLK_H265C			47
#define CV182X_CLK_JPEG				48
#define CV182X_CLK_APB_JPEG			49
#define CV182X_CLK_APB_H264C			50
#define CV182X_CLK_APB_H265C			51
#define CV182X_CLK_CSI_MAC0_VIP			52
#define CV182X_CLK_CSI_MAC1_VIP			53
#define CV182X_CLK_ISP_TOP_VIP			54
#define CV182X_CLK_IMG_D_VIP			55
#define CV182X_CLK_IMG_V_VIP			56
#define CV182X_CLK_SC_TOP_VIP			57
#define CV182X_CLK_SC_D_VIP			58
#define CV182X_CLK_SC_V1_VIP			59
#define CV182X_CLK_SC_V2_VIP			60
#define CV182X_CLK_SC_V3_VIP			61
#define CV182X_CLK_LDC_VIP			62
#define CV182X_CLK_BT_VIP			63
#define CV182X_CLK_DISP_VIP			64
#define CV182X_CLK_DSI_MAC_VIP			65
#define CV182X_CLK_LVDS0_VIP			66
#define CV182X_CLK_LVDS1_VIP			67
#define CV182X_CLK_CSI0_RX_VIP			68
#define CV182X_CLK_CSI1_RX_VIP			69
#define CV182X_CLK_PAD_VI_VIP			70
#define CV182X_CLK_1M				71
#define CV182X_CLK_PM				72
#define CV182X_CLK_TIMER0			73
#define CV182X_CLK_TIMER1			74
#define CV182X_CLK_TIMER2			75
#define CV182X_CLK_TIMER3			76
#define CV182X_CLK_TIMER4			77
#define CV182X_CLK_TIMER5			78
#define CV182X_CLK_TIMER6			79
#define CV182X_CLK_TIMER7			80
#define CV182X_CLK_APB_I2C0			81
#define CV182X_CLK_APB_I2C1			82
#define CV182X_CLK_APB_I2C2			83
#define CV182X_CLK_APB_I2C3			84
#define CV182X_CLK_APB_I2C4			85
#define CV182X_CLK_WGN				86
#define CV182X_CLK_WGN0				87
#define CV182X_CLK_WGN1				88
#define CV182X_CLK_WGN2				89
#define CV182X_CLK_KEYSCAN			90
#define CV182X_CLK_AHB_SF1			91
#define CV182X_CLK_PAD_VI1_VIP			92
#define CV182X_CLK_CFG_REG_VIP			93
#define CV182X_CLK_CFG_REG_VC			94
#define CV182X_CLK_APB_AUDSRC			95
#define CV182X_CLK_PWM_SRC			96

#define CV182X_CLK_MUX_AXI6			97
#define CV182X_CLK_MUX_PWM_SRC			98

#define CV182X_CLK_DIV_0_A53			99
#define CV182X_CLK_DIV_1_A53			100
#define CV182X_CLK_DIV_0_CPU_AXI0		101
#define CV182X_CLK_DIV_1_CPU_AXI0		102
#define CV182X_CLK_DIV_0_TPU			103
#define CV182X_CLK_DIV_1_TPU			104
#define CV182X_CLK_DIV_0_TPU_FAB		105
#define CV182X_CLK_DIV_1_TPU_FAB		106
#define CV182X_CLK_DIV_0_EMMC			107
#define CV182X_CLK_DIV_1_EMMC			108
#define CV182X_CLK_DIV_0_SD0			109
#define CV182X_CLK_DIV_1_SD0			110
#define CV182X_CLK_DIV_0_SD1			111
#define CV182X_CLK_DIV_1_SD1			112
#define CV182X_CLK_DIV_AXI4			113
#define CV182X_CLK_DIV_0_AXI6			114
#define CV182X_CLK_DIV_1_AXI6			115
#define CV182X_CLK_DIV_0_AXI_VIP		116
#define CV182X_CLK_DIV_1_AXI_VIP		117
#define CV182X_CLK_DIV_0_SRC_VIP_SYS_0		118
#define CV182X_CLK_DIV_1_SRC_VIP_SYS_0		119
#define CV182X_CLK_DIV_0_SRC_VIP_SYS_1		120
#define CV182X_CLK_DIV_1_SRC_VIP_SYS_1		121
#define CV182X_CLK_DIV_0_AXI_VIDEO_CODEC	122
#define CV182X_CLK_DIV_1_AXI_VIDEO_CODEC	123
#define CV182X_CLK_DIV_0_VC_SRC0		124
#define CV182X_CLK_DIV_1_VC_SRC0		125
#define CV182X_CLK_DIV_1M			126
#define CV182X_CLK_DIV_0_VC_SRC1		127
#define CV182X_CLK_DIV_1_VC_SRC1		128
#define CV182X_CLK_DIV_0_SRC_VIP_SYS_2		129
#define CV182X_CLK_DIV_1_SRC_VIP_SYS_2		130
#define CV182X_CLK_DIV_0_PWM_SRC		131
#define CV182X_CLK_DIV_1_PWM_SRC		132
#define CV182X_CLK_DIV_187P5M			133

#define CV182X_CLK_A53				134
#define CV182X_CLK_CPU_AXI0			135
#define CV182X_CLK_TPU				136
#define CV182X_CLK_TPU_FAB			137
#define CV182X_CLK_DEBUG			138
#define CV182X_CLK_EMMC				139
#define CV182X_CLK_SD0				140
#define CV182X_CLK_SD1				141
#define CV182X_CLK_APB_PWM			142
#define CV182X_CLK_UART0			143
#define CV182X_CLK_UART1			144
#define CV182X_CLK_UART2			145
#define CV182X_CLK_UART3			146
#define CV182X_CLK_UART4			147
#define CV182X_CLK_AXI_VIP			148
#define CV182X_CLK_SRC_VIP_SYS_0		149
#define CV182X_CLK_SRC_VIP_SYS_1		150
#define CV182X_CLK_AXI_VIDEO_CODEC		151
#define CV182X_CLK_VC_SRC0			152
#define CV182X_CLK_VC_SRC1			153
#define CV182X_CLK_SRC_VIP_SYS_2		154
#define CV182X_CLK_CPU_GIC			155
#define CV182X_CLK_100K_EMMC			156
#define CV182X_CLK_100K_SD0			157
#define CV182X_CLK_100K_SD1			158
#define CV182X_CLK_SPI_NAND			159
#define CV182X_CLK_500M_ETH0			160
#define CV182X_CLK_500M_ETH1			161
#define CV182X_CLK_GPIO_DB			162
#define CV182X_CLK_SDMA_AUD0			163
#define CV182X_CLK_SDMA_AUD1			164
#define CV182X_CLK_SDMA_AUD2			165
#define CV182X_CLK_SDMA_AUD3			166
#define CV182X_CLK_125M_USB			167
#define CV182X_CLK_33K_USB			168
#define CV182X_CLK_12M_USB			169
#define CV182X_CLK_DSI_ESC			170
#define CV182X_CLK_DISP_SRC_VIP			171
#define CV182X_CLK_CAM0				172
#define CV182X_CLK_CAM1				173
#define CV182X_CLK_SPI				174
#define CV182X_CLK_I2C				175
#define CV182X_CLK_AUDSRC			176
#define CV182X_CLK_VC_SRC2			177

#define CV182x_CLK_AP_DEBUG			178
#define CV182x_CLK_SRC_RTC_SYS_0		179
#define CV182x_CLK_PAD_VI2_VIP			180
#define CV182X_CLK_CSI_BE_VIP			181

#define CV182X_CLK_MUX_AXI_VIDEO_CODEC		182

#endif /* __DT_BINDINGS_CLK_CV182X_H__ */