80d4596c1b
- 3fa71d3, [feat](saradc):Add pm api. - cfc34b, [fix](pwm):Change pwm setting don't need to disable pwm. Change-Id: If0f2ef94f163fd534ddcd8a07444081e7bc0fb5a
145 lines
3.9 KiB
C
145 lines
3.9 KiB
C
/*
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* Copyright (C) Cvitek Co., Ltd. 2019-2021. All rights reserved.
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*
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* File Name: jpeg_common.c
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* Description: jpeg chip common interface
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*/
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#include <linux/clk.h>
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#include <linux/cdev.h>
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/version.h>
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#include "cvi_jpeg.h"
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#include "jpeg_common.h"
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void jpu_clk_get(struct cvi_jpu_device *jdev)
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{
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struct device *dev = jdev->dev;
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jdev->clk_axi_video_codec = devm_clk_get(dev, "clk_axi_video_codec");
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if (IS_ERR(jdev->clk_axi_video_codec)) {
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dev_err(dev, "failed to get clk_axi_video_codec\n");
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}
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jdev->clk_jpeg = devm_clk_get(dev, "clk_jpeg");
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if (IS_ERR(jdev->clk_jpeg)) {
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dev_err(dev, "failed to get clk_jpeg\n");
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}
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jdev->clk_apb_jpeg = devm_clk_get(dev, "clk_apb_jpeg");
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if (IS_ERR(jdev->clk_apb_jpeg)) {
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dev_err(dev, "failed to get clk_apb_jpeg\n");
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}
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jdev->clk_vc_src0 = devm_clk_get(dev, "clk_vc_src0");
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if (IS_ERR(jdev->clk_vc_src0)) {
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dev_err(dev, "failed to get clk_vc_src0\n");
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}
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jdev->clk_vc_src1 = devm_clk_get(dev, "clk_vc_src1");
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if (IS_ERR(jdev->clk_vc_src1)) {
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dev_err(dev, "failed to get clk_vc_src1\n");
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}
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jdev->clk_vc_src2 = devm_clk_get(dev, "clk_vc_src2");
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if (IS_ERR(jdev->clk_vc_src2)) {
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dev_err(dev, "failed to get clk_vc_src2\n");
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}
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jdev->clk_cfg_reg_vc = devm_clk_get(dev, "clk_cfg_reg_vc");
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if (IS_ERR(jdev->clk_cfg_reg_vc)) {
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dev_err(dev, "failed to get clk_cfg_reg_vc\n");
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}
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}
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void jpu_clk_put(struct cvi_jpu_device *jdev)
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{
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struct device *dev = jdev->dev;
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devm_clk_put(dev, jdev->clk_jpeg);
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}
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#if 0
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void jpu_clk_enable(struct cvi_jpu_device *jdev)
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{
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JPU_DBG_CLK("enable\n");
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clk_prepare_enable(jdev->clk_jpeg);
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clk_prepare_enable(jdev->clk_apb_jpeg);
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clk_prepare_enable(jdev->clk_vc_src0);
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clk_prepare_enable(jdev->clk_vc_src1);
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clk_prepare_enable(jdev->clk_vc_src2);
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clk_prepare_enable(jdev->clk_cfg_reg_vc);
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}
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void jpu_clk_disable(struct cvi_jpu_device *jdev)
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{
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if (jpu_mask & JPU_MASK_DISABLE_CLK_GATING)
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return;
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clk_disable_unprepare(jdev->clk_jpeg);
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clk_disable_unprepare(jdev->clk_apb_jpeg);
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clk_disable_unprepare(jdev->clk_vc_src0);
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clk_disable_unprepare(jdev->clk_vc_src1);
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clk_disable_unprepare(jdev->clk_vc_src2);
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clk_disable_unprepare(jdev->clk_cfg_reg_vc);
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}
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void cv1835_config_pll(struct cvi_jpu_device *jdev)
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{
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unsigned int val;
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void __iomem *base_030001;
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void __iomem *base_030028;
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#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0))
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base_030001 = ioremap(0x03000100, 0x100);
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base_030028 = ioremap(0x03002800, 0x100);
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#else
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base_030001 = ioremap_nocache(0x03000100, 0x100);
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base_030028 = ioremap_nocache(0x03002800, 0x100);
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#endif
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// 0x03002840 = 0x3E //enable synthesizer clock enable
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writel(0x3E, base_030028 + 0x40);
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// 0x03002854 = 385505882 //set apll synthesizer 104.4480001 M
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writel(385505882, base_030028 + 0x54);
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//0x03002850 ^= 0x00000001 // bit 0 toggle
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val = readl(base_030028 + 0x50);
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writel((val ^ 0x1), base_030028 + 0x50);
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// 0x0300280C = 0x01108201 // set apll *8/2
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writel(0x01108201, base_030028 + 0x0C);
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// 0x03002800 &= ~0x00000010 //clear apll pd , apll = 417.792
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val = readl(base_030028 + 0x00);
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writel((val &= (~0x10)), base_030028 + 0x00);
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// 0x03002884 = 421827145 //set cam1 synthesizer 95.45454549 M
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writel(421827145, base_030028 + 0x84);
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// 0x03002880 ^= 0x00000001 // bit 0 toggle
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val = readl(base_030028 + 0x80);
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writel((val ^ 0x1), base_030028 + 0x80);
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// 0x03002818 = 0x00168000 // set cam1 *11/1
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writel(0x00168000, base_030028 + 0x18);
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// 0x03002800 &= ~0x00010000 //clear cam1pll pd , cam1pll = 1050
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val = readl(base_030028 + 0x00);
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writel((val &= (~0x00010000)), base_030028 + 0x00);
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// #=========measure apll
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// 0x03000140 = 0x00000000
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// 0x03000140 = 0x00000049
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// Read 0x03000140 >>8 = ~ 2085
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// #=========measure cam1pll
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// 0x03000140 = 0x00000000
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// 0x03000140 = 0x00000079
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// Read 0x03000140 >>8 = ~ 5250
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iounmap(base_030001);
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iounmap(base_030028);
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}
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#endif |