f676f1ece7
-688ac2, osdrv support arm32. -3e88be, fix sync_io bug. -2dbabd, Trim adc. -985943, request idr reset rcgop err. -5e72dd, Added vo sleep wake function. Change-Id: I6c926b29118f456c319935f9ec533831d12cbaa1
225 lines
7.3 KiB
C
225 lines
7.3 KiB
C
/*
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* Copyright (C) Cvitek Co., Ltd. 2019-2021. All rights reserved.
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*
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* File Name: cvi_vcodec.h
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* Description:
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*/
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#ifndef __CVI_VCODEC_H__
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#define __CVI_VCODEC_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <linux/fs.h>
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#include <linux/types.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/proc_fs.h>
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#include <linux/seq_file.h>
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#include <linux/uaccess.h>
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#include <generated/compile.h>
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#include <base_ctx.h>
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#include <linux/cvi_comm_venc.h>
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#include <linux/cvi_comm_vdec.h>
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#include <vc_ctx.h>
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#define USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
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#define VCODEC_GET_REG_BASE 0x8000
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#define VCODEC_GET_REG_BASE_CTRL 0x8000
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#define VCODEC_GET_REG_BASE_ADDR_REMAP 0x8001
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#define VCODEC_GET_REG_BASE_SBM 0x8002
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typedef struct vpudrv_buffer_t {
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__u32 size;
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__u64 phys_addr;
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__u64 base; /* kernel logical address in use kernel */
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__u8 *virt_addr; /* virtual user space address */
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#ifdef __arm__
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__u32 padding; /* padding for keeping same size of this structure */
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#endif
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} vpudrv_buffer_t;
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typedef struct vpu_bit_firmware_info_t {
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__u32 size; /* size of this structure*/
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__u32 core_idx;
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__u64 reg_base_offset;
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__u16 bit_code[512];
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} vpu_bit_firmware_info_t;
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typedef struct vpudrv_inst_info_t {
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unsigned int core_idx;
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unsigned int inst_idx;
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int inst_open_count; /* for output only*/
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} vpudrv_inst_info_t;
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typedef struct vpudrv_intr_info_t {
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unsigned int timeout;
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int intr_reason;
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int coreIdx;
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__u64 intr_tv_sec;
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__u64 intr_tv_nsec;
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} vpudrv_intr_info_t;
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struct vpu_pltfm_data {
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const struct vpu_ops *ops;
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unsigned int quirks;
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unsigned int version;
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};
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struct cvi_vpu_device {
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struct device *dev;
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dev_t cdev_id;
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struct cdev cdev;
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int s_vpu_major;
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struct class *vpu_class;
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struct clk *clk_axi_video_codec;
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struct clk *clk_h264c;
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struct clk *clk_apb_h264c;
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struct clk *clk_h265c;
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struct clk *clk_apb_h265c;
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struct clk *clk_vc_src0;
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struct clk *clk_vc_src1;
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struct clk *clk_vc_src2;
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struct clk *clk_cfg_reg_vc;
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struct cvi_vcodec_context *pvctx;
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const struct vpu_pltfm_data *pdata;
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};
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struct vpu_ops {
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void (*clk_get)(struct cvi_vpu_device *vdev);
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void (*clk_put)(struct cvi_vpu_device *vdev);
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void (*clk_enable)(struct cvi_vpu_device *vdev, int mask);
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void (*clk_disable)(struct cvi_vpu_device *vdev, int mask);
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unsigned long (*clk_get_rate)(struct cvi_vpu_device *vdev);
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void (*config_ddr)(struct cvi_vpu_device *vdev);
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};
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#define VCODEC_DBG_MSG_ENABLE
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#define VCODEC_MASK_ERR 0x1
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#define VCODEC_MASK_WARN 0x2
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#define VCODEC_MASK_INFO 0x4
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#define VCODEC_MASK_FLOW 0x8
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#define VCODEC_MASK_DBG 0x10
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#define VCODEC_MASK_INTR 0x20
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#define VCODEC_MASK_MCU 0x40
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#define VCODEC_MASK_MEM 0x80
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#define VCODEC_MASK_BS 0x100
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#define VCODEC_MASK_TRACE 0x1000
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#define VCODEC_MASK_REG 0x10000
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#define VCODEC_MASK_DISABLE_CLK_GATING 0x20000
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#define VCODEC_MASK_ENABLE_DOWNSPEED 0x40000
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#define VCODEC_MASK_CURR (0x0 | VCODEC_MASK_ERR)
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// Below define must sync with middleware
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#define H265_CORE_IDX 0
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#define H264_CORE_IDX 1
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#ifdef VCODEC_DBG_MSG_ENABLE
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#define DPRINTK(msg, ...) VCODEC_DBG_TRACE(msg, ##__VA_ARGS__)
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#else
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#define DPRINTK(msg, ...)
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#endif
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#ifdef VCODEC_DBG_MSG_ENABLE
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extern int vcodec_mask;
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#define VCODEC_DBG_ERR(msg, ...) \
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do { \
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if (vcodec_mask & VCODEC_MASK_ERR) \
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pr_err("[ERR] %s = %d, " msg, __func__, __LINE__, \
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##__VA_ARGS__); \
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} while (0)
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#define VCODEC_DBG_WARN(msg, ...) \
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do { \
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if (vcodec_mask & VCODEC_MASK_WARN) \
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pr_info("[WARN] %s = %d, " msg, __func__, \
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__LINE__, ##__VA_ARGS__); \
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} while (0)
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#define VCODEC_DBG_INFO(msg, ...) \
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do { \
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if (vcodec_mask & VCODEC_MASK_INFO) \
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pr_info("[INFO] %s = %d, " msg, __func__, \
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__LINE__, ##__VA_ARGS__); \
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} while (0)
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#define VCODEC_DBG_FLOW(msg, ...) \
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do { \
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if (vcodec_mask & VCODEC_MASK_FLOW) \
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pr_info("[FLOW] %s = %d, " msg, __func__, \
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__LINE__, ##__VA_ARGS__); \
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} while (0)
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#define VCODEC_DBG_DBG(msg, ...) \
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do { \
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if (vcodec_mask & VCODEC_MASK_DBG) \
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pr_info("[DBG] %s = %d, " msg, __func__, __LINE__, \
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##__VA_ARGS__); \
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} while (0)
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#define VCODEC_DBG_INTR(msg, ...) \
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do { \
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if (vcodec_mask & VCODEC_MASK_INTR) \
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pr_info("[INTR] %s = %d, " msg, __func__, \
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__LINE__, ##__VA_ARGS__); \
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} while (0)
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#define VCODEC_DBG_MCU(msg, ...) \
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do { \
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if (vcodec_mask & VCODEC_MASK_MCU) \
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pr_info("[MCU] %s = %d, " msg, __func__, __LINE__, \
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##__VA_ARGS__); \
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} while (0)
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#define VCODEC_DBG_MEM(msg, ...) \
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do { \
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if (vcodec_mask & VCODEC_MASK_MEM) \
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pr_info("[MEM] %s = %d, " msg, __func__, __LINE__, \
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##__VA_ARGS__); \
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} while (0)
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#define VCODEC_DBG_BS(msg, ...) \
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do { \
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if (vcodec_mask & VCODEC_MASK_BS) \
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pr_info("[BS] %s = %d, " msg, __func__, __LINE__, \
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##__VA_ARGS__); \
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} while (0)
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#define VCODEC_DBG_TRACE(msg, ...) \
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do { \
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if (vcodec_mask & VCODEC_MASK_TRACE) \
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pr_info("[TRACE] %s = %d, " msg, __func__, \
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__LINE__, ##__VA_ARGS__); \
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} while (0)
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#define VCODEC_DBG_REG(msg, ...) \
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do { \
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if (vcodec_mask & VCODEC_MASK_REG) \
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pr_info("[REG] %s = %d, " msg, __func__, __LINE__, \
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##__VA_ARGS__); \
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} while (0)
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#else
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#define VCODEC_DBG_ERR(msg, ...)
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#define VCODEC_DBG_WARN(msg, ...)
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#define VCODEC_DBG_INFO(msg, ...)
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#define VCODEC_DBG_FLOW(msg, ...)
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#define VCODEC_DBG_DBG(msg, ...)
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#define VCODEC_DBG_INTR(msg, ...)
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#define VCODEC_DBG_MCU(msg, ...)
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#define VCODEC_DBG_MEM(msg, ...)
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#define VCODEC_DBG_BS(msg, ...)
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#define VCODEC_DBG_TRACE(msg, ...)
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#define VCODEC_DBG_REG(msg, ...)
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#endif
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extern bool __clk_is_enabled(struct clk *clk);
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#ifdef __cplusplus
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}
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#endif
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#endif
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