0545e9dc6d
commit d1edce71135cc6d98c0a4b5729774542b676e769 Author: sophgo-forum-service <forum_service@sophgo.com> Date: Fri Mar 15 16:07:33 2024 +0800 [fix] recommend using ssh method to clone repo. [fix] fix sensor driver repo branch name.
499 lines
15 KiB
C
499 lines
15 KiB
C
#ifndef __CV_DMA_H__
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#define __CV_DMA_H__
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#if defined(CONFIG_ARM)
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/* Bitfields in CTL */
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#define DWC_CTL_SMS(n) ((n & 0x1)<<0) /* src master select */
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#define DWC_CTL_DMS(n) ((n & 0x1)<<2) /* dst master select */
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#define DWC_CTL_SRC_INC (0<<4) /* Source Address Increment update*/
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#define DWC_CTL_SRC_FIX (1<<4) /* Source Address Increment not*/
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#define DWC_CTL_DST_INC (0<<6) /* Destination Address Increment update*/
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#define DWC_CTL_DST_FIX (1<<6) /* Destination Address Increment not*/
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#define DWC_CTL_SRC_WIDTH(n) ((n & 0x7)<<8) /* Source Transfer Width */
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#define DWC_CTL_DST_WIDTH(n) ((n & 0x7)<<11) /* Destination Transfer Width */
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#define DWC_CTL_SRC_MSIZE(n) ((n & 0xf)<<14) /* SRC Burst Transaction Length, data items */
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#define DWC_CTL_DST_MSIZE(n) ((n & 0xf)<<18) /* DST Burst Transaction Length, data items */
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#define DWC_CTL_AR_CACHE(n) ((n & 0xf)<<22)
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#define DWC_CTL_AW_CACHE(n) ((n & 0xf)<<26)
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#define DWC_CTL_N_LAST_W_EN (1<<30) /* last write posted write enable/disable*/
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#define DWC_CTL_N_LAST_W_DIS (0<<30) /* last write posted wrtie enable/disable*/
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#define DWC_CTL_ARLEN_DIS (0ULL<<38) /* Source Burst Length Disable */
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#define DWC_CTL_ARLEN_EN (1ULL<<38) /* Source Burst Length Enable */
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#define DWC_CTL_ARLEN(n) ((n & 0xffULL)<<39)
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#define DWC_CTL_AWLEN_DIS (0ULL<<47) /* DST Burst Length Enable */
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#define DWC_CTL_AWLEN_EN (1ULL<<47)
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#define DWC_CTL_AWLEN(n) ((n & 0xffULL)<<48)
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#define DWC_CTL_SRC_STA_DIS (0ULL<<56)
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#define DWC_CTL_SRC_STA_EN (1ULL<<56)
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#define DWC_CTL_DST_STA_DIS (0ULL<<57)
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#define DWC_CTL_DST_STA_EN (1ULL<<57)
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#define DWC_CTL_IOC_BLT_DIS (0ULL<<58) /* Interrupt On completion of Block Transfer */
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#define DWC_CTL_IOC_BLT_EN (1ULL<<58)
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#define DWC_CTL_SHADOWREG_OR_LLI_LAST (1ULL<<62) /* Last Shadow Register/Linked List Item */
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#define DWC_CTL_SHADOWREG_OR_LLI_VALID (1ULL<<63) /* Shadow Register content/Linked List Item valid */
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#define DWC_BLOCK_TS_MASK 0x3FFFFF
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#define DWC_CFG_SRC_MULTBLK_TYPE(x) ((x & 0x7) << 0)
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#define DWC_CFG_DST_MULTBLK_TYPE(x) ((x & 0x7) << 2)
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#define DWC_CFG_TT_FC(x) ((x & 0x7ULL) << 32)
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#define DWC_CFG_HS_SEL_SRC_HW (0ULL<<35)
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#define DWC_CFG_HS_SEL_SRC_SW (1ULL<<35)
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#define DWC_CFG_HS_SEL_DST_HW (0ULL<<36)
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#define DWC_CFG_HS_SEL_DST_SW (1ULL<<36)
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#define DWC_CFG_SRC_HWHS_POL_H (0ULL << 37)
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#define DWC_CFG_SRC_HWHS_POL_L (1ULL << 37)
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#define DWC_CFG_DST_HWHS_POL_H (0ULL << 38)
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#define DWC_CFG_DST_HWHS_POL_L (1ULL << 38)
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#define DWC_CFG_SRC_PER(x) ((x & 0xffULL) << 39)
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#define DWC_CFG_DST_PER(x) ((x & 0xffULL) << 44)
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#define DWC_CFG_CH_PRIOR_MASK (0x7ULL << 49) /* priority mask */
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#define DWC_CFG_CH_PRIOR(x) (((x) & 0x7ULL) << 49) /* priority */
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#define DWC_CFG_SRC_OSR_LMT(x) (((x) & 0xfULL) << 55) /* max request x + 1 <= 16 */
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#define DWC_CFG_DST_OSR_LMT(x) (((x) & 0xfULL) << 59)
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#define DWC_CFG_GET_TT_FC(x) ((x >> 32ULL) & 0x7)
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#else
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/* Bitfields in CTL */
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#define DWC_CTL_SMS(n) ((n & 0x1)<<0) /* src master select */
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#define DWC_CTL_DMS(n) ((n & 0x1)<<2) /* dst master select */
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#define DWC_CTL_SRC_INC (0<<4) /* Source Address Increment update*/
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#define DWC_CTL_SRC_FIX (1<<4) /* Source Address Increment not*/
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#define DWC_CTL_DST_INC (0<<6) /* Destination Address Increment update*/
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#define DWC_CTL_DST_FIX (1<<6) /* Destination Address Increment not*/
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#define DWC_CTL_SRC_WIDTH(n) ((n & 0x7)<<8) /* Source Transfer Width */
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#define DWC_CTL_DST_WIDTH(n) ((n & 0x7)<<11) /* Destination Transfer Width */
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#define DWC_CTL_SRC_MSIZE(n) ((n & 0xf)<<14) /* SRC Burst Transaction Length, data items */
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#define DWC_CTL_DST_MSIZE(n) ((n & 0xf)<<18) /* DST Burst Transaction Length, data items */
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#define DWC_CTL_AR_CACHE(n) ((n & 0xf)<<22)
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#define DWC_CTL_AW_CACHE(n) ((n & 0xf)<<26)
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#define DWC_CTL_N_LAST_W_EN (1<<30) /* last write posted write enable/disable*/
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#define DWC_CTL_N_LAST_W_DIS (0<<30) /* last write posted wrtie enable/disable*/
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#define DWC_CTL_ARLEN_DIS (0UL<<38) /* Source Burst Length Disable */
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#define DWC_CTL_ARLEN_EN (1UL<<38) /* Source Burst Length Enable */
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#define DWC_CTL_ARLEN(n) ((n & 0xff)<<39)
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#define DWC_CTL_AWLEN_DIS (0UL<<47) /* DST Burst Length Enable */
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#define DWC_CTL_AWLEN_EN (1UL<<47)
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#define DWC_CTL_AWLEN(n) ((n & 0xff)<<48)
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#define DWC_CTL_SRC_STA_DIS (0UL<<56)
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#define DWC_CTL_SRC_STA_EN (1UL<<56)
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#define DWC_CTL_DST_STA_DIS (0UL<<57)
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#define DWC_CTL_DST_STA_EN (1UL<<57)
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#define DWC_CTL_IOC_BLT_DIS (0UL<<58) /* Interrupt On completion of Block Transfer */
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#define DWC_CTL_IOC_BLT_EN (1UL<<58)
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#define DWC_CTL_SHADOWREG_OR_LLI_LAST (1UL<<62) /* Last Shadow Register/Linked List Item */
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#define DWC_CTL_SHADOWREG_OR_LLI_VALID (1UL<<63) /* Shadow Register content/Linked List Item valid */
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#define DWC_BLOCK_TS_MASK 0x3FFFFF
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#define DWC_CFG_SRC_MULTBLK_TYPE(x) ((x & 0x7) << 0)
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#define DWC_CFG_DST_MULTBLK_TYPE(x) ((x & 0x7) << 2)
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#define DWC_CFG_TT_FC(x) ((x & 0x7) << 32)
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#define DWC_CFG_HS_SEL_SRC_HW (0UL<<35)
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#define DWC_CFG_HS_SEL_SRC_SW (1UL<<35)
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#define DWC_CFG_HS_SEL_DST_HW (0UL<<36)
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#define DWC_CFG_HS_SEL_DST_SW (1UL<<36)
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#define DWC_CFG_SRC_HWHS_POL_H (0UL << 37)
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#define DWC_CFG_SRC_HWHS_POL_L (1UL << 37)
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#define DWC_CFG_DST_HWHS_POL_H (0UL << 38)
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#define DWC_CFG_DST_HWHS_POL_L (1UL << 38)
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#define DWC_CFG_SRC_PER(x) ((x & 0xff) << 39)
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#define DWC_CFG_DST_PER(x) ((x & 0xff) << 44)
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#define DWC_CFG_CH_PRIOR_MASK (0x7UL << 49) /* priority mask */
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#define DWC_CFG_CH_PRIOR(x) ((x & 0x7) << 49) /* priority */
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#define DWC_CFG_SRC_OSR_LMT(x) (((x) & 0xf) << 55) /* max request x + 1 <= 16 */
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#define DWC_CFG_DST_OSR_LMT(x) (((x) & 0xf) << 59)
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#define DWC_CFG_GET_TT_FC(x) ((x >> 32) & 0x7)
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#endif
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#define DWC_CH_INTSTA_DMA_TFR_DONE (1<<1)
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#define DWC_CH_INTSTA_BLOCK_TFR_DONE (1<<0)
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#define DWC_CH_INTSTA_SRC_TFR_COMP_EN (1<<3)
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#define DWC_CH_INTSTA_DST_TFR_COMP_EN (1<<4)
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#define DWC_CH_INTSTA_SRC_DEC_ERR_EN (1<<5)
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#define DWC_CH_INTSTA_DST_DEC_ERR_EN (1<<6)
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#define DWC_CH_INTSTA_SRC_SLV_ERR_EN (1<<7)
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#define DWC_CH_INTSTA_SRC_DST_ERR_EN (1<<8)
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#define DWC_CH_INTSTA_LLI_RD_DEV_ERR_EN (1<<9)
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#define DWC_CH_INTSTA_LLI_WD_DEV_ERR_EN (1<<10)
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#define DWC_CH_INTSTA_LLI_RD_SLV_ERR_EN (1<<11)
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#define DWC_CH_INTSTA_LLI_WD_SLV_ERR_EN (1<<12)
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#define DWC_CH_INTSTA_SHDW_LLI_INVALID_ERR_EN (1<<13)
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#define DWC_CH_INTSTA_SLVIF_MULTBLK_TYPE_ERR_EN (1<<14)
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#define DWC_CH_INTSTA_SLVIF_DEC_ERR_EN (1<<16)
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#define DWC_CH_INTSTA_CH_ABORTED_EN (1<<31)
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#define DWC_CH_SUSPENDED (1 << 29)
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#define DWC_CH_INTSIG_BLK_TRA_DONE (1 << 0)
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#define DWC_CH_INTSIG_DMA_TRA_DONE (1 << 1)
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#define DWC_CH_INTSIG_SRC_COMP_DONE (1 << 3)
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#define DWC_CH_INTSIG_DST_COMP_DONE (1 << 4)
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/* Bitfields in LLP */
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#define DWC_LLP_LMS(x) ((x) & 1) /* list master select */
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#define DWC_LLP_LOC(x) (((x) & ~0x3f)) /* next lli */
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#define DW_DMAC_CH_PAUSE_EN_OFFSET 24
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#define DW_DMAC_CH_PAUSE_OFFSET 16
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#define DW_DMAC_CH_EN_WE_OFFSET 8
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#define DW_DMAC_CH_ABORT_WE_OFFSET 40
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#define DW_DMAC_CH_ABORT_OFFSET 32
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#define DW_CFG_DMA_EN (1 << 0)
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#define DW_CFG_DMA_INT_EN (1 << 1)
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#define DW_DMA_MAX_NR_MASTERS 2
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#define DW_DMA_MAX_NR_CHANNELS 8
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#define DW_DMA_MAX_NR_REQUESTS 16
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#define DW_DMA_CHAN_MASK ((1 << DW_DMA_MAX_NR_CHANNELS) - 1)
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#define DW_DWC_MAX_BLOCK_TS 32
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/* The set of bus widths supported by the DMA controller */
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#define DW_DMA_BUSWIDTHS \
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(BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \
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BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
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BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
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BIT(DMA_SLAVE_BUSWIDTH_4_BYTES))
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#define BM_DMA_PERIOD_LEN 64 //The maxmium LLI data length of BM sysDMA
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#ifdef CONFIG_DW_DMAC_BIG_ENDIAN_IO
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typedef __be32 __dw32;
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typedef __be64 __dw64;
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#else
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typedef __le32 __dw32;
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typedef __le64 __dw64;
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#endif
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enum dwc_multblk_type {
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CONTIGUOUS,
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RELOAD,
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SHADOW_REGISTER,
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LINK_LIST
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};
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/* flow controller */
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enum dw_dma_fc {
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DW_DMA_FC_D_M2M, /* FlowControl is DMAC, mem to mem */
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DW_DMA_FC_D_M2P, /* FlowControl is DMAC, mem to perip */
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DW_DMA_FC_D_P2M,
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DW_DMA_FC_D_P2P,
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DW_DMA_FC_SP_P2M, /* FlowControl is Source periph, periph to mem */
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DW_DMA_FC_SP_P2P,
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DW_DMA_FC_DP_M2P, /* FlowControl is Dst periph, periph to mem */
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DW_DMA_FC_DP_P2P,
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};
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enum dwc_tr_width {
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BITS_WIDTH_UNDEFINED = 0,
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BITS_WIDTH_8_BITS,
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BITS_WIDTH_16_BITS,
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BITS_WIDTH_32_BITS,
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BITS_WIDTH_64_BITS,
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BITS_WIDTH_128_BITS,
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BITS_WIDTH_256_BITS,
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BITS_WIDTH_512_BITS,
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};
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/* chan intstatus*/
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enum dw_dmac_flags {
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DW_DMA_IS_CYCLIC = 0,
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DW_DMA_IS_SOFT_LLP = 1,
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DW_DMA_IS_PAUSED = 2,
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DW_DMA_IS_INITIALIZED = 3,
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};
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/* bursts size */
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enum dw_dma_msize {
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DW_DMA_MSIZE_1,
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DW_DMA_MSIZE_4,
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DW_DMA_MSIZE_8,
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DW_DMA_MSIZE_16,
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DW_DMA_MSIZE_32,
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DW_DMA_MSIZE_64,
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DW_DMA_MSIZE_128,
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DW_DMA_MSIZE_256,
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};
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/*
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* Redefine this macro to handle differences between 32- and 64-bit
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* addressing, big vs. little endian, etc.
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*/
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#define DW_REG(name) u64 name
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/* Hardware register definitions. */
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struct dw_dma_chan_regs {
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DW_REG(SAR); /* Source Address Register */
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DW_REG(DAR); /* Destination Address Register */
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DW_REG(BLOCK_TS); /* Block transfer size */
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DW_REG(CTL); /* Contorl dma transer */
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DW_REG(CFG); /* Configure dma transer */
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DW_REG(LLP); /* Linked List Pointer */
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DW_REG(STATUS); /* Status of dma transer */
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DW_REG(SWHSSRCREG); /* SW handshake source register */
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DW_REG(SWHSDSTREG); /* SW handshake Destination register */
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DW_REG(BLK_TFR_RESUMEREQREG); /* Block transfer resume request */
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DW_REG(AXI_IDREG); /* AXI ID register */
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DW_REG(AXI_QOSREG); /* AXI QoS register */
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DW_REG(SSTAT);
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DW_REG(DSTAT);
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DW_REG(SSTATAR);
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DW_REG(DSTATAR);
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DW_REG(INTSTATUS_ENABLEREG);
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DW_REG(INTSTATUS);
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DW_REG(INTSIGNAL_ENABLEREG);
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DW_REG(INTCLEARREG);
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u64 __reserved1[12];
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};
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struct dw_dma_regs {
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/* Common Registers */
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DW_REG(ID);
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DW_REG(COMPVER);
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DW_REG(CFG);
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DW_REG(CH_EN);
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u64 __reserved0[2];
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DW_REG(INTSTATUS);
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DW_REG(COMM_INTCLEAR);
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DW_REG(COMM_INTSTATUS_EN);
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DW_REG(COMM_INTSIGNAL_EN);
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DW_REG(COMM_INTSTATUS);
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DW_REG(RESET);
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u64 __reserved1[20];
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/* channel regs */
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struct dw_dma_chan_regs CHAN[DW_DMA_MAX_NR_CHANNELS];
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};
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/**
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* struct dw_dma_slave - Controller-specific information about a slave
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*
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* @dma_dev: required DMA master device
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* @src_id: src request line
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* @dst_id: dst request line
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* @m_master: memory master for transfers on allocated channel
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* @p_master: peripheral master for transfers on allocated channel
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* @hs_polarity:set active low polarity of handshake interface
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*/
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struct dw_dma_slave {
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struct device *dma_dev;
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u8 src_id;
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u8 dst_id;
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u8 m_master;
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u8 p_master;
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bool hs_polarity;
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};
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struct dbg_fix_buf {
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int id;
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void *cpu_addr;
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dma_addr_t dma_hanle;
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unsigned int size;
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unsigned int state;
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};
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struct dbg_fix_sg {
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int count;
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struct dbg_fix_buf *fix_buf;
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};
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struct dw_cyclic_desc {
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struct dw_desc **desc;
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unsigned long periods;
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size_t period_len;
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unsigned int last_sent;
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void (*period_callback)(void *param);
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void *period_callback_param;
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};
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struct dw_dma_chan {
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struct dma_chan chan;
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void __iomem *ch_regs;
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u64 mask;
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u64 priority;
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enum dma_transfer_direction direction;
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spinlock_t lock;
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/* these other elements are all protected by lock */
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unsigned long flags;
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unsigned long status;
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struct list_head active_list;
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struct list_head queue;
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struct dw_cyclic_desc *cdesc;
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unsigned int descs_allocated;
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/* hardware configuration */
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unsigned int axi_tr_width;
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unsigned int block_size;
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unsigned int block_ts;
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/* custom slave configuration */
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struct dw_dma_slave dws;
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/* configuration passed via .device_config */
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struct dma_slave_config dma_sconfig;
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/* fix bug sysdma */
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struct dbg_fix_sg *bug_info;
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struct dma_pool *bug_fix_dma_pool;
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u32 hw_pos;
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u32 interrupt_count;
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};
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/* LLI == Linked List Item; a.k.a. DMA block descriptor */
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struct dw_lli {
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/* values that are not changed by hardware */
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__dw64 sar;
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__dw64 dar;
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__dw64 block_ts;
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__dw64 llp; /* chain to next lli */
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__dw64 ctl;
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/* sstat and dstat can snapshot peripheral register state.
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* silicon config may discard either or both...
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*/
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__dw32 sstat;
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__dw32 dstat;
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__dw64 llp_status;
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__dw64 reserved;
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};
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struct dw_desc {
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/* FIRST values the hardware uses */
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struct dw_lli lli;
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#ifdef CONFIG_DW_DMAC_BIG_ENDIAN_IO
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#define lli_set(d, reg, v) ((d)->lli.reg |= cpu_to_be64(v))
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#define lli_clear(d, reg, v) ((d)->lli.reg &= ~cpu_to_be64(v))
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#define lli_read(d, reg) be64_to_cpu((d)->lli.reg)
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#define lli_write(d, reg, v) ((d)->lli.reg = cpu_to_be64(v))
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#else
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#define lli_set(d, reg, v) ((d)->lli.reg |= cpu_to_le64(v))
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#define lli_clear(d, reg, v) ((d)->lli.reg &= ~cpu_to_le64(v))
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#define lli_read(d, reg) le64_to_cpu((d)->lli.reg)
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#define lli_write(d, reg, v) ((d)->lli.reg = cpu_to_le64(v))
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#endif
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/* THEN values for driver housekeeping */
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struct list_head desc_node;
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struct list_head tx_list;
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struct dma_async_tx_descriptor txd;
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size_t len;
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size_t total_len;
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u32 residue;
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u32 hw_pos;
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};
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#ifdef CONFIG_PM_SLEEP
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struct dw_dma_pm_chan_regs {
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DW_REG(SAR); /* Source Address Register */
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DW_REG(DAR); /* Destination Address Register */
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DW_REG(BLOCK_TS); /* Block transfer size */
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DW_REG(CTL); /* Contorl dma transer */
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DW_REG(CFG); /* Configure dma transer */
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DW_REG(LLP); /* Linked List Pointer */
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DW_REG(INTSTATUS_ENABLEREG);
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DW_REG(INTSIGNAL_ENABLEREG);
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};
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struct dw_dma_reg_context {
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u64 cfg;
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u64 chen;
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struct dw_dma_pm_chan_regs chan[DW_DMA_MAX_NR_CHANNELS];
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};
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#endif
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|
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struct dw_dma {
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struct device *dev;
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void __iomem *regs;
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struct dma_pool *desc_pool;
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struct dma_device dma;
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|
struct clk *clk;
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|
struct tasklet_struct tasklet;
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|
|
|
/* dma configs */
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|
unsigned char nr_channels;
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|
bool is_private;
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|
bool is_memcpy;
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|
#define CHAN_ALLOCATION_ASCENDING 0 /* zero to seven */
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|
#define CHAN_ALLOCATION_DESCENDING 1 /* seven to zero */
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|
unsigned char chan_allocation_order;
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|
#define CHAN_PRIORITY_ASCENDING 0 /* chan0 highest */
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|
#define CHAN_PRIORITY_DESCENDING 1 /* chan7 highest */
|
|
unsigned char chan_priority;
|
|
unsigned int axi_tr_width;
|
|
unsigned int block_size;
|
|
unsigned int block_ts;
|
|
unsigned char nr_masters;
|
|
unsigned char data_width[DW_DMA_MAX_NR_MASTERS];
|
|
|
|
/* channels */
|
|
struct dw_dma_chan *chan;
|
|
u8 in_use;
|
|
u8 clk_count;
|
|
u8 log_on;
|
|
|
|
/* interrupt*/
|
|
int irq;
|
|
spinlock_t lock;
|
|
#ifdef CONFIG_PM_SLEEP
|
|
struct dw_dma_reg_context *reg_ctx;
|
|
#endif
|
|
};
|
|
|
|
#ifdef CONFIG_DW_DMAC_BIG_ENDIAN_IO
|
|
#define dma_readl_native ioread32be
|
|
#define dma_writel_native iowrite32be
|
|
#else
|
|
#define dma_readl_native readl
|
|
#define dma_writel_native writel
|
|
#ifdef readq
|
|
#define dma_readq_native readq
|
|
#else
|
|
#define dma_readq_native(__reg) (*(volatile u64 __force *)(__reg))
|
|
#endif
|
|
#ifdef writeq
|
|
#define dma_writeq_native writeq
|
|
#else
|
|
#define dma_writeq_native(__value,__reg) \
|
|
(*(volatile u64 __force *)(__reg) = (__value))
|
|
#endif
|
|
#endif
|
|
|
|
#define dma_readq(dw, name) \
|
|
dma_readq_native(&(__dw_regs(dw)->name))
|
|
|
|
#define dma_writeq(dw, name, val) \
|
|
dma_writeq_native((val), &(__dw_regs(dw)->name))
|
|
|
|
#define channel_readq(dwc, name) \
|
|
dma_readq_native(&(__dwc_regs(dwc)->name))
|
|
|
|
#define channel_writeq(dwc, name, val) \
|
|
dma_writeq_native((val), &(__dwc_regs(dwc)->name))
|
|
|
|
#define dma_set_bit(dw, name, mask) \
|
|
dma_writeq_native(((mask) | dma_readq_native(&(__dw_regs(dw)->name))) \
|
|
, &(__dw_regs(dw)->name))
|
|
|
|
#define dma_clear_bit(dw, name, mask) \
|
|
dma_writeq_native((~mask & dma_readq_native(&(__dw_regs(dw)->name))) \
|
|
, &(__dw_regs(dw)->name))
|
|
|
|
#define channel_set_bit(dwc, name, mask) \
|
|
dma_writeq_native((mask | dma_readq_native(&(__dwc_regs(dwc)->name))), \
|
|
&(__dwc_regs(dwc)->name))
|
|
|
|
#define channel_clear_bit(dwc, name, mask) \
|
|
dma_writeq_native((~mask & dma_readq_native(&(__dwc_regs(dwc)->name))), \
|
|
&(__dwc_regs(dwc)->name))
|
|
#endif
|