0545e9dc6d
commit d1edce71135cc6d98c0a4b5729774542b676e769 Author: sophgo-forum-service <forum_service@sophgo.com> Date: Fri Mar 15 16:07:33 2024 +0800 [fix] recommend using ssh method to clone repo. [fix] fix sensor driver repo branch name.
100 lines
3.1 KiB
C
100 lines
3.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later
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* CV1835 ADC driver on CVITEK CV1835
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*
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* Copyright 2019 CVITEK
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*
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* Author: EthanChen
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*
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*/
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#ifndef __CV1835ADC_H__
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#define __CV1835ADC_H__
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#include <linux/clk.h>
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#include <linux/miscdevice.h>
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#define CVI_ADC_GSEL_REG 0x00
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#define CVI_ADC_GSELR_MASK 0xFFFFFFE0
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#define CVI_ADC_GSELR(v) (v << 0)
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#define CVI_ADC_GSELL_MASK 0xFFFFE0FF
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#define CVI_ADC_GSELL(v) (v << 8)
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#define CVI_ADC_GSELR_MIC_MASK 0xFFF8FFFF
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#define CVI_ADC_GSELR_MIC(v) (v << 16)
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#define CVI_ADC_GSELL_MIC_MASK 0xF8FFFFFF
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#define CVI_ADC_GSELL_MIC(v) (v << 24)
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#define CVI_ADC_CTRL_REG 0x04
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#define CVI_ADC_INSELR_LINE 0xFFFFFFFE /* bit[0] == 0*/
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#define CVI_ADC_INSELR_MIC (1 << 0)
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#define CVI_ADC_INSELL_LINE 0xFFFFFFFD /* bit[1] == 0*/
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#define CVI_ADC_INSELL_MIC (1 << 1)
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#define CVI_ADC_POWER_MASK 0xFFFCFF0C /* use to reset power on/off related bits */
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#define CVI_ADC_ENADR_POWER_DOWN 0xFFFFFFFB /* bit[2] == 0*/
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#define CVI_ADC_ENADR_NORMAL (1 << 2)
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#define CVI_ADC_ENADL_POWER_DOWN 0xFFFFFFF7 /* bit[3] == 0*/
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#define CVI_ADC_ENADL_NORMAL (1 << 3)
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#define CVI_ADC_VREF_POWER_DOWN 0xFFFFFFEF /* bit[4] == 0*/
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#define CVI_ADC_VERF_NORMAL (1 << 4)
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#define CVI_ADC_ZCD_DISABLE 0xFFFFFFDF /* bit[5] == 0*/
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#define CVI_ADC_ZCD_ENABLE (1 << 5)
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#define CVI_ADC_HPR_BYPASS 0xFFFFFFBF /* bit[6] == 0*/
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#define CVI_ADC_HPR_ENABLE (1 << 6)
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#define CVI_ADC_HPL_BYPASS 0xFFFFFF7F /* bit[7] == 0*/
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#define CVI_ADC_HPL_ENABLE (1 << 7)
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#define CVI_ADC_OVRS_MASK 0xFFFCFFFF
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#define CVI_ADC_OVRS(v) (v << 16)
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#define CVI_ADC_OVTOP_REG 0x08
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#define CVI_ADC_TEST_MODE_REG 0x0C
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#define CVI_ADC_TM_NORMAL 0x0
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#define CVI_ADC_TM_READ_ROM 0x2
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#define CVI_ADC_TM_R_PCM 0x6
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#define CVI_ADC_TM_L_PCM 0x7
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#define CVI_ADC_RSEL_REG 0x10
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#define CVI_ADC_FS_SEL_REG 0x14 /* ADMCLK/LRCK ratio */
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#define CVI_ADC_RATIO_256 0x0
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#define CVI_ADC_RATIO_512 0x1
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#define CVI_ADC_RATIO_1024 0x2
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#define CVI_ADC_DAGC_CTRL_REG 0x20 /* digital AGC control */
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#define CVI_ADC_DAGC_DISABLE 0xFFFFFFFE /* bit[0] == 0 */
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#define CVI_ADC_DAGC_ENABLE (1 << 0)
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#define CVI_ADC_DAGC_RMS_MODE 0xFFFFFFFD /* bit[1] == 1 */
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#define CVI_ADC_DAGC_PEAK_MODE (1 << 1)
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#define CVI_ADC_DAGC_ZCD_DISABLE 0xFFFFFFFB /* bit[2] == 0 */
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#define CVI_ADC_DAGC_ZCD_ENABLE (1 << 2)
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#define CVI_ADC_DAGC_THOLD_REG 0x24
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#define CVI_ADC_DAGC_THOLD_MASK 0xFFFFFF81
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#define CVI_ADC_DAGC_THOLD(v) (v << 0) /* maximum is 0x7f, minimum is 0x01 */
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#define CVI_ADC_DAGC_UPDATE_THOLD_MASK 0x8000FFFF
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#define CVI_ADC_DAGC_UPDATE_THOLD(v) (v << 16) /* maximum is 0x7fff */
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#define CVI_ADC_DAGC_ATTACKTIME_REG 0x28
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#define CVI_ADC_DAGC_SRC_DM_REG 0x2C
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#define CVI_SDC_DAGC_UPDATE_FREQ_MASK 0xFFFFF000
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#define CVI_SDC_DAGC_UPDATE_FREQ(v) (v << 0)
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#define CVI_ADC_DAGC_SRC_DM_MASK 0xFFFFCFFF
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#define CVI_ADC_DAGC_SRC_DM_MONO_L (0 << 12)
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#define CVI_ADC_DAGC_PGAG_REG 0x30
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#define CVI_ADC_DAGC_PGAG_R 0x0000001F
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#define CVI_ADC_DAGC_PGAG_L 0x00001F00
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#define CVI_ADC_ADCO_REG 0x34
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struct cvi1835adc {
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void __iomem *adc_base;
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struct clk *clk;
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struct device *dev;
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struct miscdevice miscdev;
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};
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extern struct proc_dir_entry *proc_audio_dir;
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#endif /* __CV1835ADC_H__ */
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