0545e9dc6d
commit d1edce71135cc6d98c0a4b5729774542b676e769 Author: sophgo-forum-service <forum_service@sophgo.com> Date: Fri Mar 15 16:07:33 2024 +0800 [fix] recommend using ssh method to clone repo. [fix] fix sensor driver repo branch name.
276 lines
8.6 KiB
C
276 lines
8.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later
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* I2S driver on CVITEK CV1835
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*
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* Copyright 2018 CVITEK
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*
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* Author: EthanChen
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*
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*
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*/
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#ifndef __CVITEK_LOCAL_H__
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#define __CVITEK_LOCAL_H__
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#include <linux/clk.h>
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#include <linux/device.h>
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#include <linux/types.h>
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#include <sound/dmaengine_pcm.h>
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#include <sound/pcm.h>
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#include <sound/cv1835_i2s.h>
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#define I2S_MODE 0x0
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#define LJ_MODE 0x1
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#define RJ_MODE 0x2
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#define PCM_A_MODE 0x3
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#define PCM_B_MODE 0x4
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#define TDM_MODE 0x5
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#define I2STDM_FIFO_DEPTH 32 /* 32 items */
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#define I2STDM_FIFO_WIDTH 4 /* 32 bits */
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/* common register offset */
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#define BLK_MODE_SETTING 0x00
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#define FRAME_SETTING 0x04
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#define SLOT_SETTING1 0x08
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#define SLOT_SETTING2 0x0C
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#define DATA_FORMAT 0x10
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#define BLK_CFG 0x14
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#define I2S_ENABLE 0x18
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#define I2S_RESET 0x1C
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#define I2S_INT_EN 0x20
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#define I2S_INT 0x24
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#define FIFO_THRESHOLD 0x28
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#define I2S_LRCK_MASTER 0x2C
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#define FIFO_RESET 0x30
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#define RX_STATUS 0x40
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#define TX_STATUS 0x48
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#define DMA_REQ_COUNT 0x50
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#define DMA_ACK_COUNT 0x54
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#define I2S_CLK_CTRL0 0x60
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#define I2S_CLK_CTRL1 0x64
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#define I2S_PCM_SYNTH 0x68
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#define RX_RD_PORT_CH0 0x80
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#define RX_RD_PORT_CH1 0x84
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#define TX_WR_PORT_CH0 0xC0
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#define TX_WR_PORT_CH1 0xC4
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/* subsystem register offset */
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#define I2S_TDM_SCLK_IN_SEL 0x000
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#define I2S_TDM_FS_IN_SEL 0x004
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#define I2S_TDM_SDI_IN_SEL 0x008
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#define I2S_TDM_SDO_OUT_SEL 0x00C
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#define I2S_TDM_MULTI_SYNC 0x020
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#define I2S_BCLK_OEN_SEL 0x030
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/* define value of each configuration of register BLK_MODE_SETTING */
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#define RX_MODE (0x0 << 0)
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#define TX_MODE (0x1 << 0)
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#define SLAVE_MODE (0x0 << 1)
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#define MASTER_MODE (0x1 << 1)
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#define RX_SAMPLE_EDGE_N (0x0 << 2) /* Negative edge */
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#define RX_SAMPLE_EDGE_P (0x1 << 2) /* Positive edge */
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#define TX_SAMPLE_EDGE_N (0x0 << 3)
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#define TX_SAMPLE_EDGE_P (0x1 << 3)
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#define FS_SAMPLE_EDGE_N (0x0 << 4)
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#define FS_SAMPLE_EDGE_P (0x1 << 4)
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#define FS_SAMPLE_RX_DELAY (0x1 << 5)
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#define FS_SAMPLE_RX_NO_DELAY (0x0 << 5)
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#define SW_MODE (0x0 << 7)
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#define HW_DMA_MODE (0x1 << 7)
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#define MULTI_I2S_SYNC (0x1 << 8)
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#define TXRX_MODE_MASK 0x00000001
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#define ROLE_MASK 0x00000002
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#define SAMPLE_EDGE_MASK 0x0000001C
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#define FS_SAMPLE_RX_DELAY_MASK 0x00000020
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#define DMA_MODE_MASK 0x00000080
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#define MULTI_I2S_MODE_MASK 0x00000100
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/* define value of each configuration of register FRAME_SETTING */
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#define FS_POLARITY_MASK 0x00001000
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#define FS_OFFSET_MASK 0x00002000
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#define FS_IDEF_MASK 0x00004000
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#define FS_ACT_LENGTH_MASK 0x00FF0000
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#define FRAME_LENGTH_MASK 0x000001FF
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#define FRAME_LENGTH(l) (((l-1) << 0) & FRAME_LENGTH_MASK) /* frame length between 0~511 = 1~512 bits */
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#define FS_ACT_LOW (0x0 << 12)
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#define FS_ACT_HIGH (0x1 << 12)
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#define NO_FS_OFFSET (0x0 << 13)
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#define FS_OFFSET_1_BIT (0x1 << 13)
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#define FS_IDEF_FRAME_SYNC (0x0 << 14) /* frame sync*/
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#define FS_IDEF_CH_SYNC (0x1 << 14) /* channel sync */
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#define FS_ACT_LENGTH(l) (((l-1) << 16) & FS_ACT_LENGTH_MASK) /* frame active length between 0~255 = 1~256 bits*/
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/* define value of each configuration of register SLOT_SETTING1 */
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#define SLOT_NUM_MASK 0x0000000F
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#define SLOT_SIZE_MASK 0x00003F00
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#define DATA_SIZE_MASK 0x001F0000
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#define FB_OFFSET_MASK 0x1F000000
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#define SLOT_NUM(l) (((l-1) << 0) & SLOT_NUM_MASK)
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#define SLOT_SIZE(l) (((l-1) << 8) & SLOT_SIZE_MASK)
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#define DATA_SIZE(l) (((l-1) << 16) & DATA_SIZE_MASK)
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#define FB_OFFSET(l) ((l << 24) & FB_OFFSET_MASK)
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/* define value of each configuration of register DATA_FORMAT */
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#define WORD_LENGTH_MASK (0x3 << 1)
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#define WORD_LEN_8 (0x0 << 1)
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#define WORD_LEN_16 (0x1 << 1)
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#define WORD_LEN_32 (0x2 << 1)
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#define SKIP_RX_INACT_SLOT_MASK (0x1 << 4)
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#define SKIP_RX_INACT_SLOT (0x1 << 4)
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#define SKIP_TX_INACT_SLOT_MASK (0x1 << 5)
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#define SKIP_TX_INACT_SLOT (0x1 << 5)
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/* define value of each configuration of register I2S_RESET */
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#define I2S_RESET_RX_PULL_UP 0x00000001
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#define I2S_RESET_RX_PULL_DOWN 0x00000000
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#define I2S_RESET_TX_PULL_UP 0x00000002
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#define I2S_RESET_TX_PULL_DOWN 0x00000000
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/* define value of each configuration of register I2S_INT_EN */
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#define I2S_INT_EN_ALL 0x00000077
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/* define value of each configuration of register I2S_INT */
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#define I2S_INT_RXDA (0x1 << 0) /* RX FIFO data available interrupt status */
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#define I2S_INT_RXFO (0x1 << 1) /* RX FIFO overflow interrupt status */
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#define I2S_INT_RXFU (0x1 << 2) /* RX FIFO underflow interrupt status */
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#define I2S_INT_TXDA (0x1 << 4) /* RX FIFO data available interrupt status */
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#define I2S_INT_TXFO (0x1 << 5) /* RX FIFO overflow interrupt status */
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#define I2S_INT_TXFU (0x1 << 6) /* RX FIFO underflow interrupt status */
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#define I2S_INT_RXDA_RAW (0x1 << 8) /* RX FIFO data available interrupt raw status */
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#define I2S_INT_RXFO_RAW (0x1 << 9) /* RX FIFO overflow interrupt raw status */
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#define I2S_INT_RXFU_RAW (0x1 << 10) /* RX FIFO underflow interrupt raw status */
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#define I2S_INT_TXDA_RAW (0x1 << 12) /* RX FIFO data available interrupt raw status */
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#define I2S_INT_TXFO_RAW (0x1 << 13) /* RX FIFO overflow interrupt raw status */
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#define I2S_INT_TXFU_RAW (0x1 << 14) /* RX FIFO underflow interrupt raw status */
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/* define value of each configuration of register FIFO_THRESHOLD */
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#define RX_FIFO_THRESHOLD_MASK 0x0000001F
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#define TX_FIFO_THRESHOLD_MASK 0x001F0000
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#define TX_FIFO_HIGH_THRESHOLD_MASK 0x1F000000
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#define RX_FIFO_THRESHOLD(v) ((v << 0) & RX_FIFO_THRESHOLD_MASK)
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#define TX_FIFO_THRESHOLD(v) ((v << 16) & TX_FIFO_THRESHOLD_MASK)
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#define TX_FIFO_HIGH_THRESHOLD(v) ((v << 24) & TX_FIFO_HIGH_THRESHOLD_MASK)
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/* define value of each configuration of register FIFO_RESET */
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#define RX_FIFO_RESET_PULL_UP 0x00000001
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#define RX_FIFO_RESET_PULL_DOWN 0x00000000
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#define TX_FIFO_RESET_PULL_UP 0x00010000
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#define TX_FIFO_RESET_PULL_DOWN 0x00000000
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/* define value of each configuration of register RX_STATUS */
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#define RESET_RX_SCLK 0x00800000
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/* define value of each configuration of register TX_STATUS */
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#define RESET_TX_SCLK 0x00800000
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/* define value of each configuration of register CLK_CTRL0 */
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#define AUD_CLK_SOURCE_MASK 0x00000001
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#define AUD_SWITCH 0x00000100
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#define AUD_CLK_FROM_PLL (0x0 << 0)
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#define AUD_CLK_FROM_MCLK_IN (0x1 << 0)
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#define AUD_DISABLE (0x0 << 8)
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#define AUD_ENABLE (0x1 << 8)
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#define MCLK_OUT_EN (0x1 << 7)
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#define BCLK_OUT_FORCE_EN (0x1 << 6)
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/* define value of each configuration of register CLK_CTRL1 */
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#define MCLK_DIV(l) ((l << 0) & 0x0000FFFF)
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#define BCLK_DIV(l) ((l << 16) & 0xFFFF0000)
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#define FMT_IB_NF 0x0 /* sample at falling edge and sync polarity is active low*/
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#define FMT_IB_IF 0x1
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#define FMT_NB_NF 0x2
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#define FMT_NB_IF 0x3
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#define I2S_ON 0x1
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#define I2S_OFF 0x0
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/* I2S Tx Control */
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#define I2S_TX_ON 0x1
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#define I2S_TX_OFF 0x0
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/* I2S Rx Control */
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#define I2S_RX_ON 0x1
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#define I2S_RX_OFF 0x0
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#define WSS_16_CLKCYCLE 0x20
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#define WSS_24_CLKCYCLE 0x30
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#define WSS_32_CLKCYCLE 0x40
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#define WSS_256_CLKCYCLE 0x200
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union cvi_i2s_snd_dma_data {
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struct i2s_dma_data pd;
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struct snd_dmaengine_dai_dma_data dt;
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};
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#ifdef CONFIG_PM_SLEEP
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struct cvi_i2s_reg_context {
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u32 blk_setting;
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u32 frame_setting;
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u32 slot_setting1;
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u32 slot_setting2;
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u32 data_format;
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u32 blk_cfg;
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u32 i2s_en;
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u32 i2s_int_en;
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u32 fifo_threshold;
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u32 i2s_lrck_master;
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u32 i2s_clk_ctl0;
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u32 i2c_clk_ctl1;
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u32 i2s_pcm_synth;
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};
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#endif
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struct cvi_i2s_dev {
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void __iomem *i2s_base;
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struct clk *clk;
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int active;
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unsigned int capability;
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unsigned int quirks;
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struct device *dev;
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u32 wss;
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u32 fifo_th;
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u32 dev_id;
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u8 mode;
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u8 sample_edge;
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u8 role;
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/* data related to DMA transfers b/w i2s and DMAC */
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union cvi_i2s_snd_dma_data play_dma_data;
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union cvi_i2s_snd_dma_data capture_dma_data;
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struct i2s_clk_config_data config;
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int (*i2s_clk_cfg)(struct i2s_clk_config_data *config);
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struct snd_pcm_substream __rcu *tx_substream;
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unsigned int (*tx_fn)(struct cvi_i2s_dev *dev,
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struct snd_pcm_runtime *runtime, unsigned int tx_ptr,
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bool *period_elapsed);
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unsigned int tx_ptr;
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bool mclk_out;
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#ifdef CONFIG_PM_SLEEP
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struct cvi_i2s_reg_context *reg_ctx;
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#endif
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};
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#if IS_ENABLED(CONFIG_SND_CV1835_PCM)
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void cvi_pcm_push_tx(struct cvi_i2s_dev *dev);
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int cvi_pcm_register(struct platform_device *pdev);
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#else
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void cvi_pcm_push_tx(struct cvi_i2s_dev *dev) { }
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int cvi_pcm_register(struct platform_device *pdev)
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{
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return -EINVAL;
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}
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#endif
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#endif /* __CVITEK_LOCAL_H__ */
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