0545e9dc6d
commit d1edce71135cc6d98c0a4b5729774542b676e769 Author: sophgo-forum-service <forum_service@sophgo.com> Date: Fri Mar 15 16:07:33 2024 +0800 [fix] recommend using ssh method to clone repo. [fix] fix sensor driver repo branch name.
317 lines
11 KiB
C
317 lines
11 KiB
C
/*
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* Copyright (C) 2023 bitmain
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*/
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#ifndef __CVI_I2S_H_
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#define __CVI_I2S_H_
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#define I2S0 0
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#define I2S1 1
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#define I2S2 2
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#define I2S3 3
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#define CONFIG_SYS_I2S0_BASE 0x04100000
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#define CONFIG_SYS_I2S1_BASE 0x04110000
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#define CONFIG_SYS_I2S2_BASE 0x04120000
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#define CONFIG_SYS_I2S3_BASE 0x04130000
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#define CONFIG_SYS_I2S_SYS_BASE 0x04108000
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#define REG_AUDIO_SRC_BASE 0x041D0000
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#define REG_AUDIO_MISC_BASE 0x041D0C00
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#define REG_AUDIO_GPIO_BASE 0x0300A12C
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#define CONFIG_USE_AUDIO_PLL
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#define CONFIG_SHIFT_HALF_T
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//shit 1/2 T for inv, ex master generate data at falling edge and let codec sample at rising edge//
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#define I2S_BITS_PER_LONG 32
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#define BIT(nr) (1UL << (nr))
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#define I2S_GENMASK(h, l) \
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(((~0UL) << (l)) & (~0UL >> (I2S_BITS_PER_LONG - 1 - (h))))
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struct i2s_tdm_regs {
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u32 blk_mode_setting; /* 0x00 */
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u32 frame_setting; /* 0x04 */
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u32 slot_setting1; /* 0x08 */
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u32 slot_setting2; /* 0x0c */
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u32 data_format; /* 0x10 */
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u32 blk_cfg; /* 0x14 */
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u32 i2s_enable; /* 0x18 */
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u32 i2s_reset; /* 0x1C */
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u32 i2s_int_en; /* 0x20 */
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u32 i2s_int; /* 0x24 */
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u32 fifo_threshold; /* 0x28 */
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u32 dummy1[1]; /* 0x2c */
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u32 fifo_reset; /* 0x30 */
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u32 dummy2[3]; /* 0x34 ~ 0x3C */
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u32 rx_status; /* 0x40 */
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u32 dummy3[1]; /* 0x44 */
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u32 tx_status; /* 0x48 */
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u32 dummy4[5]; /* 0x4c ~ 0x5c */
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u32 i2s_clk_ctrl0; /* 0x60 */
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u32 i2s_clk_ctrl1; /* 0x64 */
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u32 dummy5[6]; /* 0x68 ~ 0x7c */
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u32 rx_rd_port_ch0; /* 0x80 */
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u32 rx_rd_port_ch1; /* 0x84 */
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u32 dummy6[14]; /* 0x88 ~ 0xbc */
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u32 tx_wr_port_ch0; /* 0xc0 */
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u32 tx_wr_port_ch1; /* 0xc4 */
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};
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struct i2s_sys_regs {
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u32 i2s_tdm_sclk_in_sel; /* 0x000 */
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u32 i2s_tdm_fs_in_sel; /* 0x004 */
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u32 i2s_tdm_sdi_in_sel; /* 0x008 */
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u32 i2s_tdm_sdo_out_sel; /* 0x00C */
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u32 dummy1[4];
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u32 i2s_tdm_multi_sync; /* 0x020 */
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u32 dummy2[3];
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u32 i2s_bclk_oen_sel; /* 0x030 */
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u32 i2s_bclk_out_ctrl; /* 0x034 */
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u32 dummy3[2];
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u32 audio_pdm_ctrl; /* 0x040 */
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u32 dummy4[3];
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u32 audio_phy_bypass1; /* 0x050 */
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u32 audio_phy_bypass2; /* 0x054 */
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u32 dummy5[6];
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u32 i2s_sys_clk_ctrl; /* 0x070 */
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u32 dummy6[3];
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u32 i2s0_master_clk_ctrl0; /* 0x080 */
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u32 i2s0_master_clk_ctrl1; /* 0x084 */
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u32 dummy7[2];
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u32 i2s1_master_clk_ctrl0; /* 0x090 */
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u32 i2s1_master_clk_ctrl1; /* 0x094 */
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u32 dummy8[2];
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u32 i2s2_master_clk_ctrl0; /* 0x0A0 */
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u32 i2s2_master_clk_ctrl1; /* 0x0A4 */
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u32 dummy9[2];
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u32 i2s3_master_clk_ctrl0; /* 0x0B0 */
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u32 i2s3_master_clk_ctrl1; /* 0x0B4 */
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u32 dummy10[2];
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u32 i2s_sys_lrck_ctrl; /* 0x0C0 */
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};
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struct reg_audio_misc_regs {
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u32 dummy[12];
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u32 reg_pdm_en; /* 0x30 */
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u32 reg_pdm_clk; /* 0x34 */
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u32 reg_pdm_i2s; /* 0x38 */
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};
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struct reg_audio_src_regs {
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u32 reg_src_en; /* 0x00 */
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u32 reg_src_sel; /* 0x04 */
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u32 reg_src_setting; /* 0x08 */
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u32 reg_src_format; /* 0x0c */
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u32 dummy1[5];
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u32 reg_src_ratio; /* 0x24 */
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u32 reg_src_fsi_init; /* 0x28 */
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u32 dummy2[1];
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u32 reg_src_i2s_status; /* 0x30 */
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u32 dummy3[11];
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u32 reg_src_data_out; /* 0x60 */
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u32 reg_dma_th; /* 0x64 */
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};
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#define I2S_TIMEOUT 2000000
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#define I2S_MODE 0x0
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#define LJ_MODE 0x1
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#define RJ_MODE 0x2
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#define PCM_A_MODE 0x3
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#define PCM_B_MODE 0x4
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#define TDM_MODE 0x5
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/* define value of each configuration of register BLK_MODE_SETTING */
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#define RX_MODE 0x0 << 0
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#define TX_MODE 0x1 << 0
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#define SLAVE_MODE 0x0 << 1
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#define MASTER_MODE 0x1 << 1
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#define RX_SAMPLE_EDGE_N 0x0 << 2 /* Negative edge */
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#define RX_SAMPLE_EDGE_P 0x1 << 2 /* Positive edge */
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#define TX_SAMPLE_EDGE_N 0x0 << 3
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#define TX_SAMPLE_EDGE_P 0x1 << 3
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#define FS_SAMPLE_EDGE_N 0x0 << 4
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#define FS_SAMPLE_EDGE_P 0x1 << 4
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#define FS_SAMPLE_RX_DELAY 0x1 << 5
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#define FS_SAMPLE_RX_NO_DELAY 0x0 << 5
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#define SW_MODE 0x0 << 7
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#define HW_DMA_MODE 0x1 << 7
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#define MULTI_I2S_SYNC 0x1 << 8
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#define TXRX_MODE_MASK 0x00000001
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#define ROLE_MASK 0x00000002
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#define SAMPLE_EDGE_MASK 0x0000001C
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#define FS_SAMPLE_RX_DELAY_MASK 0x00000020
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#define DMA_MODE_MASK 0x00000080
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#define MULTI_I2S_MODE_MASK 0x00000100
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/* define value of each configuration of register FRAME_SETTING */
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#define FS_POLARITY_MASK 0x00001000
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#define FS_OFFSET_MASK 0x00002000
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#define FS_IDEF_MASK 0x00004000
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#define FS_ACT_LENGTH_MASK 0x00FF0000
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#define FRAME_LENGTH_MASK 0x000001FF
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#define FRAME_LENGTH(l) (((l-1) << 0) & FRAME_LENGTH_MASK) /* frame length between 0~511 = 1~512 bits */
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#define FS_ACT_LOW 0x0 << 12
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#define FS_ACT_HIGH 0x1 << 12
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#define NO_FS_OFFSET 0x0 << 13
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#define FS_OFFSET_1_BIT 0x1 << 13
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#define FS_IDEF_FRAME_SYNC 0x0 << 14 /* frame sync*/
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#define FS_IDEF_I2S_LR 0x1 << 14 /* frame sync*/
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#define FS_IDEF_CH_SYNC 0x1 << 14 /* channel sync */
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#define FS_ACT_LENGTH(l) (((l-1) << 16) & FS_ACT_LENGTH_MASK) /* frame active length between 0~255 = 1~256 bits*/
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/* define value of each configuration of register SLOT_SETTING1 */
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#define SLOT_NUM_MASK 0x0000000F
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#define SLOT_SIZE_MASK 0x00003F00
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#define DATA_SIZE_MASK 0x001F0000
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#define FB_OFFSET_MASK 0x1F000000
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#define SLOT_NUM(l) (((l-1) << 0) & SLOT_NUM_MASK)
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#define SLOT_SIZE(l) (((l-1) << 8) & SLOT_SIZE_MASK)
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#define DATA_SIZE(l) (((l-1) << 16) & DATA_SIZE_MASK)
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#define FB_OFFSET(l) ((l << 24) & FB_OFFSET_MASK)
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/* define value of each configuration of register DATA_FORMAT */
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#define WORD_LENGTH_MASK 0x00000006
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#define WORD_LEN_8 0x0 << 1
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#define WORD_LEN_16 0x1 << 1
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#define WORD_LEN_32 0x2 << 1
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/* define value of each configuration of register BLK_CFG */
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#define AUTO_DISABLE_W_CH_EN 0x1 << 4
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#define RX_START_WAIT_DMA_EN 0x1 << 6
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/* define value of each configuration of register I2S_RESET */
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#define I2S_RESET_RX_PULL_UP 0x00000001
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#define I2S_RESET_RX_PULL_DOWN 0x00000000
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#define I2S_RESET_TX_PULL_UP 0x00000002
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#define I2S_RESET_TX_PULL_DOWN 0x00000000
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/* define value of each configuration of register I2S_INT_EN */
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#define I2S_INT_EN_ALL 0x00000177
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/* define value of each configuration of register I2S_INT */
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#define I2S_INT_RXDA 0x1 << 0 /* RX FIFO data available interrupt status */
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#define I2S_INT_RXFO 0x1 << 1 /* RX FIFO overflow interrupt status */
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#define I2S_INT_RXFU 0x1 << 2 /* RX FIFO underflow interrupt status */
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#define I2S_INT_TXDA 0x1 << 4 /* RX FIFO data available interrupt status */
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#define I2S_INT_TXFO 0x1 << 5 /* RX FIFO overflow interrupt status */
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#define I2S_INT_TXFU 0x1 << 6 /* RX FIFO underflow interrupt status */
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#define I2S_INT_RXDA_RAW 0x1 << 8 /* RX FIFO data available interrupt raw status */
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#define I2S_INT_RXFO_RAW 0x1 << 9 /* RX FIFO overflow interrupt raw status */
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#define I2S_INT_RXFU_RAW 0x1 << 10 /* RX FIFO underflow interrupt raw status */
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#define I2S_INT_TXDA_RAW 0x1 << 12 /* RX FIFO data available interrupt raw status */
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#define I2S_INT_TXFO_RAW 0x1 << 13 /* RX FIFO overflow interrupt raw status */
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#define I2S_INT_TXFU_RAW 0x1 << 14 /* RX FIFO underflow interrupt raw status */
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/* define value of each configuration of register FIFO_THRESHOLD */
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#define RX_FIFO_THRESHOLD_MASK 0x0000001F
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#define TX_FIFO_THRESHOLD_MASK 0x001F0000
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#define TX_FIFO_HIGH_THRESHOLD_MASK 0x1F000000
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#define RX_FIFO_THRESHOLD(v) ((v << 0) & RX_FIFO_THRESHOLD_MASK)
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#define TX_FIFO_THRESHOLD(v) ((v << 16) & TX_FIFO_THRESHOLD_MASK)
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#define TX_FIFO_HIGH_THRESHOLD(v) ((v << 24) & TX_FIFO_HIGH_THRESHOLD_MASK)
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/* define value of each configuration of register FIFO_RESET */
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#define RX_FIFO_RESET_PULL_UP 0x00000001
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#define RX_FIFO_RESET_PULL_DOWN 0x00000000
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#define TX_FIFO_RESET_PULL_UP 0x00010000
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#define TX_FIFO_RESET_PULL_DOWN 0x00000000
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/* define value of each configuration of register RX_STATUS */
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#define RESET_RX_SCLK 0x00800000
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/* define value of each configuration of register TX_STATUS */
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#define RESET_TX_SCLK 0x00800000
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/* define value of each configuration of register CLK_CTRL0 */
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#define AUD_CLK_SOURCE_MASK 0x00000001
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#define AUD_SWITCH 0x00000100
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#define AUD_CLK_FROM_PLL 0x0 << 0
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#define AUD_CLK_FROM_MCLK_IN 0x1 << 0
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#define ADU_BCLK_OUT_EN 0x1 << 6
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#define AUD_MCLK_OUT_EN 0x1 << 7
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#define AUD_DISABLE 0x0 << 8
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#define AUD_ENABLE 0x1 << 8
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/* define value of each configuration of register CLK_CTRL1 */
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#define MCLK_DIV(l) ((l << 0) & 0x0000FFFF)
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#define BCLK_DIV(l) ((l << 16) & 0xFFFF0000)
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#define FMT_IB_NF 0 /* sample at falling edge and sync polarity is active low*/
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#define FMT_IB_IF 1
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#define FMT_NB_NF 2
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#define FMT_NB_IF 3
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#define I2S_ON 1
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#define I2S_OFF 0
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/* I2S Tx Control */
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#define I2S_TX_ON 1
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#define I2S_TX_OFF 0
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/* I2S Rx Control */
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#define I2S_RX_ON 1
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#define I2S_RX_OFF 0
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#define WSS_16_CLKCYCLE 0x20
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#define WSS_24_CLKCYCLE 0x30
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#define WSS_32_CLKCYCLE 0x40
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#define WSS_256_CLKCYCLE 0x200
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#define AUD_SRC_EN 0x1 << 0
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#define AUD_SRC_OFF 0x0 << 0
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#define AUD_SRC_FSI(v) ((v << 0) & 0x000003FF)
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#define AUD_SRC_FSO(v) ((v << 16) & 0x03FF0000)
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/* This structure stores the i2s related information */
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struct i2stx_info {
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unsigned int rfs; /* LR clock frame size */
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unsigned int sclkg; /* sclk gate */
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/* unsigned int audio_pll_clk;*/ /* Audio pll frequency in Hz */
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unsigned int samplingrate; /* sampling rate */
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unsigned int mclk_out_en;
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unsigned int clk_src;
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unsigned int bitspersample; /* bits per sample */
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unsigned int channels; /* audio channels */
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struct i2s_tdm_regs *base_address; /* I2S Register Base */
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struct i2s_sys_regs *sys_base_address;
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unsigned int id; /* I2S controller id */
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unsigned char role; /* Master mode or slave mode*/
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unsigned char slot_no;
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unsigned int inv; /* Normal or invert BCLK, normal or invert WS CLK (FSYNC)*/
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unsigned char aud_mode; /*I2S mode, Left justified mode or Right justified mode*/
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u16 mclk_div;
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u16 bclk_div;
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u16 sync_div;
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};
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struct i2s_tdm_regs *i2s_get_base(unsigned int i2s_no);
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struct i2s_sys_regs *i2s_get_sys_base(void);
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// void i2s_set_clk_source(struct i2s_tdm_regs *i2s_reg, unsigned int src);
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// void i2s_set_mclk_out_enable(struct i2s_tdm_regs *i2s_reg, unsigned int enable);
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// void i2s_set_sample_rate(struct i2s_tdm_regs *i2s_reg, unsigned int sample_rate);
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// void i2s_set_ws_clock_cycle(struct i2s_tdm_regs *i2s_reg, unsigned int ws_clk, u8 aud_mode);
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// void i2s_set_resolution(struct i2s_tdm_regs *i2s_reg, unsigned int data_size, unsigned int slot_size);
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// int i2s_set_fmt(struct i2s_tdm_regs *i2s_reg,
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// unsigned char role,
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// unsigned char aud_mode,
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// unsigned int fmt,
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// unsigned char slot_no);
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// int i2s_init(struct i2stx_info *pi2s_tx, unsigned int *data);
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// void i2s_loop_test(struct i2stx_info *pi2s_tx, unsigned int sec, unsigned int *data);
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// void i2s_pdm_loop_test(struct i2stx_info *pi2s_tx, unsigned int sec, unsigned int *data);
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// void i2s_src_test(struct i2stx_info *pi2s_tx);
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// int i2s_test_rx(struct i2stx_info *pi2s_tx, unsigned int resolution);
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// int i2s_receive_rx_data(struct i2stx_info *pi2s_tx, unsigned int *data);
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// int i2s_transfer_tx_data(struct i2stx_info *pi2s_tx, unsigned int *data, unsigned long data_size);
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// void concurrent_rx(void);
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#endif /* __CVI_I2S_H_ */
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