0545e9dc6d
commit d1edce71135cc6d98c0a4b5729774542b676e769 Author: sophgo-forum-service <forum_service@sophgo.com> Date: Fri Mar 15 16:07:33 2024 +0800 [fix] recommend using ssh method to clone repo. [fix] fix sensor driver repo branch name.
362 lines
9.5 KiB
C
362 lines
9.5 KiB
C
/*
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* CVITEK PHY drivers
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* Copyright 2020 CVITEK, Inc.
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*/
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#include <config.h>
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#include <common.h>
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#include <linux/bitops.h>
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#include <phy.h>
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#include "mmio.h"
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#define EPHY_EFUSE_VALID_BIT_BASE 0x03050120
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#define EPHY_EFUSE_TXECHORC_FLAG 0x00000100 // bit 8
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#define EPHY_EFUSE_TXITUNE_FLAG 0x00000200 // bit 9
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#define EPHY_EFUSE_TXRXTERM_FLAG 0x00000800 // bit 11
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#if defined(CVI_ETH_PHY_LOOPBACK)
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static int cv182xa_set_phy_loopback(struct phy_device *phydev, int mode)
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{
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return 0
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}
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#endif
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static void cv182xa_ephy_init(void)
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{
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uint32_t val = 0;
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// set rg_ephy_apb_rw_sel 0x0804@[0]=1/APB by using APB interface
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mmio_write_32(0x03009804, 0x0001);
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/* do this in board.c */
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// // Release 0x0800[0]=0/shutdown
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// mmio_write_32(0x03009800, 0x0900);
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// // Release 0x0800[2]=1/dig_rst_n, Let mii_reg can be accessabile
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// mmio_write_32(0x03009800, 0x0904);
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//mdelay(10);
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// ANA INIT (PD/EN), switch to MII-page5
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mmio_write_32(0x0300907c, 0x0500);
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// Release ANA_PD p5.0x10@[13:8] = 6'b001100
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mmio_write_32(0x03009040, 0x0c00);
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// Release ANA_EN p5.0x10@[7:0] = 8'b01111110
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mmio_write_32(0x03009040, 0x0c7e);
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// Wait PLL_Lock, Lock_Status p5.0x12@[15] = 1
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//mdelay(1);
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// Release 0x0800[1] = 1/ana_rst_n
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mmio_write_32(0x03009800, 0x0906);
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// ANA INIT
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// @Switch to MII-page5
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mmio_write_32(0x0300907c, 0x0500);
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// Efuse register
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// Set Double Bias Current
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//Set rg_eth_txitune1 0x03009064 [15:8]
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//Set rg_eth_txitune0 0x03009064 [7:0]
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if ((mmio_read_32(EPHY_EFUSE_VALID_BIT_BASE) & EPHY_EFUSE_TXITUNE_FLAG) ==
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EPHY_EFUSE_TXITUNE_FLAG) {
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val = ((mmio_read_32(0x03051024) >> 24) & 0xFF) |
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(((mmio_read_32(0x03051024) >> 16) & 0xFF) << 8);
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mmio_clrsetbits_32(0x03009064, 0xFFFF, val);
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} else
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mmio_write_32(0x03009064, 0x5a5a);
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// Set Echo_I
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// Set rg_eth_txechoiadj 0x03009054 [15:8]
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if ((mmio_read_32(EPHY_EFUSE_VALID_BIT_BASE) & EPHY_EFUSE_TXECHORC_FLAG) ==
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EPHY_EFUSE_TXECHORC_FLAG) {
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mmio_clrsetbits_32(0x03009054, 0xFF00, ((mmio_read_32(0x03051024) >> 8) & 0xFF) << 8);
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} else
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mmio_write_32(0x03009054, 0x0000);
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//Set TX_Rterm & Echo_RC_Delay
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// Set rg_eth_txrterm_p1 0x03009058 [11:8]
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// Set rg_eth_txrterm 0x03009058 [7:4]
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// Set rg_eth_txechorcadj 0x03009058 [3:0]
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if ((mmio_read_32(EPHY_EFUSE_VALID_BIT_BASE) & EPHY_EFUSE_TXRXTERM_FLAG) ==
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EPHY_EFUSE_TXRXTERM_FLAG) {
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val = (((mmio_read_32(0x03051020) >> 28) & 0xF) << 4) |
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(((mmio_read_32(0x03051020) >> 24) & 0xF) << 8);
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mmio_clrsetbits_32(0x03009058, 0xFF0, val);
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} else
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mmio_write_32(0x03009058, 0x0bb0);
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// ETH_100BaseT
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// Set Rise update
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mmio_write_32(0x0300905c, 0x0c10);
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// Set Falling phase
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mmio_write_32(0x03009068, 0x0003);
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// Set Double TX Bias Current
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mmio_write_32(0x03009054, 0x0000);
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// Switch to MII-page16
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mmio_write_32(0x0300907c, 0x1000);
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// Set MLT3 Positive phase code, Set MLT3 +0
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mmio_write_32(0x03009068, 0x1000);
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mmio_write_32(0x0300906c, 0x3020);
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mmio_write_32(0x03009070, 0x5040);
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mmio_write_32(0x03009074, 0x7060);
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// Set MLT3 +I
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mmio_write_32(0x03009058, 0x1708);
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mmio_write_32(0x0300905c, 0x3827);
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mmio_write_32(0x03009060, 0x5748);
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mmio_write_32(0x03009064, 0x7867);
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// Switch to MII-page17
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mmio_write_32(0x0300907c, 0x1100);
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// Set MLT3 Negative phase code, Set MLT3 -0
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mmio_write_32(0x03009040, 0x9080);
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mmio_write_32(0x03009044, 0xb0a0);
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mmio_write_32(0x03009048, 0xd0c0);
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mmio_write_32(0x0300904c, 0xf0e0);
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// Set MLT3 -I
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mmio_write_32(0x03009050, 0x9788);
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mmio_write_32(0x03009054, 0xb8a7);
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mmio_write_32(0x03009058, 0xd7c8);
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mmio_write_32(0x0300905c, 0xf8e7);
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// @Switch to MII-page5
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mmio_write_32(0x0300907c, 0x0500);
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// En TX_Rterm
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mmio_write_32(0x03009040, (0x0001 | mmio_read_32(0x03009040)));
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// change rx vcm
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mmio_write_32(0x0300904c, (0x820 | mmio_read_32(0x0300904c)));
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// Link Pulse
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// Switch to MII-page10
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mmio_write_32(0x0300907c, 0x0a00);
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#if 1
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// Set Link Pulse
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mmio_write_32(0x03009040, 0x3e00);
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mmio_write_32(0x03009044, 0x7864);
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mmio_write_32(0x03009048, 0x6470);
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mmio_write_32(0x0300904c, 0x5f62);
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mmio_write_32(0x03009050, 0x5a5a);
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mmio_write_32(0x03009054, 0x5458);
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mmio_write_32(0x03009058, 0xb23a);
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mmio_write_32(0x0300905c, 0x94a0);
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mmio_write_32(0x03009060, 0x9092);
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mmio_write_32(0x03009064, 0x8a8e);
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mmio_write_32(0x03009068, 0x8688);
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mmio_write_32(0x0300906c, 0x8484);
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mmio_write_32(0x03009070, 0x0082);
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#else
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// from sean
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// Fix err: the status is still linkup when removed the network cable.
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mmio_write_32(0x03009040, 0x2000);
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mmio_write_32(0x03009044, 0x3832);
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mmio_write_32(0x03009048, 0x3132);
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mmio_write_32(0x0300904c, 0x2d2f);
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mmio_write_32(0x03009050, 0x2c2d);
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mmio_write_32(0x03009054, 0x1b2b);
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mmio_write_32(0x03009058, 0x94a0);
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mmio_write_32(0x0300905c, 0x8990);
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mmio_write_32(0x03009060, 0x8788);
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mmio_write_32(0x03009064, 0x8485);
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mmio_write_32(0x03009068, 0x8283);
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mmio_write_32(0x0300906c, 0x8182);
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mmio_write_32(0x03009070, 0x0081);
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#endif
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// TP_IDLE
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// Switch to MII-page11
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mmio_write_32(0x0300907c, 0x0b00);
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// Set TP_IDLE
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mmio_write_32(0x03009040, 0x5252);
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mmio_write_32(0x03009044, 0x5252);
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mmio_write_32(0x03009048, 0x4B52);
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mmio_write_32(0x0300904c, 0x3D47);
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mmio_write_32(0x03009050, 0xAA99);
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mmio_write_32(0x03009054, 0x989E);
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mmio_write_32(0x03009058, 0x9395);
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mmio_write_32(0x0300905C, 0x9091);
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mmio_write_32(0x03009060, 0x8E8F);
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mmio_write_32(0x03009064, 0x8D8E);
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mmio_write_32(0x03009068, 0x8C8C);
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mmio_write_32(0x0300906C, 0x8B8B);
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mmio_write_32(0x03009070, 0x008A);
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// ETH 10BaseT Data
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// Switch to MII-page13
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mmio_write_32(0x0300907c, 0x0d00);
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mmio_write_32(0x03009040, 0x1E0A);
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mmio_write_32(0x03009044, 0x3862);
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mmio_write_32(0x03009048, 0x1E62);
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mmio_write_32(0x0300904c, 0x2A08);
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mmio_write_32(0x03009050, 0x244C);
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mmio_write_32(0x03009054, 0x1A44);
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mmio_write_32(0x03009058, 0x061C);
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// Switch to MII-page14
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mmio_write_32(0x0300907c, 0x0e00);
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mmio_write_32(0x03009040, 0x2D30);
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mmio_write_32(0x03009044, 0x3470);
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mmio_write_32(0x03009048, 0x0648);
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mmio_write_32(0x0300904c, 0x261C);
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mmio_write_32(0x03009050, 0x3160);
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mmio_write_32(0x03009054, 0x2D5E);
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// Switch to MII-page15
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mmio_write_32(0x0300907c, 0x0f00);
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mmio_write_32(0x03009040, 0x2922);
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mmio_write_32(0x03009044, 0x366E);
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mmio_write_32(0x03009048, 0x0752);
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mmio_write_32(0x0300904c, 0x2556);
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mmio_write_32(0x03009050, 0x2348);
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mmio_write_32(0x03009054, 0x0C30);
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// Switch to MII-page16
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mmio_write_32(0x0300907c, 0x1000);
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mmio_write_32(0x03009040, 0x1E08);
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mmio_write_32(0x03009044, 0x3868);
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mmio_write_32(0x03009048, 0x1462);
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mmio_write_32(0x0300904c, 0x1A0E);
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mmio_write_32(0x03009050, 0x305E);
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mmio_write_32(0x03009054, 0x2F62);
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// LED PAD MUX
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// mmio_write_32(0x030010e0, 0x05);
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// mmio_write_32(0x030010e4, 0x05);
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// //(SD1_CLK selphy)
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// mmio_write_32(0x050270b0, 0x11111111);
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// //(SD1_CMD selphy)
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// mmio_write_32(0x050270b4, 0x11111111);
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// LED
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// Switch to MII-page1
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mmio_write_32(0x0300907c, 0x0100);
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// select LED_LNK/SPD/DPX out to LED_PAD
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mmio_write_32(0x03009068, (mmio_read_32(0x03009068) & ~0x0f00));
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/* do this in board.c */
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// // @Switch to MII-page0
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// mmio_write_32(0x0300907c, 0x0000);
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// // PHY_ID
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// mmio_write_32(0x03009008, 0x0043);
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// mmio_write_32(0x0300900c, 0x5649);
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// Switch to MII-page19
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mmio_write_32(0x0300907c, 0x1300);
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mmio_write_32(0x03009058, 0x0012);
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// set agc max/min swing
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mmio_write_32(0x0300905C, 0x6848);
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// Switch to MII-page18
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mmio_write_32(0x0300907c, 0x1200);
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#if IS_ENABLED(CONFIG_TARGET_CVITEK_CV181X)
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/* mars LPF(8, 8, 8, 8) HPF(-8, 50(+32), -36, -8) */
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// lpf
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mmio_write_32(0x03009048, 0x0808);
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mmio_write_32(0x0300904C, 0x0808);
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// hpf
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mmio_write_32(0x03009050, 0x32f8);
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mmio_write_32(0x03009054, 0xf8dc);
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#elif IS_ENABLED(CONFIG_TARGET_CVITEK_CV180X)
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/* phobos LPF:(1 8 23 23 8 1) HPF:(-4,58,-45,8,-5, 0) from sean PPT */
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// lpf
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mmio_write_32(0x03009048, 0x0801);
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mmio_write_32(0x0300904C, 0x1717);
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mmio_write_32(0x0300905C, 0x0108);
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// hpf
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mmio_write_32(0x03009050, 0x3afc);
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mmio_write_32(0x03009054, 0x08d3);
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mmio_write_32(0x03009060, 0x00fb);
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#endif
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// Switch to MII-page0
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mmio_write_32(0x0300907c, 0x0000);
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// EPHY start auto-neg procedure
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mmio_write_32(0x03009800, 0x090e);
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// from jinyu.zhao
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/* EPHY is configured as half-duplex after reset, but we need force full-duplex */
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mmio_write_32(0x03009000, (mmio_read_32(0x03009000) | 0x100));
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// switch to MDIO control by ETH_MAC
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mmio_write_32(0x03009804, 0x0000);
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}
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/* CVITEK cv182xa */
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static int cv182xa_config(struct phy_device *phydev)
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{
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//phy_reset(phydev);
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cv182xa_ephy_init();/* config cvitek cv182xa eth internal phy on ASIC board */
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genphy_config(phydev);
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#if defined(CVI_ETH_PHY_LOOPBACK)
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cv182xa_set_phy_loopback(phydev, LOOPBACK_PCS2MAC);
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#endif
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return 0;
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}
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static int cv182xa_parse_status(struct phy_device *phydev)
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{
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int mii_reg;
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mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR);
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if (mii_reg & (BMSR_100FULL | BMSR_100HALF))
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phydev->speed = SPEED_100;
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else
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phydev->speed = SPEED_10;
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if (mii_reg & (BMSR_10FULL | BMSR_100FULL))
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phydev->duplex = DUPLEX_FULL;
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else
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phydev->duplex = DUPLEX_HALF;
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return 0;
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}
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static int cv182xa_startup(struct phy_device *phydev)
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{
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int ret;
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/* Read the Status (2x to make sure link is right) */
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ret = genphy_update_link(phydev);
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if (ret)
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return ret;
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return cv182xa_parse_status(phydev);
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}
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/* Support for cv182xa PHYs */
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static struct phy_driver cv182xa_driver = {
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.name = "CVITEK CV182XA",
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.uid = 0x00435649,
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.mask = 0xffffffff,
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.features = PHY_BASIC_FEATURES,
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.config = &cv182xa_config,
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.startup = &cv182xa_startup,
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.shutdown = &genphy_shutdown,
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};
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int phy_cvitek_init(void)
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{
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phy_register(&cv182xa_driver);
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return 0;
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}
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