0545e9dc6d
commit d1edce71135cc6d98c0a4b5729774542b676e769 Author: sophgo-forum-service <forum_service@sophgo.com> Date: Fri Mar 15 16:07:33 2024 +0800 [fix] recommend using ssh method to clone repo. [fix] fix sensor driver repo branch name.
166 lines
5.0 KiB
C
Executable File
166 lines
5.0 KiB
C
Executable File
/*
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* Copyright (C) Cvitek Co., Ltd. 2019-2021. All rights reserved.
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*
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* File Name: cvi_spif.h
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*
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* Description: Cvitek SPI NOR flash driver header
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*/
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#ifndef __CVI_SPIF_H__
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#define __CVI_SPIF_H__
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/* spi register definitions */
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#define REG_SPI_CTRL 0x00
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#define REG_SPI_CE_CTRL 0x04
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#define REG_SPI_DLY_CTRL 0x08
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#define REG_SPI_DMMR 0x0C
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#define REG_SPI_TRAN_CSR 0x10
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#define REG_SPI_TRAN_NUM 0x14
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#define REG_SPI_FIFO_PORT 0x18
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#define REG_SPI_FIFO_PT 0x20
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#define REG_SPI_INT_STS 0x28
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#define REG_SPI_INT_EN 0x2C
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#define REG_SPI_OPT 0x30
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/* spi-nor commands */
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#define SPI_CMD_WREN 0x06
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#define SPI_CMD_WRDI 0x04
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#define SPI_CMD_RDID 0x9F
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#define SPI_CMD_RDSR 0x05
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#define SPI_CMD_WRSR 0x01
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#define SPI_CMD_READ 0x03
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#define SPI_CMD_FAST_READ 0x0B
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#define SPI_CMD_PP 0x02
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#define SPI_CMD_SE 0x20
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#define SPI_CMD_BE 0xD8
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#define SPI_CMD_CE 0xC7
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/* spi-nor status register */
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#define SPI_STATUS_WIP BIT(0)
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#define SPI_STATUS_WEL BIT(1)
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#define SPI_STATUS_BP0 BIT(2)
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#define SPI_STATUS_BP1 BIT(3)
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#define SPI_STATUS_BP2 BIT(4)
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#define SPI_STATUS_BP3 BIT(5)
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#define SPI_STATUS_TP BIT(6)
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#define SPI_STATUS_SRWD BIT(7)
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/* register bit definition */
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#define BIT_SPI_CTRL_CPHA BIT(12)
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#define BIT_SPI_CTRL_CPOL BIT(13)
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#define BIT_SPI_CTRL_HOLD_OL BIT(14)
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#define BIT_SPI_CTRL_WP_OL BIT(15)
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#define BIT_SPI_CTRL_FL BIT(16)
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#define BIT_SPI_CTRL_LSBF BIT(20)
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#define BIT_SPI_CTRL_SRST BIT(21)
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#define BIT_SPI_CTRL_SCK_DIV_SHIFT 0
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#define BIT_SPI_CTRL_FRAME_LEN_SHIFT 16
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#define BIT_SPI_CTRL_SCK_DIV_MASK 0x7FF // [10:0]
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#define BIT_SPI_CE_CTRL_CEMANUAL BIT(0)
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#define BIT_SPI_CE_CTRL_CEMANUAL_EN BIT(1)
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#define BIT_SPI_DMMR_EN BIT(0)
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#define BIT_SPI_TRAN_CSR_TRAN_MODE_RX BIT(0)
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#define BIT_SPI_TRAN_CSR_TRAN_MODE_TX BIT(1)
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#define BIT_SPI_TRAN_CSR_CNTNS_READ BIT(2)
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#define BIT_SPI_TRAN_CSR_FAST_MODE BIT(3)
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#define BIT_SPI_TRAN_CSR_BUS_WIDTH_1_BIT 0x0
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#define BIT_SPI_TRAN_CSR_BUS_WIDTH_2_BIT 0x10
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#define BIT_SPI_TRAN_CSR_BUS_WIDTH_4_BIT 0x20
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#define BIT_SPI_TRAN_CSR_DMA_EN BIT(6)
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#define BIT_SPI_TRAN_CSR_MISO_LEVEL BIT(7)
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#define BIT_SPI_TRAN_CSR_ADDR_BYTES_NO_ADDR 0
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#define BIT_SPI_TRAN_CSR_WITH_CMD BIT(11)
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#define BIT_SPI_TRAN_CSR_FIFO_TRG_LVL_1_BYTE 0x0
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#define BIT_SPI_TRAN_CSR_FIFO_TRG_LVL_2_BYTE 0x1000
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#define BIT_SPI_TRAN_CSR_FIFO_TRG_LVL_4_BYTE 0x2000
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#define BIT_SPI_TRAN_CSR_FIFO_TRG_LVL_8_BYTE 0x3000
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#define BIT_SPI_TRAN_CSR_GO_BUSY BIT(15)
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#define BIT_SPI_TRAN_CSR_TRAN_MODE_MASK 0x3
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#define BIT_SPI_TRAN_CSR_BUS_WIDTH_MASK 0x30
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#define BIT_SPI_TRAN_CSR_ADDR_BYTES_MASK 0x700
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#define BIT_SPI_TRAN_CSR_FIFO_TRG_LVL_MASK 0x3000
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#define BIT_SPI_TRAN_CSR_DUMMY_MASK 0xF0000
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#define BIT_SPI_TRAN_CSR_4BADDR_MASK BIT(20)
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#define BIT_SPI_TRAN_CSR_4BCMD_MASK BIT(21)
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#define BIT_SPI_DLY_CTRL_CET (3 << 8)
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#define BIT_SPI_DLY_CTRL_NEG_SAMPLE BIT(14)
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#define BIT_SPI_INT_TRAN_DONE BIT(0)
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#define BIT_SPI_INT_RD_FIFO BIT(2)
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#define BIT_SPI_INT_WR_FIFO BIT(3)
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#define BIT_SPI_INT_RX_FRAME BIT(4)
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#define BIT_SPI_INT_TX_FRAME BIT(5)
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#define BIT_SPI_INT_TRAN_DONE_EN BIT(0)
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#define BIT_SPI_INT_RD_FIFO_EN BIT(2)
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#define BIT_SPI_INT_WR_FIFO_EN BIT(3)
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#define BIT_SPI_INT_RX_FRAME_EN BIT(4)
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#define BIT_SPI_INT_TX_FRAME_EN BIT(5)
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/* general definition */
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#define SPI_FLASH_BLOCK_SIZE 256
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#define SPI_TRAN_CSR_ADDR_BYTES_SHIFT 8
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#define SPI_MAX_FIFO_DEPTH 8
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#define SPI_CLK_75M 1
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#define SPI_CLK_50M 2
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#define SPI_CLK_37M 3
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#define SPI_CLK_30M 4
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#define SPI_CLK_15M 9
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#define CLK_1MHZ 1000000
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/* struct */
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struct cvi_spif_regs {
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unsigned int spi_ctrl; /* 0x00 */
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unsigned int ce_ctrl; /* 0x04 */
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unsigned int dly_ctrl; /* 0x08 */
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unsigned int dmmr; /* 0x0C */
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unsigned int tran_csr; /* 0x10 */
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unsigned int tran_num; /* 0x14 */
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unsigned int ff_port; /* 0x18 */
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unsigned int rsvd; /* 0x1C */
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unsigned int ff_pt; /* 0x20 */
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unsigned int rsvd1; /* 0x24 */
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unsigned int int_sts; /* 0x28 */
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unsigned int int_en; /* 0x2C */
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};
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struct cvitek_spi_priv {
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unsigned long ctrl_base;
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unsigned int freq;
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unsigned int mode;
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unsigned int sck_div;
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unsigned int sck;
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struct cvi_spif_regs *regs;
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unsigned int max_hz;
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unsigned int orig_tran_csr;
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#define CMD_HAS_ADR BIT(24)
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#define CMD_HAS_DUMMY BIT(25)
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#define CMD_HAS_DATA BIT(26)
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};
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struct dmmr_reg_t {
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uint8_t read_cmd;
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uint32_t dummy_clock;
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uint32_t reg_set;
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};
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const struct dmmr_reg_t dmmr_reg_set[16] = {
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{0x03, 0x0, 0x003B81},
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{0x0B, 0x8, 0x003B89},
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{0x3B, 0x8, 0x003B91},
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{0xBB, 0x4, 0x003B99},
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{0x6B, 0x8, 0x003BA1},
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{0xEB, 0x6, 0x003BA9},
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{0x13, 0x0, 0x303C81},
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{0x0C, 0x8, 0x303C89},
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{0x3C, 0x8, 0x303C91},
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{0xBC, 0x4, 0x303C99},
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{0x6C, 0x8, 0x303CA1},
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{0xEC, 0x6, 0x303CA9},
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{0x0, 0x0, 0x0}
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};
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#endif /* __CVI_SPIF_H__ */
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