0545e9dc6d
commit d1edce71135cc6d98c0a4b5729774542b676e769 Author: sophgo-forum-service <forum_service@sophgo.com> Date: Fri Mar 15 16:07:33 2024 +0800 [fix] recommend using ssh method to clone repo. [fix] fix sensor driver repo branch name.
129 lines
3.2 KiB
C
129 lines
3.2 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2017 SiFive
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*/
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#include <asm/cacheflush.h>
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#include <asm/sbi.h>
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#ifdef CONFIG_SMP
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static void ipi_remote_fence_i(void *info)
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{
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return local_flush_icache_all();
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}
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void flush_icache_all(void)
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{
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if (IS_ENABLED(CONFIG_RISCV_SBI))
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sbi_remote_fence_i(NULL);
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else
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on_each_cpu(ipi_remote_fence_i, NULL, 1);
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}
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EXPORT_SYMBOL(flush_icache_all);
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/*
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* Performs an icache flush for the given MM context. RISC-V has no direct
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* mechanism for instruction cache shoot downs, so instead we send an IPI that
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* informs the remote harts they need to flush their local instruction caches.
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* To avoid pathologically slow behavior in a common case (a bunch of
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* single-hart processes on a many-hart machine, ie 'make -j') we avoid the
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* IPIs for harts that are not currently executing a MM context and instead
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* schedule a deferred local instruction cache flush to be performed before
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* execution resumes on each hart.
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*/
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void flush_icache_mm(struct mm_struct *mm, bool local)
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{
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unsigned int cpu;
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cpumask_t others, *mask;
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preempt_disable();
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/* Mark every hart's icache as needing a flush for this MM. */
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mask = &mm->context.icache_stale_mask;
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cpumask_setall(mask);
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/* Flush this hart's I$ now, and mark it as flushed. */
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cpu = smp_processor_id();
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cpumask_clear_cpu(cpu, mask);
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local_flush_icache_all();
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/*
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* Flush the I$ of other harts concurrently executing, and mark them as
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* flushed.
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*/
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cpumask_andnot(&others, mm_cpumask(mm), cpumask_of(cpu));
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local |= cpumask_empty(&others);
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if (mm == current->active_mm && local) {
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/*
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* It's assumed that at least one strongly ordered operation is
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* performed on this hart between setting a hart's cpumask bit
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* and scheduling this MM context on that hart. Sending an SBI
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* remote message will do this, but in the case where no
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* messages are sent we still need to order this hart's writes
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* with flush_icache_deferred().
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*/
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smp_mb();
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} else if (IS_ENABLED(CONFIG_RISCV_SBI)) {
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cpumask_t hartid_mask;
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riscv_cpuid_to_hartid_mask(&others, &hartid_mask);
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sbi_remote_fence_i(cpumask_bits(&hartid_mask));
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} else {
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on_each_cpu_mask(&others, ipi_remote_fence_i, NULL, 1);
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}
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preempt_enable();
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}
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#endif /* CONFIG_SMP */
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#ifdef CONFIG_MMU
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void flush_icache_pte(pte_t pte)
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{
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struct page *page = pte_page(pte);
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if (!test_and_set_bit(PG_dcache_clean, &page->flags))
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flush_icache_all();
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}
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#endif /* CONFIG_MMU */
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static bool thead_dma_init_flag = false;
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#define sync_is() asm volatile (".long 0x01b0000b")
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void dma_wbinv_range(unsigned long start, unsigned long end)
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{
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register unsigned long i asm("a0") = start & ~(L1_CACHE_BYTES - 1);
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if (!thead_dma_init_flag)
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return;
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for (; i < end; i += L1_CACHE_BYTES)
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asm volatile (".long 0x02b5000b"); /* dcache.cipa a0 */
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sync_is();
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}
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void dma_wb_range(unsigned long start, unsigned long end)
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{
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register unsigned long i asm("a0") = start & ~(L1_CACHE_BYTES - 1);
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if (!thead_dma_init_flag)
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return;
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for (; i < end; i += L1_CACHE_BYTES)
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asm volatile (".long 0x0295000b"); /* dcache.cpa a0 */
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sync_is();
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}
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#define THEAD_VENDOR_ID 0x5b7
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static int __init thead_dma_init(void)
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{
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if (sbi_get_mvendorid() == THEAD_VENDOR_ID)
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thead_dma_init_flag = true;
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return 0;
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}
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arch_initcall(thead_dma_init);
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