0545e9dc6d
commit d1edce71135cc6d98c0a4b5729774542b676e769 Author: sophgo-forum-service <forum_service@sophgo.com> Date: Fri Mar 15 16:07:33 2024 +0800 [fix] recommend using ssh method to clone repo. [fix] fix sensor driver repo branch name.
454 lines
17 KiB
C
454 lines
17 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* CVITEK CV182X thermal driver
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*
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* Copyright 2021 CVITEK Inc.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <linux/thermal.h>
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#include <linux/types.h>
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#define tempsen_top_tempsen_version 0x0
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#define tempsen_top_tempsen_ctrl 0x4
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#define tempsen_top_tempsen_status 0x8
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#define tempsen_top_tempsen_set 0xc
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#define tempsen_top_tempsen_intr_en 0x10
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#define tempsen_top_tempsen_intr_clr 0x14
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#define tempsen_top_tempsen_intr_sta 0x18
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#define tempsen_top_tempsen_intr_raw 0x1c
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#define tempsen_top_tempsen_ch0_result 0x20
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#define tempsen_top_tempsen_ch1_result 0x24
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#define tempsen_top_tempsen_ch2_result 0x28
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#define tempsen_top_tempsen_ch3_result 0x2c
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#define tempsen_top_tempsen_ch0_temp_th 0x40
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#define tempsen_top_tempsen_ch1_temp_th 0x44
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#define tempsen_top_tempsen_ch2_temp_th 0x48
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#define tempsen_top_tempsen_ch3_temp_th 0x4c
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#define tempsen_top_Overheat_th 0x60
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#define tempsen_top_tempsen_auto_cycle 0x64
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#define tempsen_top_tempsen_auto_prediv 0x64
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#define tempsen_top_tempsen_overheat_ctrl 0x68
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#define tempsen_top_tempsen_overheat_countdown 0x6c
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#define tempsen_top_tempsen_ch0_temp_th_cnt 0x70
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#define tempsen_top_tempsen_ch1_temp_th_cnt 0x74
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#define tempsen_top_tempsen_ch2_temp_th_cnt 0x78
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#define tempsen_top_tempsen_ch3_temp_th_cnt 0x7c
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#define tempsen_top_tempsen_test_force 0x80
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#define tempsen_top_reg_ip_version 0x0
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#define tempsen_top_reg_ip_version_OFFSET 0
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#define tempsen_top_reg_ip_version_MASK 0xffffffff
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#define tempsen_top_reg_tempsen_en 0x4
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#define tempsen_top_reg_tempsen_en_OFFSET 0
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#define tempsen_top_reg_tempsen_en_MASK 0x1
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#define tempsen_top_reg_tempsen_sel 0x4
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#define tempsen_top_reg_tempsen_sel_OFFSET 4
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#define tempsen_top_reg_tempsen_sel_MASK 0xf0
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#define tempsen_top_reg_tempsen_ovhl_cnt_to_irq 0x4
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#define tempsen_top_reg_tempsen_ovhl_cnt_to_irq_OFFSET 16
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#define tempsen_top_reg_tempsen_ovhl_cnt_to_irq_MASK 0xff0000
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#define tempsen_top_reg_tempsen_udll_cnt_to_irq 0x4
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#define tempsen_top_reg_tempsen_udll_cnt_to_irq_OFFSET 24
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#define tempsen_top_reg_tempsen_udll_cnt_to_irq_MASK 0xff000000
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#define tempsen_top_sta_tempsen_busy 0x8
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#define tempsen_top_sta_tempsen_busy_OFFSET 0
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#define tempsen_top_sta_tempsen_busy_MASK 0x1
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#define tempsen_top_reg_tempsen_bgen 0xc
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#define tempsen_top_reg_tempsen_bgen_OFFSET 0
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#define tempsen_top_reg_tempsen_bgen_MASK 0x1
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#define tempsen_top_reg_tempsen_chopen 0xc
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#define tempsen_top_reg_tempsen_chopen_OFFSET 1
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#define tempsen_top_reg_tempsen_chopen_MASK 0x2
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#define tempsen_top_reg_tempsen_choppol 0xc
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#define tempsen_top_reg_tempsen_choppol_OFFSET 2
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#define tempsen_top_reg_tempsen_choppol_MASK 0x4
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#define tempsen_top_reg_tempsen_clkpol 0xc
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#define tempsen_top_reg_tempsen_clkpol_OFFSET 3
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#define tempsen_top_reg_tempsen_clkpol_MASK 0x8
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#define tempsen_top_reg_tempsen_chopsel 0xc
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#define tempsen_top_reg_tempsen_chopsel_OFFSET 4
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#define tempsen_top_reg_tempsen_chopsel_MASK 0x30
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#define tempsen_top_reg_tempsen_accsel 0xc
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#define tempsen_top_reg_tempsen_accsel_OFFSET 6
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#define tempsen_top_reg_tempsen_accsel_MASK 0xc0
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#define tempsen_top_reg_tempsen_cyc_clkdiv 0xc
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#define tempsen_top_reg_tempsen_cyc_clkdiv_OFFSET 8
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#define tempsen_top_reg_tempsen_cyc_clkdiv_MASK 0xff00
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#define tempsen_top_reg_tempsen_tsel 0xc
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#define tempsen_top_reg_tempsen_tsel_OFFSET 16
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#define tempsen_top_reg_tempsen_tsel_MASK 0x30000
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#define tempsen_top_sta_tempsen_intr_en 0x10
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#define tempsen_top_sta_tempsen_intr_en_OFFSET 0
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#define tempsen_top_sta_tempsen_intr_en_MASK 0xffffffff
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#define tempsen_top_sta_tempsen_intr_clr 0x14
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#define tempsen_top_sta_tempsen_intr_clr_OFFSET 0
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#define tempsen_top_sta_tempsen_intr_clr_MASK 0xffffffff
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#define tempsen_top_sta_tempsen_intr_sta 0x18
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#define tempsen_top_sta_tempsen_intr_sta_OFFSET 0
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#define tempsen_top_sta_tempsen_intr_sta_MASK 0xffffffff
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#define tempsen_top_sta_tempsen_intr_raw 0x1c
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#define tempsen_top_sta_tempsen_intr_raw_OFFSET 0
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#define tempsen_top_sta_tempsen_intr_raw_MASK 0xffffffff
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#define tempsen_top_sta_tempsen_ch0_result 0x20
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#define tempsen_top_sta_tempsen_ch0_result_OFFSET 0
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#define tempsen_top_sta_tempsen_ch0_result_MASK 0x1fff
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#define tempsen_top_sta_tempsen_ch0_max_result 0x20
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#define tempsen_top_sta_tempsen_ch0_max_result_OFFSET 16
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#define tempsen_top_sta_tempsen_ch0_max_result_MASK 0x1fff0000
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#define tempsen_top_clr_tempsen_ch0_max_result 0x20
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#define tempsen_top_clr_tempsen_ch0_max_result_OFFSET 31
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#define tempsen_top_clr_tempsen_ch0_max_result_MASK 0x80000000
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#define tempsen_top_sta_tempsen_ch1_result 0x24
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#define tempsen_top_sta_tempsen_ch1_result_OFFSET 0
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#define tempsen_top_sta_tempsen_ch1_result_MASK 0x1fff
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#define tempsen_top_sta_tempsen_ch1_max_result 0x24
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#define tempsen_top_sta_tempsen_ch1_max_result_OFFSET 16
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#define tempsen_top_sta_tempsen_ch1_max_result_MASK 0x1fff0000
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#define tempsen_top_clr_tempsen_ch1_max_result 0x24
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#define tempsen_top_clr_tempsen_ch1_max_result_OFFSET 31
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#define tempsen_top_clr_tempsen_ch1_max_result_MASK 0x80000000
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#define tempsen_top_sta_tempsen_ch2_result 0x28
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#define tempsen_top_sta_tempsen_ch2_result_OFFSET 0
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#define tempsen_top_sta_tempsen_ch2_result_MASK 0x1fff
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#define tempsen_top_sta_tempsen_ch2_max_result 0x28
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#define tempsen_top_sta_tempsen_ch2_max_result_OFFSET 16
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#define tempsen_top_sta_tempsen_ch2_max_result_MASK 0x1fff0000
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#define tempsen_top_clr_tempsen_ch2_max_result 0x28
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#define tempsen_top_clr_tempsen_ch2_max_result_OFFSET 31
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#define tempsen_top_clr_tempsen_ch2_max_result_MASK 0x80000000
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#define tempsen_top_sta_tempsen_ch3_result 0x2c
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#define tempsen_top_sta_tempsen_ch3_result_OFFSET 0
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#define tempsen_top_sta_tempsen_ch3_result_MASK 0x1fff
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#define tempsen_top_sta_tempsen_ch3_max_result 0x2c
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#define tempsen_top_sta_tempsen_ch3_max_result_OFFSET 16
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#define tempsen_top_sta_tempsen_ch3_max_result_MASK 0x1fff0000
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#define tempsen_top_clr_tempsen_ch3_max_result 0x2c
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#define tempsen_top_clr_tempsen_ch3_max_result_OFFSET 31
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#define tempsen_top_clr_tempsen_ch3_max_result_MASK 0x80000000
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#define tempsen_top_reg_tempsen_ch0_hi_th 0x40
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#define tempsen_top_reg_tempsen_ch0_hi_th_OFFSET 0
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#define tempsen_top_reg_tempsen_ch0_hi_th_MASK 0x1fff
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#define tempsen_top_reg_tempsen_ch0_lo_th 0x40
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#define tempsen_top_reg_tempsen_ch0_lo_th_OFFSET 16
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#define tempsen_top_reg_tempsen_ch0_lo_th_MASK 0x1fff0000
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#define tempsen_top_reg_tempsen_ch1_hi_th 0x44
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#define tempsen_top_reg_tempsen_ch1_hi_th_OFFSET 0
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#define tempsen_top_reg_tempsen_ch1_hi_th_MASK 0x1fff
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#define tempsen_top_reg_tempsen_ch1_lo_th 0x44
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#define tempsen_top_reg_tempsen_ch1_lo_th_OFFSET 16
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#define tempsen_top_reg_tempsen_ch1_lo_th_MASK 0x1fff0000
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#define tempsen_top_reg_tempsen_ch2_hi_th 0x48
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#define tempsen_top_reg_tempsen_ch2_hi_th_OFFSET 0
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#define tempsen_top_reg_tempsen_ch2_hi_th_MASK 0x1fff
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#define tempsen_top_reg_tempsen_ch2_lo_th 0x48
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#define tempsen_top_reg_tempsen_ch2_lo_th_OFFSET 16
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#define tempsen_top_reg_tempsen_ch2_lo_th_MASK 0x1fff0000
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#define tempsen_top_reg_tempsen_ch3_hi_th 0x4c
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#define tempsen_top_reg_tempsen_ch3_hi_th_OFFSET 0
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#define tempsen_top_reg_tempsen_ch3_hi_th_MASK 0x1fff
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#define tempsen_top_reg_tempsen_ch3_lo_th 0x4c
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#define tempsen_top_reg_tempsen_ch3_lo_th_OFFSET 16
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#define tempsen_top_reg_tempsen_ch3_lo_th_MASK 0x1fff0000
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#define tempsen_top_reg_tempsen_overheat_th 0x60
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#define tempsen_top_reg_tempsen_overheat_th_OFFSET 0
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#define tempsen_top_reg_tempsen_overheat_th_MASK 0x1fff
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#define tempsen_top_reg_tempsen_auto_cycle 0x64
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#define tempsen_top_reg_tempsen_auto_cycle_OFFSET 0
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#define tempsen_top_reg_tempsen_auto_cycle_MASK 0xffffff
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#define tempsen_top_reg_tempsen_auto_prediv 0x64
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#define tempsen_top_reg_tempsen_auto_prediv_OFFSET 24
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#define tempsen_top_reg_tempsen_auto_prediv_MASK 0xff000000
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#define tempsen_top_reg_tempsen_overheat_cycle 0x68
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#define tempsen_top_reg_tempsen_overheat_cycle_OFFSET 0
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#define tempsen_top_reg_tempsen_overheat_cycle_MASK 0x3fffffff
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#define tempsen_top_reg_overheat_reset_clr 0x68
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#define tempsen_top_reg_overheat_reset_clr_OFFSET 30
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#define tempsen_top_reg_overheat_reset_clr_MASK 0x40000000
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#define tempsen_top_reg_overheat_reset_en 0x68
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#define tempsen_top_reg_overheat_reset_en_OFFSET 31
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#define tempsen_top_reg_overheat_reset_en_MASK 0x80000000
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#define tempsen_top_sta_tempsen_overheat_countdown 0x6c
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#define tempsen_top_sta_tempsen_overheat_countdown_OFFSET 0
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#define tempsen_top_sta_tempsen_overheat_countdown_MASK 0x3fffffff
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#define tempsen_top_sta_overheat_reset 0x6c
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#define tempsen_top_sta_overheat_reset_OFFSET 31
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#define tempsen_top_sta_overheat_reset_MASK 0x80000000
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#define tempsen_top_sta_ch0_over_hi_temp_th_cnt 0x70
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#define tempsen_top_sta_ch0_over_hi_temp_th_cnt_OFFSET 0
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#define tempsen_top_sta_ch0_over_hi_temp_th_cnt_MASK 0xff
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#define tempsen_top_sta_ch0_under_lo_temp_th_cnt 0x70
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#define tempsen_top_sta_ch0_under_lo_temp_th_cnt_OFFSET 8
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#define tempsen_top_sta_ch0_under_lo_temp_th_cnt_MASK 0xff00
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#define tempsen_top_reg_ch0_temp_th_cnt_clr 0x70
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#define tempsen_top_reg_ch0_temp_th_cnt_clr_OFFSET 16
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#define tempsen_top_reg_ch0_temp_th_cnt_clr_MASK 0x10000
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#define tempsen_top_sta_ch1_over_hi_temp_th_cnt 0x74
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#define tempsen_top_sta_ch1_over_hi_temp_th_cnt_OFFSET 0
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#define tempsen_top_sta_ch1_over_hi_temp_th_cnt_MASK 0xff
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#define tempsen_top_sta_ch1_under_lo_temp_th_cnt 0x74
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#define tempsen_top_sta_ch1_under_lo_temp_th_cnt_OFFSET 8
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#define tempsen_top_sta_ch1_under_lo_temp_th_cnt_MASK 0xff00
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#define tempsen_top_reg_ch1_temp_th_cnt_clr 0x74
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#define tempsen_top_reg_ch1_temp_th_cnt_clr_OFFSET 16
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#define tempsen_top_reg_ch1_temp_th_cnt_clr_MASK 0x10000
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#define tempsen_top_sta_ch2_over_hi_temp_th_cnt 0x78
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#define tempsen_top_sta_ch2_over_hi_temp_th_cnt_OFFSET 0
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#define tempsen_top_sta_ch2_over_hi_temp_th_cnt_MASK 0xff
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#define tempsen_top_sta_ch2_under_lo_temp_th_cnt 0x78
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#define tempsen_top_sta_ch2_under_lo_temp_th_cnt_OFFSET 8
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#define tempsen_top_sta_ch2_under_lo_temp_th_cnt_MASK 0xff00
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#define tempsen_top_reg_ch2_temp_th_cnt_clr 0x78
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#define tempsen_top_reg_ch2_temp_th_cnt_clr_OFFSET 16
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#define tempsen_top_reg_ch2_temp_th_cnt_clr_MASK 0x10000
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#define tempsen_top_sta_ch3_over_hi_temp_th_cnt 0x7c
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#define tempsen_top_sta_ch3_over_hi_temp_th_cnt_OFFSET 0
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#define tempsen_top_sta_ch3_over_hi_temp_th_cnt_MASK 0xff
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#define tempsen_top_sta_ch3_under_lo_temp_th_cnt 0x7c
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#define tempsen_top_sta_ch3_under_lo_temp_th_cnt_OFFSET 8
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#define tempsen_top_sta_ch3_under_lo_temp_th_cnt_MASK 0xff00
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#define tempsen_top_reg_ch3_temp_th_cnt_clr 0x7c
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#define tempsen_top_reg_ch3_temp_th_cnt_clr_OFFSET 16
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#define tempsen_top_reg_ch3_temp_th_cnt_clr_MASK 0x10000
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#define tempsen_top_reg_tempsen_force_result 0x80
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#define tempsen_top_reg_tempsen_force_result_OFFSET 0
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#define tempsen_top_reg_tempsen_force_result_MASK 0x1fff
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#define tempsen_top_reg_tempsen_force_valid 0x80
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#define tempsen_top_reg_tempsen_force_valid_OFFSET 13
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#define tempsen_top_reg_tempsen_force_valid_MASK 0x2000
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#define tempsen_top_reg_tempsen_force_busy 0x80
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#define tempsen_top_reg_tempsen_force_busy_OFFSET 14
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#define tempsen_top_reg_tempsen_force_busy_MASK 0x4000
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#define tempsen_top_reg_tempsen_force_en 0x80
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#define tempsen_top_reg_tempsen_force_en_OFFSET 15
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#define tempsen_top_reg_tempsen_force_en_MASK 0x8000
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#define TEMPSEN_MASK(REG_NAME) tempsen_top_##REG_NAME##_MASK
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#define TEMPSEN_OFFSET(REG_NAME) tempsen_top_##REG_NAME##_OFFSET
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#define TEMPSEN_SET(BASE_ADDR, REG_NAME, VAL) \
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clrsetbits(BASE_ADDR + tempsen_top_##REG_NAME, \
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TEMPSEN_MASK(REG_NAME), (VAL) << TEMPSEN_OFFSET(REG_NAME))
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#define TEMPSEN_GET(BASE_ADDR, REG_NAME) \
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((readl(BASE_ADDR + tempsen_top_##REG_NAME) & \
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TEMPSEN_MASK(REG_NAME)) >> TEMPSEN_OFFSET(REG_NAME))
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static void __maybe_unused clrsetbits(void __iomem *reg, u32 clrval, u32 setval)
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{
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u32 regval;
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regval = readl(reg);
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regval &= ~(clrval);
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regval |= setval;
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writel(regval, reg);
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}
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struct cv182x_thermal_zone {
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unsigned int ch;
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void __iomem *base;
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struct cv182x_thermal *ct;
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};
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struct cv182x_thermal {
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struct device *dev;
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void __iomem *base;
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struct clk *clk_tempsen;
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};
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static void cv182x_thermal_init(struct cv182x_thermal *ct)
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{
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void __iomem *base = ct->base;
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u32 regval;
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/* clear all interrupt status */
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regval = TEMPSEN_GET(base, sta_tempsen_intr_raw);
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TEMPSEN_SET(base, sta_tempsen_intr_clr, regval);
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/* clear max result */
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TEMPSEN_SET(base, clr_tempsen_ch0_max_result, 1);
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TEMPSEN_SET(base, clr_tempsen_ch1_max_result, 1);
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/* set chop period to 3:1024T */
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TEMPSEN_SET(base, reg_tempsen_chopsel, 0x3);
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/* set acc period to 2:2048T*/
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TEMPSEN_SET(base, reg_tempsen_accsel, 0x2);
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/* set tempsen clock divider to 25M/(0x31+1)= 0.5M ,T=2us */
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TEMPSEN_SET(base, reg_tempsen_cyc_clkdiv, 0x31);
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/* set reg_tempsen_auto_cycle */
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TEMPSEN_SET(base, reg_tempsen_auto_cycle, 0x100000);
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/* enable tempsen channel */
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TEMPSEN_SET(base, reg_tempsen_sel, 0x1);
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TEMPSEN_SET(base, reg_tempsen_en, 1);
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}
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static void cv182x_thermal_uninit(struct cv182x_thermal *ct)
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{
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void __iomem *base = ct->base;
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u32 regval;
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/* disable all tempsen channel */
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TEMPSEN_SET(base, reg_tempsen_sel, 0);
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TEMPSEN_SET(base, reg_tempsen_en, 0);
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/* clear all interrupt status */
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regval = TEMPSEN_GET(base, sta_tempsen_intr_raw);
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TEMPSEN_SET(base, sta_tempsen_intr_clr, regval);
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}
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static int calc_temp(uint32_t result)
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{
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return ((result * 1000) * 716 / 2048 - 273000);
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/* Original calculation formula */
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// return ((result * 1000) / 2048 * 716 - 273000);
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}
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static int cv182x_read_temp(void *data, int *temperature)
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{
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struct cv182x_thermal_zone *ctz = data;
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void __iomem *base = ctz->base;
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unsigned int ch = ctz->ch;
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u32 result;
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|
|
/* read temperature */
|
|
switch (ch) {
|
|
case 0:
|
|
result = TEMPSEN_GET(base, sta_tempsen_ch0_result); break;
|
|
default:
|
|
result = 0;
|
|
}
|
|
*temperature = calc_temp(result);
|
|
pr_debug("ch%d temp = %d mC(0x%x)\n", ch, *temperature, result);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct thermal_zone_of_device_ops cv182x_thermal_ops = {
|
|
.get_temp = cv182x_read_temp,
|
|
};
|
|
|
|
static const struct of_device_id cv182x_thermal_of_match[] = {
|
|
{
|
|
.compatible = "cvitek,cv182x-thermal",
|
|
},
|
|
{},
|
|
};
|
|
MODULE_DEVICE_TABLE(of, cv182x_thermal_of_match);
|
|
|
|
static int cv182x_thermal_probe(struct platform_device *pdev)
|
|
{
|
|
struct cv182x_thermal *ct;
|
|
struct cv182x_thermal_zone *ctz;
|
|
struct resource *res;
|
|
struct thermal_zone_device *tz;
|
|
int i;
|
|
|
|
ct = devm_kzalloc(&pdev->dev, sizeof(*ct), GFP_KERNEL);
|
|
if (!ct)
|
|
return -ENOMEM;
|
|
|
|
ct->clk_tempsen = devm_clk_get(&pdev->dev, "clk_tempsen");
|
|
if (IS_ERR(ct->clk_tempsen)) {
|
|
dev_err(&pdev->dev, "failed to get clk_tempsen\n");
|
|
return PTR_ERR(ct->clk_tempsen);
|
|
}
|
|
|
|
/* enable clk_tempsen */
|
|
clk_prepare_enable(ct->clk_tempsen);
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
ct->base = devm_ioremap_resource(&pdev->dev, res);
|
|
if (IS_ERR(ct->base)) {
|
|
dev_err(&pdev->dev, "failed to map tempsen registers\n");
|
|
return PTR_ERR(ct->base);
|
|
}
|
|
|
|
ct->dev = &pdev->dev;
|
|
|
|
cv182x_thermal_init(ct);
|
|
|
|
platform_set_drvdata(pdev, ct);
|
|
|
|
for (i = 0; i < 1; i++) {
|
|
ctz = devm_kzalloc(&pdev->dev, sizeof(*ctz), GFP_KERNEL);
|
|
if (!ctz)
|
|
return -ENOMEM;
|
|
|
|
ctz->base = ct->base;
|
|
ctz->ct = ct;
|
|
ctz->ch = i;
|
|
tz = devm_thermal_zone_of_sensor_register(&pdev->dev, i, ctz,
|
|
&cv182x_thermal_ops);
|
|
if (IS_ERR(tz)) {
|
|
dev_err(&pdev->dev, "failed to register thermal zone %d\n", i);
|
|
return PTR_ERR(tz);
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int cv182x_thermal_remove(struct platform_device *pdev)
|
|
{
|
|
struct cv182x_thermal *ct = platform_get_drvdata(pdev);
|
|
|
|
cv182x_thermal_uninit(ct);
|
|
|
|
clk_disable_unprepare(ct->clk_tempsen);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
static int cv182x_thermal_suspend(struct device *dev)
|
|
{
|
|
struct cv182x_thermal *ct = dev_get_drvdata(dev);
|
|
|
|
cv182x_thermal_uninit(ct);
|
|
|
|
clk_disable_unprepare(ct->clk_tempsen);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int cv182x_thermal_resume(struct device *dev)
|
|
{
|
|
struct cv182x_thermal *ct = dev_get_drvdata(dev);
|
|
|
|
/* enable clk_tempsen */
|
|
clk_prepare_enable(ct->clk_tempsen);
|
|
|
|
cv182x_thermal_init(ct);
|
|
|
|
return 0;
|
|
}
|
|
#endif /* CONFIG_PM_SLEEP */
|
|
|
|
static SIMPLE_DEV_PM_OPS(cv182x_thermal_pm_ops,
|
|
cv182x_thermal_suspend, cv182x_thermal_resume);
|
|
|
|
static struct platform_driver cv182x_thermal_driver = {
|
|
.probe = cv182x_thermal_probe,
|
|
.remove = cv182x_thermal_remove,
|
|
.driver = {
|
|
.name = "cv182x-thermal",
|
|
.pm = &cv182x_thermal_pm_ops,
|
|
.of_match_table = cv182x_thermal_of_match,
|
|
},
|
|
};
|
|
|
|
module_platform_driver(cv182x_thermal_driver);
|
|
MODULE_DESCRIPTION("CV182X thermal driver");
|