0545e9dc6d
commit d1edce71135cc6d98c0a4b5729774542b676e769 Author: sophgo-forum-service <forum_service@sophgo.com> Date: Fri Mar 15 16:07:33 2024 +0800 [fix] recommend using ssh method to clone repo. [fix] fix sensor driver repo branch name.
107 lines
2.9 KiB
C
107 lines
2.9 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2012 Regents of the University of California
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* Copyright (C) 2017 SiFive
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*/
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#include <linux/mm.h>
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#include <asm/tlbflush.h>
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#include <asm/cacheflush.h>
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#include <asm/mmu_context.h>
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/*
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* When necessary, performs a deferred icache flush for the given MM context,
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* on the local CPU. RISC-V has no direct mechanism for instruction cache
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* shoot downs, so instead we send an IPI that informs the remote harts they
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* need to flush their local instruction caches. To avoid pathologically slow
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* behavior in a common case (a bunch of single-hart processes on a many-hart
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* machine, ie 'make -j') we avoid the IPIs for harts that are not currently
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* executing a MM context and instead schedule a deferred local instruction
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* cache flush to be performed before execution resumes on each hart. This
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* actually performs that local instruction cache flush, which implicitly only
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* refers to the current hart.
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*/
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static inline void flush_icache_deferred(struct mm_struct *mm)
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{
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#ifdef CONFIG_SMP
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unsigned int cpu = smp_processor_id();
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cpumask_t *mask = &mm->context.icache_stale_mask;
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if (cpumask_test_cpu(cpu, mask)) {
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cpumask_clear_cpu(cpu, mask);
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/*
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* Ensure the remote hart's writes are visible to this hart.
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* This pairs with a barrier in flush_icache_mm.
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*/
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smp_mb();
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local_flush_icache_all();
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}
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#endif
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}
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void switch_mm(struct mm_struct *prev, struct mm_struct *next,
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struct task_struct *task)
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{
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unsigned int cpu;
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unsigned long asid;
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if (unlikely(prev == next))
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return;
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/*
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* Mark the current MM context as inactive, and the next as
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* active. This is at least used by the icache flushing
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* routines in order to determine who should be flushed.
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*/
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cpu = smp_processor_id();
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cpumask_clear_cpu(cpu, mm_cpumask(prev));
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cpumask_set_cpu(cpu, mm_cpumask(next));
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#ifdef CONFIG_MMU
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check_and_switch_context(next, cpu);
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asid = (next->context.asid.counter & SATP_ASID_MASK)
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<< SATP_ASID_SHIFT;
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csr_write(sptbr, virt_to_pfn(next->pgd) | SATP_MODE | asid);
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#endif
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flush_icache_deferred(next);
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}
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static DEFINE_PER_CPU(atomic64_t, active_asids);
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static DEFINE_PER_CPU(u64, reserved_asids);
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struct asid_info asid_info;
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void check_and_switch_context(struct mm_struct *mm, unsigned int cpu)
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{
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asid_check_context(&asid_info, &mm->context.asid, cpu, mm);
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}
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static void asid_flush_cpu_ctxt(void)
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{
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local_flush_tlb_all();
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}
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static int asids_init(void)
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{
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BUG_ON(((1 << SATP_ASID_BITS) - 1) <= num_possible_cpus());
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if (asid_allocator_init(&asid_info, SATP_ASID_BITS, 1,
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asid_flush_cpu_ctxt))
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panic("Unable to initialize ASID allocator for %lu ASIDs\n",
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NUM_ASIDS(&asid_info));
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asid_info.active = &active_asids;
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asid_info.reserved = &reserved_asids;
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pr_info("ASID allocator initialised with %lu entries\n",
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NUM_CTXT_ASIDS(&asid_info));
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local_flush_tlb_all();
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return 0;
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}
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early_initcall(asids_init);
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