88a2fed916
commit 9f1f57a19c3c281a931dfc71b318494487193d56 Author: sophgo-forum-service <forum_service@sophgo.com> Date: Mon May 13 13:58:23 2024 +0800 [feat] cvikernel opensource for cv18xx soc. - 79b6a7, set lookup_interp_table layer_id.
39 lines
2.0 KiB
C
39 lines
2.0 KiB
C
#ifndef __BM1822_TPU_CFG__
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#define __BM1822_TPU_CFG__
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#define BM1822_VER 1822
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#define BM1822_HW_NPU_SHIFT 3
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#define BM1822_HW_EU_SHIFT 4
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#define BM1822_HW_LMEM_SHIFT 15
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#define BM1822_HW_LMEM_BANKS 8
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#define BM1822_HW_LMEM_BANK_SIZE 0x1000
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#define BM1822_HW_NODE_CHIP_SHIFT 0
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#define BM1822_HW_NPU_NUM (1 << BM1822_HW_NPU_SHIFT)
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#define BM1822_HW_EU_NUM (1 << BM1822_HW_EU_SHIFT)
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#define BM1822_HW_LMEM_SIZE (1 << BM1822_HW_LMEM_SHIFT)
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#define BM1822_HW_LMEM_START_ADDR 0x0C000000
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#define BM1822_HW_NODE_CHIP_NUM (1 << BM1822_HW_NODE_CHIP_SHIFT)
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#if (BM1822_HW_LMEM_SIZE != (BM1822_HW_LMEM_BANK_SIZE * BM1822_HW_LMEM_BANKS))
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#error "Set wrong TPU configuraiton."
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#endif
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#define BM1822_GLOBAL_MEM_START_ADDR 0x0
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#define BM1822_GLOBAL_MEM_SIZE 0x100000000
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#define BM1822_GLOBAL_TIU_CMDBUF_ADDR 0x00000000
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#define BM1822_GLOBAL_TDMA_CMDBUF_ADDR 0x10000000
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#define BM1822_GLOBAL_TIU_CMDBUF_RESERVED_SIZE 0x10000000
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#define BM1822_GLOBAL_TDMA_CMDBUF_RESERVED_SIZE 0x10000000
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#define BM1822_GLOBAL_POOL_RESERVED_SIZE (BM1822_GLOBAL_MEM_SIZE - BM1822_GLOBAL_TIU_CMDBUF_RESERVED_SIZE - BM1822_GLOBAL_TDMA_CMDBUF_RESERVED_SIZE)
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#define BM1822_UART_CTLR_BASE_ADDR 0x04140000
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#define BM1822_TDMA_ENGINE_BASE_ADDR 0x0C100000
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#define BM1822_TDMA_ENGINE_END_ADDR (BM1822_TDMA_ENGINE_BASE_ADDR + 0x1000)
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#define BM1822_TIU_ENGINE_BASE_ADDR 0x0C101000 //"NPS Register" in memory map?
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#define BM1822_TIU_ENGINE_END_ADDR (BM1822_TIU_ENGINE_BASE_ADDR + 0x1000)
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#endif
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