88a2fed916
commit 9f1f57a19c3c281a931dfc71b318494487193d56 Author: sophgo-forum-service <forum_service@sophgo.com> Date: Mon May 13 13:58:23 2024 +0800 [feat] cvikernel opensource for cv18xx soc. - 79b6a7, set lookup_interp_table layer_id.
116 lines
3.0 KiB
C
116 lines
3.0 KiB
C
#ifndef __BM_KERNEL_H__
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#define __BM_KERNEL_H__
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#include <stdint.h>
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#include <stdbool.h>
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#include <math.h>
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#include <stddef.h>
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#include <stdbool.h>
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#include <stdint.h>
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#include <cvikernel/cvikernel.h>
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typedef uint8_t u8;
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typedef uint16_t u16;
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typedef uint32_t u32;
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typedef uint64_t u64;
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typedef int8_t s8;
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typedef int16_t s16;
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typedef int32_t s32;
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typedef int64_t s64;
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef int bmerr_t;
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#define BM_SUCCESS 0 // The operation was successful
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#define BM_ERR_AGAIN 1 // Not ready yet
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#define BM_ERR_FAILURE 2 // General failure
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#define BM_ERR_TIMEOUT 3 // Timeout
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#define BM_ERR_UNINITIALIZED 4 // Uninitialzed
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#define BM_ERR_INVALID_ARGUMENT 5 // Arguments invalid
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#define BM_ERR_NOMEM 6 // Not enough memory
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#define BM_ERR_DATA 7 // Data error
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#define BM_ERR_BUSY 8 // Busy
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#define BM_ERR_NOT_SUPPORTED 9 // Not supported yet
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#define CVI_TPU_TIU 0 // Tensor Instruction Unit
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#define CVI_TPU_CPU 1 // CPU, Reserved for common cpu op
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#define CVI_TPU_TDMA 2 // TPU DMA
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#define CVI_TPU_ENGINE_NUM 3 // Number of Engines
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typedef cvk_fmt_t fmt_t;
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#define FMT_F32 CVK_FMT_F32
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#define FMT_F16 CVK_FMT_F16
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#define FMT_I32 CVK_FMT_I32
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#define FMT_I16 CVK_FMT_I16
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#define FMT_I8 CVK_FMT_I8
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#define FMT_I4 CVK_FMT_I4
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#define FMT_I2 CVK_FMT_I2
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#define FMT_I1 CVK_FMT_I1
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#define FMT_U32 CVK_FMT_U32
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#define FMT_U16 CVK_FMT_U16
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#define FMT_U8 CVK_FMT_U8
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#define FMT_BF16 CVK_FMT_BF16
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#define FMT_INVALID CVK_FMT_INVALID
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typedef enum _Cmdbuf_Head_Magic {
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CMDBUF_HDR_MAGIC_1880v2 = 0xA5,
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CMDBUF_HDR_MAGIC_1822 = 0xA6,
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CMDBUF_HDR_MAGIC_181X = 0xA7,
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CMDBUF_HDR_MAGIC_180X = 0xA8,
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} Cmdbuf_Head_Magic;
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#define BM_CMB_HDR_FLAG_NEURON (0x1)
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#define BM_CMB_HDR_FLAG_WEIGHT (0x2)
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typedef struct __cmd_hdr_s {
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uint8_t magic; // 0xA5
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uint8_t len; // lens in bytes
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uint8_t engine_id: 4; // TPU, GDMA, CDMA
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uint8_t __deprecated: 4;
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uint8_t flags; // CMD_ID, sync flags, etc. TBD
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uint32_t mask; // bit mask for which register need to write
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uint8_t cmd[0];
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} __attribute__((packed)) cmd_hdr_t;
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typedef struct {
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uint32_t chip_version;
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uint32_t cmdbuf_size;
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uint8_t *cmdbuf;
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} bmk_info_t;
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cvk_chip_info_t bmk1880v2_chip_info(void);
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cvk_chip_info_t bmk1822_chip_info(void);
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static inline int ceiling_func(int numerator, int denominator)
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{
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return (numerator + denominator - 1) / denominator;
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}
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static inline int ceiling_func_shift(int numerator, int shift)
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{
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return (numerator + (1 << shift) - 1) >> shift;
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}
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static inline uint64_t align_up(uint64_t x, uint64_t n)
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{
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return (x + n - 1) / n * n;
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}
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// len max number is 255, sometimes cmd larger than 255
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static inline uint32_t cmd_hdr_len(cmd_hdr_t * hdr) {
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if (hdr->len == 0) {
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return hdr->mask;
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}
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return hdr->len;
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}
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#ifdef __cplusplus
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}
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#endif
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#endif /* __BM_KERNEL_H__ */
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