88a2fed916
commit 9f1f57a19c3c281a931dfc71b318494487193d56 Author: sophgo-forum-service <forum_service@sophgo.com> Date: Mon May 13 13:58:23 2024 +0800 [feat] cvikernel opensource for cv18xx soc. - 79b6a7, set lookup_interp_table layer_id.
99 lines
3.0 KiB
C
99 lines
3.0 KiB
C
#ifndef REG_GDMA_H
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#define REG_GDMA_H
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#define TDMA_DESC_REG_BYTES (0x40)
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#define TDMA_ENGINE_DESCRIPTOR_NUM (TDMA_DESC_REG_BYTES >> 2)
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#define TDMA_NUM_BASE_REGS (0x8)
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//backward compatible?
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#define GDMA_TYPE_f32 0
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#define GDMA_TYPE_f16 1
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#define GDMA_TYPE_i32 2
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#define GDMA_TYPE_i16 3
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#define GDMA_TYPE_i8 4
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#define GDMA_TYPE_i4 5
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#define GDMA_TYPE_i2 6
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#define GDMA_TYPE_i1 7
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#define LAST_GDMA_TYPE_i1 8
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//tdma descriptor define
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#define TDMA_DESCRIPTOR_ALIGNED_BIT 6
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#define TDMA_CMD_ACCP0 0
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#define TDMA_CMD_ACCP1 4
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#define TDMA_CMD_ACCP2 8
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#define TDMA_CMD_ACCP3 12
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#define TDMA_CMD_ACCP4 16
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#define TDMA_CMD_ACCP5 20
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#define TDMA_CMD_ACCP6 24
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#define TDMA_CMD_ACCP7 28
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#define TDMA_CMD_ACCP8 32
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#define TDMA_CMD_ACCP9 36
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#define TDMA_CMD_ACCP10 40
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#define TDMA_CMD_ACCP11 44
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#define TDMA_CMD_ACCP12 48
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#define TDMA_CMD_ACCP13 52
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#define TDMA_CMD_ACCP14 56
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#define TDMA_ACCPI0_CMD_VALID_BIT 0
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#define TDMA_ACCPI0_EOD_BIT 2
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#define TDMA_ACCPI0_INTERRUPT_BIT 3
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#define TDMA_ACCPI0_BARRIER_ENABLE_BIT 4
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//tdma control define
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#define TDMA_CTRL (TDMA_ENGINE_BASE_ADDR + 0x0)
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#define TDMA_DES_BASE (TDMA_ENGINE_BASE_ADDR + 0x4)
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#define TDMA_INT_MASK (TDMA_ENGINE_BASE_ADDR + 0x8)
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#define TDMA_SYNC_STATUS (TDMA_ENGINE_BASE_ADDR + 0xC)
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#define TDMA_ARRAYBASE0_L (TDMA_ENGINE_BASE_ADDR + 0x70)
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#define TDMA_ARRAYBASE1_L (TDMA_ENGINE_BASE_ADDR + 0x74)
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#define TDMA_ARRAYBASE2_L (TDMA_ENGINE_BASE_ADDR + 0x78)
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#define TDMA_ARRAYBASE3_L (TDMA_ENGINE_BASE_ADDR + 0x7C)
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#define TDMA_ARRAYBASE4_L (TDMA_ENGINE_BASE_ADDR + 0x80)
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#define TDMA_ARRAYBASE5_L (TDMA_ENGINE_BASE_ADDR + 0x84)
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#define TDMA_ARRAYBASE6_L (TDMA_ENGINE_BASE_ADDR + 0x88)
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#define TDMA_ARRAYBASE7_L (TDMA_ENGINE_BASE_ADDR + 0x8C)
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#define TDMA_ARRAYBASE0_H (TDMA_ENGINE_BASE_ADDR + 0x90)
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#define TDMA_ARRAYBASE1_H (TDMA_ENGINE_BASE_ADDR + 0x94)
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#define TDMA_DEBUG_MODE (TDMA_ENGINE_BASE_ADDR + 0xA0)
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#define TDMA_CTRL_ENABLE_BIT 0
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#define TDMA_CTRL_MODESEL_BIT 1
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#define TDMA_CTRL_RESET_SYNCID_BIT 2
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#define TDMA_CTRL_FORCE_1ARRAY 5
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#define TDMA_CTRL_FORCE_2ARRAY 6
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#define TDMA_CTRL_BURSTLEN_BIT 8
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#define TDMA_CTRL_64BYTE_ALIGN_EN 10
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#define TDMA_CTRL_DESNUM_BIT 16
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//This function only supports the following condition
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//localmem2tensor or tensor2localmem
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//The source and dst shares the the same format
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//Data is 32 bit
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//no stride
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//We use it in the forward_cpu backward_cpu
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static inline int get_index_data_format(int size)
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{
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if (size == 1) {
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return GDMA_TYPE_i1;
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} else if (size <= 16) {
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return GDMA_TYPE_i4;
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} else if (size <= 256){
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return GDMA_TYPE_i8;
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} else {
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return GDMA_TYPE_i16;
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}
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}
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#define LRN_LEFT_SHIFT 0
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#define LRN_RIGHT_SHIFT 1
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#endif /* REG_GDMA_H */
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