From 17af9557abd6b7a2ddf80b45d025d5164eebbddf Mon Sep 17 00:00:00 2001
From: Xing Zheng <zhengxing@rock-chips.com>
Date: Fri, 23 Sep 2022 21:36:27 +0800
Subject: [PATCH] ASoC: rockchip: rk817-codec: clear status of ADC sdo and
 keeping low level during stop stream

Change-Id: I9284c7dce0c5f3e42b8fdea5d2be273c578735f9
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
---
 sound/soc/codecs/rk817_codec.c | 20 ++++++++++++++++++++
 sound/soc/codecs/rk817_codec.h |  3 +++
 2 files changed, 23 insertions(+)

diff --git a/sound/soc/codecs/rk817_codec.c b/sound/soc/codecs/rk817_codec.c
index d64ccd54c9c9..613746f903b9 100644
--- a/sound/soc/codecs/rk817_codec.c
+++ b/sound/soc/codecs/rk817_codec.c
@@ -1036,11 +1036,31 @@ static int rk817_digital_mute(struct snd_soc_dai *dai, int mute)
 			SNDRV_PCM_FMTBIT_S24_LE |\
 			SNDRV_PCM_FMTBIT_S32_LE)
 
+static void rk817_codec_shutdown(struct snd_pcm_substream *substream,
+				 struct snd_soc_dai *dai)
+{
+	struct snd_soc_component *component = dai->component;
+
+	/**
+	 * Note: The following configurations will take effect when i2s bclk
+	 * is working, and we just need to handle the part of ADC that is
+	 * output to SoC.
+	 */
+	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
+		snd_soc_component_update_bits(component, RK817_CODEC_DTOP_DIGEN_CLKE,
+					      I2STX_CKE_EN, I2STX_CKE_EN);
+		usleep_range(1000, 1100);
+		snd_soc_component_update_bits(component, RK817_CODEC_DTOP_DIGEN_CLKE,
+					      I2STX_CKE_EN, I2STX_CKE_DIS);
+	}
+}
+
 static struct snd_soc_dai_ops rk817_dai_ops = {
 	.hw_params	= rk817_hw_params,
 	.set_fmt	= rk817_set_dai_fmt,
 	.set_sysclk	= rk817_set_dai_sysclk,
 	.digital_mute	= rk817_digital_mute,
+	.shutdown	= rk817_codec_shutdown,
 };
 
 static struct snd_soc_dai_driver rk817_dai[] = {
diff --git a/sound/soc/codecs/rk817_codec.h b/sound/soc/codecs/rk817_codec.h
index 5c4a1bc89d84..c5df0af9a73c 100644
--- a/sound/soc/codecs/rk817_codec.h
+++ b/sound/soc/codecs/rk817_codec.h
@@ -83,6 +83,9 @@
 #define ADC_DIG_CLK_DIS			(0x0 << 4)
 #define ADC_DIG_CLK_EN			(0xf << 4)
 
+#define I2STX_CKE_EN			(0x1 << 6)
+#define I2STX_CKE_DIS			(0x0 << 6)
+
 #define DAC_DIG_CLK_MASK		(0xf << 0)
 #define DAC_DIG_CLK_SFT			0
 #define DAC_DIG_CLK_DIS			(0x0 << 0)