From c7f15aed02b9535dd2947fb45ede858f1708c517 Mon Sep 17 00:00:00 2001 From: hejiawencc Date: Wed, 20 Apr 2022 15:06:23 +0800 Subject: [PATCH] =?UTF-8?q?dts/driver/config=20=E5=90=8C=E6=AD=A5=E5=BC=80?= =?UTF-8?q?=E5=8F=91=E6=9C=8D=E5=8A=A1=E5=99=A8=E5=86=85=E5=AE=B9?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .gitignore | 2 + .../dts/rockchip/rk3568-lubancat-core.dtsi | 44 +- .../dts/rockchip/rk3568-lubancat-dev-cam.dtsi | 298 ++++++++ .../boot/dts/rockchip/rk3568-lubancat-dev.dts | 11 +- .../dts/rockchip/rk3568-lubancat-dev.dtsi | 151 ++-- .../boot/dts/rockchip/rk3568-lubancat-edp.dts | 149 ++++ .../dts/rockchip/rk3568-lubancat-mipi.dts | 697 ++++++++++++++++++ .../rockchip/rk3568-lubancat-mipi_lcd.dtsi | 310 ++++++++ .../dts/rockchip/rk3568-lubancat-port.dtsi | 368 +++++---- arch/arm64/configs/rockchip_linux_defconfig | 15 +- drivers/rtc/rtc-rx8010.c | 1 + 11 files changed, 1816 insertions(+), 230 deletions(-) create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-lubancat-dev-cam.dtsi create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-lubancat-edp.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-lubancat-mipi.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-lubancat-mipi_lcd.dtsi diff --git a/.gitignore b/.gitignore index f2f21dd93b87..54f9958c8f80 100644 --- a/.gitignore +++ b/.gitignore @@ -133,6 +133,8 @@ x509.genkey # Kconfig presets all.config +defconfig # Kdevelop4 *.kdev4 + diff --git a/arch/arm64/boot/dts/rockchip/rk3568-lubancat-core.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-lubancat-core.dtsi index a6c9421b000f..64a47cc5af9b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-lubancat-core.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568-lubancat-core.dtsi @@ -13,6 +13,7 @@ #include #include #include "rk3568.dtsi" +#include "rk3568-linux.dtsi" / { compatible = "rockchip,rk3568-lubancat-core", "rockchip,rk3568"; @@ -57,14 +58,6 @@ }; }; - rk_headset: rk-headset { - status = "disabled"; - compatible = "rockchip_headset"; - headset_gpio = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&hp_det>; - }; - pdmics: dummy-codec { status = "disabled"; compatible = "rockchip,dummy-codec"; @@ -161,6 +154,16 @@ regulator-always-on; }; + vcc5v0_usb20_host: vcc5v0-usb20-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb20_host_en>; + regulator-name = "vcc5v0_usb20_host"; + regulator-always-on; + }; + vcc5v0_otg: vcc5v0-otg-regulator { compatible = "regulator-fixed"; enable-active-high; @@ -537,11 +540,10 @@ rk809_codec: codec { #sound-dai-cells = <0>; compatible = "rockchip,rk809-codec", "rockchip,rk817-codec"; - clocks = <&cru I2S1_MCLKOUT>; + clocks = <&cru I2S1_MCLKOUT_TX>; clock-names = "mclk"; - assigned-clocks = <&cru I2S1_MCLKOUT>, <&cru I2S1_MCLK_TX_IOE>; - assigned-clock-rates = <12288000>; - assigned-clock-parents = <&cru I2S1_MCLKOUT_TX>, <&cru I2S1_MCLKOUT_TX>; + assigned-clocks = <&cru I2S1_MCLKOUT_TX>; + assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; pinctrl-names = "default","spk_gpio"; pinctrl-0 = <&i2s1m0_mclk>; pinctrl-1 = <&spk_ctl_gpio>; @@ -656,6 +658,12 @@ status = "okay"; }; +&reserved_memory { + abc: abc@80900000{ + reg = <0x0 0x80900000 0x0 0x100000>; + }; +}; + &bus_npu { bus-supply = <&vdd_logic>; pvtm-supply = <&vdd_cpu>; @@ -671,11 +679,7 @@ bus-width = <8>; supports-emmc; non-removable; - mmc-ddr-1_8v; - mmc-hs200-1_8v; max-frequency = <200000000>; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; status = "okay"; }; @@ -713,12 +717,12 @@ }; &u2phy1_host { - phy-supply = <&vcc5v0_host>; + phy-supply = <&vcc5v0_usb20_host>; status = "okay"; }; &u2phy1_otg { - phy-supply = <&vcc5v0_host>; + phy-supply = <&vcc5v0_usb20_host>; status = "okay"; }; @@ -830,6 +834,10 @@ rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; }; + vcc5v0_usb20_host_en: vcc5v0-usb20-host-en { + rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + vcc5v0_otg_en: vcc5v0-otg-en { rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-lubancat-dev-cam.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-lubancat-dev-cam.dtsi new file mode 100644 index 000000000000..4a5072ed6843 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-lubancat-dev-cam.dtsi @@ -0,0 +1,298 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ + +/ { + ext_cam0_clk: external-camera0-clock { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "CLK_CAMERA0_24MHZ"; + #clock-cells = <0>; + }; + + ext_cam1_clk: external-camera1-clock { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "CLK_CAMERA1_24MHZ"; + #clock-cells = <0>; + }; +}; + +&rkisp { + status = "okay"; +}; + +&rkisp_mmu { + status = "okay"; +}; + +&rkisp_vir0 { + status = "okay"; + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&dphy1_out>; + }; + }; +}; + +&rkisp_vir1 { + status = "okay"; + port { + #address-cells = <1>; + #size-cells = <0>; + + isp1_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds_sditf>; + }; + }; +}; + +&csi2_dphy_hw { + status = "okay"; +}; + +&csi2_dphy0 { + status = "disabled"; +}; + +&csi2_dphy1 { + status = "okay"; + /* + * dphy1 only used for split mode, + * can be used concurrently with dphy2 + * full mode and split mode are mutually exclusive + */ + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + dphy1_in: endpoint@1 { + reg = <1>; + remote-endpoint = <&cam0_ov5640_out>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dphy1_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&isp0_in>; + // remote-endpoint = <&mipi_csi2_input>; + }; + }; + }; +}; + +&csi2_dphy2 { + status = "okay"; + /* + * dphy2 only used for split mode, + * can be used concurrently with dphy1 + * full mode and split mode are mutually exclusive + */ + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + dphy2_in: endpoint@1 { + reg = <1>; + remote-endpoint = <&cam1_ov5640_out>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dphy2_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&mipi_csi2_input>; + // remote-endpoint = <&isp1_in>; + }; + }; + }; +}; + +&mipi_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&dphy2_out>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&rkcif_mipi_lvds { + status = "okay"; + port { + cif_mipi_in: endpoint { + remote-endpoint = <&mipi_csi2_output>; + data-lanes = <1 2>; + }; + }; +}; + +&rkcif_mipi_lvds_sditf { + status = "okay"; + port { + mipi_lvds_sditf: endpoint { + remote-endpoint = <&isp1_in>; + data-lanes = <1 2>; + }; + }; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&rkcif { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + cam0_ov5640: camera0@3c { + status = "okay"; + compatible = "ovti,ov5640"; + reg = <0x3c>; + + clocks = <&ext_cam0_clk>; + clock-names = "xvclk"; + // pinctrl-names = "default"; + // pinctrl-0 = <&pinctrl_cam0>; + + dovdd-supply = <&cam0_dovdd>; /* 1.8v */ + avdd-supply = <&cam0_avdd>; /* 2.8v */ + dvdd-supply = <&cam0_dvdd>; /* 1.5v */ + reset-gpios = <&gpio3 RK_PB6 GPIO_ACTIVE_LOW>; + pwdn-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "rockchip,camera_default", "rockchip,camera_sleep"; + rotation = <180>; + + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "NC"; + rockchip,camera-module-lens-name = "NC"; + + port { + /* MIPI CSI bus endpoint */ + cam0_ov5640_out: endpoint { + remote-endpoint = <&dphy1_in>; + // clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&i2c5{ + status = "okay"; + + cam1_ov5640: camera1@3c { + status = "okay"; + compatible = "ovti,ov5640"; + reg = <0x3c>; + + clocks = <&ext_cam1_clk>; + clock-names = "xvclk"; + // pinctrl-names = "default"; + // pinctrl-0 = <&pinctrl_cam1>; + + dovdd-supply = <&cam1_dovdd>; /* 1.8v */ + avdd-supply = <&cam1_avdd>; /* 2.8v */ + dvdd-supply = <&cam1_dvdd>; /* 1.5v */ + reset-gpios = <&gpio3 RK_PB5 GPIO_ACTIVE_LOW>; + pwdn-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "rockchip,camera_default", "rockchip,camera_sleep"; + + rotation = <180>; + + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "NC"; + rockchip,camera-module-lens-name = "NC"; + + port { + /* MIPI CSI bus endpoint */ + cam1_ov5640_out: endpoint { + remote-endpoint = <&dphy2_in>; + // clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&pwm11 { + status = "okay"; +}; + + +// &pinctrl { + +// cam { + +// pinctrl_cam0: pinctrl-cam0 { +// rockchip,pins = +// <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>, +// <3 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>; +// }; + +// pinctrl_cam1: pinctrl-cam1 { +// rockchip,pins = +// <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>, +// <3 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; +// }; + +// }; + +// }; \ No newline at end of file diff --git a/arch/arm64/boot/dts/rockchip/rk3568-lubancat-dev.dts b/arch/arm64/boot/dts/rockchip/rk3568-lubancat-dev.dts index b484c68a43e3..72cbbc4a4d82 100755 --- a/arch/arm64/boot/dts/rockchip/rk3568-lubancat-dev.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-lubancat-dev.dts @@ -7,14 +7,15 @@ /dts-v1/; #include "rk3568-lubancat-dev.dtsi" +#include "rk3568-lubancat-dev-cam.dtsi" / { - model = "AIO-3568J HDMI (Linux)"; + model = "LubanCat-RK3568 HDMI"; compatible = "rockchip,rk3568-lubancat-dev", "rockchip,rk3568"; }; -// &route_hdmi { -// status = "okay"; -// connect = <&vp0_out_hdmi>; -// }; +&route_hdmi { + status = "okay"; + connect = <&vp0_out_hdmi>; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-lubancat-dev.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-lubancat-dev.dtsi index 91eb1c8342d0..7299a88ff0e2 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-lubancat-dev.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568-lubancat-dev.dtsi @@ -28,59 +28,68 @@ regulator-always-on; }; - // pcie_pi6c_oe: pcie-pi6c-oe-regulator { - // compatible = "regulator-fixed"; - // //enable-active-high; - // gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_LOW>; - // pinctrl-names = "default"; - // pinctrl-0 = <&pcie_pi6c_oe_en>; - // regulator-name = "pcie_pi6c_oe_en"; - // regulator-always-on; - // }; - vcc_4g_power: vcc-4g-power-regulator { compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc_4g_power_en>; - regulator-name = "vcc_4g_power_en"; - regulator-always-on; - }; + enable-active-high; + gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc_4g_power_en>; + regulator-name = "vcc_4g_power_en"; + regulator-always-on; + }; leds: leds { status = "okay"; compatible = "gpio-leds"; - power_led: power { - label = "led_power"; - linux,default-trigger = "ir-power-click"; - default-state = "on"; - gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&led2_power>; - }; - - user_led: user { - label = "led_user"; - linux,default-trigger = "ir-user-click"; - default-state = "on"; - gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&led1_power>; - }; - - fan_ctl: fan-ctl { - label = "led_fan_ctl"; - linux,default-trigger = "ir-user-click"; + led0: led0 { + label = "led0"; + linux,default-trigger = "heartbeat"; default-state = "on"; gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; - pinctrl-0 = <&led0_power>; + pinctrl-0 = <&led0_pin>; + }; + + led1: led1 { + label = "led1"; + linux,default-trigger = "heartbeat"; + default-state = "on"; + gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&led1_pin>; + }; + + led2: led2 { + label = "led2"; + linux,default-trigger = "heartbeat"; + default-state = "on"; + gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&led2_pin>; }; }; }; +&xin32k { + status = "disabled"; +}; + +&pwm2 { + status = "okay"; +}; + +&i2c0 { + rx8010: rx8010@32 { + compatible = "epson,rx8010"; + reg = <0x32>; + pinctrl-0 = <&rx8010_irq>; + interrupt-parent = <&gpio4>; + interrupts = <10 IRQ_TYPE_LEVEL_LOW>; + status = "okay"; + }; +}; + &csi2_dphy0 { status = "disabled"; }; @@ -95,7 +104,7 @@ }; &csi2_dphy2 { - status = "okay"; + status = "disabled"; /* * dphy2 only used for split mode, * can be used concurrently with dphy1 @@ -114,26 +123,22 @@ &i2c1 { status = "okay"; }; - +/* &i2c4 { status = "okay"; }; - -&pca9555 { - status = "okay"; -}; +*/ +// &pca9555 { +// status = "disabled"; +// }; &i2c5 { status = "okay"; }; -&hym8563 { - status = "okay"; -}; - -&mc3230 { - status = "okay"; -}; +// &mc3230 { +// status = "okay"; +// }; &uart3 { status = "okay"; @@ -144,7 +149,7 @@ }; &spi1 { - status = "okay"; + status = "disabled"; }; &spi_wk2xxx { @@ -159,7 +164,7 @@ reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&pcie30_3v3>; - status = "okay"; + status = "disable"; }; &its { @@ -190,10 +195,18 @@ led_status_value = <0x6940>; }; +&uart7 { + status = "disable"; +}; + &uart8 { status = "okay"; }; +&uart9 { + status = "okay"; +}; + &sdio_pwrseq { status = "okay"; reset-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>; @@ -206,7 +219,7 @@ }; &wireless_wlan { - wifi_chip_type = "rtl8822cs"; + wifi_chip_type = "ty4358"; status = "okay"; }; @@ -247,36 +260,42 @@ usb { vcc_hub_power_en: vcc-hub-power-en { - rockchip,pins = <2 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <2 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>; }; vcc_hub_reset_en: vcc-hub-reset-en { rockchip,pins = <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; }; }; - - // pcie { - // pcie_pi6c_oe_en: pcie-pi6c-oe-en { - // rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; - // }; - // }; - +/* + pcie { + pcie_pi6c_oe_en: pcie-pi6c-oe-en { + rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +*/ 4g { vcc_4g_power_en: vcc-4g-power-en { rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; }; }; + rx8010 { + rx8010_irq: rx8010-irq { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + leds { - led0_power: led0-power { + led0_pin: led0-pin { rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; }; - led1_power: led1-power { + led1_pin: led1-pin { rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; }; - led2_power: led2-power { + led2_pin: led2-pin { rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-lubancat-edp.dts b/arch/arm64/boot/dts/rockchip/rk3568-lubancat-edp.dts new file mode 100644 index 000000000000..b4945c952c17 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-lubancat-edp.dts @@ -0,0 +1,149 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + * EDP接口设备树 + * AUX通信失败，协商速率过低，怀疑硬件问题 + * + * + */ + + /dts-v1/; + +#include "rk3568-lubancat-dev.dtsi" + +/ { + model = "LubanCat-RK3568 HDMI+EDP (Linux)"; + compatible = "rockchip,rk3568-lubancat-edp", "rockchip,rk3568"; + + vcc3v3_lcd_edp: vcc3v3-lcd-edp { + compatible = "regulator-fixed"; + gpio = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-name = "vcc3v3_lcd_edp"; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + edp_panel: edp-panel { + compatible = "simple-panel"; + status = "okay"; + power-supply = <&vcc3v3_lcd_edp>; + enable-gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_HIGH>; + //bus-format = ; + prepare-delay-ms = <500>; //AUX通信前延时 + enable-delay-ms = <500>; + + backlight = <&backlight>; + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <140000000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <40>; + hsync-len = <40>; + hback-porch = <80>; + vfront-porch = <16>; + vsync-len = <8>; + vback-porch = <16>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + panel_in_edp: endpoint { + remote-endpoint = <&edp_out_panel>; + }; + }; + }; + + backlight: backlight { + status = "okay"; + compatible = "pwm-backlight"; + pwms = <&pwm0 0 500000 0>; //2khz + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <200>; + }; +}; + +&pwm0 { + status = "okay"; +}; + +&edp { + status = "okay"; + hpd-gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>; + // force-hpd; //强制hpd，忽略物理hdp信号 + + ports { + edp_out: port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + edp_out_panel: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_in_edp>; + }; + }; + }; +}; + +&edp_phy { + status = "okay"; +}; + +&route_edp { + status = "okay"; +}; + +&edp_in_vp0 { + status = "okay"; +}; + +&edp_in_vp1 { + status = "disabled"; +}; + +&hdmi { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-lubancat-mipi.dts b/arch/arm64/boot/dts/rockchip/rk3568-lubancat-mipi.dts new file mode 100644 index 000000000000..4b2413c385b4 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-lubancat-mipi.dts @@ -0,0 +1,697 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3568-lubancat-dev.dtsi" + +/ { + model = "LubanCat-RK3568 HDMI (Linux)"; + compatible = "rockchip,rk3568-lubancat-dev", "rockchip,rk3568"; + + backlight: backlight { + status = "okay"; + compatible = "pwm-backlight"; + pwms = <&pwm4 0 50000 0>; + brightness-levels = < + 95 95 95 95 95 95 95 95 + 95 95 95 95 95 95 95 95 + 95 95 95 95 95 95 95 95 + 95 95 95 95 95 95 95 95 + 95 95 95 95 95 95 95 95 + 95 95 95 95 95 95 95 95 + 95 95 95 95 95 95 95 95 + 95 95 95 95 95 95 95 95 + 95 95 95 95 95 95 95 95 + 95 95 95 95 95 95 95 95 + 95 95 95 95 95 95 95 95 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + backlight1: backlight { + status = "okay"; + compatible = "pwm-backlight"; + pwms = <&pwm5 0 50000 0>; + brightness-levels = < + 95 95 95 95 95 95 95 95 + 95 95 95 95 95 95 95 95 + 95 95 95 95 95 95 95 95 + 95 95 95 95 95 95 95 95 + 95 95 95 95 95 95 95 95 + 95 95 95 95 95 95 95 95 + 95 95 95 95 95 95 95 95 + 95 95 95 95 95 95 95 95 + 95 95 95 95 95 95 95 95 + 95 95 95 95 95 95 95 95 + 95 95 95 95 95 95 95 95 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; +}; + +&i2c1 { + status = "okay"; + goodix_ts@5d { + status = "okay"; + compatible = "goodix,gt9xxx"; + reg = <0x5d>; + interrupt-parent = <&gpio0>; + interrupts = ; + goodix,rst-gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + goodix,irq-gpio = <&gpio0 RK_PB5 GPIO_ACTIVE_LOW>; +// flip-x = <1>; +// flip-y = <1>; + }; +}; +/* +&i2c5 { + status = "okay"; + goodix_ts@5d { + status = "okay"; + compatible = "goodix,gt9xxx"; + reg = <0x5d>; + interrupt-parent = <&gpio1>; + interrupts = ; + goodix,rst-gpio = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + goodix,irq-gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>; +// flip-x = <1>; +// flip-y = <1>; + }; +}; +*/ +&route_dsi0 { + status = "okay"; + connect = <&vp0_out_dsi0>; +}; + +&video_phy0 { + status = "okay"; +}; + +&dsi0_in_vp0 { + status = "okay"; +}; + +&dsi0_in_vp1 { + status = "disabled"; +}; + +&dsi0 { + status = "okay"; + rockchip,dual-channel=<&dsi1>; + panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + backlight = <&backlight>; + reset-gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_LOW>; + + size,width = <68>; + size,height = <121>; + + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + panel-init-sequence = [ + 15 00 04 FF 98 81 03 + 15 00 02 01 00 + 15 00 02 02 00 + 15 00 02 03 72 + 15 00 02 04 00 + 15 00 02 05 00 + 15 00 02 06 09 + 15 00 02 07 00 + 15 00 02 08 00 + 15 00 02 09 01 + 15 00 02 0A 00 + 15 00 02 0B 00 + 15 00 02 0C 01 + 15 00 02 0D 00 + 15 00 02 0E 00 + 15 00 02 0F 00 + 15 00 02 10 00 + 15 00 02 11 00 + 15 00 02 12 00 + 15 00 02 13 00 + 15 00 02 14 00 + 15 00 02 15 00 + 15 00 02 16 00 + 15 00 02 17 00 + 15 00 02 18 00 + 15 00 02 19 00 + 15 00 02 1A 00 + 15 00 02 1B 00 + 15 00 02 1C 00 + 15 00 02 1D 00 + 15 00 02 1E 40 + 15 00 02 1F 80 + 15 00 02 20 05 + 15 00 02 21 02 + 15 00 02 22 00 + 15 00 02 23 00 + 15 00 02 24 00 + 15 00 02 25 00 + 15 00 02 26 00 + 15 00 02 27 00 + 15 00 02 28 33 + 15 00 02 29 02 + 15 00 02 2A 00 + 15 00 02 2B 00 + 15 00 02 2C 00 + 15 00 02 2D 00 + 15 00 02 2E 00 + 15 00 02 2F 00 + 15 00 02 30 00 + 15 00 02 31 00 + 15 00 02 32 00 + 15 00 02 33 00 + 15 00 02 34 00 + 15 00 02 35 00 + 15 00 02 36 00 + 15 00 02 37 00 + 15 00 02 38 3C + 15 00 02 39 00 + 15 00 02 3A 40 + 15 00 02 3B 40 + 15 00 02 3C 00 + 15 00 02 3D 00 + 15 00 02 3E 00 + 15 00 02 3F 00 + 15 00 02 40 00 + 15 00 02 41 00 + 15 00 02 42 00 + 15 00 02 43 00 + 15 00 02 44 00 + 15 00 02 50 00 + 15 00 02 51 23 + 15 00 02 52 45 + 15 00 02 53 67 + 15 00 02 54 89 + 15 00 02 55 AB + 15 00 02 56 01 + 15 00 02 57 23 + 15 00 02 58 45 + 15 00 02 59 67 + 15 00 02 5A 89 + 15 00 02 5B AB + 15 00 02 5C CD + 15 00 02 5D EF + 15 00 02 5E 11 + 15 00 02 5F 01 + 15 00 02 60 00 + 15 00 02 61 15 + 15 00 02 62 14 + 15 00 02 63 0E + 15 00 02 64 0F + 15 00 02 65 0C + 15 00 02 66 0D + 15 00 02 67 06 + 15 00 02 68 02 + 15 00 02 69 02 + 15 00 02 6A 02 + 15 00 02 6B 02 + 15 00 02 6C 02 + 15 00 02 6D 02 + 15 00 02 6E 07 + 15 00 02 6F 02 + 15 00 02 70 02 + 15 00 02 71 02 + 15 00 02 72 02 + 15 00 02 73 02 + 15 00 02 74 02 + 15 00 02 75 01 + 15 00 02 76 00 + 15 00 02 77 14 + 15 00 02 78 15 + 15 00 02 79 0E + 15 00 02 7A 0F + 15 00 02 7B 0C + 15 00 02 7C 0D + 15 00 02 7D 06 + 15 00 02 7E 02 + 15 00 02 7F 07 + 15 00 02 80 02 + 15 00 02 81 02 + 15 00 02 82 02 + 15 00 02 83 02 + 15 00 02 84 07 + 15 00 02 85 02 + 15 00 02 86 02 + 15 00 02 87 02 + 15 00 02 88 02 + 15 00 02 89 02 + 15 00 02 8A 02 + + 15 00 04 FF 98 81 04 + 15 00 02 6C 15 + 15 00 02 6E 2A + 15 00 02 6F 33 + 15 00 02 3A 94 + 15 00 02 8D 1A + 15 00 02 87 BA + 15 00 02 26 76 + 15 00 02 B2 D1 + 15 00 02 B5 06 + + 15 00 04 FF 98 81 01 + 15 00 02 22 0A + 15 00 02 31 00 + 15 00 02 53 8A + 15 00 02 55 8A + 15 00 02 50 AE + 15 00 02 51 AE + 15 00 02 60 28 + 15 00 02 61 00 + 15 00 02 62 19 + 15 00 02 63 10 + 15 00 02 A0 0F + 15 00 02 A1 1B + 15 00 02 A2 28 + 15 00 02 A3 12 + 15 00 02 A4 15 + 15 00 02 A5 28 + 15 00 02 A6 1B + 15 00 02 A7 1E + 15 00 02 A8 79 + 15 00 02 A9 1B + 15 00 02 AA 27 + 15 00 02 AB 69 + 15 00 02 AC 19 + 15 00 02 AD 18 + 15 00 02 AE 4C + 15 00 02 AF 21 + 15 00 02 B0 28 + 15 00 02 B1 52 + 15 00 02 B2 65 + 15 00 02 B3 3F + 15 00 02 C0 04 + 15 00 02 C1 1B + 15 00 02 C0 27 + 15 00 02 C3 13 + 15 00 02 C4 15 + 15 00 02 C5 28 + 15 00 02 C6 1C + 15 00 02 C7 1E + 15 00 02 C8 79 + 15 00 02 C9 1A + 15 00 02 CA 27 + 15 00 02 CB 69 + 15 00 02 CC 1A + 15 00 02 CD 18 + 15 00 02 CE 4C + 15 00 02 CF 21 + 15 00 02 D0 27 + 15 00 02 D1 52 + 15 00 02 D2 65 + 15 00 02 D3 3F + + 15 00 04 FF 98 81 00 + 15 00 02 35 00 + 15 00 02 3A 70 + 15 78 01 11 + 15 19 01 29 + ]; + + panel-exit-sequence = [ + 05 78 01 11 + 05 00 01 29 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi0_timing0>; + dsi0_timing0: timing0 { + clock-frequency = <61589808>; + hactive = <720>; + vactive = <1280>; + hsync-len = <6>; + hback-porch = <20>; + hfront-porch = <10>; + vsync-len = <4>; + vback-porch = <20>; + vfront-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; +}; + +&route_dsi1 { + status = "okay"; + connect = <&vp1_out_dsi1>; +}; + +&video_phy1 { + status = "okay"; +}; + +&dsi1_in_vp0 { + status = "disabled"; +}; + +&dsi1_in_vp1 { + status = "okay"; +}; + + +&dsi1 { + status = "okay"; + panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + backlight = <&backlight1>; + reset-gpios = <&gpio1 RK_PB1 GPIO_ACTIVE_LOW>; + + size,width = <68>; + size,height = <121>; + + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + panel-init-sequence = [ + 15 00 04 FF 98 81 03 + 15 00 02 01 00 + 15 00 02 02 00 + 15 00 02 03 72 + 15 00 02 04 00 + 15 00 02 05 00 + 15 00 02 06 09 + 15 00 02 07 00 + 15 00 02 08 00 + 15 00 02 09 01 + 15 00 02 0A 00 + 15 00 02 0B 00 + 15 00 02 0C 01 + 15 00 02 0D 00 + 15 00 02 0E 00 + 15 00 02 0F 00 + 15 00 02 10 00 + 15 00 02 11 00 + 15 00 02 12 00 + 15 00 02 13 00 + 15 00 02 14 00 + 15 00 02 15 00 + 15 00 02 16 00 + 15 00 02 17 00 + 15 00 02 18 00 + 15 00 02 19 00 + 15 00 02 1A 00 + 15 00 02 1B 00 + 15 00 02 1C 00 + 15 00 02 1D 00 + 15 00 02 1E 40 + 15 00 02 1F 80 + 15 00 02 20 05 + 15 00 02 21 02 + 15 00 02 22 00 + 15 00 02 23 00 + 15 00 02 24 00 + 15 00 02 25 00 + 15 00 02 26 00 + 15 00 02 27 00 + 15 00 02 28 33 + 15 00 02 29 02 + 15 00 02 2A 00 + 15 00 02 2B 00 + 15 00 02 2C 00 + 15 00 02 2D 00 + 15 00 02 2E 00 + 15 00 02 2F 00 + 15 00 02 30 00 + 15 00 02 31 00 + 15 00 02 32 00 + 15 00 02 33 00 + 15 00 02 34 00 + 15 00 02 35 00 + 15 00 02 36 00 + 15 00 02 37 00 + 15 00 02 38 3C + 15 00 02 39 00 + 15 00 02 3A 40 + 15 00 02 3B 40 + 15 00 02 3C 00 + 15 00 02 3D 00 + 15 00 02 3E 00 + 15 00 02 3F 00 + 15 00 02 40 00 + 15 00 02 41 00 + 15 00 02 42 00 + 15 00 02 43 00 + 15 00 02 44 00 + 15 00 02 50 00 + 15 00 02 51 23 + 15 00 02 52 45 + 15 00 02 53 67 + 15 00 02 54 89 + 15 00 02 55 AB + 15 00 02 56 01 + 15 00 02 57 23 + 15 00 02 58 45 + 15 00 02 59 67 + 15 00 02 5A 89 + 15 00 02 5B AB + 15 00 02 5C CD + 15 00 02 5D EF + 15 00 02 5E 11 + 15 00 02 5F 01 + 15 00 02 60 00 + 15 00 02 61 15 + 15 00 02 62 14 + 15 00 02 63 0E + 15 00 02 64 0F + 15 00 02 65 0C + 15 00 02 66 0D + 15 00 02 67 06 + 15 00 02 68 02 + 15 00 02 69 02 + 15 00 02 6A 02 + 15 00 02 6B 02 + 15 00 02 6C 02 + 15 00 02 6D 02 + 15 00 02 6E 07 + 15 00 02 6F 02 + 15 00 02 70 02 + 15 00 02 71 02 + 15 00 02 72 02 + 15 00 02 73 02 + 15 00 02 74 02 + 15 00 02 75 01 + 15 00 02 76 00 + 15 00 02 77 14 + 15 00 02 78 15 + 15 00 02 79 0E + 15 00 02 7A 0F + 15 00 02 7B 0C + 15 00 02 7C 0D + 15 00 02 7D 06 + 15 00 02 7E 02 + 15 00 02 7F 07 + 15 00 02 80 02 + 15 00 02 81 02 + 15 00 02 82 02 + 15 00 02 83 02 + 15 00 02 84 07 + 15 00 02 85 02 + 15 00 02 86 02 + 15 00 02 87 02 + 15 00 02 88 02 + 15 00 02 89 02 + 15 00 02 8A 02 + + 15 00 04 FF 98 81 04 + 15 00 02 6C 15 + 15 00 02 6E 2A + 15 00 02 6F 33 + 15 00 02 3A 94 + 15 00 02 8D 1A + 15 00 02 87 BA + 15 00 02 26 76 + 15 00 02 B2 D1 + 15 00 02 B5 06 + + 15 00 04 FF 98 81 01 + 15 00 02 22 0A + 15 00 02 31 00 + 15 00 02 53 8A + 15 00 02 55 8A + 15 00 02 50 AE + 15 00 02 51 AE + 15 00 02 60 28 + 15 00 02 61 00 + 15 00 02 62 19 + 15 00 02 63 10 + 15 00 02 A0 0F + 15 00 02 A1 1B + 15 00 02 A2 28 + 15 00 02 A3 12 + 15 00 02 A4 15 + 15 00 02 A5 28 + 15 00 02 A6 1B + 15 00 02 A7 1E + 15 00 02 A8 79 + 15 00 02 A9 1B + 15 00 02 AA 27 + 15 00 02 AB 69 + 15 00 02 AC 19 + 15 00 02 AD 18 + 15 00 02 AE 4C + 15 00 02 AF 21 + 15 00 02 B0 28 + 15 00 02 B1 52 + 15 00 02 B2 65 + 15 00 02 B3 3F + 15 00 02 C0 04 + 15 00 02 C1 1B + 15 00 02 C0 27 + 15 00 02 C3 13 + 15 00 02 C4 15 + 15 00 02 C5 28 + 15 00 02 C6 1C + 15 00 02 C7 1E + 15 00 02 C8 79 + 15 00 02 C9 1A + 15 00 02 CA 27 + 15 00 02 CB 69 + 15 00 02 CC 1A + 15 00 02 CD 18 + 15 00 02 CE 4C + 15 00 02 CF 21 + 15 00 02 D0 27 + 15 00 02 D1 52 + 15 00 02 D2 65 + 15 00 02 D3 3F + + 15 00 04 FF 98 81 00 + 15 00 02 35 00 + 15 00 02 3A 70 + 15 78 01 11 + 15 19 01 29 + ]; + + panel-exit-sequence = [ + 05 78 01 11 + 05 00 01 29 + ]; + + disp_timings1: display-timings { + native-mode = <&dsi1_timing0>; + dsi1_timing0: timing0 { + clock-frequency = <61589808>; + hactive = <720>; + vactive = <1280>; + hsync-len = <6>; + hback-porch = <20>; + hfront-porch = <10>; + vsync-len = <4>; + vback-porch = <20>; + vfront-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + panel_in_dsi1: endpoint { + remote-endpoint = <&dsi1_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi1_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi1>; + }; + }; + }; +}; + +&route_hdmi { + status = "disabled"; + connect = <&vp0_out_hdmi>; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-lubancat-mipi_lcd.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-lubancat-mipi_lcd.dtsi new file mode 100644 index 000000000000..dc1f7ec75929 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-lubancat-mipi_lcd.dtsi @@ -0,0 +1,310 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ + + +#include "rk3568-lubancat-dev.dtsi" + +/ { + model = "LubanCat-RK3568 MIPI (Linux)"; + compatible = "rockchip,rk3568-lubancat-dev", "rockchip,rk3568"; + + backlight: backlight { + status = "okay"; + compatible = "pwm-backlight"; + pwms = <&pwm4 0 50000 0>; + brightness-levels = < + 95 95 95 95 95 95 95 95 + 95 95 95 95 95 95 95 95 + 95 95 95 95 95 95 95 95 + 95 95 95 95 95 95 95 95 + 95 95 95 95 95 95 95 95 + 95 95 95 95 95 95 95 95 + 95 95 95 95 95 95 95 95 + 95 95 95 95 95 95 95 95 + 95 95 95 95 95 95 95 95 + 95 95 95 95 95 95 95 95 + 95 95 95 95 95 95 95 95 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; +}; + +&route_dsi0 { + status = "okay"; + connect = <&vp0_out_dsi0>; +}; + +&video_phy0 { + status = "okay"; +}; + +&dsi0_in_vp0 { + status = "okay"; +}; + +&dsi0_in_vp1 { + status = "disabled"; +}; + + +/* + * video_phy0 needs to be enabled + * when dsi0 is enabled + */ +&dsi0 { + status = "okay"; + + dsi0_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + backlight = <&backlight>; + reset-gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_LOW>; + reset-delay-ms = <20>; + + size,width = <68>; + size,height = <121>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | MIPI_DSI_MODE_LPM | MIPI_DSI_ MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + panel-init-sequence = [ + 15 00 04 FF 98 81 03 + 15 00 02 01 00 + 15 00 02 02 00 + 15 00 02 03 72 + 15 00 02 04 00 + 15 00 02 05 00 + 15 00 02 06 09 + 15 00 02 07 00 + 15 00 02 08 00 + 15 00 02 09 01 + 15 00 02 0A 00 + 15 00 02 0B 00 + 15 00 02 0C 01 + 15 00 02 0D 00 + 15 00 02 0E 00 + 15 00 02 0F 00 + 15 00 02 10 00 + 15 00 02 11 00 + 15 00 02 12 00 + 15 00 02 13 00 + 15 00 02 14 00 + 15 00 02 15 00 + 15 00 02 16 00 + 15 00 02 17 00 + 15 00 02 18 00 + 15 00 02 19 00 + 15 00 02 1a 00 + 15 00 02 1b 00 + 15 00 02 1c 00 + 15 00 02 1d 00 + 15 00 02 1e 40 + 15 00 02 1f 80 + 15 00 02 20 05 + 15 00 02 21 02 + 15 00 02 22 00 + 15 00 02 23 00 + 15 00 02 24 00 + 15 00 02 25 00 + 15 00 02 26 00 + 15 00 02 27 00 + 15 00 02 28 33 + 15 00 02 29 02 + 15 00 02 2a 00 + 15 00 02 2b 00 + 15 00 02 2c 00 + 15 00 02 2d 00 + 15 00 02 2e 00 + 15 00 02 2f 00 + 15 00 02 30 00 + 15 00 02 31 00 + 15 00 02 32 00 + 15 00 02 33 00 + 15 00 02 34 00 + 15 00 02 35 00 + 15 00 02 36 00 + 15 00 02 37 00 + 15 00 02 38 3C + 15 00 02 39 00 + 15 00 02 3a 40 + 15 00 02 3b 40 + 15 00 02 3c 00 + 15 00 02 3d 00 + 15 00 02 3e 00 + 15 00 02 3f 00 + 15 00 02 40 00 + 15 00 02 41 00 + 15 00 02 42 00 + 15 00 02 43 00 + 15 00 02 44 00 + 15 00 02 50 00 + 15 00 02 51 23 + 15 00 02 52 45 + 15 00 02 53 67 + 15 00 02 54 89 + 15 00 02 55 ab + 15 00 02 56 01 + 15 00 02 57 23 + 15 00 02 58 45 + 15 00 02 59 67 + 15 00 02 5a 89 + 15 00 02 5b ab + 15 00 02 5c cd + 15 00 02 5d ef + 15 00 02 5e 11 + 15 00 02 5f 01 + 15 00 02 60 00 + 15 00 02 61 15 + 15 00 02 62 14 + 15 00 02 63 0e + 15 00 02 64 0f + 15 00 02 65 0c + 15 00 02 66 0d + 15 00 02 67 06 + 15 00 02 68 02 + 15 00 02 69 02 + 15 00 02 6a 02 + 15 00 02 6b 02 + 15 00 02 6c 02 + 15 00 02 6d 02 + 15 00 02 6e 07 + 15 00 02 6f 02 + 15 00 02 70 02 + 15 00 02 71 02 + 15 00 02 72 02 + 15 00 02 73 02 + 15 00 02 74 02 + 15 00 02 75 01 + 15 00 02 76 00 + 15 00 02 77 14 + 15 00 02 78 15 + 15 00 02 79 0e + 15 00 02 7a 0f + 15 00 02 7b 0c + 15 00 02 7c 0d + 15 00 02 7d 06 + 15 00 02 7e 02 + 15 00 02 7f 07 + 15 00 02 80 02 + 15 00 02 81 02 + 15 00 02 82 02 + 15 00 02 83 02 + 15 00 02 84 07 + 15 00 02 85 02 + 15 00 02 86 02 + 15 00 02 87 02 + 15 00 02 88 02 + 15 00 02 89 02 + 15 00 02 8a 02 + + 15 00 04 ff 98 81 04 + 15 00 02 6c 15 + 15 00 02 6e 2a + 15 00 02 6f 33 + 15 00 02 3a 94 + 15 00 02 8d 1a + 15 00 02 87 ba + 15 00 02 26 76 + 15 00 02 b2 d1 + 15 00 02 b5 06 + + 15 00 04 ff 98 81 01 + 15 00 02 22 0a + 15 00 02 31 00 + 15 00 02 53 8a + 15 00 02 55 8a + 15 00 02 50 ae + 15 00 02 51 ae + 15 00 02 60 28 + 15 00 02 61 00 + 15 00 02 62 19 + 15 00 02 63 10 + 15 00 02 a0 0f + 15 00 02 a1 1b + 15 00 02 a2 28 + 15 00 02 a3 12 + 15 00 02 a4 15 + 15 00 02 a5 28 + 15 00 02 a6 1b + 15 00 02 a7 1e + 15 00 02 a8 79 + 15 00 02 a9 1b + 15 00 02 aa 27 + 15 00 02 ab 69 + 15 00 02 ac 19 + 15 00 02 ad 18 + 15 00 02 ae 4c + 15 00 02 af 21 + 15 00 02 b0 28 + 15 00 02 b1 52 + 15 00 02 b2 65 + 15 00 02 b3 3f + 15 00 02 c0 04 + 15 00 02 c1 1b + 15 00 02 c0 27 + 15 00 02 c3 13 + 15 00 02 c4 15 + 15 00 02 c5 28 + 15 00 02 c6 1c + 15 00 02 c7 1e + 15 00 02 c8 79 + 15 00 02 c9 1a + 15 00 02 ca 27 + 15 00 02 cb 69 + 15 00 02 cc 1a + 15 00 02 cd 18 + 15 00 02 ce 4c + 15 00 02 cf 21 + 15 00 02 d0 27 + 15 00 02 d1 52 + 15 00 02 d2 65 + 15 00 02 d3 3f + + 15 00 04 ff 98 81 00 + 15 00 02 35 00 + 15 00 02 3a 70 + 15 78 01 11 + 15 19 01 29 + ]; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; +}; + +&hdmi { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-lubancat-port.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-lubancat-port.dtsi index fc6dfda526ef..157fde783022 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-lubancat-port.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568-lubancat-port.dtsi @@ -9,7 +9,6 @@ #include #include #include "rk3568-lubancat-core.dtsi" -#include "rk3568-linux.dtsi" / { compatible = "rockchip,rk3568-lubancat-port", "rockchip,rk3568"; @@ -46,6 +45,14 @@ }; }; + rk_headset: rk-headset { + status = "disabled"; + compatible = "rockchip_headset"; + headset_gpio = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + }; + vcc2v5_sys: vcc2v5-ddr { compatible = "regulator-fixed"; regulator-name = "vcc2v5-sys"; @@ -97,6 +104,86 @@ 3300000 0x1>; }; + vcc_cam0_power: vcc-cam0-power-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc_cam0_power_en>; + regulator-name = "vcc_cam0_power"; + regulator-always-on; + }; + + cam0_dovdd: cam0-dovdd { + compatible = "regulator-fixed"; + regulator-name = "cam0_dovdd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_cam0_power>; + }; + + cam0_avdd: cam0-avdd { + compatible = "regulator-fixed"; + regulator-name = "cam0_avdd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + vin-supply = <&vcc_cam0_power>; + }; + + cam0_dvdd: cam0-dvdd { + compatible = "regulator-fixed"; + regulator-name = "cam0_dvdd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + vin-supply = <&vcc_cam0_power>; + }; + + vcc_cam1_power: vcc-cam1-power-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc_cam1_power_en>; + regulator-name = "vcc_cam1_power"; + regulator-always-on; + }; + + cam1_dovdd: cam1-dovdd { + compatible = "regulator-fixed"; + regulator-name = "cam1_dovdd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_cam1_power>; + }; + + cam1_avdd: cam1-avdd { + compatible = "regulator-fixed"; + regulator-name = "cam1_avdd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + vin-supply = <&vcc_cam1_power>; + }; + + cam1_dvdd: cam1-dvdd { + compatible = "regulator-fixed"; + regulator-name = "cam1_dvdd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + vin-supply = <&vcc_cam1_power>; + }; + vcc3v3_bu: vcc3v3-bu { compatible = "regulator-fixed"; regulator-name = "vcc3v3_bu"; @@ -119,13 +206,13 @@ * - SDIO_RESET_L_WL_REG_ON * - PDN (power down when low) */ - reset-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; }; wireless_wlan: wireless-wlan { compatible = "wlan-platdata"; rockchip,grf = <&grf>; - wifi_chip_type = "rtl8822cs"; + wifi_chip_type = "ty4358"; pinctrl-names = "default"; pinctrl-0 = <&wifi_host_wake_irq>; WIFI,host_wake_irq = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; @@ -146,29 +233,6 @@ BT,wake_host_irq = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; status = "disabled"; }; - - flash_led: flash-led { - compatible = "led,rgb13h"; - label = "pwm-flash-led"; - led-max-microamp = <20000>; - flash-max-microamp = <20000>; - flash-max-timeout-us = <1000000>; - pwms = <&pwm11 0 25000 0>; - rockchip,camera-module-index = <1>; - rockchip,camera-module-facing = "front"; - status = "disabled"; - }; - - vcc_camera: vcc-camera-regulator { - compatible = "regulator-fixed"; - //gpio = <&pca9555 PCA_IO0_0 GPIO_ACTIVE_HIGH>; - // gpio = <&pca9555 PCA_IO0_3 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc_cam>; - regulator-name = "vcc_camera"; - enable-active-high; - status = "disabled"; - }; }; &combphy0_us { @@ -187,45 +251,53 @@ status = "okay"; }; -&csi2_dphy0 { - status = "okay"; +// &csi2_dphy0 { +// status = "disable"; - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; +// ports { +// #address-cells = <1>; +// #size-cells = <0>; +// port@0 { +// reg = <0>; +// #address-cells = <1>; +// #size-cells = <0>; +// /* +// mipi_in_ucam0: endpoint@1 { +// reg = <1>; +// remote-endpoint = <&ucam_out0>; +// data-lanes = <1 2 3 4>; +// }; - mipi_in_ucam0: endpoint@1 { - reg = <1>; - remote-endpoint = <&ucam_out0>; - data-lanes = <1 2 3 4>; - }; - mipi_in_ucam1: endpoint@2 { - reg = <2>; - remote-endpoint = <&gc8034_out>; - data-lanes = <1 2 3 4>; - }; - mipi_in_ucam2: endpoint@3 { - reg = <3>; - remote-endpoint = <&ov5695_out>; - data-lanes = <1 2>; - }; - }; - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; +// mipi_in_ucam1: endpoint@2 { +// reg = <2>; +// remote-endpoint = <&gc8034_out>; +// data-lanes = <1 2 3 4>; +// }; - csidphy_out: endpoint@0 { - reg = <0>; - remote-endpoint = <&isp0_in>; - }; - }; - }; -}; +// mipi_in_ucam2: endpoint@3 { +// reg = <3>; +// remote-endpoint = <&ov5695_out>; +// data-lanes = <1 2>; +// }; +// */ +// // mipi_in_ucam3: endpoint@4 { +// // reg = <4>; +// // remote-endpoint = <&ov5640_out>; +// // data-lanes = <1 2>; +// // }; +// }; +// port@1 { +// reg = <1>; +// #address-cells = <1>; +// #size-cells = <0>; + +// csidphy_out: endpoint@0 { +// reg = <0>; +// remote-endpoint = <&isp0_in>; +// }; +// }; +// }; +// }; &gmac0 { phy-mode = "rgmii"; @@ -285,7 +357,7 @@ * power-supply should switche to vcc3v3_lcd1_n * when mipi panel is connected to dsi1. */ - +/* &i2c4 { status = "okay"; gc8034: gc8034@37 { @@ -355,69 +427,74 @@ }; }; }; +*/ +// &i2c1 { +// status = "disabled"; +// clock-frequency = <100000>; -&i2c1 { - status = "disabled"; - clock-frequency = <100000>; +// // pca9555: gpio@21 { +// // status = "disabled"; +// // compatible = "nxp,pca9555"; +// // reg = <0x21>; +// // gpio-controller; +// // #gpio-cells = <2>; +// // gpio-group-num = <500>; +// // }; - pca9555: gpio@21 { - status = "disabled"; - compatible = "nxp,pca9555"; - reg = <0x21>; - gpio-controller; - #gpio-cells = <2>; - gpio-group-num = <500>; - }; +// // ov5640: camera@3c { +// // compatible = "ovti,ov5640"; +// // pinctrl-names = "default"; +// // pinctrl-0 = <&pinctrl_ov5640>; +// // reg = <0x3c>; +// // clocks = <&cru CLK_CIF_OUT>; +// // clock-names = "xclk"; +// // DOVDD-supply = <&cam0_dovdd>; /* 1.8v */ +// // AVDD-supply = <&cam0_avdd>; /* 2.8v */ +// // DVDD-supply = <&cam0_dvdd>; /* 1.5v */ +// // powerdown-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; +// // reset-gpios = <&gpio3 RK_PB6 GPIO_ACTIVE_LOW>; +// // rotation = <180>; +// // status = "okay"; - gt1x: gt1x@14 { - status = "disabled"; - compatible = "goodix,gt1x"; - reg = <0x14>; - pinctrl-names = "default"; - pinctrl-0 = <&touch_gpio>; - goodix,rst-gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; - goodix,irq-gpio = <&gpio0 RK_PB5 IRQ_TYPE_LEVEL_LOW>; - }; -}; +// // port { +// // /* MIPI CSI bus endpoint */ +// // ov5640_out: endpoint { +// // remote-endpoint = <&mipi_in_ucam3>; +// // clock-lanes = <0>; +// // data-lanes = <1 2>; +// // }; +// // }; +// // }; +// }; -&i2c5 { - status = "disabled"; +// &i2c5 { +// status = "disabled"; - hym8563: hym8563@51 { - status = "disabled"; - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - rtc-irq-gpio = <&gpio0 RK_PD3 IRQ_TYPE_EDGE_FALLING>; - clock-frequency = <32768>; - //clock-output-names = "xin32k"; - /* rtc_int is not connected */ - }; - - mc3230: mc3230sensor@4c { - compatible = "gs_mc3230"; - reg = <0x4c>; - type = ; - irq_enable = <0>; - poll_delay_ms = <30>; - layout = <4>; - status = "disabled"; - }; - - mxc6655xa: mxc6655xa@15 { - status = "disabled"; - compatible = "gs_mxc6655xa"; - pinctrl-names = "default"; - pinctrl-0 = <&mxc6655xa_irq_gpio>; - reg = <0x15>; - irq-gpio = <&gpio3 RK_PC1 IRQ_TYPE_LEVEL_LOW>; - irq_enable = <0>; - poll_delay_ms = <30>; - type = ; - power-off-in-suspend = <1>; - layout = <1>; - }; -}; +// mc3230: mc3230sensor@4c { +// compatible = "gs_mc3230"; +// reg = <0x4c>; +// type = ; +// irq_enable = <0>; +// poll_delay_ms = <30>; +// layout = <4>; +// status = "disabled"; +// }; +// /* +// mxc6655xa: mxc6655xa@15 { +// status = "disabled"; +// compatible = "gs_mxc6655xa"; +// pinctrl-names = "default"; +// pinctrl-0 = <&mxc6655xa_irq_gpio>; +// reg = <0x15>; +// irq-gpio = <&gpio3 RK_PC1 IRQ_TYPE_LEVEL_LOW>; +// irq_enable = <0>; +// poll_delay_ms = <30>; +// type = ; +// power-off-in-suspend = <1>; +// layout = <1>; +// }; +// */ +// }; &mdio0 { rgmii_phy0: phy@0 { @@ -443,14 +520,6 @@ status = "disabled"; }; -&rk809_sound { - /delete-property/ simple-audio-card,hp-det-gpio; -}; - -&rk809_codec { - pinctrl-0 = <&i2s1m0_mclk>; -}; - &rkisp { status = "okay"; }; @@ -511,17 +580,29 @@ pinctrl-0 = <&uart4m1_xfer>; }; +&uart7 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&uart7m1_xfer>; +}; + &uart8 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&uart8m0_xfer &uart8m0_ctsn>; }; +&uart9 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&uart9m1_xfer>; +}; + &can1 { status = "disabled"; compatible = "rockchip,can-1.0"; assigned-clocks = <&cru CLK_CAN1>; - assigned-clock-rates = <200000000>; + assigned-clock-rates = <100000000>; pinctrl-names = "default"; pinctrl-0 = <&can1m1_pins>; }; @@ -530,7 +611,7 @@ status = "disabled"; compatible = "rockchip,can-1.0"; assigned-clocks = <&cru CLK_CAN2>; - assigned-clock-rates = <200000000>; + assigned-clock-rates = <100000000>; pinctrl-names = "default"; pinctrl-0 = <&can2m0_pins>; }; @@ -559,7 +640,7 @@ }; &pwm7 { - status = "disabled"; + status = "okay"; compatible = "rockchip,remotectl-pwm"; interrupts = ; @@ -588,13 +669,22 @@ }; &pinctrl { + cam { - vcc_cam: vcc-cam { - rockchip,pins = - /* camera power en */ - <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; - }; + vcc_cam0_power_en: vcc-cam0-power-en { + rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc_cam1_power_en: vcc-cam1-power-en { + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + // pinctrl_ov5640: pinctrl-ov5640 { + // rockchip,pins = + // <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>, + // <3 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>; + // }; }; + headphone { hp_det: hp-det { rockchip,pins = <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; @@ -626,12 +716,13 @@ <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; }; }; - +/* mxc6655xa { mxc6655xa_irq_gpio: mxc6655xa_irq_gpio { rockchip,pins = ; }; }; +*/ }; &sfc{ @@ -640,4 +731,3 @@ assigned-clock-rates = <50000000>; status = "okay"; }; - diff --git a/arch/arm64/configs/rockchip_linux_defconfig b/arch/arm64/configs/rockchip_linux_defconfig index 7bf10ea60205..28b711346aa3 100644 --- a/arch/arm64/configs/rockchip_linux_defconfig +++ b/arch/arm64/configs/rockchip_linux_defconfig @@ -98,6 +98,8 @@ CONFIG_BT=y CONFIG_BT_RFCOMM=y CONFIG_BT_HIDP=y CONFIG_BT_HCIBTUSB=y +CONFIG_BT_HCIUART=y +CONFIG_BT_HCIUART_ATH3K=y CONFIG_BT_HCIBFUSB=y CONFIG_BT_HCIVHCI=y CONFIG_BT_MRVL=y @@ -192,8 +194,11 @@ CONFIG_MWIFIEX=m CONFIG_MWIFIEX_SDIO=m CONFIG_WL_ROCKCHIP=y CONFIG_WIFI_BUILD_MODULE=y -# CONFIG_BCMDHD is not set -CONFIG_RTL8822CS=m +CONFIG_AP6XXX=m +CONFIG_BCMDHD_FW_PATH="/vendor/etc/firmware/bcmdhd.bin" +CONFIG_BCMDHD_NVRAM_PATH="/vendor/etc/firmware/nvram_4358.txt" +CONFIG_BCMDHD_STATIC_IF=y +# CONFIG_RTL_WIRELESS_SOLUTION is not set CONFIG_USB_NET_RNDIS_WLAN=y CONFIG_INPUT_FF_MEMLESS=y CONFIG_INPUT_EVDEV=y @@ -239,6 +244,7 @@ CONFIG_HW_RANDOM_ROCKCHIP=y CONFIG_TCG_TPM=y CONFIG_TCG_TIS_I2C_INFINEON=y CONFIG_I2C_CHARDEV=y +CONFIG_I2C_GPIO=y CONFIG_I2C_RK3X=y CONFIG_I2C_CROS_EC_TUNNEL=y CONFIG_SPI=y @@ -264,6 +270,7 @@ CONFIG_THERMAL_DEFAULT_GOV_POWER_ALLOCATOR=y CONFIG_THERMAL_GOV_FAIR_SHARE=y CONFIG_THERMAL_GOV_STEP_WISE=y CONFIG_CPU_THERMAL=y +CONFIG_DEVFREQ_THERMAL=y CONFIG_ROCKCHIP_THERMAL=y CONFIG_WATCHDOG=y CONFIG_DW_WATCHDOG=y @@ -308,6 +315,7 @@ CONFIG_VIDEO_LT6911UXC=y CONFIG_VIDEO_LT8619C=y CONFIG_VIDEO_OS04A10=y CONFIG_VIDEO_OV4689=y +CONFIG_VIDEO_OV5640=y CONFIG_VIDEO_OV5695=y CONFIG_VIDEO_OV7251=y CONFIG_VIDEO_OV13850=y @@ -343,6 +351,7 @@ CONFIG_MALI_PLATFORM_THIRDPARTY_NAME="rk" CONFIG_MALI_DEBUG=y CONFIG_MALI_PWRSOFT_765=y CONFIG_MALI_BIFROST=y +CONFIG_MALI_BIFROST_DEVFREQ=y CONFIG_MALI_PLATFORM_NAME="rk" CONFIG_BACKLIGHT_LCD_SUPPORT=y # CONFIG_LCD_CLASS_DEVICE is not set @@ -473,6 +482,7 @@ CONFIG_ROCKCHIP_PM_DOMAINS=y CONFIG_ROCKCHIP_PVTM=y CONFIG_ROCKCHIP_SUSPEND_MODE=y CONFIG_ROCKCHIP_VENDOR_STORAGE_UPDATE_LOADER=y +CONFIG_PM_DEVFREQ=y CONFIG_DEVFREQ_GOV_PERFORMANCE=y CONFIG_DEVFREQ_GOV_POWERSAVE=y CONFIG_DEVFREQ_GOV_USERSPACE=y @@ -524,6 +534,7 @@ CONFIG_EXT4_FS_SECURITY=y CONFIG_XFS_FS=y # CONFIG_DNOTIFY is not set CONFIG_FUSE_FS=y +CONFIG_OVERLAY_FS=y CONFIG_ISO9660_FS=y CONFIG_JOLIET=y CONFIG_ZISOFS=y diff --git a/drivers/rtc/rtc-rx8010.c b/drivers/rtc/rtc-rx8010.c index f4db80f9c1b1..75335130f7e9 100644 --- a/drivers/rtc/rtc-rx8010.c +++ b/drivers/rtc/rtc-rx8010.c @@ -464,6 +464,7 @@ static int rx8010_probe(struct i2c_client *client, rx8010->client = client; i2c_set_clientdata(client, rx8010); + device_set_wakeup_capable(&client->dev, true); err = rx8010_init_client(client); if (err)