[Add] First commit

CMakeLists.txt

@@ -0,0 +1,35 @@
+cmake_minimum_required(VERSION 3.15)
+set (CMAKE_C_COMPILER_FORCED true)
+project(GD32W51X LANGUAGES C ASM)
+
+set(CONFIG_TZ_ENABLED              OFF           CACHE BOOL      "Whether to enable trustzone")
+set(CONFIG_OS                      "FREERTOS"    CACHE STRING    "Select which OS")
+set(CONFIG_STATIC_LIB_BUILDED         ON            CACHE BOOL      "Whether static lib builded, like wlan, iperf3 lib")
+
+include(${CMAKE_TOOLCHAIN_FILE})
+toolchain_reload_compiler()
+
+include_directories(
+    config
+    NSPE/Firmware/CMSIS/ARM/cmsis
+    NSPE/Firmware/CMSIS/GD/GD32W51x/Include
+    NSPE/Firmware/CMSIS/DSP_Lib_v1.6.0/include
+    NSPE/WIFI_IOT/app
+    NSPE/WIFI_IOT/bsp
+    NSPE/WIFI_IOT/common
+    MBL/platform
+    ROM-EXPORT/platform
+    ROM-EXPORT/source
+    ROM-EXPORT/mbedtls-2.17.0-rom/include
+)
+
+if (CONFIG_TZ_ENABLED)
+    add_subdirectory(MBL/source)
+    include_directories(MBL/source)
+else()
+    include_directories(MBL/source_ns)
+    add_subdirectory(MBL/source_ns)
+endif()
+
+
+add_subdirectory(NSPE)

MBL/platform/gdm32/armclang/mbl_gdm32.sct

@@ -0,0 +1,49 @@
+#! armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -xc -I ../../platform -I ../../../config
+
+/*
+ * Copyright (c) 2017-2018 ARM Limited. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#undef __ARM_FEATURE_CMSE
+#define __ARM_FEATURE_CMSE  3
+#include "mbl_region.h"
+
+LR_CODE_1 MBL_CODE_START MBL_CODE_SIZE {
+    MBL_CMSE_VENEER MBL_CODE_START {
+        *.o (RESET +First)
+        *(Veneer$$CMSE)
+    }
+
+    MBL_CODE +0 {
+        .ANY (+RO)
+    }
+
+    MBL_SHARED_DATA MBL_SHARED_DATA_START ALIGN 8 EMPTY MBL_SHARED_DATA_SIZE {
+    }
+
+    MBL_DATA MBL_DATA_START {
+        .ANY (+ZI +RW)
+    }
+
+    MBL_BUF +0 ALIGN 8 {
+        mbl.o (.bss.alloc_buf)
+    }
+
+    ARM_LIB_STACKHEAP +0 ALIGN 16 EMPTY MBL_MSP_STACK_SIZE {
+    }
+
+
+
+
+}

MBL/platform/gdm32/armclang/mbl_gdm32_ns.sct

@@ -0,0 +1,39 @@
+#! armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -xc -I ../../platform -I ../../../config
+
+/*
+ * Copyright (c) 2017-2018 ARM Limited. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "mbl_region.h"
+
+LR_CODE_1 MBL_CODE_START MBL_CODE_SIZE {
+    MBL_CODE MBL_CODE_START {
+        *.o (RESET +First)
+        .ANY (+RO)
+    }
+    MBL_CODE_SRAM MBL_DATA_START {
+        mbl_qspi_flash.o (+RO)
+        gd32w51x_qspi.o (+RO)
+    }
+    MBL_DATA +0 ALIGN 16 {
+        .ANY (+ZI +RW)
+    }
+    ARM_LIB_STACKHEAP +0 ALIGN 16 EMPTY MBL_MSP_STACK_SIZE {
+    }
+}
+LR_CODE_2 MBL_API_START MBL_API_SIZE {
+    MBL_API MBL_API_START {
+        mbl_api.o(.rodata.mbl_api)
+    }
+}

MBL/platform/gdm32/armclang/mbl_startup_gdm32.s

@@ -0,0 +1,406 @@
+;/*!
+;    \file    mbl_startup_gdm32.s
+;    \brief   start up file
+;
+;    \version 2021-10-30, V1.0.0, firmware for GD32W51x
+;*/
+
+;/*
+;    Copyright (c) 2021, GigaDevice Semiconductor Inc.
+
+;
+;    Redistribution and use in source and binary forms, with or without modification,
+;are permitted provided that the following conditions are met:
+;
+;    1. Redistributions of source code must retain the above copyright notice, this
+;       list of conditions and the following disclaimer.
+;    2. Redistributions in binary form must reproduce the above copyright notice,
+;       this list of conditions and the following disclaimer in the documentation
+;       and/or other materials provided with the distribution.
+;    3. Neither the name of the copyright holder nor the names of its contributors
+;       may be used to endorse or promote products derived from this software without
+;       specific prior written permission.
+;
+;    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+;OF SUCH DAMAGE.
+;*/
+
+                IMPORT |Image$$ARM_LIB_STACKHEAP$$ZI$$Limit|
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     |Image$$ARM_LIB_STACKHEAP$$ZI$$Limit|              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     SecureFault_Handler       ; Secure Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+;               /* external interrupts handler */
+                DCD     WWDGT_IRQHandler                  ; 16:Window Watchdog Timer
+                DCD     LVD_IRQHandler                    ; 17:LVD through EXTI Line detect
+                DCD     TAMPER_STAMP_IRQHandler           ; 18:Tamper and TimeStamp through EXTI Line detect
+                DCD     RTC_WKUP_IRQHandler               ; 19:RTC Wakeup through EXTI Line
+                DCD     FMC_IRQHandler                    ; 20:FMC
+                DCD     RCU_IRQHandler                    ; 21:RCU
+                DCD     EXTI0_IRQHandler                  ; 22:EXTI Line 0
+                DCD     EXTI1_IRQHandler                  ; 23:EXTI Line 1
+                DCD     EXTI2_IRQHandler                  ; 24:EXTI Line 2
+                DCD     EXTI3_IRQHandler                  ; 25:EXTI Line 3
+                DCD     EXTI4_IRQHandler                  ; 26:EXTI Line 4
+                DCD     DMA0_Channel0_IRQHandler          ; 27:DMA0 Channel0
+                DCD     DMA0_Channel1_IRQHandler          ; 28:DMA0 Channel1
+                DCD     DMA0_Channel2_IRQHandler          ; 29:DMA0 Channel2
+                DCD     DMA0_Channel3_IRQHandler          ; 30:DMA0 Channel3
+                DCD     DMA0_Channel4_IRQHandler          ; 31:DMA0 Channel4
+                DCD     DMA0_Channel5_IRQHandler          ; 32:DMA0 Channel5
+                DCD     DMA0_Channel6_IRQHandler          ; 33:DMA0 Channel6
+                DCD     DMA0_Channel7_IRQHandler          ; 34:DMA0 Channel7
+                DCD     ADC_IRQHandler                    ; 35:ADC
+                DCD     TAMP_STAMP_S_IRQHandler           ; 36:RTC tamper security interrupt
+                DCD     RTC_WKUP_S_IRQHandler             ; 37:RTC wakeup security interrupt
+                DCD     RTC_Alarm_S_IRQHandler            ; 38:RTC Alarm security interrupt
+                DCD     EXTI5_9_IRQHandler                ; 39:EXTI5 to EXTI9
+                DCD     TIMER0_BRK_IRQHandler             ; 40:TIMER0 Break
+                DCD     TIMER0_UP_IRQHandler              ; 41:TIMER0 Update
+                DCD     TIMER0_CMT_IRQHandler             ; 42:TIMER0 Commutation
+                DCD     TIMER0_Channel_IRQHandler         ; 43:TIMER0 Channel Capture Compare
+                DCD     TIMER1_IRQHandler                 ; 44:TIMER1
+                DCD     TIMER2_IRQHandler                 ; 45:TIMER2
+                DCD     TIMER3_IRQHandler                 ; 46:TIMER3
+                DCD     I2C0_EV_IRQHandler                ; 47:I2C0 Event
+                DCD     I2C0_ER_IRQHandler                ; 48:I2C0 Error
+                DCD     I2C1_EV_IRQHandler                ; 49:I2C1 Event
+                DCD     I2C1_ER_IRQHandler                ; 50:I2C1 Error
+                DCD     SPI0_IRQHandler                   ; 51:SPI0
+                DCD     SPI1_IRQHandler                   ; 52:SPI1/I2S1
+                DCD     USART0_IRQHandler                 ; 53:USART0
+                DCD     USART1_IRQHandler                 ; 54:USART1
+                DCD     USART2_IRQHandler                 ; 55:USART2
+                DCD     EXTI10_15_IRQHandler              ; 56:EXTI10 to EXTI15
+                DCD     RTC_Alarm_IRQHandler              ; 57:RTC Alarm
+                DCD     PVM_IRQHandler                    ; 58:EXTI[18](PVMO)
+                DCD     0                                 ; 59:Reserved
+                DCD     TIMER15_IRQHandler                ; 60:TIMER15
+                DCD     TIMER16_IRQHandler                ; 61:TIMER16
+                DCD     0                                 ; 62:Reserved
+                DCD     0                                 ; 63:Reserved
+                DCD     0                                 ; 64:Reserved
+                DCD     SDIO_IRQHandler                   ; 65:SDIO
+                DCD     TIMER4_IRQHandler                 ; 66:TIMER4
+                DCD     I2C0_WKUP_IRQHandler              ; 67:I2C0 Wakeup
+                DCD     USART0_WKUP_IRQHandler            ; 68:USART0 Wakeup
+                DCD     USART2_WKUP_IRQHandler            ; 69:USART2 Wakeup
+                DCD     TIMER5_IRQHandler                 ; 70:TIMER5
+                DCD     0                                 ; 71:Reserved
+                DCD     DMA1_Channel0_IRQHandler          ; 72:DMA1 Channel0
+                DCD     DMA1_Channel1_IRQHandler          ; 73:DMA1 Channel1
+                DCD     DMA1_Channel2_IRQHandler          ; 74:DMA1 Channel2
+                DCD     DMA1_Channel3_IRQHandler          ; 75:DMA1 Channel3
+                DCD     DMA1_Channel4_IRQHandler          ; 76:DMA1 Channel4
+                DCD     DMA1_Channel5_IRQHandler          ; 77:DMA1 Channel5
+                DCD     DMA1_Channel6_IRQHandler          ; 78:DMA1 Channel6
+                DCD     DMA1_Channel7_IRQHandler          ; 79:DMA1 Channel7
+                DCD     0                                 ; 80:Reserved
+                DCD     0                                 ; 81:Reserved
+                DCD     WLAN_WKUP_IRQHandler              ; 82:WIFI11N wakeup interrupt
+                DCD     USBFS_IRQHandler                  ; 83:USBFS global interrupt
+                DCD     0                                 ; 84:Reserved
+                DCD     0                                 ; 85:Reserved
+                DCD     0                                 ; 86:Reserved
+                DCD     0                                 ; 87:Reserved
+                DCD     0                                 ; 88:Reserved
+                DCD     0                                 ; 89:Reserved
+                DCD     0                                 ; 90:Reserved
+                DCD     0                                 ; 91:Reserved
+                DCD     USBFS_WKUP_IRQHandler             ; 92:USBFS_WKUP
+                DCD     0                                 ; 93:Reserved
+                DCD     DCI_IRHandler                     ; 94:DCI
+                DCD     CAU_IRQHandler                    ; 95:CAU
+                DCD     HAU_TRNG_IRQHandler               ; 96:HAU and TRNG
+                DCD     FPU_IRQHandler                    ; 97:FPU
+                DCD     0                                 ; 98:Reserved
+                DCD     0                                 ; 99:Reserved
+                DCD     0                                 ; 100:Reserved
+                DCD     0                                 ; 101:Reserved
+                DCD     0                                 ; 102:Reserved
+                DCD     0                                 ; 103:Reserved
+                DCD     0                                 ; 104:Reserved
+                DCD     HPDF_INT0_IRQHandler              ; 105:HPDF global Interrupt 0
+                DCD     HPDF_INT1_IRQHandler              ; 106:HPDF global Interrupt 1
+                DCD     WLAN_Rx_IRQHandler                ; 107:WIFI11N global interrupt0
+                DCD     WLAN_Tx_IRQHandler                ; 108:WIFI11N global interrupt1
+                DCD     WLAN_Cmn_IRQHandler               ; 109:WIFI11N global interrupt2
+                DCD     EFUSE_IRQHandler                  ; 110:EFUSE
+                DCD     QSPI_IRQHandler                   ; 111:QUADSPI1
+                DCD     PKCAU_IRQHandler                  ; 112:PKCAU
+                DCD     TSI_IRQHandler                    ; 113:TSI
+                DCD     ICACHE_IRQHandler                 ; 114:ICACHE
+                DCD     TZIAC_S_IRQHandler                ; 115:TrustZone interrupt controller secure interrupts
+                DCD     FMC_S_IRQHandler                  ; 116:FMC
+                DCD     QSPI_S_IRQHandler                 ; 117:QSPI security interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU     __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+;/* reset Handler */
+Reset_Handler   PROC
+                EXPORT  Reset_Handler                        [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+;/* dummy Exception Handlers */
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                          [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler                    [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler                    [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler                     [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler                   [WEAK]
+                B       .
+                ENDP
+SecureFault_Handler\
+                PROC
+                EXPORT  SecureFault_Handler                  [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                          [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler                     [WEAK]
+                B       .
+                ENDP
+PendSV_Handler\
+                PROC
+                EXPORT  PendSV_Handler                       [WEAK]
+                B       .
+                ENDP
+SysTick_Handler\
+                PROC
+                EXPORT  SysTick_Handler                      [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+;               /* external interrupts handler */
+                EXPORT     WWDGT_IRQHandler                  [WEAK]
+                EXPORT     LVD_IRQHandler                    [WEAK]
+                EXPORT     TAMPER_STAMP_IRQHandler           [WEAK]
+                EXPORT     RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT     FMC_IRQHandler                    [WEAK]
+                EXPORT     RCU_IRQHandler                    [WEAK]
+                EXPORT     EXTI0_IRQHandler                  [WEAK]
+                EXPORT     EXTI1_IRQHandler                  [WEAK]
+                EXPORT     EXTI2_IRQHandler                  [WEAK]
+                EXPORT     EXTI3_IRQHandler                  [WEAK]
+                EXPORT     EXTI4_IRQHandler                  [WEAK]
+                EXPORT     DMA0_Channel0_IRQHandler          [WEAK]
+                EXPORT     DMA0_Channel1_IRQHandler          [WEAK]
+                EXPORT     DMA0_Channel2_IRQHandler          [WEAK]
+                EXPORT     DMA0_Channel3_IRQHandler          [WEAK]
+                EXPORT     DMA0_Channel4_IRQHandler          [WEAK]
+                EXPORT     DMA0_Channel5_IRQHandler          [WEAK]
+                EXPORT     DMA0_Channel6_IRQHandler          [WEAK]
+                EXPORT     DMA0_Channel7_IRQHandler          [WEAK]
+                EXPORT     ADC_IRQHandler                    [WEAK]
+                EXPORT     TAMP_STAMP_S_IRQHandler           [WEAK]
+                EXPORT     RTC_WKUP_S_IRQHandler             [WEAK]
+                EXPORT     RTC_Alarm_S_IRQHandler            [WEAK]
+                EXPORT     EXTI5_9_IRQHandler                [WEAK]
+                EXPORT     TIMER0_BRK_IRQHandler             [WEAK]
+                EXPORT     TIMER0_UP_IRQHandler              [WEAK]
+                EXPORT     TIMER0_CMT_IRQHandler             [WEAK]
+                EXPORT     TIMER0_Channel_IRQHandler         [WEAK]
+                EXPORT     TIMER1_IRQHandler                 [WEAK]
+                EXPORT     TIMER2_IRQHandler                 [WEAK]
+                EXPORT     TIMER3_IRQHandler                 [WEAK]
+                EXPORT     I2C0_EV_IRQHandler                [WEAK]
+                EXPORT     I2C0_ER_IRQHandler                [WEAK]
+                EXPORT     I2C1_EV_IRQHandler                [WEAK]
+                EXPORT     I2C1_ER_IRQHandler                [WEAK]
+                EXPORT     SPI0_IRQHandler                   [WEAK]
+                EXPORT     SPI1_IRQHandler                   [WEAK]
+                EXPORT     USART0_IRQHandler                 [WEAK]
+                EXPORT     USART1_IRQHandler                 [WEAK]
+                EXPORT     USART2_IRQHandler                 [WEAK]
+                EXPORT     EXTI10_15_IRQHandler              [WEAK]
+                EXPORT     RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT     PVM_IRQHandler                    [WEAK]
+                EXPORT     TIMER15_IRQHandler                [WEAK]
+                EXPORT     TIMER16_IRQHandler                [WEAK]
+                EXPORT     SDIO_IRQHandler                   [WEAK]
+                EXPORT     TIMER4_IRQHandler                 [WEAK]
+                EXPORT     I2C0_WKUP_IRQHandler              [WEAK]
+                EXPORT     USART0_WKUP_IRQHandler            [WEAK]
+                EXPORT     USART2_WKUP_IRQHandler            [WEAK]
+                EXPORT     TIMER5_IRQHandler                 [WEAK]
+                EXPORT     DMA1_Channel0_IRQHandler          [WEAK]
+                EXPORT     DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT     DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT     DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT     DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT     DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT     DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT     DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT     WLAN_WKUP_IRQHandler              [WEAK]
+                EXPORT     USBFS_IRQHandler                  [WEAK]
+                EXPORT     USBFS_WKUP_IRQHandler             [WEAK]
+                EXPORT     DCI_IRHandler                     [WEAK]
+                EXPORT     CAU_IRQHandler                    [WEAK]
+                EXPORT     HAU_TRNG_IRQHandler               [WEAK]
+                EXPORT     FPU_IRQHandler                    [WEAK]
+                EXPORT     HPDF_INT0_IRQHandler              [WEAK]
+                EXPORT     HPDF_INT1_IRQHandler              [WEAK]
+                EXPORT     WLAN_Rx_IRQHandler                [WEAK]
+                EXPORT     WLAN_Tx_IRQHandler                [WEAK]
+                EXPORT     WLAN_Cmn_IRQHandler               [WEAK]
+                EXPORT     EFUSE_IRQHandler                  [WEAK]
+                EXPORT     QSPI_IRQHandler                   [WEAK]
+                EXPORT     PKCAU_IRQHandler                  [WEAK]
+                EXPORT     TSI_IRQHandler                    [WEAK]
+                EXPORT     ICACHE_IRQHandler                 [WEAK]
+                EXPORT     TZIAC_S_IRQHandler                [WEAK]
+                EXPORT     FMC_S_IRQHandler                  [WEAK]
+                EXPORT     QSPI_S_IRQHandler                 [WEAK]
+
+;/* external interrupts handler */
+WWDGT_IRQHandler
+LVD_IRQHandler
+TAMPER_STAMP_IRQHandler
+RTC_WKUP_IRQHandler
+FMC_IRQHandler
+RCU_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA0_Channel0_IRQHandler
+DMA0_Channel1_IRQHandler
+DMA0_Channel2_IRQHandler
+DMA0_Channel3_IRQHandler
+DMA0_Channel4_IRQHandler
+DMA0_Channel5_IRQHandler
+DMA0_Channel6_IRQHandler
+DMA0_Channel7_IRQHandler
+ADC_IRQHandler
+TAMP_STAMP_S_IRQHandler
+RTC_WKUP_S_IRQHandler
+RTC_Alarm_S_IRQHandler
+EXTI5_9_IRQHandler
+TIMER0_BRK_IRQHandler
+TIMER0_UP_IRQHandler
+TIMER0_CMT_IRQHandler
+TIMER0_Channel_IRQHandler
+TIMER1_IRQHandler
+TIMER2_IRQHandler
+TIMER3_IRQHandler
+I2C0_EV_IRQHandler
+I2C0_ER_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+SPI0_IRQHandler
+SPI1_IRQHandler
+USART0_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+EXTI10_15_IRQHandler
+RTC_Alarm_IRQHandler
+PVM_IRQHandler
+TIMER15_IRQHandler
+TIMER16_IRQHandler
+SDIO_IRQHandler
+TIMER4_IRQHandler
+I2C0_WKUP_IRQHandler
+USART0_WKUP_IRQHandler
+USART2_WKUP_IRQHandler
+TIMER5_IRQHandler
+DMA1_Channel0_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+WLAN_WKUP_IRQHandler
+USBFS_IRQHandler
+USBFS_WKUP_IRQHandler
+DCI_IRHandler
+CAU_IRQHandler
+HAU_TRNG_IRQHandler
+FPU_IRQHandler
+HPDF_INT0_IRQHandler
+HPDF_INT1_IRQHandler
+WLAN_Rx_IRQHandler
+WLAN_Tx_IRQHandler
+WLAN_Cmn_IRQHandler
+EFUSE_IRQHandler
+QSPI_IRQHandler
+PKCAU_IRQHandler
+TSI_IRQHandler
+ICACHE_IRQHandler
+TZIAC_S_IRQHandler
+FMC_S_IRQHandler
+QSPI_S_IRQHandler
+                B       .
+
+                ENDP
+
+
+                ALIGN
+
+                END

MBL/platform/gdm32/cmsis_core/mbl_system_gdm32.c

@@ -0,0 +1,210 @@
+/**************************************************************************//**
+ * @file     system_ARMCM33.c
+ * @brief    CMSIS Device System Source File for
+ *           ARMCM33 Device Series
+ * @version  V5.00
+ * @date     02. November 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "stdint.h"
+#include "platform_def.h"
+#include "gd32w51x.h"
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+#if defined (__CC_ARM) || defined ( __ARMCC_VERSION ) || defined(__GNUC__)
+  extern uint32_t __Vectors;
+#endif
+#if defined (__ICCARM__)
+  extern uint32_t __vector_table;
+#endif
+#endif
+
+#define HXTALSTB_DELAY {                             \
+                            volatile uint32_t i;     \
+                            for(i=0; i<0x2000; i++){ \
+                            }                        \
+                        }
+
+/*!
+    \brief      configure the system clock to HXTAL
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+static void system_clock_hxtal(void)
+{
+    uint32_t timeout = 0U;
+    uint32_t stab_flag = 0U;
+
+    /* power up the HXTAL */
+    RCU_CTL |= RCU_CTL_HXTALPU;
+    /* enable HXTAL */
+    RCU_CTL |= RCU_CTL_HXTALEN;
+    RCU_CTL |= RCU_CTL_HXTALENPLL;
+    HXTALSTB_DELAY
+    RCU_CTL |= RCU_CTL_HXTALREADY;
+    /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
+    do{
+        timeout++;
+        stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
+    }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
+
+    /* if fail */
+    if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){
+        while(1){
+        }
+    }
+    RCU_APB1EN |= RCU_APB1EN_PMUEN;
+    PMU_CTL0 |= PMU_CTL0_LDOVS;
+    /* AHB = SYSCLK */
+    RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
+    /* APB2 = AHB */
+    RCU_CFG0 |= RCU_APB2_CKAHB_DIV2;
+    /* APB1 = AHB */
+    RCU_CFG0 |= RCU_APB1_CKAHB_DIV4;
+
+    /* select HXTAL as system clock */
+    RCU_CFG0 &= ~RCU_CFG0_SCS;
+    RCU_CFG0 |= RCU_CKSYSSRC_HXTAL;
+
+    /* wait until HXTAL is selected as system clock */
+    while(0 == (RCU_CFG0 & RCU_SCSS_HXTAL)){
+    }
+}
+
+/*!
+    \brief      configure the system clock to 180M by PLL which selects HXTAL(40M) as its clock source
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void system_clock_180m_40m_hxtal(void)
+{
+    uint32_t timeout = 0U;
+    uint32_t stab_flag = 0U;
+
+    /* power up HXTAL */
+    RCU_CTL |= RCU_CTL_HXTALPU;
+    /* enable HXTAL */
+    RCU_CTL |= RCU_CTL_HXTALEN;
+    RCU_CTL |= RCU_CTL_HXTALENPLL;
+    HXTALSTB_DELAY
+    RCU_CTL |= RCU_CTL_HXTALREADY;
+    /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
+    do{
+        timeout++;
+        stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
+    }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
+
+    /* if fail */
+    if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){
+        while(1){
+        }
+    }
+
+    RCU_APB1EN |= RCU_APB1EN_PMUEN;
+    PMU_CTL0 |= PMU_CTL0_LDOVS;
+
+    /* HXTAL is stable */
+    /* AHB = SYSCLK */
+    RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
+    /* APB2 = AHB/2 */
+    RCU_CFG0 |= RCU_APB2_CKAHB_DIV2;
+    /* APB1 = AHB/4 */
+    RCU_CFG0 |= RCU_APB1_CKAHB_DIV4;
+
+    /* Configure the main PLL, PSC = 40, PLL_N = 360, PLL_P = 2 */
+    RCU_PLL = (40U | (360U << 6U) | (((2U >> 1U) - 1U) << 16U) |
+                   (RCU_PLLSRC_HXTAL) );
+
+    /* enable PLL */
+    RCU_CTL |= RCU_CTL_PLLEN;
+
+    /* wait until PLL is stable */
+    while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
+    }
+
+    /* select PLLP as system clock */
+    RCU_CFG0 &= ~RCU_CFG0_SCS;
+    RCU_CFG0 |= RCU_CKSYSSRC_PLLP;
+
+    /* wait until PLL is selected as system clock */
+    while(0U == (RCU_CFG0 & RCU_SCSS_PLLP)){
+    }
+}
+
+/*----------------------------------------------------------------------------
+  System initialization function
+ *----------------------------------------------------------------------------*/
+/*!
+    \brief      setup the microcontroller system, initialize the system
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void SystemInit (void)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+#if defined (__CC_ARM) || defined ( __ARMCC_VERSION ) || defined(__GNUC__)
+    SCB->VTOR = (uint32_t) &__Vectors;
+#endif
+#if defined (__ICCARM__)
+    SCB->VTOR = (uint32_t) &__vector_table;
+#endif
+#endif
+#ifdef UNALIGNED_SUPPORT_DISABLE
+    SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
+#endif
+    /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2));  /* set CP10 and CP11 Full Access */
+#endif
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) && (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    /* set CP10 and CP11 non-secure access */
+    SCB->NSACR |= BIT(SCB_NSACR_CP11_Pos) | BIT(SCB_NSACR_CP10_Pos);
+#endif
+
+    /* reset the RCU clock configuration to the default reset state */
+    RCU_CTL |= RCU_CTL_HXTALBPS;
+    {
+       __IO int i;
+       for (i = 0; i < 0x20; i++);
+    }
+
+    /* reset CFG0 register */
+    RCU_CFG0 &= ~RCU_CFG0_SCS;
+
+    /* reset HXTALEN, CKMEN and PLLEN bits */
+    RCU_CTL &= ~(RCU_CTL_PLLEN | RCU_CTL_CKMEN | RCU_CTL_HXTALEN);
+    /* reset CFG0 register */
+    RCU_CFG0 = 0x00009400U;
+
+    /* reset PLLCFGR register */
+    RCU_PLL = 0x00003010U;
+
+#ifdef CONFIG_PLATFORM_ASIC
+    system_clock_180m_40m_hxtal();
+#else
+    system_clock_hxtal();
+#endif
+
+    /* Enable icache */
+    icache_enable();
+}

MBL/platform/gdm32/gcc/mbl_gdm32_ns.ld

@@ -0,0 +1,152 @@
+#include "mbl_region.h"
+/* memory map */
+MEMORY
+{
+  FLASH (rx)            : ORIGIN = MBL_CODE_START, LENGTH = MBL_CODE_SIZE
+  FLASH_API (rx)        : ORIGIN = MBL_API_START, LENGTH = MBL_API_SIZE
+  RAM (xrw)             : ORIGIN = MBL_DATA_START, LENGTH = 64K
+}
+
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+  .MBL_API_CODE :
+  {
+    KEEP(*mbl_api.o* (.rodata.mbl_api))
+  } > FLASH_API
+  __stack_size = DEFINED(__stack_size) ? __stack_size : 12K;
+
+/* ISR vectors */
+  .vectors :
+  {
+    . = ALIGN(4);
+    KEEP(*(.vectors)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  memory_layout :
+  {
+    KEEP(*mbl_flash.o* (.bss.qspi_writing))
+  } > RAM
+
+  _sicode = LOADADDR(.code_to_sram);
+  .code_to_sram :
+  {
+    . = ALIGN(4);
+    _scode = .;
+
+    KEEP(*mbl_qspi_flash.o* (.text* .rodata*))
+    KEEP(*gd32w51x_qspi.o* (.text* .rodata*))
+
+    . = ALIGN(4);
+    _ecode = .;
+  } >RAM AT> FLASH
+
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)
+    *(.text*)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    /* the symbol _etext will be defined at the end of code section */
+    _etext = .;
+  } >FLASH
+
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)
+    *(.rodata*)
+    . = ALIGN(4);
+  } >FLASH
+
+   .ARM.extab :
+  {
+     *(.ARM.extab* .gnu.linkonce.armextab.*)
+  } >FLASH
+
+    .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    } >FLASH
+
+  .ARM.attributes : { *(.ARM.attributes) } > FLASH
+
+  .preinit_array :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(.fini_array*))
+    KEEP (*(SORT(.fini_array.*)))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* provide some necessary symbols for startup file to initialize data */
+  _sidata = LOADADDR(.data);
+
+
+  .data :
+  {
+    . = ALIGN(4);
+    /* the symbol _sdata will be defined at the data section end start */
+    _sdata = .;
+    *(.data)
+    *(.data*)
+    . = ALIGN(4);
+    /* the symbol _edata will be defined at the data section end */
+    _edata = .;
+  } >RAM AT> FLASH
+
+  . = ALIGN(4);
+  .bss :
+  {
+    /* the symbol _sbss will be defined at the bss section start */
+    _sbss = .;
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+    . = ALIGN(4);
+    /* the symbol _ebss will be defined at the bss section end */
+    _ebss = .;
+    __bss_end__ = _ebss;
+  } >RAM
+
+ . = ALIGN(8);
+  PROVIDE ( end = _ebss );
+  PROVIDE ( _end = _ebss );
+
+  .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size :
+  {
+    . = ALIGN(4);
+    PROVIDE( _heap_end = . );
+    PROVIDE( Image$$ARM_LIB_STACKHEAP$$ZI$$Base = . );
+    . += __stack_size;
+    . = ALIGN(4);
+    PROVIDE( Image$$ARM_LIB_STACKHEAP$$ZI$$Limit = . );
+  } >RAM AT>RAM
+}
+
+ /* input sections */
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+

MBL/platform/gdm32/gcc/mbl_startup_gdm32.s

@@ -0,0 +1,411 @@
+/*!
+;    \file    mbl_startup_gdm32.s
+;    \brief   start up file
+
+    \version 2021-10-30, V1.0.0, firmware for GD32W51x
+*/
+
+/*
+    Copyright (c) 2021, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice,
+       this list of conditions and the following disclaimer in the documentation
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors
+       may be used to endorse or promote products derived from this software without
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+  .syntax unified
+  .cpu cortex-m33
+  .fpu softvfp
+  .thumb
+
+.global  Default_Handler
+
+/* necessary symbols defined in linker script to initialize data */
+.word  _sidata
+.word  _sdata
+.word  _edata
+.word  _sbss
+.word  _ebss
+
+.equ  BootRAM,        0xF1E0F85F
+
+  .section  .text.Reset_Handler
+  .weak  Reset_Handler
+  .type  Reset_Handler, %function
+
+/* reset Handler */
+Reset_Handler:
+  movs r1, #0
+  b CodeInit
+
+CopyData:
+  ldr r3, =_sidata
+  ldr r3, [r3, r1]
+  str r3, [r0, r1]
+  adds r1, r1, #4
+
+DataInit:
+  ldr r0, =_sdata
+  ldr r3, =_edata
+  adds r2, r0, r1
+  cmp r2, r3
+  bcc CopyData
+  ldr r2, =_sbss
+  b Zerobss
+
+CopyCode:
+  ldr r3, =_sicode
+  ldr r3, [r3, r1]
+  str r3, [r0, r1]
+  adds r1, r1, #4
+
+CodeInit:
+  ldr r0, =_scode
+  ldr r3, =_ecode
+  adds r2, r0, r1
+  cmp r2, r3
+  bcc CopyCode
+  movs r1, #0
+  b DataInit
+
+FillZerobss:
+  movs r3, #0
+  str r3, [r2], #4
+
+Zerobss:
+  ldr r3, = _ebss
+  cmp r2, r3
+  bcc FillZerobss
+/* Call SystemInit function */
+  bl  SystemInit
+/* Call static constructors */
+    bl __libc_init_array
+/* Call the application's entry point.*/
+  bl  main
+
+LoopForever:
+    b LoopForever
+
+
+.size  Reset_Handler, .-Reset_Handler
+
+
+
+    .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b Infinite_Loop
+  .size Default_Handler, .-Default_Handler
+
+
+   .section  .vectors,"a",%progbits
+   .global __Vectors
+
+
+
+__Vectors:
+                .word     Image$$ARM_LIB_STACKHEAP$$ZI$$Limit                      /* Top of Stack */
+                .word     Reset_Handler                     /* Reset Handler */
+                .word     NMI_Handler                       /* NMI Handler */
+                .word     HardFault_Handler                 /* Hard Fault Handler */
+                .word     MemManage_Handler                 /* MPU Fault Handler */
+                .word     BusFault_Handler                  /* Bus Fault Handler */
+                .word     UsageFault_Handler                /* Usage Fault Handler */
+                .word     SecureFault_Handler               /* Secure Fault Handler */
+                .word     0                                 /* Reserved */
+                .word     0                                 /* Reserved */
+                .word     0                                 /* Reserved */
+                .word     SVC_Handler                       /* SVCall Handler */
+                .word     DebugMon_Handler                  /* Debug Monitor Handler */
+                .word     0                                 /* Reserved */
+                .word     PendSV_Handler                    /* PendSV Handler */
+                .word     SysTick_Handler                   /* SysTick Handler */
+
+                /* external interrupts handler */
+                .word     WWDGT_IRQHandler                  /* 16:Window Watchdog Timer */
+                .word     LVD_IRQHandler                    /* 17:LVD through EXTI Line detect */
+                .word     TAMPER_STAMP_IRQHandler           /* 18:Tamper and TimeStamp through EXTI Line detect */
+                .word     RTC_WKUP_IRQHandler               /* 19:RTC Wakeup through EXTI Line */
+                .word     FMC_IRQHandler                    /* 20:FMC */
+                .word     RCU_IRQHandler                    /* 21:RCU */
+                .word     EXTI0_IRQHandler                  /* 22:EXTI Line 0 */
+                .word     EXTI1_IRQHandler                  /* 23:EXTI Line 1 */
+                .word     EXTI2_IRQHandler                  /* 24:EXTI Line 2 */
+                .word     EXTI3_IRQHandler                  /* 25:EXTI Line 3 */
+                .word     EXTI4_IRQHandler                  /* 26:EXTI Line 4 */
+                .word     DMA0_Channel0_IRQHandler          /* 27:DMA0 Channel0 */
+                .word     DMA0_Channel1_IRQHandler          /* 28:DMA0 Channel1 */
+                .word     DMA0_Channel2_IRQHandler          /* 29:DMA0 Channel2 */
+                .word     DMA0_Channel3_IRQHandler          /* 30:DMA0 Channel3 */
+                .word     DMA0_Channel4_IRQHandler          /* 31:DMA0 Channel4 */
+                .word     DMA0_Channel5_IRQHandler          /* 32:DMA0 Channel5 */
+                .word     DMA0_Channel6_IRQHandler          /* 33:DMA0 Channel6 */
+                .word     DMA0_Channel7_IRQHandler          /* 34:DMA0 Channel7 */
+                .word     ADC_IRQHandler                    /* 35:ADC */
+                .word     TAMP_STAMP_S_IRQHandler           /* 36:RTC tamper security interrupt */
+                .word     RTC_WKUP_S_IRQHandler             /* 37:RTC wakeup security interrupt */
+                .word     RTC_Alarm_S_IRQHandler            /* 38:RTC Alarm security interrupt */
+                .word     EXTI5_9_IRQHandler                /* 39:EXTI5 to EXTI9 */
+                .word     TIMER0_BRK_IRQHandler             /* 40:TIMER0 Break */
+                .word     TIMER0_UP_IRQHandler              /* 41:TIMER0 Update */
+                .word     TIMER0_CMT_IRQHandler             /* 42:TIMER0 Commutation */
+                .word     TIMER0_Channel_IRQHandler         /* 43:TIMER0 Channel Capture Compare */
+                .word     TIMER1_IRQHandler                 /* 44:TIMER1 */
+                .word     TIMER2_IRQHandler                 /* 45:TIMER2 */
+                .word     TIMER3_IRQHandler                 /* 46:TIMER3 */
+                .word     I2C0_EV_IRQHandler                /* 47:I2C0 Event */
+                .word     I2C0_ER_IRQHandler                /* 48:I2C0 Error */
+                .word     I2C1_EV_IRQHandler                /* 49:I2C1 Event */
+                .word     I2C1_ER_IRQHandler                /* 50:I2C1 Error */
+                .word     SPI0_IRQHandler                   /* 51:SPI0 */
+                .word     SPI1_IRQHandler                   /* 52:SPI1/I2S1 */
+                .word     USART0_IRQHandler                 /* 53:USART0 */
+                .word     USART1_IRQHandler                 /* 54:USART1 */
+                .word     USART2_IRQHandler                 /* 55:USART2 */
+                .word     EXTI10_15_IRQHandler              /* 56:EXTI10 to EXTI15 */
+                .word     RTC_Alarm_IRQHandler              /* 57:RTC Alarm */
+                .word     PVM_IRQHandler                    /* 58:EXTI[18](PVMO) */
+                .word     0                                 /* 59:Reserved */
+                .word     TIMER15_IRQHandler                /* 60:TIMER15 */
+                .word     TIMER16_IRQHandler                /* 61:TIMER16 */
+                .word     0                                 /* 62:Reserved */
+                .word     0                                 /* 63:Reserved */
+   .size   __Vectors, . - __Vectors
+
+
+  .weak NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+
+
+  .weak HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+
+  .weak MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+
+  .weak BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+
+  .weak UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+
+  .weak SecureFault_Handler
+  .thumb_set SecureFault_Handler,Default_Handler
+
+
+  .weak SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+
+  .weak DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+
+  .weak PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+
+  .weak SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+
+  .weak WWDGT_IRQHandler
+  .thumb_set WWDGT_IRQHandler,Default_Handler
+
+
+  .weak LVD_IRQHandler
+  .thumb_set LVD_IRQHandler,Default_Handler
+
+
+  .weak TAMPER_STAMP_IRQHandler
+  .thumb_set TAMPER_STAMP_IRQHandler,Default_Handler
+
+
+  .weak RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+
+  .weak FMC_IRQHandler
+  .thumb_set FMC_IRQHandler,Default_Handler
+
+
+  .weak RCU_IRQHandler
+  .thumb_set RCU_IRQHandler,Default_Handler
+
+
+  .weak EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+
+  .weak EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+
+  .weak EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+
+  .weak EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+
+  .weak EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+
+  .weak DMA0_Channel0_IRQHandler
+  .thumb_set DMA0_Channel0_IRQHandler,Default_Handler
+
+
+  .weak DMA0_Channel1_IRQHandler
+  .thumb_set DMA0_Channel1_IRQHandler,Default_Handler
+
+
+  .weak DMA0_Channel2_IRQHandler
+  .thumb_set DMA0_Channel2_IRQHandler,Default_Handler
+
+
+  .weak DMA0_Channel3_IRQHandler
+  .thumb_set DMA0_Channel3_IRQHandler,Default_Handler
+
+
+  .weak DMA0_Channel4_IRQHandler
+  .thumb_set DMA0_Channel4_IRQHandler,Default_Handler
+
+
+  .weak DMA0_Channel5_IRQHandler
+  .thumb_set DMA0_Channel5_IRQHandler,Default_Handler
+
+
+  .weak DMA0_Channel6_IRQHandler
+  .thumb_set DMA0_Channel6_IRQHandler,Default_Handler
+
+
+  .weak DMA0_Channel7_IRQHandler
+  .thumb_set DMA0_Channel7_IRQHandler,Default_Handler
+
+
+  .weak ADC_IRQHandler
+  .thumb_set ADC_IRQHandler,Default_Handler
+
+
+  .weak TAMP_STAMP_S_IRQHandler
+  .thumb_set TAMP_STAMP_S_IRQHandler,Default_Handler
+
+
+  .weak RTC_WKUP_S_IRQHandler
+  .thumb_set RTC_WKUP_S_IRQHandler,Default_Handler
+
+
+  .weak RTC_Alarm_S_IRQHandler
+  .thumb_set RTC_Alarm_S_IRQHandler,Default_Handler
+
+
+  .weak EXTI5_9_IRQHandler
+  .thumb_set EXTI5_9_IRQHandler,Default_Handler
+
+
+  .weak TIMER0_BRK_IRQHandler
+  .thumb_set TIMER0_BRK_IRQHandler,Default_Handler
+
+
+  .weak TIMER0_UP_IRQHandler
+  .thumb_set TIMER0_UP_IRQHandler,Default_Handler
+
+
+  .weak TIMER0_CMT_IRQHandler
+  .thumb_set TIMER0_CMT_IRQHandler,Default_Handler
+
+
+  .weak TIMER0_Channel_IRQHandler
+  .thumb_set TIMER0_Channel_IRQHandler,Default_Handler
+
+
+  .weak TIMER1_IRQHandler
+  .thumb_set TIMER1_IRQHandler,Default_Handler
+
+
+  .weak TIMER2_IRQHandler
+  .thumb_set TIMER2_IRQHandler,Default_Handler
+
+
+  .weak TIMER3_IRQHandler
+  .thumb_set TIMER3_IRQHandler,Default_Handler
+
+
+  .weak I2C0_EV_IRQHandler
+  .thumb_set I2C0_EV_IRQHandler,Default_Handler
+
+
+  .weak I2C0_ER_IRQHandler
+  .thumb_set I2C0_ER_IRQHandler,Default_Handler
+
+
+  .weak I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+
+  .weak I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+
+  .weak SPI0_IRQHandler
+  .thumb_set SPI0_IRQHandler,Default_Handler
+
+
+  .weak SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+
+  .weak USART0_IRQHandler
+  .thumb_set USART0_IRQHandler,Default_Handler
+
+
+  .weak USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+
+  .weak USART2_IRQHandler
+  .thumb_set USART2_IRQHandler,Default_Handler
+
+
+  .weak EXTI10_15_IRQHandler
+  .thumb_set EXTI10_15_IRQHandler,Default_Handler
+
+
+  .weak RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+
+  .weak PVM_IRQHandler
+  .thumb_set PVM_IRQHandler,Default_Handler
+
+
+  .weak TIMER15_IRQHandler
+  .thumb_set TIMER15_IRQHandler,Default_Handler
+
+
+  .weak TIMER16_IRQHandler
+  .thumb_set TIMER16_IRQHandler,Default_Handler

MBL/platform/gdm32/gd32w51x_it.c

@@ -0,0 +1,129 @@
+/*!
+    \file    gd32w51x_it.c
+    \brief   interrupt service routines
+
+    \version 2021-10-30, V1.0.0, firmware for GD32W51x
+*/
+
+/*
+    Copyright (c) 2021, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice,
+       this list of conditions and the following disclaimer in the documentation
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors
+       may be used to endorse or promote products derived from this software without
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#include "gd32w51x_it.h"
+#include "rom_export.h"
+
+/*!
+    \brief      this function handles NMI exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void NMI_Handler(void)
+{
+}
+
+/*!
+    \brief      this function print core register information
+    \param[in]  stack: store core register value
+    \param[out] none
+    \retval     none
+*/
+void HardFault_Handler_c(unsigned int stack[])
+{
+    rom_printf("[Hard Fault Handler]\r\n");
+    rom_printf("    R0 = 0x%08X\r\n", stack[0]);
+    rom_printf("    R1 = 0x%08X\r\n", stack[1]);
+    rom_printf("    R2 = 0x%08X\r\n", stack[2]);
+    rom_printf("    R3 = 0x%08X\r\n", stack[3]);
+    rom_printf("    R12 = 0x%08X\r\n", stack[4]);
+    rom_printf("    LR = 0x%08X\r\n", stack[5]);
+    rom_printf("    PC = 0x%08X\r\n", stack[6]);
+    rom_printf("    PSR = 0x%08X\r\n", stack[7]);
+    rom_printf("    BFAR = 0x%08X\r\n", SCB->BFAR);
+    rom_printf("    CFSR = 0x%08X\r\n", SCB->CFSR);
+    rom_printf("    HFSR = 0x%08X\r\n", SCB->HFSR);
+    rom_printf("    DFSR = 0x%08X\r\n", SCB->DFSR);
+    rom_printf("    AFSR = 0x%08X\r\n", SCB->AFSR);
+
+    __ASM volatile("BKPT #01");
+
+    while(1);
+}
+
+/*!
+    \brief      this function handles HardFault exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void HardFault_Handler(void)
+{
+    __asm(/*"PUBLIC Hard_Fault_Handler\n"*/
+    "TST lr, #4\n"
+    "ITE EQ\n"
+    "MRSEQ r0, MSP\n"
+    "MRSNE r0, PSP\n"
+    "B HardFault_Handler_c");
+}
+
+/*!
+    \brief      this function handles MemManage exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void MemManage_Handler(void)
+{
+    /* if Memory Manage exception occurs, go to infinite loop */
+    while(1){
+    }
+}
+
+/*!
+    \brief      this function handles BusFault exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void BusFault_Handler(void)
+{
+    /* if Bus Fault exception occurs, go to infinite loop */
+    while(1){
+    }
+}
+
+/*!
+    \brief      this function handles UsageFault exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void UsageFault_Handler(void)
+{
+    /* if Usage Fault exception occurs, go to infinite loop */
+    while(1){
+    }
+}

MBL/platform/gdm32/gd32w51x_it.h

@@ -0,0 +1,56 @@
+/*!
+    \file    gd32w51x_it.h
+    \brief   the header file of the ISR
+
+    \version 2021-10-30, V1.0.0, firmware for GD32W51x
+*/
+
+/*
+    Copyright (c) 2021, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice,
+       this list of conditions and the following disclaimer in the documentation
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors
+       may be used to endorse or promote products derived from this software without
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32W51X_IT_H
+#define GD32W51X_IT_H
+
+#include "gd32w51x.h"
+
+/* function declarations */
+/* this function handles NMI exception */
+void NMI_Handler(void);
+/* this function handles HardFault exception */
+void HardFault_Handler(void);
+/* this function handles MemManage exception */
+void MemManage_Handler(void);
+/* this function handles BusFault exception */
+void BusFault_Handler(void);
+/* this function handles UsageFault exception */
+void UsageFault_Handler(void);
+
+void USART0_IRQHandler(void);
+void USART1_IRQHandler(void);
+extern void usart_irq_handler(void);
+
+#endif /* GD32W51X_IT_H */

MBL/platform/gdm32/gd32w51x_libopt.h

@@ -0,0 +1,70 @@
+/*!
+    \file    gd32w51x_libopt.h
+    \brief   library optional for gd32w51x
+
+    \version 2021-10-30, V1.0.0, firmware for GD32W51x
+*/
+
+/*
+    Copyright (c) 2021, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice,
+       this list of conditions and the following disclaimer in the documentation
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors
+       may be used to endorse or promote products derived from this software without
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32W51X_LIBOPT_H
+#define GD32W51X_LIBOPT_H
+
+#include "gd32w51x_adc.h"
+#include "gd32w51x_cau.h"
+#include "gd32w51x_crc.h"
+#include "gd32w51x_dbg.h"
+#include "gd32w51x_dci.h"
+#include "gd32w51x_dma.h"
+#include "gd32w51x_efuse.h"
+#include "gd32w51x_exti.h"
+#include "gd32w51x_fmc.h"
+#include "gd32w51x_fwdgt.h"
+#include "gd32w51x_gpio.h"
+#include "gd32w51x_hau.h"
+#include "gd32w51x_hpdf.h"
+#include "gd32w51x_i2c.h"
+#include "gd32w51x_icache.h"
+#include "gd32w51x_misc.h"
+#include "gd32w51x_pkcau.h"
+#include "gd32w51x_pmu.h"
+#include "gd32w51x_qspi.h"
+#include "gd32w51x_rcu.h"
+#include "gd32w51x_rtc.h"
+#include "gd32w51x_sdio.h"
+#include "gd32w51x_spi.h"
+#include "gd32w51x_sqpi.h"
+#include "gd32w51x_syscfg.h"
+#include "gd32w51x_timer.h"
+#include "gd32w51x_trng.h"
+#include "gd32w51x_tsi.h"
+#include "gd32w51x_tzpcu.h"
+#include "gd32w51x_usart.h"
+#include "gd32w51x_wwdgt.h"
+
+#endif /* GD32W51X_LIBOPT_H */

MBL/platform/gdm32/iar/mbl_gdm32.i

@@ -0,0 +1,55 @@
+#include "config_gdm32.h"
+#include "mbl_region.h"
+include "..\..\..\ROM-EXPORT\symbol\rom_symbol.icf";
+
+
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = MBL_CODE_START;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = MBL_CODE_START;
+define symbol __ICFEDIT_region_ROM_end__   = MBL_CODE_START + MBL_CODE_SIZE - 1;
+define symbol __ICFEDIT_region_RAM_SHARED_DATA_start__ = MBL_SHARED_DATA_START;
+define symbol __ICFEDIT_region_RAM_SHARED_DATA_end__   = MBL_SHARED_DATA_START + MBL_SHARED_DATA_SIZE - 1;
+define symbol __ICFEDIT_region_RAM_start__ = MBL_DATA_START;
+define symbol __ICFEDIT_region_RAM_end__   = MBL_DATA_START + 0x10000;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x0400;
+define symbol __ICFEDIT_size_heap__   = 0x0400;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_SHARED_DATA_region  = mem:[from __ICFEDIT_region_RAM_SHARED_DATA_start__  to __ICFEDIT_region_RAM_SHARED_DATA_end__];
+define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block MBL_CMSE_VENEER  { 
+                                section Veneer$$CMSE,    
+                              };
+define block MBL_BUF  { 
+                                section .bss object mbl.o,
+                              };
+
+
+define block CSTACK    with alignment = 32, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 32, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy            { readwrite };
+                    
+do not initialize             { section .noinit };
+
+//place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place at start of ROM_region  { 
+                                readonly section .intvec,
+                                block MBL_CMSE_VENEER,
+                                readonly,
+                              };
+place in RAM_region     { 
+                                block MBL_BUF,
+                                readwrite,
+                                block CSTACK, 
+                                block HEAP,
+                              };
+

MBL/platform/gdm32/iar/mbl_gdm32_ns.i

@@ -0,0 +1,55 @@
+#include "config_gdm32_ntz.h"
+#include "mbl_region.h"
+include "..\..\..\ROM-EXPORT\symbol\rom_symbol.icf";
+
+
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = MBL_CODE_START;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_FLASH_start__ = MBL_CODE_START;
+define symbol __ICFEDIT_region_FLASH_end__   = MBL_CODE_START + MBL_CODE_SIZE - 1;
+define symbol __ICFEDIT_region_FLASH_MBL_API_start__ = MBL_API_START;
+define symbol __ICFEDIT_region_FLASH_MBL_API_end__   = MBL_API_START + MBL_API_SIZE  - 1;
+define symbol __ICFEDIT_region_RAM_start__ = MBL_DATA_START;
+define symbol __ICFEDIT_region_RAM_end__   = MBL_DATA_START + 0x10000;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x1000;
+define symbol __ICFEDIT_size_heap__   = 0x1000;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region FLASH_region   = mem:[from __ICFEDIT_region_FLASH_start__   to __ICFEDIT_region_FLASH_end__];
+define region FLASH_MBL_API_region  = mem:[from __ICFEDIT_region_FLASH_MBL_API_start__  to __ICFEDIT_region_FLASH_MBL_API_end__];
+define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+keep { section .rodata object mbl_api.o };
+
+define block CSTACK    with alignment = 32, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 32, size = __ICFEDIT_size_heap__     { };
+
+define block RAM_CODE { readonly object mbl_qspi_flash.o,  
+                        readonly object gd32w51x_qspi.o };
+					
+define block MBL_API { readonly object mbl_api.o};
+                        
+initialize by copy { readwrite, 
+                     object mbl_qspi_flash.o,  
+                     object gd32w51x_qspi.o };
+                    
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+
+place in FLASH_region          { readonly,
+                                 block RAM_CODE };
+place in FLASH_MBL_API_region  { block MBL_API};
+place in RAM_region            { readwrite,
+                                 block CSTACK, 
+                                 block HEAP };
+
+export symbol __ICFEDIT_region_RAM_start__;
+export symbol __ICFEDIT_region_RAM_end__;
+

MBL/platform/gdm32/iar/mbl_startup_gdm32.s

@@ -0,0 +1,641 @@
+;/*!
+;    \file    mbl_startup_gdm32.s
+;    \brief   start up file
+;
+;    \version 2021-10-30, V1.0.0, firmware for GD32W51x
+;*/
+;
+;/*
+;    Copyright (c) 2021, GigaDevice Semiconductor Inc.
+;
+;    Redistribution and use in source and binary forms, with or without modification,
+;are permitted provided that the following conditions are met:
+;
+;    1. Redistributions of source code must retain the above copyright notice, this
+;       list of conditions and the following disclaimer.
+;    2. Redistributions in binary form must reproduce the above copyright notice,
+;       this list of conditions and the following disclaimer in the documentation
+;       and/or other materials provided with the distribution.
+;    3. Neither the name of the copyright holder nor the names of its contributors
+;       may be used to endorse or promote products derived from this software without
+;       specific prior written permission.
+;
+;    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+;OF SUCH DAMAGE.
+;*/
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__iar_init$$done
+
+__vector_table
+        DCD     sfe(CSTACK)                         ; top of stack
+        DCD     Reset_Handler                       ; Vector Number 1,Reset Handler
+        DCD     NMI_Handler                         ; Vector Number 2,NMI Handler
+        DCD     HardFault_Handler                   ; Vector Number 3,Hard Fault Handler
+        DCD     MemManage_Handler                   ; Vector Number 4,MPU Fault Handler
+        DCD     BusFault_Handler                    ; Vector Number 5,Bus Fault Handler
+        DCD     UsageFault_Handler                  ; Vector Number 6,Usage Fault Handler
+        DCD     SecureFault_Handler                 ; Vector Number 7,Secure Fault Handler
+        DCD     0                                   ; Reserved
+        DCD     0                                   ; Reserved
+        DCD     0                                   ; Reserved
+        DCD     SVC_Handler                         ; Vector Number 11,SVCall Handler
+        DCD     DebugMon_Handler                    ; Vector Number 12,Debug Monitor Handler
+        DCD     0                                   ; Reserved
+        DCD     PendSV_Handler                      ; Vector Number 14,PendSV Handler
+        DCD     SysTick_Handler                     ; Vector Number 15,SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDGT_IRQHandler                    ; 16:Window Watchdog Timer
+        DCD     LVD_IRQHandler                      ; 17:LVD through EXTI Line detect
+        DCD     TAMPER_STAMP_IRQHandler             ; 18:Tamper and TimeStamp through EXTI Line detect
+        DCD     RTC_WKUP_IRQHandler                 ; 19:RTC Wakeup through EXTI Line
+        DCD     FMC_IRQHandler                      ; 20:FMC
+        DCD     RCU_IRQHandler                      ; 21:RCU
+        DCD     EXTI0_IRQHandler                    ; 22:EXTI Line 0
+        DCD     EXTI1_IRQHandler                    ; 23:EXTI Line 1
+        DCD     EXTI2_IRQHandler                    ; 24:EXTI Line 2
+        DCD     EXTI3_IRQHandler                    ; 25:EXTI Line 3
+        DCD     EXTI4_IRQHandler                    ; 26:EXTI Line 4
+        DCD     DMA0_Channel0_IRQHandler            ; 27:DMA0 Channel0
+        DCD     DMA0_Channel1_IRQHandler            ; 28:DMA0 Channel1
+        DCD     DMA0_Channel2_IRQHandler            ; 29:DMA0 Channel2
+        DCD     DMA0_Channel3_IRQHandler            ; 30:DMA0 Channel3
+        DCD     DMA0_Channel4_IRQHandler            ; 31:DMA0 Channel4
+        DCD     DMA0_Channel5_IRQHandler            ; 32:DMA0 Channel5
+        DCD     DMA0_Channel6_IRQHandler            ; 33:DMA0 Channel6
+        DCD     DMA0_Channel7_IRQHandler            ; 34:DMA0 Channel7
+        DCD     ADC_IRQHandler                      ; 35:ADC
+        DCD     TAMP_STAMP_S_IRQHandler             ; 36:RTC tamper security interrupt
+        DCD     RTC_WKUP_S_IRQHandler               ; 37:RTC wakeup security interrupt
+        DCD     RTC_Alarm_S_IRQHandler              ; 38:RTC Alarm security interrupt
+        DCD     EXTI5_9_IRQHandler                  ; 39:EXTI5 to EXTI9
+        DCD     TIMER0_BRK_IRQHandler               ; 40:TIMER0 Break
+        DCD     TIMER0_UP_IRQHandler                ; 41:TIMER0 Update
+        DCD     TIMER0_CMT_IRQHandler               ; 42:TIMER0 Commutation
+        DCD     TIMER0_Channel_IRQHandler           ; 43:TIMER0 Channel Capture Compare
+        DCD     TIMER1_IRQHandler                   ; 44:TIMER1
+        DCD     TIMER2_IRQHandler                   ; 45:TIMER2
+        DCD     TIMER3_IRQHandler                   ; 46:TIMER3
+        DCD     I2C0_EV_IRQHandler                  ; 47:I2C0 Event
+        DCD     I2C0_ER_IRQHandler                  ; 48:I2C0 Error
+        DCD     I2C1_EV_IRQHandler                  ; 49:I2C1 Event
+        DCD     I2C1_ER_IRQHandler                  ; 50:I2C1 Error
+        DCD     SPI0_IRQHandler                     ; 51:SPI0
+        DCD     SPI1_IRQHandler                     ; 52:SPI1/I2S1
+        DCD     USART0_IRQHandler                   ; 53:USART0
+        DCD     USART1_IRQHandler                   ; 54:USART1
+        DCD     USART2_IRQHandler                   ; 55:USART2
+        DCD     EXTI10_15_IRQHandler                ; 56:EXTI10 to EXTI15
+        DCD     RTC_Alarm_IRQHandler                ; 57:RTC Alarm
+        DCD     PVM_IRQHandler                      ; 58:EXTI[18](PVMO)
+        DCD     0                                   ; 59:Reserved
+        DCD     TIMER15_IRQHandler                  ; 60:TIMER15
+        DCD     TIMER16_IRQHandler                  ; 61:TIMER16
+        DCD     0                                   ; 62:Reserved
+        DCD     0                                   ; 63:Reserved
+        DCD     0                                   ; 64:Reserved
+        DCD     SDIO_IRQHandler                     ; 65:SDIO
+        DCD     TIMER4_IRQHandler                   ; 66:TIMER4
+        DCD     I2C0_WKUP_IRQHandler                ; 67:I2C0 Wakeup
+        DCD     USART0_WKUP_IRQHandler              ; 68:USART0 Wakeup
+        DCD     USART2_WKUP_IRQHandler              ; 69:USART2 Wakeup
+        DCD     TIMER5_IRQHandler                   ; 70:TIMER5
+        DCD     0                                   ; 71:Reserved
+        DCD     DMA1_Channel0_IRQHandler            ; 72:DMA1 Channel0
+        DCD     DMA1_Channel1_IRQHandler            ; 73:DMA1 Channel1
+        DCD     DMA1_Channel2_IRQHandler            ; 74:DMA1 Channel2
+        DCD     DMA1_Channel3_IRQHandler            ; 75:DMA1 Channel3
+        DCD     DMA1_Channel4_IRQHandler            ; 76:DMA1 Channel4
+        DCD     DMA1_Channel5_IRQHandler            ; 77:DMA1 Channel5
+        DCD     DMA1_Channel6_IRQHandler            ; 78:DMA1 Channel6
+        DCD     DMA1_Channel7_IRQHandler            ; 79:DMA1 Channel7
+        DCD     0                                   ; 80:Reserved
+        DCD     0                                   ; 81:Reserved
+        DCD     WLAN_WKUP_IRQHandler                ; 82:WIFI11N wakeup interrupt
+        DCD     USBFS_IRQHandler                    ; 83:USBFS global interrupt
+        DCD     0                                   ; 84:Reserved
+        DCD     0                                   ; 85:Reserved
+        DCD     0                                   ; 86:Reserved
+        DCD     0                                   ; 87:Reserved
+        DCD     0                                   ; 88:Reserved
+        DCD     0                                   ; 89:Reserved
+        DCD     0                                   ; 90:Reserved
+        DCD     0                                   ; 91:Reserved
+        DCD     USBFS_WKUP_IRQHandler               ; 92:USBFS_WKUP
+        DCD     0                                   ; 93:Reserved
+        DCD     DCI_IRHandler                       ; 94:DCI
+        DCD     CAU_IRQHandler                      ; 95:CAU
+        DCD     HAU_TRNG_IRQHandler                 ; 96:HAU and TRNG
+        DCD     FPU_IRQHandler                      ; 97:FPU
+        DCD     0                                   ; 98:Reserved
+        DCD     0                                   ; 99:Reserved
+        DCD     0                                   ; 100:Reserved
+        DCD     0                                   ; 101:Reserved
+        DCD     0                                   ; 102:Reserved
+        DCD     0                                   ; 103:Reserved
+        DCD     0                                   ; 104:Reserved
+        DCD     HPDF_INT0_IRQHandler                ; 105:HPDF global Interrupt 0
+        DCD     HPDF_INT1_IRQHandler                ; 106:HPDF global Interrupt 1
+        DCD     WLAN_Rx_IRQHandler                  ; 107:WIFI11N global interrupt0
+        DCD     WLAN_Tx_IRQHandler                  ; 108:WIFI11N global interrupt1
+        DCD     WLAN_Cmn_IRQHandler                 ; 109:WIFI11N global interrupt2
+        DCD     EFUSE_IRQHandler                    ; 110:EFUSE
+        DCD     QSPI_IRQHandler                     ; 111:QUADSPI1
+        DCD     PKCAU_IRQHandler                    ; 112:PKCAU
+        DCD     TSI_IRQHandler                      ; 113:TSI
+        DCD     ICACHE_IRQHandler                   ; 114:ICACHE
+        DCD     TZIAC_S_IRQHandler                  ; 115:TrustZone Interrupt Controller secure interrupts
+        DCD     FMC_S_IRQHandler                    ; 116:FMC
+        DCD     QSPI_S_IRQHandler                   ; 117:QSPI security interrupt
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SecureFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SecureFault_Handler
+        B SecureFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDGT_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDGT_IRQHandler
+        B WWDGT_IRQHandler
+
+        PUBWEAK LVD_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LVD_IRQHandler
+        B LVD_IRQHandler
+
+        PUBWEAK TAMPER_STAMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMPER_STAMP_IRQHandler
+        B TAMPER_STAMP_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FMC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FMC_IRQHandler
+        B FMC_IRQHandler
+
+        PUBWEAK RCU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCU_IRQHandler
+        B RCU_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK DMA0_Channel0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA0_Channel0_IRQHandler
+        B DMA0_Channel0_IRQHandler
+
+        PUBWEAK DMA0_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA0_Channel1_IRQHandler
+        B DMA0_Channel1_IRQHandler
+
+        PUBWEAK DMA0_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA0_Channel2_IRQHandler
+        B DMA0_Channel2_IRQHandler
+
+        PUBWEAK DMA0_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA0_Channel3_IRQHandler
+        B DMA0_Channel3_IRQHandler
+
+        PUBWEAK DMA0_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA0_Channel4_IRQHandler
+        B DMA0_Channel4_IRQHandler
+
+        PUBWEAK DMA0_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA0_Channel5_IRQHandler
+        B DMA0_Channel5_IRQHandler
+
+        PUBWEAK DMA0_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA0_Channel6_IRQHandler
+        B DMA0_Channel6_IRQHandler
+
+        PUBWEAK DMA0_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA0_Channel7_IRQHandler
+        B DMA0_Channel7_IRQHandler
+
+        PUBWEAK ADC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC_IRQHandler
+        B ADC_IRQHandler
+
+        PUBWEAK TAMP_STAMP_S_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_S_IRQHandler
+        B TAMP_STAMP_S_IRQHandler
+
+        PUBWEAK RTC_WKUP_S_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_S_IRQHandler
+        B RTC_WKUP_S_IRQHandler
+
+        PUBWEAK RTC_Alarm_S_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_S_IRQHandler
+        B RTC_Alarm_S_IRQHandler
+
+        PUBWEAK EXTI5_9_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI5_9_IRQHandler
+        B EXTI5_9_IRQHandler
+
+        PUBWEAK TIMER0_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER0_BRK_IRQHandler
+        B TIMER0_BRK_IRQHandler
+
+        PUBWEAK TIMER0_UP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER0_UP_IRQHandler
+        B TIMER0_UP_IRQHandler
+
+        PUBWEAK TIMER0_CMT_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER0_CMT_IRQHandler
+        B TIMER0_CMT_IRQHandler
+
+        PUBWEAK TIMER0_Channel_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER0_Channel_IRQHandler
+        B TIMER0_Channel_IRQHandler
+
+        PUBWEAK TIMER1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER1_IRQHandler
+        B TIMER1_IRQHandler
+
+        PUBWEAK TIMER2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER2_IRQHandler
+        B TIMER2_IRQHandler
+
+        PUBWEAK TIMER3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER3_IRQHandler
+        B TIMER3_IRQHandler
+
+        PUBWEAK I2C0_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C0_EV_IRQHandler
+        B I2C0_EV_IRQHandler
+
+        PUBWEAK I2C0_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C0_ER_IRQHandler
+        B I2C0_ER_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK SPI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI0_IRQHandler
+        B SPI0_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK USART0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART0_IRQHandler
+        B USART0_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK USART2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+        B USART2_IRQHandler
+
+        PUBWEAK EXTI10_15_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI10_15_IRQHandler
+        B EXTI10_15_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVM_IRQHandler
+        B PVM_IRQHandler
+
+        PUBWEAK TIMER15_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER15_IRQHandler
+        B TIMER15_IRQHandler
+
+        PUBWEAK TIMER16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER16_IRQHandler
+        B TIMER16_IRQHandler
+
+        PUBWEAK SDIO_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SDIO_IRQHandler
+        B SDIO_IRQHandler
+
+        PUBWEAK TIMER4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER4_IRQHandler
+        B TIMER4_IRQHandler
+
+        PUBWEAK I2C0_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C0_WKUP_IRQHandler
+        B I2C0_WKUP_IRQHandler
+
+        PUBWEAK USART0_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART0_WKUP_IRQHandler
+        B USART0_WKUP_IRQHandler
+
+        PUBWEAK USART2_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_WKUP_IRQHandler
+        B USART2_WKUP_IRQHandler
+
+        PUBWEAK TIMER5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER5_IRQHandler
+        B TIMER5_IRQHandler
+
+        PUBWEAK UART4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART4_IRQHandler
+        B UART4_IRQHandler
+
+        PUBWEAK TIMER5_DAC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER5_DAC_IRQHandler
+        B TIMER5_DAC_IRQHandler
+
+        PUBWEAK DMA1_Channel0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel0_IRQHandler
+        B DMA1_Channel0_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK WLAN_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WLAN_WKUP_IRQHandler
+        B WLAN_WKUP_IRQHandler
+
+        PUBWEAK USBFS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USBFS_IRQHandler
+        B USBFS_IRQHandler
+
+        PUBWEAK USBFS_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USBFS_WKUP_IRQHandler
+        B USBFS_WKUP_IRQHandler
+
+        PUBWEAK DCI_IRHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DCI_IRHandler
+        B DCI_IRHandler
+
+        PUBWEAK CAU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CAU_IRQHandler
+        B CAU_IRQHandler
+
+        PUBWEAK HAU_TRNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HAU_TRNG_IRQHandler
+        B HAU_TRNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK HPDF_INT0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HPDF_INT0_IRQHandler
+        B HPDF_INT0_IRQHandler
+
+        PUBWEAK HPDF_INT1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HPDF_INT1_IRQHandler
+        B HPDF_INT1_IRQHandler
+
+        PUBWEAK WLAN_Rx_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WLAN_Rx_IRQHandler
+        B WLAN_Rx_IRQHandler
+
+        PUBWEAK WLAN_Tx_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WLAN_Tx_IRQHandler
+        B WLAN_Tx_IRQHandler
+
+        PUBWEAK WLAN_Cmn_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WLAN_Cmn_IRQHandler
+        B WLAN_Cmn_IRQHandler
+
+        PUBWEAK EFUSE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EFUSE_IRQHandler
+        B EFUSE_IRQHandler
+
+        PUBWEAK QSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QSPI_IRQHandler
+        B QSPI_IRQHandler
+
+        PUBWEAK PKCAU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKCAU_IRQHandler
+        B PKCAU_IRQHandler
+
+        PUBWEAK TSI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSI_IRQHandler
+        B TSI_IRQHandler
+
+        PUBWEAK ICACHE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ICACHE_IRQHandler
+        B ICACHE_IRQHandler
+
+        PUBWEAK TZIAC_S_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TZIAC_S_IRQHandler
+        B TZIAC_S_IRQHandler
+
+        PUBWEAK FMC_S_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FMC_S_IRQHandler
+        B FMC_S_IRQHandler
+
+        PUBWEAK QSPI_S_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QSPI_S_IRQHandler
+        B QSPI_S_IRQHandler
+
+        END

MBL/platform/mbl_region.h

@@ -0,0 +1,74 @@
+/*!
+    \file    mbl_region.h
+    \brief   MBL region definition for GD32W51x WiFi SDK
+
+    \version 2021-10-30, V1.0.0, firmware for GD32W51x
+*/
+
+/*
+    Copyright (c) 2021, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice,
+       this list of conditions and the following disclaimer in the documentation
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors
+       may be used to endorse or promote products derived from this software without
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#ifndef __MBL_REGION_H__
+#define __MBL_REGION_H__
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#if defined(PLATFORM_MSP_AN521)
+#include "config_an521.h"
+#elif defined(PLATFORM_GDM32)
+#include "config_gdm32.h"
+#endif
+
+/* MBL: code and ro data */
+#define MBL_BASE_ADDRESS                 (RE_FLASH_BASE_S + RE_MBL_OFFSET + RE_VTOR_ALIGNMENT)
+#define MBL_CODE_START                   MBL_BASE_ADDRESS
+#define MBL_CODE_SIZE                    (28 * 1024 - RE_VTOR_ALIGNMENT)   /* 28 KB */
+
+/* SRAM: shared SRAM, store initial boot state */
+#define MBL_SHARED_DATA_START            (RE_SRAM_BASE_S + RE_SHARED_DATA_START)  // the same as IBL_SHARED_DATA_START
+#define MBL_SHARED_DATA_SIZE             (RE_MBL_DATA_START - RE_SHARED_DATA_START)
+
+/* SRAM: STACK, HEAP and other Global varaiables */
+#define MBL_DATA_START                   (RE_SRAM_BASE_S + RE_MBL_DATA_START)  /* skip rom variables and shared data */
+#define MBL_BUF_SIZE                     0x3000
+#define MBL_MSP_STACK_SIZE               0x400
+#else  /* __ARM_FEATURE_CMSE */
+#include "config_gdm32_ntz.h"
+
+/* MBL: code and ro data */
+#define MBL_BASE_ADDRESS                 RE_FLASH_BASE_NS
+#define MBL_CODE_START                   MBL_BASE_ADDRESS
+#define MBL_CODE_SIZE                    (31 * 1024)   /* 31 KB */
+#define MBL_API_START                    (MBL_BASE_ADDRESS + 31 * 1024)
+#define MBL_API_SIZE                     (256)          /* unit: byte, skip lock word */
+
+/* SRAM: Global varaiables, STACK, HEAP*/
+#define MBL_DATA_START                    (RE_SRAM_BASE_NS + RE_MBL_DATA_START)  /* skip rom variables */
+#define MBL_MSP_STACK_SIZE                0x1000
+
+#endif  /* __ARM_FEATURE_CMSE */
+
+#endif  // __MBL_REGION_H__

MBL/project/IAR/mbl_prebuild.bat

@@ -0,0 +1,28 @@
+@echo off
+:: Preprocess to generate ICF file
+set TZ=%1
+set PROJ_DIR=%2
+set TOOLKIT_DIR=%3
+
+if "%TZ%" == "TZ" (
+    set IFILE=%PROJ_DIR%\..\..\platform\gdm32\iar\mbl_gdm32.i
+    set OFILE=%PROJ_DIR%\mbl_gdm32.icf
+    set CMSE=-D__ARM_FEATURE_CMSE=3
+) else (
+    set IFILE=%PROJ_DIR%\..\..\platform\gdm32\iar\mbl_gdm32_ns.i
+    set OFILE=%PROJ_DIR%\mbl_gdm32_ns.icf
+    set CMSE=
+)
+
+
+IF EXIST %OFILE%  del %OFILE%
+%TOOLKIT_DIR%\bin\iccarm.exe %IFILE% ^
+                             --preprocess=sn ^
+                             %OFILE% ^
+                             -I %PROJ_DIR%\..\..\..\config ^
+                             -I %PROJ_DIR%\..\..\platform %CMSE%
+
+:: set CONFIG_FILE=%1
+:: echo /* config_gdm32*.h symbol list */ > %PROJ_DIR%\..\..\platform\gdm32\iar\%CONFIG_FILE%.icf
+:: for /f "eol=/ tokens=1,2,3" %%i in (%PROJ_DIR%\..\..\..\..\config\%CONFIG_FILE%.h ) 
+::      do echo define exported symbol %%j = %%k; >> %PROJ_DIR%\..\..\platform\gdm32\iar\%CONFIG_FILE%.icf

MBL/project/KEIL/Project_MBL.uvoptx

@@ -0,0 +1,648 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
+
+  <SchemaVersion>1.0</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Extensions>
+    <cExt>*.c</cExt>
+    <aExt>*.s*; *.src; *.a*</aExt>
+    <oExt>*.obj; *.o</oExt>
+    <lExt>*.lib</lExt>
+    <tExt>*.txt; *.h; *.inc</tExt>
+    <pExt>*.plm</pExt>
+    <CppX>*.cpp</CppX>
+    <nMigrate>0</nMigrate>
+  </Extensions>
+
+  <DaveTm>
+    <dwLowDateTime>0</dwLowDateTime>
+    <dwHighDateTime>0</dwHighDateTime>
+  </DaveTm>
+
+  <Target>
+    <TargetName>Target_AN521</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>12000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>0</RunSim>
+        <RunTarget>1</RunTarget>
+        <RunAbUc>0</RunAbUc>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\An521\Listings\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>0</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>7</CpuCode>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>0</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>1</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <bEvRecOn>1</bEvRecOn>
+        <bSchkAxf>0</bSchkAxf>
+        <bTchkAxf>0</bTchkAxf>
+        <nTsel>20</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile>.\mbl.ini</tIfile>
+        <pMon>BIN\DbgFMv8M.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DbgFMv8M</Key>
+          <Name>-I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M33_MDK.exe" -MF".\ARMCM33_TZ_config.txt" -MA</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2V8M</Key>
+          <Name>UL2V8M(-S0 -C0 -P0  -FC1000 -FD20000000</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGTARM</Key>
+          <Name>(6010=-1,-1,-1,-1,0)(6018=-1,-1,-1,-1,0)(6019=-1,-1,-1,-1,0)(6008=-1,-1,-1,-1,0)(6009=-1,-1,-1,-1,0)(6014=-1,-1,-1,-1,0)(6015=-1,-1,-1,-1,0)(6003=-1,-1,-1,-1,0)(6000=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>ARMDBGFLAGS</Key>
+          <Name></Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGUARM</Key>
+          <Name>(105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <WatchWindow1>
+        <Ww>
+          <count>0</count>
+          <WinNumber>1</WinNumber>
+          <ItemText>uart_buf</ItemText>
+        </Ww>
+        <Ww>
+          <count>1</count>
+          <WinNumber>1</WinNumber>
+          <ItemText>&amp;major</ItemText>
+        </Ww>
+      </WatchWindow1>
+      <MemoryWindow1>
+        <Mm>
+          <WinNumber>1</WinNumber>
+          <SubType>0</SubType>
+          <ItemText>0x38005F04</ItemText>
+          <AccSizeX>0</AccSizeX>
+        </Mm>
+      </MemoryWindow1>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>1</periodic>
+        <aLwin>1</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>1</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+      <bLintAuto>0</bLintAuto>
+      <bAutoGenD>0</bAutoGenD>
+      <LntExFlags>0</LntExFlags>
+      <pMisraName></pMisraName>
+      <pszMrule></pszMrule>
+      <pSingCmds></pSingCmds>
+      <pMultCmds></pMultCmds>
+      <pMisraNamep></pMisraNamep>
+      <pszMrulep></pszMrulep>
+      <pSingCmdsp></pSingCmdsp>
+      <pMultCmdsp></pMultCmdsp>
+    </TargetOption>
+  </Target>
+
+  <Target>
+    <TargetName>Target_GDM32</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>12000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>0</RunSim>
+        <RunTarget>1</RunTarget>
+        <RunAbUc>0</RunAbUc>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\mbl\Listings\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>1</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>7</CpuCode>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>1</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <bEvRecOn>1</bEvRecOn>
+        <bSchkAxf>0</bSchkAxf>
+        <bTchkAxf>0</bTchkAxf>
+        <nTsel>4</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile>.\mbl.ini</tIfile>
+        <pMon>Segger\JL2CM3.dll</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2V8M</Key>
+          <Name>UL2V8M(-S0 -C0 -P0  -FC1000 -FD20000000</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>JL2CM3</Key>
+          <Name>-U59406895 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BE12477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO0 -FD20000000 -FC8000 -FN0</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGUARM</Key>
+          <Name></Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGTARM</Key>
+          <Name>(6010=-1,-1,-1,-1,0)(6018=-1,-1,-1,-1,0)(6019=-1,-1,-1,-1,0)(6008=-1,-1,-1,-1,0)(6009=-1,-1,-1,-1,0)(6014=-1,-1,-1,-1,0)(6015=-1,-1,-1,-1,0)(6003=-1,-1,-1,-1,0)(6000=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>ARMDBGFLAGS</Key>
+          <Name></Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <MemoryWindow1>
+        <Mm>
+          <WinNumber>1</WinNumber>
+          <SubType>2</SubType>
+          <ItemText>0x08001200</ItemText>
+          <AccSizeX>0</AccSizeX>
+        </Mm>
+      </MemoryWindow1>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>1</periodic>
+        <aLwin>1</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>1</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+      <bLintAuto>0</bLintAuto>
+      <bAutoGenD>0</bAutoGenD>
+      <LntExFlags>0</LntExFlags>
+      <pMisraName></pMisraName>
+      <pszMrule></pszMrule>
+      <pSingCmds></pSingCmds>
+      <pMultCmds></pMultCmds>
+      <pMisraNamep></pMisraNamep>
+      <pszMrulep></pszMrulep>
+      <pSingCmdsp></pSingCmdsp>
+      <pMultCmdsp></pMultCmdsp>
+    </TargetOption>
+  </Target>
+
+  <Group>
+    <GroupName>bootloader</GroupName>
+    <tvExp>0</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>0</RteFlg>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>1</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\source\mbl.c</PathWithFileName>
+      <FilenameWithoutPath>mbl.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>2</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\source\mbl_image_validate.c</PathWithFileName>
+      <FilenameWithoutPath>mbl_image_validate.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>3</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\source\mbl_status.c</PathWithFileName>
+      <FilenameWithoutPath>mbl_status.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>4</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\source\mbl_target_config.c</PathWithFileName>
+      <FilenameWithoutPath>mbl_target_config.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>5</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\source\mbl_nsc_api.c</PathWithFileName>
+      <FilenameWithoutPath>mbl_nsc_api.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>6</FileNumber>
+      <FileType>4</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\ROM\project\MDK-ARM\rom_symbol_mbedtls</PathWithFileName>
+      <FilenameWithoutPath>rom_symbol_mbedtls</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>7</FileNumber>
+      <FileType>4</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\ROM-EXPORT\symbol\rom_symbol_mbedtls_20200709</PathWithFileName>
+      <FilenameWithoutPath>rom_symbol_mbedtls_20200709</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+  </Group>
+
+  <Group>
+    <GroupName>an521</GroupName>
+    <tvExp>0</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>0</RteFlg>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>8</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\platform\msp2-an521\cmsis_core\mbl_system_an521.c</PathWithFileName>
+      <FilenameWithoutPath>mbl_system_an521.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>9</FileNumber>
+      <FileType>2</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\platform\msp2-an521\armclang\mbl_startup_an521.s</PathWithFileName>
+      <FilenameWithoutPath>mbl_startup_an521.s</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+  </Group>
+
+  <Group>
+    <GroupName>gdm32</GroupName>
+    <tvExp>0</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>0</RteFlg>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>10</FileNumber>
+      <FileType>2</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\platform\gdm32\armclang\mbl_startup_gdm32.s</PathWithFileName>
+      <FilenameWithoutPath>mbl_startup_gdm32.s</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>11</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\platform\gdm32\cmsis_core\mbl_system_gdm32.c</PathWithFileName>
+      <FilenameWithoutPath>mbl_system_gdm32.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>12</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\NSPE\Firmware\GD32W51x_standard_peripheral\Source\gd32w51x_fmc.c</PathWithFileName>
+      <FilenameWithoutPath>gd32w51x_fmc.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>13</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\NSPE\Firmware\GD32W51x_standard_peripheral\Source\gd32w51x_gpio.c</PathWithFileName>
+      <FilenameWithoutPath>gd32w51x_gpio.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>14</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\NSPE\Firmware\GD32W51x_standard_peripheral\Source\gd32w51x_icache.c</PathWithFileName>
+      <FilenameWithoutPath>gd32w51x_icache.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>15</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\NSPE\Firmware\GD32W51x_standard_peripheral\Source\gd32w51x_misc.c</PathWithFileName>
+      <FilenameWithoutPath>gd32w51x_misc.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>16</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\NSPE\Firmware\GD32W51x_standard_peripheral\Source\gd32w51x_rcu.c</PathWithFileName>
+      <FilenameWithoutPath>gd32w51x_rcu.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>17</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\NSPE\Firmware\GD32W51x_standard_peripheral\Source\gd32w51x_usart.c</PathWithFileName>
+      <FilenameWithoutPath>gd32w51x_usart.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>18</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\NSPE\Firmware\GD32W51x_standard_peripheral\Source\gd32w51x_tzpcu.c</PathWithFileName>
+      <FilenameWithoutPath>gd32w51x_tzpcu.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>19</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\platform\gdm32\gd32w51x_it.c</PathWithFileName>
+      <FilenameWithoutPath>gd32w51x_it.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+  </Group>
+
+  <Group>
+    <GroupName>::CMSIS</GroupName>
+    <tvExp>0</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>1</RteFlg>
+  </Group>
+
+</ProjectOpt>

MBL/project/KEIL/Project_MBL_NS.uvoptx

@@ -0,0 +1,453 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
+
+  <SchemaVersion>1.0</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Extensions>
+    <cExt>*.c</cExt>
+    <aExt>*.s*; *.src; *.a*</aExt>
+    <oExt>*.obj; *.o</oExt>
+    <lExt>*.lib</lExt>
+    <tExt>*.txt; *.h; *.inc</tExt>
+    <pExt>*.plm</pExt>
+    <CppX>*.cpp</CppX>
+    <nMigrate>0</nMigrate>
+  </Extensions>
+
+  <DaveTm>
+    <dwLowDateTime>0</dwLowDateTime>
+    <dwHighDateTime>0</dwHighDateTime>
+  </DaveTm>
+
+  <Target>
+    <TargetName>Target_GDM32</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>12000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>0</RunSim>
+        <RunTarget>1</RunTarget>
+        <RunAbUc>0</RunAbUc>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\mbl_ns\Listings\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>1</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>255</CpuCode>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>0</tLdApp>
+        <tGomain>0</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>1</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <bEvRecOn>1</bEvRecOn>
+        <bSchkAxf>0</bSchkAxf>
+        <bTchkAxf>0</bTchkAxf>
+        <nTsel>15</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile>.\mbl_ns.ini</tIfile>
+        <pMon>BIN\CMSIS_AGDI_V8M.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>CMSIS_AGDI_V8M</Key>
+          <Name>-X"Any" -UAny -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BE12477) -L00(0) -TO18 -TC10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC2000 -FN1 -FF0GD32W515_NS -FS08000000 -FL0200000 -FP0($$Device:GD32W515PIQ6$Flash\GD32W515_NS.FLM)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2V8M</Key>
+          <Name>UL2V8M(-S0 -C0 -P0  -FN2 -FC1000 -FD20000000 -FF0GD32W515_NS -FF1GD32W515_S -FL02000 -FL12000 -FS08000000 -FS1C000000 -FP0($$Device:GD32W515PIQ6$Flash\GD32W515_NS.FLM) -FP1($$Device:GD32W515PIQ6$Flash\GD32W515_S.FLM)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>JL2CM3</Key>
+          <Name>-U69662772 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD20000000 -FC2000 -FN1 -FF0GD32W515_NS.FLM -FS08000000 -FL0200000 -FP0($$Device:GD32W515PIQ6$Flash\GD32W515_NS.FLM)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGUARM</Key>
+          <Name></Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGTARM</Key>
+          <Name>(6010=234,272,711,868,0)(6018=105,137,294,470,0)(6019=105,137,294,457,0)(6008=-1,-1,-1,-1,0)(6009=-1,-1,-1,-1,0)(6014=-1,-1,-1,-1,0)(6015=-1,-1,-1,-1,0)(6003=135,169,708,705,0)(6000=75,104,528,436,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>ARMDBGFLAGS</Key>
+          <Name></Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <MemoryWindow1>
+        <Mm>
+          <WinNumber>1</WinNumber>
+          <SubType>2</SubType>
+          <ItemText>0x08000000</ItemText>
+          <AccSizeX>0</AccSizeX>
+        </Mm>
+      </MemoryWindow1>
+      <MemoryWindow2>
+        <Mm>
+          <WinNumber>2</WinNumber>
+          <SubType>2</SubType>
+          <ItemText>0x08007c00</ItemText>
+          <AccSizeX>0</AccSizeX>
+        </Mm>
+      </MemoryWindow2>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>1</periodic>
+        <aLwin>1</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>1</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+      <bLintAuto>0</bLintAuto>
+      <bAutoGenD>0</bAutoGenD>
+      <LntExFlags>0</LntExFlags>
+      <pMisraName></pMisraName>
+      <pszMrule></pszMrule>
+      <pSingCmds></pSingCmds>
+      <pMultCmds></pMultCmds>
+      <pMisraNamep></pMisraNamep>
+      <pszMrulep></pszMrulep>
+      <pSingCmdsp></pSingCmdsp>
+      <pMultCmdsp></pMultCmdsp>
+    </TargetOption>
+  </Target>
+
+  <Group>
+    <GroupName>bootloader</GroupName>
+    <tvExp>0</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>0</RteFlg>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>1</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\source_ns\mbl_flash.c</PathWithFileName>
+      <FilenameWithoutPath>mbl_flash.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>2</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\source_ns\mbl_image.c</PathWithFileName>
+      <FilenameWithoutPath>mbl_image.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>3</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\source_ns\mbl_ns.c</PathWithFileName>
+      <FilenameWithoutPath>mbl_ns.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>4</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\source_ns\mbl_sys.c</PathWithFileName>
+      <FilenameWithoutPath>mbl_sys.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>5</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\source_ns\mbl_uart.c</PathWithFileName>
+      <FilenameWithoutPath>mbl_uart.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>6</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\source_ns\mbl_api.c</PathWithFileName>
+      <FilenameWithoutPath>mbl_api.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>7</FileNumber>
+      <FileType>4</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\ROM-EXPORT\symbol\rom_symbol_mbedtls_20200709</PathWithFileName>
+      <FilenameWithoutPath>rom_symbol_mbedtls_20200709</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>8</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\source_ns\mbl_qspi_flash.c</PathWithFileName>
+      <FilenameWithoutPath>mbl_qspi_flash.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+  </Group>
+
+  <Group>
+    <GroupName>gdm32</GroupName>
+    <tvExp>0</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>0</RteFlg>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>9</FileNumber>
+      <FileType>2</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\platform\gdm32\armclang\mbl_startup_gdm32.s</PathWithFileName>
+      <FilenameWithoutPath>mbl_startup_gdm32.s</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>10</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\platform\gdm32\cmsis_core\mbl_system_gdm32.c</PathWithFileName>
+      <FilenameWithoutPath>mbl_system_gdm32.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>11</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\NSPE\Firmware\GD32W51x_standard_peripheral\Source\gd32w51x_fmc.c</PathWithFileName>
+      <FilenameWithoutPath>gd32w51x_fmc.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>12</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\NSPE\Firmware\GD32W51x_standard_peripheral\Source\gd32w51x_fwdgt.c</PathWithFileName>
+      <FilenameWithoutPath>gd32w51x_fwdgt.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>13</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\NSPE\Firmware\GD32W51x_standard_peripheral\Source\gd32w51x_gpio.c</PathWithFileName>
+      <FilenameWithoutPath>gd32w51x_gpio.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>14</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\NSPE\Firmware\GD32W51x_standard_peripheral\Source\gd32w51x_icache.c</PathWithFileName>
+      <FilenameWithoutPath>gd32w51x_icache.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>15</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\NSPE\Firmware\GD32W51x_standard_peripheral\Source\gd32w51x_qspi.c</PathWithFileName>
+      <FilenameWithoutPath>gd32w51x_qspi.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>16</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\NSPE\Firmware\GD32W51x_standard_peripheral\Source\gd32w51x_rcu.c</PathWithFileName>
+      <FilenameWithoutPath>gd32w51x_rcu.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>17</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\NSPE\Firmware\GD32W51x_standard_peripheral\Source\gd32w51x_usart.c</PathWithFileName>
+      <FilenameWithoutPath>gd32w51x_usart.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>18</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\NSPE\Firmware\GD32W51x_standard_peripheral\Source\gd32w51x_misc.c</PathWithFileName>
+      <FilenameWithoutPath>gd32w51x_misc.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+  </Group>
+
+  <Group>
+    <GroupName>::CMSIS</GroupName>
+    <tvExp>0</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>1</RteFlg>
+  </Group>
+
+</ProjectOpt>

MBL/project/KEIL/Project_MBL_NS.uvprojx

@@ -0,0 +1,501 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
+
+  <SchemaVersion>2.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>Target_GDM32</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <pCCUsed>6090000::V6.9::.\ARMCLANG</pCCUsed>
+      <uAC6>1</uAC6>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>GD32W515PIQ6</Device>
+          <Vendor>GigaDevice</Vendor>
+          <PackID>GigaDevice.GD32W51x_DFP.1.0.2</PackID>
+          <PackURL>http://gd32mcu.com/data/documents/pack/</PackURL>
+          <Cpu>IRAM(0x20000000,0x70000) IRAM2(0x30000000,0x70000) IROM(0x08000000,0x0200000) IROM2(0x0C000000,0x0200000) CPUTYPE("Cortex-M33") FPU3(SFPU) DSP TZ CLOCK(12000000) ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll>UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000 -FN2 -FF0GD32W515_NS -FS08000000 -FL02000 -FF1GD32W515_S -FS1C000000 -FL12000 -FP0($$Device:GD32W515PIQ6$Flash\GD32W515_NS.FLM) -FP1($$Device:GD32W515PIQ6$Flash\GD32W515_S.FLM))</FlashDriverDll>
+          <DeviceId>0</DeviceId>
+          <RegisterFile>$$Device:GD32W515PIQ6$Device\Include\gd32w51x.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>$$Device:GD32W515PIQ6$SVD\GD32W515Px.svd</SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\mbl_ns\Objects\</OutputDirectory>
+          <OutputName>mbl-ns</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath>.\mbl_ns\Listings\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopB1X>0</nStopB1X>
+            <nStopB2X>0</nStopB2X>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>1</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name>..\mbl_afterbuild.bat  $L @L KEIL $K</UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopA1X>0</nStopA1X>
+            <nStopA2X>0</nStopA2X>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName></SimDllName>
+          <SimDllArguments></SimDllArguments>
+          <SimDlgDll></SimDlgDll>
+          <SimDlgDllArguments></SimDlgDllArguments>
+          <TargetDllName>SARMV8M.DLL</TargetDllName>
+          <TargetDllArguments> -MPU</TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM33</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4099</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2V8M.DLL</Flash2>
+          <Flash3></Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M33"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>2</RvdsVP>
+            <hadIRAM2>1</hadIRAM2>
+            <hadIROM2>1</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>1</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <nSecure>0</nSecure>
+            <RoSelD>4</RoSelD>
+            <RwSelD>4</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x70000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x8000000</StartAddress>
+                <Size>0x200000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x8000000</StartAddress>
+                <Size>0x200000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0xc000000</StartAddress>
+                <Size>0x200000</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x70000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x30000000</StartAddress>
+                <Size>0x70000</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>3</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>1</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>3</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>0</uC99>
+            <uGnu>0</uGnu>
+            <useXO>0</useXO>
+            <v6Lang>3</v6Lang>
+            <v6LangP>3</v6LangP>
+            <vShortEn>0</vShortEn>
+            <vShortWch>0</vShortWch>
+            <v6Lto>0</v6Lto>
+            <v6WtE>0</v6WtE>
+            <v6Rtti>0</v6Rtti>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define>PLATFORM_GDM32</Define>
+              <Undefine></Undefine>
+              <IncludePath>..\..\source_ns;..\..\platform;..\..\platform\gdm32;..\..\..\config;..\..\..\ROM-EXPORT\mbedtls-2.17.0-rom\include;..\..\..\ROM-EXPORT\platform;..\..\..\ROM-EXPORT\source;..\..\..\NSPE\Firmware\CMSIS\GD\GD32W51x\Include;..\..\..\NSPE\Firmware\GD32W51x_standard_peripheral\Include</IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <useXO>0</useXO>
+            <uClangAs>0</uClangAs>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>0</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x00000000</TextAddressRange>
+            <DataAddressRange>0x20000000</DataAddressRange>
+            <pXoBase></pXoBase>
+            <ScatterFile>..\..\platform\gdm32\armclang\mbl_gdm32_ns.sct</ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc>--predefine="-DPLATFORM_GDM32"  --keep=mbl_api</Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>bootloader</GroupName>
+          <Files>
+            <File>
+              <FileName>mbl_flash.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\source_ns\mbl_flash.c</FilePath>
+            </File>
+            <File>
+              <FileName>mbl_image.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\source_ns\mbl_image.c</FilePath>
+            </File>
+            <File>
+              <FileName>mbl_ns.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\source_ns\mbl_ns.c</FilePath>
+            </File>
+            <File>
+              <FileName>mbl_sys.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\source_ns\mbl_sys.c</FilePath>
+            </File>
+            <File>
+              <FileName>mbl_uart.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\source_ns\mbl_uart.c</FilePath>
+            </File>
+            <File>
+              <FileName>mbl_api.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\source_ns\mbl_api.c</FilePath>
+            </File>
+            <File>
+              <FileName>rom_symbol_mbedtls_20200709</FileName>
+              <FileType>4</FileType>
+              <FilePath>..\..\..\ROM-EXPORT\symbol\rom_symbol_mbedtls_20200709</FilePath>
+            </File>
+            <File>
+              <FileName>mbl_qspi_flash.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\source_ns\mbl_qspi_flash.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>gdm32</GroupName>
+          <Files>
+            <File>
+              <FileName>mbl_startup_gdm32.s</FileName>
+              <FileType>2</FileType>
+              <FilePath>..\..\platform\gdm32\armclang\mbl_startup_gdm32.s</FilePath>
+            </File>
+            <File>
+              <FileName>mbl_system_gdm32.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\platform\gdm32\cmsis_core\mbl_system_gdm32.c</FilePath>
+            </File>
+            <File>
+              <FileName>gd32w51x_fmc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\NSPE\Firmware\GD32W51x_standard_peripheral\Source\gd32w51x_fmc.c</FilePath>
+            </File>
+            <File>
+              <FileName>gd32w51x_fwdgt.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\NSPE\Firmware\GD32W51x_standard_peripheral\Source\gd32w51x_fwdgt.c</FilePath>
+            </File>
+            <File>
+              <FileName>gd32w51x_gpio.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\NSPE\Firmware\GD32W51x_standard_peripheral\Source\gd32w51x_gpio.c</FilePath>
+            </File>
+            <File>
+              <FileName>gd32w51x_icache.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\NSPE\Firmware\GD32W51x_standard_peripheral\Source\gd32w51x_icache.c</FilePath>
+            </File>
+            <File>
+              <FileName>gd32w51x_qspi.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\NSPE\Firmware\GD32W51x_standard_peripheral\Source\gd32w51x_qspi.c</FilePath>
+            </File>
+            <File>
+              <FileName>gd32w51x_rcu.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\NSPE\Firmware\GD32W51x_standard_peripheral\Source\gd32w51x_rcu.c</FilePath>
+            </File>
+            <File>
+              <FileName>gd32w51x_usart.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\NSPE\Firmware\GD32W51x_standard_peripheral\Source\gd32w51x_usart.c</FilePath>
+            </File>
+            <File>
+              <FileName>gd32w51x_misc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\NSPE\Firmware\GD32W51x_standard_peripheral\Source\gd32w51x_misc.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>::CMSIS</GroupName>
+        </Group>
+      </Groups>
+    </Target>
+  </Targets>
+
+  <RTE>
+    <apis/>
+    <components>
+      <component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.5.0" condition="ARMv6_7_8-M Device">
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.8.0"/>
+        <targetInfos>
+          <targetInfo name="Target_GDM32"/>
+        </targetInfos>
+      </component>
+    </components>
+    <files/>
+  </RTE>
+
+</Project>

MBL/project/KEIL/mbl.ini

@@ -0,0 +1,6 @@
+//LOAD "..\\..\\..\\ROM-EXPORT\\symbol\\rom.axf"  incremental
+LOAD "..\\..\\..\\MBL\\project\\KEIL\\mbl\\Objects\\mbl.axf"  incremental
+LOAD "..\\..\\..\\PROT\\project\\KEIL\\secure_main\\Gdm32\\Objects\\prot.axf"  incremental
+LOAD "..\\..\\..\\NSPE\\Project\\WIFI_IOT\\KEIL\\nspe\\output\\nspe.axf"  incremental
+
+RESET

MBL/project/KEIL/mbl_ns.ini

@@ -0,0 +1,4 @@
+LOAD "mbl_ns\\Objects\\mbl-ns.axf"  incremental
+LOAD "..\\..\\..\\NSPE\\Project\\WIFI_IOT\\KEIL\\wifi_iot\\output\\nspe.axf"  incremental
+
+RESET

MBL/project/mbl_afterbuild.bat

@@ -0,0 +1,40 @@
+@echo off
+
+set OUTPUT_PATH=%1
+set OUTPUT_NAME=%2
+set TOOLKIT=%3
+set TOOLKIT_PATH=%4
+set "OUTPUT_PATH=%OUTPUT_PATH:/=\%"
+
+set ROOT=%OUTPUT_PATH%\..\..\..\..\..
+set SREC_CAT=%ROOT%\scripts\imgtool\srec_cat.exe
+set OUTPUT_IMAGE_PATH=%ROOT%\scripts\images
+
+
+
+if "%TOOLKIT%" == "KEIL" (
+    :: Generate txt for debug
+    %TOOLKIT_PATH%\ARM\ARMCC\bin\fromelf.exe --text -c -d --output=%OUTPUT_PATH%\..\%OUTPUT_NAME%.txt %OUTPUT_PATH%\%OUTPUT_NAME%.axf
+
+    :: Generate binary image
+    %TOOLKIT_PATH%\ARM\ARMCC\bin\fromelf.exe --bin --8x1  --bincombined --output=%OUTPUT_PATH%\..\%OUTPUT_NAME%.bin %OUTPUT_PATH%\%OUTPUT_NAME%.axf
+)
+if "%TOOLKIT%" == "IAR" (
+    :: Generate ASM file
+    %TOOLKIT_PATH%\bin\ielfdumparm.exe %OUTPUT_PATH%\%OUTPUT_NAME%.axf  --output %OUTPUT_PATH%\..\%OUTPUT_NAME%.asm --code
+
+    :: Generate binary image
+    %TOOLKIT_PATH%\bin\ielftool.exe %OUTPUT_PATH%\%OUTPUT_NAME%.axf  --bin %OUTPUT_PATH%\..\%OUTPUT_NAME%.bin
+)
+if "%TOOLKIT%" == "GCC" (
+    arm-none-eabi-objdump -xS  %OUTPUT_PATH%\%OUTPUT_NAME%.axf > %OUTPUT_PATH%\..\%OUTPUT_NAME%.txt
+    arm-none-eabi-objcopy -Obinary %OUTPUT_PATH%\%OUTPUT_NAME%.axf %OUTPUT_PATH%\..\%OUTPUT_NAME%.bin
+)
+
+IF EXIST %OUTPUT_IMAGE_PATH%\%OUTPUT_NAME%* del %OUTPUT_IMAGE_PATH%\%OUTPUT_NAME%*
+:: Copy to output image path
+copy %OUTPUT_PATH%\..\%OUTPUT_NAME%.bin %OUTPUT_IMAGE_PATH%\
+:: Generate Hex file
+%SREC_CAT%  %OUTPUT_IMAGE_PATH%\%OUTPUT_NAME%.bin -Binary -offset 0x0C000000 -o %OUTPUT_IMAGE_PATH%\%OUTPUT_NAME%.hex -Intel
+ 
+::exit

MBL/project/mbl_afterbuild_adv.bat

@@ -0,0 +1,87 @@
+@echo off
+set SIP=%1
+set AESK=%~2
+set DEBUGGER=%3
+set OUTPUT_PATH=%4
+set OUTPUT_NAME=%5
+set TOOLKIT=%6
+set TOOLKIT_PATH=%7
+
+set "OUTPUT_PATH=%OUTPUT_PATH:/=\%"
+
+set ROOT=%OUTPUT_PATH%\..\..\..\..\..
+set IMGTOOL=%ROOT%\scripts\imgtool\imgtool.py
+set AESTOOL=%ROOT%\scripts\imgtool\aestool.py
+set SREC_CAT=%ROOT%\scripts\imgtool\srec_cat.exe
+set DLTOOL=%ROOT%\scripts\imgtool\download.py
+set CONFIG_FILE=%ROOT%\config\config_gdm32_ntz.h
+set OUTPUT_HEX_PATH=%ROOT%\scripts\images
+set OUTPUT_FILE=%OUTPUT_PATH%\..\%OUTPUT_NAME%
+
+:: Save Orignal Working Path
+set WORK_PATH=%CD%
+
+if "%SIP%" == "SIP" (
+    set ALGO=GD32W51x
+) else (
+    set ALGO=GD32W51x_Q
+)
+
+if "%AESK%" NEQ "" (
+    set AES_SUFFIX=-aes
+) else (
+    set AES_SUFFIX=
+)
+
+if "%TOOLKIT%" == "KEIL" (
+    :: Generate txt for debug
+    %TOOLKIT_PATH%\ARM\ARMCC\bin\fromelf.exe --text -c -d --output=%OUTPUT_FILE%.txt %OUTPUT_PATH%\%OUTPUT_NAME%.axf
+
+    :: Generate binary image
+    %TOOLKIT_PATH%\ARM\ARMCC\bin\fromelf.exe --bin --8x1  --bincombined --output=%OUTPUT_FILE%.bin %OUTPUT_PATH%\%OUTPUT_NAME%.axf
+)
+if "%TOOLKIT%" == "IAR" (
+    :: Generate ASM file
+    %TOOLKIT_PATH%\bin\ielfdumparm.exe %OUTPUT_PATH%\%OUTPUT_NAME%.axf  --output %OUTPUT_FILE%.asm --code
+
+    :: Generate binary image
+    %TOOLKIT_PATH%\bin\ielftool.exe %OUTPUT_PATH%\%OUTPUT_NAME%.axf  --bin %OUTPUT_FILE%.bin
+)
+
+if "%TOOLKIT%" == "GCC" (
+    arm-none-eabi-objdump -xS  %OUTPUT_PATH%/%OUTPUT_NAME%.axf > %OUTPUT_FILE%.txt
+    arm-none-eabi-objcopy -Obinary %OUTPUT_PATH%/%OUTPUT_NAME%.axf %OUTPUT_FILE%.bin
+)
+
+IF EXIST %OUTPUT_HEX_PATH%\mbl_ns* del %OUTPUT_HEX_PATH%\mbl_ns*
+
+if "%AESK%" == "" (
+    %SREC_CAT%  %OUTPUT_FILE%.bin -Binary -offset 0x0C000000 -o %OUTPUT_FILE%.hex -Intel
+) else (
+    :: Pad mbl.bin to 32K with 0xFF
+    python %IMGTOOL% pad -s 0x8000 %OUTPUT_FILE%.bin %OUTPUT_FILE%-pad.bin
+
+    :: Encrypt MBL with AES Key
+    python %AESTOOL% --c %CONFIG_FILE%   ^
+        -t "MBL" ^
+        -i %OUTPUT_FILE%-pad.bin ^
+        -o %OUTPUT_FILE%-aes.bin ^
+        -k %AESK%
+
+    :: Convert to HEX file
+    %SREC_CAT%  %OUTPUT_FILE%-aes.bin -Binary -offset 0x0C000000 -o %OUTPUT_FILE%-aes.hex -Intel
+
+    IF EXIST %OUTPUT_FILE%-pad.bin del %OUTPUT_FILE%-pad.bin
+    echo AES encrypted!
+)
+
+:: Copy to output hex path
+copy %OUTPUT_FILE%%AES_SUFFIX%.bin %OUTPUT_HEX_PATH%
+copy %OUTPUT_FILE%%AES_SUFFIX%.hex %OUTPUT_HEX_PATH%
+
+:: Download to FLASH
+cd %ROOT%
+python %DLTOOL% -a %ALGO% -f %OUTPUT_FILE%%AES_SUFFIX%.hex --debugger %DEBUGGER%
+cd %WORK_PATH%
+
+::exit

MBL/project/mbl_afterbuild_tz.bat

@@ -0,0 +1,114 @@
+@echo off
+set SIP=%1
+set AESK=%~2
+set DEBUGGER=%3
+set OUTPUT_PATH=%4
+set OUTPUT_NAME=%5
+set TOOLKIT=%6
+set TOOLKIT_DIR=%7
+
+set "OUTPUT_PATH=%OUTPUT_PATH:/=\%"
+
+set ROOT=%OUTPUT_PATH%\..\..\..\..\..\
+set KEY_PASSPHRASE="12345678"
+set MBL_KEY=%ROOT%\scripts\certs\mbl-key.pem
+set ROTPK=%ROOT%\scripts\certs\rot-key.pem
+set MBL_CERT=%ROOT%\scripts\certs\mbl-cert.pem
+set CONFIG_FILE=%ROOT%\config\config_gdm32.h
+set SYSTOOL=%ROOT%\scripts\imgtool\sysset.py
+set IMGTOOL=%ROOT%\scripts\imgtool\imgtool.py
+set HEXTOOL=%ROOT%\scripts\imgtool\hextool.py
+set GENTOOL=%ROOT%\scripts\imgtool\gentool.py
+set AESTOOL=%ROOT%\scripts\imgtool\aestool.py
+set SREC_CAT=%ROOT%\scripts\imgtool\srec_cat.exe
+set DLTOOL=%ROOT%\scripts\imgtool\download.py
+set OUTPUT_HEX_PATH=%ROOT%\scripts\images\
+set OUTPUT_FILE=%OUTPUT_PATH%\..\%OUTPUT_NAME%
+
+:: Save Orignal Working Path
+set WORK_PATH=%CD%
+
+if "%SIP%" == "SIP" (
+    set ALGO=GD32W51x_S
+) else (
+    set ALGO=GD32W51x_Q_S
+)
+
+if "%AESK%" NEQ "" (
+    set AES_SUFFIX=-aes
+) else (
+    set AES_SUFFIX=
+)
+
+:: Generate system setting hex
+python %SYSTOOL% -t "SYS_SET" -c %CONFIG_FILE%  %OUTPUT_HEX_PATH%\sysset.bin
+
+:: Generate system status hex (padding with 0xFF)
+:: python %SYSTOOL% -t "SYS_STATUS" -c %CONFIG_FILE%  %OUTPUT_HEX_PATH%\sysstatus.bin
+
+if "%TOOLKIT%" == "KEIL" (
+    :: Generate txt for debug
+    %TOOLKIT_DIR%\ARM\ARMCC\bin\fromelf.exe --text -c -d --output=%OUTPUT_FILE%.txt %OUTPUT_PATH%\%OUTPUT_NAME%.axf
+
+    :: Generate binary image
+    %TOOLKIT_DIR%\ARM\ARMCC\bin\fromelf.exe --bin --8x1  --bincombined --output=%OUTPUT_FILE%.bin %OUTPUT_PATH%\%OUTPUT_NAME%.axf
+)
+if "%TOOLKIT%" == "IAR" (
+    :: Generate ASM file
+    %TOOLKIT_DIR%\bin\ielfdumparm.exe %OUTPUT_PATH%\%OUTPUT_NAME%.axf  --output %OUTPUT_FILE%.asm --code
+
+    :: Generate binary image
+    %TOOLKIT_DIR%\bin\ielftool.exe %OUTPUT_PATH%\%OUTPUT_NAME%.axf  --bin %OUTPUT_FILE%.bin
+)
+
+if "%TOOLKIT%" == "GCC" (
+    arm-none-eabi-objdump -xS  %OUTPUT_PATH%/%OUTPUT_NAME%.axf > %OUTPUT_FILE%.txt
+    arm-none-eabi-objcopy -Obinary %OUTPUT_PATH%/%OUTPUT_NAME%.axf %OUTPUT_FILE%.bin
+)
+
+if exist %OUTPUT_HEX_PATH%\mbl-sign.bin  del %OUTPUT_HEX_PATH%\mbl-sign.bin
+:: Add image header, ptlvs and concatenate the cert
+python %IMGTOOL% sign --config %CONFIG_FILE% ^
+                      -k %MBL_KEY% ^
+                      -P %KEY_PASSPHRASE% ^
+                      -t "MBL" ^
+                      --cert %MBL_CERT% ^
+                      %OUTPUT_FILE%.bin %OUTPUT_HEX_PATH%\mbl-sign.bin
+
+python %GENTOOL% --config %CONFIG_FILE% ^
+                 --sys_set %OUTPUT_HEX_PATH%\sysset.bin ^
+                 --mbl %OUTPUT_HEX_PATH%\mbl-sign.bin ^
+                 -o %OUTPUT_HEX_PATH%\mbl-sys.bin
+IF EXIST %OUTPUT_HEX_PATH%\sysset.bin del %OUTPUT_HEX_PATH%\sysset.bin
+IF EXIST %OUTPUT_HEX_PATH%\mbl-sign.bin del %OUTPUT_HEX_PATH%\mbl-sign.bin
+
+if "%AESK%" == ""  (
+    python %HEXTOOL% -c %CONFIG_FILE% ^
+            -t "SYS_SET" ^
+            -e %SREC_CAT% ^
+            %OUTPUT_HEX_PATH%\mbl-sys.bin ^
+            %OUTPUT_HEX_PATH%\mbl-sys.hex
+)  else (
+    python %IMGTOOL% pad -s 0x8000 ^
+                         %OUTPUT_HEX_PATH%\mbl-sys.bin %OUTPUT_HEX_PATH%\mbl-sys-pad.bin
+    python %AESTOOL% --c %CONFIG_FILE%   ^
+            -t "SYS_SET" ^
+            -i %OUTPUT_HEX_PATH%\mbl-sys-pad.bin ^
+            -o %OUTPUT_HEX_PATH%\mbl-sys%AES_SUFFIX%.bin ^
+            -k %AESK%
+    python %HEXTOOL% -c %CONFIG_FILE% ^
+            -t "SYS_SET" ^
+            -e %SREC_CAT% ^
+            %OUTPUT_HEX_PATH%\mbl-sys%AES_SUFFIX%.bin ^
+            %OUTPUT_HEX_PATH%\mbl-sys.hex
+    del %OUTPUT_HEX_PATH%\mbl-sys-pad.bin
+    echo Encrypted!
+)
+
+copy %OUTPUT_HEX_PATH%\mbl-sys.hex %OUTPUT_PATH%\mbl.hex
+copy %OUTPUT_PATH%\mbl_cmse_Lib.o %ROOT%\NSPE\WIFI_IOT\lib\%TOOLKIT%
+
+cd %ROOT%
+python %DLTOOL%  -a %ALGO% -f %OUTPUT_HEX_PATH%\mbl-sys.hex  --debugger %DEBUGGER%
+cd %WORK_PATH%
+::exit

MBL/source/mbl.c

@@ -0,0 +1,349 @@
+/*!
+    \file    mbl.c
+    \brief   Main boot loader for GD32W51x WiFi SDK
+
+    \version 2021-10-30, V1.0.0, firmware for GD32W51x
+*/
+
+/*
+    Copyright (c) 2021, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice,
+       this list of conditions and the following disclaimer in the documentation
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors
+       may be used to endorse or promote products derived from this software without
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#include "mbl_includes.h"
+#include "rom_export_mbedtls.h"
+#include "mbl_nsc_api.h"
+#include "mbl_dummy.c"
+
+#if defined (__ICCARM__)
+extern uint32_t MBL_CMSE_VENEER$$Base;
+extern uint32_t MBL_CMSE_VENEER$$Limit;
+extern uint32_t MBL_BUF$$Base;
+extern uint32_t HEAP$$Limit;
+#else
+REGION_DECLARE(Image$$, MBL_CMSE_VENEER, $$Base);
+REGION_DECLARE(Image$$, MBL_CMSE_VENEER, $$Limit);
+REGION_DECLARE(Image$$, MBL_BUF, $$ZI$$Base);
+#endif
+
+
+typedef void (*nsfptr_t) (void) __attribute__((cmse_nonsecure_call));
+struct rom_api_s_t *p_rom_api_s = (struct rom_api_s_t *)ROM_API_ARRAY_BASE;
+static uint8_t alloc_buf[MBL_BUF_SIZE];
+
+/*!
+    \brief      initialize usart
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+static void log_uart_init(void)
+{
+    rcu_periph_clock_enable(RCU_USART1);
+    rcu_periph_clock_enable(RCU_GPIOB);
+    rcu_periph_clock_enable(RCU_GPIOA);
+
+    gpio_af_set(GPIOB, GPIO_AF_7, GPIO_PIN_15);
+    gpio_af_set(GPIOA, GPIO_AF_3, GPIO_PIN_8);
+    gpio_mode_set(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_15);
+    gpio_output_options_set(GPIOB, GPIO_OTYPE_PP, GPIO_OSPEED_25MHZ, GPIO_PIN_15);
+    gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_8);
+    gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_25MHZ, GPIO_PIN_8);
+
+    usart_deinit(USART1);
+    usart_baudrate_set(USART1, 115200U);
+    usart_receive_config(USART1, USART_RECEIVE_ENABLE);
+    usart_transmit_config(USART1, USART_TRANSMIT_ENABLE);
+    usart_enable(USART1);
+
+    usart_interrupt_enable(USART1, USART_INT_RBNE);
+}
+
+/*!
+    \brief      wait usart transmit complete
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void log_uart_idle_wait(void)
+{
+    while (RESET == usart_flag_get(USART1, USART_FLAG_TC));
+}
+
+/*!
+    \brief      deinitialize mbedtls
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+static void mbedtls_deinit(void)
+{
+    mbedtls_platform_set_calloc_free(NULL, NULL);
+    mbedtls_platform_set_snprintf(NULL);
+    mbedtls_platform_set_printf(NULL);
+}
+
+#if defined (__ICCARM__)
+/*!
+    \brief      clear ram data
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+__attribute__((naked))
+void ram_data_clear(void)
+{
+    __ASM volatile(
+        "mov     r0, #0                              \n"
+        "ldr     r1, =MBL_BUF$$Base                  \n"
+        "ldr     r2, =HEAP$$Limit                    \n"
+        "subs    r2, r2, r1                          \n"
+        "Loop:                                       \n"
+        "subs    r2, #4                              \n"
+        "itt     ge                                  \n"
+        "strge   r0, [r1, r2]                        \n"
+        "bge     Loop                                \n"
+        "bx      lr                                  \n"
+         : : : "r0" , "r1" , "r2" , "memory"
+    );
+}
+#else
+/*!
+    \brief      clear ram data
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+__attribute__((naked))
+void ram_data_clear(void)
+{
+    __ASM volatile(
+        "mov     r0, #0                              \n"
+        "ldr     r1, =Image$$MBL_BUF$$ZI$$Base       \n"
+        "ldr     r2, =Image$$ARM_LIB_STACKHEAP$$ZI$$Limit \n"
+        "subs    r2, r2, r1                          \n"
+        "Loop:                                       \n"
+        "subs    r2, #4                              \n"
+        "itt     ge                                  \n"
+        "strge   r0, [r1, r2]                        \n"
+        "bge     Loop                                \n"
+        "bx      lr                                  \n"
+         : : : "r0" , "r1" , "r2" , "memory"
+    );
+}
+#endif
+//        ".syntax unified                 \n"
+/*!
+    \brief      jump to PSA root
+    \param[in]  reset_handler_addr: reset handler adress
+    \param[out] none
+    \retval     none
+*/
+__attribute__((naked))
+void jump_to_prot_asm(uint32_t reset_handler_addr)
+{
+    __ASM volatile(
+
+        "mov     r7, r0                  \n"
+        "bl      ram_data_clear          \n" /* Clear ram data before jump to Main Image including the data rom uesed */
+        "movs    r0, #0                  \n" /* Clear registers: R0-R12, */
+        "mov     r1, r0                  \n" /* except R7 */
+        "mov     r2, r0                  \n"
+        "mov     r3, r0                  \n"
+        "mov     r4, r0                  \n"
+        "mov     r5, r0                  \n"
+        "mov     r6, r0                  \n"
+        "mov     r8, r0                  \n"
+        "mov     r9, r0                  \n"
+        "mov     r10, r0                 \n"
+        "mov     r11, r0                 \n"
+        "mov     r12, r0                 \n"
+        "mov     lr,  r0                 \n"
+        "bx      r7                      \n" /* Jump to Reset_handler */
+    );
+}
+
+/*!
+    \brief      jump to main image
+    \param[in]  to_nsec: decide jujmp to non-secure or secure
+    \param[in]  msp: main stack pointer
+    \param[in]  reset: reset handler
+    \param[out] none
+    \retval     none
+*/
+static void jump_to_main_image(IN uint32_t to_nsec, IN uint32_t msp, IN uint32_t reset)
+{
+    static uint32_t prot_reset;
+    static nsfptr_t nspe_reset;
+
+    if (to_nsec) {
+        nspe_reset = (nsfptr_t)cmse_nsfptr_create(reset);
+#if defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8M_BASE__)
+        __TZ_set_MSPLIM_NS(0);
+#endif
+        __TZ_set_MSP_NS(msp);
+        __DSB();
+        __ISB();
+        nspe_reset();
+    } else {
+        prot_reset = reset;
+#if defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8M_BASE__)
+        /* Restore the Main Stack Pointer Limit register's reset value
+         * before passing execution to runtime firmware to make the
+         * bootloader transparent to it.
+         */
+        __set_MSPLIM(0);
+#endif
+        __set_MSP(msp);
+
+        __DSB();
+        __ISB();
+
+        jump_to_prot_asm(prot_reset);
+    }
+
+}
+
+/*!
+    \brief      main function
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+int main(void)
+{
+    struct ibl_state_t ibl_state;
+    uint32_t boot_idx = 0, image_addr = 0;
+    uint8_t boot_seed[BOOT_SEED_SIZE];
+    uint8_t impl_id[IMPLEMENTATION_ID_MAX_SIZE];
+    uint8_t inst_id[INSTANCE_ID_MAX_SIZE];
+    uint32_t arm_vector[2];
+    uint32_t bonly_nspe = 0;
+    uint32_t nsc_start, nsc_end;
+    int ret;
+
+#if defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8M_BASE__)
+#if defined (__ICCARM__)
+    uint32_t msp_stack_bottom = (uint32_t)&MBL_BUF$$Base + 0x1000;
+#else
+    uint32_t msp_stack_bottom = (uint32_t)&REGION_NAME(Image$$, MBL_BUF, $$ZI$$Base) + 0x1000;
+#endif
+    __set_MSPLIM(msp_stack_bottom);
+#endif
+
+    /* Set all flash pages as secure */
+    mbl_flash_wm_init();
+
+    /* Reinitialize uart since system clock source changed from IRC16M to HXTAL40M */
+    log_uart_init();
+
+    /* Read Initial boot state from shared SRAM */
+    memcpy(&ibl_state, (void *)IBL_SHARED_DATA_START, sizeof(struct ibl_state_t));
+
+    /* Re-initialize shared SRAM */
+    mbl_status_init();
+    mbl_status_sw_info_add(&ibl_state.mbl_info);
+
+    mbedtls_memory_buffer_alloc_init(alloc_buf, sizeof(alloc_buf));
+
+    /* Find the correct image to boot, Image 0 or Image 1 */
+    ret = boot_image_find(&boot_idx, &image_addr);
+    if (ret < 0) {
+        rom_trace_ex(ROM_ERR, "No image to boot (ret = %d).\r\n", ret);
+        goto BootFailed;
+    } else {
+        rom_trace_ex(ROM_ALWAYS, "MBL: Boot from Image %d.\r\n", boot_idx);
+    }
+
+    /* If boot from Image 1, config offset mapping */
+    if (boot_idx == IMAGE_1) {
+        flash_offset_mapping();
+    }
+
+    /* Verify Image */
+    ret = image_x_validate(image_addr, ibl_state.mbl_pk, ibl_state.ibl_opt, &bonly_nspe);
+    if (ret < 0) {
+        rom_trace_ex(ROM_ERR, "Validate Image %d failed (ret = %d).\r\n", boot_idx, ret);
+        rom_sys_set_img_flag(boot_idx, IMG_FLAG_VERIFY_MASK, IMG_FLAG_VERIFY_FAIL);
+        goto BootFailed;
+    } else {
+        rom_trace_ex(ROM_ALWAYS, "MBL: Validate Image %d OK.\r\n", boot_idx);
+    }
+
+    /* Update Image status and Running Image flag */
+    rom_sys_set_img_flag(boot_idx, IMG_FLAG_VERIFY_MASK, IMG_FLAG_VERIFY_OK);
+    rom_sys_set_running_img(boot_idx);
+
+    /* Generate boot seed, Instance ID, Implementation ID  */
+    boot_seed_gen(boot_seed);
+    memcpy(impl_id, ibl_state.impl_id, sizeof(impl_id));
+    instance_id_gen(inst_id);
+
+    /* Save General info to MBL status */
+    mbl_status_boot_seed_add(boot_seed);
+    mbl_status_impl_id_add(impl_id);
+    mbl_status_inst_id_add(inst_id);
+    mbl_status_running_img_add((uint8_t *)&boot_idx);
+#if defined (__ICCARM__)
+    nsc_start = (uint32_t)&MBL_CMSE_VENEER$$Base;
+    nsc_end = (uint32_t)&MBL_CMSE_VENEER$$Limit;
+#else
+    nsc_start = (uint32_t)&REGION_NAME(Image$$, MBL_CMSE_VENEER, $$Base);
+    nsc_end = (uint32_t)&REGION_NAME(Image$$, MBL_CMSE_VENEER, $$Limit);
+#endif
+    mbl_status_sau_entry_add((uint8_t *)&nsc_start, (uint8_t *)&nsc_end);
+    mbl_status_rom_version_add((uint8_t *)&ibl_state.rom_ver);
+
+    /* Clear the pointers of mbedtls platform APIs */
+    if (!bonly_nspe)
+        mbedtls_deinit();
+
+    /*####### Test #######*/
+    //mbl_status_show();
+
+    /* Jump to PROT or AROT or NSPE */
+    rom_flash_read((image_addr + sizeof(struct image_header)), arm_vector, 8);
+    if (!rom_is_valid_flash_addr(arm_vector[1])) {
+        rom_trace_ex(ROM_ERR, "Image vector reset is invalid (%08x).\r\n", arm_vector[1]);
+        goto BootFailed;
+    }
+
+    rom_trace_ex(ROM_ALWAYS, "MBL: Jump to Main Image.\r\n");
+
+    /* Setup security related settings for NSPE if no PROT or AROT */
+    if (bonly_nspe) {
+        if (mbl_sec_for_nspe_setup(boot_idx)< 0) {
+            rom_trace_ex(ROM_ERR, "Setup security settings for NSPE failed. \r\n");
+            goto BootFailed;
+        }
+        SCB_NS->VTOR = FLASH_BASE_NS + image_addr + sizeof(struct image_header);
+    }
+    log_uart_idle_wait();
+
+    jump_to_main_image(bonly_nspe, arm_vector[0], arm_vector[1]);
+
+BootFailed:
+    while(1);
+}

MBL/source/mbl_dummy.c

@@ -0,0 +1,137 @@
+/*!
+    \file    mbl_dummy.c
+    \brief   MBL dummy for GD32W51x WiFi SDK
+
+    \version 2021-10-30, V1.0.0, firmware for GD32W51x
+*/
+
+/*
+    Copyright (c) 2021, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice,
+       this list of conditions and the following disclaimer in the documentation
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors
+       may be used to endorse or promote products derived from this software without
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#include "mbl_includes.h"
+
+/* Initial attestation private key in raw format, without any encoding.
+ * It belongs to the ECDSA P-256 curve.
+ * It MUST present on the device-
+ */
+const uint8_t initial_attestation_private_key[] =
+{
+    0xA9, 0xB4, 0x54, 0xB2, 0x6D, 0x6F, 0x90, 0xA4,
+    0xEA, 0x31, 0x19, 0x35, 0x64, 0xCB, 0xA9, 0x1F,
+    0xEC, 0x6F, 0x9A, 0x00, 0x2A, 0x7D, 0xC0, 0x50,
+    0x4B, 0x92, 0xA1, 0x93, 0x71, 0x34, 0x58, 0x5F
+};
+
+/* Initial attestation x-coordinate of the public key in raw format,
+ * without any encoding.
+ * It belongs to the ECDSA P-256 curve.
+ * It MIGHT be present on the device.
+ */
+const uint8_t initial_attestation_public_x_key[] =
+{
+    0x79, 0xEB, 0xA9, 0x0E, 0x8B, 0xF4, 0x50, 0xA6,
+    0x75, 0x15, 0x76, 0xAD, 0x45, 0x99, 0xB0, 0x7A,
+    0xDF, 0x93, 0x8D, 0xA3, 0xBB, 0x0B, 0xD1, 0x7D,
+    0x00, 0x36, 0xED, 0x49, 0xA2, 0xD0, 0xFC, 0x3F
+};
+
+/* Initial attestation y-coordinate of the public key in raw format,
+ * without any encoding.
+ * It belongs to the ECDSA P-256 curve.
+ * It MIGHT be present on the device.
+ */
+const uint8_t initial_attestation_public_y_key[] =
+{
+    0xBF, 0xCD, 0xFA, 0x89, 0x56, 0xB5, 0x68, 0xBF,
+    0xDB, 0x86, 0x73, 0xE6, 0x48, 0xD8, 0xB5, 0x8D,
+    0x92, 0x99, 0x55, 0xB1, 0x4A, 0x26, 0xC3, 0x08,
+    0x0F, 0x34, 0x11, 0x7D, 0x97, 0x1D, 0x68, 0x64
+};
+
+/* Hash (SHA256) of initial attestation public key.
+ * Byte string representation of ECC public key according to
+ * psa_export_public_key() in interface/include/psa/crypto.h:
+ * 0x04 || X_coord || Y_coord
+ */
+const uint8_t initial_attestation_raw_public_key_hash[] =
+{
+    0xfa, 0x58, 0x75, 0x5f, 0x65, 0x86, 0x27, 0xce,
+    0x54, 0x60, 0xf2, 0x9b, 0x75, 0x29, 0x67, 0x13,
+    0x24, 0x8c, 0xae, 0x7a, 0xd9, 0xe2, 0x98, 0x4b,
+    0x90, 0x28, 0x0e, 0xfc, 0xbc, 0xb5, 0x02, 0x48
+};
+
+const uint8_t implementation_id[] =
+{
+    0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA,
+    0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB,
+    0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+    0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD,
+};
+
+/*!
+    \brief      generate boot seed
+    \param[in]  none
+    \param[out] boot_seed: pointer to boot seed
+    \retval     none
+*/
+void boot_seed_gen(uint8_t *boot_seed)
+{
+#if 0
+    int i;
+
+    for (i = 0; i < BOOT_SEED_SIZE; i += 4) {
+        *(uint32_t *)boot_seed = rom_rand();
+    }
+#else
+    int ret = rom_rand(boot_seed, BOOT_SEED_SIZE);
+    if (ret < 0)
+        rom_trace_ex(ROM_ERR, "Get boot seed failed.\r\n");
+#endif
+}
+
+/*!
+    \brief      generate implementation id
+    \param[in]  none
+    \param[out] impl_id: pointer to implementation id
+    \retval     none
+*/
+void implement_id_gen(uint8_t *impl_id)
+{
+    memcpy(impl_id, implementation_id, IMPLEMENTATION_ID_MAX_SIZE);
+}
+
+/*!
+    \brief      generate instance id
+    \param[in]  none
+    \param[out] inst_id: pointer to instance id
+    \retval     none
+*/
+void instance_id_gen(uint8_t *inst_id)
+{
+    memcpy(inst_id, initial_attestation_raw_public_key_hash, INSTANCE_ID_MAX_SIZE);
+}

MBL/source/mbl_image_validate.c

@@ -0,0 +1,574 @@
+/*!
+    \file    mbl_image_validate.c
+    \brief   MBL image validate file for GD32W51x WiFi SDK
+
+    \version 2021-10-30, V1.0.0, firmware for GD32W51x
+*/
+
+/*
+    Copyright (c) 2021, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice,
+       this list of conditions and the following disclaimer in the documentation
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors
+       may be used to endorse or promote products derived from this software without
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#include "mbl_includes.h"
+
+/*!
+    \brief      find boot image
+    \param[in]  none
+    \param[out] idx: pointer index of boot image
+    \param[out] image_offset: pointer to offset of boot image
+    \retval     result of find boot image
+      \arg        0: find image success
+      \arg        -1: offset of image is null
+      \arg        -2: find image0 fail
+      \arg        -3: find image1 fail
+      \arg        -4: image1 has downloaded but image0 has not downloaded
+      \arg        -5: other fail
+      \arg        -6: read image address from system setting fail
+*/
+int boot_image_find(OUT uint32_t *idx, OUT uint32_t *image_offset)
+{
+    uint8_t img0_stat = 0, img1_stat = 0;
+    struct sys_setting_t setting;
+    uint8_t img0_found = 0, img1_found = 0;
+    int boot_idx = -1;
+    int ret, result = 0;
+
+    if (NULL == image_offset) {
+        result = -1;
+        goto Failed;
+    }
+
+    ret = rom_sys_status_get(SYS_IMAGE0_STATUS, LEN_SYS_IMAGE_STATUS, &img0_stat);
+    if (ret <= SYS_STATUS_FOUND_ERR) {
+        result = -2;
+        goto Failed;
+    } else if (ret == SYS_STATUS_FOUND_OK) {
+        img0_found = 1;
+    } else {  // SYS_STATUS_NOT_FOUND
+        img0_found = 0;
+    }
+    ret = rom_sys_status_get(SYS_IMAGE1_STATUS, LEN_SYS_IMAGE_STATUS, &img1_stat);
+    if (ret <= SYS_STATUS_FOUND_ERR) {
+        result = -3;
+        goto Failed;
+    } else if (ret == SYS_STATUS_FOUND_OK) {
+        img1_found = 1;
+    } else {  // SYS_STATUS_NOT_FOUND
+        img1_found = 0;
+    }
+
+    /* Image0 never downloaded, Image1 should not be downloaded too. */
+    if (!img0_found && img1_found) {
+        result = -4;
+        goto Failed;
+    }
+
+    if (!img0_found && !img1_found) {
+        /* ISP newly downloaded */
+        rom_sys_set_img_flag(IMAGE_0, IMG_FLAG_NEWER_MASK, IMG_FLAG_NEWER);
+        boot_idx = 0;
+        goto ImgSelected;
+    }
+
+    if (img0_found && ((img0_stat & IMG_FLAG_NEWER_MASK) == IMG_FLAG_NEWER)) {
+        if (((img0_stat & IMG_FLAG_VERIFY_MASK) != IMG_FLAG_VERIFY_FAIL)
+            && ((img0_stat & IMG_FLAG_IA_MASK) != IMG_FLAG_IA_FAIL)) {
+            boot_idx = 0;
+            goto ImgSelected;
+        }
+    }
+
+    if (img1_found && ((img1_stat & IMG_FLAG_NEWER_MASK) == IMG_FLAG_NEWER)) {
+        if (((img1_stat & IMG_FLAG_VERIFY_MASK) != IMG_FLAG_VERIFY_FAIL)
+            && ((img1_stat & IMG_FLAG_IA_MASK) != IMG_FLAG_IA_FAIL)) {
+            boot_idx = 1;
+            goto ImgSelected;
+        }
+    }
+
+    if (img0_found && ((img0_stat & IMG_FLAG_VERIFY_MASK) == IMG_FLAG_VERIFY_OK)
+        && ((img0_stat & IMG_FLAG_IA_MASK) == IMG_FLAG_IA_OK)) {
+        boot_idx = 0;
+        goto ImgSelected;
+    }
+
+    if (img1_found && ((img1_stat & IMG_FLAG_VERIFY_MASK) == IMG_FLAG_VERIFY_OK)
+        && ((img1_stat & IMG_FLAG_IA_MASK) == IMG_FLAG_IA_OK)) {
+        boot_idx = 1;
+        goto ImgSelected;
+    }
+
+    if (boot_idx == -1) {
+        result = -5;
+        goto Failed;
+    }
+
+ImgSelected:
+    /* Read Image Address from system setting */
+    ret = rom_sys_setting_get(&setting);
+    if (ret != 0) {
+        result = -6;
+        goto Failed;
+    }
+    *idx = boot_idx;
+    *image_offset = setting.img0_offset;
+
+    return 0;
+
+Failed:
+    return result;
+}
+
+/*!
+    \brief      find mbl image
+    \param[in]  start_offset: flash start offset
+    \param[in]  img_type: image type
+    \param[out] img_offset: pointer to offset of image
+    \retval     result of find mbl image
+      \arg         0: find image success
+      \arg         -1: invalid flash start offset
+      \arg         -2: find image header fail
+      \arg         -3: invalid flash offset
+*/
+int mbl_img_find(IN uint32_t start_offset,
+                IN uint8_t img_type,
+                OUT uint32_t *img_offset)
+{
+    struct image_header hdr;
+    uint32_t flash_offset = start_offset;
+    uint32_t hdr_offset = 0;
+    uint32_t chksum;
+    int ret;
+    uint32_t flash_sz, erase_size;
+
+    if (!rom_is_valid_flash_offset(flash_offset)) {
+        return -3;
+    }
+
+    flash_sz = rom_flash_total_size();
+    erase_size = rom_flash_erase_size();
+    while (flash_offset < flash_sz) {
+        hdr_offset = flash_offset + RE_VTOR_ALIGNMENT - sizeof(hdr);
+        ret = rom_flash_read(hdr_offset, (void*)&hdr, sizeof(hdr));
+        if (ret != 0) {
+            return -2;
+        }
+        if ((hdr.magic_h == IMG_MAGIC_H) && (hdr.img_type == img_type)) {
+            chksum = rom_cal_checksum((uint8_t *)(&hdr), sizeof(hdr));
+            if (chksum == 0)
+                break;
+        }
+
+        flash_offset += erase_size;
+    }
+
+    if (!rom_is_valid_flash_offset(flash_offset)) {
+        return -1;
+    } else {
+        if (img_offset)
+            *img_offset = hdr_offset;
+        return 0;
+    }
+}
+
+/*!
+    \brief      find PSA root, application root and non-secure processing environment
+    \param[in]  start_offset: flash start offset
+    \param[out] prot_offset: pointer to offset of PSA root
+    \param[out] arot_offset: pointer to offset of application root
+    \param[out] nspe_offset: pointer to offfset of non-secure processing environment
+    \retval     result of find mbl image
+      \arg        1: find success
+      \arg        -1: read flash fail while get image header
+      \arg        -2: find arot fail
+      \arg        -3: read flash fail while get arot size
+      \arg        -4: find nspe fail
+*/
+static int prot_arot_nspe_find(IN uint32_t start_offset,
+                               OUT uint32_t *prot_offset,
+                               OUT uint32_t *arot_offset,
+                               OUT uint32_t *nspe_offset)
+{
+    struct image_header hdr;
+    uint32_t prot_sz, arot_sz, offset;
+    int ret;
+
+    /* Get image header */
+    ret = rom_flash_read(start_offset, (void*)&hdr, sizeof(hdr));
+    if (ret != 0) {
+        rom_trace_ex(ROM_ERR, "find_arot_nspe: read flash error (%d)\r\n", ret);
+        return -1;
+    }
+    if (hdr.img_type == IMG_TYPE_NSPE) {
+        *prot_offset = 0;
+        *arot_offset = 0;
+        *nspe_offset = start_offset;
+        return 1;
+    } else if (hdr.img_type == IMG_TYPE_AROT) {
+        *prot_offset = 0;
+        *arot_offset = start_offset;
+    } else if (hdr.img_type == IMG_TYPE_PROT) {
+        *prot_offset = start_offset;
+        prot_sz = hdr.tot_sz;
+
+        /* Get AROT address */
+        offset = *prot_offset + prot_sz;
+        offset = (((offset >> 12) + 1) << 12);
+        ret = mbl_img_find(offset, IMG_TYPE_AROT, arot_offset);
+        if (ret == -1) {
+            /* Not found, it may be happened. */
+            *arot_offset = 0;
+        } else if (ret < -1) {
+            rom_trace_ex(ROM_ERR, "find_arot_nspe: found AROT error(%d, 0x%x). \r\n", ret, arot_offset);
+            return -2;
+        }
+    }
+
+    /* Get AROT size if existed */
+    if (*arot_offset) {
+        ret = rom_flash_read(*arot_offset, (void*)&hdr, sizeof(hdr));
+        if (ret != 0) {
+            rom_trace_ex(ROM_ERR, "find_arot_nspe: read flash error (%d)\r\n", ret);
+            return -3;
+        }
+        arot_sz = hdr.tot_sz;
+        offset = *arot_offset + arot_sz;
+    } else {
+        offset = (*prot_offset + prot_sz);
+        arot_sz = 0;
+    }
+
+    /* Get NSPE address */
+    offset = (((offset >> 12) + 1) << 12);
+    ret = mbl_img_find(offset, IMG_TYPE_NSPE, nspe_offset);
+    if (ret < 0) {
+        rom_trace_ex(ROM_ERR, "find_arot_nspe: not found NSPE(%d, 0x%x). \r\n", ret, *nspe_offset);
+        *nspe_offset = 0;
+        return -4;
+    }
+
+    return 1;
+}
+
+/*!
+    \brief      check non-secure processing environment header
+    \param[in]  nspe_offset: processing environment header offset
+    \param[out] none
+    \retval     result of check nspe header
+      \arg        0: check success
+      \arg        -1: read flash fail while get image header
+      \arg        -2: nspe header check fail
+*/
+static int nspe_header_check(IN uint32_t nspe_offset)
+{
+    struct image_header hdr;
+    int ret;
+
+    ret = rom_flash_read(nspe_offset, (void*)&hdr, sizeof(hdr));
+    if (ret != 0) {
+        rom_trace_ex(ROM_ERR, "nspe_header_check: read flash error (%d)\r\n", ret);
+        return -1;
+    }
+    ret = rom_img_verify_hdr(&hdr, IMG_TYPE_IMG);
+    if (ret != 0) {
+        rom_trace_ex(ROM_ERR, "nspe_header_check: nspe header check failed (%d).\r\n", ret);
+        return -2;
+    }
+    return 0;
+}
+/*!
+    \brief      validate PSA root
+    \param[in]  prot_offset: PSA root offset
+    \param[in]  prot_pk: pointer to PSA root pass key
+    \param[out] prot_info: pointer to PSA root information
+    \retval     result of validate arot cert, Return non-zero if image could not be validated/does not validate
+*/
+static int prot_validate(IN uint32_t prot_offset,
+                    IN uint8_t *prot_pk,
+                    OUT struct sw_info_t *prot_info)
+{
+
+    return rom_img_validate(prot_offset, IMG_TYPE_PROT, prot_pk, prot_info);
+}
+
+/*!
+    \brief      validate application root certification
+    \param[in]  arot_offset: application root offset
+    \param[in]  prot_pk: pointer to PSA root pass key
+    \param[out] arot_pk: pointer to application root pass key
+    \retval     result of validate arot cert, Return non-zero if image could not be validated/does not validate
+      \arg        CERT_ERR_READ_FLASH: read flash fail while get image header
+      \arg        CERT_ERR_BAD_SZ: cert size error
+*/
+static int arot_cert_validate(IN uint32_t arot_offset,
+                    IN uint8_t *prot_pk,
+                    OUT uint8_t *arot_pk)
+{
+    struct image_header hdr;
+    uint32_t crt_offset;
+    int crt_sz, ret;
+
+    ret = rom_flash_read(arot_offset, (void*)&hdr, sizeof(hdr));
+    if (ret != 0) {
+        rom_trace_ex(ROM_ERR, "arot_cert_validate: read flash error (%d)\r\n", ret);
+        return CERT_ERR_READ_FLASH;
+    }
+
+    crt_sz = hdr.tot_sz - hdr.hdr_sz - hdr.img_sz - hdr.ptlv_sz;
+    if (crt_sz <= 0) {
+        rom_trace_ex(ROM_ERR, "arot_cert_validate: the cert size is zero.\r\n", crt_sz);
+        return CERT_ERR_BAD_SZ;
+    }
+
+    crt_offset = arot_offset + (hdr.hdr_sz + hdr.img_sz + hdr.ptlv_sz);
+
+    return rom_cert_validate(crt_offset, crt_sz, prot_pk, arot_pk);
+}
+
+/*!
+    \brief      validate application root
+    \param[in]  arot_offset: application root offset
+    \param[in]  arot_pk: pointer to application root pass key
+    \param[out] arot_info: pointer to application root information
+    \retval     result of validate arot, Return non-zero if image could not be validated/does not validate
+*/
+static int arot_validate(IN uint32_t arot_offset,
+                    IN uint8_t *arot_pk,
+                    OUT struct sw_info_t *arot_info)
+{
+    return rom_img_validate(arot_offset, IMG_TYPE_AROT, arot_pk, arot_info);
+}
+
+/*!
+    \brief      validate non-secure processing environment certification
+    \param[in]  nspe_offset: non-secure processing environment offset
+    \param[in]  prot_pk: pointer to PSA root pass key
+    \param[out] nspe_pk: pointer to nspe information
+    \retval     result of validate nspe cert
+      \arg        CERT_ERR_READ_FLASH: read flash fail while get image header
+      \arg        CERT_ERR_BAD_SZ: cert size error
+*/
+static int nspe_cert_validate(IN uint32_t nspe_offset,
+                    IN uint8_t *prot_pk,
+                    OUT uint8_t *nspe_pk)
+{
+    struct image_header hdr;
+    uint32_t crt_offset;
+    int crt_sz, ret;
+
+    ret = rom_flash_read(nspe_offset, (void*)&hdr, sizeof(hdr));
+    if (ret != 0) {
+        rom_trace_ex(ROM_ERR, "nspe_cert_validate: read flash error (%d)\r\n", ret);
+        return CERT_ERR_READ_FLASH;
+    }
+
+    crt_sz = hdr.tot_sz - hdr.hdr_sz - hdr.img_sz - hdr.ptlv_sz;
+    if (crt_sz <= 0) {
+        rom_trace_ex(ROM_ERR, "nspe_cert_validate: the cert size is zero.\r\n", crt_sz);
+        return CERT_ERR_BAD_SZ;
+    }
+
+    crt_offset = nspe_offset + (hdr.hdr_sz + hdr.img_sz + hdr.ptlv_sz);
+
+    return rom_cert_validate(crt_offset, crt_sz, prot_pk, nspe_pk);
+}
+
+/*!
+    \brief      validate non-secure processing environment
+    \param[in]  nspe_offset: non-secure processing environment offset
+    \param[in]  nspe_pk: pointer to nspe information
+    \param[out] nspe_info: pointer to nspe information
+    \retval     result of validate nspe, Return non-zero if image could not be validated/does not validate
+*/
+static int nspe_validate(IN uint32_t nspe_offset,
+                    IN uint8_t *nspe_pk,
+                    OUT struct sw_info_t *nspe_info)
+{
+    return rom_img_validate(nspe_offset, IMG_TYPE_NSPE, nspe_pk, nspe_info);
+}
+
+/*!
+    \brief      validate image x
+    \param[in]  img_offset: image offset
+    \param[in]  pk: pointer to public key
+    \param[in]  boot_opt: boot option
+    \param[out] only_nspe: pointer to only npse, there is only npse while *only_npse = 1.
+    \retval     result of validate nspe
+      \arg        0: validate image success
+      \arg        -1: find prot, arot and nspe address fail
+      \arg        -2: check nspe header fail
+      \arg        -3: verify prot fail
+      \arg        -4: save prot information into mbl status fail
+      \arg        -5: verify arot cert fail
+      \arg        -6: verify arot fail
+      \arg        -7: save arot information into mbl status fail
+      \arg        -8: verify nspe cert fail
+      \arg        -9: verify nspe fail
+      \arg        -10: save nspe into mbl status fail
+      \arg        -11: update main image version counter fail
+*/
+int image_x_validate(IN uint32_t img_offset,
+                     IN uint8_t *pk,
+                     IN uint8_t boot_opt,
+                     OUT uint32_t *only_nspe)
+{
+    struct sw_info_t sw_info;
+    uint32_t prot_offset = 0, arot_offset = 0, nspe_offset = 0;
+    uint8_t arot_pk[IMG_PK_LEN];
+    int ret, result = 0;
+
+    /* Find PROT, AROT and NSPE address */
+    ret = prot_arot_nspe_find(img_offset, &prot_offset, &arot_offset, &nspe_offset);
+    if (ret != 1) {
+        rom_trace_ex(ROM_ERR, "image_x_validate: image found error (ret = %d). \r\n", ret);
+        result = -1;
+        goto Failed;
+    }
+    if (prot_offset == 0 && arot_offset == 0 && only_nspe) {
+        *only_nspe = 1;
+    }
+    rom_trace_ex(ROM_DBG, "image_x_validate: NSPE offset is 0x%x.\r\n", nspe_offset);
+
+    if (boot_opt == IBL_VERIFY_NONE)
+        return 0;
+
+    /* Check if the Main Image Version (equal to NSPE Version) is higher than local NV counter */
+    ret = nspe_header_check(nspe_offset);
+    if (ret < 0) {
+        rom_trace_ex(ROM_ERR, "image_x_validate: the nspe header check failed (ret = %d). \r\n", ret);
+        result = -2;
+        goto Failed;
+    }
+
+    /* ============ PROT ============ */
+    if (prot_offset) {
+        /* Validate PROT */
+        memset(&sw_info, 0, sizeof(struct sw_info_t));
+        ret = prot_validate(prot_offset, pk, &sw_info);
+        if (ret != 0) {
+            rom_trace_ex(ROM_ERR, "image_x_validate: PROT verified failed. \r\n");
+            result = -3;
+            goto Failed;
+        } else {
+            rom_trace_ex(ROM_ALWAYS, "MBL: PROT image verify OK.\r\n");
+        }
+        /* Save PROT sw info to MBL status */
+        ret = mbl_status_sw_info_add(&sw_info);
+        if (ret != BOOT_STATUS_OK) {
+            rom_trace_ex(ROM_ERR, "image_x_validate: Failed to save PROT info to MBL status. \r\n");
+            result = -4;
+            goto Failed;
+        }
+    }
+    /* ============ AROT ============ */
+    if (arot_offset) {
+        /* Validate AROT cert */
+        if (boot_opt == IBL_VERIFY_CERT_IMG) {
+            ret = arot_cert_validate(arot_offset, pk, arot_pk);
+            if (ret != CERT_OK) {
+                rom_trace_ex(ROM_ERR, "image_x_validate: AROT cert verified failed. \r\n");
+                result = -5;
+                goto Failed;
+            } else {
+                rom_trace_ex(ROM_ALWAYS, "MBL: AROT cert verify OK.\r\n");
+            }
+        } else {
+            memcpy(arot_pk, pk, sizeof(arot_pk));
+        }
+        /* Validate AROT */
+        memset(&sw_info, 0, sizeof(struct sw_info_t));
+        ret = arot_validate(arot_offset, arot_pk, &sw_info);
+        if (ret != 0) {
+            rom_trace_ex(ROM_ERR, "image_x_validate: AROT verified failed. \r\n");
+            result = -6;
+            goto Failed;
+        } else {
+            rom_trace_ex(ROM_ALWAYS, "MBL: AROT image verify OK.\r\n");
+        }
+        /* Save AROT sw info to MBL status */
+        ret = mbl_status_sw_info_add(&sw_info);
+        if (ret != BOOT_STATUS_OK) {
+            rom_trace_ex(ROM_ERR, "image_x_validate: Failed to save AROT info to MBL status. \r\n");
+            result = -7;
+            goto Failed;
+        }
+    }
+
+    /* ============ NSPE ============ */
+    if (arot_offset == 0) {
+        /* Validate NSPE cert */
+        if (boot_opt == IBL_VERIFY_CERT_IMG) {
+            ret = nspe_cert_validate(nspe_offset, pk, arot_pk);
+            if (ret != CERT_OK) {
+                rom_trace_ex(ROM_ERR, "image_x_validate: NSPE cert verified failed. \r\n");
+                result = -8;
+                goto Failed;
+            } else {
+                rom_trace_ex(ROM_ALWAYS, "MBL: NSPE cert verify OK.\r\n");
+            }
+        } else {
+            memcpy(arot_pk, pk, sizeof(arot_pk));
+        }
+    }
+    /* Validate NSPE */
+    memset(&sw_info, 0, sizeof(struct sw_info_t));
+    ret = nspe_validate(nspe_offset, arot_pk, &sw_info);
+    if (ret != 0) {
+        rom_trace_ex(ROM_ERR, "image_x_validate: NSPE verified failed. \r\n");
+        result = -9;
+        goto Failed;
+    } else {
+        rom_trace_ex(ROM_ALWAYS, "MBL: NSPE image verify OK.\r\n");
+    }
+
+    /* Save NSPE sw info to MBL status */
+    ret = mbl_status_sw_info_add(&sw_info);
+    if (ret != BOOT_STATUS_OK) {
+        rom_trace_ex(ROM_ERR, "image_x_validate: Failed to save NSPE info to MBL status. \r\n");
+        result = -10;
+        goto Failed;
+    }
+
+    /* Update Main Image Version Counter */
+    ret = rom_sys_set_fw_ver(IMG_TYPE_IMG, sw_info.version);
+    if (ret < 0) {
+        rom_trace_ex(ROM_ERR, "Update Main Image version counter failed(%d).\r\n", ret);
+        result = -11;
+        goto Failed;
+    } else if (ret == 1){
+        /* The new image version is equal to the local counter. Do nothing. */
+    } else if (ret == 0){
+        rom_trace_ex(ROM_ALWAYS, "MBL: Current image version is %d.%d.%d\r\n",
+                    (sw_info.version >> 24),
+                    ((sw_info.version << 8) >> 24),
+                    (sw_info.version & 0xFFFF));
+    }
+
+    return 0;
+
+Failed:
+    return result;
+}

MBL/source/mbl_image_validate.h

@@ -0,0 +1,45 @@
+/*!
+    \file    mbl_image_validate.h
+    \brief   MBL image validate file for GD32W51x WiFi SDK
+
+    \version 2021-10-30, V1.0.0, firmware for GD32W51x
+*/
+
+/*
+    Copyright (c) 2021, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice,
+       this list of conditions and the following disclaimer in the documentation
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors
+       may be used to endorse or promote products derived from this software without
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#ifndef __MBL_H__
+#define __MBL_H__
+
+int boot_image_find(OUT uint32_t *idx,
+                        OUT uint32_t *image_offset);
+int image_x_validate(IN uint32_t img_offset,
+                        IN uint8_t *pk,
+                        IN uint8_t boot_opt,
+                        OUT uint32_t *only_nspe);
+
+#endif  // __MBL_H__

MBL/source/mbl_includes.h

@@ -0,0 +1,50 @@
+/*!
+    \file    mbl_includes.h
+    \brief   MBL inlcude file for GD32W51x WiFi SDK
+
+    \version 2021-10-30, V1.0.0, firmware for GD32W51x
+*/
+
+/*
+    Copyright (c) 2021, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice,
+       this list of conditions and the following disclaimer in the documentation
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors
+       may be used to endorse or promote products derived from this software without
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#ifndef __MBL_INCLUDES_H__
+#define __MBL_INCLUDES_H__
+
+#include <stdio.h>
+#include <string.h>
+#if defined PLATFORM_MSP_AN521
+#include "cmsis_cpu.h"
+#elif defined PLATFORM_GDM32
+#include "gd32w51x.h"
+#endif
+#include "mbl_region.h"
+#include "rom_export.h"
+#include "mbl_status.h"
+#include "mbl_image_validate.h"
+#include "mbl_target_config.h"
+#endif  // __MBL_INCLUDES_H__

MBL/source/mbl_nsc_api.c

@@ -0,0 +1,808 @@
+/*!
+    \file    mbl_nsc_api.c
+    \brief   MBL non-secure callable API for GD32W51x WiFi SDK
+
+    \version 2021-10-30, V1.0.0, firmware for GD32W51x
+*/
+
+/*
+    Copyright (c) 2021, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice,
+       this list of conditions and the following disclaimer in the documentation
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors
+       may be used to endorse or promote products derived from this software without
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#include "stdint.h"
+#include "stdio.h"
+#include "gd32w51x.h"
+#include "rom_export.h"
+#include "rom_flash.h"
+#include "config_gdm32.h"
+#include "arm_cmse.h"
+#include "mbl_nsc_api.h"
+#include "mbl_status.h"
+
+typedef void (*nsfptr_mutex_t) (int) __attribute__((cmse_nonsecure_call));
+static nsfptr_mutex_t get_mutex_nsf;
+static nsfptr_mutex_t put_mutex_nsf;
+
+/*!
+    \brief      erase flash
+    \param[in]  offset: flash erase offset
+    \param[in]  len: flash erase length
+    \param[out] none
+    \retval     result of erase flash (0: erase success, -1: invalid offset or length)
+*/
+static int flash_patch_erase(uint32_t offset, int len)
+{
+    if (OBSTAT_NQSPI() == SET) {  /* SIP Flash */
+        return rom_flash_erase(offset, len);
+
+    } else {  /* QSPI Flash */
+        uint32_t erase_sz = rom_flash_erase_size();
+        uint32_t sector_start;
+
+        if (!rom_is_valid_flash_offset(offset)
+            || len <= 0 || !rom_is_valid_flash_offset(offset + len - 1)) {
+            return -1;
+        }
+        sector_start = FLASH_START_QSPI + (offset & (~(erase_sz - 1)));
+        while (len > 0) {
+            __disable_irq();
+            rom_qspi_flash_erase_sector(sector_start);
+            __enable_irq();
+            sector_start += erase_sz;
+            len -= erase_sz;
+        }
+    }
+    return 0;
+}
+
+/*!
+    \brief      write flash
+    \param[in]  offset: flash write offset
+    \param[in]  data: pointer to buffer write to flash
+    \param[in]  len: flash write length
+    \param[out] none
+    \retval     result of write to flash (0: write success, -1: invalid offset or length)
+*/
+static int flash_patch_write(uint32_t offset, const void *data, int len)
+{
+    if (OBSTAT_NQSPI() == SET) {  /* SIP Flash */
+        return rom_flash_write_fast(offset, data, len);
+
+    } else {  /* QSPI Flash */
+        uint8_t *data_u8 = (uint8_t *)data;
+        uint32_t base_addr;
+        uint32_t page_offset;
+        uint32_t size_to_program;
+
+        if (!rom_is_valid_flash_offset(offset) || data == NULL
+            || len <= 0 || !rom_is_valid_flash_offset(offset + len - 1)) {
+            return -1;
+        }
+
+        base_addr = FLASH_START_QSPI;
+        page_offset = (offset & (FLASH_QSPI_PAGE_SIZE - 1));
+        if (page_offset != 0) {
+            size_to_program = (len > FLASH_QSPI_PAGE_SIZE - page_offset) ? (FLASH_QSPI_PAGE_SIZE - page_offset) : len;
+            __disable_irq();
+            rom_qspi_flash_program_page((base_addr + offset), data_u8, size_to_program);
+            __enable_irq();
+            offset += size_to_program;
+            data_u8 += size_to_program;
+            len -= size_to_program;
+        }
+
+        while (len > 0) {
+            size_to_program = (len > FLASH_QSPI_PAGE_SIZE) ? FLASH_QSPI_PAGE_SIZE : len;
+            __disable_irq();
+            rom_qspi_flash_program_page((base_addr + offset), data_u8, size_to_program);
+            __enable_irq();
+            offset += size_to_program;
+            data_u8 += size_to_program;
+            len -= size_to_program;
+        }
+        return 0;
+    }
+}
+
+/*!
+    \brief      read flash indirect
+    \param[in]  offset: flash read offset
+    \param[out] data: pointer to buffer store data read from flash
+    \param[in]  len: flash read length
+    \retval     result of read from flash (0 if read success, otherwise non-zero)
+*/
+static int flash_indirect_patch_read(uint32_t offset, void *data, int len)
+{
+    int cache_enabled = 0;
+    int ret;
+
+    if (ICACHE_CTL & ICACHE_CTL_EN) {
+        icache_disable();
+        cache_enabled = 1;
+    }
+
+    if (OBSTAT_NQSPI() == SET) {  /* SIP Flash */
+        /* !!!Please set this area as no decryption by calling fmc_set_nodec */
+        ret = rom_flash_read(offset, data, len);
+
+    } else {  /* QSPI Flash */
+        if (!rom_is_valid_flash_offset(offset) || data == NULL
+            || len <= 0 || !rom_is_valid_flash_offset(offset + len - 1)) {
+            ret = -1;
+            goto Exit;
+        }
+
+        ret = rom_qspi_flash_read(FLASH_START_QSPI + offset, data, len);
+    }
+Exit:
+    if (cache_enabled)
+        icache_enable();
+    return ret;
+}
+
+/*!
+    \brief      derive symmetric key
+    \param[in]  label: pinter to lable that derive key
+    \param[in]  label_sz: size of lable
+    \param[out] key: pointer to key
+    \param[in]  key_len: length of key
+    \retval     result of derive symmetric key
+*/
+static int symm_key_patch_derive(uint8_t *label, size_t label_sz,
+                        uint8_t *key, size_t key_len)
+{// TODO
+    int i;
+
+    for (i = 0; i < key_len; i++) {
+        key[i] = i + label[i % label_sz];
+    }
+    return 0;
+}
+
+/* NS callable */
+/*!
+    \brief      get mutex function
+    \param[in]  type: mutex type
+    \param[out] none
+    \retval     none
+*/
+static void sys_mutex_get_func_s(int type)
+{
+    uint32_t prim = __get_PRIMASK();
+    if (prim != 1)
+        get_mutex_nsf(type);
+}
+
+/*!
+    \brief      put mutex function
+    \param[in]  type: mutex type
+    \param[out] none
+    \retval     none
+*/
+static void sys_mutex_put_func_s(int type)
+{
+    uint32_t prim = __get_PRIMASK();
+    if (prim != 1)
+        put_mutex_nsf(type);
+}
+
+/* NS callable */
+/*!
+    \brief      set mutex function
+    \param[in]  tolock: lock or unlock flag
+    \param[in]  func: pointer to nonsecure function
+    \param[out] none
+    \retval     none
+*/
+__attribute__((cmse_nonsecure_entry))
+void mbl_mutex_set_func(int tolock, void *func)
+{
+    if (tolock) {
+        get_mutex_nsf = (nsfptr_mutex_t)cmse_nsfptr_create(func);
+        rom_set_mutex_func(1, (void *)sys_mutex_get_func_s);
+    } else {
+        put_mutex_nsf = (nsfptr_mutex_t)cmse_nsfptr_create(func);
+        rom_set_mutex_func(0, (void *)sys_mutex_put_func_s);
+    }
+}
+
+/* NS callable */
+/*!
+    \brief      mbl read flash indirect
+    \param[in]  offset: flash offset
+    \param[out] buf: pointer to buffer store data read from flash
+    \param[in]  sz: size of data read from flash
+    \retval     result of read from flash
+*/
+__attribute__((cmse_nonsecure_entry))
+int mbl_flash_indirect_read(uint32_t offset, uint8_t *buf, uint32_t sz)
+{
+    return flash_indirect_patch_read(offset, buf, sz);
+}
+
+/*!
+    \brief      mbl write flash
+    \param[in]  offset: flash offset
+    \param[in]  buf: pointer to buffer store data  write to flash
+    \param[in]  sz: size of data write flash
+    \param[out] none
+    \retval     result of write to flash
+*/
+__attribute__((cmse_nonsecure_entry))
+int mbl_flash_write(uint32_t offset, uint8_t *buf, uint32_t sz)
+{
+    return flash_patch_write(offset, buf, sz);
+}
+
+/*!
+    \brief      mbl erase flash
+    \param[in]  offset: flash offset
+    \param[in]  sz: size of erase flash
+    \param[out] none
+    \retval     result of erase flash
+*/
+__attribute__((cmse_nonsecure_entry))
+int mbl_flash_erase(uint32_t offset, uint32_t sz)
+{
+    return flash_patch_erase(offset, sz);
+}
+
+/*!
+    \brief      mbl set system status
+    \param[in]  type: type of system status to set
+    \param[in]  len: length of system status to set
+    \param[in]  pval: pointer to the value of system status to set
+    \param[out] none
+    \retval     result of set system status
+*/
+__attribute__((cmse_nonsecure_entry))
+int mbl_sys_status_set(uint8_t type, uint8_t len, uint8_t *pval)
+{
+    return rom_sys_status_set(type, len, pval);
+}
+
+/*!
+    \brief      mbl get system status
+    \param[in]  type: type of get
+    \param[in]  len: length of get
+    \param[out] pval: pointer to the value of system status to get
+    \retval     result of get system status
+*/
+__attribute__((cmse_nonsecure_entry))
+int mbl_sys_status_get(uint8_t type, uint8_t len, uint8_t* pval)
+{
+    return rom_sys_status_get(type, len, pval);
+}
+
+/*!
+    \brief      mbl set error status
+    \param[in]  method: type of method
+    \param[out] none
+    \retval     result of set error status
+*/
+__attribute__((cmse_nonsecure_entry))
+int mbl_sys_set_err_process(uint8_t method)
+{
+    return rom_sys_set_err_process(method);
+}
+
+/*!
+    \brief      mbl set system trace level
+    \param[in]  trace_level: trace level of system to set
+    \param[out] none
+    \retval     status of set system trace level
+*/
+__attribute__((cmse_nonsecure_entry))
+int mbl_sys_trace_level_set(uint8_t trace_level)
+{
+    return rom_sys_set_trace_level(trace_level);
+}
+
+/*!
+    \brief      mbl set system image flag
+    \param[in]  inx: image index
+    \param[in]  mask: image status mask value
+    \param[in]  flag: image flag
+    \param[out] none
+    \retval     status of set image flag
+*/
+__attribute__((cmse_nonsecure_entry))
+int mbl_sys_img_flag_set(uint8_t idx, uint8_t mask, uint8_t flag)
+{
+    rom_sys_set_img_flag(idx, mask, flag);
+    return 0;
+}
+
+/*!
+    \brief      mbl set system running image
+    \param[in]  idx: image index
+    \param[out] none
+    \retval     status of set running image
+*/
+__attribute__((cmse_nonsecure_entry))
+int mbl_sys_running_img_set(uint8_t idx)
+{
+    return rom_sys_set_running_img(idx);
+}
+
+/*!
+    \brief      mbl set system firmware version
+    \param[in]  type: image type
+    \param[in]  version: image version
+    \param[out] none
+    \retval     status of set firmware version
+*/
+__attribute__((cmse_nonsecure_entry))
+int mbl_sys_fw_version_set(uint32_t type, uint32_t version)
+{
+    rom_sys_set_fw_ver(type, version);
+    return 0;
+}
+
+/*!
+    \brief      mbl set system trng seed
+    \param[in]  val: trng seed value
+    \param[out] none
+    \retval     status of set system trng
+*/
+__attribute__((cmse_nonsecure_entry))
+int mbl_sys_trng_seed_set(uint8_t val)
+{
+    return rom_sys_set_trng_seed(val);
+}
+#if 0
+/*!
+    \brief      get efuse control non-secure callable function
+    \param[in]  none
+    \param[out] none
+    \retval     result of get efuse control
+*/
+__attribute__((cmse_nonsecure_entry))
+uint8_t efuse_ctl_get_nsc(void)
+{
+    return rom_efuse_get_ctl();
+}
+
+/*!
+    \brief      set efuse control non-secure callable function
+    \param[in]  ctl: control
+    \param[out] none
+    \retval     status of efuse control
+*/
+__attribute__((cmse_nonsecure_entry))
+int efuse_ctl_set_nsc(uint8_t ctl)
+{
+    return rom_efuse_set_ctl(ctl);
+}
+
+/*!
+    \brief      get efuse trust zone control non-secure callable function
+    \param[in]  none
+    \param[out] none
+    \retval     result of get efuse trust zone control
+*/
+__attribute__((cmse_nonsecure_entry))
+uint8_t efuse_tzctl_get_nsc(void)
+{
+    return rom_efuse_get_tzctl();
+}
+
+/*!
+    \brief      set efuse trust zone control non-secure callable function
+    \param[in]  tzctl: trust zone control
+    \param[out] none
+    \retval     status of set efuse trust zone control
+*/
+__attribute__((cmse_nonsecure_entry))
+int efuse_tzctl_set_nsc(uint8_t tzctl)
+{
+    return rom_efuse_set_tzctl(tzctl);
+}
+
+/*!
+    \brief      get efuse flash protection non-secure callable function
+    \param[in]  none
+    \param[out] none
+    \retval     result of get efuse flash protection non-secure callable function
+*/
+__attribute__((cmse_nonsecure_entry))
+uint8_t efuse_fp_get_nsc(void)
+{
+    return rom_efuse_get_fp();
+}
+
+/*!
+    \brief      set efuse flash protection non-secure callable function
+    \param[in]  fp: flash protection
+    \param[out] none
+    \retval     status of set efuse flash protection
+*/
+__attribute__((cmse_nonsecure_entry))
+int efuse_fp_set_nsc(uint8_t fp)
+{
+    return rom_efuse_set_fp(fp);
+}
+
+/*!
+    \brief      get efuse user control non-secure callable function
+    \param[in]  none
+    \param[out] none
+    \retval     result of get efuse user control
+*/
+__attribute__((cmse_nonsecure_entry))
+uint8_t efuse_usctl_get_nsc(void)
+{
+    return rom_efuse_get_usctl();
+}
+
+/*!
+    \brief      set efuse user control non-secure callable function
+    \param[in]  usctl: user control
+    \param[out] none
+    \retval     result of set efuse user control
+*/
+__attribute__((cmse_nonsecure_entry))
+int efuse_usctl_set_nsc(uint8_t usctl)
+{
+    return rom_efuse_set_usctl(usctl);
+}
+
+/*!
+    \brief      get efuse mcu id non-secure callable function
+    \param[in]  none
+    \param[out] mcui: pointer to mcu id
+    \retval     status of get efuse mcu id
+*/
+__attribute__((cmse_nonsecure_entry))
+int efuse_mcui_get_nsc(uint8_t *mcui)
+{
+    return rom_efuse_get_mcui(mcui);
+}
+
+/*!
+    \brief      set efuse mcu id non-secure callable function
+    \param[in]  mcui: pointer to mcu id
+    \param[out] none
+    \retval     status of set efuse mcu id
+*/
+__attribute__((cmse_nonsecure_entry))
+int efuse_mcui_set_nsc(uint8_t *mcui)
+{
+    return rom_efuse_set_mcui(mcui);
+}
+
+/*!
+    \brief      get efuse aes key non-secure callable function
+    \param[in]  none
+    \param[out] aeskey: pointer to aes key
+    \retval     status of get efuse aes key
+*/
+__attribute__((cmse_nonsecure_entry))
+int efuse_aeskey_get_nsc(uint8_t *aeskey)
+{
+    return rom_efuse_get_aeskey(aeskey);
+}
+
+/*!
+    \brief      set efuse aes key non-secure callable function
+    \param[in]  aeskey: pointer to aes key
+    \param[out] none
+    \retval     status of set efuse aes key non-secure callable function
+*/
+__attribute__((cmse_nonsecure_entry))
+int efuse_aeskey_set_nsc(uint8_t *aeskey)
+{
+    return rom_efuse_set_aeskey(aeskey);
+}
+
+/*!
+    \brief      get efuse root of trust public key non-secure callable function
+    \param[in]  none
+    \param[out] rotpk: pointer to root of trust public key
+    \retval     status of get efuse root of trust public key
+*/
+__attribute__((cmse_nonsecure_entry))
+int efuse_rotpk_get_nsc(uint8_t *rotpk)
+{
+    return rom_efuse_get_rotpk(rotpk);
+}
+
+/*!
+    \brief      set efuse root of trust public key non-secure callable function
+    \param[in]  *rotpk: pointer to root of trust public key
+    \param[out] none
+    \retval     status of set efuse root of trust public key
+*/
+__attribute__((cmse_nonsecure_entry))
+int efuse_set_rotpk_nsc(uint8_t *rotpk)
+{
+    return rom_efuse_set_rotpk(rotpk);
+}
+
+/*!
+    \brief      get efuse debug pass word non-secure callable function
+    \param[in]  none
+    \param[out] pwd: pointer to pass word
+    \retval     status of get efuse pass word
+*/
+__attribute__((cmse_nonsecure_entry))
+int efuse_dbg_pwd_get_nsc(uint8_t *pwd)
+{
+    return rom_efuse_get_dbg_pwd(pwd);
+}
+
+/*!
+    \brief      set efuse debug pass word non-secure callable function
+    \param[in]  pwd: pointer to pass word to set
+    \param[out] none
+    \retval     status of set efuse pass word
+*/
+__attribute__((cmse_nonsecure_entry))
+int efuse_dbg_pwd_set_nsc(uint8_t *pwd)
+{
+    return rom_efuse_set_dbg_pwd(pwd);
+}
+
+/*!
+    \brief      get efuse rss non-secure callable function
+    \param[in]  none
+    \param[out] rss: pointer to rss to get
+    \retval     status of get efuse rss
+*/
+__attribute__((cmse_nonsecure_entry))
+int efuse_rss_get_nsc(uint8_t *rss)
+{
+    return rom_efuse_get_rss(rss);
+}
+
+/*!
+    \brief      set efuse rss non-secure callable function
+    \param[in]  rss: pointer to rss
+    \param[out] none
+    \retval     status of set efuse rss
+*/
+__attribute__((cmse_nonsecure_entry))
+int efuse_rss_set_nsc(uint8_t *rss)
+{
+    return rom_efuse_set_rss(rss);
+}
+
+/*!
+    \brief      get efuse uid non-secure callable function
+    \param[in]  none
+    \param[out] uid: pointer to uid
+    \retval     status of get efuse uid
+*/
+__attribute__((cmse_nonsecure_entry))
+int efuse_uid_get_nsc(uint8_t *uid)
+{
+    return rom_efuse_get_uid(uid);
+}
+
+/*!
+    \brief      get efuse rf parameters non-secure callable function
+    \param[out] rf: pointer to rf
+    \param[in]  offset: offset of rf
+    \param[in]  sz: size of rf
+    \retval     status of get efuse rf
+*/
+__attribute__((cmse_nonsecure_entry))
+int efuse_rf_get_nsc(uint8_t *rf, uint32_t offset, uint32_t sz)
+{
+    return rom_efuse_get_rf(rf, offset, sz);
+}
+
+/*!
+    \brief      set efuse rf parameters non-secure callable function
+    \param[in]  rf: pointer to rf
+    \param[in]  offset: offset of rf
+    \param[in]  sz: size of rf
+    \param[out] none
+    \retval     status of set efuse rf
+*/
+__attribute__((cmse_nonsecure_entry))
+int efuse_rf_set_nsc(uint8_t *rf, uint32_t offset, uint32_t sz)
+{
+    return rom_efuse_set_rf(rf, offset, sz);
+}
+
+/*!
+    \brief      get efuse user data non-secure callable function
+    \param[out] usdata: pointer to user data
+    \param[in]  offset: offset of user data
+    \param[in]  sz: size of user data
+    \retval     status of get efuse user data
+*/
+__attribute__((cmse_nonsecure_entry))
+int efuse_usdata_get_nsc(uint8_t *usdata, uint32_t offset, uint32_t sz)
+{
+    return rom_efuse_get_usdata(usdata, offset, sz);
+}
+
+/*!
+    \brief      set efuse user data non-secure callable function
+    \param[in]  usdata: pointer to user data
+    \param[in]  offset: offset of user data
+    \param[in]  sz: size of user data
+    \param[out] none
+    \retval     status of set efuse user data
+*/
+__attribute__((cmse_nonsecure_entry))
+int efuse_usdata_get_nsc(uint8_t *usdata, uint32_t offset, uint32_t sz)
+{
+    return rom_efuse_set_usdata(usdata, offset, sz);
+}
+#endif
+/*!
+    \brief      get iak public key callable function
+    \param[in]  none
+    \param[out] output: pointer to output value
+    \param[out] len: pointer to length
+    \retval     result of get iak public key
+*/
+__attribute__((cmse_nonsecure_entry))
+int iak_pub_get_nsc(uint8_t *output, uint32_t *len)
+{
+    return rom_do_iak_getpub(2, 0, 1, 0, output, len);
+}
+
+/*!
+    \brief      sign iak callable function
+    \param[in]  hash: pointer to hash value
+    \param[in]  hash_len: hash length
+    \param[out] sig: pointer to sign
+    \param[out] sig_len: pointer to sign length
+    \retval     status of sign iak
+*/
+__attribute__((cmse_nonsecure_entry))
+int iak_sign_nsc(uint8_t *hash, uint32_t hash_len, uint8_t *sig, uint32_t *sig_len)
+{
+    return rom_do_iak_sign(2, 0, 1, hash, hash_len, sig, sig_len);
+}
+
+/*!
+    \brief      derive key non-secure callable function
+    \param[in]  label: pointer to lable
+    \param[in]  label_len: lable length
+    \param[out] key: pointer to key
+    \param[in]  key_len: key length
+    \retval     status of derive key
+*/
+__attribute__((cmse_nonsecure_entry))
+int key_derive_nsc(uint8_t *label, size_t label_len, uint8_t *key, size_t key_len)
+{
+    uint32_t rom_version;
+
+    mbl_status_rom_version_get((uint8_t *)&rom_version);
+    if (rom_version == V_1_0) {
+        rom_trace_ex(ROM_INFO, "Rom Version: 1.0\r\n");
+        return symm_key_patch_derive(label, label_len, key, key_len);
+    } else {
+        rom_trace_ex(ROM_INFO, "Rom Version: %d.%d\r\n", (rom_version >> 8), (rom_version & 0xFF));
+        return rom_do_symm_key_derive(label, label_len, key, key_len);
+    }
+}
+
+/*!
+    \brief      hmac sha1 non-secure callable function
+    \param[in]  in_vec: pointer to in vector
+    \param[in]  in_len: in length
+    \param[out] out: pointer to out
+    \retval     status of hmac sha1
+*/
+__attribute__((cmse_nonsecure_entry))
+int hmac_sha1_nsc(param_vec *in_vec, uint32_t in_len, uint8_t *out)
+{
+    int ROM_HMAC_SHA1(uint8_t *, uint32_t, uint8_t *, uint32_t, uint8_t *);
+    uint8_t *Key = in_vec[0].base;
+    uint32_t Keylen = in_vec[0].len;
+    uint8_t *Input = in_vec[1].base;
+    uint32_t Ilen = in_vec[1].len;
+    uint8_t* Output = out;
+    ROM_HMAC_SHA1(Key, Keylen, Input, Ilen, Output);
+    return 0;
+}
+
+/*!
+    \brief      cryp aes ecb non-secure callable function
+    \param[in]  in_vec: pointer to in vector
+    \param[in]  in_len: in length
+    \param[out]  out: pointer to out
+    \retval     status of cryp aes ecb
+*/
+__attribute__((cmse_nonsecure_entry))
+int cryp_aes_ecb_nsc(param_vec *in_vec, uint32_t in_len, uint8_t *out)
+{
+    int ROM_CRYP_AES_ECB(uint8_t, uint8_t *, uint16_t, uint8_t *, uint32_t, uint8_t *);
+    uint8_t Mode = *(uint8_t *)in_vec[0].base;
+    uint8_t* Key = in_vec[1].base;
+    uint16_t Keysize = in_vec[1].len;
+    uint8_t* Input = in_vec[2].base;
+    uint32_t Ilength = in_vec[2].len;
+    uint8_t* Output = out;
+    ROM_CRYP_AES_ECB(Mode, Key, Keysize, Input, Ilength, Output);
+    return 0;
+}
+
+
+#if 0
+/* NS callable */
+#define MAX_LINE_LENGTH_BYTES (64)
+#define DEFAULT_LINE_LENGTH_BYTES (16)
+/*!
+    \brief      print buffer
+    \param[in]  addr: address of buffer to print
+    \param[in]  width: print width
+    \param[in]  count: print count
+    \param[in]  linelen: print line length
+    \param[out] none
+    \retval     result of print buffer
+*/
+__attribute__((cmse_nonsecure_entry))
+int buffer_print(uint32_t addr, uint32_t width, uint32_t count, uint32_t linelen)
+{
+    uint8_t linebuf[MAX_LINE_LENGTH_BYTES];
+    uint32_t *uip = (void *)linebuf;
+    uint16_t *usp = (void *)linebuf;
+    uint8_t *ucp = (void *)linebuf;
+    uint8_t *pdata = (uint8_t *)addr;
+    int i;
+
+    if (linelen*width > MAX_LINE_LENGTH_BYTES)
+        linelen = MAX_LINE_LENGTH_BYTES / width;
+    if (linelen < 1)
+        linelen = DEFAULT_LINE_LENGTH_BYTES / width;
+
+    while (count) {
+        printf("%08x:", addr);
+
+        /* check for overflow condition */
+        if (count < linelen)
+            linelen = count;
+
+        /* Copy from memory into linebuf and print hex values */
+        for (i = 0; i < linelen; i++) {
+            if (width == 4) {
+                uip[i] = *(volatile unsigned long *)pdata;
+                printf(" %08x", uip[i]);
+            } else if (width == 2) {
+                usp[i] = *(volatile unsigned short *)pdata;
+                printf(" %04x", usp[i]);
+            } else {
+                ucp[i] = *(volatile unsigned char *)pdata;
+                printf(" %02x", ucp[i]);
+            }
+            pdata += width;
+        }
+
+        /* update references */
+        addr += linelen * width;
+        count -= linelen;
+    }
+
+    return 0;
+}
+#endif

MBL/source/mbl_nsc_api.h

@@ -0,0 +1,107 @@
+/*!
+    \file    mbl_nsc_api.h
+    \brief   MBL non-secure callable API for GD32W51x WiFi SDK
+
+    \version 2021-10-30, V1.0.0, firmware for GD32W51x
+*/
+
+/*
+    Copyright (c) 2021, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice,
+       this list of conditions and the following disclaimer in the documentation
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors
+       may be used to endorse or promote products derived from this software without
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#ifndef __MBL_NSC_API_H__
+#define __MBL_NSC_API_H__
+
+#define EFUSE_WD_CTL                    0x01
+#define EFUSE_WD_TZ_CTL                 0x01
+#define EFUSE_WD_FP                     0x01
+#define EFUSE_WD_US_CTL                 0x01
+#define EFUSE_WD_MCU_INIT               0x0c
+#define EFUSE_WD_AES_KEY                0x10
+#define EFUSE_WD_ROTPK                  0x20
+#define EFUSE_WD_DBG_PWD                0x08
+#define EFUSE_WD_RSS                    0x40
+#define EFUSE_WD_PUID                   0x10
+#define EFUSE_WD_HUK                    0x10
+#define EFUSE_WD_RF                     0x30
+#define EFUSE_WD_US_DATA                0x20
+
+#undef cmse_nsfptr_create
+#define cmse_nsfptr_create(p) ((intptr_t) (p) & ~1)
+
+typedef struct param_vec {
+    void *base;                 /*!< the start address of the memory buffer */
+    size_t len;                 /*!< the size in bytes                      */
+} param_vec;
+
+void mbl_mutex_set_func(int tolock, void *func);
+int mbl_flash_indirect_read(uint32_t offset, uint8_t *buf, uint32_t sz);
+int mbl_flash_write(uint32_t offset, uint8_t *buf, uint32_t sz);
+int mbl_flash_erase(uint32_t offset, uint32_t sz);
+int mbl_sys_status_set(uint8_t type, uint8_t len, uint8_t *pval);
+int mbl_sys_status_get(uint8_t type, uint8_t len, uint8_t* pval);
+int mbl_sys_set_err_process(uint8_t method);
+int mbl_sys_trace_level_set(uint8_t trace_level);
+int mbl_sys_img_flag_set(uint8_t idx, uint8_t mask, uint8_t flag);
+int mbl_sys_img_flag_reset(uint8_t idx);
+int mbl_sys_running_img_set(uint8_t idx);
+int mbl_sys_fw_version_set(uint32_t type, uint32_t version);
+int mbl_sys_trng_seed_set(uint8_t val);
+#if 0
+uint8_t efuse_ctl_get_nsc(void);
+int efuse_ctl_set_nsc(uint8_t ctl);
+uint8_t efuse_tzctl_get_nsc(void);
+int efuse_tzctl_set_nsc(uint8_t tzctl);
+uint8_t efuse_fp_get_nsc(void);
+int efuse_fp_set_nsc(uint8_t fp);
+uint8_t efuse_usctl_get_nsc(void);
+int efuse_usctl_set_nsc(uint8_t usctl);
+int efuse_mcui_get_nsc(uint8_t *mcui);
+int efuse_mcui_set_nsc(uint8_t *mcui);
+int efuse_aeskey_get_nsc(uint8_t *aeskey);
+int efuse_aeskey_set_nsc(uint8_t *aeskey);
+int efuse_rotpk_get_nsc(uint8_t *rotpk);
+int efuse_set_rotpk_nsc(uint8_t *rotpk);
+int efuse_dbg_pwd_get_nsc(uint8_t *pwd);
+int efuse_dbg_pwd_set_nsc(uint8_t *pwd);
+int efuse_rss_get_nsc(uint8_t *rss);
+int efuse_rss_set_nsc(uint8_t *rss);
+int efuse_uid_get_nsc(uint8_t *uid);
+int efuse_rf_get_nsc(uint8_t *rf, uint32_t offset, uint32_t sz);;
+int efuse_rf_set_nsc(uint8_t *rf, uint32_t offset, uint32_t sz);
+int efuse_usdata_get_nsc(uint8_t *usdata, uint32_t offset, uint32_t sz);
+int efuse_usdata_get_nsc(uint8_t *usdata, uint32_t offset, uint32_t sz);
+#endif
+int iak_pub_get_nsc(uint8_t *output, uint32_t *len);
+int iak_sign_nsc(uint8_t *hash, uint32_t hash_len, uint8_t *sig, uint32_t *sig_len);
+/* #if (ROM_VERSION >= V_1_1) */
+int key_derive_nsc(uint8_t *label, size_t label_len, uint8_t *key, size_t key_len);
+/* #endif (ROM_VERSION >= V_1_1) */
+
+int hmac_sha1_nsc(param_vec *in_vec, uint32_t in_len, uint8_t *out);
+int cryp_aes_ecb_nsc(param_vec *in_vec, uint32_t in_len, uint8_t *out);
+
+#endif  //__MBL_NSC_API_H__

MBL/source/mbl_status.c

@@ -0,0 +1,757 @@
+/*!
+    \file    mbl_status.c
+    \brief   MBL status operation for GD32W51x WiFi SDK
+
+    \version 2021-10-30, V1.0.0, firmware for GD32W51x
+*/
+
+/*
+    Copyright (c) 2021, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice,
+       this list of conditions and the following disclaimer in the documentation
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors
+       may be used to endorse or promote products derived from this software without
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#include "mbl_includes.h"
+
+/*!
+    \brief      print data
+    \param[in]  data: pointer to data
+    \param[in]  count: print count
+    \param[out] none
+    \retval     result of print data
+*/
+static int print_data(uint8_t *data, uint32_t count)
+{
+    uint32_t i;
+
+    for (i = 0; i < count; i++) {
+        if (i % 16 == 0)
+            rom_printf("\r\n\t");
+        rom_printf("%02x ", *(data + i));
+    }
+    rom_printf("\r\n");
+    return 0;
+}
+
+/*!
+    \brief      print sw information
+    \param[in]  sw_info: pointer to sw information
+    \param[out] none
+    \retval     result of print sw information
+*/
+static void sw_info_print(struct sw_info_t *sw_info)
+{
+    rom_printf("Add sw info:\r\n");
+    rom_printf("  Type: %d\r\n", sw_info->type);
+    rom_printf("  Version: 0x%x\r\n", sw_info->version);
+#ifdef BOOT_RECORD
+    rom_printf("  Boot Record: ");
+    print_data(sw_info->record, sw_info->record_len);
+#else
+    rom_printf("  Digest: ");
+    print_data(sw_info->digest, IMG_HASH_LEN);
+    rom_printf("  Signer ID: ");
+    print_data(sw_info->signer_id, IMG_PK_LEN);
+#endif
+}
+
+/*!
+    \brief      mbl status initialize
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void mbl_status_init(void)
+{
+    struct tfm_boot_data *boot_data;
+
+    boot_data = (struct tfm_boot_data *)MBL_SHARED_DATA_START;
+
+    memset((void *)MBL_SHARED_DATA_START, 0, MBL_SHARED_DATA_SIZE);
+    boot_data->header.tlv_magic   = SHARED_DATA_TLV_INFO_MAGIC;
+    boot_data->header.tlv_tot_len = SHARED_DATA_HEADER_SIZE;
+}
+
+/* See in boot_record.h */
+/*!
+    \brief      mbl add status type, length and value
+    \param[in]  major_type: major type, identify consumer
+    \param[in]  minor_type: minor type, identify tlv type
+    \param[in]  size: size of data
+    \param[in]  data: pointer to data
+    \param[out] none
+    \retval     result of mbl status add tlv
+      \arg        SHARED_MEMORY_OK: mbl status add tlv success
+      \arg        SHARED_MEMORY_OVERWRITE: shared memory overwrite
+      \arg        SHARED_MEMORY_OVERFLOW: shared memory overflow
+*/
+enum shared_memory_err_t
+mbl_status_tlv_add(uint8_t        major_type,
+                   uint16_t       minor_type,
+                   size_t         size,
+                   const uint8_t *data)
+{
+    struct shared_data_tlv_entry tlv_entry = {0};
+    struct tfm_boot_data *boot_data;
+    uint8_t *next_tlv;
+    uint32_t tlv_end, offset;
+
+    boot_data = (struct tfm_boot_data *)MBL_SHARED_DATA_START;
+
+    /* Check whether TLV entry is already added.
+    * Get the boundaries of TLV section
+    */
+    tlv_end = MBL_SHARED_DATA_START + boot_data->header.tlv_tot_len;
+    offset  = MBL_SHARED_DATA_START + SHARED_DATA_HEADER_SIZE;
+
+    /* Iterates over the TLV section looks for the same entry if found then
+    * returns with error: SHARED_MEMORY_OVERWRITE
+    */
+    for (; offset < tlv_end; offset += tlv_entry.tlv_len) {
+        /* Create local copy to avoid unaligned access */
+        memcpy(&tlv_entry, (const void *)offset, SHARED_DATA_ENTRY_HEADER_SIZE);
+        if (GET_MAJOR(tlv_entry.tlv_type) == major_type &&
+                GET_MINOR(tlv_entry.tlv_type) == minor_type) {
+            return SHARED_MEMORY_OVERWRITE;
+        }
+    }
+
+    /* Add TLV entry */
+    tlv_entry.tlv_type = SET_TLV_TYPE(major_type, minor_type);
+    tlv_entry.tlv_len  = SHARED_DATA_ENTRY_SIZE(size);
+
+    /* Verify overflow of shared area */
+    if ((boot_data->header.tlv_tot_len + tlv_entry.tlv_len) > IBL_SHARED_DATA_SIZE){
+        return SHARED_MEMORY_OVERFLOW;
+    }
+
+    next_tlv = (uint8_t *)boot_data + boot_data->header.tlv_tot_len;
+    memcpy(next_tlv, &tlv_entry, SHARED_DATA_ENTRY_HEADER_SIZE);
+
+    next_tlv += SHARED_DATA_ENTRY_HEADER_SIZE;
+    memcpy(next_tlv, data, size);
+
+    boot_data->header.tlv_tot_len += tlv_entry.tlv_len;
+
+    return SHARED_MEMORY_OK;
+}
+
+/*!
+    \brief      mbl get status type, length and value
+    \param[in]  major_type: major type, identify consumer
+    \param[in]  minor_type: minor type, identify tlv type
+    \param[out] tlv_len: pointer to tlv length
+    \param[out] tlv_ptr: pointer to tlv address
+    \retval     result of mbl get status tlv
+*/
+int32_t mbl_status_tlv_get(uint8_t       major_type,
+                           uint16_t      minor_type,
+                           uint16_t      *tlv_len,
+                           uint8_t       **tlv_ptr)
+{
+    struct shared_data_tlv_entry tlv_entry;
+    struct tfm_boot_data *boot_data;
+    uint8_t *tlv_end;
+    uint8_t *tlv_curr;
+
+    boot_data = (struct tfm_boot_data *)MBL_SHARED_DATA_START;
+    if (boot_data->header.tlv_magic != SHARED_DATA_TLV_INFO_MAGIC) {
+        return -1;
+    }
+
+    /* Get the boundaries of TLV section where to lookup*/
+    tlv_end = (uint8_t *)&boot_data + boot_data->header.tlv_tot_len;
+    if (*tlv_ptr == NULL) {
+        /* At first call set to the beginning of the TLV section */
+        tlv_curr = boot_data->data;
+    } else {
+        /* Any subsequent call set to the next TLV entry */
+        memcpy(&tlv_entry, *tlv_ptr, SHARED_DATA_ENTRY_HEADER_SIZE);
+        tlv_curr  = (*tlv_ptr) + tlv_entry.tlv_len;
+    }
+
+    /* Iterates over the TLV section and returns the address and size of TLVs
+    * with requested module identifier
+    */
+    for (; tlv_curr < tlv_end; tlv_curr += tlv_entry.tlv_len) {
+        /* Create local copy to avoid unaligned access */
+        memcpy(&tlv_entry, tlv_curr, SHARED_DATA_ENTRY_HEADER_SIZE);
+        if (GET_MAJOR(tlv_entry.tlv_type) == major_type &&
+                GET_MINOR(tlv_entry.tlv_type) == minor_type) {
+            *tlv_ptr = tlv_curr + SHARED_DATA_ENTRY_HEADER_SIZE;
+            if (tlv_len)
+                *tlv_len = tlv_entry.tlv_len - SHARED_DATA_ENTRY_HEADER_SIZE;
+            return 1;
+        }
+    }
+
+    return 0;
+}
+
+
+#ifndef BOOT_RECORD
+/*!
+    \brief      Add a type identifier(short test name) of SW component to the shared
+                memory area
+    \param[in]  sw_module: identifier of the SW component
+    \param[out] none
+    \retval     result of add sw type
+      \arg        BOOT_STATUS_OK: boot status ok
+      \arg        BOOT_STATUS_ERROR: boot status error
+*/
+static enum boot_status_err_t
+mbl_status_sw_type_add(uint32_t sw_module)
+{
+    /*FixMe: Use a hard coded value for now. Later on when multiple image will
+    *       be handled by MCUBoot then this must be revisited.
+    */
+    uint16_t ias_minor;
+    uint32_t cnt;
+    enum shared_memory_err_t res;
+    char *sw_type;
+
+    switch (sw_module) {
+        case SW_MBL:
+            sw_type = "MBL";
+            cnt = 3;
+            break;
+        case SW_PROT:
+            sw_type = "PROT";
+            cnt = 4;
+            break;
+        case SW_AROT:
+            sw_type = "AROT";
+            cnt = 4;
+            break;
+        case SW_NSPE:
+            sw_type = "NSPE";
+            cnt = 4;
+            break;
+        default:
+            sw_type = "UNKNOWN";
+            cnt = 7;
+    }
+
+    /* Add the type identifier of the SW component to the shared data area */
+    ias_minor = SET_IAS_MINOR(sw_module, SW_TYPE);
+    res = mbl_status_tlv_add(TLV_MAJOR_IAS,
+                                ias_minor,
+                                cnt,
+                                (const uint8_t *)sw_type);
+    if (res) {
+        return BOOT_STATUS_ERROR;
+    }
+
+    return BOOT_STATUS_OK;
+}
+
+
+/*!
+    \brief      add status sw version
+    \param[in]  sw_module: identifier of the sw component
+    \param[in]  version: sw version
+    \param[out] none
+    \retval     result of add sw version
+      \arg        BOOT_STATUS_OK: boot status ok
+      \arg        BOOT_STATUS_ERROR: boot status error
+ */
+static enum boot_status_err_t
+mbl_status_sw_version_add(uint32_t sw_module, uint32_t version)
+{
+    int32_t cnt;
+    enum shared_memory_err_t res;
+    char sw_version[14]; /* 8bit.8bit.16bit: 3 + 1 + 3 + 1 + 5 + 1 */
+    uint16_t ias_minor;
+
+    /* FixMe: snprintf can be replaced with a custom implementation */
+    cnt = snprintf(sw_version, sizeof(sw_version), "%u.%u.%u",
+                    (version >> 24),
+                    ((version & 0xFF0000) >> 16),
+                    (version & 0xFFFF));
+    if (cnt < 0 || cnt >= sizeof(sw_version)) {
+        return BOOT_STATUS_ERROR;
+    }
+
+    /* Add the version of the SW component to the shared data area */
+    ias_minor = SET_IAS_MINOR(sw_module, SW_VERSION);
+    res = mbl_status_tlv_add(TLV_MAJOR_IAS,
+                                ias_minor,
+                                cnt,
+                                (const uint8_t *)sw_version);
+    if (res) {
+        return BOOT_STATUS_ERROR;
+    }
+
+    return BOOT_STATUS_OK;
+}
+
+/*!
+    \brief      add status sw digest
+    \param[in]  sw_module: identifier of the sw component
+    \param[in]  digest: pointer to diget add to tlv
+    \param[out] none
+    \retval     result of add sw digest
+      \arg        BOOT_STATUS_OK: boot status ok
+      \arg        BOOT_STATUS_ERROR: boot status error
+*/
+static enum boot_status_err_t
+mbl_status_sw_digest_add(uint32_t sw_module, uint8_t *digest)
+{
+    uint16_t ias_minor;
+    enum shared_memory_err_t res;
+    char measure_type[] = "SHA256";
+
+    /* Add the image's hash value to the shared data area */
+    ias_minor = SET_IAS_MINOR(sw_module, SW_MEASURE_VALUE);
+    res = mbl_status_tlv_add(TLV_MAJOR_IAS,
+                                ias_minor,
+                                IMG_HASH_LEN,
+                                digest);
+    if (res) {
+        return BOOT_STATUS_ERROR;
+    }
+
+    /* Add the measurement type to the shared data area */
+    ias_minor = SET_IAS_MINOR(sw_module, SW_MEASURE_TYPE);
+                                res = mbl_status_tlv_add(TLV_MAJOR_IAS,
+                                ias_minor,
+                                sizeof(measure_type) - 1,
+                                (const uint8_t *)measure_type);
+    if (res) {
+        return BOOT_STATUS_ERROR;
+    }
+    return BOOT_STATUS_OK;
+}
+
+/*!
+    \brief      add status sw signer
+    \param[in]  sw_module: identifier of the sw component
+    \param[in]  signer_id: pointer to signer id
+    \param[out] none
+    \retval     result of add sw signer
+      \arg        BOOT_STATUS_OK: boot status ok
+      \arg        BOOT_STATUS_ERROR: boot status error
+*/
+static enum boot_status_err_t
+mbl_status_sw_signer_add(uint32_t sw_module, uint8_t *signer_id)
+{
+    uint16_t ias_minor;
+    enum shared_memory_err_t res;
+
+    /* Add the hash of the public key to the shared data area */
+    ias_minor = SET_IAS_MINOR(sw_module, SW_SIGNER_ID);
+    res = mbl_status_tlv_add(TLV_MAJOR_IAS,
+                                ias_minor,
+                                IMG_PKHASH_LEN,
+                                signer_id);
+    if (res) {
+        return BOOT_STATUS_ERROR;
+    }
+
+    return BOOT_STATUS_OK;
+}
+#endif
+
+/*!
+    \brief      add status sw information
+    \param[in]  sw_info: pointer to sw information
+    \param[out] none
+    \retval     result of add sw information
+      \arg        BOOT_STATUS_OK: boot status ok
+      \arg        BOOT_STATUS_ERROR: boot status error
+*/
+enum boot_status_err_t
+mbl_status_sw_info_add(struct sw_info_t *sw_info)
+{
+    uint32_t sw_module;
+#ifdef BOOT_RECORD
+    uint16_t ias_minor;
+    enum shared_memory_err_t res;
+#else
+    enum boot_status_err_t res;
+#endif
+
+    switch(sw_info->type) {
+        case IMG_TYPE_MBL:
+            sw_module = SW_MBL;
+            break;
+        case IMG_TYPE_PROT:
+            sw_module = SW_PROT;
+            break;
+        case IMG_TYPE_AROT:
+            sw_module = SW_AROT;
+            break;
+        case IMG_TYPE_NSPE:
+            sw_module = SW_NSPE;
+            break;
+        default:
+            sw_module = SW_MAX;
+            break;
+    }
+#ifdef BOOT_RECORD
+    /* Add the CBOR encoded boot record to the shared data area. */
+    ias_minor = SET_IAS_MINOR(sw_module, SW_BOOT_RECORD);
+    res = mbl_status_tlv_add(TLV_MAJOR_IAS,
+                                ias_minor,
+                                sw_info->record_len,
+                                sw_info->record);
+    if (res) {
+        return BOOT_STATUS_ERROR;
+    }
+#else
+    res = mbl_status_sw_type_add(sw_module);
+    if (res) {
+        return res;
+    }
+
+    res = mbl_status_sw_version_add(sw_module, sw_info->version);
+    if (res) {
+        return res;
+    }
+
+    res = mbl_status_sw_digest_add(sw_module, sw_info->digest);
+    if (res) {
+        return res;
+    }
+
+    res = mbl_status_sw_signer_add(sw_module, sw_info->signer_id);
+    if (res) {
+        return res;
+    }
+#endif /* BOOT RECORD */
+
+    // print_sw_info(sw_info);
+    return BOOT_STATUS_OK;
+}
+
+/*!
+    \brief      add status boot seed
+    \param[in]  boot_seed: pointer to boot seed
+    \param[out] none
+    \retval     result of add boot seed
+      \arg        BOOT_STATUS_OK: boot status ok
+      \arg        BOOT_STATUS_ERROR: boot status error
+*/
+enum boot_status_err_t
+mbl_status_boot_seed_add(uint8_t *boot_seed)
+{
+    uint16_t ias_minor;
+    enum shared_memory_err_t res;
+
+    ias_minor = SET_IAS_MINOR(SW_GENERAL, BOOT_SEED);
+    res = mbl_status_tlv_add(TLV_MAJOR_IAS,
+                                ias_minor,
+                                BOOT_SEED_SIZE,
+                                boot_seed);
+    if (res) {
+        return BOOT_STATUS_ERROR;
+    }
+
+    return BOOT_STATUS_OK;
+}
+
+/*!
+    \brief      add status hardware version
+    \param[in]  hw_version: pointer to boot hardware version
+    \param[out] none
+    \retval     result of add hardware version
+      \arg        BOOT_STATUS_OK: boot status ok
+      \arg        BOOT_STATUS_ERROR: boot status error
+*/
+enum boot_status_err_t
+mbl_status_hw_ver_add(uint8_t *hw_version)
+{
+    uint16_t ias_minor;
+    enum shared_memory_err_t res;
+
+    ias_minor = SET_IAS_MINOR(SW_GENERAL, HW_VERSION);
+    res = mbl_status_tlv_add(TLV_MAJOR_IAS,
+                                ias_minor,
+                                HW_VERSION_MAX_SIZE,
+                                hw_version);
+    if (res) {
+        return BOOT_STATUS_ERROR;
+    }
+
+    return BOOT_STATUS_OK;
+}
+
+/*!
+    \brief      add status life cycle
+    \param[in]  life_cycle: life cycle
+    \param[out] none
+    \retval     result of add life cycle
+      \arg        BOOT_STATUS_OK: boot status ok
+      \arg        BOOT_STATUS_ERROR: boot status error
+*/
+enum boot_status_err_t
+mbl_status_life_cycle_add(uint32_t life_cycle)
+{
+    uint16_t ias_minor;
+    enum shared_memory_err_t res;
+
+    ias_minor = SET_IAS_MINOR(SW_GENERAL, SECURITY_LIFECYCLE);
+    res = mbl_status_tlv_add(TLV_MAJOR_IAS,
+                                ias_minor,
+                                sizeof(uint32_t),
+                                (uint8_t *)&life_cycle);
+    if (res) {
+        return BOOT_STATUS_ERROR;
+    }
+
+    return BOOT_STATUS_OK;
+}
+
+/*!
+    \brief      add status implement id
+    \param[in]  impl_id: pointer to implement id
+    \param[out] none
+    \retval     result of add implement id
+      \arg        BOOT_STATUS_OK: boot status ok
+      \arg        BOOT_STATUS_ERROR: boot status error
+*/
+enum boot_status_err_t
+mbl_status_impl_id_add(uint8_t *impl_id)
+{
+    uint16_t ias_minor;
+    enum shared_memory_err_t res;
+
+    ias_minor = SET_IAS_MINOR(SW_GENERAL, IMPLEMENTATION_ID);
+    res = mbl_status_tlv_add(TLV_MAJOR_IAS,
+                                ias_minor,
+                                IMPLEMENTATION_ID_MAX_SIZE,
+                                impl_id);
+    if (res) {
+        return BOOT_STATUS_ERROR;
+    }
+
+    return BOOT_STATUS_OK;
+}
+
+/*!
+    \brief      add status instance id
+    \param[in]  instance_id: pointer to instance id
+    \param[out] none
+    \retval     result of add instance id
+      \arg        BOOT_STATUS_OK: boot status ok
+      \arg        BOOT_STATUS_ERROR: boot status error
+*/
+enum boot_status_err_t
+mbl_status_inst_id_add(uint8_t *instance_id)
+{
+    uint16_t ias_minor;
+    enum shared_memory_err_t res;
+
+    ias_minor = SET_IAS_MINOR(SW_GENERAL, INSTANCE_ID);
+    res = mbl_status_tlv_add(TLV_MAJOR_IAS,
+                                ias_minor,
+                                INSTANCE_ID_MAX_SIZE,
+                                instance_id);
+    if (res) {
+        return BOOT_STATUS_ERROR;
+    }
+
+    return BOOT_STATUS_OK;
+}
+
+/*!
+    \brief      add status running image
+    \param[in]  img_idx: pointer to image index
+    \param[out] none
+    \retval     result of add image index
+      \arg        BOOT_STATUS_OK: boot status ok
+      \arg        BOOT_STATUS_ERROR: boot status error
+*/
+enum boot_status_err_t
+mbl_status_running_img_add(uint8_t *img_idx)
+{
+    uint16_t core_minor;
+    enum shared_memory_err_t res;
+
+    core_minor = SET_CORE_MINOR(SYS_STATUS, STATUS_RUNNING_IMG);
+    res = mbl_status_tlv_add(TLV_MAJOR_CORE,
+                                core_minor,
+                                4,
+                                img_idx);
+    if (res) {
+        return BOOT_STATUS_ERROR;
+    }
+
+    return BOOT_STATUS_OK;
+}
+
+/*!
+    \brief      add status sau entry
+    \param[in]  start: pointer to start entry
+    \param[in]  end: pointer to end entry
+    \param[out] none
+    \retval     result of add sau entry
+      \arg        BOOT_STATUS_OK: boot status ok
+      \arg        BOOT_STATUS_ERROR: boot status error
+*/
+enum boot_status_err_t
+mbl_status_sau_entry_add(uint8_t *start, uint8_t *end)
+{
+    uint16_t core_minor;
+    enum shared_memory_err_t res;
+
+    core_minor = SET_CORE_MINOR(SYS_SAU, SAU_ENTRY_START);
+    res = mbl_status_tlv_add(TLV_MAJOR_CORE,
+                                core_minor,
+                                4,
+                                start);
+    if (res) {
+        return BOOT_STATUS_ERROR;
+    }
+
+    core_minor = SET_CORE_MINOR(SYS_SAU, SAU_ENTRY_END);
+    res = mbl_status_tlv_add(TLV_MAJOR_CORE,
+                                core_minor,
+                                4,
+                                end);
+    if (res) {
+        return BOOT_STATUS_ERROR;
+    }
+
+    return BOOT_STATUS_OK;
+}
+
+/*!
+    \brief      add status rom version
+    \param[in]  rom_ver: pointer to rom version
+    \param[out] none
+    \retval     result of add rom version
+      \arg        BOOT_STATUS_OK: boot status ok
+      \arg        BOOT_STATUS_ERROR: boot status error
+*/
+enum boot_status_err_t
+mbl_status_rom_version_add(uint8_t *rom_ver)
+{
+    uint16_t core_minor;
+    enum shared_memory_err_t res;
+
+    core_minor = SET_CORE_MINOR(SYS_STATUS, STATUS_ROM_VERSION);
+    res = mbl_status_tlv_add(TLV_MAJOR_CORE,
+                                core_minor,
+                                4,
+                                rom_ver);
+    if (res) {
+        return BOOT_STATUS_ERROR;
+    }
+
+    return BOOT_STATUS_OK;
+}
+
+/*!
+    \brief      get status rom version
+    \param[in]  none
+    \param[out] rom_ver: pointer to rom version
+    \retval     result of add rom version
+      \arg        BOOT_STATUS_OK: boot status ok
+      \arg        BOOT_STATUS_ERROR: boot status error
+*/
+enum boot_status_err_t
+mbl_status_rom_version_get(uint8_t *rom_ver)
+{
+    uint16_t core_minor;
+    enum shared_memory_err_t res;
+    uint8_t *tlv_val = NULL;
+
+    core_minor = SET_CORE_MINOR(SYS_STATUS, STATUS_ROM_VERSION);
+    res = (enum shared_memory_err_t) mbl_status_tlv_get(TLV_MAJOR_CORE,
+                                core_minor,
+                                NULL,
+                                &tlv_val);
+    if (res == 1) {
+        memcpy(rom_ver, tlv_val, 4);
+        return BOOT_STATUS_OK;
+    } else {
+        memset(rom_ver, 0, 4);
+        return BOOT_STATUS_ERROR;
+    }
+}
+
+/*!
+    \brief      show status
+    \param[in]  none
+    \param[out] none
+    \retval     result of show status
+*/
+int32_t mbl_status_show(void)
+{
+    struct shared_data_tlv_entry tlv_entry;
+    struct tfm_boot_data *boot_data;
+    uint8_t *tlv_end;
+    uint8_t *tlv_curr;
+    uint16_t i;
+
+    boot_data = (struct tfm_boot_data *)MBL_SHARED_DATA_START;
+    if (boot_data->header.tlv_magic != SHARED_DATA_TLV_INFO_MAGIC) {
+        return -1;
+    }
+
+    /* Get the boundaries of TLV section where to lookup*/
+    tlv_end = (uint8_t *)boot_data + boot_data->header.tlv_tot_len;
+
+    /* Iterates over the TLV section */
+    rom_printf("MBL Status Show:\r\n================================\r\n");
+    rom_printf("Magic: %04x\r\n", boot_data->header.tlv_magic);
+    rom_printf("Total length: 0x%04x\r\n", boot_data->header.tlv_tot_len);
+
+    tlv_curr = boot_data->data;
+    rom_printf("T\tL\tV\r\n");
+    for (; tlv_curr < tlv_end; tlv_curr += tlv_entry.tlv_len) {
+        /* Create local copy to avoid unaligned access */
+        memcpy(&tlv_entry, tlv_curr, SHARED_DATA_ENTRY_HEADER_SIZE);
+        rom_printf("%04x\t%04x\t", tlv_entry.tlv_type, tlv_entry.tlv_len);
+        i = SHARED_DATA_ENTRY_HEADER_SIZE;
+        for (; i < tlv_entry.tlv_len; i++) {
+            if (i == tlv_entry.tlv_len -1)
+                rom_printf("%02x", tlv_curr[i]);
+            else
+                rom_printf("%02x-", tlv_curr[i]);
+        }
+        rom_printf("\r\n");
+    }
+    return 0;
+}
+
+/*!
+    \brief      dump status
+    \param[in]  none
+    \param[out] none
+    \retval     result of dump status
+*/
+int32_t mbl_status_dump(void)
+{
+    struct tfm_boot_data *boot_data;
+    uint8_t *p;
+
+    boot_data = (struct tfm_boot_data *)MBL_SHARED_DATA_START;
+    p = (uint8_t *)boot_data;
+    rom_printf("MBL Status Dump:\r\n================================\r\n");
+    print_data(p, boot_data->header.tlv_tot_len);
+
+    return 0;
+}

MBL/source/mbl_status.h

@@ -0,0 +1,327 @@
+/*!
+    \file    mbl_status.h
+    \brief   MBL status operation for GD32W51x WiFi SDK
+
+    \version 2021-10-30, V1.0.0, firmware for GD32W51x
+*/
+
+/*
+    Copyright (c) 2021, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice,
+       this list of conditions and the following disclaimer in the documentation
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors
+       may be used to endorse or promote products derived from this software without
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#ifndef __MBL_STATUS_H__
+#define __MBL_STATUS_H__
+
+#include <stdint.h>
+#include <stddef.h>
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Major numbers (4 bit) to identify
+ * the consumer of shared data in runtime SW
+ */
+#define TLV_MAJOR_CORE     0x0
+#define TLV_MAJOR_IAS      0x1
+
+/**
+ * The shared data between boot loader and runtime SW is TLV encoded. The
+ * shared data is stored in a well known location in secure memory and this is
+ * a contract between boot loader and runtime SW.
+ *
+ * The structure of shared data must be the following:
+ *  - At the beginning there must be a header: struct shared_data_tlv_header
+ *    This contains a magic number and a size field which covers the entire
+ *    size of the shared data area including this header.
+ *  - After the header there come the entries which are composed from an entry
+ *    header structure: struct shared_data_tlv_entry and the data. In the entry
+ *    header is a type field (tly_type) which identify the consumer of the
+ *    entry in the runtime SW and specify the subtype of that data item. There
+ *    is a size field (tlv_len) which covers the size of the entry header and
+ *    the data. After this structure comes the actual data.
+ *  - Arbitrary number and size of data entry can be in the shared memory area.
+ *
+ * This table gives of overview about the tlv_type field in the entry header.
+ * The tlv_type always composed from a major and minor number. Major number
+ * identifies the addressee in runtime SW, who should process the data entry.
+ * Minor number used to encode more info about the data entry. The actual
+ * definition of minor number could change per major number. In case of boot
+ * status data, which is going to be processed by initial attestation service
+ * the minor number is split further to two part: sw_module and claim. The
+ * sw_module identifies the SW component in the system which the data item
+ * belongs to and the claim part identifies the exact type of the data.
+ *
+ * |---------------------------------------|
+ * |            tlv_type (16)              |
+ * |---------------------------------------|
+ * | tlv_major(4)|      tlv_minor(12)      |
+ * |---------------------------------------|
+ * | MAJOR_IAS   | sw_module(6) | claim(6) |
+ * |---------------------------------------|
+ * | MAJOR_CORE  |          TBD            |
+ * |---------------------------------------|
+ */
+
+/*====================================================*/
+/* TLV_MAJOR_CORE */
+/*====================================================*/
+/*
+ * Type
+ */
+#define SYS_STATUS                    0x00
+#define SYS_SAU                       0x01
+
+/*
+ * Subtype
+ */
+#define STATUS_RUNNING_IMG            0x00
+#define STATUS_ROM_VERSION            0x01
+
+#define SAU_ENTRY_START               0x00
+#define SAU_ENTRY_END                 0x01
+
+#define GET_CORE_TYPE(tlv_type)       (GET_MINOR(tlv_type) >> 8)
+#define GET_CORE_SUBTYPE(tlv_type)    (GET_MINOR(tlv_type) & 0xFF)
+#define SET_CORE_MINOR(type, subtype) (((type) << 8) | (subtype))
+
+/*====================================================*/
+/* TLV_MAJOR_IAS */
+/*====================================================*/
+/* Initial attestation: SW components / SW modules
+ * This list is intended to be adjusted per device. It contains more SW
+ * components than currently available in TF-M project. It serves as an example,
+ * what kind of SW components might be available.
+ */
+#define SW_GENERAL     0x00
+#define SW_MBL         0x01
+#define SW_PROT        0x02
+#define SW_AROT        0x03
+#define SW_SPE         0x04
+#define SW_NSPE        0x05
+#define SW_S_NS        0x06
+#define SW_MAX         0x07
+#define SW_BOOT_RECORD    0x3F
+
+/* Initial attestation: Claim per SW components / SW modules */
+/* Bits: 0-2 */
+#define SW_VERSION       0x00
+#define SW_SIGNER_ID     0x01
+/* Reserved              0x02 */
+#define SW_TYPE          0x03
+/* Bits: 3-5 */
+#define SW_MEASURE_VALUE 0x08
+#define SW_MEASURE_TYPE  0x09
+
+/* Initial attestation: General claim does not belong any particular SW
+ * component. But they might be part of the boot status.
+ */
+#define BOOT_SEED          0x00
+#define HW_VERSION         0x01
+#define SECURITY_LIFECYCLE 0x02
+/*Added by GD*/
+#define IMPLEMENTATION_ID  0x03
+#define INSTANCE_ID        0x04
+/*Added by GD end*/
+
+/* General macros to handle TLV type */
+#define MAJOR_MASK 0xF     /* 4  bit */
+#define MAJOR_POS  12      /* 12 bit */
+#define MINOR_MASK 0xFFF   /* 12 bit */
+
+#define SET_TLV_TYPE(major, minor) \
+        ((((major) & MAJOR_MASK) << MAJOR_POS) | ((minor) & MINOR_MASK))
+#define GET_MAJOR(tlv_type) ((tlv_type) >> MAJOR_POS)
+#define GET_MINOR(tlv_type) ((tlv_type) &  MINOR_MASK)
+
+/* Initial attestation specific macros */
+#define MODULE_POS 6               /* 6 bit */
+#define CLAIM_MASK 0x3F            /* 6 bit */
+#define MEASUREMENT_CLAIM_POS 3    /* 3 bit */
+
+#define GET_IAS_MODULE(tlv_type) (GET_MINOR(tlv_type) >> MODULE_POS)
+#define GET_IAS_CLAIM(tlv_type)  (GET_MINOR(tlv_type)  & CLAIM_MASK)
+#define SET_IAS_MINOR(sw_module, claim) (((sw_module) << 6) | (claim))
+
+#define GET_IAS_MEASUREMENT_CLAIM(ias_claim) ((ias_claim) >> \
+                                              MEASUREMENT_CLAIM_POS)
+#define BOOT_SEED_SIZE (32u)
+#define HW_VERSION_MAX_SIZE (18u)
+#define IMPLEMENTATION_ID_MAX_SIZE (32u)
+#define INSTANCE_ID_MAX_SIZE (33u)
+
+/*====================================================*/
+/* TLV structures */
+/*====================================================*/
+
+/* Magic value which marks the beginning of shared data area in memory */
+#define SHARED_DATA_TLV_INFO_MAGIC    0x2019
+
+/**
+ * Shared data TLV header.  All fields in little endian.
+ *
+ *    -----------------------------------
+ *    | tlv_magic(16) | tlv_tot_len(16) |
+ *    -----------------------------------
+ */
+struct shared_data_tlv_header {
+    uint16_t tlv_magic;
+    uint16_t tlv_tot_len; /* size of whole TLV area (including this header) */
+};
+
+#define SHARED_DATA_HEADER_SIZE sizeof(struct shared_data_tlv_header)
+
+/**
+ * Shared data TLV entry header format. All fields in little endian.
+ *
+ *    -------------------------------
+ *    | tlv_type(16) |  tlv_len(16) |
+ *    -------------------------------
+ *    |         Raw data            |
+ *    -------------------------------
+ */
+struct shared_data_tlv_entry {
+    uint16_t tlv_type;
+    uint16_t tlv_len; /* size of single TLV entry (including this header). */
+};
+
+/**
+ * \struct tfm_boot_data
+ *
+ * \brief Store the data for the runtime SW
+ */
+struct tfm_boot_data {
+    struct shared_data_tlv_header header;
+    uint8_t data[];
+};
+
+#define SHARED_DATA_ENTRY_HEADER_SIZE sizeof(struct shared_data_tlv_entry)
+#define SHARED_DATA_ENTRY_SIZE(size) (size + SHARED_DATA_ENTRY_HEADER_SIZE)
+
+
+/*!
+ * \enum shared_data_err_t
+ *
+ * \brief Return values for adding data entry to shared memory area
+ */
+enum shared_memory_err_t {
+    SHARED_MEMORY_OK = 0,
+    SHARED_MEMORY_OVERFLOW = 1,
+    SHARED_MEMORY_OVERWRITE = 2,
+    SHARED_MEMORY_GEN_ERROR = 3,
+
+    /* This is used to force the maximum size */
+    TLV_TYPE_MAX = 0xFFFFFFFF,
+};
+
+/*!
+ * \enum boot_status_err_t
+ *
+ * \brief Return values for saving boot status information to shared memory are
+ */
+enum boot_status_err_t {
+    BOOT_STATUS_OK,
+    BOOT_STATUS_ERROR,
+};
+
+void
+mbl_status_init(void);
+
+/*!
+ * \brief Add a data item to the shared data area between bootloader and
+ *        runtime SW
+ *
+ * \param[in] major_type  TLV major type, identify consumer
+ * \param[in] minor_type  TLV minor type, identify TLV type
+ * \param[in] size        length of added data
+ * \param[in] data        pointer to data
+ *
+ * \return Returns error code as specified in \ref shared_memory_err_t
+ */
+enum shared_memory_err_t
+mbl_status_tlv_add(uint8_t        major_type,
+                             uint16_t       minor_type,
+                             size_t         size,
+                             const uint8_t *data);
+
+int32_t
+mbl_status_tlv_get(uint8_t        major_type,
+                             uint16_t       minor_type,
+                                        uint16_t  *tlv_len,
+                                        uint8_t  **tlv_ptr);
+/*!
+ * \brief Add an image's all boot status information to the shared data area
+ *        between bootloader and runtime SW
+ *
+ * \param[in]  sw_module  Identifier of the SW component
+ * \param[in]  hdr        Pointer to the image header stored in RAM
+ * \param[in]  fap        Pointer to the flash area where image is stored
+ *
+ * \return Returns error code as specified in \ref boot_status_err_t
+ */
+enum boot_status_err_t
+mbl_status_sw_info_add(struct sw_info_t *sw_info);
+
+
+enum boot_status_err_t
+mbl_status_boot_seed_add(uint8_t *boot_seed);
+
+enum boot_status_err_t
+mbl_status_hw_ver_add(uint8_t *hw_version);
+
+enum boot_status_err_t
+mbl_status_life_cycle_add(uint32_t life_cycle);
+
+enum boot_status_err_t
+mbl_status_impl_id_add(uint8_t *impl_id);
+
+enum boot_status_err_t
+mbl_status_inst_id_add(uint8_t *instance_id);
+
+enum boot_status_err_t
+mbl_status_running_img_add(uint8_t *img_idx);
+
+enum boot_status_err_t
+mbl_status_sau_entry_add(uint8_t *start, uint8_t * end);
+
+enum boot_status_err_t
+mbl_status_rom_version_add(uint8_t *rom_ver);
+
+enum boot_status_err_t
+mbl_status_rom_version_get(uint8_t *rom_ver);
+
+int32_t
+mbl_status_show(void);
+
+int32_t
+mbl_status_dump(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MBL_STATUS_H__ */

MBL/source/mbl_target_config.c

@@ -0,0 +1,400 @@
+/*!
+    \file    mbl_target_config.c
+    \brief   MBL target configuration for GD32W51x WiFi SDK
+
+    \version 2021-10-30, V1.0.0, firmware for GD32W51x
+*/
+
+/*
+    Copyright (c) 2021, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice,
+       this list of conditions and the following disclaimer in the documentation
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors
+       may be used to endorse or promote products derived from this software without
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#include "mbl_includes.h"
+#include "rom_flash.h"
+
+#if defined PLATFORM_GDM32
+#if 0
+enum {
+    NS_REGION_CODE_1 = 0,
+    NS_REGION_CODE_2,
+    NS_REGION_DATA,
+    NS_REGION_CMSE_1,  /* NSC */
+    NS_REGION_CMSE_2,  /* NSC */
+    NS_REGION_PERIPH,
+    NS_REGION_USER,
+};
+/*!
+    \brief      configure sau and idau
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+static void sau_and_idau_cfg(void)
+{
+  SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) |
+               ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk));
+
+  FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) |
+               ((FPU_FPCCR_TS_VAL        << FPU_FPCCR_TS_Pos) & FPU_FPCCR_TS_Msk) |
+               ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) |
+               ((FPU_FPCCR_CLRONRET_VAL  << FPU_FPCCR_CLRONRET_Pos) & FPU_FPCCR_CLRONRET_Msk);
+
+  /* Disable SAU */
+  TZ_SAU_Disable();
+
+#ifdef CODE_FROM_FLASH
+  /* Configures SAU regions to be non-secure */
+  /* CODE */
+  SAU->RNR  = NS_REGION_CODE_1;
+  SAU->RBAR = ((FLASH_BASE_NS + FLASH_AREA_1_OFFSET)
+               & SAU_RBAR_BADDR_Msk);
+  SAU->RLAR = ((FLASH_BASE_NS + FLASH_AREA_1_OFFSET + FLASH_AREA_1_SIZE - 1)
+               & SAU_RLAR_LADDR_Msk)
+              | SAU_RLAR_ENABLE_Msk;
+
+  SAU->RNR  = NS_REGION_CODE_2;
+  SAU->RBAR = ((FLASH_BASE_NS + FLASH_AREA_3_OFFSET)
+               & SAU_RBAR_BADDR_Msk);
+  SAU->RLAR = ((FLASH_BASE_NS + FLASH_AREA_3_OFFSET + FLASH_AREA_3_SIZE - 1)
+               & SAU_RLAR_LADDR_Msk)
+              | SAU_RLAR_ENABLE_Msk;
+
+  /* DATA */
+  SAU->RNR  = NS_REGION_DATA;
+  SAU->RBAR = ((RAM_BASE_NS + RAM_BANK3_OFFSET)
+               & SAU_RBAR_BADDR_Msk);
+  SAU->RLAR = ((RAM_BASE_NS + RAM_BANK3_OFFSET + RAM_BANK3_SIZE + RAM_BANK4_SIZE - 1)
+               & SAU_RLAR_LADDR_Msk)
+              | SAU_RLAR_ENABLE_Msk;
+
+  /* Configures veneers region to be non-secure callable */
+  SAU->RNR  = NS_REGION_CMSE_1;
+  SAU->RBAR = ((FLASH_BASE_S + FLASH_AREA_0_CMSE_OFFSET)
+               & SAU_RBAR_BADDR_Msk);
+  SAU->RLAR = ((FLASH_BASE_S + FLASH_AREA_0_CMSE_OFFSET + FLASH_AREA_0_CMSE_SIZE - 1)
+               & SAU_RLAR_LADDR_Msk)
+              | SAU_RLAR_ENABLE_Msk
+              | SAU_RLAR_NSC_Msk;
+
+  SAU->RNR  = NS_REGION_CMSE_2;
+  SAU->RBAR = ((FLASH_BASE_S + FLASH_AREA_2_CMSE_OFFSET)
+               & SAU_RBAR_BADDR_Msk);
+  SAU->RLAR = ((FLASH_BASE_S + FLASH_AREA_2_CMSE_OFFSET + FLASH_AREA_2_CMSE_SIZE - 1)
+               & SAU_RLAR_LADDR_Msk)
+              | SAU_RLAR_ENABLE_Msk
+              | SAU_RLAR_NSC_Msk;
+#elif defined (CODE_FROM_SRAM)
+  /* Configures SAU regions to be non-secure */
+  /* CODE */
+  SAU->RNR  = NS_REGION_CODE_1;
+  SAU->RBAR = ((RAM_BASE_NS + RAM_BANK4_OFFSET)
+               & SAU_RBAR_BADDR_Msk);
+  SAU->RLAR = ((RAM_BASE_NS + RAM_BANK4_OFFSET + RAM_BANK4_SIZE - 1)
+               & SAU_RLAR_LADDR_Msk)
+              | SAU_RLAR_ENABLE_Msk;
+
+  /* DATA */
+  SAU->RNR  = NS_REGION_DATA;
+  SAU->RBAR = ((RAM_BASE_NS + RAM_BANK2_OFFSET)
+               & SAU_RBAR_BADDR_Msk);
+  SAU->RLAR = ((RAM_BASE_NS + RAM_BANK2_OFFSET + RAM_BANK2_SIZE - 1)
+               & SAU_RLAR_LADDR_Msk)
+              | SAU_RLAR_ENABLE_Msk;
+
+  /* Configures veneers region to be non-secure callable */
+  SAU->RNR  = NS_REGION_CMSE_1;
+  SAU->RBAR = ((RAM_BASE_S + RAM_BANK1_CMSE_OFFSET)
+               & SAU_RBAR_BADDR_Msk);
+  SAU->RLAR = ((RAM_BASE_S + RAM_BANK1_CMSE_OFFSET + RAM_BANK1_CMSE_SIZE - 1)
+               & SAU_RLAR_LADDR_Msk)
+              | SAU_RLAR_ENABLE_Msk
+              | SAU_RLAR_NSC_Msk;
+#endif
+
+  /* Configure the peripherals space */
+  SAU->RNR  = NS_REGION_PERIPH;
+  SAU->RBAR = (PERIPH_BASE_NS & SAU_RBAR_BADDR_Msk);
+  SAU->RLAR = ((PERIPH_BASE_NS + 0xFFFFFFF) & SAU_RLAR_LADDR_Msk)
+              | SAU_RLAR_ENABLE_Msk;
+
+  /* Force memory writes before continuing */
+  __DSB();
+  /* Flush and refill pipeline with updated permissions */
+  __ISB();
+
+  /* Enable SAU */
+  TZ_SAU_Enable();
+
+  /* Lock SAU config */
+  //FIXME
+  //__HAL_RCC_SYSCFG_CLK_ENABLE();
+  //SYSCFG->CSLCKR |= SYSCFG_CSLCKR_LOCKSAU;
+}
+#endif
+/* NVIC interrupt target state configuration */
+/*!
+    \brief      configure nvic interrupts
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void mbl_nvic_its_config(void)
+{
+    uint32_t sz;
+    int i;
+
+    sz = sizeof(NVIC->ITNS)/sizeof(NVIC->ITNS[0]);
+    for (i = 0; i < sz; i++) {
+        NVIC->ITNS[i] = 0xFFFFFFFF;
+    }
+}
+/*!
+    \brief      configure gpio attribute
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void mbl_gpio_attr_config(void)
+{
+    /* RFIO pins */
+    gpio_bit_reset_sec_cfg(GPIOA, GPIO_PIN_9);
+    gpio_bit_reset_sec_cfg(GPIOA, GPIO_PIN_10);
+    gpio_bit_reset_sec_cfg(GPIOA, GPIO_PIN_11);
+    gpio_bit_reset_sec_cfg(GPIOA, GPIO_PIN_12);
+
+    /* USART pins */
+    gpio_bit_reset_sec_cfg(GPIOA, GPIO_PIN_8);
+    gpio_bit_reset_sec_cfg(GPIOB, GPIO_PIN_15);
+}
+/*!
+    \brief      configure sram block secure access mode
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void mbl_sram_mpcbb_config(void)
+{
+#ifndef ROM_SELF_TEST
+    static const uint32_t groups[] = {TZBMPC0, TZBMPC1, TZBMPC2, TZBMPC3};
+    static const uint32_t sizes[] = {0, 0x10000, 0x20000, 0x40000, 0x70000}; /* Start addresses of 4 SRAMs */
+    const uint32_t address = RE_NSPE_DATA_START;
+    uint32_t start_block, end_block, array_sz;
+    int32_t i;
+
+    array_sz = (sizeof(groups)/sizeof(groups[0]));
+    for (i = array_sz - 1; i >= 0; i--) {
+        if (address >= sizes[i + 1]) {
+            continue;
+        }
+        start_block = address > sizes[i] ? (address - sizes[i]) >> 8 : 0;
+        end_block = (sizes[i + 1] - sizes[i]) >> 8;
+        for (uint32_t j = start_block; j < end_block; j++) {
+            tzpcu_tzbmpc_block_secure_access_mode_config(groups[i], j, BLOCK_SECURE_ACCESS_MODE_NSEC);
+        }
+    }
+#else
+    int32_t i;
+    uint32_t blk_num = (RE_NSPE_DATA_START >> 8);
+    for (i = blk_num; i < 768; i++) {  /* SRAM4: 192K */
+        tzpcu_tzbmpc_block_secure_access_mode_config(TZBMPC3, i, BLOCK_SECURE_ACCESS_MODE_NSEC);
+    }
+    tzgpc_tzbmpc_secure_illegal_access_disable_config(TZBMPC3, SECURE_ILLEGAL_ACCESS_DISABLE);
+#endif
+}
+
+/*!
+    \brief      initialize flash water mark secure pages
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void mbl_flash_wm_init(void)
+{
+    if (IS_SIP_FLASH()) {
+        if (OBSTAT_FMCOB()) {
+            /* unlock the flash program erase controller */
+            fmc_unlock();
+            ob_unlock();
+
+            /* clear pending flags */
+            fmc_flag_clear(FMC_FLAG_END | FMC_FLAG_SECERR | FMC_FLAG_WPERR);
+
+            /* Set MBL region as secure */
+            ob_secmark_config(0, 0x3FF, SECM_INDEX2);
+
+            /* lock the flash program erase controller */
+            ob_lock();
+            fmc_lock();
+        }
+    }
+}
+
+/*!
+    \brief      configure flash water secure pages
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void mbl_flash_wm_config(uint8_t boot_idx)
+{
+    if (IS_SIP_FLASH()) {
+        uint32_t ota_spage, ota_epage;
+        if (boot_idx == IMAGE_0) {
+            ota_spage = (RE_IMG_1_PROT_OFFSET >> 12);
+            ota_epage = (RE_IMG_1_END_OFFSET >> 12) - 1;
+        } else {
+            ota_spage = (RE_IMG_0_PROT_OFFSET >> 12);
+            ota_epage = (RE_IMG_1_PROT_OFFSET >> 12) - 1;
+        }
+
+        /* unlock the flash program erase controller */
+        fmc_unlock();
+        ob_unlock();
+
+        /* clear pending flags */
+        fmc_flag_clear(FMC_FLAG_END | FMC_FLAG_SECERR | FMC_FLAG_WPERR);
+
+        if (OBSTAT_FMCOB()) {
+            /* Set MBL region as secure */
+            ob_secmark_config(0, ((RE_IMG_0_NSPE_OFFSET >> 12) - 1), SECM_INDEX2);
+            /* Set IMAGE-not-running region as secure */
+            ob_secmark_config(ota_spage, ota_epage, SECM_INDEX3);
+        } else {
+            /* Set MBL region as secure */
+            ob_secmark_config(0, ((RE_IMG_0_NSPE_OFFSET >> 12) - 1), SECM_INDEX0);
+            /* Set IMAGE-not-running region as secure */
+            ob_secmark_config(ota_spage, ota_epage, SECM_INDEX1);
+            ob_secmark_config(0x3FF, 0, SECM_INDEX2);
+            ob_secmark_config(0x3FF, 0, SECM_INDEX3);
+        }
+        /* lock the flash program erase controller */
+        ob_lock();
+        fmc_lock();
+    } else {
+        tzpcu_non_secure_mark_struct wm;
+
+        wm.memory_type = QSPI_FLASH_MEM;
+        wm.region_number = NON_SECURE_MARK_REGION0;
+        if (boot_idx == IMAGE_0) {
+            wm.start_address = RE_IMG_0_NSPE_OFFSET;
+            wm.length = RE_IMG_1_PROT_OFFSET - RE_IMG_0_NSPE_OFFSET;
+        } else {
+            wm.start_address = RE_IMG_1_NSPE_OFFSET;
+            wm.length = RE_IMG_1_END_OFFSET - RE_IMG_1_NSPE_OFFSET;
+        }
+        tzpcu_tzspc_emnsm_config(&wm);
+    }
+}
+
+/*!
+    \brief      configure system reset
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void mbl_system_reset_config(void)
+{
+    uint32_t reg_value;
+
+    //struct sysctrl_t *sysctrl = (struct sysctrl_t *)CMSDK_SYSCTRL_BASE_S;
+    reg_value = SCB->AIRCR;
+
+    /* Enable system reset request for CPU 0, to be triggered via
+     * NVIC_SystemReset function.
+     */
+    //sysctrl->resetmask |= ENABLE_CPU0_SYSTEM_RESET_REQUEST;
+
+    /* Clear SCB_AIRCR_VECTKEY value */
+    reg_value &= ~(uint32_t)(SCB_AIRCR_VECTKEY_Msk);
+
+    /* Enable system reset request only to the secure world */
+    //reg_value |= (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB_AIRCR_SYSRESETREQS_Msk | SCB_AIRCR_PRIS_Msk);
+    reg_value &= ~(uint32_t)(SCB_AIRCR_SYSRESETREQS_Msk);
+    reg_value |= (uint32_t)(0x5FAUL << SCB_AIRCR_VECTKEY_Pos);
+
+    SCB->AIRCR = reg_value;
+}
+
+/*!
+    \brief      setup secure for non-secure processing environment
+    \param[in]  boot_idx: boot index
+    \param[out] none
+    \retval     result of setup secure for nspe
+*/
+int mbl_sec_for_nspe_setup(uint8_t boot_idx)
+{
+    /* System reset options */
+    mbl_system_reset_config();
+
+    //__enable_irq();
+
+    /* GPIO: set gpios used by WIFI to non-secure */
+    mbl_gpio_attr_config();
+
+    /* Flash: only first ten pages(40KB) are secure */
+    mbl_flash_wm_config(boot_idx);
+
+    /* SRAM: only first ten blocks(0xA00 Bytes) are secure */
+    mbl_sram_mpcbb_config();
+
+    /* Target every interrupt to NS; unimplemented interrupts will be WI */
+    mbl_nvic_its_config();
+
+    rom_trace_ex(ROM_ALWAYS, "Setup security settings for NSPE OK. \r\n");
+
+    return 0;
+}
+
+/*!
+    \brief      mapping flash offset
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void flash_offset_mapping(void)
+{
+    fmc_unlock();
+    ob_unlock();
+    fmc_offset_region_config(RE_IMG_0_PROT_OFFSET >> 12, (RE_IMG_1_PROT_OFFSET >> 12) - 1);
+    fmc_offset_value_config((RE_IMG_1_PROT_OFFSET - RE_IMG_0_PROT_OFFSET) >> 12);
+    ob_lock();
+    fmc_lock();
+}
+
+#else
+int mbl_sec_for_nspe_setup(void)
+{
+}
+/*!
+    \brief      mapping flash offset
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void flash_offset_mapping(void)
+{
+}
+#endif

MBL/source/mbl_target_config.h

@@ -0,0 +1,42 @@
+/*!
+    \file    mbl_target_config.h
+    \brief   MBL target configuration for GD32W51x WiFi SDK
+
+    \version 2021-10-30, V1.0.0, firmware for GD32W51x
+*/
+
+/*
+    Copyright (c) 2021, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice,
+       this list of conditions and the following disclaimer in the documentation
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors
+       may be used to endorse or promote products derived from this software without
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#ifndef __MBL_TARGET_CONFIG_H__
+#define __MBL_TARGET_CONFIG_H__
+
+void mbl_flash_wm_init(void);
+int  mbl_sec_for_nspe_setup(uint8_t boot_idx);
+void flash_offset_mapping(void);
+
+#endif  /* __MBL_TARGET_CONFIG_H__ */

MBL/source_ns/CMakeLists.txt

@@ -0,0 +1,67 @@
+
+cmake_minimum_required(VERSION 3.15)
+set(TARGET_EXE mbl-ns)
+set(TAGET_PROJECT_DIR ${PROJECT_SOURCE_DIR}/MBL/Project)
+add_executable(${TARGET_EXE})
+
+add_definitions(
+    -DPLATFORM_GDM32
+)
+
+set_target_properties(${TARGET_EXE}
+    PROPERTIES
+        SUFFIX ".axf"
+        ARCHIVE_OUTPUT_DIRECTORY "${TAGET_PROJECT_DIR}/GCC/output/lib"
+        LIBRARY_OUTPUT_DIRECTORY "${TAGET_PROJECT_DIR}/GCC/output/lib"
+        RUNTIME_OUTPUT_DIRECTORY "${TAGET_PROJECT_DIR}/GCC/output/bin"
+)
+
+target_sources(${TARGET_EXE}
+    PRIVATE
+        mbl_api.c
+        mbl_flash.c
+        mbl_image.c
+        mbl_ns.c
+        mbl_qspi_flash.c
+        mbl_sys.c
+        mbl_uart.c
+    )
+
+target_sources(${TARGET_EXE}
+    PRIVATE
+        ${PROJECT_SOURCE_DIR}/NSPE/Firmware/GD32W51x_standard_peripheral/Source/gd32w51x_fmc.c
+        ${PROJECT_SOURCE_DIR}/NSPE/Firmware/GD32W51x_standard_peripheral/Source/gd32w51x_fwdgt.c
+        ${PROJECT_SOURCE_DIR}/NSPE/Firmware/GD32W51x_standard_peripheral/Source/gd32w51x_gpio.c
+        ${PROJECT_SOURCE_DIR}/NSPE/Firmware/GD32W51x_standard_peripheral/Source/gd32w51x_icache.c
+        ${PROJECT_SOURCE_DIR}/NSPE/Firmware/GD32W51x_standard_peripheral/Source/gd32w51x_misc.c
+        ${PROJECT_SOURCE_DIR}/NSPE/Firmware/GD32W51x_standard_peripheral/Source/gd32w51x_qspi.c
+        ${PROJECT_SOURCE_DIR}/NSPE/Firmware/GD32W51x_standard_peripheral/Source/gd32w51x_rcu.c
+        ${PROJECT_SOURCE_DIR}/NSPE/Firmware/GD32W51x_standard_peripheral/Source/gd32w51x_usart.c
+    )
+
+target_sources(${TARGET_EXE}
+    PRIVATE
+        ../platform/gdm32/cmsis_core/mbl_system_gdm32.c
+        ../platform/gdm32/gcc/mbl_startup_gdm32.s
+    )
+
+target_include_directories(${TARGET_EXE}
+    PRIVATE
+        ${PROJECT_SOURCE_DIR}/NSPE/Firmware/GD32W51x_standard_peripheral/Include
+)
+
+target_add_scatter_file(${TARGET_EXE}
+    ../platform/gdm32/gcc/mbl_gdm32_ns.ld
+)
+
+
+target_link_options(${TARGET_EXE}
+    PUBLIC
+    -Wl,--just-symbols=${PROJECT_SOURCE_DIR}/ROM-EXPORT/symbol/rom_symbol.gcc
+    -Wl,-Map=${RUNTIME_OUTPUT_DIRECTORY}/${TARGET_EXE}.map
+)
+
+add_custom_command(TARGET ${TARGET_EXE} POST_BUILD
+    COMMAND ${TAGET_PROJECT_DIR}/mbl_afterbuild.bat ${TAGET_PROJECT_DIR}/GCC/output/bin ${TARGET_EXE} GCC \"\"
+    COMMENT "Building ${TARGET_EXE}"
+)

MBL/source_ns/mbl_api.c

@@ -0,0 +1,55 @@
+/*!
+    \file    mbl_api.c
+    \brief   Non-secure MBL API for GD32W51x WiFi SDK
+
+    \version 2021-10-30, V1.0.0, firmware for GD32W51x
+*/
+
+/*
+    Copyright (c) 2021, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice,
+       this list of conditions and the following disclaimer in the documentation
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors
+       may be used to endorse or promote products derived from this software without
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#include "mbl_trace.h"
+#include "mbl_api.h"
+
+const uint32_t mbl_api[MBL_MAX_API_NUM] = {
+    /* SYS STATUS */
+    (uint32_t)sys_status_show,
+    (uint32_t)sys_status_dump,
+    (uint32_t)sys_status_get,
+    (uint32_t)sys_status_set,
+    (uint32_t)sys_err_process_set,
+    (uint32_t)sys_trace_level_set,
+    (uint32_t)sys_img_flag_set,
+    (uint32_t)sys_running_img_set,
+    (uint32_t)sys_fw_version_set,
+    (uint32_t)sys_trng_seed_set,
+    /* FLASH */
+    (uint32_t)flash_indirect_read,
+    (uint32_t)flash_verify_read,
+    (uint32_t)flash_fast_write,
+    (uint32_t)flash_erase,
+};

MBL/source_ns/mbl_api.h

@@ -0,0 +1,106 @@
+/*!
+    \file    mbl_api.h
+    \brief   Non-secure MBL API for GD32W51x WiFi SDK
+
+    \version 2021-10-30, V1.0.0, firmware for GD32W51x
+*/
+
+/*
+    Copyright (c) 2021, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice,
+       this list of conditions and the following disclaimer in the documentation
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors
+       may be used to endorse or promote products derived from this software without
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#ifndef __MBL_API_H__
+#define __MBL_API_H__
+#include "mbl_region.h"
+#include "mbl_trace.h"
+#include "mbl_sys.h"
+#include "mbl_image.h"
+#include "mbl_flash.h"
+#include "rom_api.h"
+
+#define MBL_MAX_API_NUM     (MBL_API_SIZE >> 2)
+
+struct mbl_api_t {
+    void (*sys_status_show)(void);
+    void (*sys_status_dump)(int is_ping);
+    int (*sys_status_get)(uint8_t type, uint8_t len, uint8_t* pval);
+    int (*sys_status_set)(uint8_t type, uint8_t len, uint8_t* pval);
+    int (*sys_err_process_set)(uint8_t method);
+    int (*sys_trace_level_set)(uint8_t trace_level);
+    int (*sys_img_flag_set)(uint8_t idx, uint8_t mask, uint8_t flag);
+    int (*sys_running_img_set)(uint8_t idx);
+    int (*sys_fw_version_set)(uint32_t type, uint32_t version);
+    int (*sys_trng_seed_set)(uint8_t val);
+    int (*flash_indirect_read)(uint32_t offset, void *data, int len);
+    int (*flash_verify_read)(uint32_t offset, void *data, int len);
+    int (*flash_fast_write)(uint32_t offset, const void *data, int len);
+    int (*flash_erase)(uint32_t offset, int len);
+};
+
+#if (RE_IMG_0_NSPE_OFFSET == 0)
+/* 0x08000000: NSPE  */
+#define mbl_sys_status_show()               mbl_dummy_func(__func__, "mbl_sys_status_show")
+#define mbl_sys_status_dump(a)              mbl_dummy_func(__func__, "mbl_sys_status_dump")
+#define mbl_sys_status_get(a, b, c)         mbl_dummy_func(__func__, "mbl_sys_status_get")
+#define mbl_sys_status_set(a, b, c)         mbl_dummy_func(__func__, "mbl_sys_status_set")
+#define mbl_sys_set_err_process(a)          mbl_dummy_func(__func__, "mbl_sys_set_err_process")
+#define mbl_sys_trace_level_set(a)          mbl_dummy_func(__func__, "mbl_sys_trace_level_set")
+#define mbl_sys_img_flag_set(a, b, c)       mbl_dummy_func(__func__, "mbl_sys_img_flag_set")
+#define mbl_sys_running_img_set(a)          mbl_dummy_func(__func__, "mbl_sys_running_img_set")
+#define mbl_sys_fw_version_set(a, b)        mbl_dummy_func(__func__, "mbl_sys_fw_version_set")
+#define mbl_sys_trng_seed_set(a)            mbl_dummy_func(__func__, "mbl_sys_trng_seed_set")
+#define mbl_flash_indirect_read(a, b, c)    mbl_dummy_func(__func__, "mbl_flash_indirect_read")
+#define mbl_flash_verify_read(a, b, c)      mbl_dummy_func(__func__, "mbl_flash_verify_read")
+#define mbl_flash_write(a, b, c)            mbl_dummy_func(__func__, "mbl_flash_write")
+#define mbl_flash_erase(a, b)               mbl_dummy_func(__func__, "mbl_flash_erase")
+static __INLINE int mbl_dummy_func(const char *caller, const char *func)
+{
+    printf("%s: %s is dummy.\r\n", caller, func);
+    return -1;
+}
+#else
+/* 0x08000000: MBL  */
+extern struct mbl_api_t *p_mbl_api;
+#define mbl_sys_status_show                 p_mbl_api->sys_status_show
+#define mbl_sys_status_dump                 p_mbl_api->sys_status_dump
+#define mbl_sys_status_get                  p_mbl_api->sys_status_get
+#define mbl_sys_status_set                  p_mbl_api->sys_status_set
+#define mbl_sys_set_err_process             p_mbl_api->sys_err_process_set
+#define mbl_sys_trace_level_set             p_mbl_api->sys_trace_level_set
+#define mbl_sys_img_flag_set                p_mbl_api->sys_img_flag_set
+#define mbl_sys_running_img_set             p_mbl_api->sys_running_img_set
+#define mbl_sys_fw_version_set              p_mbl_api->sys_fw_version_set
+#define mbl_sys_trng_seed_set               p_mbl_api->sys_trng_seed_set
+#define mbl_flash_indirect_read             p_mbl_api->flash_indirect_read
+#define mbl_flash_verify_read               p_mbl_api->flash_verify_read
+#define mbl_flash_write                     p_mbl_api->flash_fast_write
+#define mbl_flash_erase                     p_mbl_api->flash_erase
+#endif  /*(RE_IMG_0_NSPE_OFFSET == 0) */
+
+extern struct rom_api_s_t *p_rom_api_s;
+#define mbl_mutex_set_func                    p_rom_api_s->set_mutex_func
+
+#endif  //__MBL_API_H__

MBL/source_ns/mbl_flash.c

@@ -0,0 +1,553 @@
+/*!
+    \file    mbl_flash.c
+    \brief   Non-secure MBL flash file for GD32W51x WiFi SDK
+
+    \version 2021-10-30, V1.0.0, firmware for GD32W51x
+*/
+
+/*
+    Copyright (c) 2021, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice,
+       this list of conditions and the following disclaimer in the documentation
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors
+       may be used to endorse or promote products derived from this software without
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#include "gd32w51x.h"
+#include "config_gdm32_ntz.h"
+#include "mbl_trace.h"
+#include "mbl_flash.h"
+
+/*!
+    \brief      get flash cache enabled state
+    \param[in]  none
+    \param[out] none
+    \retval     result of state(1: enabled, or 0: disabled)
+*/
+int is_flash_cache_enabled(void)
+{
+    if (ICACHE_CTL & ICACHE_CTL_EN)
+        return 1;
+    else
+        return 0;
+}
+
+/*!
+    \brief      disable flash cache
+    \param[in]  none
+    \param[out] none
+    \retval     0
+*/
+int flash_cache_disable(void)
+{
+    icache_disable();
+    return 0;
+}
+
+/*!
+    \brief      enable flash cache
+    \param[in]  none
+    \param[out] none
+    \retval     0
+*/
+int flash_cache_enable(void)
+{
+    icache_enable();
+    return 0;
+}
+
+/*!
+    \brief      check memory structure is SIP Flash or EXT Flash
+    \param[in]  none
+    \param[out] none
+    \retval     memory structure(1: FMC mode: SIP Flash, 0: EXT Flash)
+*/
+int is_sip_flash(void)
+{
+    return (OBSTAT_NQSPI() == SET);
+}
+
+/*!
+    \brief      get flash offset valid state
+    \param[in]  offset: flash offset
+    \param[out] none
+    \retval     result of state(1: offset is valid, or 0: offset is invalid)
+*/
+int is_valid_flash_offset(uint32_t offset)
+{
+    if (offset < flash_total_size()) {
+        return 1;
+    }
+    return 0;
+}
+
+/*!
+    \brief      get flash addr valid state
+    \param[in]  addr: flash address
+    \param[out] none
+    \retval     result of state(1: addr is valid, or 0: addr is not valid)
+*/
+int is_valid_flash_addr(uint32_t addr)
+{
+    int bvalid = 0;
+    if ((addr >= FLASH_BASE) && (addr < (FLASH_BASE + flash_total_size()))) {
+        bvalid = 1;
+    }
+    return bvalid;
+}
+
+/*!
+    \brief      get flash total size
+    \param[in]  none
+    \param[out] none
+    \retval     flash total size
+*/
+uint32_t flash_total_size(void)
+{
+    return FLASH_TOTAL_SIZE;
+}
+
+/*!
+    \brief      get flash erase size
+    \param[in]  none
+    \param[out] none
+    \retval     flash erase size. sip flash page size or qspi sector size
+*/
+uint32_t flash_erase_size(void)
+{
+    if (is_sip_flash()) {
+        return FLASH_SIP_PAGE_SIZE;
+    } else {
+        return FLASH_QSPI_SECTOR_SIZE;
+    }
+}
+
+/*!
+    \brief      configure no real time decrypt areas for flash
+    \param[in]  nd_idx: no decrypt register index
+    \param[in]  start_page: start page of no real time decrypt area
+    \param[in]  end_page: end page of no real time decrypt area
+    \param[out] none
+    \retval     none
+*/
+void flash_nodec_config(uint32_t nd_idx, uint32_t start_page, uint32_t end_page)
+{
+    if (is_sip_flash()) {
+        /* unlock the flash program erase controller */
+        fmc_unlock();
+        /* unlock the option byte operation (include SECWM/HDP/WRP/NODEC/OFRG/OFVR) */
+        ob_unlock();
+        /* clear pending flags */
+        fmc_flag_clear(FMC_FLAG_END | FMC_FLAG_WPERR);
+
+        /* set no OTFDEC region for sip flash */
+        fmc_no_rtdec_config(start_page, end_page, nd_idx);
+
+        /* lock the option byte operation */
+        ob_lock();
+        /* lock the flash program erase controller */
+        fmc_lock();
+    }
+}
+
+/*!
+    \brief      config flash offset region and value
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void flash_offset_mapping(void)
+{
+    fmc_unlock();
+    ob_unlock();
+    fmc_offset_region_config(RE_IMG_0_PROT_OFFSET >> 12, (RE_IMG_1_PROT_OFFSET >> 12) - 1);
+    fmc_offset_value_config((RE_IMG_1_PROT_OFFSET - RE_IMG_0_PROT_OFFSET) >> 12);
+    ob_lock();
+    fmc_lock();
+}
+
+/*!
+    \brief      initialize flash
+    \param[in]  none
+    \param[out] none
+    \retval     0
+*/
+int flash_init(void)
+{
+    if (!is_sip_flash()) {
+        qspi_flash_config(3);
+    }
+    return 0;
+}
+
+/*!
+    \brief      read flash
+    \param[in]  offset: flash offset
+    \param[out] data: pointer to the buffer store flash read data
+    \param[in]  len: length of data read from flash
+    \retval     result of read flash(0: read ok, or -1: read error)
+*/
+int flash_read(uint32_t offset, void *data, int len)
+{
+    uint32_t i;
+    uint32_t dst = (uint32_t)data;
+    uint32_t left;
+
+    if (!is_valid_flash_offset(offset) || data == NULL
+        || len <= 0 || !is_valid_flash_offset(offset + len - 1)) {
+        return -1;
+    }
+
+    if ((offset & 3) || (dst & 3)) {
+        for (i = 0; i < len; i++) {
+            ((uint8_t *)data)[i] = *(uint8_t *)(FLASH_BASE + offset + i);
+        }
+    } else {
+        left = (len & 3);
+        len -= left;
+        for (i = 0; i < len; i += 4) {
+            *(uint32_t *)(dst + i) = *(uint32_t *)(FLASH_BASE + offset + i);
+        }
+        if (left > 0)
+            memcpy((uint8_t *)(dst + len), (uint8_t *)(FLASH_BASE + offset + len), left);
+    }
+    return 0;
+}
+
+/*!
+    \brief      read flash indirectly
+                consider encrypted image, two flash read api will be needed,
+                one is directly read and flash value is decrypted, another is indirect
+                read and no decryption is done.
+    \param[in]  offset: flash offset
+    \param[out] data: pointer to the buffer store flash read data
+    \param[in]  len: length of data read from flash
+    \retval     result of read flash(0: read ok, or -1: read error)
+*/
+int flash_indirect_read(uint32_t offset, void *data, int len)
+{
+    int cache_enabled = 0;
+    int ret;
+
+    if (is_flash_cache_enabled()) {
+        flash_cache_disable();
+        cache_enabled = 1;
+    }
+
+    if (is_sip_flash()) {
+        ret = flash_read(offset, data, len);
+
+    } else {
+        if (!is_valid_flash_offset(offset) || data == NULL
+            || len <= 0 || !is_valid_flash_offset(offset + len - 1)) {
+            ret = -1;
+            goto Exit;
+        }
+        __disable_irq();
+        ret = qspi_flash_read(FLASH_START_QSPI + offset, data, len);
+        __enable_irq();
+    }
+
+Exit:
+    if (cache_enabled)
+        flash_cache_enable();
+    return ret;
+}
+
+/*!
+    \brief      read flash while verify image during OTA
+    \param[in]  offset: flash offset
+    \param[out] data: pointer to the buffer store flash read data
+    \param[in]  len: length of data read from flash
+    \retval     result of read flash(0: read ok, or -1: read error)
+*/
+int flash_verify_read(uint32_t offset, void *data, int len)
+{
+    int cache_enabled = 0;
+    int ret;
+
+    uint32_t fmc_ofvr_temp = FMC_OFVR;
+
+    if (is_flash_cache_enabled()) {
+        flash_cache_disable();
+        cache_enabled = 1;
+    }
+
+    if (is_sip_flash()) {
+        __disable_irq(); //disable all irqs here, cause it will change the FMC_OFVR value
+
+        fmc_unlock();
+        ob_unlock();
+        fmc_offset_value_config(0);// reset FMC_OFVR to 0
+        ob_lock();
+        fmc_lock();
+
+        ret = flash_read(offset, data, len);
+
+        fmc_unlock();
+        ob_unlock();
+        fmc_offset_value_config(fmc_ofvr_temp);// recovery FMC_OFVR value
+        ob_lock();
+        fmc_lock();
+
+        __enable_irq();// enable irq here
+    } else {
+        if (!is_valid_flash_offset(offset) || data == NULL
+            || len <= 0 || !is_valid_flash_offset(offset + len - 1)) {
+            ret = -1;
+            goto Exit;
+        }
+        __disable_irq();
+        ret = qspi_flash_read(FLASH_START_QSPI + offset, data, len);
+        __enable_irq();
+    }
+
+Exit:
+    if (cache_enabled)
+        flash_cache_enable();
+    return ret;
+}
+
+
+/*!
+    \brief      write flash
+    \param[in]  offset: flash offset
+    \param[in]  data: pointer to the data write to flash
+    \param[in]  len: length of data write to flash
+    \param[out] none
+    \retval     result of write flash(0: write ok, or -1: write error)
+*/
+int flash_write(uint32_t offset, const void *data, int len)
+{
+    uint8_t *data_u8 = (uint8_t *)data;
+    uint32_t base_addr;
+
+    if (!is_valid_flash_offset(offset) || data == NULL
+        || len <= 0 || !is_valid_flash_offset(offset + len - 1)) {
+        return -1;
+    }
+
+    if (is_sip_flash()) {
+        uint32_t offset_align, val32;
+        int vb, act_len, i;
+        uint8_t val[4] = {0xFF, 0xFF, 0xFF, 0xFF};
+
+        base_addr = FLASH_BASE;
+        /* unlock the flash program erase controller */
+        fmc_unlock();
+        /* clear pending flags */
+        fmc_flag_clear(FMC_FLAG_END | FMC_FLAG_WPERR);
+
+        offset_align = (offset & ~0x3);
+
+        /* if offset is not 4-byte alignment */
+        vb = (offset & 0x3);
+        if (vb > 0) {
+            act_len = ((4 - vb) > len) ? len : (4 - vb);
+            for (i = 0; i < act_len; i++) {
+                val[vb + i] = *(data_u8 + i);
+            }
+            fmc_word_program((base_addr + offset_align), *(uint32_t *)val);
+            offset_align += 4;
+            data_u8 += act_len;
+            len -= act_len;
+        }
+
+        /* word program */
+        while (len >= 4) {
+            fmc_word_program((base_addr + offset_align), *(uint32_t *)data_u8);
+            offset_align += 4;
+            data_u8 += 4;
+            len -= 4;
+        }
+
+        /* if len is not 4-byte alignment */
+        val32 = 0xFFFFFFFF;
+        if (len > 0) {
+            while (len-- > 0) {
+                val32 = (val32 << 8);
+                val32 |= *(data_u8 + len);
+            }
+            fmc_word_program((base_addr + offset_align), val32);
+        }
+
+        /* lock the flash program erase controller */
+        fmc_lock();
+    } else {
+        uint32_t page_offset;
+        uint32_t size_to_program;
+
+        base_addr = FLASH_START_QSPI;
+        page_offset = (offset & (FLASH_QSPI_PAGE_SIZE - 1));
+        if (page_offset != 0) {
+            size_to_program = (len > FLASH_QSPI_PAGE_SIZE - page_offset) ? (FLASH_QSPI_PAGE_SIZE - page_offset) : len;
+            __disable_irq();
+            qspi_flash_page_program((base_addr + offset), data_u8, size_to_program);
+            __enable_irq();
+            offset += size_to_program;
+            data_u8 += size_to_program;
+            len -= size_to_program;
+        }
+
+        while (len > 0) {
+            size_to_program = (len > FLASH_QSPI_PAGE_SIZE) ? FLASH_QSPI_PAGE_SIZE : len;
+            __disable_irq();
+            qspi_flash_page_program((base_addr + offset), data_u8, size_to_program);
+            __enable_irq();
+            offset += size_to_program;
+            data_u8 += size_to_program;
+            len -= size_to_program;
+        }
+    }
+    return 0;
+}
+
+/*!
+    \brief      write flash fast
+    \param[in]  offset: flash offset
+    \param[in]  data: pointer to the data write to flash
+    \param[in]  len: length of data write to flash
+    \param[out] none
+    \retval     result of write flash(0: write ok, or -1: write error)
+*/
+int flash_fast_write(uint32_t offset, const void *data, int len)
+{
+    uint8_t *data_u8 = (uint8_t *)data;
+    uint32_t base_addr;
+    int ret = 0;
+
+    if (!is_valid_flash_offset(offset) || data == NULL
+        || len <= 0 || !is_valid_flash_offset(offset + len - 1)) {
+        return -1;
+    }
+
+    if (is_sip_flash()) {
+        uint8_t r, rr;
+        if (len <= 4)
+            return flash_write(offset, data, len);
+
+        r = 4 - (offset & 0x3);
+        rr = (offset + len) & 0x3;
+        r = r == 4 ? 0 : r;
+        if (r) {
+            ret = flash_write(offset, data, r);
+            if (ret)
+                return ret;
+        }
+
+        /* unlock the flash program erase controller */
+        fmc_unlock();
+        /* clear pending flags */
+        fmc_flag_clear(FMC_FLAG_END | FMC_FLAG_WPERR);
+
+        /* prevent interrupt handler from reading flash, it will disrupt the flash continuous programming pipeline */
+        __disable_irq();
+        ret = fmc_continuous_program(FLASH_BASE + offset + r, (uint32_t *)((uint8_t *)data + r), len - r - rr);
+        __enable_irq();
+
+        /* lock the flash program erase controller */
+        fmc_lock();
+
+        if (rr) {
+            ret = flash_write(offset + len - rr, ((uint8_t *)data + len - rr), rr);
+            if (ret)
+                return ret;
+        }
+    } else {
+        uint32_t page_offset;
+        uint32_t size_to_program;
+
+        base_addr = FLASH_START_QSPI;
+        page_offset = (offset & (FLASH_QSPI_PAGE_SIZE - 1));
+        if (page_offset != 0) {
+            size_to_program = (len > FLASH_QSPI_PAGE_SIZE - page_offset) ? (FLASH_QSPI_PAGE_SIZE - page_offset) : len;
+            __disable_irq();
+            qspi_flash_page_program((base_addr + offset), data_u8, size_to_program);
+            __enable_irq();
+            offset += size_to_program;
+            data_u8 += size_to_program;
+            len -= size_to_program;
+        }
+
+        while (len > 0) {
+            size_to_program = (len > FLASH_QSPI_PAGE_SIZE) ? FLASH_QSPI_PAGE_SIZE : len;
+            __disable_irq();
+            qspi_flash_page_program((base_addr + offset), data_u8, size_to_program);
+            __enable_irq();
+            offset += size_to_program;
+            data_u8 += size_to_program;
+            len -= size_to_program;
+        }
+    }
+    return ret;
+}
+
+/*!
+    \brief      erase flash
+    \param[in]  offset: flash offset
+    \param[in]  len: flash erase length
+    \param[out] none
+    \retval     result of erase flash(0: erase ok, or -1: erase error)
+*/
+int flash_erase(uint32_t offset, int len)
+{
+    int ret;
+    uint32_t erase_sz = flash_erase_size();
+    uint32_t page_start, sector_start;
+
+    if (!is_valid_flash_offset(offset)
+        || len <= 0 || !is_valid_flash_offset(offset + len - 1)) {
+        return -1;
+    }
+
+    if (is_sip_flash()) {
+        /* Get page start */
+        page_start = FLASH_BASE + (offset & (~(erase_sz - 1)));
+
+        /* unlock the flash program erase controller */
+        fmc_unlock();
+
+        /* clear pending flags */
+        fmc_flag_clear(FMC_FLAG_END | FMC_FLAG_OBERR | FMC_FLAG_WPERR);
+
+        while (len > 0) {
+            /* erase page */
+            ret = fmc_page_erase(page_start);
+            if (ret != FMC_READY)
+                return -2;
+            page_start += erase_sz;
+            len -= erase_sz;
+        }
+        /* lock the flash program erase controller */
+        fmc_lock();
+    } else {
+        sector_start = FLASH_START_QSPI + (offset & (~(erase_sz - 1)));
+        while (len > 0) {
+            __disable_irq();
+            qspi_flash_sector_erase(sector_start);
+            __enable_irq();
+            sector_start += erase_sz;
+            len -= erase_sz;
+        }
+    }
+    return 0;
+}

MBL/source_ns/mbl_flash.h

@@ -0,0 +1,65 @@
+/*!
+    \file    mbl_flash.h
+    \brief   Non-secure MBL flash file for GD32W51x WiFi SDK
+
+    \version 2021-10-30, V1.0.0, firmware for GD32W51x
+*/
+
+/*
+    Copyright (c) 2021, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice,
+       this list of conditions and the following disclaimer in the documentation
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors
+       may be used to endorse or promote products derived from this software without
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#ifndef __MBL_FLASH_H__
+#define __MBL_FLASH_H__
+
+#include "mbl_qspi_flash.h"
+
+#define FLASH_SIZE_SIP              (0x200000)
+#define FLASH_SIP_PAGE_SIZE         (0x1000)
+
+#define FLASH_TOTAL_SIZE            (is_sip_flash() ? FLASH_SIZE_SIP : FLASH_SIZE_QSPI)
+#define IS_SIP_FLASH()              (OBSTAT_NQSPI() == SET)
+
+int is_flash_cache_enabled(void);
+int flash_cache_disable(void);
+int flash_cache_enable(void);
+
+int is_sip_flash(void);
+int is_valid_flash_offset(uint32_t offset);
+int is_valid_flash_addr(uint32_t addr);
+uint32_t flash_total_size(void);
+uint32_t flash_erase_size(void);
+int flash_init(void);
+int flash_indirect_read(uint32_t offset, void *data, int len);
+int flash_verify_read(uint32_t offset, void *data, int len);
+int flash_read(uint32_t offset, void *data, int len);
+int flash_write(uint32_t offset, const void *data, int len);
+int flash_fast_write(uint32_t offset, const void *data, int len);
+int flash_erase(uint32_t offset, int len);
+void flash_nodec_config(uint32_t nd_idx, uint32_t start_page, uint32_t end_page);
+void flash_offset_mapping(void);
+
+#endif  /* __MBL_FLASH_H__ */

MBL/source_ns/mbl_image.c

@@ -0,0 +1,218 @@
+/*!
+    \file    mbl_image.c
+    \brief   Non-secure MBL image file for GD32W51x WiFi SDK
+
+    \version 2021-10-30, V1.0.0, firmware for GD32W51x
+*/
+
+/*
+    Copyright (c) 2021, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice,
+       this list of conditions and the following disclaimer in the documentation
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors
+       may be used to endorse or promote products derived from this software without
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#include "config_gdm32_ntz.h"
+#include "mbl_trace.h"
+#include "mbl_image.h"
+#include "mbl_sys.h"
+
+/*!
+    \brief      calculate checksum
+    \param[in]  ptr: array pointer to calculate checksum
+    \param[in]  sz: array size to calculate checksum
+    \param[out] none
+    \retval     checksum value
+*/
+uint32_t checksum_cal(uint8_t *ptr, uint32_t sz)
+{
+    uint32_t chksum = 0;
+    int i;
+
+    /* should be 4 bytes align */
+    sz = ((sz >> 2) << 2);
+
+    for (i = 0; i < sz; i += 4) {
+        chksum ^= *(uint32_t *)(ptr + i);
+    }
+
+    return chksum;
+}
+
+/*!
+    \brief      find boot image
+    \param[in]  none
+    \param[out] idx: pointer index of boot image
+    \param[out] image_offset: pointer offset of boot image
+    \retval     result of find boot image
+      \arg        0: find image success
+      \arg        -1: offset of image is null
+      \arg        -2: find image0 fail
+      \arg        -3: find image1 fail
+      \arg        -4: image1 has downloaded but image0 has not downloaded
+      \arg        -5: other fail
+*/
+int boot_image_find(OUT uint32_t *idx, OUT uint32_t *image_offset)
+{
+    uint8_t img0_stat = 0, img1_stat = 0;
+    uint8_t img0_found = 0, img1_found = 0;
+    int boot_idx = -1;
+    int ret, result = 0;
+
+    if (NULL == image_offset) {
+        result = -1;
+        goto Failed;
+    }
+
+    ret = sys_status_get(SYS_IMAGE0_STATUS, LEN_SYS_IMAGE_STATUS, &img0_stat);
+    if (ret <= SYS_STATUS_FOUND_ERR) {
+        result = -2;
+        goto Failed;
+    } else if (ret == SYS_STATUS_FOUND_OK) {
+        img0_found = 1;
+    } else {  // SYS_STATUS_NOT_FOUND
+        img0_found = 0;
+    }
+    ret = sys_status_get(SYS_IMAGE1_STATUS, LEN_SYS_IMAGE_STATUS, &img1_stat);
+    if (ret <= SYS_STATUS_FOUND_ERR) {
+        result = -3;
+        goto Failed;
+    } else if (ret == SYS_STATUS_FOUND_OK) {
+        img1_found = 1;
+    } else {  // SYS_STATUS_NOT_FOUND
+        img1_found = 0;
+    }
+
+    /* Image0 never downloaded, Image1 should not be downloaded too. */
+    if (!img0_found && img1_found) {
+        result = -4;
+        goto Failed;
+    }
+
+    if (!img0_found && !img1_found) {
+        /* ISP newly downloaded */
+        sys_img_flag_set(IMAGE_0, IMG_FLAG_NEWER_MASK, IMG_FLAG_NEWER);
+        boot_idx = 0;
+        goto ImgSelected;
+    }
+
+    if (img0_found && ((img0_stat & IMG_FLAG_NEWER_MASK) == IMG_FLAG_NEWER)) {
+        if (((img0_stat & IMG_FLAG_VERIFY_MASK) != IMG_FLAG_VERIFY_FAIL)
+            && ((img0_stat & IMG_FLAG_IA_MASK) != IMG_FLAG_IA_FAIL)) {
+            boot_idx = 0;
+            goto ImgSelected;
+        }
+    }
+
+    if (img1_found && ((img1_stat & IMG_FLAG_NEWER_MASK) == IMG_FLAG_NEWER)) {
+        if (((img1_stat & IMG_FLAG_VERIFY_MASK) != IMG_FLAG_VERIFY_FAIL)
+            && ((img1_stat & IMG_FLAG_IA_MASK) != IMG_FLAG_IA_FAIL)) {
+            boot_idx = 1;
+            goto ImgSelected;
+        }
+    }
+
+    if (img0_found && ((img0_stat & IMG_FLAG_VERIFY_MASK) == IMG_FLAG_VERIFY_OK)
+        && ((img0_stat & IMG_FLAG_IA_MASK) == IMG_FLAG_IA_OK)) {
+        boot_idx = 0;
+        goto ImgSelected;
+    }
+
+    if (img1_found && ((img1_stat & IMG_FLAG_VERIFY_MASK) == IMG_FLAG_VERIFY_OK)
+        && ((img1_stat & IMG_FLAG_IA_MASK) == IMG_FLAG_IA_OK)) {
+        boot_idx = 1;
+        goto ImgSelected;
+    }
+
+    if (boot_idx == -1) {
+        result = -5;
+        goto Failed;
+    }
+
+ImgSelected:
+    *idx = boot_idx;
+    *image_offset = RE_IMG_0_NSPE_OFFSET + RE_VTOR_ALIGNMENT - IMAGE_HEADER_SIZE;
+
+    return 0;
+
+Failed:
+    return result;
+}
+
+/*!
+    \brief      check image header
+    \param[in]  hdr: pointer to image header
+    \param[out] none
+    \retval     check result of image header
+      \arg        0: image header is ok
+      \arg        -1: head magic for boundary check
+      \arg        -2: image type error
+      \arg        -3: hash algorithm error
+      \arg        -5: verson error
+      \arg        -6: checksum error
+      \arg        -7: nv counter for image version not found error
+      \arg        -8: image version too low error
+*/
+int image_header_check(IN struct image_header *hdr)
+{
+    uint32_t ver_nv, ver_img;
+    uint32_t chksum;
+    int ret = 0;
+
+    if (hdr->magic_h != IMG_MAGIC_H) {
+        return -1;
+    }
+    if (hdr->img_type != IMG_TYPE_IMG) {
+        return -2;
+    }
+    if (hdr->algo_hash != IMG_HASH_SHA256) {
+        return -3;
+    }
+    /*if (hdr->algo_sign!= IMG_SIG_ED25519) {
+        return -4;
+    }*/
+
+    if ((hdr->ver_major > MAX_VER_MAJOR) || (hdr->ver_minor > MAX_VER_MINOR)) {
+        return -5;
+    }
+
+    chksum = checksum_cal((uint8_t *)hdr, sizeof(struct image_header));
+    if (chksum != 0) {
+        return -6;
+    }
+
+    ver_img = (hdr->ver_major << 24) | (hdr->ver_minor << 16) | hdr->ver_rev;
+    ret = sys_status_get(SYS_IMG_VER_COUNTER, LEN_SYS_VER_COUNTER, (uint8_t *)&ver_nv);
+    mbl_trace(MBL_INFO, "IMG version: %d.%d.%d, Local: %d.%d.%d\r\n",
+                    hdr->ver_major, hdr->ver_minor, hdr->ver_rev,
+                    ((ver_nv >> 24) & 0xff), ((ver_nv >> 16) & 0xff), (ver_nv & 0xffff));
+    if (ret != 0) {
+        return -7;
+    }
+    if (ver_img < ver_nv) {
+        mbl_trace(MBL_ERR, "The image version too low(0x%08x < 0x%08x).\r\n", ver_img, ver_nv);
+        return -8;
+    }
+
+    return 0;
+}

MBL/source_ns/mbl_image.h

@@ -0,0 +1,107 @@
+/*!
+    \file    mbl_image.h
+    \brief   Non-secure MBL image file for GD32W51x WiFi SDK
+
+    \version 2021-10-30, V1.0.0, firmware for GD32W51x
+*/
+
+/*
+    Copyright (c) 2021, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice,
+       this list of conditions and the following disclaimer in the documentation
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors
+       may be used to endorse or promote products derived from this software without
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#ifndef __MBL_IMAGE_H__
+#define __MBL_IMAGE_H__
+
+#define IN
+#define OUT
+
+/* Image Index */
+#define IMAGE_0                   0
+#define IMAGE_1                   1
+
+/* Image Magic */
+#define IMG_MAGIC_H               0x96f3b83d
+
+/* Image type */
+#define IMG_TYPE_MBL              0x1
+#define IMG_TYPE_IMG              0x8
+
+/* Image Hash Algorithm */
+#define IMG_HASH_SHA256           0x1
+#define IMG_HASH_SHA512           0x2
+
+/* Image status */
+#define IMG_FLAG_NEWER_MASK       0x01
+#define IMG_FLAG_VERIFY_MASK      0x06
+#define IMG_FLAG_IA_MASK          0x18
+
+#define IMG_FLAG_OLDER            0x0
+#define IMG_FLAG_NEWER            0x1         /* The image with higher version will be set to NEWER.
+                                                Default Newer after ISP. Set or Cleared when New image downloaded though OTA.
+                                                Checked when MBL finding the boot image.
+                                                Only one image is set to be NEWER at the same time. */
+
+#define IMG_FLAG_VERIFY_NONE      (0x0 << 1)  /* Default None. Set after MBL verification finished. Checked when MBL finding the boot image. */
+#define IMG_FLAG_VERIFY_OK        (0x1 << 1)
+#define IMG_FLAG_VERIFY_FAIL      (0x2 << 1)
+#define IMG_FLAG_IA_NONE          (0x0 << 3)  /* Default None. Set after IA finished. Checked when MBL finding the boot image. */
+#define IMG_FLAG_IA_OK            (0x1 << 3)
+#define IMG_FLAG_IA_FAIL          (0x2 << 3)
+
+/* Image version */
+#define MAX_VER_MAJOR             254  // 16
+#define MAX_VER_MINOR             254  // 16
+
+/* Image header size */
+#ifdef CONFIG_IMAGE_VERIFICATION
+#define IMAGE_HEADER_SIZE         sizeof(struct image_header)
+#else
+#define IMAGE_HEADER_SIZE         0
+#endif
+
+/** Image header.  All fields are in little endian byte order. Total 32 bytes. */
+struct image_header {
+    uint32_t magic_h;                /* Head Magic for boundary check. */
+    uint32_t tot_sz;                 /* The total size of Image, including header, TLVs and the cert if existed. */
+    uint8_t mani_ver;                /* The version of Image Manifest Format. */
+    uint8_t img_type;                /* Always NSPE. The type of Image (Firmware). */
+    uint8_t algo_hash;               /* The Hash algorithm for Image digest */
+    uint8_t algo_sign;               /* Not used when TZEN is 0. The algorithm used to sign Image manifest. */
+    uint16_t hdr_sz;                 /* Size of Image Header (bytes). */
+    uint16_t ptlv_sz;                /* Size of PTLVs (bytes). */
+    uint32_t img_sz;                 /* Size of Image itself (bytes). */
+    uint8_t ver_major;               /* Major Version. */
+    uint8_t ver_minor;               /* Minor Version. */
+    uint16_t ver_rev;                /* Revision. */
+    uint32_t rsvd;                   /* Reserved. */
+    uint32_t chksum;                 /* Header check sum. */
+};
+
+int boot_image_find(OUT uint32_t *idx, OUT uint32_t *image_offset);
+int image_header_check(IN struct image_header *hdr);
+uint32_t checksum_cal(uint8_t *ptr, uint32_t sz);
+
+#endif  /* __MBL_IMAGE_H__ */

MBL/source_ns/mbl_ns.c

@@ -0,0 +1,182 @@
+/*!
+    \file    mbl_ns.c
+    \brief   Non-secure MBL for GD32W51x WiFi SDK
+
+    \version 2021-10-30, V1.0.0, firmware for GD32W51x
+*/
+
+/*
+    Copyright (c) 2021, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice,
+       this list of conditions and the following disclaimer in the documentation
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors
+       may be used to endorse or promote products derived from this software without
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#include "gd32w51x.h"
+#include "mbl_trace.h"
+#include "mbl_region.h"
+#include "mbl_image.h"
+#include "mbl_sys.h"
+#include "mbl_uart.h"
+#include "mbl_flash.h"
+
+typedef void (*img_fptr_t) (void);
+int32_t mbl_err_process = ERR_PROCESS_ENDLESS_LOOP;
+int32_t mbl_trace_level = MBL_WARN;
+
+#if defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8M_BASE__)
+/* Macros to pick linker symbols */
+#if defined (__ICCARM__)
+#define REGION(a, b) a##b
+#define REGION_NAME(a, b) REGION(a, b)
+#define REGION_DECLARE(a, b) extern uint32_t REGION_NAME(a, b)
+REGION_DECLARE(CSTACK, $$Base);
+#else /* __CC_ARM or __GNUC__ */
+#define REGION(a, b, c) a##b##c
+#define REGION_NAME(a, b, c) REGION(a, b, c)
+#define REGION_DECLARE(a, b, c) extern uint32_t REGION_NAME(a, b, c)
+REGION_DECLARE(Image$$, ARM_LIB_STACKHEAP, $$ZI$$Base);
+#endif /* __ICCARM__ */
+#endif
+
+/*!
+    \brief      jump to main image
+    \param[in]  msp: top of stack pointer for main image
+    \param[in]  reset: Reset Handler for main
+    \param[out] none
+    \retval     none
+*/
+static void jump_to_main_image(uint32_t msp, uint32_t reset)
+{
+    static img_fptr_t img_reset;
+
+    img_reset = (img_fptr_t)reset;
+
+#if defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8M_BASE__)
+    /* Restore the Main Stack Pointer Limit register's reset value
+     * before passing execution to runtime firmware to make the
+     * bootloader transparent to it.
+     */
+    __set_MSPLIM(0);
+#endif
+    __set_MSP(msp);
+
+    __DSB();
+    __ISB();
+
+    img_reset();
+}
+
+/*!
+    \brief      main function
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+int main(void)
+{
+    struct image_header hdr;
+    uint32_t boot_idx = 0, image_offset = 0, version;
+    uint32_t arm_vector[2];
+    int ret;
+#if defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8M_BASE__)
+    uint32_t msp_stack_bottom = 0;
+    #if defined (__ICCARM__)
+        msp_stack_bottom = (uint32_t)&REGION_NAME(CSTACK, $$Base);
+    #else
+        msp_stack_bottom = (uint32_t)&REGION_NAME(Image$$, ARM_LIB_STACKHEAP, $$ZI$$Base);
+    #endif
+    __set_MSPLIM(msp_stack_bottom);
+#endif
+
+    /* Clear SRAM used by rom variables */
+    memset((uint32_t *)SRAM_BASE_NS, 0, RE_MBL_DATA_START);
+
+    /* Initialize UART for trace print */
+    log_uart_init();
+    printf("GIGA DEVICE\r\n");
+
+    /* Initialize flash for reading system info */
+    flash_init();
+
+    /* Initialize system status if empty or validate system status */
+    ret = sys_status_check();
+    if (ret < 0) {
+        mbl_trace(MBL_ERR, "Check sys status failed (ret = %d).\r\n", ret);
+        goto BootFailed;
+    }
+
+    /* Find the correct image to boot, Image 0 or Image 1 */
+    ret = boot_image_find(&boot_idx, &image_offset);
+    if (ret < 0) {
+        mbl_trace(MBL_ERR, "No image to boot (ret = %d).\r\n", ret);
+        goto BootFailed;
+    } else {
+        mbl_trace(MBL_ALWAYS, "MBL: Boot from Image %d.\r\n", boot_idx);
+    }
+
+    /* If boot from Image 1, config offset mapping */
+    if (boot_idx == IMAGE_1) {
+        flash_offset_mapping();
+    }
+
+#ifdef CONFIG_IMAGE_VERIFICATION
+    /* Read and check if image header is valid */
+    flash_read(image_offset, (void *)&hdr, sizeof(struct image_header));
+    ret = image_header_check(&hdr);
+    if (ret < 0) {
+        mbl_trace(MBL_ERR, "Check image header failed (ret = %d).\r\n", ret);
+        sys_img_flag_set(boot_idx, IMG_FLAG_VERIFY_MASK, IMG_FLAG_VERIFY_FAIL);
+        goto BootFailed;
+    }
+#endif
+    /* Update Image status and Running Image flag */
+    ret = sys_img_flag_set(boot_idx, IMG_FLAG_VERIFY_MASK, IMG_FLAG_VERIFY_OK);
+    ret |= sys_running_img_set(boot_idx);
+
+#ifdef CONFIG_IMAGE_VERIFICATION
+    /* Update image version counter */
+    version = (hdr.ver_major << 24) | (hdr.ver_minor << 16) | hdr.ver_rev;
+    ret = sys_fw_version_set(IMG_TYPE_IMG, version);
+    if (ret < 0) {
+        mbl_trace(MBL_ERR, "Update image version counter failed(%d).\r\n", ret);
+        goto BootFailed;
+    } else if (ret == 0){
+        mbl_trace(MBL_ALWAYS, "Current image version is %d.%d.%d.\r\n",
+                            hdr.ver_major, hdr.ver_minor, hdr.ver_rev);
+    }
+#endif
+    /* Read the MSP and Reset_Handler of the main image */
+    flash_read((image_offset + IMAGE_HEADER_SIZE), arm_vector, 8);
+    if (!is_valid_flash_addr(arm_vector[1])) {
+        mbl_trace(MBL_ERR, "Image vector reset is invalid (%08x).\r\n", arm_vector[1]);
+        goto BootFailed;
+    }
+    log_uart_idle_wait();
+
+    /* Jump to main image */
+    jump_to_main_image(arm_vector[0], arm_vector[1]);
+
+BootFailed:
+    while(1);
+}

MBL/source_ns/mbl_qspi_flash.c

@@ -0,0 +1,491 @@
+/*!
+    \file    mbl_qspi_flash.c
+    \brief   Non-secure MBL qspi flash file for GD32W51x WiFi SDK
+
+    \version 2021-10-30, V1.0.0, firmware for GD32W51x
+*/
+
+/*
+    Copyright (c) 2021, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice,
+       this list of conditions and the following disclaimer in the documentation
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors
+       may be used to endorse or promote products derived from this software without
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#include "gd32w51x.h"
+#include "mbl_qspi_flash.h"
+#include "platform_def.h"
+
+/*!
+    \brief      configure qspi flash gpio
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+static void qspi_flash_gpio_config(void)
+{
+    rcu_periph_clock_enable(RCU_GPIOA);
+    rcu_periph_clock_enable(RCU_GPIOB);
+
+    gpio_af_set(GPIOA, GPIO_AF_3, GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7);
+    gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7);
+    gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_25MHZ, GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7);
+
+    gpio_af_set(GPIOB, GPIO_AF_3, GPIO_PIN_3 | GPIO_PIN_4);
+    gpio_mode_set(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_3 | GPIO_PIN_4);
+    gpio_output_options_set(GPIOB, GPIO_OTYPE_PP, GPIO_OSPEED_25MHZ, GPIO_PIN_3 | GPIO_PIN_4);
+}
+
+/*!
+    \brief      enable qspi flash write
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+static void qspi_flash_write_enable(void)
+{
+    qspi_command_struct sCommand;
+    qspi_autopolling_struct sConfig;
+
+    /* Enable write operations ------------------------------------------ */
+    sCommand.instruction_mode   = QSPI_INSTRUCTION_1_LINE;
+    sCommand.instruction        = WRITE_ENABLE_CMD;
+    sCommand.addr_mode          = QSPI_ADDR_NONE;
+    sCommand.addr_size          = QSPI_ADDR_24_BITS;
+    sCommand.addr               = 0;
+    sCommand.altebytes_mode     = QSPI_ALTE_BYTES_NONE;
+    sCommand.altebytes_size     = QSPI_ALTE_BYTES_8_BITS;
+    sCommand.altebytes          = 0;
+    sCommand.dummycycles        = 0;
+    sCommand.data_mode          = QSPI_DATA_NONE;
+    sCommand.data_length        = 0;
+    sCommand.sioo_mode          = QSPI_SIOO_INST_EVERY_CMD;
+
+    qspi_command(&sCommand);
+
+    /* Configure automatic polling mode to wait for write enabling ---- */
+    sConfig.match               = 0x02;
+    sConfig.mask                = 0x02;
+    sConfig.match_mode          = QSPI_MATCH_MODE_AND;
+    sConfig.statusbytes_size    = 1;
+    sConfig.interval            = 0x10;
+    sConfig.auto_stop           = QSPI_AUTO_STOP_ENABLE;
+
+    sCommand.instruction        = READ_STATUS_REG1_CMD;
+    sCommand.data_mode          = QSPI_DATA_1_LINE;
+
+    qspi_autopolling(&sCommand, &sConfig);
+}
+
+/*!
+    \brief      configure automatic polling mode to wait for memory ready
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+static void qspi_flash_autopolling_ready(void)
+{
+    qspi_command_struct sCommand;
+    qspi_autopolling_struct sConfig;
+
+    /* Configure automatic polling mode to wait for memory ready ------ */
+    sCommand.instruction_mode   = QSPI_INSTRUCTION_1_LINE;
+    sCommand.instruction        = READ_STATUS_REG1_CMD;
+    sCommand.addr_mode          = QSPI_ADDR_NONE;
+    sCommand.addr_size          = QSPI_ADDR_24_BITS;
+    sCommand.addr               = 0;
+    sCommand.altebytes_mode     = QSPI_ALTE_BYTES_NONE;
+    sCommand.altebytes_size     = QSPI_ALTE_BYTES_8_BITS;
+    sCommand.altebytes          = 0;
+    sCommand.dummycycles        = 0;
+    sCommand.data_mode          = QSPI_DATA_1_LINE;
+    sCommand.data_length        = 0;
+    sCommand.sioo_mode          = QSPI_SIOO_INST_EVERY_CMD;
+
+    sConfig.match               = 0x00;
+    sConfig.mask                = 0x01;
+    sConfig.match_mode          = QSPI_MATCH_MODE_AND;
+    sConfig.statusbytes_size    = 1;
+    sConfig.interval            = 0x10;
+    sConfig.auto_stop           = QSPI_AUTO_STOP_ENABLE;
+
+    qspi_autopolling(&sCommand, &sConfig);
+}
+
+static void qspi_tcfg_fmc_set(void)
+{
+    qspi_command_struct sCommand;
+
+#if ( QSPI_FLASH_MODE == QSPI_FLASH_4_LINES )
+    sCommand.instruction_mode   = (BITS(8,9) & ((uint32_t)(1) << 8));                            // 1 line
+    sCommand.instruction        = (BITS(0,7) & (uint32_t)(QUAD_IO_FAST_READ_CMD));   // 0xeb
+    sCommand.addr_mode          = (BITS(10,11) & ((uint32_t)(3) << 10));                         // 4 lines
+    sCommand.addr_size          = (BITS(12,13) & ((uint32_t)(2) << 12));                          // 24 bits address
+    sCommand.addr               = 0;
+    sCommand.altebytes_mode     = (BITS(14,15) & ((uint32_t)(3) << 14));                         // 4 lines
+    sCommand.altebytes_size     = 0;                            // 8 bits
+    sCommand.altebytes          = 0;
+    sCommand.dummycycles        = (BITS(18,22) & ((uint32_t)(4) << 18));                           // 4 dummy cycles
+    sCommand.data_mode          = (BITS(24,25) & ((uint32_t)(3) << 24));    // 4 lines
+    sCommand.data_length        = 0;
+    sCommand.sioo_mode          = 0;
+#elif ( QSPI_FLASH_MODE == QSPI_FLASH_2_LINES )
+    sCommand.instruction_mode   = (BITS(8,9) & ((uint32_t)(1) << 8))(0x1);                            // 1 line
+    sCommand.instruction        = (BITS(0,7) & (uint32_t)(DUAL_IO_FAST_READ_CMD));   // 0xBB
+    sCommand.addr_mode          = (BITS(10,11) & ((uint32_t)(2) << 10));                         // 2 lines
+    sCommand.addr_size          = (BITS(12,13) & ((uint32_t)(2) << 12));                          // 24 bits address
+    sCommand.addr               = 0;
+    sCommand.altebytes_mode     = (BITS(14,15) & ((uint32_t)(2) << 14));                         // 2 lines
+    sCommand.altebytes_size     = 0;                            // 8 bits
+    sCommand.altebytes          = 0;
+    /*
+        according to GD25Q16C datasheet, there are 4 alternate bits and 2 dummy cycles for 0xBB cmd,
+        but GD32W51x QSPI mode has alternate bits's limit to 8bits, so set sCommand.altebytes_size
+        to 8, so alternate data[3:0]'s transfer costs 2 cycles on two lines transfer, so set
+        sCommand.dummycycles to 0(which not means there is no dummy cycles)
+    */
+    sCommand.dummycycles        = 0;                             // 0 dummy cycles
+    sCommand.data_mode          = (BITS(24,25) & ((uint32_t)(2) << 24));                         // 2 lines
+    sCommand.data_length        = 0;
+    sCommand.sioo_mode          = 0;
+#elif ( QSPI_FLASH_MODE == QSPI_FLASH_1_LINE )
+    sCommand.instruction_mode   = (BITS(8,9) & ((uint32_t)(1) << 8))(0x1);                            // 1 line
+    sCommand.instruction        = (BITS(0,7) & (uint32_t)(READ_DATA_BYTE_CMD));      // 0x03
+    sCommand.addr_mode          = (BITS(10,11) & ((uint32_t)(1) << 10));                         // 1 line
+    sCommand.addr_size          = (BITS(12,13) & ((uint32_t)(2) << 12));                          // 24 bits address
+    sCommand.addr               = 0;
+    sCommand.altebytes_mode     = 0;                           // no alternate byte
+    sCommand.altebytes_size     = 0;                            // 8 bits
+    sCommand.altebytes          = 0;
+    sCommand.dummycycles        = 0;                             // 0 dummy cycles
+    sCommand.data_mode          = (BITS(24,25) & ((uint32_t)(1) << 24));                         // 1 line
+    sCommand.data_length        = 0;
+    sCommand.sioo_mode          = 0;
+#endif
+
+    while((QSPI_CTL & QSPI_FLAG_BUSY) != 0U){
+    }
+    QSPI_TCFGF = sCommand.instruction_mode | sCommand.instruction | sCommand.addr_mode | \
+           sCommand.addr_size | sCommand.addr | sCommand.altebytes_mode | sCommand.altebytes | \
+           sCommand.dummycycles | sCommand.data_mode | sCommand.data_length | sCommand.sioo_mode;
+}
+
+/*!
+    \brief      configure qspi flash to quad mode
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+static void qspi_flash_quad_enable_set(void)
+{
+    uint32_t id = 0;
+    uint8_t mode_s = 0;
+    uint16_t mode = 0;
+    qspi_command_struct sCommand;
+
+    qspi_flash_read_id(&id);
+
+    qspi_flash_write_enable();
+
+    sCommand.instruction_mode   = QSPI_INSTRUCTION_1_LINE;
+    sCommand.instruction        = 0;
+    sCommand.addr_mode          = QSPI_ADDR_NONE;
+    sCommand.addr_size          = QSPI_ADDR_24_BITS;
+    sCommand.addr               = 0;
+    sCommand.altebytes_mode     = QSPI_ALTE_BYTES_NONE;
+    sCommand.altebytes_size     = QSPI_ALTE_BYTES_8_BITS;
+    sCommand.altebytes          = 0;
+    sCommand.dummycycles        = 0;
+    sCommand.data_mode          = QSPI_DATA_1_LINE;
+    sCommand.data_length        = 1;
+    sCommand.sioo_mode          = QSPI_SIOO_INST_EVERY_CMD;
+
+    sCommand.instruction        = READ_STATUS_REG1_CMD;
+    qspi_command(&sCommand);
+    qspi_receive(&mode_s);
+
+    mode |= (uint16_t)mode_s;
+
+    sCommand.instruction        = READ_STATUS_REG_CMD;
+    qspi_command(&sCommand);
+    qspi_receive(&mode_s);
+
+    mode |= (uint16_t)mode_s << 8;
+
+    if (mode & 0x0200) {
+        /* quad mode, do nothing */
+    } else {
+        switch ((id & 0x00ff0000) >> 16) {
+        case 0x16:                                       //GD32Q32
+        case 0x17:                                       //GD32Q64
+        case 0x18:                                       //GD32Q128
+            mode = mode >> 8;
+            mode |= 0x02;
+            sCommand.instruction = WRITE_STATUS_REG_CMD;//write flash status[s15-s8]
+            qspi_command(&sCommand);
+            qspi_transmit((uint8_t *)&mode);
+            break;
+        case 0x14:                                       //GD32Q80
+        case 0x15:                                       //GD32Q16
+        case 0x19:                                       //GD32Q256
+            /* To fully support GD32Q256, user has to set bit8(ADS) of Status Registers
+                to enable 4-bytes Address Mode, which enabled by cmd 0xB7(the Enter 4-Byte
+                Address Mode command enables accessing the address length of 32-bit for
+                the memory area of higher density (larger than 128Mb), The device default
+                is in 24-bit address mode); and then change all qspi related operations's
+                address size from QSPI_ADDR_24_BITS to QSPI_ADDR_32_BITS. */
+        default:
+            mode |= (0x0200);
+            sCommand.instruction = WRITE_STATUS_REG1_CMD;//write flash status[s15-s0]
+            sCommand.data_length = 2;
+            qspi_command(&sCommand);
+            qspi_transmit((uint8_t *)&mode);
+            break;
+        }
+
+        qspi_flash_autopolling_ready();
+    }
+}
+
+/*!
+    \brief      configure qspi flash
+    \param[in]  clock_prescaler: prescaler of qspi clock
+    \param[out] none
+    \retval     none
+*/
+void qspi_flash_config(uint32_t clock_prescaler)
+{
+    qspi_init_struct Init;
+
+    // rcu_periph_clock_enable(RCU_GTZC);
+    // tzgpc_tzspc_peripheral_attributes_config(TZGPC_PERIPH_QSPI_FLASHREG, TZGPC_TZSPC_PERIPH_SEC);
+
+    qspi_flash_gpio_config();
+
+    // qspi_deinit();
+    rcu_periph_clock_enable(RCU_QSPI);
+
+    Init.prescaler              = clock_prescaler;  /* QSPI clock = AHBCLK/(ClockPrescaler+1) */
+    Init.fifo_threshold         = 4;
+    Init.sample_shift           = QSPI_SAMPLE_SHIFTING_HALFCYCLE;  // QSPI_SAMPLE_SHIFTING_NONE;
+    Init.flash_size             = 23;  /* 2^(FlashSize+1) ***** number of address bits = FlashSize + 1*/
+    Init.cs_high_time           = QSPI_CS_HIGH_TIME_1_CYCLE;
+    Init.clock_mode             = QSPI_CLOCK_MODE_0;
+    qspi_init(&Init);
+
+    qspi_flash_quad_enable_set();
+    qspi_tcfg_fmc_set();
+}
+
+/*!
+    \brief      erase qspi flash sector
+    \param[in]  address: qspi flash address
+    \param[out] none
+    \retval     0
+*/
+int32_t qspi_flash_sector_erase(uint32_t address)
+{
+    qspi_command_struct sCommand;
+
+    qspi_flash_write_enable();
+    sCommand.instruction_mode   = QSPI_INSTRUCTION_1_LINE;
+    sCommand.instruction        = SECTOR_ERASE_CMD;
+    sCommand.addr_mode          = QSPI_ADDR_1_LINE;
+    sCommand.addr_size          = QSPI_ADDR_24_BITS;
+    sCommand.addr               = address;
+    sCommand.altebytes_mode     = QSPI_ALTE_BYTES_NONE;
+    sCommand.altebytes_size     = QSPI_ALTE_BYTES_8_BITS;
+    sCommand.altebytes          = 0;
+    sCommand.dummycycles        = 0;
+    sCommand.data_mode          = QSPI_DATA_NONE;
+    sCommand.data_length        = 0;
+    sCommand.sioo_mode          = QSPI_SIOO_INST_EVERY_CMD;
+    qspi_command(&sCommand);
+    qspi_flash_autopolling_ready();
+
+    return 0;
+}
+
+/*!
+    \brief      erase qspi flash full chip
+    \param[in]  none
+    \param[out] none
+    \retval     0
+*/
+int32_t qspi_flash_chip_erase(void)
+{
+    qspi_command_struct sCommand;
+
+    qspi_flash_write_enable();
+    sCommand.instruction_mode   = QSPI_INSTRUCTION_1_LINE;
+    sCommand.instruction        = CHIP_ERASE_CMD;
+    sCommand.addr_mode          = QSPI_ADDR_NONE;
+    sCommand.addr_size          = QSPI_ADDR_8_BITS;
+    sCommand.addr               = 0;
+    sCommand.altebytes_mode     = QSPI_ALTE_BYTES_NONE;
+    sCommand.altebytes_size     = QSPI_ALTE_BYTES_8_BITS;
+    sCommand.altebytes          = 0;
+    sCommand.dummycycles        = 0;
+    sCommand.data_mode          = QSPI_DATA_NONE;
+    sCommand.data_length        = 0;
+    sCommand.sioo_mode          = QSPI_SIOO_INST_EVERY_CMD;
+    qspi_command(&sCommand);
+    qspi_flash_autopolling_ready();
+
+    return 0;
+}
+
+/*!
+    \brief      read qspi flash device id
+    \param[in]  None
+    \param[out] None
+    \retval     0
+*/
+int32_t qspi_flash_read_id(void *id)
+{
+    qspi_command_struct sCommand = {0};
+
+    sCommand.instruction_mode   = QSPI_INSTRUCTION_1_LINE;
+    sCommand.instruction        = CHIP_READ_ID_CMD;
+    sCommand.dummycycles        = 0;
+    sCommand.data_mode          = QSPI_DATA_1_LINE;
+    sCommand.data_length        = 3;
+    sCommand.sioo_mode          = QSPI_SIOO_INST_EVERY_CMD;
+    qspi_command(&sCommand);
+    qspi_receive(id);
+
+    return 0;
+}
+
+/*!
+    \brief      read qspi flash
+    \param[in]  adress: flash's internal address to read from
+    \param[out] data: pointer to the buffer that receives the data read from the flash
+    \param[in]  size: size of data read from flash
+    \retval     0
+*/
+int32_t qspi_flash_read(uint32_t address, void *data, uint32_t size)
+{
+    qspi_command_struct sCommand;
+
+#if ( QSPI_FLASH_MODE == QSPI_FLASH_4_LINES )
+    sCommand.instruction_mode   = QSPI_INSTRUCTION_1_LINE;
+    sCommand.instruction        = QUAD_IO_FAST_READ_CMD;
+    sCommand.addr_mode          = QSPI_ADDR_4_LINES;
+    sCommand.addr_size          = QSPI_ADDR_24_BITS;
+    sCommand.addr               = address;
+    sCommand.altebytes_mode     = QSPI_ALTE_BYTES_4_LINES;
+    sCommand.altebytes_size     = QSPI_ALTE_BYTES_8_BITS;
+    sCommand.altebytes          = 0;
+    sCommand.dummycycles        = 4;
+    sCommand.data_mode          = QSPI_DATA_4_LINES;
+    sCommand.data_length        = size;
+    sCommand.sioo_mode          = QSPI_SIOO_INST_EVERY_CMD;
+#elif ( QSPI_FLASH_MODE == QSPI_FLASH_2_LINES )
+    sCommand.instruction_mode   = QSPI_INSTRUCTION_1_LINE;
+    sCommand.instruction        = DUAL_IO_FAST_READ_CMD;
+    sCommand.addr_mode          = QSPI_ADDR_2_LINES;
+    sCommand.addr_size          = QSPI_ADDR_24_BITS;
+    sCommand.addr               = address;
+    sCommand.altebytes_mode     = QSPI_ALTE_BYTES_2_LINES;
+    sCommand.altebytes_size     = QSPI_ALTE_BYTES_8_BITS;
+    sCommand.altebytes          = 0;
+    /*
+        according to GD25Q16C datasheet, there are 4 alternate bits and 2 dummy cycles for 0xBB cmd,
+        but GD32W51x QSPI mode has alternate bits's limit to 8bits, so set sCommand.altebytes_size
+        to 8, so alternate data[3:0]'s transfer costs 2 cycles on two lines transfer, so set
+        sCommand.dummycycles to 0(which not means there is no dummy cycles)
+    */
+    sCommand.dummycycles        = 0;
+    sCommand.data_mode          = QSPI_DATA_2_LINES;
+    sCommand.data_length        = size;
+    sCommand.sioo_mode          = QSPI_SIOO_INST_EVERY_CMD;
+#elif ( QSPI_FLASH_MODE == QSPI_FLASH_1_LINE )
+    sCommand.instruction_mode   = QSPI_INSTRUCTION_1_LINE;
+    sCommand.instruction        = READ_DATA_BYTE_CMD;
+    sCommand.addr_mode          = QSPI_ADDR_1_LINE;
+    sCommand.addr_size          = QSPI_ADDR_24_BITS;
+    sCommand.addr               = address;
+    sCommand.altebytes_mode     = QSPI_ALTE_BYTES_NONE;
+    sCommand.altebytes_size     = QSPI_ALTE_BYTES_8_BITS;
+    sCommand.altebytes          = 0;
+    sCommand.dummycycles        = 0;
+    sCommand.data_mode          = QSPI_DATA_1_LINE;
+    sCommand.data_length        = size;
+    sCommand.sioo_mode          = QSPI_SIOO_INST_EVERY_CMD;
+#endif
+
+    qspi_command(&sCommand);
+    qspi_receive(data);
+
+    return 0;
+}
+
+/*!
+    \brief      program qspi flash page
+    \param[in]  adress: flash's internal address to write to
+    \param[in]  data: pointer to the buffer that receives the data read from the flash
+    \param[in]  size: size of data read from flash
+    \param[out] none
+    \retval     0
+*/
+int32_t qspi_flash_page_program(uint32_t address, const uint8_t *data, uint32_t size)
+{
+    qspi_command_struct sCommand;
+
+    /* Writing Sequence 4 Line------------------------------------------ */
+    qspi_flash_write_enable();
+
+#if ( QSPI_FLASH_MODE == QSPI_FLASH_4_LINES )
+    sCommand.instruction_mode   = QSPI_INSTRUCTION_1_LINE;
+    sCommand.instruction        = QUAD_IN_FAST_PROG_CMD;
+    sCommand.addr_mode          = QSPI_ADDR_1_LINE;
+    sCommand.addr_size          = QSPI_ADDR_24_BITS;
+    sCommand.addr               = address;
+    sCommand.altebytes_mode     = QSPI_ALTE_BYTES_NONE;
+    sCommand.altebytes_size     = QSPI_ALTE_BYTES_8_BITS;
+    sCommand.altebytes          = 0;
+    sCommand.dummycycles        = 0;
+    sCommand.data_mode          = QSPI_DATA_4_LINES;
+    sCommand.data_length        = size;
+    sCommand.sioo_mode          = QSPI_SIOO_INST_EVERY_CMD;
+#elif ( QSPI_FLASH_MODE == QSPI_FLASH_2_LINES ) || ( QSPI_FLASH_MODE == QSPI_FLASH_1_LINE )
+    sCommand.instruction_mode   = QSPI_INSTRUCTION_1_LINE;
+    sCommand.instruction        = PAGE_PROG_CMD;
+    sCommand.addr_mode          = QSPI_ADDR_1_LINE;
+    sCommand.addr_size          = QSPI_ADDR_24_BITS;
+    sCommand.addr               = address;
+    sCommand.altebytes_mode     = QSPI_ALTE_BYTES_NONE;
+    sCommand.altebytes_size     = QSPI_ALTE_BYTES_8_BITS;
+    sCommand.altebytes          = 0;
+    sCommand.dummycycles        = 0;
+    sCommand.data_mode          = QSPI_DATA_1_LINE;
+    sCommand.data_length        = size;
+    sCommand.sioo_mode          = QSPI_SIOO_INST_EVERY_CMD;
+#endif
+    qspi_command(&sCommand);
+    qspi_transmit((uint8_t *)data);
+    qspi_flash_autopolling_ready();
+
+    return 0;
+}

MBL/source_ns/mbl_qspi_flash.h

@@ -0,0 +1,70 @@
+/*!
+    \file    mbl_qspi_flash.h
+    \brief   Non-secure MBL qspi flash file for GD32W51x WiFi SDK
+
+    \version 2021-10-30, V1.0.0, firmware for GD32W51x
+*/
+
+/*
+    Copyright (c) 2021, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice,
+       this list of conditions and the following disclaimer in the documentation
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors
+       may be used to endorse or promote products derived from this software without
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#ifndef __MBL_QSPI_FLASH_H__
+#define __MBL_QSPI_FLASH_H__
+
+#define FLASH_SIZE_QSPI             (0x2000000 - FLASH_OB_SIZE)
+#define FLASH_QSPI_PAGE_SIZE        (0x100)
+#define FLASH_QSPI_SECTOR_SIZE      (0x1000)
+
+#define FLASH_OB_SIZE               (0)
+#define FLASH_START_QSPI            FLASH_OB_SIZE
+
+/* QSPI FLASH COMMANDs */
+#define WRITE_ENABLE_CMD            0x06
+#define WRITE_DISABLE_CMD           0x04
+#define READ_DATA_BYTE_CMD          0x03
+#define READ_STATUS_REG1_CMD        0x05
+#define WRITE_STATUS_REG1_CMD       0x01
+#define READ_STATUS_REG_CMD         0x35
+#define WRITE_STATUS_REG_CMD        0x31
+#define DUAL_IO_FAST_READ_CMD       0xBB
+#define PAGE_PROG_CMD               0x02
+#define QUAD_IN_FAST_PROG_CMD       0x32
+#define QUAD_OUT_FAST_READ_CMD      0x6B
+#define QUAD_IO_FAST_READ_CMD       0xEB
+#define SECTOR_ERASE_CMD            0x20    // 0xD8
+#define HIGH_PERFORMANCE_CMD        0xA3
+#define CHIP_ERASE_CMD              0xC7
+#define CHIP_READ_ID_CMD            0x9F
+
+/* QSPI FLASH APIs */
+void qspi_flash_config(uint32_t clock_prescaler);
+int32_t qspi_flash_sector_erase(uint32_t address);
+int32_t qspi_flash_read_id(void *id);
+int32_t qspi_flash_read(uint32_t address, void *data, uint32_t size);
+int32_t qspi_flash_page_program(uint32_t address, const uint8_t *data, uint32_t size);
+
+#endif  /* __MBL_QSPI_FLASH_H__ */

MBL/source_ns/mbl_sys.h

@@ -0,0 +1,145 @@
+/*!
+    \file    mbl_sys.h
+    \brief   Non-secure MBL system file for GD32W51x WiFi SDK
+
+    \version 2021-10-30, V1.0.0, firmware for GD32W51x
+*/
+
+/*
+    Copyright (c) 2021, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice,
+       this list of conditions and the following disclaimer in the documentation
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors
+       may be used to endorse or promote products derived from this software without
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#ifndef __MBL_SYS_H__
+#define __MBL_SYS_H__
+
+#include "mbl_region.h"
+
+/* ============================================================= */
+#define FLASH_OFFSET_SYS_STATUS_PING     (RE_SYS_STATUS_OFFSET)
+#define FLASH_OFFSET_SYS_STATUS_PONG     (FLASH_OFFSET_SYS_STATUS_PING + SYS_STATUS_AREA_SZ)
+#define FLASH_OFFSET_IMG_VERSION_LOCK    (FLASH_OFFSET_SYS_STATUS_PING - 4)
+#define SYS_STATUS_SALT                  "sys_gigadevice"
+
+/* System status related size */
+#define SYS_STATUS_AREA_SZ            0x1000
+#define SYS_STATUS_HEADER_SZ          (sizeof(struct sys_status_header_t))
+#define SYS_STATUS_TLV_HEADER_SZ      2
+#define MAX_TLV_VALUE_SIZE            16
+#define SYS_STATUS_MAGIC_CODE         0x19342750
+#define AES_KEY_SZ                    16
+#define AES_BLOCK_SZ                  AES_KEY_SZ
+
+/* System status error definitions */
+#define SYS_STATUS_OK                0
+#define SYS_STATUS_ERR_FLASH         1
+#define SYS_STATUS_ERR_KEY           (1 << 1)
+#define SYS_STATUS_ERR_TOTAL_LEN     (1 << 2)
+#define SYS_STATUS_ERR_MAGIC         (1 << 3)
+#define SYS_STATUS_ERR_CHECKSUM      (1 << 4)
+#define SYS_STATUS_ERR_TLV           (1 << 5)
+#define SYS_STATUS_ERR_CRYPT         (1 << 6)
+#define SYS_STATUS_ERR_MEM           (1 << 7)
+#define SYS_STATUS_ERR_INPUT         (1 << 8)
+
+/* System status item length */
+#define LEN_SYS_ERROR_PROCESS        1
+#define LEN_SYS_TRACE_LEVEL          1
+#define LEN_SYS_IMAGE_STATUS         1
+#define LEN_SYS_RUNNING_IMG          1
+#define LEN_SYS_VER_COUNTER          4
+#define LEN_SYS_TRNG_SEED            1
+
+#define LEN_SYS_AUTO_CONN            1
+#define LEN_SYS_SSID_X               16
+#define LEN_SYS_PASSWD_X             16
+#define LEN_SYS_IP_ADDR              4
+
+/* ERROR process  */
+#define ERR_PROCESS_REDOWNLOD        0
+#define ERR_PROCESS_ENDLESS_LOOP     1
+
+/* SYS status found result */
+#define SYS_STATUS_FOUND_OK          0
+#define SYS_STATUS_NOT_FOUND         -1
+#define SYS_STATUS_FOUND_ERR         -2
+
+/* There are two flash blocks used to manage system status: Ping, Pong.
+    The format of system status is shown as below.
+    | total size   |  valid count  | Magic   | Checksum |
+    | type | len | value|
+    valid count - used to indicate which is active, Ping or Pong. A higher valid count represents the active system status.
+    total size - the total size of the following TLVs
+ */
+enum {
+    SYS_ERROR_PROCESS = 1,          /* 0: Redownload; 1: while(1) */
+    SYS_TRACE_LEVEL = 2,            /* The Trace Level for IBL and MBL */
+    SYS_IMAGE0_STATUS = 3,          /* the status of Main Image 0, enum image_status */
+    SYS_IMAGE1_STATUS = 4,          /* the status of Main Image 1, enum image_status */
+    SYS_RUNNING_IMG = 5,            /* 0: Image0, 1: Image1 */
+    SYS_MBL_VER_COUNTER = 6,        /* NV counter for MBL version */
+    SYS_IMG_VER_COUNTER = 7,        /* NV counter for Image version */
+    SYS_MBLPK_VER_COUNTER = 8,      /* NV counter for MBL Public Key version */
+    SYS_AROTPK_VER_COUNTER = 9,     /* NV counter for AROT Public Key version */
+    SYS_TRNG_SEED = 10,             /* 1: Rand use TRNG seed, 0: software seed */
+
+    /* Defined by Application */
+    SYS_AUTO_CONN,
+    SYS_SSID_1,
+    SYS_SSID_2,
+    SYS_PASSWD_1,
+    SYS_PASSWD_2,
+    SYS_PASSWD_3,
+    SYS_PASSWD_4,
+    SYS_IP_ADDR,
+    SYS_UNKNOWN_TYPE = 0xFF
+};
+
+struct sys_status_header_t {
+    uint32_t tot_len;
+    uint32_t act_cntr;
+    uint32_t magic;
+    uint32_t checksum;
+};
+
+extern int32_t mbl_err_process;
+extern int32_t mbl_trace_level;
+
+/* ============================================================= */
+int sys_status_init(void);
+int sys_statu_integritys_check(void);
+int sys_status_set(uint8_t type, uint8_t len, uint8_t* pval);
+int sys_status_get(uint8_t type, uint8_t len, uint8_t* pval);
+int sys_err_process_set(uint8_t method);
+int sys_trace_level_set(uint8_t trace_level);
+int sys_img_flag_set(uint8_t idx, uint8_t mask, uint8_t flag);
+int sys_running_img_set(uint8_t idx);
+int sys_fw_version_set(uint32_t type, uint32_t version);
+int sys_trng_seed_set(uint8_t val);
+void sys_status_show(void);
+void sys_status_dump(int is_ping);
+int sys_status_check(void);
+
+#endif //__MBL_SYS_H__

MBL/source_ns/mbl_trace.h

@@ -0,0 +1,87 @@
+/*!
+    \file    mbl_trace.h
+    \brief   Non-secure MBL trace file for GD32W51x WiFi SDK
+
+    \version 2021-10-30, V1.0.0, firmware for GD32W51x
+*/
+
+/*
+    Copyright (c) 2021, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice,
+       this list of conditions and the following disclaimer in the documentation
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors
+       may be used to endorse or promote products derived from this software without
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#ifndef __MBL_TRACE_H__
+#define __MBL_TRACE_H__
+
+#include "stdint.h"
+#include "stddef.h"
+#include "stdio.h"
+#include "stdlib.h"
+#include "string.h"
+
+/* Define Trace Level */
+#define MBL_ALWAYS        1
+#define MBL_ERR           2
+#define MBL_WARN          3
+#define MBL_INFO          4
+#define MBL_DBG           5
+
+extern int32_t mbl_trace_level;
+
+#define MBL_ASSERT(expr)             \
+    if ((expr) == 0) {               \
+        printf("ASSERT: "#expr);     \
+        for( ;; );                   \
+    }
+
+#define mbl_trace(level, fmt, arg...) do {  \
+    if (level <= mbl_trace_level) {         \
+        if (level == MBL_ERR) {             \
+            printf("ERR: "fmt, ##arg);      \
+        } else if (level == MBL_WARN) {     \
+            printf("WARN: "fmt, ##arg);     \
+        } else if (level == MBL_INFO) {     \
+            printf("INFO: "fmt, ##arg);     \
+        } else if (level == MBL_DBG) {      \
+            printf("DBG: "fmt, ##arg);      \
+        } else {                            \
+            printf(fmt, ##arg);             \
+        }                                   \
+    }                                       \
+} while(0);
+
+#define mbl_print_data(title, data, count) do {\
+    int i;                                     \
+    printf("\r\n----------------------\r\n");  \
+    printf("%s\r\n\t", title);                 \
+    for (i = 0; i < count; i++) {              \
+        if ((i > 0) && (i % 16 == 0))          \
+            printf("\r\n\t");                  \
+        printf("%02x ", *(data + i));          \
+    }                                          \
+    printf("\r\n");                            \
+} while(0);
+
+#endif  // __MBL_TRACE_H__

MBL/source_ns/mbl_uart.c

@@ -0,0 +1,149 @@
+/*!
+    \file    mbl_uart.c
+    \brief   Non-secure MBL uart file for GD32W51x WiFi SDK
+
+    \version 2021-10-30, V1.0.0, firmware for GD32W51x
+*/
+
+/*
+    Copyright (c) 2021, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice,
+       this list of conditions and the following disclaimer in the documentation
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors
+       may be used to endorse or promote products derived from this software without
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#include "platform_def.h"
+#include "gd32w51x.h"
+#include "mbl_trace.h"
+
+
+/*!
+    \brief      send byte to usart
+    \param[in]  c: data to transmission
+    \param[out] none
+    \retval     none
+*/
+void uart_putc(uint8_t c)
+{
+    while (RESET == usart_flag_get(LOG_UART, USART_FLAG_TBE));
+    usart_data_transmit(LOG_UART, (uint8_t)c);
+}
+
+#if defined(__ARMCC_VERSION)
+FILE __stdout;
+
+/* __ARMCC_VERSION is only defined starting from Arm compiler version 6 */
+int fputc(int ch, FILE *f)
+{
+    /* Send byte to USART */
+    uart_putc(ch);
+
+    /* Return character written */
+    return ch;
+}
+#elif defined(__ICCARM__)
+int putchar(int ch)
+{
+    /* Send byte to USART */
+    uart_putc(ch);
+
+    /* Return character written */
+    return ch;
+}
+#elif defined(__GNUC__)
+int _write(int fd, char *str, int len)
+{
+    (void)fd;
+    uint32_t i = 0;
+
+    /* Send string and return the number of characters written */
+    for (i = 0; i < len; i ++) {
+        uart_putc(*str++);
+    }
+    return len;
+}
+#endif
+
+/*!
+    \brief      configure usart
+    \param[in]  usart_periph: USARTx(x=0,1,2)
+    \param[out] none
+    \retval     none
+*/
+void uart_config(uint32_t usart_periph)
+{
+    if (usart_periph == USART1) {
+        rcu_periph_clock_enable(RCU_USART1);
+        rcu_periph_clock_enable(RCU_GPIOB);
+        rcu_periph_clock_enable(RCU_GPIOA);
+
+        gpio_af_set(GPIOB, GPIO_AF_7, GPIO_PIN_15);
+        gpio_af_set(GPIOA, GPIO_AF_3, GPIO_PIN_8);
+        gpio_mode_set(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_15);
+        gpio_output_options_set(GPIOB, GPIO_OTYPE_PP, GPIO_OSPEED_25MHZ, GPIO_PIN_15);
+        gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_8);
+        gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_25MHZ, GPIO_PIN_8);
+    } else if (usart_periph == USART2) {
+        rcu_periph_clock_enable(RCU_USART2);
+        rcu_periph_clock_enable(RCU_GPIOB);
+
+        gpio_af_set(GPIOB, GPIO_AF_7, GPIO_PIN_10);
+        gpio_af_set(GPIOB, GPIO_AF_7, GPIO_PIN_11);
+        gpio_mode_set(GPIOB, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO_PIN_10);
+        gpio_output_options_set(GPIOB, GPIO_OTYPE_PP, GPIO_OSPEED_25MHZ, GPIO_PIN_10);
+        gpio_mode_set(GPIOB, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO_PIN_11);
+        gpio_output_options_set(GPIOB, GPIO_OTYPE_PP, GPIO_OSPEED_25MHZ, GPIO_PIN_11);
+    } else {
+        return;
+    }
+
+    usart_deinit(usart_periph);
+    usart_baudrate_set(usart_periph, 115200U);
+    //usart_receive_config(usart_periph, USART_RECEIVE_ENABLE);
+    usart_transmit_config(usart_periph, USART_TRANSMIT_ENABLE);
+    usart_enable(usart_periph);
+
+    //usart_interrupt_enable(usart_periph, USART_INT_RBNE);
+}
+
+/*!
+    \brief      initialize log usart
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void log_uart_init(void)
+{
+    uart_config(LOG_UART);
+}
+
+/*!
+    \brief      wait log usart transmit complete
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void log_uart_idle_wait(void)
+{
+    while (RESET == usart_flag_get(LOG_UART, USART_FLAG_TC));
+}

MBL/source_ns/mbl_uart.h

@@ -0,0 +1,41 @@
+/*!
+    \file    mbl_uart.h
+    \brief   Non-secure MBL uart file for GD32W51x WiFi SDK
+
+    \version 2021-10-30, V1.0.0, firmware for GD32W51x
+*/
+
+/*
+    Copyright (c) 2021, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice,
+       this list of conditions and the following disclaimer in the documentation
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors
+       may be used to endorse or promote products derived from this software without
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#ifndef __MBL_UART_H__
+#define __MBL_UART_H__
+
+void log_uart_init(void);
+void log_uart_idle_wait(void);
+
+#endif  // __MBL_UART_H__

MultiProject.eww

@@ -0,0 +1,13 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<workspace>
+    <project>
+        <path>$WS_DIR$\MBL\project\IAR\Project_MBL.ewp</path>  
+    </project>
+    <project>
+        <path>$WS_DIR$\PROT\project\IAR\Project_PROT.ewp</path>  
+    </project>
+    <project>
+        <path>$WS_DIR$\NSPE\Project\WIFI_IOT\IAR\Project_NSPE.ewp</path>  
+    </project>
+    <batchBuild />
+</workspace>

MultiProject.uvmpw

@@ -0,0 +1,19 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectWorkspace xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_mpw.xsd">
+    <SchemaVersion>1.0</SchemaVersion>
+    <Header>### uVision Project, (C) Keil Software</Header>
+    <WorkspaceName>WorkSpace</WorkspaceName>
+    <project>
+        <PathAndName>.\MBL\project\KEIL\Project_MBL.uvprojx</PathAndName>
+        <NodeIsActive>1</NodeIsActive>
+        <NodeIsExpanded>1</NodeIsExpanded>
+    </project>
+    <project>
+        <PathAndName>.\PROT\project\KEIL\secure_main\Project_PROT.uvprojx</PathAndName>
+        <NodeIsExpanded>1</NodeIsExpanded>
+    </project>
+    <project>
+        <PathAndName>.\NSPE\Project\WIFI_IOT\KEIL\Project_NSPE.uvprojx</PathAndName>
+        <NodeIsExpanded>1</NodeIsExpanded>
+    </project>
+</ProjectWorkspace>

MultiProject_NS.eww

@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<workspace>
+    <project>
+        <path>$WS_DIR$\MBL\project\IAR\Project_MBL_NS.ewp</path>  
+    </project>
+    <project>
+        <path>$WS_DIR$\NSPE\Project\WIFI_IOT\IAR\Project_WIFI_IOT.ewp</path>  
+    </project>
+    <batchBuild />
+</workspace>

MultiProject_NS.uvmpw

@@ -0,0 +1,15 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectWorkspace xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_mpw.xsd">
+    <SchemaVersion>1.0</SchemaVersion>
+    <Header>### uVision Project, (C) Keil Software</Header>
+    <WorkspaceName>WorkSpace</WorkspaceName>
+    <project>
+        <PathAndName>.\MBL\project\KEIL\Project_MBL_NS.uvprojx</PathAndName>
+        <NodeIsActive>1</NodeIsActive>
+        <NodeIsExpanded>1</NodeIsExpanded>
+    </project>
+    <project>
+        <PathAndName>.\NSPE\Project\WIFI_IOT\KEIL\Project_WIFI_IOT.uvprojx</PathAndName>
+        <NodeIsExpanded>1</NodeIsExpanded>
+    </project>
+</ProjectWorkspace>

NSPE/CMakeLists.txt

@@ -0,0 +1,63 @@
+cmake_minimum_required(VERSION 3.15)
+set(TARGET_EXE nspe)
+set(TAGET_PROJECT_DIR ${PROJECT_SOURCE_DIR}/NSPE/Project/WIFI_IOT)
+
+add_executable(${TARGET_EXE})
+
+add_subdirectory(Firmware/GD32W51x_standard_peripheral)
+add_subdirectory(Firmware/GD32W51x_wifi_driver)
+add_subdirectory(Firmware/CMSIS)
+add_subdirectory(WIFI_IOT)
+
+set_target_properties(${TARGET_EXE}
+    PROPERTIES
+        SUFFIX ".axf"
+        ARCHIVE_OUTPUT_DIRECTORY "${TAGET_PROJECT_DIR}/GCC/output/lib"
+        LIBRARY_OUTPUT_DIRECTORY "${TAGET_PROJECT_DIR}/GCC/output/lib"
+        RUNTIME_OUTPUT_DIRECTORY "${TAGET_PROJECT_DIR}/GCC/output/bin"
+    )
+
+
+target_add_scatter_file(${TARGET_EXE}
+    ${TAGET_PROJECT_DIR}/GCC/nspe_gdm32_ns.ld
+    )
+
+
+if (CONFIG_STATIC_LIB_BUILDED)
+
+    add_library(gd32w51x_wifi STATIC IMPORTED GLOBAL)
+
+    set_target_properties(gd32w51x_wifi
+        PROPERTIES IMPORTED_LOCATION
+        ${PROJECT_SOURCE_DIR}/NSPE/WIFI_IOT/lib/GCC/libgd32w51x_wifi.a)
+endif()
+
+target_link_libraries(${TARGET_EXE}
+    PRIVATE
+        gd32w51x_wifi
+    )
+
+target_link_libraries(${TARGET_EXE}
+    PRIVATE
+        app
+        gd32w51x_peripheral
+        bsp
+        common
+        lwIP
+        mbedtls_ssl
+        wifi
+        os
+        cmsis
+    )
+
+target_link_options(${TARGET_EXE}
+    PUBLIC
+    -Wl,--just-symbols=${PROJECT_SOURCE_DIR}/ROM-EXPORT/symbol/rom_symbol.gcc
+    -Wl,-Map=${TAGET_PROJECT_DIR}/GCC/output/bin/${TARGET_EXE}.map
+    -Wl,--cref
+)
+
+add_custom_command(TARGET ${TARGET_EXE} POST_BUILD
+    COMMAND ${TAGET_PROJECT_DIR}/nspe_afterbuild.bat ${TAGET_PROJECT_DIR}/GCC/output/bin GCC \"\"
+    COMMENT "Building ${TARGET_EXE}"
+)

NSPE/Example/ADC/Analog_watchdog/gd32w51x_it.c

@@ -0,0 +1,160 @@
+/*!
+    \file    gd32w51x_it.c
+    \brief   interrupt service routines
+
+    \version 2021-10-30, V1.0.0, firmware for GD32W51x
+*/
+
+/*
+    Copyright (c) 2021, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#include "gd32w51x_it.h"
+#include "systick.h"
+#include "gd32w515p_eval.h"
+
+extern uint8_t data;
+
+/*!
+    \brief      this function handles NMI exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void NMI_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles HardFault exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void HardFault_Handler(void)
+{
+    /* if Hard Fault exception occurs, go to infinite loop */
+    while (1){
+    }
+}
+
+/*!
+    \brief      this function handles MemManage exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void MemManage_Handler(void)
+{
+    /* if Memory Manage exception occurs, go to infinite loop */
+    while (1){
+    }
+}
+
+/*!
+    \brief      this function handles BusFault exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void BusFault_Handler(void)
+{
+    /* if Bus Fault exception occurs, go to infinite loop */
+    while (1){
+    }
+}
+
+/*!
+    \brief      this function handles UsageFault exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void UsageFault_Handler(void)
+{
+    /* if Usage Fault exception occurs, go to infinite loop */
+    while (1){
+    }
+}
+
+/*!
+    \brief      this function handles SVC exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void SVC_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles DebugMon exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void DebugMon_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles PendSV exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void PendSV_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles SysTick exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void SysTick_Handler(void)
+{
+    delay_decrement();
+}
+
+/*!
+    \brief      this function handles ADC exception 
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void ADC_IRQHandler(void)
+{
+    if(SET == adc_interrupt_flag_get(ADC_INT_FLAG_WDE)){
+        /* clear the ADC interrupt or status flag */
+        adc_interrupt_flag_clear(ADC_INT_FLAG_WDE);
+
+        /* turn on LED2 */
+        gd_eval_led_on(LED2);
+        data = 1U;
+    }
+}

NSPE/Example/ADC/Analog_watchdog/gd32w51x_it.h

@@ -0,0 +1,62 @@
+/*!
+    \file    gd32w51x_it.h
+    \brief   the header file of the ISR
+
+    \version 2021-10-30, V1.0.0, firmware for GD32W51x
+*/
+
+/*
+    Copyright (c) 2021, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32W51X_IT_H
+#define GD32W51X_IT_H
+
+#include "gd32w51x.h"
+
+/* function declarations */
+/* this function handles NMI exception */
+void NMI_Handler(void);
+/* this function handles HardFault exception */
+void HardFault_Handler(void);
+/* this function handles MemManage exception */
+void MemManage_Handler(void);
+/* this function handles BusFault exception */
+void BusFault_Handler(void);
+/* this function handles UsageFault exception */
+void UsageFault_Handler(void);
+/* this function handles SVC exception */
+void SVC_Handler(void);
+/* this function handles DebugMon exception */
+void DebugMon_Handler(void);
+/* this function handles PendSV exception */
+void PendSV_Handler(void);
+/* this function handles SysTick exception */
+void SysTick_Handler(void);
+/* this function handles ADC exception */
+void ADC_IRQHandler(void);
+
+#endif /* GD32W51X_IT_H */

NSPE/Example/ADC/Analog_watchdog/gd32w51x_libopt.h

@@ -0,0 +1,70 @@
+/*!
+    \file    gd32w51x_libopt.h
+    \brief   library optional for gd32w51x
+
+    \version 2021-10-30, V1.0.0, firmware for GD32W51x
+*/
+
+/*
+    Copyright (c) 2021, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32W51X_LIBOPT_H
+#define GD32W51X_LIBOPT_H
+
+#include "gd32w51x_adc.h"
+#include "gd32w51x_cau.h"
+#include "gd32w51x_crc.h"
+#include "gd32w51x_dbg.h"
+#include "gd32w51x_dci.h"
+#include "gd32w51x_dma.h"
+#include "gd32w51x_efuse.h"
+#include "gd32w51x_exti.h"
+#include "gd32w51x_fmc.h"
+#include "gd32w51x_fwdgt.h"
+#include "gd32w51x_gpio.h"
+#include "gd32w51x_hau.h"
+#include "gd32w51x_hpdf.h"
+#include "gd32w51x_i2c.h"
+#include "gd32w51x_icache.h"
+#include "gd32w51x_misc.h"
+#include "gd32w51x_pkcau.h"
+#include "gd32w51x_pmu.h"
+#include "gd32w51x_qspi.h"
+#include "gd32w51x_rcu.h"
+#include "gd32w51x_rtc.h"
+#include "gd32w51x_sdio.h"
+#include "gd32w51x_spi.h"
+#include "gd32w51x_sqpi.h"
+#include "gd32w51x_syscfg.h"
+#include "gd32w51x_timer.h"
+#include "gd32w51x_trng.h"
+#include "gd32w51x_tsi.h"
+#include "gd32w51x_tzpcu.h"
+#include "gd32w51x_usart.h"
+#include "gd32w51x_wwdgt.h"
+
+#endif /* GD32W51X_LIBOPT_H */

NSPE/Example/ADC/Analog_watchdog/main.c

@@ -0,0 +1,178 @@
+/*!
+    \file    main.c
+    \brief   ADC analog watchdog demo
+
+    \version 2021-10-30, V1.0.0, firmware for GD32W51x
+*/
+
+/*
+    Copyright (c) 2021, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#include "gd32w51x.h"
+#include "systick.h"
+#include <stdio.h>
+#include "gd32w515p_eval.h"
+
+#define BOARD_ADC_CHANNEL              ADC_CHANNEL_0
+#define ADC_GPIO_PORT                  GPIOA
+#define ADC_GPIO_PIN                   GPIO_PIN_0
+
+#define ADC_WATCHDOG_HT                0x0A00U
+#define ADC_WATCHDOG_LT                0x0400U
+
+uint8_t data;
+uint16_t adc_value;
+
+void rcu_config(void);
+void gpio_config(void);
+void nvic_config(void);
+void adc_config(void);
+
+/*!
+    \brief      main function
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+
+int main(void)
+{
+    /* system clocks configuration */
+    rcu_config();
+    /* systick configuration */
+    systick_config();
+    /* GPIO configuration */
+    gpio_config();
+   /* configure COM port */
+    gd_eval_com_init(EVAL_COM0);
+    /* NVIC configuration */
+    nvic_config();
+    /* ADC configuration */
+    adc_config();
+
+    while(1){
+        delay_1ms(1000);
+        /* ADC software trigger enable */
+        adc_software_trigger_enable(ADC_REGULAR_CHANNEL);
+        while(SET != adc_flag_get(ADC_FLAG_EOC)){
+        }
+        adc_flag_clear(ADC_FLAG_EOC);
+        adc_value = adc_regular_data_read();
+        
+        printf("\r\n //*********************************//");
+        printf("\r\n ADC watchdog low threshold: 0x%04X", ADC_WATCHDOG_LT);
+        printf("\r\n ADC watchdog hgih threshold: 0x%04X", ADC_WATCHDOG_HT);
+        printf("\r\n ADC regular channel data = 0x%04X \r\n", adc_value);
+
+        if(1U == data){
+            /* turn off LED2 */
+            if((adc_value < ADC_WATCHDOG_HT) && (adc_value > ADC_WATCHDOG_LT)){
+                data = 0;
+                gd_eval_led_off(LED2);
+            }
+        }
+    }
+}
+
+/*!
+    \brief      configure the different system clocks
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void rcu_config(void)
+{
+    /* enable GPIOC clock */
+    rcu_periph_clock_enable(RCU_GPIOA);
+    /* enable ADC clock */
+    rcu_periph_clock_enable(RCU_ADC);
+    /* config ADC clock */
+    adc_clock_config(ADC_ADCCK_HCLK_DIV5);
+}
+
+/*!
+    \brief      configure the GPIO peripheral
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void gpio_config(void)
+{
+    /* configure led GPIO */
+    gd_eval_led_init(LED2);
+    /* config the GPIO as analog mode */
+    gpio_mode_set(ADC_GPIO_PORT, GPIO_MODE_ANALOG, GPIO_PUPD_NONE, ADC_GPIO_PIN);
+}
+
+/*!
+    \brief      configure interrupt priority
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void nvic_config(void)
+{
+    nvic_priority_group_set(NVIC_PRIGROUP_PRE2_SUB2);
+    nvic_irq_enable(ADC_IRQn, 0U, 0U);
+}
+
+/*!
+    \brief      configure the ADC peripheral
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void adc_config(void)
+{
+    /* ADC data alignment config */
+    adc_data_alignment_config(ADC_DATAALIGN_RIGHT);
+    /* ADC channel length config */
+    adc_channel_length_config(ADC_REGULAR_CHANNEL, 1U);
+ 
+    /* ADC regular channel config */
+    adc_regular_channel_config(0U, BOARD_ADC_CHANNEL, ADC_SAMPLETIME_55POINT5);
+    adc_external_trigger_config(ADC_REGULAR_CHANNEL, EXTERNAL_TRIGGER_DISABLE);
+    
+    /* enable ADC interface */
+    adc_enable();
+    delay_1ms(1U);
+
+    /* ADC analog watchdog threshold config */
+    adc_watchdog_threshold_config(ADC_WATCHDOG_LT, ADC_WATCHDOG_HT);
+    /* ADC analog watchdog single channel config */
+    adc_watchdog_single_channel_enable(BOARD_ADC_CHANNEL);
+    /* ADC interrupt config */
+    adc_interrupt_enable(ADC_INT_WDE);
+}
+
+/* retarget the C library printf function to the USART */
+int fputc(int ch, FILE *f)
+{
+    usart_data_transmit(EVAL_COM0, (uint8_t)ch);
+    while(RESET == usart_flag_get(EVAL_COM0, USART_FLAG_TBE));
+    return ch;
+}

NSPE/Example/ADC/Analog_watchdog/readme.txt

@@ -0,0 +1,45 @@
+/*!
+    \file    readme.txt
+    \brief   description of the ADC analog watchdog demo
+
+    \version 2021-10-30, V1.0.0, firmware for GD32W51x
+*/
+
+/*
+    Copyright (c) 2021, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+  This demo is based on the GD32W515P-EVAL-V1.0 board, it shows how to use the ADC analog 
+watchdog to guard continuously an ADC channel. The ADC is configured in continuous mode, 
+PA0 is chosen as analog input pin.
+
+  Change the VR1 on the GD32W515P-EVAL-V1.0 board, when the channel0 converted value is 
+over the programmed analog watchdog high threshold (value 0x0A00) or below the analog 
+watchdog low threshold(value 0x0400), an WDE interrupt will occur, and LED2 will turn on.
+When the channel0 converted value is in safe range(among 0x0400 and 0x0A00), the LED2 
+will be off.
+
+  The analog input pin should be configured to AIN mode.

NSPE/Example/ADC/Analog_watchdog/systick.c

@@ -0,0 +1,82 @@
+/*!
+    \file    systick.c
+    \brief   the systick configuration file
+
+    \version 2021-10-30, V1.0.0, firmware for GD32W51x
+*/
+
+/*
+    Copyright (c) 2021, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#include "gd32w51x.h"
+#include "systick.h"
+
+volatile static uint32_t delay;
+
+/*!
+    \brief      configure systick
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void systick_config(void)
+{
+    /* setup systick timer for 1000Hz interrupts */
+    if(SysTick_Config(SystemCoreClock / 1000U)){
+        /* capture error */
+        while(1){
+        }
+    }
+    /* configure the systick handler priority */
+    NVIC_SetPriority(SysTick_IRQn, 0x00U);
+}
+
+/*!
+    \brief      delay a time in milliseconds
+    \param[in]  count: count in milliseconds
+    \param[out] none
+    \retval     none
+*/
+void delay_1ms(uint32_t count)
+{
+    delay = count;
+    while(0U != delay){
+    }
+}
+
+/*!
+    \brief      delay decrement
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void delay_decrement(void)
+{
+    if(0U != delay){
+        delay--;
+    }
+}

NSPE/Example/ADC/Analog_watchdog/systick.h

@@ -0,0 +1,47 @@
+/*!
+    \file    systick.h
+    \brief   the header file of systick
+
+    \version 2021-10-30, V1.0.0, firmware for GD32W51x
+*/
+
+/*
+    Copyright (c) 2021, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef SYSTICK_H
+#define SYSTICK_H
+
+#include <stdint.h>
+
+/* configure systick */
+void systick_config(void);
+/* delay a time in milliseconds */
+void delay_1ms(uint32_t count);
+/* delay decrement */
+void delay_decrement(void);
+
+#endif /* SYSTICK_H */

NSPE/Example/ADC/EXTI_trigger_regular_inserted_channel/gd32w51x_it.c

@@ -0,0 +1,159 @@
+/*!
+    \file    gd32w51x_it.c
+    \brief   interrupt service routines
+
+    \version 2021-10-30, V1.0.0, firmware for GD32W51x
+*/
+
+/*
+    Copyright (c) 2021, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#include "gd32w51x_it.h"
+#include "systick.h"
+#include "gd32w515p_eval.h"
+
+extern uint16_t inserted_data[4];
+
+/*!
+    \brief      this function handles NMI exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void NMI_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles HardFault exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void HardFault_Handler(void)
+{
+    /* if Hard Fault exception occurs, go to infinite loop */
+    while (1){
+    }
+}
+
+/*!
+    \brief      this function handles MemManage exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void MemManage_Handler(void)
+{
+    /* if Memory Manage exception occurs, go to infinite loop */
+    while (1){
+    }
+}
+
+/*!
+    \brief      this function handles BusFault exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void BusFault_Handler(void)
+{
+    /* if Bus Fault exception occurs, go to infinite loop */
+    while (1){
+    }
+}
+
+/*!
+    \brief      this function handles UsageFault exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void UsageFault_Handler(void)
+{
+    /* if Usage Fault exception occurs, go to infinite loop */
+    while (1){
+    }
+}
+
+/*!
+    \brief      this function handles SVC exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void SVC_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles DebugMon exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void DebugMon_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles PendSV exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void PendSV_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles SysTick exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void SysTick_Handler(void)
+{
+    delay_decrement();
+}
+
+/*!
+    \brief      this function handles ADC interrupt
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void ADC_IRQHandler(void)
+{
+    /* clear the ADC flag */
+    adc_interrupt_flag_clear(ADC_INT_FLAG_EOIC);
+    /* read ADC inserted group data register */
+    inserted_data[0] = adc_inserted_data_read(ADC_INSERTED_CHANNEL_0);
+    inserted_data[1] = adc_inserted_data_read(ADC_INSERTED_CHANNEL_1);
+    inserted_data[2] = adc_inserted_data_read(ADC_INSERTED_CHANNEL_2);
+    inserted_data[3] = adc_inserted_data_read(ADC_INSERTED_CHANNEL_3);
+}

NSPE/Example/ADC/EXTI_trigger_regular_inserted_channel/gd32w51x_it.h

@@ -0,0 +1,62 @@
+/*!
+    \file    gd32w51x_it.h
+    \brief   the header file of the ISR
+
+    \version 2021-10-30, V1.0.0, firmware for GD32W51x
+*/
+
+/*
+    Copyright (c) 2021, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32W51X_IT_H
+#define GD32W51X_IT_H
+
+#include "gd32w51x.h"
+
+/* function declarations */
+/* this function handles NMI exception */
+void NMI_Handler(void);
+/* this function handles HardFault exception */
+void HardFault_Handler(void);
+/* this function handles MemManage exception */
+void MemManage_Handler(void);
+/* this function handles BusFault exception */
+void BusFault_Handler(void);
+/* this function handles UsageFault exception */
+void UsageFault_Handler(void);
+/* this function handles SVC exception */
+void SVC_Handler(void);
+/* this function handles DebugMon exception */
+void DebugMon_Handler(void);
+/* this function handles PendSV exception */
+void PendSV_Handler(void);
+/* this function handles SysTick exception */
+void SysTick_Handler(void);
+/* this function handles ADC exception */
+void ADC_IRQHandler(void);
+
+#endif /* GD32W51X_IT_H */

NSPE/Example/ADC/EXTI_trigger_regular_inserted_channel/gd32w51x_libopt.h

@@ -0,0 +1,70 @@
+/*!
+    \file    gd32w51x_libopt.h
+    \brief   library optional for gd32w51x
+
+    \version 2021-10-30, V1.0.0, firmware for GD32W51x
+*/
+
+/*
+    Copyright (c) 2021, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32W51X_LIBOPT_H
+#define GD32W51X_LIBOPT_H
+
+#include "gd32w51x_adc.h"
+#include "gd32w51x_cau.h"
+#include "gd32w51x_crc.h"
+#include "gd32w51x_dbg.h"
+#include "gd32w51x_dci.h"
+#include "gd32w51x_dma.h"
+#include "gd32w51x_efuse.h"
+#include "gd32w51x_exti.h"
+#include "gd32w51x_fmc.h"
+#include "gd32w51x_fwdgt.h"
+#include "gd32w51x_gpio.h"
+#include "gd32w51x_hau.h"
+#include "gd32w51x_hpdf.h"
+#include "gd32w51x_i2c.h"
+#include "gd32w51x_icache.h"
+#include "gd32w51x_misc.h"
+#include "gd32w51x_pkcau.h"
+#include "gd32w51x_pmu.h"
+#include "gd32w51x_qspi.h"
+#include "gd32w51x_rcu.h"
+#include "gd32w51x_rtc.h"
+#include "gd32w51x_sdio.h"
+#include "gd32w51x_spi.h"
+#include "gd32w51x_sqpi.h"
+#include "gd32w51x_syscfg.h"
+#include "gd32w51x_timer.h"
+#include "gd32w51x_trng.h"
+#include "gd32w51x_tsi.h"
+#include "gd32w51x_tzpcu.h"
+#include "gd32w51x_usart.h"
+#include "gd32w51x_wwdgt.h"
+
+#endif /* GD32W51X_LIBOPT_H */

NSPE/Example/ADC/EXTI_trigger_regular_inserted_channel/main.c

@@ -0,0 +1,244 @@
+/*!
+    \file    main.c
+    \brief   EXTI trigger ADC regular and inserted channel demo
+
+    \version 2021-10-30, V1.0.0, firmware for GD32W51x
+*/
+
+/*
+    Copyright (c) 2021, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#include "gd32w51x.h"
+#include "systick.h"
+#include <stdio.h>
+#include "gd32w515p_eval.h"
+
+uint16_t adc_value[4];
+uint16_t inserted_data[4];
+
+void rcu_config(void);
+void gpio_config(void);
+void nvic_config(void);
+void dma_config(void);
+void adc_config(void);
+void exti_config(void);
+
+/*!
+    \brief      main function
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+int main(void)
+{
+    /* system clocks configuration */
+    rcu_config();
+    /* GPIO configuration */
+    gpio_config();
+    /* configure the EXTI peripheral */
+    exti_config();
+    /* systick configuration */
+    systick_config();
+    /* NVIC configuration */
+    nvic_config();
+    /* configure COM port */
+    gd_eval_com_init(EVAL_COM0);
+    /* DMA configuration */
+    dma_config();
+    /* ADC configuration */
+    adc_config();
+    
+    while(1){
+        delay_1ms(1000);
+        printf("\r\n ADC regular channel 0 data = %d \r\n", adc_value[0]);
+        printf(" ADC regular channel 1 data = %d \r\n", adc_value[1]);
+        printf(" ADC regular channel 2 data = %d \r\n", adc_value[2]);
+        printf(" ADC regular channel 3 data = %d \r\n", adc_value[3]);
+        printf("\r\n ADC inserted channel 0 data = %d \r\n", inserted_data[0]);
+        printf(" ADC inserted channel 1 data = %d \r\n", inserted_data[1]);
+        printf(" ADC inserted channel 2 data = %d \r\n", inserted_data[2]);
+        printf(" ADC inserted channel 3 data = %d \r\n", inserted_data[3]);
+        printf(" ***********************************\r\n");
+    }
+}
+
+/*!
+    \brief      configure the different system clocks
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void rcu_config(void)
+{
+    /* enable GPIOA clock */
+    rcu_periph_clock_enable(RCU_GPIOA);
+    /* enable DMA clock */
+    rcu_periph_clock_enable(RCU_DMA1);
+    /* config ADC clock */
+    rcu_periph_clock_enable(RCU_ADC);
+    adc_clock_config(ADC_ADCCK_HCLK_DIV6);
+}
+
+/*!
+    \brief      configure the GPIO peripheral
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void gpio_config(void)
+{
+    /* config the GPIO as analog mode, for ADC */
+    gpio_mode_set(GPIOA, GPIO_MODE_ANALOG, GPIO_PUPD_NONE,GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3);
+    gpio_mode_set(GPIOA, GPIO_MODE_ANALOG, GPIO_PUPD_NONE,GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7);
+    /* config the GPIO as floating input mode, for EXTI */
+    gpio_mode_set(GPIOA, GPIO_MODE_INPUT, GPIO_PUPD_NONE, GPIO_PIN_11|GPIO_PIN_15);
+}
+
+/**
+    \brief      configure the nested vectored interrupt controller
+    \param[in]  none
+    \param[out] none
+    \retval     none
+  */
+void nvic_config(void)
+{
+    nvic_priority_group_set(NVIC_PRIGROUP_PRE1_SUB3);
+    nvic_irq_enable(ADC_IRQn, 1, 1);
+}
+
+/*!
+    \brief      configure the DMA peripheral
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void dma_config(void)
+{
+    /* ADC_DMA_channel configuration */
+    dma_single_data_parameter_struct dma_single_data_parameter;
+    
+    /* ADC DMA_channel configuration */
+    dma_deinit(DMA1, DMA_CH0);
+    
+    /* initialize DMA single data mode */
+    dma_single_data_parameter.periph_addr         = (uint32_t)(&ADC_RDATA);
+    dma_single_data_parameter.periph_inc          = DMA_PERIPH_INCREASE_DISABLE;
+    dma_single_data_parameter.memory0_addr        = (uint32_t)(&adc_value);
+    dma_single_data_parameter.memory_inc          = DMA_MEMORY_INCREASE_ENABLE;
+    dma_single_data_parameter.periph_memory_width = DMA_PERIPH_WIDTH_16BIT;
+    dma_single_data_parameter.direction           = DMA_PERIPH_TO_MEMORY;
+    dma_single_data_parameter.number              = 4;
+    dma_single_data_parameter.priority            = DMA_PRIORITY_HIGH;
+    dma_single_data_mode_init(DMA1, DMA_CH0, &dma_single_data_parameter);
+    dma_channel_subperipheral_select(DMA1, DMA_CH0, DMA_SUBPERI0);
+
+    /* enable DMA circulation mode */
+    dma_circulation_enable(DMA1, DMA_CH0);
+    /* enable DMA channel */
+    dma_channel_enable(DMA1, DMA_CH0);
+}
+
+/*!
+    \brief      configure the ADC peripheral
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void adc_config(void)
+{
+    /* ADC scan function enable */
+    adc_special_function_config(ADC_SCAN_MODE, ENABLE);
+    /* ADC data alignment config */
+    adc_data_alignment_config(ADC_DATAALIGN_RIGHT);
+
+    /* ADC inserted channel length config */
+    adc_channel_length_config(ADC_INSERTED_CHANNEL, 4U);
+    /* ADC inserted channel config */
+    adc_inserted_channel_config(0, ADC_CHANNEL_0, ADC_SAMPLETIME_14POINT5);
+    adc_inserted_channel_config(1, ADC_CHANNEL_1, ADC_SAMPLETIME_14POINT5);
+    adc_inserted_channel_config(2, ADC_CHANNEL_2, ADC_SAMPLETIME_14POINT5);
+    adc_inserted_channel_config(3, ADC_CHANNEL_3, ADC_SAMPLETIME_14POINT5);
+    /* ADC inserted channel trigger config */
+    adc_external_trigger_source_config(ADC_INSERTED_CHANNEL, ADC_EXTTRIG_INSERTED_EXTI_15);
+    /* ADC inserted channel external trigger enable */
+    adc_external_trigger_config(ADC_INSERTED_CHANNEL, EXTERNAL_TRIGGER_RISING);
+    /* clear the ADC flag */
+    adc_interrupt_flag_clear(ADC_INT_FLAG_EOC);
+    adc_interrupt_flag_clear(ADC_INT_FLAG_EOIC);
+    /* enable ADC interrupt */
+    adc_interrupt_enable(ADC_INT_EOIC);
+    
+    /* ADC regular channel length config */
+    adc_channel_length_config(ADC_REGULAR_CHANNEL, 4U);
+    /* ADC regular channel config */
+    adc_regular_channel_config(0, ADC_CHANNEL_4, ADC_SAMPLETIME_14POINT5);
+    adc_regular_channel_config(1, ADC_CHANNEL_5, ADC_SAMPLETIME_14POINT5);
+    adc_regular_channel_config(2, ADC_CHANNEL_6, ADC_SAMPLETIME_14POINT5);
+    adc_regular_channel_config(3, ADC_CHANNEL_7, ADC_SAMPLETIME_14POINT5);
+    /* ADC regular channel trigger config */
+    adc_external_trigger_source_config(ADC_REGULAR_CHANNEL, ADC_EXTTRIG_REGULAR_EXTI_11);
+    adc_external_trigger_config(ADC_REGULAR_CHANNEL, EXTERNAL_TRIGGER_RISING);
+    /* ADC regular channel discontinuous mode */
+    adc_discontinuous_mode_config(ADC_REGULAR_CHANNEL, 1);
+    /* ADC DMA function enable */
+    adc_dma_request_after_last_enable();
+    adc_dma_mode_enable();
+
+    /* enable ADC interface */
+    adc_enable();
+    /* wait for ADC stability */
+    delay_1ms(1);
+}
+
+/*!
+    \brief      configure the EXTI peripheral
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void exti_config(void)
+{
+    /* connect EXTI line to GPIO pin for inserted group */
+    syscfg_exti_line_config(EXTI_SOURCE_GPIOA, EXTI_SOURCE_PIN15);
+    /* configure EXTI line for inserted group */
+    exti_init(EXTI_15, EXTI_EVENT, EXTI_TRIG_RISING);
+    exti_flag_clear(EXTI_15);
+    
+    /* connect EXTI line to GPIO pin for inserted group */
+    syscfg_exti_line_config(EXTI_SOURCE_GPIOA, EXTI_SOURCE_PIN11);
+    /* configure EXTI line for inserted group */
+    exti_init(EXTI_11, EXTI_EVENT, EXTI_TRIG_RISING);
+    exti_flag_clear(EXTI_11);
+}
+
+/* retarget the C library printf function to the USART */
+int fputc(int ch, FILE *f)
+{
+    usart_data_transmit(EVAL_COM0, (uint8_t)ch);
+    while(RESET == usart_flag_get(EVAL_COM0, USART_FLAG_TBE));
+    return ch;
+}

NSPE/Example/ADC/EXTI_trigger_regular_inserted_channel/readme.txt

@@ -0,0 +1,48 @@
+/*!
+    \file    readme.txt
+    \brief   description of the EXTI trigger ADC regular and inserted channel demo
+
+    \version 2021-10-30, V1.0.0, firmware for GD32W51x
+*/
+
+/*
+    Copyright (c) 2021, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+  This demo is based on the GD32W515P-EVAL-V1.0 board, it shows how to convert ADC 
+regular and inserted group channels using EXTI external triggers.
+
+  The inserted group length is 4, the scan mode is set, every rising edge event of 
+EXTI15 (PA15) will trigger ADC to convert all the channels in the inserted group. When
+all inserted group channels are converted, EOIC Interrupt will be generated. The 
+inserted datas are print by USART.
+
+  The regular group is configured in discontinuous mode, group length is 4, conversion 
+length is 1, Every rising edge event of EXTI11 (PA11) converts 1 channel and DMA can be
+used to transfer the converted data.
+
+  We can watch array adc_value[]/inserted_data[] in debug mode or by COM0.
+  Connect PA11/PA15 to key Tamper(PA2).

NSPE/Example/ADC/EXTI_trigger_regular_inserted_channel/systick.c

@@ -0,0 +1,82 @@
+/*!
+    \file    systick.c
+    \brief   the systick configuration file
+
+    \version 2021-10-30, V1.0.0, firmware for GD32W51x
+*/
+
+/*
+    Copyright (c) 2021, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#include "gd32w51x.h"
+#include "systick.h"
+
+volatile static uint32_t delay;
+
+/*!
+    \brief      configure systick
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void systick_config(void)
+{
+    /* setup systick timer for 1000Hz interrupts */
+    if(SysTick_Config(SystemCoreClock / 1000U)){
+        /* capture error */
+        while(1){
+        }
+    }
+    /* configure the systick handler priority */
+    NVIC_SetPriority(SysTick_IRQn, 0x00U);
+}
+
+/*!
+    \brief      delay a time in milliseconds
+    \param[in]  count: count in milliseconds
+    \param[out] none
+    \retval     none
+*/
+void delay_1ms(uint32_t count)
+{
+    delay = count;
+    while(0U != delay){
+    }
+}
+
+/*!
+    \brief      delay decrement
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void delay_decrement(void)
+{
+    if(0U != delay){
+        delay--;
+    }
+}

NSPE/Example/ADC/EXTI_trigger_regular_inserted_channel/systick.h

@@ -0,0 +1,47 @@
+/*!
+    \file    systick.h
+    \brief   the header file of systick
+
+    \version 2021-10-30, V1.0.0, firmware for GD32W51x
+*/
+
+/*
+    Copyright (c) 2021, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef SYSTICK_H
+#define SYSTICK_H
+
+#include <stdint.h>
+
+/* configure systick */
+void systick_config(void);
+/* delay a time in milliseconds */
+void delay_1ms(uint32_t count);
+/* delay decrement */
+void delay_decrement(void);
+
+#endif /* SYSTICK_H */

NSPE/Example/ADC/Oversample_shift/gd32w51x_it.c

@@ -0,0 +1,140 @@
+/*!
+    \file    gd32w51x_it.c
+    \brief   interrupt service routines
+
+    \version 2021-10-30, V1.0.0, firmware for GD32W51x
+*/
+
+/*
+    Copyright (c) 2021, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#include "gd32w51x_it.h"
+#include "systick.h"
+#include "gd32w515p_eval.h"
+
+/*!
+    \brief      this function handles NMI exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void NMI_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles HardFault exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void HardFault_Handler(void)
+{
+    /* if Hard Fault exception occurs, go to infinite loop */
+    while (1){
+    }
+}
+
+/*!
+    \brief      this function handles MemManage exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void MemManage_Handler(void)
+{
+    /* if Memory Manage exception occurs, go to infinite loop */
+    while (1){
+    }
+}
+
+/*!
+    \brief      this function handles BusFault exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void BusFault_Handler(void)
+{
+    /* if Bus Fault exception occurs, go to infinite loop */
+    while (1){
+    }
+}
+
+/*!
+    \brief      this function handles UsageFault exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void UsageFault_Handler(void)
+{
+    /* if Usage Fault exception occurs, go to infinite loop */
+    while (1){
+    }
+}
+
+/*!
+    \brief      this function handles SVC exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void SVC_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles DebugMon exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void DebugMon_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles PendSV exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void PendSV_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles SysTick exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void SysTick_Handler(void)
+{
+    delay_decrement();
+}

NSPE/Example/ADC/Oversample_shift/gd32w51x_it.h

@@ -0,0 +1,60 @@
+/*!
+    \file    gd32w51x_it.h
+    \brief   the header file of the ISR
+
+    \version 2021-10-30, V1.0.0, firmware for GD32W51x
+*/
+
+/*
+    Copyright (c) 2021, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32W51X_IT_H
+#define GD32W51X_IT_H
+
+#include "gd32w51x.h"
+
+/* function declarations */
+/* this function handles NMI exception */
+void NMI_Handler(void);
+/* this function handles HardFault exception */
+void HardFault_Handler(void);
+/* this function handles MemManage exception */
+void MemManage_Handler(void);
+/* this function handles BusFault exception */
+void BusFault_Handler(void);
+/* this function handles UsageFault exception */
+void UsageFault_Handler(void);
+/* this function handles SVC exception */
+void SVC_Handler(void);
+/* this function handles DebugMon exception */
+void DebugMon_Handler(void);
+/* this function handles PendSV exception */
+void PendSV_Handler(void);
+/* this function handles SysTick exception */
+void SysTick_Handler(void);
+
+#endif /* GD32W51X_IT_H */

NSPE/Example/ADC/Oversample_shift/gd32w51x_libopt.h

@@ -0,0 +1,70 @@
+/*!
+    \file    gd32w51x_libopt.h
+    \brief   library optional for gd32w51x
+
+    \version 2021-10-30, V1.0.0, firmware for GD32W51x
+*/
+
+/*
+    Copyright (c) 2021, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32W51X_LIBOPT_H
+#define GD32W51X_LIBOPT_H
+
+#include "gd32w51x_adc.h"
+#include "gd32w51x_cau.h"
+#include "gd32w51x_crc.h"
+#include "gd32w51x_dbg.h"
+#include "gd32w51x_dci.h"
+#include "gd32w51x_dma.h"
+#include "gd32w51x_efuse.h"
+#include "gd32w51x_exti.h"
+#include "gd32w51x_fmc.h"
+#include "gd32w51x_fwdgt.h"
+#include "gd32w51x_gpio.h"
+#include "gd32w51x_hau.h"
+#include "gd32w51x_hpdf.h"
+#include "gd32w51x_i2c.h"
+#include "gd32w51x_icache.h"
+#include "gd32w51x_misc.h"
+#include "gd32w51x_pkcau.h"
+#include "gd32w51x_pmu.h"
+#include "gd32w51x_qspi.h"
+#include "gd32w51x_rcu.h"
+#include "gd32w51x_rtc.h"
+#include "gd32w51x_sdio.h"
+#include "gd32w51x_spi.h"
+#include "gd32w51x_sqpi.h"
+#include "gd32w51x_syscfg.h"
+#include "gd32w51x_timer.h"
+#include "gd32w51x_trng.h"
+#include "gd32w51x_tsi.h"
+#include "gd32w51x_tzpcu.h"
+#include "gd32w51x_usart.h"
+#include "gd32w51x_wwdgt.h"
+
+#endif /* GD32W51X_LIBOPT_H */

NSPE/Example/ADC/Oversample_shift/main.c

@@ -0,0 +1,146 @@
+/*!
+    \file    main.c
+    \brief   ADC oversample shift example demo
+
+    \version 2021-10-30, V1.0.0, firmware for GD32W51x
+*/
+
+/*
+    Copyright (c) 2021, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#include "gd32w51x.h"
+#include "systick.h"
+#include <stdio.h>
+#include "gd32w515p_eval.h"
+
+#define BOARD_ADC_CHANNEL               ADC_CHANNEL_0
+#define ADC_GPIO_PORT                   GPIOA
+#define ADC_GPIO_PIN                    GPIO_PIN_0
+
+uint16_t adc_value = 0U;
+
+void rcu_config(void);
+void gpio_config(void);
+void adc_config(void);
+
+/*!
+    \brief      main function
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+int main(void)
+{
+    /* system clocks configuration */
+    rcu_config();
+    /* systick configuration */
+    systick_config();  
+    /* GPIO configuration */
+    gpio_config();
+    /* ADC configuration */
+    adc_config();
+    /* configures COM port */
+    gd_eval_com_init(EVAL_COM0);
+    
+    /* enable ADC software trigger for regular channel */
+    adc_software_trigger_enable(ADC_REGULAR_CHANNEL);
+
+    while(1){
+        adc_flag_clear(ADC_FLAG_EOC);
+        while(SET != adc_flag_get(ADC_FLAG_EOC)){
+        }
+        
+        adc_value = ADC_RDATA;
+        printf("\r\n*ADC oversample shift example demo*\r\n");
+        printf("16 times sample, 4 bits shift: 0x%X\r\n", adc_value);
+        delay_1ms(1000U);
+    }
+}
+
+/*!
+    \brief      configure the different system clocks
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void rcu_config(void)
+{
+    /* enable GPIOC clock */
+    rcu_periph_clock_enable(RCU_GPIOA);
+    /* config ADC clock */
+    rcu_periph_clock_enable(RCU_ADC);
+    adc_clock_config(ADC_ADCCK_HCLK_DIV6);
+}
+
+/*!
+    \brief      configure the GPIO peripheral
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void gpio_config(void)
+{
+    /* config the GPIO as analog mode */
+    gpio_mode_set(ADC_GPIO_PORT, GPIO_MODE_ANALOG, GPIO_PUPD_NONE, ADC_GPIO_PIN);
+}
+
+/*!
+    \brief      configure the ADC peripheral
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void adc_config(void)
+{
+    /* ADC contineous function disable */
+    adc_special_function_config(ADC_CONTINUOUS_MODE, ENABLE);
+    /* ADC data alignment config */
+    adc_data_alignment_config(ADC_DATAALIGN_RIGHT);
+    /* ADC external trigger enable */
+    adc_external_trigger_config(ADC_REGULAR_CHANNEL, EXTERNAL_TRIGGER_DISABLE);
+
+    /* ADC channel length config */
+    adc_channel_length_config(ADC_REGULAR_CHANNEL, 1U);
+    /* ADC inserted channel config */
+    adc_regular_channel_config(0U, BOARD_ADC_CHANNEL, ADC_SAMPLETIME_55POINT5);
+
+    /* 16 times sample, 4 bits shift */
+    adc_oversample_mode_config(ADC_OVERSAMPLING_ALL_CONVERT, ADC_OVERSAMPLING_SHIFT_4B, ADC_OVERSAMPLING_RATIO_MUL16);
+    adc_oversample_mode_enable();
+    /* enable ADC interface */
+    adc_enable();
+    /* wait for ADC stability */
+    delay_1ms(1);
+}
+
+/* retarget the C library printf function to the USART */
+int fputc(int ch, FILE *f)
+{
+    usart_data_transmit(EVAL_COM0, (uint8_t)ch);
+    while(RESET == usart_flag_get(EVAL_COM0, USART_FLAG_TBE));
+    return ch;
+}

NSPE/Example/ADC/Oversample_shift/readme.txt

@@ -0,0 +1,40 @@
+/*!
+    \file    readme.txt
+    \brief   description of the ADC oversample shift example demo
+
+    \version 2021-10-30, V1.0.0, firmware for GD32W51x
+*/
+
+/*
+    Copyright (c) 2021, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+  This demo is based on the GD32W515P-EVAL-V1.0 board, it shows how to use the function 
+of oversample and shift. In this demo, 16 times ratio of oversample and 4 bits shift are 
+configured. PA0 (channel0) is chosen as analog input pin. The ADC conversion begins by 
+software, the converted data is printed by USART.
+
+  The analog input pin should configured to analog mode.

NSPE/Example/ADC/Oversample_shift/systick.c

@@ -0,0 +1,82 @@
+/*!
+    \file    systick.c
+    \brief   the systick configuration file
+
+    \version 2021-10-30, V1.0.0, firmware for GD32W51x
+*/
+
+/*
+    Copyright (c) 2021, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#include "gd32w51x.h"
+#include "systick.h"
+
+volatile static uint32_t delay;
+
+/*!
+    \brief      configure systick
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void systick_config(void)
+{
+    /* setup systick timer for 1000Hz interrupts */
+    if(SysTick_Config(SystemCoreClock / 1000U)){
+        /* capture error */
+        while(1){
+        }
+    }
+    /* configure the systick handler priority */
+    NVIC_SetPriority(SysTick_IRQn, 0x00U);
+}
+
+/*!
+    \brief      delay a time in milliseconds
+    \param[in]  count: count in milliseconds
+    \param[out] none
+    \retval     none
+*/
+void delay_1ms(uint32_t count)
+{
+    delay = count;
+    while(0U != delay){
+    }
+}
+
+/*!
+    \brief      delay decrement
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void delay_decrement(void)
+{
+    if(0U != delay){
+        delay--;
+    }
+}

NSPE/Example/ADC/Oversample_shift/systick.h

@@ -0,0 +1,47 @@
+/*!
+    \file    systick.h
+    \brief   the header file of systick
+
+    \version 2021-10-30, V1.0.0, firmware for GD32W51x
+*/
+
+/*
+    Copyright (c) 2021, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef SYSTICK_H
+#define SYSTICK_H
+
+#include <stdint.h>
+
+/* configure systick */
+void systick_config(void);
+/* delay a time in milliseconds */
+void delay_1ms(uint32_t count);
+/* delay decrement */
+void delay_decrement(void);
+
+#endif /* SYSTICK_H */

NSPE/Example/ADC/Regular_channel_discontinuous_mode/gd32w51x_it.c

@@ -0,0 +1,140 @@
+/*!
+    \file    gd32w51x_it.c
+    \brief   interrupt service routines
+
+    \version 2021-10-30, V1.0.0, firmware for GD32W51x
+*/
+
+/*
+    Copyright (c) 2021, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#include "gd32w51x_it.h"
+#include "systick.h"
+#include "gd32w515p_eval.h"
+
+/*!
+    \brief      this function handles NMI exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void NMI_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles HardFault exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void HardFault_Handler(void)
+{
+    /* if Hard Fault exception occurs, go to infinite loop */
+    while (1){
+    }
+}
+
+/*!
+    \brief      this function handles MemManage exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void MemManage_Handler(void)
+{
+    /* if Memory Manage exception occurs, go to infinite loop */
+    while (1){
+    }
+}
+
+/*!
+    \brief      this function handles BusFault exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void BusFault_Handler(void)
+{
+    /* if Bus Fault exception occurs, go to infinite loop */
+    while (1){
+    }
+}
+
+/*!
+    \brief      this function handles UsageFault exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void UsageFault_Handler(void)
+{
+    /* if Usage Fault exception occurs, go to infinite loop */
+    while (1){
+    }
+}
+
+/*!
+    \brief      this function handles SVC exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void SVC_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles DebugMon exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void DebugMon_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles PendSV exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void PendSV_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles SysTick exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void SysTick_Handler(void)
+{
+    delay_decrement();
+}

NSPE/Example/ADC/Regular_channel_discontinuous_mode/gd32w51x_it.h

@@ -0,0 +1,60 @@
+/*!
+    \file    gd32w51x_it.h
+    \brief   the header file of the ISR
+
+    \version 2021-10-30, V1.0.0, firmware for GD32W51x
+*/
+
+/*
+    Copyright (c) 2021, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32W51X_IT_H
+#define GD32W51X_IT_H
+
+#include "gd32w51x.h"
+
+/* function declarations */
+/* this function handles NMI exception */
+void NMI_Handler(void);
+/* this function handles HardFault exception */
+void HardFault_Handler(void);
+/* this function handles MemManage exception */
+void MemManage_Handler(void);
+/* this function handles BusFault exception */
+void BusFault_Handler(void);
+/* this function handles UsageFault exception */
+void UsageFault_Handler(void);
+/* this function handles SVC exception */
+void SVC_Handler(void);
+/* this function handles DebugMon exception */
+void DebugMon_Handler(void);
+/* this function handles PendSV exception */
+void PendSV_Handler(void);
+/* this function handles SysTick exception */
+void SysTick_Handler(void);
+
+#endif /* GD32W51X_IT_H */

NSPE/Example/ADC/Regular_channel_discontinuous_mode/gd32w51x_libopt.h

@@ -0,0 +1,70 @@
+/*!
+    \file    gd32w51x_libopt.h
+    \brief   library optional for gd32w51x
+
+    \version 2021-10-30, V1.0.0, firmware for GD32W51x
+*/
+
+/*
+    Copyright (c) 2021, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32W51X_LIBOPT_H
+#define GD32W51X_LIBOPT_H
+
+#include "gd32w51x_adc.h"
+#include "gd32w51x_cau.h"
+#include "gd32w51x_crc.h"
+#include "gd32w51x_dbg.h"
+#include "gd32w51x_dci.h"
+#include "gd32w51x_dma.h"
+#include "gd32w51x_efuse.h"
+#include "gd32w51x_exti.h"
+#include "gd32w51x_fmc.h"
+#include "gd32w51x_fwdgt.h"
+#include "gd32w51x_gpio.h"
+#include "gd32w51x_hau.h"
+#include "gd32w51x_hpdf.h"
+#include "gd32w51x_i2c.h"
+#include "gd32w51x_icache.h"
+#include "gd32w51x_misc.h"
+#include "gd32w51x_pkcau.h"
+#include "gd32w51x_pmu.h"
+#include "gd32w51x_qspi.h"
+#include "gd32w51x_rcu.h"
+#include "gd32w51x_rtc.h"
+#include "gd32w51x_sdio.h"
+#include "gd32w51x_spi.h"
+#include "gd32w51x_sqpi.h"
+#include "gd32w51x_syscfg.h"
+#include "gd32w51x_timer.h"
+#include "gd32w51x_trng.h"
+#include "gd32w51x_tsi.h"
+#include "gd32w51x_tzpcu.h"
+#include "gd32w51x_usart.h"
+#include "gd32w51x_wwdgt.h"
+
+#endif /* GD32W51X_LIBOPT_H */

NSPE/Example/ADC/Regular_channel_discontinuous_mode/main.c

@@ -0,0 +1,173 @@
+/*!
+    \file    main.c
+    \brief   ADC discontinuous mode for regular channel demo
+
+    \version 2021-10-30, V1.0.0, firmware for GD32W51x
+*/
+
+/*
+    Copyright (c) 2021, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#include "gd32w51x.h"
+#include "systick.h"
+#include <stdio.h>
+#include "gd32w515p_eval.h"
+
+uint16_t adc_value[16];
+
+void rcu_config(void);
+void gpio_config(void);
+void dma_config(void);
+void adc_config(void);
+
+/*!
+    \brief      main function
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+
+int main(void)
+{
+    /* system clocks configuration */
+    rcu_config();
+    /* systick configuration */
+    systick_config();
+    /* GPIO configuration */
+    gpio_config();
+    /* DMA configuration */
+    dma_config();
+    /* ADC configuration */
+    adc_config();
+
+    while(1){
+        /* delay 1s */
+        delay_1ms(1000U);
+        /* ADC software trigger enable */
+        adc_software_trigger_enable(ADC_REGULAR_CHANNEL);
+    }
+}
+
+/*!
+    \brief      configure the different system clocks
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void rcu_config(void)
+{
+    /* enable GPIO clock */
+    rcu_periph_clock_enable(RCU_GPIOA);
+    rcu_periph_clock_enable(RCU_GPIOB);
+    /* enable ADC clock */
+    rcu_periph_clock_enable(RCU_ADC);
+    adc_clock_config(ADC_ADCCK_HCLK_DIV6);
+    /* enable DMA clock */
+    rcu_periph_clock_enable(RCU_DMA1);
+}
+
+/*!
+    \brief      configure the GPIO peripheral
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void gpio_config(void)
+{
+    /* config the GPIO as analog mode */ 
+    gpio_mode_set(GPIOA, GPIO_MODE_ANALOG, GPIO_PUPD_NONE, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3);
+    gpio_mode_set(GPIOB, GPIO_MODE_ANALOG, GPIO_PUPD_NONE, GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_4|GPIO_PIN_5);
+}
+
+/*!
+    \brief      configure the DMA peripheral
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void dma_config(void)
+{
+    /* ADC_DMA_channel configuration */
+    dma_single_data_parameter_struct dma_single_data_parameter;
+    
+    /* ADC DMA_channel configuration */
+    dma_deinit(DMA1, DMA_CH0);
+    
+    /* initialize DMA single data mode */
+    dma_single_data_parameter.periph_addr         = (uint32_t)(&ADC_RDATA);
+    dma_single_data_parameter.periph_inc          = DMA_PERIPH_INCREASE_DISABLE;
+    dma_single_data_parameter.memory0_addr        = (uint32_t)(adc_value);
+    dma_single_data_parameter.memory_inc          = DMA_MEMORY_INCREASE_ENABLE;
+    dma_single_data_parameter.periph_memory_width = DMA_PERIPH_WIDTH_16BIT;
+    dma_single_data_parameter.direction           = DMA_PERIPH_TO_MEMORY;
+    dma_single_data_parameter.number              = 16U;
+    dma_single_data_parameter.priority            = DMA_PRIORITY_HIGH;
+    
+    dma_single_data_mode_init(DMA1, DMA_CH0, &dma_single_data_parameter);
+    dma_channel_subperipheral_select(DMA1, DMA_CH0, DMA_SUBPERI0);
+    /* enable DMA circulation mode */
+    dma_circulation_enable(DMA1, DMA_CH0);
+  
+    /* enable DMA channel */
+    dma_channel_enable(DMA1, DMA_CH0);
+}
+
+/*!
+    \brief      configure the ADC peripheral
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void adc_config(void)
+{
+    /* ADC data alignment config */
+    adc_data_alignment_config(ADC_DATAALIGN_RIGHT);
+    /* ADC channel length config */
+    adc_channel_length_config(ADC_REGULAR_CHANNEL, 8U);
+    /* ADC discontinuous mode */
+    adc_discontinuous_mode_config(ADC_REGULAR_CHANNEL, 3U);
+
+    /* ADC regular channel config */
+    adc_regular_channel_config(0U, ADC_CHANNEL_0, ADC_SAMPLETIME_55POINT5);
+    adc_regular_channel_config(1U, ADC_CHANNEL_1, ADC_SAMPLETIME_55POINT5);
+    adc_regular_channel_config(2U, ADC_CHANNEL_2, ADC_SAMPLETIME_55POINT5);
+    adc_regular_channel_config(3U, ADC_CHANNEL_3, ADC_SAMPLETIME_55POINT5);
+    adc_regular_channel_config(4U, ADC_CHANNEL_4, ADC_SAMPLETIME_55POINT5);
+    adc_regular_channel_config(5U, ADC_CHANNEL_5, ADC_SAMPLETIME_55POINT5);
+    adc_regular_channel_config(6U, ADC_CHANNEL_6, ADC_SAMPLETIME_55POINT5);
+    adc_regular_channel_config(7U, ADC_CHANNEL_7, ADC_SAMPLETIME_55POINT5);
+
+    /* ADC external trigger config */
+    adc_external_trigger_config(ADC_REGULAR_CHANNEL, EXTERNAL_TRIGGER_DISABLE);
+
+    /* enable ADC interface */
+    adc_enable();
+    delay_1ms(1U);
+
+    /* ADC DMA function enable */
+    adc_dma_mode_enable();
+}

NSPE/Example/ADC/Regular_channel_discontinuous_mode/readme.txt

@@ -0,0 +1,39 @@
+/*!
+    \file    readme.txt
+    \brief   description of the ADC regular channel discontinuous mode example
+
+    \version 2021-10-30, V1.0.0, firmware for GD32W51x
+*/
+
+/*
+    Copyright (c) 2021, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+  This demo is based on the GD32W515P-EVAL-V1.0 board, it shows how to use the ADC
+discontinuous mode. The ADC is configured in discontinuous mode, group length is 8,
+conversion length is 3, using software trigger. Every trigger converts 3 channels.
+
+  You can use the watch window to see the conversion result.

NSPE/Example/ADC/Regular_channel_discontinuous_mode/systick.c

@@ -0,0 +1,82 @@
+/*!
+    \file    systick.c
+    \brief   the systick configuration file
+
+    \version 2021-10-30, V1.0.0, firmware for GD32W51x
+*/
+
+/*
+    Copyright (c) 2021, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#include "gd32w51x.h"
+#include "systick.h"
+
+volatile static uint32_t delay;
+
+/*!
+    \brief      configure systick
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void systick_config(void)
+{
+    /* setup systick timer for 1000Hz interrupts */
+    if(SysTick_Config(SystemCoreClock / 1000U)){
+        /* capture error */
+        while(1){
+        }
+    }
+    /* configure the systick handler priority */
+    NVIC_SetPriority(SysTick_IRQn, 0x00U);
+}
+
+/*!
+    \brief      delay a time in milliseconds
+    \param[in]  count: count in milliseconds
+    \param[out] none
+    \retval     none
+*/
+void delay_1ms(uint32_t count)
+{
+    delay = count;
+    while(0U != delay){
+    }
+}
+
+/*!
+    \brief      delay decrement
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void delay_decrement(void)
+{
+    if(0U != delay){
+        delay--;
+    }
+}

NSPE/Example/ADC/Regular_channel_discontinuous_mode/systick.h

@@ -0,0 +1,47 @@
+/*!
+    \file    systick.h
+    \brief   the header file of systick
+
+    \version 2021-10-30, V1.0.0, firmware for GD32W51x
+*/
+
+/*
+    Copyright (c) 2021, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef SYSTICK_H
+#define SYSTICK_H
+
+#include <stdint.h>
+
+/* configure systick */
+void systick_config(void);
+/* delay a time in milliseconds */
+void delay_1ms(uint32_t count);
+/* delay decrement */
+void delay_decrement(void);
+
+#endif /* SYSTICK_H */

NSPE/Example/ADC/Regular_channel_with_DMA/gd32w51x_it.c

@@ -0,0 +1,139 @@
+/*!
+    \file    gd32w51x_it.c
+    \brief   interrupt service routines
+
+    \version 2021-10-30, V1.0.0, firmware for GD32W51x
+*/
+
+/*
+    Copyright (c) 2021, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#include "gd32w51x_it.h"
+#include "systick.h"
+
+/*!
+    \brief      this function handles NMI exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void NMI_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles HardFault exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void HardFault_Handler(void)
+{
+    /* if Hard Fault exception occurs, go to infinite loop */
+    while(1){
+    }
+}
+
+/*!
+    \brief      this function handles MemManage exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void MemManage_Handler(void)
+{
+    /* if Memory Manage exception occurs, go to infinite loop */
+    while(1){
+    }
+}
+
+/*!
+    \brief      this function handles BusFault exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void BusFault_Handler(void)
+{
+    /* if Bus Fault exception occurs, go to infinite loop */
+    while(1){
+    }
+}
+
+/*!
+    \brief      this function handles UsageFault exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void UsageFault_Handler(void)
+{
+    /* if Usage Fault exception occurs, go to infinite loop */
+    while(1){
+    }
+}
+
+/*!
+    \brief      this function handles SVC exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void SVC_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles DebugMon exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void DebugMon_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles PendSV exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void PendSV_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles SysTick exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void SysTick_Handler(void)
+{
+    delay_decrement();
+}

NSPE/Example/ADC/Regular_channel_with_DMA/gd32w51x_it.h

@@ -0,0 +1,60 @@
+/*!
+    \file    gd32w51x_it.h
+    \brief   the header file of the ISR
+
+    \version 2021-10-30, V1.0.0, firmware for GD32W51x
+*/
+
+/*
+    Copyright (c) 2021, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32W51X_IT_H
+#define GD32W51X_IT_H
+
+#include "gd32w51x.h"
+
+/* function declarations */
+/* this function handles NMI exception */
+void NMI_Handler(void);
+/* this function handles HardFault exception */
+void HardFault_Handler(void);
+/* this function handles MemManage exception */
+void MemManage_Handler(void);
+/* this function handles BusFault exception */
+void BusFault_Handler(void);
+/* this function handles UsageFault exception */
+void UsageFault_Handler(void);
+/* this function handles SVC exception */
+void SVC_Handler(void);
+/* this function handles DebugMon exception */
+void DebugMon_Handler(void);
+/* this function handles PendSV exception */
+void PendSV_Handler(void);
+/* this function handles SysTick exception */
+void SysTick_Handler(void);
+
+#endif /* GD32W51X_IT_H */

NSPE/Example/ADC/Regular_channel_with_DMA/gd32w51x_libopt.h

@@ -0,0 +1,70 @@
+/*!
+    \file    gd32w51x_libopt.h
+    \brief   library optional for gd32w51x
+
+    \version 2021-10-30, V1.0.0, firmware for GD32W51x
+*/
+
+/*
+    Copyright (c) 2021, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32W51X_LIBOPT_H
+#define GD32W51X_LIBOPT_H
+
+#include "gd32w51x_adc.h"
+#include "gd32w51x_cau.h"
+#include "gd32w51x_crc.h"
+#include "gd32w51x_dbg.h"
+#include "gd32w51x_dci.h"
+#include "gd32w51x_dma.h"
+#include "gd32w51x_efuse.h"
+#include "gd32w51x_exti.h"
+#include "gd32w51x_fmc.h"
+#include "gd32w51x_fwdgt.h"
+#include "gd32w51x_gpio.h"
+#include "gd32w51x_hau.h"
+#include "gd32w51x_hpdf.h"
+#include "gd32w51x_i2c.h"
+#include "gd32w51x_icache.h"
+#include "gd32w51x_misc.h"
+#include "gd32w51x_pkcau.h"
+#include "gd32w51x_pmu.h"
+#include "gd32w51x_qspi.h"
+#include "gd32w51x_rcu.h"
+#include "gd32w51x_rtc.h"
+#include "gd32w51x_sdio.h"
+#include "gd32w51x_spi.h"
+#include "gd32w51x_sqpi.h"
+#include "gd32w51x_syscfg.h"
+#include "gd32w51x_timer.h"
+#include "gd32w51x_trng.h"
+#include "gd32w51x_tsi.h"
+#include "gd32w51x_tzpcu.h"
+#include "gd32w51x_usart.h"
+#include "gd32w51x_wwdgt.h"
+
+#endif /* GD32W51X_LIBOPT_H */

NSPE/Example/ADC/Regular_channel_with_DMA/main.c

@@ -0,0 +1,182 @@
+/*!
+    \file    main.c
+    \brief   ADC regular channel with DMA demo
+
+    \version 2021-10-30, V1.0.0, firmware for GD32W51x
+*/
+
+/*
+    Copyright (c) 2021, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#include "gd32w51x.h"
+#include "systick.h"
+#include <stdio.h>
+#include "gd32w515p_eval.h"
+
+uint16_t adc_value[4];
+
+void rcu_config(void);
+void gpio_config(void);
+void dma_config(void);
+void adc_config(void);
+
+/*!
+    \brief      main function
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+int main(void)
+{
+    /* system clocks configuration */
+    rcu_config();
+    /* systick configuration */
+    systick_config();
+    /* GPIO configuration */
+    gpio_config();
+    /* configure COM port */
+    gd_eval_com_init(EVAL_COM0);
+    /* DMA configuration */
+    dma_config();
+    /* ADC configuration */
+    adc_config();
+  
+    while(1){
+        delay_1ms(1000U);
+        printf("\r\n //*******************************//");
+        printf("\r\n ADC regular channel data = %04X", adc_value[0]);
+        printf("\r\n ADC regular channel data = %04X", adc_value[1]);
+        printf("\r\n ADC regular channel data = %04X", adc_value[2]);
+        printf("\r\n ADC regular channel data = %04X\r\n", adc_value[3]);
+    }
+}
+
+/*!
+    \brief      configure the different system clocks
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void rcu_config(void)
+{
+    /* enable GPIOC clock */
+    rcu_periph_clock_enable(RCU_GPIOA);
+    /* enable DMA clock */
+    rcu_periph_clock_enable(RCU_DMA1);
+    /* config ADC clock */
+    rcu_periph_clock_enable(RCU_ADC);
+    adc_clock_config(ADC_ADCCK_HCLK_DIV6);
+}
+
+/*!
+    \brief      configure the GPIO peripheral
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void gpio_config(void)
+{
+    /* config the GPIO as analog mode */
+    gpio_mode_set(GPIOA, GPIO_MODE_ANALOG, GPIO_PUPD_NONE, GPIO_PIN_0| GPIO_PIN_1| GPIO_PIN_2| GPIO_PIN_3);
+}
+
+/*!
+    \brief      configure the DMA peripheral
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void dma_config(void)
+{
+    /* ADC_DMA_channel configuration */
+    dma_single_data_parameter_struct dma_single_data_parameter;
+    
+    /* ADC DMA_channel configuration */
+    dma_deinit(DMA1, DMA_CH0);
+    
+    /* initialize DMA single data mode */
+    dma_single_data_parameter.periph_addr         = (uint32_t)(&ADC_RDATA);
+    dma_single_data_parameter.periph_inc          = DMA_PERIPH_INCREASE_DISABLE;
+    dma_single_data_parameter.memory0_addr        = (uint32_t)(&adc_value);
+    dma_single_data_parameter.memory_inc          = DMA_MEMORY_INCREASE_ENABLE;
+    dma_single_data_parameter.periph_memory_width = DMA_PERIPH_WIDTH_16BIT;
+    dma_single_data_parameter.direction           = DMA_PERIPH_TO_MEMORY;
+    dma_single_data_parameter.number              = 4U;
+    dma_single_data_parameter.priority            = DMA_PRIORITY_HIGH;
+    dma_single_data_mode_init(DMA1, DMA_CH0, &dma_single_data_parameter);
+    dma_channel_subperipheral_select(DMA1, DMA_CH0, DMA_SUBPERI0);
+
+    /* enable DMA circulation mode */
+    dma_circulation_enable(DMA1, DMA_CH0);
+    /* enable DMA channel */
+    dma_channel_enable(DMA1, DMA_CH0);
+}
+
+/*!
+    \brief      configure the ADC peripheral
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void adc_config(void)
+{
+    /* ADC contineous function disable */
+    adc_special_function_config(ADC_CONTINUOUS_MODE, ENABLE);
+    /* ADC scan mode disable */
+    adc_special_function_config(ADC_SCAN_MODE, ENABLE);
+    /* ADC data alignment config */
+    adc_data_alignment_config(ADC_DATAALIGN_RIGHT);
+    /* ADC external trigger enable */
+    adc_external_trigger_config(ADC_REGULAR_CHANNEL, EXTERNAL_TRIGGER_DISABLE);
+
+    /* ADC channel length config */
+    adc_channel_length_config(ADC_REGULAR_CHANNEL, 4U);
+    /* ADC inserted channel config */
+    adc_regular_channel_config(0U, ADC_CHANNEL_0, ADC_SAMPLETIME_55POINT5);
+    adc_regular_channel_config(1U, ADC_CHANNEL_1, ADC_SAMPLETIME_55POINT5);
+    adc_regular_channel_config(2U, ADC_CHANNEL_2, ADC_SAMPLETIME_55POINT5);
+    adc_regular_channel_config(3U, ADC_CHANNEL_3, ADC_SAMPLETIME_55POINT5);
+    
+    /* enable ADC interface */
+    adc_enable();
+    /* wait for ADC stability */
+    delay_1ms(1);
+
+    /* ADC DMA function enable */
+    adc_dma_request_after_last_enable();
+    adc_dma_mode_enable();
+    /* enable ADC software trigger */
+    adc_software_trigger_enable(ADC_REGULAR_CHANNEL);
+}
+
+/* retarget the C library printf function to the USART */
+int fputc(int ch, FILE *f)
+{
+    usart_data_transmit(EVAL_COM0, (uint8_t)ch);
+    while(RESET == usart_flag_get(EVAL_COM0, USART_FLAG_TBE));
+    return ch;
+}

NSPE/Example/ADC/Regular_channel_with_DMA/readme.txt

@@ -0,0 +1,44 @@
+/*!
+    \file    readme.txt
+    \brief   description of the ADC regular channel with DMA demo
+
+    \version 2021-10-30, V1.0.0, firmware for GD32W51x
+*/
+
+/*
+    Copyright (c) 2021, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+  This demo is based on the GD32W515P-EVAL-V1.0 board, it shows how to use the ADC to 
+convert analog signal to digital data through DMA. The ADC is configured in continuous 
+mode, PA0~PA3 is chosen as analog input pin.
+
+  As the ADC conversion begins by software, the converted data from ADC_RDATA register 
+to SRAM begins continuously. Users can change the voltage on the pins, and check if the 
+values matche the converted data through the watch window.
+
+  The analog input pin should configured to AIN mode. We can watch array adc_value[] in 
+debug mode or COM.

NSPE/Example/ADC/Regular_channel_with_DMA/systick.c

@@ -0,0 +1,82 @@
+/*!
+    \file    systick.c
+    \brief   the systick configuration file
+
+    \version 2021-10-30, V1.0.0, firmware for GD32W51x
+*/
+
+/*
+    Copyright (c) 2021, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#include "gd32w51x.h"
+#include "systick.h"
+
+volatile static uint32_t delay;
+
+/*!
+    \brief      configure systick
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void systick_config(void)
+{
+    /* setup systick timer for 1000Hz interrupts */
+    if(SysTick_Config(SystemCoreClock / 1000U)){
+        /* capture error */
+        while(1){
+        }
+    }
+    /* configure the systick handler priority */
+    NVIC_SetPriority(SysTick_IRQn, 0x00U);
+}
+
+/*!
+    \brief      delay a time in milliseconds
+    \param[in]  count: count in milliseconds
+    \param[out] none
+    \retval     none
+*/
+void delay_1ms(uint32_t count)
+{
+    delay = count;
+    while(0U != delay){
+    }
+}
+
+/*!
+    \brief      delay decrement
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void delay_decrement(void)
+{
+    if(0U != delay){
+        delay--;
+    }
+}

NSPE/Example/ADC/Regular_channel_with_DMA/systick.h

@@ -0,0 +1,47 @@
+/*!
+    \file    systick.h
+    \brief   the header file of systick
+
+    \version 2021-10-30, V1.0.0, firmware for GD32W51x
+*/
+
+/*
+    Copyright (c) 2021, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef SYSTICK_H
+#define SYSTICK_H
+
+#include <stdint.h>
+
+/* configure systick */
+void systick_config(void);
+/* delay a time in milliseconds */
+void delay_1ms(uint32_t count);
+/* delay decrement */
+void delay_decrement(void);
+
+#endif /* SYSTICK_H */

NSPE/Example/ADC/Software_trigger_regular_channel_polling/gd32w51x_it.c

@@ -0,0 +1,152 @@
+/*!
+    \file    gd32w51x_it.c
+    \brief   interrupt service routines
+
+    \version 2021-10-30, V1.0.0, firmware for GD32W51x
+*/
+
+/*
+    Copyright (c) 2021, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#include "gd32w51x_it.h"
+#include "systick.h"
+#include "gd32w515p_eval.h"
+
+/*!
+    \brief      this function handles NMI exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void NMI_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles HardFault exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void HardFault_Handler(void)
+{
+    /* if Hard Fault exception occurs, go to infinite loop */
+    while (1){
+    }
+}
+
+/*!
+    \brief      this function handles MemManage exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void MemManage_Handler(void)
+{
+    /* if Memory Manage exception occurs, go to infinite loop */
+    while (1){
+    }
+}
+
+/*!
+    \brief      this function handles BusFault exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void BusFault_Handler(void)
+{
+    /* if Bus Fault exception occurs, go to infinite loop */
+    while (1){
+    }
+}
+
+/*!
+    \brief      this function handles UsageFault exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void UsageFault_Handler(void)
+{
+    /* if Usage Fault exception occurs, go to infinite loop */
+    while (1){
+    }
+}
+
+/*!
+    \brief      this function handles SVC exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void SVC_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles DebugMon exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void DebugMon_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles PendSV exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void PendSV_Handler(void)
+{
+}
+
+/*!
+    \brief      this function handles SecureFault exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void SecureFault_Handler(void)
+{
+    /* if Secure Fault exception occurs, go to infinite loop */
+    while (1){
+    }
+}
+/*!
+    \brief      this function handles SysTick exception
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void SysTick_Handler(void)
+{
+    delay_decrement();
+}

NSPE/Example/ADC/Software_trigger_regular_channel_polling/gd32w51x_it.h

@@ -0,0 +1,62 @@
+/*!
+    \file    gd32w51x_it.h
+    \brief   the header file of the ISR
+
+    \version 2021-10-30, V1.0.0, firmware for GD32W51x
+*/
+
+/*
+    Copyright (c) 2021, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32W51X_IT_H
+#define GD32W51X_IT_H
+
+#include "gd32w51x.h"
+
+/* function declarations */
+/* this function handles NMI exception */
+void NMI_Handler(void);
+/* this function handles HardFault exception */
+void HardFault_Handler(void);
+/* this function handles MemManage exception */
+void MemManage_Handler(void);
+/* this function handles BusFault exception */
+void BusFault_Handler(void);
+/* this function handles UsageFault exception */
+void UsageFault_Handler(void);
+/* this function handles SVC exception */
+void SVC_Handler(void);
+/* this function handles DebugMon exception */
+void DebugMon_Handler(void);
+/* this function handles PendSV exception */
+void PendSV_Handler(void);
+/* this function handles SecureFault exception */
+void SecureFault_Handler(void);
+/* this function handles SysTick exception */
+void SysTick_Handler(void);
+
+#endif /* GD32W51X_IT_H */

NSPE/Example/ADC/Software_trigger_regular_channel_polling/gd32w51x_libopt.h

@@ -0,0 +1,70 @@
+/*!
+    \file    gd32w51x_libopt.h
+    \brief   library optional for gd32w51x
+
+    \version 2021-10-30, V1.0.0, firmware for GD32W51x
+*/
+
+/*
+    Copyright (c) 2021, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32W51X_LIBOPT_H
+#define GD32W51X_LIBOPT_H
+
+#include "gd32w51x_adc.h"
+#include "gd32w51x_cau.h"
+#include "gd32w51x_crc.h"
+#include "gd32w51x_dbg.h"
+#include "gd32w51x_dci.h"
+#include "gd32w51x_dma.h"
+#include "gd32w51x_efuse.h"
+#include "gd32w51x_exti.h"
+#include "gd32w51x_fmc.h"
+#include "gd32w51x_fwdgt.h"
+#include "gd32w51x_gpio.h"
+#include "gd32w51x_hau.h"
+#include "gd32w51x_hpdf.h"
+#include "gd32w51x_i2c.h"
+#include "gd32w51x_icache.h"
+#include "gd32w51x_misc.h"
+#include "gd32w51x_pkcau.h"
+#include "gd32w51x_pmu.h"
+#include "gd32w51x_qspi.h"
+#include "gd32w51x_rcu.h"
+#include "gd32w51x_rtc.h"
+#include "gd32w51x_sdio.h"
+#include "gd32w51x_spi.h"
+#include "gd32w51x_sqpi.h"
+#include "gd32w51x_syscfg.h"
+#include "gd32w51x_timer.h"
+#include "gd32w51x_trng.h"
+#include "gd32w51x_tsi.h"
+#include "gd32w51x_tzpcu.h"
+#include "gd32w51x_usart.h"
+#include "gd32w51x_wwdgt.h"
+
+#endif /* GD32W51X_LIBOPT_H */

NSPE/Example/ADC/Software_trigger_regular_channel_polling/main.c

@@ -0,0 +1,140 @@
+/*!
+    \file    main.c
+    \brief   ADC software trigger regular channel polling
+
+    \version 2021-10-30, V1.0.0, firmware for GD32W51x
+*/
+
+/*
+    Copyright (c) 2021, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#include "gd32w51x.h"
+#include "systick.h"
+#include <stdio.h>
+#include "gd32w515p_eval.h"
+
+__IO uint16_t adc_value[4];
+
+void rcu_config(void);
+void gpio_config(void);
+void adc_config(void);
+uint16_t adc_channel_sample(uint8_t channel);
+
+/*!
+    \brief      main function
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+
+int main(void)
+{
+    /* system clocks configuration */
+    rcu_config();
+    /* systick configuration */
+    systick_config();
+    /* GPIO configuration */
+    gpio_config();
+    /* ADC configuration */
+    adc_config();
+  
+    while(1){
+        adc_value[0] = adc_channel_sample(ADC_CHANNEL_0);
+        adc_value[1] = adc_channel_sample(ADC_CHANNEL_1);
+        adc_value[2] = adc_channel_sample(ADC_CHANNEL_2);
+        adc_value[3] = adc_channel_sample(ADC_CHANNEL_3);
+    }
+}
+
+/*!
+    \brief      configure the different system clocks
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void rcu_config(void)
+{
+    /* enable GPIO clock */
+    rcu_periph_clock_enable(RCU_GPIOA);
+    /* enable ADC clock */
+    rcu_periph_clock_enable(RCU_ADC);
+    adc_clock_config(ADC_ADCCK_HCLK_DIV6);
+}
+
+/*!
+    \brief      configure the GPIO peripheral
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void gpio_config(void)
+{
+    /* config the GPIO as analog mode */
+    gpio_mode_set(GPIOA, GPIO_MODE_ANALOG, GPIO_PUPD_NONE, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3);
+}
+
+/*!
+    \brief      configure the ADC peripheral
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void adc_config(void)
+{
+    /* ADC data alignment config */
+    adc_data_alignment_config(ADC_DATAALIGN_RIGHT);
+    /* ADC channel length config */
+    adc_channel_length_config( ADC_REGULAR_CHANNEL, 1U);
+    
+    /* ADC external trigger config */
+    adc_external_trigger_config(ADC_REGULAR_CHANNEL, EXTERNAL_TRIGGER_DISABLE);
+
+    /* enable ADC interface */
+    adc_enable();
+    delay_1ms(1U);
+}
+
+/*!
+    \brief      ADC channel sample
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+uint16_t adc_channel_sample(uint8_t channel)
+{
+    /* ADC regular channel config */
+    adc_regular_channel_config(0U, channel, ADC_SAMPLETIME_14POINT5);
+    /* ADC software trigger enable */
+    adc_software_trigger_enable(ADC_REGULAR_CHANNEL);
+
+    /* wait the end of conversion flag */
+    while(!adc_flag_get(ADC_FLAG_EOC));
+    /* clear the end of conversion flag */
+    adc_flag_clear(ADC_FLAG_EOC);
+    /* return regular channel sample value */
+    return (adc_regular_data_read());
+}