diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/BuildLog.log b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/BuildLog.log
new file mode 100755
index 0000000..5f28270
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/BuildLog.log
@@ -0,0 +1 @@
+
\ No newline at end of file
diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/Ebyte_Kfifo.pbi.xcl b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/Ebyte_Kfifo.pbi.xcl
new file mode 100755
index 0000000..e061f4f
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/Ebyte_Kfifo.pbi.xcl
@@ -0,0 +1,312 @@
+"D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\1_Middleware\Kfifo\ebyte_kfifo.c"
+-std=c99
+-ferror-limit=0
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\2_Ebyte_Board_Support\E15-EVB02
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers\inc
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Kfifo
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\ebyte
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Produce
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx
+-I
+D:\software\IAR_EW\IAR_STM8_310\stm8\inc
+-I
+D:\software\IAR_EW\IAR_STM8_310\stm8\inc\c
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\2_Ebyte_Board_Support\E15-EVB02
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\4_STM8_L15x_StdPeriph_Drivers\inc
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\4_STM8_L15x_StdPeriph_Drivers
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\1_Middleware\Kfifo
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\ebyte
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\1_Middleware\Produce
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\3_Ebyte_WirelessModule_Drivers\E48xMx
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+-D__DATA_PTR_MEMORY_LIST3__(_P1,_P2)=__DATA_PTR_MEM_HELPER3__(__tiny, 0, _P1, _P2) __DATA_PTR_MEM_HELPER3__(__near, 1, _P1, _P2) __DATA_PTR_MEM_HELPER3__(__far, 2, _P1, _P2) __DATA_PTR_MEM_HELPER3__(__huge, 3, _P1, _P2) __DATA_PTR_MEM_HELPER3__(__eeprom, 4, _P1, _P2)
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+-D__TOPP_DATA_MEMORY_LIST3__(_P1,_P2)=__TOPP_DATA_MEM_HELPER3__(__near, 1, _P1, _P2) __TOPP_DATA_MEM_HELPER3__(__huge, 3, _P1, _P2) __TOPP_DATA_MEM_HELPER3__(__eeprom, 4, _P1, _P2)
+-D__DEF_HEAP_MEM__=__near
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+-D_DLIB_CONFIG_FILE_STRING="D:\\software\\IAR_EW\\IAR_STM8_310\\stm8\\LIB\\dlstm8smn.h"
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+-D__CODE_MEMORY_LIST1__()=__CODE_MEM_HELPER1__(__code, 0 )
+-D__CODE_MEMORY_LIST2__(_P1)=__CODE_MEM_HELPER2__(__code, 0 ,  _P1 )
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+-D__HVAR_MEMORY_LIST1__()=__HVAR_MEM_HELPER1__(__data, 0 )
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+-D__TOPM_DATA_MEMORY_LIST2__(_P1)=
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diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/board.pbi b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/board.pbi
new file mode 100755
index 0000000..4b6344c
Binary files /dev/null and b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/board.pbi differ
diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/board.pbi.xcl b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/board.pbi.xcl
new file mode 100755
index 0000000..2b3e265
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/board.pbi.xcl
@@ -0,0 +1,312 @@
+"D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\2_Ebyte_Board_Support\E15-EVB02\board.c"
+-std=c99
+-ferror-limit=0
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\2_Ebyte_Board_Support\E15-EVB02
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers\inc
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Kfifo
+-I
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diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/board_button.pbi b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/board_button.pbi
new file mode 100755
index 0000000..b85e69f
Binary files /dev/null and b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/board_button.pbi differ
diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/board_button.pbi.xcl b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/board_button.pbi.xcl
new file mode 100755
index 0000000..656f634
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/board_button.pbi.xcl
@@ -0,0 +1,312 @@
+"D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\2_Ebyte_Board_Support\E15-EVB02\board_button.c"
+-std=c99
+-ferror-limit=0
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\2_Ebyte_Board_Support\E15-EVB02
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers\inc
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Kfifo
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\ebyte
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Produce
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx
+-I
+D:\software\IAR_EW\IAR_STM8_310\stm8\inc
+-I
+D:\software\IAR_EW\IAR_STM8_310\stm8\inc\c
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\2_Ebyte_Board_Support\E15-EVB02
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\4_STM8_L15x_StdPeriph_Drivers\inc
+-I
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+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\1_Middleware\Kfifo
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\ebyte
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\1_Middleware\Produce
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\3_Ebyte_WirelessModule_Drivers\E48xMx
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diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/board_mini_printf.pbi.xcl b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/board_mini_printf.pbi.xcl
new file mode 100755
index 0000000..11863cf
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/board_mini_printf.pbi.xcl
@@ -0,0 +1,312 @@
+"D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\2_Ebyte_Board_Support\E15-EVB02\board_mini_printf.c"
+-std=c99
+-ferror-limit=0
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\2_Ebyte_Board_Support\E15-EVB02
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers\inc
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Kfifo
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\ebyte
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Produce
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx
+-I
+D:\software\IAR_EW\IAR_STM8_310\stm8\inc
+-I
+D:\software\IAR_EW\IAR_STM8_310\stm8\inc\c
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\2_Ebyte_Board_Support\E15-EVB02
+-I
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+-I
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+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\1_Middleware\Kfifo
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\ebyte
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\1_Middleware\Produce
+-I
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diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/cmt2310a_410mhz.pbi.xcl b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/cmt2310a_410mhz.pbi.xcl
new file mode 100755
index 0000000..ea3c2e0
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/cmt2310a_410mhz.pbi.xcl
@@ -0,0 +1,312 @@
+"D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\3_Ebyte_WirelessModule_Drivers\E48xMx\cmt2310a_410mhz.c"
+-std=c99
+-ferror-limit=0
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\2_Ebyte_Board_Support\E15-EVB02
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers\inc
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Kfifo
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\ebyte
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Produce
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx
+-I
+D:\software\IAR_EW\IAR_STM8_310\stm8\inc
+-I
+D:\software\IAR_EW\IAR_STM8_310\stm8\inc\c
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\2_Ebyte_Board_Support\E15-EVB02
+-I
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+-I
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+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\1_Middleware\Kfifo
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\ebyte
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\1_Middleware\Produce
+-I
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diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/cmt2310a_433mhz.pbi.xcl b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/cmt2310a_433mhz.pbi.xcl
new file mode 100755
index 0000000..945e025
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/cmt2310a_433mhz.pbi.xcl
@@ -0,0 +1,312 @@
+"D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\3_Ebyte_WirelessModule_Drivers\E48xMx\cmt2310a_433mhz.c"
+-std=c99
+-ferror-limit=0
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\2_Ebyte_Board_Support\E15-EVB02
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers\inc
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Kfifo
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\ebyte
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Produce
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx
+-I
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+-I
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+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\1_Middleware\Kfifo
+-I
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diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/cmt2310a_868mhz.pbi.xcl b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/cmt2310a_868mhz.pbi.xcl
new file mode 100755
index 0000000..746a2ce
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/cmt2310a_868mhz.pbi.xcl
@@ -0,0 +1,312 @@
+"D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\3_Ebyte_WirelessModule_Drivers\E48xMx\cmt2310a_868mhz.c"
+-std=c99
+-ferror-limit=0
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\2_Ebyte_Board_Support\E15-EVB02
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers\inc
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Kfifo
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\ebyte
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Produce
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx
+-I
+D:\software\IAR_EW\IAR_STM8_310\stm8\inc
+-I
+D:\software\IAR_EW\IAR_STM8_310\stm8\inc\c
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\2_Ebyte_Board_Support\E15-EVB02
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\4_STM8_L15x_StdPeriph_Drivers\inc
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\4_STM8_L15x_StdPeriph_Drivers
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\1_Middleware\Kfifo
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\ebyte
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\1_Middleware\Produce
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\3_Ebyte_WirelessModule_Drivers\E48xMx
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diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/cmt2310a_915mhz.pbi.xcl b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/cmt2310a_915mhz.pbi.xcl
new file mode 100755
index 0000000..6318cb8
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/cmt2310a_915mhz.pbi.xcl
@@ -0,0 +1,312 @@
+"D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\3_Ebyte_WirelessModule_Drivers\E48xMx\cmt2310a_915mhz.c"
+-std=c99
+-ferror-limit=0
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\2_Ebyte_Board_Support\E15-EVB02
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers\inc
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Kfifo
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\ebyte
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Produce
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx
+-I
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+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\1_Middleware\Kfifo
+-I
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+-I
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diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/ebyte_callback.pbi.xcl b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/ebyte_callback.pbi.xcl
new file mode 100755
index 0000000..f0b3562
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/ebyte_callback.pbi.xcl
@@ -0,0 +1,312 @@
+"D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\ebyte\ebyte_callback.c"
+-std=c99
+-ferror-limit=0
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+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers\inc
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Kfifo
+-I
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+-I
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+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx
+-I
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diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/ebyte_core.pbi.xcl b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/ebyte_core.pbi.xcl
new file mode 100755
index 0000000..cc65d1e
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/ebyte_core.pbi.xcl
@@ -0,0 +1,312 @@
+"D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\ebyte\ebyte_core.c"
+-std=c99
+-ferror-limit=0
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\2_Ebyte_Board_Support\E15-EVB02
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers\inc
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Kfifo
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\ebyte
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Produce
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx
+-I
+D:\software\IAR_EW\IAR_STM8_310\stm8\inc
+-I
+D:\software\IAR_EW\IAR_STM8_310\stm8\inc\c
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\2_Ebyte_Board_Support\E15-EVB02
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\4_STM8_L15x_StdPeriph_Drivers\inc
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\4_STM8_L15x_StdPeriph_Drivers
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\1_Middleware\Kfifo
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\ebyte
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\1_Middleware\Produce
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\3_Ebyte_WirelessModule_Drivers\E48xMx
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diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/ebyte_debug.pbi.xcl b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/ebyte_debug.pbi.xcl
new file mode 100755
index 0000000..b86504c
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/ebyte_debug.pbi.xcl
@@ -0,0 +1,312 @@
+"D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\1_Middleware\Produce\ebyte_debug.c"
+-std=c99
+-ferror-limit=0
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\2_Ebyte_Board_Support\E15-EVB02
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers\inc
+-I
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diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/ebyte_e07x.o b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/ebyte_e07x.o
new file mode 100755
index 0000000..93a7510
Binary files /dev/null and b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/ebyte_e07x.o differ
diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/ebyte_e07x.pbi.xcl b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/ebyte_e07x.pbi.xcl
new file mode 100755
index 0000000..38a29c8
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/ebyte_e07x.pbi.xcl
@@ -0,0 +1,312 @@
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+-std=c99
+-ferror-limit=0
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+E:\Ebyte_Product\0_Ebyte\E15\E15-EVB02\Software\2021-05-06-Project\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\2_Ebyte_Board_Support\E15-EVB02
+-I
+E:\Ebyte_Product\0_Ebyte\E15\E15-EVB02\Software\2021-05-06-Project\0_Project\IAR_for_Stm8\Uart_PingPong\ebyte\E07xMx
+-I
+E:\Ebyte_Product\0_Ebyte\E15\E15-EVB02\Software\2021-05-06-Project\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers\inc
+-I
+E:\Ebyte_Product\0_Ebyte\E15\E15-EVB02\Software\2021-05-06-Project\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers
+-I
+E:\Ebyte_Product\0_Ebyte\E15\E15-EVB02\Software\2021-05-06-Project\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Kfifo
+-I
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+E:\Ebyte_Product\0_Ebyte\E15\E15-EVB02\Software\2021-05-06-Project\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Produce
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diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/ebyte_e10x.o b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/ebyte_e10x.o
new file mode 100755
index 0000000..0204442
Binary files /dev/null and b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/ebyte_e10x.o differ
diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/ebyte_e10x.pbi.xcl b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/ebyte_e10x.pbi.xcl
new file mode 100755
index 0000000..c154bcf
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/ebyte_e10x.pbi.xcl
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diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/ebyte_e220x.o b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/ebyte_e220x.o
new file mode 100755
index 0000000..6e7d2ad
Binary files /dev/null and b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/ebyte_e220x.o differ
diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/ebyte_e220x.pbi.xcl b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/ebyte_e220x.pbi.xcl
new file mode 100755
index 0000000..229627b
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/ebyte_e220x.pbi.xcl
@@ -0,0 +1,312 @@
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diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/ebyte_e22x.pbi b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/ebyte_e22x.pbi
new file mode 100755
index 0000000..33dab83
Binary files /dev/null and b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/ebyte_e22x.pbi differ
diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/ebyte_e22x.pbi.xcl b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/ebyte_e22x.pbi.xcl
new file mode 100755
index 0000000..8b11c89
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/ebyte_e22x.pbi.xcl
@@ -0,0 +1,316 @@
+"D:\Project_UART\E48\E48-XXXM20S\E15-EVB02-E48\0_Project\IAR_for_Stm8\Uart_PingPong\ebyte\E22xMx\ebyte_e22x.c"
+-std=c99
+-ferror-limit=0
+-I
+D:\Project_UART\E48\E48-XXXM20S\E15-EVB02-E48\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\2_Ebyte_Board_Support\E15-EVB02
+-I
+D:\Project_UART\E48\E48-XXXM20S\E15-EVB02-E48\0_Project\IAR_for_Stm8\Uart_PingPong\ebyte\E22xMx
+-I
+D:\Project_UART\E48\E48-XXXM20S\E15-EVB02-E48\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers\inc
+-I
+D:\Project_UART\E48\E48-XXXM20S\E15-EVB02-E48\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers
+-I
+D:\Project_UART\E48\E48-XXXM20S\E15-EVB02-E48\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Kfifo
+-I
+D:\Project_UART\E48\E48-XXXM20S\E15-EVB02-E48\0_Project\IAR_for_Stm8\Uart_PingPong\ebyte
+-I
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+-I
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diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/ebyte_e48x.pbi.xcl b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/ebyte_e48x.pbi.xcl
new file mode 100755
index 0000000..49660f5
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/ebyte_e48x.pbi.xcl
@@ -0,0 +1,312 @@
+"D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\3_Ebyte_WirelessModule_Drivers\E48xMx\ebyte_e48x.c"
+-std=c99
+-ferror-limit=0
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\2_Ebyte_Board_Support\E15-EVB02
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers\inc
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Kfifo
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\ebyte
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Produce
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx
+-I
+D:\software\IAR_EW\IAR_STM8_310\stm8\inc
+-I
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+-I
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+-I
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+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\1_Middleware\Kfifo
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\ebyte
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\1_Middleware\Produce
+-I
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diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/ebyte_e49x.o b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/ebyte_e49x.o
new file mode 100755
index 0000000..cf0577e
Binary files /dev/null and b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/ebyte_e49x.o differ
diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/ebyte_e49x.pbi.xcl b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/ebyte_e49x.pbi.xcl
new file mode 100755
index 0000000..0d7bcb2
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/ebyte_e49x.pbi.xcl
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diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/ebyte_port.pbi.xcl b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/ebyte_port.pbi.xcl
new file mode 100755
index 0000000..c90f7b4
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/ebyte_port.pbi.xcl
@@ -0,0 +1,312 @@
+"D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\ebyte\ebyte_port.c"
+-std=c99
+-ferror-limit=0
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+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers\inc
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Kfifo
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\ebyte
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Produce
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx
+-I
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diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/main.pbi.xcl b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/main.pbi.xcl
new file mode 100755
index 0000000..fb353e9
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/main.pbi.xcl
@@ -0,0 +1,312 @@
+"D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\main.c"
+-std=c99
+-ferror-limit=0
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\2_Ebyte_Board_Support\E15-EVB02
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers\inc
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Kfifo
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\ebyte
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Produce
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx
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diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/project.pbd b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/project.pbd
new file mode 100755
index 0000000..575e2e8
Binary files /dev/null and b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/project.pbd differ
diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/radio.pbi.xcl b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/radio.pbi.xcl
new file mode 100755
index 0000000..8ea525e
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/radio.pbi.xcl
@@ -0,0 +1,312 @@
+"D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\3_Ebyte_WirelessModule_Drivers\E48xMx\radio.c"
+-std=c99
+-ferror-limit=0
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\2_Ebyte_Board_Support\E15-EVB02
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers\inc
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Kfifo
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\ebyte
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Produce
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx
+-I
+D:\software\IAR_EW\IAR_STM8_310\stm8\inc
+-I
+D:\software\IAR_EW\IAR_STM8_310\stm8\inc\c
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\2_Ebyte_Board_Support\E15-EVB02
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\4_STM8_L15x_StdPeriph_Drivers\inc
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\4_STM8_L15x_StdPeriph_Drivers
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\1_Middleware\Kfifo
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\ebyte
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\1_Middleware\Produce
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\3_Ebyte_WirelessModule_Drivers\E48xMx
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diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/radio_hal.pbi.xcl b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/radio_hal.pbi.xcl
new file mode 100755
index 0000000..ab69b97
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/radio_hal.pbi.xcl
@@ -0,0 +1,312 @@
+"D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\3_Ebyte_WirelessModule_Drivers\E48xMx\radio_hal.c"
+-std=c99
+-ferror-limit=0
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\2_Ebyte_Board_Support\E15-EVB02
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers\inc
+-I
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diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/radio_mac.pbi.xcl b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/radio_mac.pbi.xcl
new file mode 100755
index 0000000..e850c46
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/radio_mac.pbi.xcl
@@ -0,0 +1,312 @@
+"D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\3_Ebyte_WirelessModule_Drivers\E48xMx\radio_mac.c"
+-std=c99
+-ferror-limit=0
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\2_Ebyte_Board_Support\E15-EVB02
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers\inc
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Kfifo
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\ebyte
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Produce
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx
+-I
+D:\software\IAR_EW\IAR_STM8_310\stm8\inc
+-I
+D:\software\IAR_EW\IAR_STM8_310\stm8\inc\c
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\2_Ebyte_Board_Support\E15-EVB02
+-I
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+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\4_STM8_L15x_StdPeriph_Drivers
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\1_Middleware\Kfifo
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\ebyte
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\1_Middleware\Produce
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\3_Ebyte_WirelessModule_Drivers\E48xMx
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diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/radio_phy.pbi.xcl b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/radio_phy.pbi.xcl
new file mode 100755
index 0000000..d9a6623
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/radio_phy.pbi.xcl
@@ -0,0 +1,312 @@
+"D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\3_Ebyte_WirelessModule_Drivers\E48xMx\radio_phy.c"
+-std=c99
+-ferror-limit=0
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\2_Ebyte_Board_Support\E15-EVB02
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers\inc
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Kfifo
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\ebyte
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Produce
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx
+-I
+D:\software\IAR_EW\IAR_STM8_310\stm8\inc
+-I
+D:\software\IAR_EW\IAR_STM8_310\stm8\inc\c
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\2_Ebyte_Board_Support\E15-EVB02
+-I
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+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\4_STM8_L15x_StdPeriph_Drivers
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\1_Middleware\Kfifo
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\ebyte
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\1_Middleware\Produce
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\3_Ebyte_WirelessModule_Drivers\E48xMx
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diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/radio_spi.pbi.xcl b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/radio_spi.pbi.xcl
new file mode 100755
index 0000000..5e00acb
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/radio_spi.pbi.xcl
@@ -0,0 +1,312 @@
+"D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\3_Ebyte_WirelessModule_Drivers\E48xMx\radio_spi.c"
+-std=c99
+-ferror-limit=0
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\2_Ebyte_Board_Support\E15-EVB02
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers\inc
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Kfifo
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\ebyte
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Produce
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx
+-I
+D:\software\IAR_EW\IAR_STM8_310\stm8\inc
+-I
+D:\software\IAR_EW\IAR_STM8_310\stm8\inc\c
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\2_Ebyte_Board_Support\E15-EVB02
+-I
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+-I
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+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\1_Middleware\Kfifo
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\ebyte
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\1_Middleware\Produce
+-I
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diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_adc.pbi.xcl b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_adc.pbi.xcl
new file mode 100755
index 0000000..3191868
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_adc.pbi.xcl
@@ -0,0 +1,312 @@
+"D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_adc.c"
+-std=c99
+-ferror-limit=0
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\2_Ebyte_Board_Support\E15-EVB02
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers\inc
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Kfifo
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\ebyte
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Produce
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx
+-I
+D:\software\IAR_EW\IAR_STM8_310\stm8\inc
+-I
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+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\1_Middleware\Kfifo
+-I
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+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\1_Middleware\Produce
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+-D__DATA_PTR_MEMORY_LIST3__(_P1,_P2)=__DATA_PTR_MEM_HELPER3__(__tiny, 0, _P1, _P2) __DATA_PTR_MEM_HELPER3__(__near, 1, _P1, _P2) __DATA_PTR_MEM_HELPER3__(__far, 2, _P1, _P2) __DATA_PTR_MEM_HELPER3__(__huge, 3, _P1, _P2) __DATA_PTR_MEM_HELPER3__(__eeprom, 4, _P1, _P2)
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diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_aes.pbi.xcl b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_aes.pbi.xcl
new file mode 100755
index 0000000..a69b17b
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_aes.pbi.xcl
@@ -0,0 +1,312 @@
+"D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_aes.c"
+-std=c99
+-ferror-limit=0
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\2_Ebyte_Board_Support\E15-EVB02
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers\inc
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Kfifo
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\ebyte
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Produce
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx
+-I
+D:\software\IAR_EW\IAR_STM8_310\stm8\inc
+-I
+D:\software\IAR_EW\IAR_STM8_310\stm8\inc\c
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\2_Ebyte_Board_Support\E15-EVB02
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\4_STM8_L15x_StdPeriph_Drivers\inc
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\4_STM8_L15x_StdPeriph_Drivers
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\1_Middleware\Kfifo
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\ebyte
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\1_Middleware\Produce
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\3_Ebyte_WirelessModule_Drivers\E48xMx
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diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_beep.pbi.xcl b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_beep.pbi.xcl
new file mode 100755
index 0000000..233cb4f
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_beep.pbi.xcl
@@ -0,0 +1,312 @@
+"D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_beep.c"
+-std=c99
+-ferror-limit=0
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\2_Ebyte_Board_Support\E15-EVB02
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers\inc
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Kfifo
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\ebyte
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Produce
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx
+-I
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diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_clk.pbi.xcl b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_clk.pbi.xcl
new file mode 100755
index 0000000..c95eaba
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_clk.pbi.xcl
@@ -0,0 +1,312 @@
+"D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_clk.c"
+-std=c99
+-ferror-limit=0
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\2_Ebyte_Board_Support\E15-EVB02
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers\inc
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Kfifo
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\ebyte
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Produce
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx
+-I
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+-D__HVAR_MEMORY_LIST1__()=__HVAR_MEM_HELPER1__(__data, 0 )
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+-D__TOPM_DATA_MEMORY_LIST2__(_P1)=
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diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_comp.pbi.xcl b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_comp.pbi.xcl
new file mode 100755
index 0000000..eb2d3eb
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_comp.pbi.xcl
@@ -0,0 +1,312 @@
+"D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_comp.c"
+-std=c99
+-ferror-limit=0
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\2_Ebyte_Board_Support\E15-EVB02
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers\inc
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Kfifo
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\ebyte
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Produce
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx
+-I
+D:\software\IAR_EW\IAR_STM8_310\stm8\inc
+-I
+D:\software\IAR_EW\IAR_STM8_310\stm8\inc\c
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\2_Ebyte_Board_Support\E15-EVB02
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\4_STM8_L15x_StdPeriph_Drivers\inc
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\4_STM8_L15x_StdPeriph_Drivers
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\1_Middleware\Kfifo
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\ebyte
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\1_Middleware\Produce
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\3_Ebyte_WirelessModule_Drivers\E48xMx
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diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_dac.pbi.xcl b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_dac.pbi.xcl
new file mode 100755
index 0000000..b59db76
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_dac.pbi.xcl
@@ -0,0 +1,312 @@
+"D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_dac.c"
+-std=c99
+-ferror-limit=0
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\2_Ebyte_Board_Support\E15-EVB02
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers\inc
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers
+-I
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diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_dma.pbi.xcl b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_dma.pbi.xcl
new file mode 100755
index 0000000..d361e61
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_dma.pbi.xcl
@@ -0,0 +1,312 @@
+"D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_dma.c"
+-std=c99
+-ferror-limit=0
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\2_Ebyte_Board_Support\E15-EVB02
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers\inc
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Kfifo
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\ebyte
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Produce
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx
+-I
+D:\software\IAR_EW\IAR_STM8_310\stm8\inc
+-I
+D:\software\IAR_EW\IAR_STM8_310\stm8\inc\c
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\2_Ebyte_Board_Support\E15-EVB02
+-I
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+-I
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+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\1_Middleware\Kfifo
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\ebyte
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\1_Middleware\Produce
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\3_Ebyte_WirelessModule_Drivers\E48xMx
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diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_exti.pbi.xcl b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_exti.pbi.xcl
new file mode 100755
index 0000000..6148c10
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_exti.pbi.xcl
@@ -0,0 +1,312 @@
+"D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_exti.c"
+-std=c99
+-ferror-limit=0
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\2_Ebyte_Board_Support\E15-EVB02
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers\inc
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Kfifo
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\ebyte
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Produce
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx
+-I
+D:\software\IAR_EW\IAR_STM8_310\stm8\inc
+-I
+D:\software\IAR_EW\IAR_STM8_310\stm8\inc\c
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\2_Ebyte_Board_Support\E15-EVB02
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\4_STM8_L15x_StdPeriph_Drivers\inc
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\4_STM8_L15x_StdPeriph_Drivers
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\1_Middleware\Kfifo
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\ebyte
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\1_Middleware\Produce
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\3_Ebyte_WirelessModule_Drivers\E48xMx
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diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_flash.pbi.xcl b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_flash.pbi.xcl
new file mode 100755
index 0000000..5c66475
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_flash.pbi.xcl
@@ -0,0 +1,312 @@
+"D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_flash.c"
+-std=c99
+-ferror-limit=0
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\2_Ebyte_Board_Support\E15-EVB02
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers\inc
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Kfifo
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\ebyte
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Produce
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx
+-I
+D:\software\IAR_EW\IAR_STM8_310\stm8\inc
+-I
+D:\software\IAR_EW\IAR_STM8_310\stm8\inc\c
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\2_Ebyte_Board_Support\E15-EVB02
+-I
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+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\4_STM8_L15x_StdPeriph_Drivers
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\1_Middleware\Kfifo
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\ebyte
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\1_Middleware\Produce
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\3_Ebyte_WirelessModule_Drivers\E48xMx
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+-D__DATA_MEMORY_LIST3__(_P1,_P2)=__DATA_MEM_HELPER3__(__tiny, 0, _P1, _P2) __DATA_MEM_HELPER3__(__near, 1, _P1, _P2) __DATA_MEM_HELPER3__(__far, 2, _P1, _P2) __DATA_MEM_HELPER3__(__huge, 3, _P1, _P2) __DATA_MEM_HELPER3__(__eeprom, 4, _P1, _P2)
+-D__CODE_MEM0__=__near_func
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+-D__DATA_MEM1_INTPTR_SIZE_PREFIX__="h"
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+-D__TOPP_DATA_MEMORY_LIST3__(_P1,_P2)=__TOPP_DATA_MEM_HELPER3__(__near, 1, _P1, _P2) __TOPP_DATA_MEM_HELPER3__(__huge, 3, _P1, _P2) __TOPP_DATA_MEM_HELPER3__(__eeprom, 4, _P1, _P2)
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+-D__HEAP_MEMORY_LIST3__(_P1, _P2)=__HEAP_MEM_HELPER3__(__data, 0 ,  _P1 ,  _P2 )
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+-D__TOPM_DATA_MEMORY_LIST2__(_P1)=
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+-D__TOPP_DATA_MEMORY_LIST1__()=__TOPP_DATA_MEM_HELPER1__(__data, 0 )
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diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_gpio.pbi.xcl b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_gpio.pbi.xcl
new file mode 100755
index 0000000..c793157
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_gpio.pbi.xcl
@@ -0,0 +1,312 @@
+"D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_gpio.c"
+-std=c99
+-ferror-limit=0
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\2_Ebyte_Board_Support\E15-EVB02
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers\inc
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Kfifo
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\ebyte
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Produce
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx
+-I
+D:\software\IAR_EW\IAR_STM8_310\stm8\inc
+-I
+D:\software\IAR_EW\IAR_STM8_310\stm8\inc\c
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\2_Ebyte_Board_Support\E15-EVB02
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\4_STM8_L15x_StdPeriph_Drivers\inc
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\4_STM8_L15x_StdPeriph_Drivers
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\1_Middleware\Kfifo
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\ebyte
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\1_Middleware\Produce
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\3_Ebyte_WirelessModule_Drivers\E48xMx
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+-D__INT8_C_SUFFIX__=
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+-D__UINT_FAST16_T_MAX__=0xffffU
+-D__INT_FAST16_SIZE_PREFIX__=""
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+-D__DATA_MEMORY_LIST3__(_P1,_P2)=__DATA_MEM_HELPER3__(__tiny, 0, _P1, _P2) __DATA_MEM_HELPER3__(__near, 1, _P1, _P2) __DATA_MEM_HELPER3__(__far, 2, _P1, _P2) __DATA_MEM_HELPER3__(__huge, 3, _P1, _P2) __DATA_MEM_HELPER3__(__eeprom, 4, _P1, _P2)
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diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_i2c.pbi.xcl b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_i2c.pbi.xcl
new file mode 100755
index 0000000..3fa5a10
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_i2c.pbi.xcl
@@ -0,0 +1,312 @@
+"D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_i2c.c"
+-std=c99
+-ferror-limit=0
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\2_Ebyte_Board_Support\E15-EVB02
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers\inc
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Kfifo
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\ebyte
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Produce
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx
+-I
+D:\software\IAR_EW\IAR_STM8_310\stm8\inc
+-I
+D:\software\IAR_EW\IAR_STM8_310\stm8\inc\c
+-I
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+-I
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+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\4_STM8_L15x_StdPeriph_Drivers
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\1_Middleware\Kfifo
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\ebyte
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\1_Middleware\Produce
+-I
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diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_irtim.pbi.xcl b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_irtim.pbi.xcl
new file mode 100755
index 0000000..e85ce4d
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_irtim.pbi.xcl
@@ -0,0 +1,312 @@
+"D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_irtim.c"
+-std=c99
+-ferror-limit=0
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\2_Ebyte_Board_Support\E15-EVB02
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers\inc
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Kfifo
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\ebyte
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Produce
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx
+-I
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diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_it.pbi.xcl b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_it.pbi.xcl
new file mode 100755
index 0000000..71c04bc
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_it.pbi.xcl
@@ -0,0 +1,312 @@
+"D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\stm8l15x_it.c"
+-std=c99
+-ferror-limit=0
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\2_Ebyte_Board_Support\E15-EVB02
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers\inc
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Kfifo
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\ebyte
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Produce
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx
+-I
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+-I
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diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_itc.pbi.xcl b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_itc.pbi.xcl
new file mode 100755
index 0000000..64dc956
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_itc.pbi.xcl
@@ -0,0 +1,304 @@
+"E:\Ebyte_Product\0_Ebyte\E15\E15-EVB02\Software\2021-05-06-Project\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_itc.c"
+-std=c99
+-ferror-limit=0
+-I
+E:\Ebyte_Product\0_Ebyte\E15\E15-EVB02\Software\2021-05-06-Project\0_Project\IAR_for_Stm8\Empty_Template\..\..\..\2_Ebyte_Board_Support\E15-EVB02
+-I
+E:\Ebyte_Product\0_Ebyte\E15\E15-EVB02\Software\2021-05-06-Project\0_Project\IAR_for_Stm8\Empty_Template\..\..\..\3_Ebyte_WirelessModule_Drivers
+-I
+E:\Ebyte_Product\0_Ebyte\E15\E15-EVB02\Software\2021-05-06-Project\0_Project\IAR_for_Stm8\Empty_Template\..\..\..\3_Ebyte_WirelessModule_Drivers\E22xMx
+-I
+E:\Ebyte_Product\0_Ebyte\E15\E15-EVB02\Software\2021-05-06-Project\0_Project\IAR_for_Stm8\Empty_Template\..\..\..\4_STM8_L15x_StdPeriph_Drivers\inc
+-I
+E:\Ebyte_Product\0_Ebyte\E15\E15-EVB02\Software\2021-05-06-Project\0_Project\IAR_for_Stm8\Empty_Template\..\..\..\4_STM8_L15x_StdPeriph_Drivers
+-I
+F:\01_JH_Software\IAR\Install_ForStm8\stm8\inc
+-I
+F:\01_JH_Software\IAR\Install_ForStm8\stm8\inc\c
+-I
+E:\Ebyte_Product\0_Ebyte\E15\E15-EVB02\Software\2021-05-06-Project\2_Ebyte_Board_Support\E15-EVB02
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+E:\Ebyte_Product\0_Ebyte\E15\E15-EVB02\Software\2021-05-06-Project\3_Ebyte_WirelessModule_Drivers
+-I
+E:\Ebyte_Product\0_Ebyte\E15\E15-EVB02\Software\2021-05-06-Project\3_Ebyte_WirelessModule_Drivers\E22xMx
+-I
+E:\Ebyte_Product\0_Ebyte\E15\E15-EVB02\Software\2021-05-06-Project\4_STM8_L15x_StdPeriph_Drivers\inc
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diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_iwdg.pbi.xcl b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_iwdg.pbi.xcl
new file mode 100755
index 0000000..64ebbfe
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_iwdg.pbi.xcl
@@ -0,0 +1,312 @@
+"D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_iwdg.c"
+-std=c99
+-ferror-limit=0
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\2_Ebyte_Board_Support\E15-EVB02
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers\inc
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Kfifo
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\ebyte
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Produce
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx
+-I
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+-I
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diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_lcd.pbi.xcl b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_lcd.pbi.xcl
new file mode 100755
index 0000000..b924f0c
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_lcd.pbi.xcl
@@ -0,0 +1,312 @@
+"D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_lcd.c"
+-std=c99
+-ferror-limit=0
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\2_Ebyte_Board_Support\E15-EVB02
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers\inc
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Kfifo
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\ebyte
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Produce
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx
+-I
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+-I
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+-I
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+-I
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diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_pwr.pbi.xcl b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_pwr.pbi.xcl
new file mode 100755
index 0000000..1132389
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_pwr.pbi.xcl
@@ -0,0 +1,312 @@
+"D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_pwr.c"
+-std=c99
+-ferror-limit=0
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\2_Ebyte_Board_Support\E15-EVB02
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers\inc
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Kfifo
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\ebyte
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Produce
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx
+-I
+D:\software\IAR_EW\IAR_STM8_310\stm8\inc
+-I
+D:\software\IAR_EW\IAR_STM8_310\stm8\inc\c
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\2_Ebyte_Board_Support\E15-EVB02
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\4_STM8_L15x_StdPeriph_Drivers\inc
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\4_STM8_L15x_StdPeriph_Drivers
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\1_Middleware\Kfifo
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\ebyte
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\1_Middleware\Produce
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\3_Ebyte_WirelessModule_Drivers\E48xMx
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diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_rst.pbi.xcl b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_rst.pbi.xcl
new file mode 100755
index 0000000..daa51ed
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_rst.pbi.xcl
@@ -0,0 +1,312 @@
+"D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_rst.c"
+-std=c99
+-ferror-limit=0
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\2_Ebyte_Board_Support\E15-EVB02
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers\inc
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Kfifo
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\ebyte
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Produce
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx
+-I
+D:\software\IAR_EW\IAR_STM8_310\stm8\inc
+-I
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+-I
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+-I
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+-I
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+-I
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+-I
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diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_rtc.pbi.xcl b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_rtc.pbi.xcl
new file mode 100755
index 0000000..aa4ede8
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_rtc.pbi.xcl
@@ -0,0 +1,312 @@
+"D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_rtc.c"
+-std=c99
+-ferror-limit=0
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\2_Ebyte_Board_Support\E15-EVB02
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers\inc
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Kfifo
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\ebyte
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Produce
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx
+-I
+D:\software\IAR_EW\IAR_STM8_310\stm8\inc
+-I
+D:\software\IAR_EW\IAR_STM8_310\stm8\inc\c
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\2_Ebyte_Board_Support\E15-EVB02
+-I
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+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\4_STM8_L15x_StdPeriph_Drivers
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\1_Middleware\Kfifo
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\ebyte
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\1_Middleware\Produce
+-I
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diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_spi.pbi.xcl b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_spi.pbi.xcl
new file mode 100755
index 0000000..413a5e6
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_spi.pbi.xcl
@@ -0,0 +1,312 @@
+"D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_spi.c"
+-std=c99
+-ferror-limit=0
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\2_Ebyte_Board_Support\E15-EVB02
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers\inc
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Kfifo
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\ebyte
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Produce
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx
+-I
+D:\software\IAR_EW\IAR_STM8_310\stm8\inc
+-I
+D:\software\IAR_EW\IAR_STM8_310\stm8\inc\c
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\2_Ebyte_Board_Support\E15-EVB02
+-I
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+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\4_STM8_L15x_StdPeriph_Drivers
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\1_Middleware\Kfifo
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\ebyte
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\1_Middleware\Produce
+-I
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diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_syscfg.pbi.xcl b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_syscfg.pbi.xcl
new file mode 100755
index 0000000..93fb2cc
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_syscfg.pbi.xcl
@@ -0,0 +1,312 @@
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+-std=c99
+-ferror-limit=0
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+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\2_Ebyte_Board_Support\E15-EVB02
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers\inc
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Kfifo
+-I
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+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Produce
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx
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diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_tim1.pbi.xcl b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_tim1.pbi.xcl
new file mode 100755
index 0000000..5bd21ff
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_tim1.pbi.xcl
@@ -0,0 +1,312 @@
+"D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_tim1.c"
+-std=c99
+-ferror-limit=0
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\2_Ebyte_Board_Support\E15-EVB02
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers\inc
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Kfifo
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\ebyte
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Produce
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx
+-I
+D:\software\IAR_EW\IAR_STM8_310\stm8\inc
+-I
+D:\software\IAR_EW\IAR_STM8_310\stm8\inc\c
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\2_Ebyte_Board_Support\E15-EVB02
+-I
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+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\4_STM8_L15x_StdPeriph_Drivers
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\1_Middleware\Kfifo
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\ebyte
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\1_Middleware\Produce
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diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_tim2.pbi.xcl b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_tim2.pbi.xcl
new file mode 100755
index 0000000..d89cd12
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_tim2.pbi.xcl
@@ -0,0 +1,312 @@
+"D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_tim2.c"
+-std=c99
+-ferror-limit=0
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\2_Ebyte_Board_Support\E15-EVB02
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers\inc
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Kfifo
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\ebyte
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Produce
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx
+-I
+D:\software\IAR_EW\IAR_STM8_310\stm8\inc
+-I
+D:\software\IAR_EW\IAR_STM8_310\stm8\inc\c
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\2_Ebyte_Board_Support\E15-EVB02
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\4_STM8_L15x_StdPeriph_Drivers\inc
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\4_STM8_L15x_StdPeriph_Drivers
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\1_Middleware\Kfifo
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\ebyte
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\1_Middleware\Produce
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\3_Ebyte_WirelessModule_Drivers\E48xMx
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+-D__TOPP_DATA_MEMORY_LIST3__(_P1,_P2)=__TOPP_DATA_MEM_HELPER3__(__near, 1, _P1, _P2) __TOPP_DATA_MEM_HELPER3__(__huge, 3, _P1, _P2) __TOPP_DATA_MEM_HELPER3__(__eeprom, 4, _P1, _P2)
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+-D__TOPM_DATA_MEMORY_LIST2__(_P1)=
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+-D__TOPP_DATA_MEMORY_LIST1__()=__TOPP_DATA_MEM_HELPER1__(__data, 0 )
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diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_tim3.pbi.xcl b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_tim3.pbi.xcl
new file mode 100755
index 0000000..1efc674
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_tim3.pbi.xcl
@@ -0,0 +1,312 @@
+"D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_tim3.c"
+-std=c99
+-ferror-limit=0
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\2_Ebyte_Board_Support\E15-EVB02
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers\inc
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Kfifo
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\ebyte
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Produce
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx
+-I
+D:\software\IAR_EW\IAR_STM8_310\stm8\inc
+-I
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+-I
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diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_tim4.pbi.xcl b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_tim4.pbi.xcl
new file mode 100755
index 0000000..a40685b
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_tim4.pbi.xcl
@@ -0,0 +1,312 @@
+"D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_tim4.c"
+-std=c99
+-ferror-limit=0
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\2_Ebyte_Board_Support\E15-EVB02
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers\inc
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Kfifo
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\ebyte
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Produce
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx
+-I
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+-I
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+-I
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+-I
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+-I
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+-I
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+-I
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+-I
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diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_tim5.pbi.xcl b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_tim5.pbi.xcl
new file mode 100755
index 0000000..0e7bf7b
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_tim5.pbi.xcl
@@ -0,0 +1,312 @@
+"D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_tim5.c"
+-std=c99
+-ferror-limit=0
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\2_Ebyte_Board_Support\E15-EVB02
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers\inc
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Kfifo
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\ebyte
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Produce
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx
+-I
+D:\software\IAR_EW\IAR_STM8_310\stm8\inc
+-I
+D:\software\IAR_EW\IAR_STM8_310\stm8\inc\c
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\2_Ebyte_Board_Support\E15-EVB02
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\4_STM8_L15x_StdPeriph_Drivers\inc
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\4_STM8_L15x_StdPeriph_Drivers
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\1_Middleware\Kfifo
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\ebyte
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\1_Middleware\Produce
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\3_Ebyte_WirelessModule_Drivers\E48xMx
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diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_usart.pbi.xcl b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_usart.pbi.xcl
new file mode 100755
index 0000000..b711e28
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_usart.pbi.xcl
@@ -0,0 +1,312 @@
+"D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_usart.c"
+-std=c99
+-ferror-limit=0
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\2_Ebyte_Board_Support\E15-EVB02
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers\inc
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Kfifo
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\ebyte
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Produce
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx
+-I
+D:\software\IAR_EW\IAR_STM8_310\stm8\inc
+-I
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+-I
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+-I
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+-I
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+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\1_Middleware\Kfifo
+-I
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+-I
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diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_wfe.pbi.xcl b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_wfe.pbi.xcl
new file mode 100755
index 0000000..298f8b9
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_wfe.pbi.xcl
@@ -0,0 +1,312 @@
+"D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_wfe.c"
+-std=c99
+-ferror-limit=0
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\2_Ebyte_Board_Support\E15-EVB02
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers\inc
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Kfifo
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\ebyte
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Produce
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx
+-I
+D:\software\IAR_EW\IAR_STM8_310\stm8\inc
+-I
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+-I
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+-I
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diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_wwdg.pbi.xcl b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_wwdg.pbi.xcl
new file mode 100755
index 0000000..8ba2c07
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/Debug/Obj/stm8l15x_wwdg.pbi.xcl
@@ -0,0 +1,312 @@
+"D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_wwdg.c"
+-std=c99
+-ferror-limit=0
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\2_Ebyte_Board_Support\E15-EVB02
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers\inc
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\4_STM8_L15x_StdPeriph_Drivers
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Kfifo
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\ebyte
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\1_Middleware\Produce
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx
+-I
+D:\software\IAR_EW\IAR_STM8_310\stm8\inc
+-I
+D:\software\IAR_EW\IAR_STM8_310\stm8\inc\c
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\2_Ebyte_Board_Support\E15-EVB02
+-I
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+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\4_STM8_L15x_StdPeriph_Drivers
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\1_Middleware\Kfifo
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\ebyte
+-I
+D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\1_Middleware\Produce
+-I
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+-D__MEDIUM_CODE_MODEL__=2
+-D__MEDIUM_DATA_MODEL__=2
+-D__SMALL_CODE_MODEL__=1
+-D__SMALL_DATA_MODEL__=1
+-D__STM8__=1
+-D__PLAIN_INT_BITFIELD_IS_SIGNED__=1
+-D__HAS_WEAK__=1
+-D__HAS_LOCATED_DECLARATION__=1
+-D__HAS_LOCATED_WITH_INIT__=1
+-D__IAR_COMPILERBASE__=595714
+-D__STDC__=1
+-D__STDC_VERSION__=199901L
+-D__STDC_HOSTED__=1
+-D__STDC_NO_VLA__=1
+-D__STDC_NO_ATOMICS__=1
+-D__EDG_IA64_ABI=1
+-D__EDG_IA64_ABI_VARIANT_CTORS_AND_DTORS_RETURN_THIS=1
+-D__EDG_IA64_ABI_USE_INT_STATIC_INIT_GUARD=1
+-D__EDG_TYPE_TRAITS_ENABLED=1
+-D__EDG__=1
+-D__EDG_VERSION__=410
+-D__EDG_SIZE_TYPE__=unsigned short
+-D__EDG_PTRDIFF_TYPE__=short
+-D__EDG_DELTA_TYPE=short
+-D__EDG_IA64_VTABLE_ENTRY_TYPE=short
+-D__EDG_VIRTUAL_FUNCTION_INDEX_TYPE=unsigned short
+-D__EDG_LOWER_VARIABLE_LENGTH_ARRAYS=1
+-D__EDG_IA64_ABI_USE_VARIANT_ARRAY_COOKIES=1
+-D__EDG_ABI_COMPATIBILITY_VERSION=9999
+-D__EDG_ABI_CHANGES_FOR_RTTI=1
+-D__EDG_ABI_CHANGES_FOR_ARRAY_NEW_AND_DELETE=1
+-D__EDG_ABI_CHANGES_FOR_PLACEMENT_DELETE=1
+-D__EDG_BSD=0
+-D__EDG_SYSV=0
+-D__EDG_ANSIC=1
+-D__EDG_CPP11_IL_EXTENSIONS_SUPPORTED=1
+-D_DLIB_CONFIG_FILE_HEADER_NAME="D:\software\IAR_EW\IAR_STM8_310\stm8\LIB\dlstm8smn.h"
+-D_DLIB_CONFIG_FILE_STRING="D:\\software\\IAR_EW\\IAR_STM8_310\\stm8\\LIB\\dlstm8smn.h"
+-D__VERSION__="IAR C/C++ Compiler V3.10.1.201 for STM8"
+-D__CODE_MEMORY_LIST1__()=__CODE_MEM_HELPER1__(__code, 0 )
+-D__CODE_MEMORY_LIST2__(_P1)=__CODE_MEM_HELPER2__(__code, 0 ,  _P1 )
+-D__CODE_MEMORY_LIST3__(_P1, _P2)=__CODE_MEM_HELPER3__(__code, 0 ,  _P1 ,  _P2 )
+-D__DATA_MEMORY_LIST1__()=__DATA_MEM_HELPER1__(__data, 0 )
+-D__DATA_MEMORY_LIST2__(_P1)=__DATA_MEM_HELPER2__(__data, 0 ,  _P1 )
+-D__DATA_MEMORY_LIST3__(_P1, _P2)=__DATA_MEM_HELPER3__(__data, 0 ,  _P1 ,  _P2 )
+-D__CODE_PTR_MEMORY_LIST1__()=__CODE_PTR_MEM_HELPER1__(__code, 0 )
+-D__CODE_PTR_MEMORY_LIST2__(_P1)=__CODE_PTR_MEM_HELPER2__(__code, 0 ,  _P1 )
+-D__CODE_PTR_MEMORY_LIST3__(_P1, _P2)=__CODE_PTR_MEM_HELPER3__(__code, 0 ,  _P1 ,  _P2 )
+-D__DATA_PTR_MEMORY_LIST1__()=__DATA_PTR_MEM_HELPER1__(__data, 0 )
+-D__DATA_PTR_MEMORY_LIST2__(_P1)=__DATA_PTR_MEM_HELPER2__(__data, 0 ,  _P1 )
+-D__DATA_PTR_MEMORY_LIST3__(_P1, _P2)=__DATA_PTR_MEM_HELPER3__(__data, 0 ,  _P1 ,  _P2 )
+-D__VAR_MEMORY_LIST1__()=__VAR_MEM_HELPER1__(__data, 0 )
+-D__VAR_MEMORY_LIST2__(_P1)=__VAR_MEM_HELPER2__(__data, 0 ,  _P1 )
+-D__VAR_MEMORY_LIST3__(_P1, _P2)=__VAR_MEM_HELPER3__(__data, 0 ,  _P1 ,  _P2 )
+-D__VARD_MEMORY_LIST1__()=__VARD_MEM_HELPER1__(__data, 0, _ )
+-D__HEAP_MEMORY_LIST1__()=__HEAP_MEM_HELPER1__(__data, 0 )
+-D__HEAP_MEMORY_LIST2__(_P1)=__HEAP_MEM_HELPER2__(__data, 0 ,  _P1 )
+-D__HEAP_MEMORY_LIST3__(_P1, _P2)=__HEAP_MEM_HELPER3__(__data, 0 ,  _P1 ,  _P2 )
+-D__HVAR_MEMORY_LIST1__()=__HVAR_MEM_HELPER1__(__data, 0 )
+-D__HEAPD_MEMORY_LIST1__()=__HEAPD_MEM_HELPER1__(__data, 0, _ )
+-D__HEAPU_MEMORY_LIST1__()=__HEAPU_MEM_HELPER1__(__data, 0 )
+-D__TOPM_DATA_MEMORY_LIST1__()=
+-D__TOPM_DATA_MEMORY_LIST2__(_P1)=
+-D__TOPM_DATA_MEMORY_LIST3__(_P1, _P2)=
+-D__TOPP_DATA_MEMORY_LIST1__()=__TOPP_DATA_MEM_HELPER1__(__data, 0 )
+-D__TOPP_DATA_MEMORY_LIST2__(_P1)=__TOPP_DATA_MEM_HELPER2__(__data, 0 ,  _P1 )
+-D__TOPP_DATA_MEMORY_LIST3__(_P1, _P2)=__TOPP_DATA_MEM_HELPER3__(__data, 0 ,  _P1 ,  _P2 )
+-D__DATA_MEM0_SIZE_TYPE__=unsigned int
+-D__DATA_MEM0_INDEX_TYPE__=signed int
diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/ebyte/ebyte_callback.c b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/ebyte/ebyte_callback.c
new file mode 100755
index 0000000..dbe525c
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/ebyte/ebyte_callback.c
@@ -0,0 +1,155 @@
+/**
+  **********************************************************************************
+  * @file      ebyte_callback.h
+  * @brief     EBYTEÇý¶¯¿âµÄÊÕ·¢Íê³É»Øµ÷º¯Êý ÓÉ¿Í»§ÊµÏÖ×Ô¼ºµÄÂß¼­´úÂë 
+  * @details   ÏêÇéÇë²Î¼û https://www.ebyte.com/       
+  * @author    JiangHeng     
+  * @date      2021-05-13     
+  * @version   1.0.0     
+  **********************************************************************************
+  * @copyright BSD License 
+  *            ³É¶¼ÒÚ°ÛÌصç×ӿƼ¼ÓÐÏÞ¹«Ë¾  
+  *   ______   ____   __     __  _______   ______ 
+  *  |  ____| |  _ \  \ \   / / |__   __| |  ____|
+  *  | |__    | |_) |  \ \_/ /     | |    | |__   
+  *  |  __|   |  _ <    \   /      | |    |  __|  
+  *  | |____  | |_) |    | |       | |    | |____ 
+  *  |______| |____/     |_|       |_|    |______| 
+  *
+  **********************************************************************************
+  */
+#include "ebyte_callback.h"
+
+/*= !!!ÅäÖÃÄ¿±êÓ²¼þƽ̨ͷÎļþ =======================================*/
+#include "board.h"  //E15-EVB02 ÆÀ¹À°å
+#include "ebyte_debug.h"  //E15-EVB02 ÆÀ¹À°å
+/*= !!!ÅäÖÃÄ¿±êÓ²¼þ±äÁ¿       =======================================*/
+extern uint8_t RxBuffer[64];
+extern uint8_t BufferPing[5];
+extern uint8_t BufferPong[5];
+extern uint8_t Callback_isPingCheckReady;
+extern uint8_t PC_isConnected;
+extern uint8_t PcEchoBuffer[20];
+/*==================================================================*/
+
+
+
+/* !
+ * @brief ·¢ËÍÍê³É»Øµ÷½Ó¿Ú ÓÉ¿Í»§ÊµÏÖ×Ô¼ºµÄ·¢ËÍÍê³ÉÂß¼­
+ * 
+ * @param state Éϲã»Øµ÷ÌṩµÄ״̬Âë ¿Í»§Çë¸ù¾ÝʾÀý×¢ÊÍÕÒµ½¶ÔÓ¦ÇøÓò
+ *  
+ */
+void Ebyte_Port_TransmitCallback( uint16e_t state )
+{       
+    /* ·¢ËÍ: Õý³£Íê³É */
+    if( state &= 0x0001 )
+    {
+        //To-do ʵÏÖ×Ô¼ºµÄÂß¼­ 
+    }
+    /* ·¢ËÍ: Òì³£³¬Ê± */
+    else if ( state &= 0x0200 )
+    {
+        //To-do ʵÏÖ×Ô¼ºµÄÂß¼­ 
+    }
+    /* ·¢ËÍ: δ֪´íÎó */
+    else
+    {
+        /* ·¢ËÍ״̬±êʶ²»ÕýÈ·£¬Çë¼ì²éÈíÓ²¼þ  
+           ³£¼ûÎÊÌâ 1:SPIͨÐŲ»ÕýÈ· 2:Ä£¿é¹©µç²»×ã */
+        while(1);
+    }
+}
+
+/* !
+ * @brief ½ÓÊÕÍê³É»Øµ÷½Ó¿Ú ÓÉ¿Í»§ÊµÏÖ×Ô¼ºµÄ·¢ËÍÍê³ÉÂß¼­
+ * 
+ * @param state Éϲã»Øµ÷ÌṩµÄ״̬Âë ¿Í»§Çë¸ù¾ÝʾÀý×¢ÊÍÕÒµ½¶ÔÓ¦ÇøÓò
+ * 
+ */
+void Ebyte_Port_ReceiveCallback(  uint16_t state, uint8_t *buffer, uint8_t length )
+{
+    uint8_t  j,  pcEchoLength;
+    uint8_t *p;
+    /* ½ÓÊÕ: Õý³£ */
+    if( state &= 0x0002 )
+    {
+         //To-do ʵÏÖ×Ô¼ºµÄÂß¼­
+
+        /* ͨ¹ý³¤¶ÈÅжÏÊÇ·ñÊÇping pongÖ¸Áî  */
+        if( length == 4 || length == 5 )
+        {
+
+            p = buffer;
+            for( j = 0; j < 4; j++ )
+            {
+                if( BufferPing[j] != *p++ )
+                {
+                    break;
+                }
+
+            }
+            //±È½Ïµ½ÁËĩβ±íʾÍêÈ«Æ¥Åäping
+            if( j == 4 )
+            {
+                Callback_isPingCheckReady = 1;//֪ͨ»Ø¸´Pong
+                if( length == 5 && PC_isConnected  )
+                {
+                    BufferPong[4] = buffer[4];//µÚ5×Ö½ÚΪ°´¼ü±êʶ
+                }
+                
+            }
+
+            if( j!=4 && length == 5 && PC_isConnected )
+            {
+                p = buffer;
+                
+                for( j = 0; j < 4; j++ )
+                {
+                    if( BufferPong[j] != *p++ )
+                    {
+                        break;
+                    }
+
+                }
+
+                if( j == 4 )//ÍêÈ«Æ¥Åäpong
+                {
+                    if( 0x01 == buffer[4]  )
+                    {
+                        Ebyte_DEBUG_CommandEcho( ( uint8_t* )SimulatedCommandsWireless1, EBYTE_CMD_PACKAGE_LENGTH, PcEchoBuffer, &pcEchoLength );
+                    }
+                    else
+                    {
+                        Ebyte_DEBUG_CommandEcho( ( uint8_t* )SimulatedCommandsWireless2, EBYTE_CMD_PACKAGE_LENGTH, PcEchoBuffer, &pcEchoLength );
+                    }
+                    Ebyte_BSP_UartTransmit( PcEchoBuffer, pcEchoLength );
+                }
+
+            }
+        }
+
+        Ebyte_BSP_LedControl( BSP_LED_1, ON );
+
+        if( ! PC_isConnected )
+        {
+            
+            DEBUG("\r\n Receive Data:");
+            Ebyte_BSP_UartTransmit ( buffer, length );
+        }
+
+        Ebyte_BSP_LedControl( BSP_LED_1, OFF );
+    }
+    /* ½ÓÊÕ: Òì³£³¬Ê± */
+    else if ( state &= 0x0200 )
+    {
+        //To-do ʵÏÖ×Ô¼ºµÄÂß¼­ 
+    }
+    /* ½ÓÊÕ: δ֪´íÎó */
+    else
+    {
+        /* ·¢ËÍ״̬±êʶ²»ÕýÈ·£¬Çë¼ì²éÈíÓ²¼þ  
+           ³£¼ûÎÊÌâ 1:SPIͨÐŲ»ÕýÈ· 2:Ä£¿é¹©µç²»×ã */
+        while(1);
+    }
+}
\ No newline at end of file
diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/ebyte/ebyte_callback.h b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/ebyte/ebyte_callback.h
new file mode 100755
index 0000000..0c299fb
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/ebyte/ebyte_callback.h
@@ -0,0 +1,8 @@
+#ifndef _EBYTE_CALLBACK_H_
+#define _EBYTE_CALLBACK_H_
+#include "ebyte_port.h"
+
+void Ebyte_Port_TransmitCallback( uint16e_t state );
+void Ebyte_Port_ReceiveCallback(  uint16e_t state ,uint8e_t *buffer, uint8e_t length);
+
+#endif
\ No newline at end of file
diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/ebyte/ebyte_conf.h b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/ebyte/ebyte_conf.h
new file mode 100755
index 0000000..5f42b81
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/ebyte/ebyte_conf.h
@@ -0,0 +1,34 @@
+/**
+  **********************************************************************************
+  * @file      ebyte_conf.h
+  * @brief     EBYTEÇý¶¯¿âµÄͨÓÃÅäÖÃÎļþ    
+  * @details   ÏêÇéÇë²Î¼û https://www.ebyte.com/       
+  * @author    JiangHeng     
+  * @date      2021-05-13     
+  * @version   1.0.0     
+  **********************************************************************************
+  * @copyright BSD License 
+  *            ³É¶¼ÒÚ°ÛÌصç×ӿƼ¼ÓÐÏÞ¹«Ë¾  
+  *   ______   ____   __     __  _______   ______ 
+  *  |  ____| |  _ \  \ \   / / |__   __| |  ____|
+  *  | |__    | |_) |  \ \_/ /     | |    | |__   
+  *  |  __|   |  _ <    \   /      | |    |  __|  
+  *  | |____  | |_) |    | |       | |    | |____ 
+  *  |______| |____/     |_|       |_|    |______| 
+  *
+  **********************************************************************************
+  */
+
+/*= !!!ÅäÖòúÆ·ÐͺŠµ¥Ñ¡ ============================================*/
+#define EBYTE_E48_433M20S
+//#define EBYTE_E48_900M20S
+
+/*==================================================================*/
+
+/* SPIͨÐÅ ÓÉÈí¼þ¿ØÖÆCS(NSS)ÐźŠ 0:½ûÓà 1:ÆôÓà */
+#define EBYTE_PORT_SPI_CS_SOFTWARE    1
+
+/* ÈçºÎ¼ì²âÄ£¿é·¢ËÍʱµÄ״̬  0:Òì²½ÖжÏ֪ͨ  1:ͬ²½×èÈû */
+#define EBYTE_RF_TRANSMIT_CHECK_MODE  1
+
+
diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/ebyte/ebyte_core.c b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/ebyte/ebyte_core.c
new file mode 100755
index 0000000..7c5cec8
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/ebyte/ebyte_core.c
@@ -0,0 +1,48 @@
+/**
+  **********************************************************************************
+  * @file      ebyte_core.c
+  * @brief     EBYTEÇý¶¯¿âµÄÉϲãAPI·â×°²ã °ïÖú¿Í»§³éÏóµ×²ãÂß¼­    
+  * @details   ÏêÇéÇë²Î¼û https://www.ebyte.com/       
+  * @author    JiangHeng     
+  * @date      2021-05-13     
+  * @version   1.0.0     
+  **********************************************************************************
+  * @copyright BSD License 
+  *            ³É¶¼ÒÚ°ÛÌصç×ӿƼ¼ÓÐÏÞ¹«Ë¾  
+  *   ______   ____   __     __  _______   ______ 
+  *  |  ____| |  _ \  \ \   / / |__   __| |  ____|
+  *  | |__    | |_) |  \ \_/ /     | |    | |__   
+  *  |  __|   |  _ <    \   /      | |    |  __|  
+  *  | |____  | |_) |    | |       | |    | |____ 
+  *  |______| |____/     |_|       |_|    |______| 
+  *
+  **********************************************************************************
+  */
+
+
+#include "ebyte_core.h"
+
+/* Ö¸Ïò E48x µ×²ãÇý¶¯º¯Êý */
+
+#if defined(EBYTE_E48_433M20S)||defined(EBYTE_E48_900M20S)
+const Ebyte_RF_t Ebyte_RF =
+{
+  Ebyte_E48x_Init,
+  Ebyte_E48x_SendPayload,
+  Ebyte_E48x_SetSleep,
+  Ebyte_E48x_SetRx,  
+  Ebyte_E48x_IntOrPollTask,
+  Ebyte_E48x_InterruptTrigger,
+  Ebyte_E48x_GetName,
+  Ebyte_E48x_GetDriverVersion
+};
+#else
+/* ebyte_conf.h ºêÅäÖÃÑ¡ÔñµÄ²úÆ·ÐͺŲ»ÕýÈ· */
+#error No product selected !
+#endif
+
+
+
+
+
+
diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/ebyte/ebyte_core.h b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/ebyte/ebyte_core.h
new file mode 100755
index 0000000..c4d1df2
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/ebyte/ebyte_core.h
@@ -0,0 +1,45 @@
+/**
+  **********************************************************************************
+  * @file      ebyte_core.h
+  * @brief     EBYTEÇý¶¯¿âµÄÉϲãAPI·â×°²ã °ïÖú¿Í»§³éÏóµ×²ãÂß¼­    
+  * @details   ÏêÇéÇë²Î¼û https://www.ebyte.com/       
+  * @author    JiangHeng     
+  * @date      2021-05-13     
+  * @version   1.0.0     
+  **********************************************************************************
+  * @copyright BSD License 
+  *            ³É¶¼ÒÚ°ÛÌصç×ӿƼ¼ÓÐÏÞ¹«Ë¾  
+  *   ______   ____   __     __  _______   ______ 
+  *  |  ____| |  _ \  \ \   / / |__   __| |  ____|
+  *  | |__    | |_) |  \ \_/ /     | |    | |__   
+  *  |  __|   |  _ <    \   /      | |    |  __|  
+  *  | |____  | |_) |    | |       | |    | |____ 
+  *  |______| |____/     |_|       |_|    |______| 
+  *
+  **********************************************************************************
+  */
+
+#include "ebyte_conf.h"
+
+#if defined(EBYTE_E48_433M20S)||defined(EBYTE_E48_900M20S)
+#include "ebyte_e48x.h"
+#else
+#error No product selected !
+#endif
+
+typedef struct
+{
+    void   ( *Init )( void );
+    void   ( *Send )( uint8e_t *buffer, uint8e_t size , uint32e_t timeout);
+    void   ( *EnterSleepMode )( uint8e_t command);    
+    void   ( *EnterReceiveMode )( uint32e_t timeout );  
+    void   ( *StartPollTask)( void );
+    void   ( *InterruptTrigger)( void );
+    uint32e_t ( *GetName ) (void );
+    uint8e_t ( *GetDriverVersion ) (void );
+}Ebyte_RF_t; 
+
+extern const Ebyte_RF_t Ebyte_RF;
+
+
+
diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/ebyte/ebyte_port.c b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/ebyte/ebyte_port.c
new file mode 100755
index 0000000..d8fe985
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/ebyte/ebyte_port.c
@@ -0,0 +1,99 @@
+/**
+  **********************************************************************************
+  * @file      ebyte_port.h
+  * @brief     EBYTEÇý¶¯¿âµÄÓ²¼þ½Ó¿Ú²ã ÓÉ¿Í»§×Ô¼ºÌṩIO½Ó¿Ú    
+  * @details   ÏêÇéÇë²Î¼û https://www.ebyte.com/       
+  * @author    JiangHeng     
+  * @date      2021-05-13     
+  * @version   1.0.0     
+  **********************************************************************************
+  * @copyright BSD License 
+  *            ³É¶¼ÒÚ°ÛÌصç×ӿƼ¼ÓÐÏÞ¹«Ë¾  
+  *   ______   ____   __     __  _______   ______ 
+  *  |  ____| |  _ \  \ \   / / |__   __| |  ____|
+  *  | |__    | |_) |  \ \_/ /     | |    | |__   
+  *  |  __|   |  _ <    \   /      | |    |  __|  
+  *  | |____  | |_) |    | |       | |    | |____ 
+  *  |______| |____/     |_|       |_|    |______| 
+  *
+  **********************************************************************************
+  */
+#include "ebyte_port.h"
+
+
+/*= !!!ÅäÖÃÄ¿±êÓ²¼þƽ̨ͷÎļþ =======================================*/
+#include "board.h"  //E15-EVB02 ÆÀ¹À°å
+/*==================================================================*/
+
+/* !
+ * @brief ÅäÖÃÄ¿±êÓ²¼þƽ̨SPI½Ó¿ÚÊÕ·¢º¯Êý 
+ * 
+ * @param send EBYTEÇý¶¯¿âÉϲãµ÷ÓÃÐèÒª´«ÊäµÄÊý¾Ý 1 Byte 
+ * @return SPI½ÓÊÕµÄÊý¾Ý 1 Byte
+ * @note µ±Ä¿±êƽ̨²ÉÓÃÓ²¼þSPI_NSSʱ£¬ÇëÅäÖà ebyte_conf.hÎļþ ¹Ø±ÕÇý¶¯¿âµÄÈí¼þ¿ØÖÆSPI_CS(NSS)
+ *       µ±Ä¿±êƽ̨²ÉÓÃÈí¼þSPI_NSSʱ£¬»¹Ðè¶îÍâÅäÖà Ebyte_Port_SpiCsIoControl() ¾ßÌåÇë²éÔĺ¯Êý˵Ã÷
+ */
+uint8e_t Ebyte_Port_SpiTransmitAndReceivce( uint8e_t send )
+{
+    uint8e_t result = 0;
+    
+    /* !±ØÐëÌṩ: SPI½Ó¿Ú */
+    result = Ebyte_BSP_SpiTransAndRecv( send );
+    
+    return result;
+}
+
+/* !
+ * @brief (¿ÉÑ¡)ÅäÖÃÄ¿±êÓ²¼þƽ̨SPI_CS(NSS)º¯Êý 
+ * 
+ * @param cmd EBYTEÇý¶¯¿âÉϲãÆÚÍûµÄ¿ØÖÆÖ¸Áî
+ *            @arg 0: ÆÚÍûCS(NSS)Òý½ÅÊä³öµÍµçƽÂß¼­ÐźŠEBYTEÄ£¿éSPI½Ó¿ÚΪµÍµçƽѡÖÐ
+ *            @arg 1: ÆÚÍûCS(NSS)Òý½ÅÊä³ö¸ßµçƽÂß¼­ÐźÅ
+ * @note µ±Ä¿±êƽ̨²ÉÓÃÓ²¼þSPI_NSSʱ£¬ÓÉÅäÖÃÎļþ¶¨Òå ´Ëº¯Êý½«ÎÞЧ
+ *       µ±Ä¿±êƽ̨²ÉÓÃÈí¼þSPI_NSSʱ£¬ÇëÅäÖô˺¯Êý
+ */
+void Ebyte_Port_SpiCsIoControl( uint8e_t cmd )
+{
+    if ( cmd == 1 )
+    {
+       /* !¿ÉÑ¡: SPI CS¿ØÖÆ ¸ßµçƽδѡÖÐ */  
+       Ebyte_BSP_RfSpiUnselected(); 
+    }
+    else
+    {
+       /* !¿ÉÑ¡: SPI CS¿ØÖÆ µÍµçƽѡÖÐ */  
+       Ebyte_BSP_RfSpiSelected( );
+    }
+}
+
+
+
+/* !
+ * @brief ÅäÖÃÄ¿±êÓ²¼þƽ̨ÑÓʱº¯Êý
+ * 
+ * @param time ÆÚÍûÑÓʱºÁÃë 
+ * @note Çë×¢ÒâʱÐò£¬Ä£¿é³õʼ»¯Ê±½«µ÷Óô˺¯Êý£¬Çë×¢ÒâÖжÏÊÇ·ñ»áÓ°Ïìµ½´Ëº¯Êý
+ */
+void Ebyte_Port_DelayMs( uint16e_t time )
+{
+    /* !±ØÐëÌṩ: ÑÓʱº¯Êý */
+  
+    uint16e_t i,n;
+    
+    while(time--)//ÕâÀïʾ·¶ÁËSTM8L 16MʱÖÓÇ°ÌáϵĴÖÂÔÈí¼þÑÓʱ 
+    {
+        for(i=900;i>0;i--)
+        {
+              for( n=1 ;n>0 ;n--)
+              {
+                  asm("nop"); 
+                  asm("nop");
+                  asm("nop");
+                  asm("nop");
+              }
+        }
+    }    
+}
+
+
+
diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/ebyte/ebyte_port.h b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/ebyte/ebyte_port.h
new file mode 100755
index 0000000..1ba9e60
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/ebyte/ebyte_port.h
@@ -0,0 +1,28 @@
+#include "ebyte_conf.h"
+#include "stm8l15x.h"
+//typedef  unsigned  char   uint8e_t;
+//typedef  unsigned  short  uint16e_t;
+//typedef  unsigned  long   uint32e_t;
+//
+//typedef  signed char     int8e_t;
+//typedef  signed short    int16e_t;
+//typedef  signed long     int32e_t;
+
+#define uint8e_t        uint8_t
+#define uint16e_t        uint16_t
+#define uint32e_t        uint32_t
+#define int8e_t        int8_t
+#define int16e_t        int16_t
+#define int32e_t        int32_t
+
+void Ebyte_Port_RstIoControl( uint8e_t cmd );
+void Ebyte_Port_TxenIoControl( uint8e_t cmd );
+void Ebyte_Port_RxenIoControl( uint8e_t cmd );
+void Ebyte_Port_DelayMs( uint16e_t time );
+void Ebyte_Port_SpiCsIoControl( uint8e_t cmd );
+
+uint8e_t Ebyte_Port_BusyIoRead( void );
+uint8e_t Ebyte_Port_SpiTransmitAndReceivce( uint8e_t send );
+
+
+
diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/main.c b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/main.c
new file mode 100755
index 0000000..4483984
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/main.c
@@ -0,0 +1,229 @@
+/**
+  **********************************************************************************
+  * @file      main.c
+  * @brief     E15-EVB02 ÆÀ¹À°å¹Ì¼þ
+  * @details   ±¾Àý³ÌΪ: ´®¿ÚÎÞÏß͸´«Ê¾Àý  ÏêÇéÇë²Î¼û https://www.ebyte.com/
+  * @author    yxw
+  * @date      2023-12-25
+  * @version   1.0.0
+  **********************************************************************************
+  * @copyright BSD License
+  *            ³É¶¼ÒÚ°ÛÌصç×ӿƼ¼ÓÐÏÞ¹«Ë¾
+  *   ______   ____   __     __  _______   ______
+  *  |  ____| |  _ \  \ \   / / |__   __| |  ____|
+  *  | |__    | |_) |  \ \_/ /     | |    | |__
+  *  |  __|   |  _ <    \   /      | |    |  __|
+  *  | |____  | |_) |    | |       | |    | |____
+  *  |______| |____/     |_|       |_|    |______|
+  *
+  **********************************************************************************
+  */
+
+#include "ebyte_core.h"
+#include "ebyte_kfifo.h"
+#include "ebyte_debug.h"
+    
+void Task_Transmit( void );
+void Task_Button( void );
+
+/* ´®¿Ú Êý¾Ý´æ´¢¶ÓÁÐ */
+Ebyte_FIFO_t hfifo;
+
+/* ´®¿Ú Ö¡½ÓÊÕÍê³É±êʶ */
+uint8_t Uart_isRecvReady = 0;
+
+/* ´®¿Ú FIFO¼ì²é±êʶ */
+uint8_t FIFO_isTimeCheckReady = 0;
+
+/* ´®¿Ú ×Ô¶¨ÒåÊÕ/·¢»º´æ */
+uint8_t TxBuffer[64] = {0};
+uint8_t RxBuffer[64] = {0};
+uint8_t PcEchoBuffer[20] = {0};
+
+uint8_t BufferPing[5] = {'p', 'i', 'n', 'g'};
+uint8_t BufferPong[5] = {'p', 'o', 'n', 'g'};
+
+/* ´®¿Ú FIFO¼ì²é±êʶ */
+uint8_t Callback_isPingCheckReady = 0;
+
+/* ×Ô¼ìģʽ ±êʶ */
+uint8_t PC_isConnected = 0;
+
+static BSP_BTN_EVENT_t BTN_Event;
+
+
+/* !
+ * @brief Ö÷º¯Êý
+ */
+int main( void )
+{
+    /* °åÔØÓ²¼þ×ÊÔ´ ³õʼ»¯ */
+    Ebyte_BSP_Init();
+
+    /* (¿ÉÑ¡) ´®¿ÚÖжϽÓÊÕFIFO ¿É¸ù¾ÝÐèÒª×ÔÐд¦Àí */
+    Ebyte_FIFO_Init( &hfifo, EBYTE_FIFO_SIZE );
+
+    /* EBYTE ÎÞÏßÄ£¿é³õʼ»¯ */
+    Ebyte_RF.Init();
+     /* ÆôÓÃÎÞÏßÄ£¿é½ÓÊÕ */
+    Ebyte_RF.EnterReceiveMode( 0 );   
+    /* MCU ¿ªÈ«¾ÖÖÐ¶Ï */
+    Ebyte_BSP_GlobalIntEnable();
+
+    DEBUG( "Start PingPong.....\r\n" );
+    DEBUG( "Please push button1 or button2.....\r\n" );
+    
+    while( 1 )
+    {
+        /* °´¼üʼþÏìÓ¦ */
+        Task_Button();
+
+        /* ÈÎÎñ:¼ì²â´®¿ÚÊý¾Ý²¢ÎÞÏß·¢ËÍ ¿Í»§Çë°´Ðè×Ô¶¨Òå */
+        Task_Transmit();
+
+        /* ÈÎÎñ:EBYTEÇý¶¯¿â±ØÐëµÄÖÜÆÚÖ´ÐÐÈÎÎñ  ¿Í»§ÎÞÐèÐÞ¸Ä */
+        Ebyte_RF.StartPollTask();
+       
+    }
+
+}
+
+/* !
+ * @brief  ÂÖѯÈÎÎñ ´®¿Ú½ÓÊÕµÄÊý¾Ýͨ¹ýÄ£¿é·¢ËÍ
+ *
+ * @note ½¨Òé¿Í»§½«ÐèÒª·¢Ë͵ÄÊý¾Ý½øÐÐ×é°ü´¦Àí£¬·ñÔòÐèÒª¿¼ÂǶîÍâµÄÎÞÏß´«Ê俪Ïú
+ *       ×¢ÒâÎÞÏßÄ£¿éµÄģʽÇл»£¬Ò»°ãÇé¿öÏ¿ÉÒÔ´¦ÓÚ½ÓÊÕ/ÐÝÃß/ÖÜÆÚÐÝÃß  ´ËʾÀý¹ý³ÌΪ: ½ÓÊÕģʽ->·¢ËÍģʽ->½ÓÊÕģʽ
+ */
+void Task_Transmit( void )
+{
+    uint16_t length = 0;
+    uint8_t pcEchoLength = 0;
+    uint8_t pongLength = 0;
+
+    /* ÊÇ·ñÓÐÊý¾ÝÐèÒªÎÞÏß´«Êä (À´×Ô´®¿Ú½ÓÊÕFIFO»º´æ) */
+    Ebyte_FIFO_GetDataLength( &hfifo, &length );
+
+    /* Éæ¼°µ½Òì²½ÖжÏ,ÕâÀï¼òµ¥Ê¾·¶ ÅжÏÁ½ÖÖÌõ¼þ
+       1; ´®¿ÚFIFOÖÐÓÐÊý¾ÝÇÒÒѾ­ÓÐÍêÕû½ÓÊÕµÄÖ¡£¬´ËʱÆôÓÃÎÞÏß·¢ËÍ( ²ÉÓÃʱ¼ä¶ÏÖ¡·½Ê½,Á¬Ðø´«ÊäʱµÍÓÚÅжÏʱ¼ä»áµ¼ÖÂÊý¾ÝÕ³°ü Çë¸ù¾Ý¾ßÌåÏîÄ¿×ÔÐп¼ÂÇÖ¡ÅÐ¶Ï )
+       2: ´®¿ÚFIFOÖÐÓÐÊý¾Ýµ«´®¿ÚÒѾ­Í˳öÁ˽ÓÊÕ״̬£¬³¬Ê±¼ì²âÌõ¼þ³ÉÁ¢ ( »áµ¼ÖÂFIFOÊ£Óàδ·¢ËÍÊý¾Ý±»´ò°üÎÞÏß·¢ËÍ Çë¸ù¾Ý¾ßÌåÏîÄ¿×ÔÐп¼ÂÇÖ¡ÅÐ¶Ï )*/
+    if( ( length != 0 && Uart_isRecvReady ) || ( length != 0 && FIFO_isTimeCheckReady ) )
+    {
+        Ebyte_BSP_LedControl( BSP_LED_1, ON );
+
+        /* ¶ÁÈ¡FIFO Êý¾Ý·ÅÈëTxBuffer */
+        Ebyte_FIFO_Read( &hfifo, TxBuffer, length );
+
+        /* PCÌØÊâÖ¸ÁîÏìÓ¦ */
+        if( Ebyte_DEBUG_CommandEcho( TxBuffer,length, PcEchoBuffer, &pcEchoLength ) )
+        {
+            Ebyte_BSP_UartTransmit( PcEchoBuffer , pcEchoLength); 
+        }
+        /* ·ÇÌØÊâÖ¸ÁîÔòÎÞÏß͸´« */
+        else
+        {
+            /* ÆôÓÃÎÞÏßÄ£¿é½øÐз¢ËÍ  */
+            Ebyte_RF.Send( TxBuffer, length, 0 );
+
+            /* ÆôÓÃÎÞÏßÄ£¿é¼ÌÐø½ÓÊÕ */
+            Ebyte_RF.EnterReceiveMode( 0 );          
+        }
+        
+        /* ÿ·¢ÍêÒ»Ö¡¾Í¼õÉÙÖ¡¼ÆÊý ´®¿ÚÖжϿÉÄÜÒѾ­Ð´ÈëÁ˶àÖ¡ */
+        if( Uart_isRecvReady )  Uart_isRecvReady --;
+        if( FIFO_isTimeCheckReady ) FIFO_isTimeCheckReady = 0;
+
+        Ebyte_BSP_LedControl( BSP_LED_1, OFF );
+    }
+    
+    /* ½ÓÊÕÍê³É»Øµ÷º¯Êý¼ì²âµ½ÁË ping ÃüÁî »Ø¸´ pong */
+    if( Callback_isPingCheckReady )
+    {   
+        if( PC_isConnected )
+        {
+            pongLength = 5;
+        }else{
+            DEBUG( "\r\n Echo : pong \r\n" );
+            pongLength = 4;
+        }
+        
+        /* ÆôÓÃÎÞÏßÄ£¿é½øÐз¢ËÍ  */
+        Ebyte_RF.Send( BufferPong, pongLength, 0 );
+
+        /* ÆôÓÃÎÞÏßÄ£¿é¼ÌÐø½ÓÊÕ */
+        Ebyte_RF.EnterReceiveMode( 0 );   
+        
+        Callback_isPingCheckReady = 0;
+    }
+}
+
+/* !
+ * @brief °´¼üʼþÏìÓ¦
+ */
+void Task_Button( void )
+{
+    uint8_t pcEchoLength = 0;
+    uint8_t pingLength = 0;
+    
+    if( ! Ebyte_BTN_FIFO_Pop( &BSP_BTN_FIFO, &BTN_Event ) )
+    {
+        switch( BTN_Event )
+        {
+        /* °´¼ü1 ¶Ì°´ */
+        case BTN_1_SHORT: 
+            Ebyte_BSP_LedControl( BSP_LED_1, ON );
+            
+            if( PC_isConnected )
+            {
+               /* ֪ͨPC */
+                Ebyte_DEBUG_CommandEcho( (uint8_t*)SimulatedCommandsButton1, EBYTE_CMD_PACKAGE_LENGTH , PcEchoBuffer, &pcEchoLength );
+                Ebyte_BSP_UartTransmit( PcEchoBuffer , pcEchoLength); 
+                BufferPing[4] = 0x01;
+                pingLength = 5;
+            }else
+            {
+                DEBUG( "\r\n Send Command : ping \r\n" );
+                pingLength = 4;
+            }
+            
+            /* ·¢ËÍ ping */
+            Ebyte_RF.Send( BufferPing, pingLength, 0 );
+            Ebyte_RF.EnterReceiveMode( 0 );
+            
+            Ebyte_BSP_LedControl( BSP_LED_1, OFF );
+            break;
+        /* °´¼ü1 ³¤°´ */    
+        case BTN_1_LONG:
+            Ebyte_BSP_LedControl( BSP_LED_1, TOGGLE );
+            break;
+        /* °´¼ü2 ¶Ì°´ */     
+        case BTN_2_SHORT:
+            Ebyte_BSP_LedControl( BSP_LED_2, ON );
+            if( PC_isConnected )
+            {
+               /* ֪ͨPC */
+                Ebyte_DEBUG_CommandEcho( (uint8_t*)SimulatedCommandsButton2, EBYTE_CMD_PACKAGE_LENGTH , PcEchoBuffer, &pcEchoLength );
+                Ebyte_BSP_UartTransmit( PcEchoBuffer , pcEchoLength); 
+                BufferPing[4] = 0x02;
+                pingLength = 5;
+            }else
+            {
+                DEBUG( "\r\n Send Command : ping \r\n" );
+                pingLength = 4;
+            }
+            
+            /* ·¢ËÍ ping */
+            Ebyte_RF.Send( BufferPing, pingLength, 0 );
+            Ebyte_RF.EnterReceiveMode( 0 );
+            
+            Ebyte_BSP_LedControl( BSP_LED_2, OFF );  
+            break;
+        /* °´¼ü2 ³¤°´ */     
+        case BTN_2_LONG:
+            Ebyte_BSP_LedControl( BSP_LED_2, TOGGLE );
+            break;
+        default :
+            break;
+        }
+    }
+}
+
diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/project.dep b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/project.dep
new file mode 100755
index 0000000..5fcdfdd
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/project.dep
@@ -0,0 +1,1552 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<project>
+    <fileVersion>2</fileVersion>
+    <fileChecksum>2357017305</fileChecksum>
+    <configuration>
+        <name>Debug</name>
+        <outputs>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_spi.c</file>
+            <file>$PROJ_DIR$\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx\cmt2310a_410mhz.c</file>
+            <file>$PROJ_DIR$\..\..\..\2_Ebyte_Board_Support\E15-EVB02\board.c</file>
+            <file>$PROJ_DIR$\..\..\..\2_Ebyte_Board_Support\E15-EVB02\board_button.c</file>
+            <file>$PROJ_DIR$\..\..\..\2_Ebyte_Board_Support\E15-EVB02\board_mini_printf.c</file>
+            <file>$PROJ_DIR$\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx\cmt2310a_433mhz.c</file>
+            <file>$PROJ_DIR$\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx\radio_spi.c</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_lcd.c</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_pwr.c</file>
+            <file>$PROJ_DIR$\ebyte\ebyte_core.c</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_adc.c</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_clk.c</file>
+            <file>$PROJ_DIR$\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx\radio_mac.c</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_rst.c</file>
+            <file>$PROJ_DIR$\ebyte\ebyte_callback.c</file>
+            <file>$PROJ_DIR$\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx\radio_phy.c</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_irtim.c</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_iwdg.c</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_rtc.c</file>
+            <file>$PROJ_DIR$\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx\cmt2310a_868mhz.c</file>
+            <file>$PROJ_DIR$\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx\radio_hal.c</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_comp.c</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_dac.c</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_dma.c</file>
+            <file>$PROJ_DIR$\ebyte\ebyte_port.c</file>
+            <file>$PROJ_DIR$\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx\radio.c</file>
+            <file>$PROJ_DIR$\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx\cmt2310a_915mhz.c</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_aes.c</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_flash.c</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_beep.c</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_exti.c</file>
+            <file>$PROJ_DIR$\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx\ebyte_e48x.c</file>
+            <file>$PROJ_DIR$\ebyte\ebyte_conf.h</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_gpio.c</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_i2c.c</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\inc\stm8l15x_exti.h</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\inc\stm8l15x_dma.h</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\inc\stm8l15x_syscfg.h</file>
+            <file>$TOOLKIT_DIR$\inc\c\intrinsics.h</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\inc\stm8l15x_irtim.h</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\inc\stm8l15x_rst.h</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\inc\stm8l15x_tim2.h</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\inc\stm8l15x_tim4.h</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\inc\stm8l15x_rtc.h</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\inc\stm8l15x_gpio.h</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\inc\stm8l15x_usart.h</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\inc\stm8l15x_beep.h</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\stm8l15x_conf.h</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\inc\stm8l15x_tim1.h</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\inc\stm8l15x.h</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\inc\stm8l15x_pwr.h</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\inc\stm8l15x_itc.h</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\inc\stm8l15x_spi.h</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\inc\stm8l15x_wwdg.h</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\inc\stm8l15x_dac.h</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\inc\stm8l15x_flash.h</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\inc\stm8l15x_iwdg.h</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\inc\stm8l15x_aes.h</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\inc\stm8l15x_adc.h</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\inc\stm8l15x_lcd.h</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\inc\stm8l15x_tim3.h</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\inc\stm8l15x_tim5.h</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\inc\stm8l15x_clk.h</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\inc\stm8l15x_i2c.h</file>
+            <file>$PROJ_DIR$\Debug\Obj\radio_phy.pbi</file>
+            <file>$PROJ_DIR$\Debug\Obj\stm8l15x_dac.pbi</file>
+            <file>$PROJ_DIR$\Debug\Obj\stm8l15x_aes.pbi</file>
+            <file>$PROJ_DIR$\Debug\Obj\stm8l15x_clk.pbi</file>
+            <file>$PROJ_DIR$\Debug\Obj\stm8l15x_pwr.pbi</file>
+            <file>$PROJ_DIR$\Debug\Obj\stm8l15x_irtim.pbi</file>
+            <file>$PROJ_DIR$\Debug\Obj\stm8l15x_rtc.pbi</file>
+            <file>$PROJ_DIR$\Debug\Obj\radio_hal.pbi</file>
+            <file>$PROJ_DIR$\Debug\Obj\stm8l15x_iwdg.pbi</file>
+            <file>$PROJ_DIR$\Debug\Obj\ebyte_e48x.pbi</file>
+            <file>$PROJ_DIR$\Debug\Obj\stm8l15x_irtim.o</file>
+            <file>$PROJ_DIR$\..\..\..\2_Ebyte_Board_Support\E15-EVB02\board.h</file>
+            <file>$PROJ_DIR$\Debug\Obj\stm8l15x_beep.pbi</file>
+            <file>$PROJ_DIR$\Debug\Obj\stm8l15x_wfe.o</file>
+            <file>$PROJ_DIR$\..\..\..\2_Ebyte_Board_Support\E15-EVB02\board_mini_printf.h</file>
+            <file>$PROJ_DIR$\Debug\Obj\stm8l15x_comp.pbi</file>
+            <file>$PROJ_DIR$\Debug\Obj\radio_mac.pbi</file>
+            <file>$PROJ_DIR$\Debug\Obj\ebyte_port.pbi</file>
+            <file>$PROJ_DIR$\Debug\Obj\stm8l15x_gpio.pbi</file>
+            <file>$PROJ_DIR$\Debug\Obj\stm8l15x_flash.o</file>
+            <file>$PROJ_DIR$\Debug\Obj\ebyte_core.pbi</file>
+            <file>$PROJ_DIR$\Debug\Obj\cmt2310a_433mhz.pbi</file>
+            <file>$PROJ_DIR$\Debug\Obj\radio.pbi</file>
+            <file>$PROJ_DIR$\Debug\Obj\stm8l15x_it.o</file>
+            <file>$PROJ_DIR$\Debug\Obj\stm8l15x_it.pbi</file>
+            <file>$PROJ_DIR$\Debug\Obj\cmt2310a_868mhz.pbi</file>
+            <file>$PROJ_DIR$\Debug\Obj\stm8l15x_tim4.pbi</file>
+            <file>$PROJ_DIR$\Debug\Obj\stm8l15x_tim5.pbi</file>
+            <file>$PROJ_DIR$\Debug\Obj\stm8l15x_wfe.pbi</file>
+            <file>$PROJ_DIR$\Debug\Obj\ebyte_debug.pbi</file>
+            <file>$PROJ_DIR$\Debug\Obj\stm8l15x_i2c.pbi</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\inc\stm8l15x_wfe.h</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\inc\stm8l15x_comp.h</file>
+            <file>$PROJ_DIR$\Debug\Obj\stm8l15x_dma.pbi</file>
+            <file>$PROJ_DIR$\Debug\Obj\stm8l15x_tim1.pbi</file>
+            <file>$PROJ_DIR$\Debug\Obj\cmt2310a_915mhz.pbi</file>
+            <file>$PROJ_DIR$\Debug\Obj\project.pbd</file>
+            <file>$PROJ_DIR$\Debug\Obj\stm8l15x_adc.pbi</file>
+            <file>$PROJ_DIR$\Debug\Obj\stm8l15x_rst.pbi</file>
+            <file>$PROJ_DIR$\Debug\Obj\ebyte_callback.pbi</file>
+            <file>$PROJ_DIR$\Debug\Obj\radio_spi.pbi</file>
+            <file>$PROJ_DIR$\Debug\Obj\stm8l15x_exti.pbi</file>
+            <file>$PROJ_DIR$\Debug\Exe\project.hex</file>
+            <file>$PROJ_DIR$\Debug\Obj\main.pbi</file>
+            <file>$PROJ_DIR$\Debug\Obj\stm8l15x_syscfg.pbi</file>
+            <file>$PROJ_DIR$\Debug\Exe\project.out</file>
+            <file>$PROJ_DIR$\Debug\Obj\stm8l15x_lcd.pbi</file>
+            <file>$PROJ_DIR$\Debug\Obj\stm8l15x_tim2.pbi</file>
+            <file>$PROJ_DIR$\Debug\Obj\stm8l15x_wwdg.pbi</file>
+            <file>$PROJ_DIR$\Debug\Obj\stm8l15x_tim3.pbi</file>
+            <file>$PROJ_DIR$\Debug\Obj\ebyte_kfifo.pbi</file>
+            <file>$PROJ_DIR$\Debug\Obj\stm8l15x_spi.pbi</file>
+            <file>$PROJ_DIR$\Debug\Obj\stm8l15x_flash.pbi</file>
+            <file>$PROJ_DIR$\Debug\Obj\stm8l15x_usart.pbi</file>
+            <file>$PROJ_DIR$\Debug\Obj\ebyte_kfifo.o</file>
+            <file>$PROJ_DIR$\Debug\Obj\stm8l15x_wwdg.o</file>
+            <file>$PROJ_DIR$\Debug\Obj\stm8l15x_comp.o</file>
+            <file>$PROJ_DIR$\Debug\Obj\main.o</file>
+            <file>$PROJ_DIR$\Debug\Obj\stm8l15x_tim4.o</file>
+            <file>$PROJ_DIR$\Debug\Obj\stm8l15x_rst.o</file>
+            <file>$PROJ_DIR$\Debug\Obj\stm8l15x_i2c.o</file>
+            <file>$PROJ_DIR$\Debug\Obj\stm8l15x_spi.o</file>
+            <file>$PROJ_DIR$\Debug\Obj\stm8l15x_gpio.o</file>
+            <file>$PROJ_DIR$\Debug\Obj\stm8l15x_pwr.o</file>
+            <file>$PROJ_DIR$\Debug\Obj\board_mini_printf.o</file>
+            <file>$PROJ_DIR$\Debug\Obj\stm8l15x_tim5.o</file>
+            <file>$PROJ_DIR$\Debug\Obj\stm8l15x_tim1.o</file>
+            <file>$PROJ_DIR$\Debug\Obj\ebyte_debug.o</file>
+            <file>$PROJ_DIR$\Debug\Obj\radio.o</file>
+            <file>$PROJ_DIR$\Debug\Obj\stm8l15x_tim3.o</file>
+            <file>$PROJ_DIR$\Debug\Obj\stm8l15x_rtc.o</file>
+            <file>$PROJ_DIR$\Debug\Obj\stm8l15x_dac.o</file>
+            <file>$PROJ_DIR$\Debug\Obj\board.o</file>
+            <file>$PROJ_DIR$\Debug\Obj\cmt2310a_915mhz.o</file>
+            <file>$PROJ_DIR$\Debug\Obj\board.pbi</file>
+            <file>$PROJ_DIR$\Debug\Obj\stm8l15x_tim2.o</file>
+            <file>$PROJ_DIR$\Debug\Obj\board_mini_printf.pbi</file>
+            <file>$PROJ_DIR$\Debug\Obj\stm8l15x_dma.o</file>
+            <file>$PROJ_DIR$\Debug\Obj\stm8l15x_lcd.o</file>
+            <file>$PROJ_DIR$\Debug\Obj\stm8l15x_exti.o</file>
+            <file>$PROJ_DIR$\Debug\Obj\stm8l15x_syscfg.o</file>
+            <file>$PROJ_DIR$\Debug\Obj\board_button.pbi</file>
+            <file>$PROJ_DIR$\Debug\Obj\stm8l15x_usart.o</file>
+            <file>$PROJ_DIR$\Debug\Obj\stm8l15x_clk.o</file>
+            <file>$PROJ_DIR$\Debug\Obj\cmt2310a_868mhz.o</file>
+            <file>$PROJ_DIR$\Debug\Obj\stm8l15x_iwdg.o</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_wfe.c</file>
+            <file>$PROJ_DIR$\Debug\Obj\ebyte_e48x.o</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_tim3.c</file>
+            <file>$PROJ_DIR$\Debug\Obj\radio_mac.o</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_usart.c</file>
+            <file>$PROJ_DIR$\Debug\Obj\ebyte_callback.o</file>
+            <file>$PROJ_DIR$\Debug\Obj\cmt2310a_410mhz.pbi</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_tim2.c</file>
+            <file>$PROJ_DIR$\stm8l15x_it.c</file>
+            <file>$PROJ_DIR$\Debug\Obj\ebyte_core.o</file>
+            <file>$PROJ_DIR$\Debug\Obj\stm8l15x_adc.o</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_wwdg.c</file>
+            <file>$PROJ_DIR$\Debug\Obj\radio_hal.o</file>
+            <file>$PROJ_DIR$\..\..\..\1_Middleware\Kfifo\ebyte_kfifo.c</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_tim1.c</file>
+            <file>$PROJ_DIR$\Debug\Obj\radio_spi.o</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_tim5.c</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_tim4.c</file>
+            <file>$PROJ_DIR$\Debug\Obj\stm8l15x_aes.o</file>
+            <file>$PROJ_DIR$\Debug\Obj\cmt2310a_410mhz.o</file>
+            <file>$PROJ_DIR$\Debug\Obj\board_button.o</file>
+            <file>$PROJ_DIR$\Debug\Obj\ebyte_port.o</file>
+            <file>$PROJ_DIR$\Debug\Obj\stm8l15x_beep.o</file>
+            <file>$PROJ_DIR$\main.c</file>
+            <file>$PROJ_DIR$\Debug\Obj\cmt2310a_433mhz.o</file>
+            <file>$PROJ_DIR$\..\..\..\1_Middleware\Produce\ebyte_debug.c</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_syscfg.c</file>
+            <file>$PROJ_DIR$\Debug\Obj\radio_phy.o</file>
+        </outputs>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_spi.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCSTM8</name>
+                    <file> 125</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 115</file>
+                </tool>
+            </outputs>
+        </file>
+        <file>
+            <name>[ROOT_NODE]</name>
+            <outputs>
+                <tool>
+                    <name>ILINK</name>
+                    <file> 109</file>
+                </tool>
+            </outputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx\cmt2310a_410mhz.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCSTM8</name>
+                    <file> 169</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 156</file>
+                </tool>
+            </outputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\2_Ebyte_Board_Support\E15-EVB02\board.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCSTM8</name>
+                    <file> 136</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 138</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 58 49 40 55 61 96 51 48 38 47 46 36 63 59 52 60 95 32 78 57 62 54 35 44 39 56 50 43 37 41 42 45 53 75</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\2_Ebyte_Board_Support\E15-EVB02\board_button.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCSTM8</name>
+                    <file> 170</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 145</file>
+                </tool>
+            </outputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\2_Ebyte_Board_Support\E15-EVB02\board_mini_printf.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCSTM8</name>
+                    <file> 128</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 140</file>
+                </tool>
+            </outputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx\cmt2310a_433mhz.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCSTM8</name>
+                    <file> 174</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 85</file>
+                </tool>
+            </outputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx\radio_spi.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCSTM8</name>
+                    <file> 165</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 104</file>
+                </tool>
+            </outputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_lcd.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCSTM8</name>
+                    <file> 142</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 110</file>
+                </tool>
+            </outputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_pwr.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCSTM8</name>
+                    <file> 127</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 68</file>
+                </tool>
+            </outputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\ebyte\ebyte_core.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCSTM8</name>
+                    <file> 159</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 84</file>
+                </tool>
+            </outputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_adc.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCSTM8</name>
+                    <file> 160</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 101</file>
+                </tool>
+            </outputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_clk.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCSTM8</name>
+                    <file> 147</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 67</file>
+                </tool>
+            </outputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx\radio_mac.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCSTM8</name>
+                    <file> 153</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 80</file>
+                </tool>
+            </outputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_rst.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCSTM8</name>
+                    <file> 123</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 102</file>
+                </tool>
+            </outputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\ebyte\ebyte_callback.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCSTM8</name>
+                    <file> 155</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 103</file>
+                </tool>
+            </outputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx\radio_phy.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCSTM8</name>
+                    <file> 177</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 64</file>
+                </tool>
+            </outputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_irtim.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCSTM8</name>
+                    <file> 74</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 69</file>
+                </tool>
+            </outputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_iwdg.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCSTM8</name>
+                    <file> 149</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 72</file>
+                </tool>
+            </outputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_rtc.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCSTM8</name>
+                    <file> 134</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 70</file>
+                </tool>
+            </outputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx\cmt2310a_868mhz.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCSTM8</name>
+                    <file> 148</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 89</file>
+                </tool>
+            </outputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx\radio_hal.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCSTM8</name>
+                    <file> 162</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 71</file>
+                </tool>
+            </outputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_comp.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCSTM8</name>
+                    <file> 120</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 79</file>
+                </tool>
+            </outputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_dac.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCSTM8</name>
+                    <file> 135</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 65</file>
+                </tool>
+            </outputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_dma.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCSTM8</name>
+                    <file> 141</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 97</file>
+                </tool>
+            </outputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\ebyte\ebyte_port.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCSTM8</name>
+                    <file> 171</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 81</file>
+                </tool>
+            </outputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx\radio.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCSTM8</name>
+                    <file> 132</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 86</file>
+                </tool>
+            </outputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx\cmt2310a_915mhz.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCSTM8</name>
+                    <file> 137</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 99</file>
+                </tool>
+            </outputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_aes.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCSTM8</name>
+                    <file> 168</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 66</file>
+                </tool>
+            </outputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_flash.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCSTM8</name>
+                    <file> 83</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 116</file>
+                </tool>
+            </outputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_beep.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCSTM8</name>
+                    <file> 172</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 76</file>
+                </tool>
+            </outputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_exti.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCSTM8</name>
+                    <file> 143</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 105</file>
+                </tool>
+            </outputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx\ebyte_e48x.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCSTM8</name>
+                    <file> 151</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 73</file>
+                </tool>
+            </outputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_gpio.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCSTM8</name>
+                    <file> 126</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 82</file>
+                </tool>
+            </outputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_i2c.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCSTM8</name>
+                    <file> 124</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 94</file>
+                </tool>
+            </outputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\Debug\Exe\project.out</name>
+            <outputs>
+                <tool>
+                    <name>OBJCOPY</name>
+                    <file> 106</file>
+                </tool>
+            </outputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_wfe.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCSTM8</name>
+                    <file> 77</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 92</file>
+                </tool>
+            </outputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_tim3.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCSTM8</name>
+                    <file> 133</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 113</file>
+                </tool>
+            </outputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_usart.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCSTM8</name>
+                    <file> 146</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 117</file>
+                </tool>
+            </outputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_tim2.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCSTM8</name>
+                    <file> 139</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 111</file>
+                </tool>
+            </outputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\stm8l15x_it.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCSTM8</name>
+                    <file> 87</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 88</file>
+                </tool>
+            </outputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_wwdg.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCSTM8</name>
+                    <file> 119</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 112</file>
+                </tool>
+            </outputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\1_Middleware\Kfifo\ebyte_kfifo.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCSTM8</name>
+                    <file> 118</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 114</file>
+                </tool>
+            </outputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_tim1.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCSTM8</name>
+                    <file> 130</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 98</file>
+                </tool>
+            </outputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_tim5.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCSTM8</name>
+                    <file> 129</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 91</file>
+                </tool>
+            </outputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_tim4.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCSTM8</name>
+                    <file> 122</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 90</file>
+                </tool>
+            </outputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\main.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCSTM8</name>
+                    <file> 121</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 107</file>
+                </tool>
+            </outputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\1_Middleware\Produce\ebyte_debug.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCSTM8</name>
+                    <file> 131</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 93</file>
+                </tool>
+            </outputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_syscfg.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCSTM8</name>
+                    <file> 144</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 108</file>
+                </tool>
+            </outputs>
+        </file>
+    </configuration>
+    <configuration>
+        <name>Release</name>
+        <outputs>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_spi.c</file>
+            <file>$PROJ_DIR$\..\..\..\2_Ebyte_Board_Support\E15-EVB02\board.c</file>
+            <file>$PROJ_DIR$\..\..\..\2_Ebyte_Board_Support\E15-EVB02\board_button.c</file>
+            <file>$PROJ_DIR$\..\..\..\2_Ebyte_Board_Support\E15-EVB02\board_mini_printf.c</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_lcd.c</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_pwr.c</file>
+            <file>$PROJ_DIR$\ebyte\ebyte_core.c</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_adc.c</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_clk.c</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_itc.c</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_rst.c</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_irtim.c</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_iwdg.c</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_rtc.c</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_comp.c</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_dac.c</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_dma.c</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_aes.c</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_flash.c</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_beep.c</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_exti.c</file>
+            <file>$PROJ_DIR$\ebyte\ebyte_conf.h</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_gpio.c</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_i2c.c</file>
+            <file>$PROJ_DIR$\Release\Obj\stm8l15x_tim2.__cstat.et</file>
+            <file>$PROJ_DIR$\Release\Obj\stm8l15x_beep.pbi</file>
+            <file>$PROJ_DIR$\Release\Obj\stm8l15x_wwdg.__cstat.et</file>
+            <file>$PROJ_DIR$\Release\Obj\board_button.pbi</file>
+            <file>$PROJ_DIR$\Release\Obj\main.__cstat.et</file>
+            <file>$PROJ_DIR$\Release\Obj\stm8l15x_clk.__cstat.et</file>
+            <file>$PROJ_DIR$\Release\Obj\stm8l15x_lcd.__cstat.et</file>
+            <file>$PROJ_DIR$\ebyte\E22xMx\ebyte_port.h</file>
+            <file>$PROJ_DIR$\Release\Obj\stm8l15x_rst.pbi</file>
+            <file>$PROJ_DIR$\Release\Obj\stm8l15x_itc.__cstat.et</file>
+            <file>$PROJ_DIR$\Release\Obj\ebyte_e22x.pbi</file>
+            <file>$PROJ_DIR$\Release\Obj\stm8l15x_usart.__cstat.et</file>
+            <file>$PROJ_DIR$\Release\Obj\ebyte_core.pbi</file>
+            <file>$PROJ_DIR$\Release\Obj\board_mini_printf.pbi</file>
+            <file>$PROJ_DIR$\Release\Obj\ebyte_kfifo.__cstat.et</file>
+            <file>$PROJ_DIR$\Release\Obj\board.__cstat.et</file>
+            <file>$PROJ_DIR$\Release\Obj\board.pbi</file>
+            <file>$PROJ_DIR$\Release\Obj\stm8l15x_syscfg.__cstat.et</file>
+            <file>$PROJ_DIR$\Release\Obj\stm8l15x_aes.__cstat.et</file>
+            <file>$PROJ_DIR$\Release\Obj\stm8l15x_adc.__cstat.et</file>
+            <file>$PROJ_DIR$\Release\Obj\stm8l15x_tim1.pbi</file>
+            <file>$PROJ_DIR$\Release\Obj\stm8l15x_tim3.__cstat.et</file>
+            <file>$PROJ_DIR$\Release\Obj\stm8l15x_gpio.__cstat.et</file>
+            <file>$PROJ_DIR$\Release\Obj\stm8l15x_it.pbi</file>
+            <file>$PROJ_DIR$\Release\Exe\project.out</file>
+            <file>$PROJ_DIR$\Release\Obj\stm8l15x_itc.pbi</file>
+            <file>$PROJ_DIR$\Release\Obj\main.pbi</file>
+            <file>$PROJ_DIR$\Release\Obj\stm8l15x_dac.__cstat.et</file>
+            <file>$PROJ_DIR$\ebyte\E22xMx\ebyte_e22x.h</file>
+            <file>$PROJ_DIR$\Release\Obj\stm8l15x_pwr.pbi</file>
+            <file>$PROJ_DIR$\Release\Obj\ebyte_core.__cstat.et</file>
+            <file>$PROJ_DIR$\Release\Obj\stm8l15x_wfe.pbi</file>
+            <file>$PROJ_DIR$\Release\Obj\stm8l15x_tim5.__cstat.et</file>
+            <file>$PROJ_DIR$\Release\Obj\ebyte_callback.__cstat.et</file>
+            <file>$PROJ_DIR$\Release\Obj\stm8l15x_iwdg.pbi</file>
+            <file>$PROJ_DIR$\Release\Obj\stm8l15x_tim4.__cstat.et</file>
+            <file>$PROJ_DIR$\Release\Obj\stm8l15x_exti.pbi</file>
+            <file>$PROJ_DIR$\Release\Obj\stm8l15x_aes.pbi</file>
+            <file>$PROJ_DIR$\Release\Obj\stm8l15x_tim5.pbi</file>
+            <file>$PROJ_DIR$\Release\Obj\stm8l15x_usart.pbi</file>
+            <file>$PROJ_DIR$\Release\Obj\stm8l15x_beep.__cstat.et</file>
+            <file>$PROJ_DIR$\Release\Obj\stm8l15x_spi.__cstat.et</file>
+            <file>$PROJ_DIR$\Release\Obj\stm8l15x_clk.pbi</file>
+            <file>$PROJ_DIR$\Release\Obj\stm8l15x_comp.__cstat.et</file>
+            <file>$PROJ_DIR$\Release\Obj\stm8l15x_gpio.pbi</file>
+            <file>$PROJ_DIR$\Release\Obj\stm8l15x_wwdg.pbi</file>
+            <file>$PROJ_DIR$\Release\Obj\ebyte_port.__cstat.et</file>
+            <file>$PROJ_DIR$\Release\Obj\stm8l15x_lcd.pbi</file>
+            <file>$PROJ_DIR$\Release\Obj\stm8l15x_exti.__cstat.et</file>
+            <file>$PROJ_DIR$\Release\Obj\stm8l15x_dac.pbi</file>
+            <file>$PROJ_DIR$\Release\Obj\stm8l15x_tim3.pbi</file>
+            <file>$PROJ_DIR$\Release\Obj\stm8l15x_spi.pbi</file>
+            <file>$PROJ_DIR$\Release\Obj\stm8l15x_syscfg.pbi</file>
+            <file>$PROJ_DIR$\ebyte\E22xMx\ebyte_callback.h</file>
+            <file>$PROJ_DIR$\Release\Obj\stm8l15x_iwdg.__cstat.et</file>
+            <file>$PROJ_DIR$\Release\Obj\stm8l15x_irtim.pbi</file>
+            <file>$PROJ_DIR$\ebyte\E22xMx\ebyte_callback.c</file>
+            <file>$PROJ_DIR$\Release\Obj\ebyte_e22x.__cstat.et</file>
+            <file>$PROJ_DIR$\Release\Obj\stm8l15x_comp.pbi</file>
+            <file>$PROJ_DIR$\Release\Obj\board_button.__cstat.et</file>
+            <file>$PROJ_DIR$\Release\Obj\stm8l15x_i2c.__cstat.et</file>
+            <file>$PROJ_DIR$\Release\Obj\ebyte_callback.pbi</file>
+            <file>$PROJ_DIR$\ebyte\E22xMx\ebyte_port.c</file>
+            <file>$PROJ_DIR$\Release\Obj\stm8l15x_rtc.pbi</file>
+            <file>$PROJ_DIR$\ebyte\E22xMx\ebyte_e22x.c</file>
+            <file>$PROJ_DIR$\Release\Obj\stm8l15x_flash.pbi</file>
+            <file>$PROJ_DIR$\Release\Obj\stm8l15x_tim4.pbi</file>
+            <file>$PROJ_DIR$\Release\Obj\stm8l15x_it.__cstat.et</file>
+            <file>$PROJ_DIR$\Release\Obj\stm8l15x_tim2.pbi</file>
+            <file>$PROJ_DIR$\Release\Obj\stm8l15x_dma.pbi</file>
+            <file>$PROJ_DIR$\Release\Obj\stm8l15x_irtim.__cstat.et</file>
+            <file>$PROJ_DIR$\Release\Obj\board_mini_printf.__cstat.et</file>
+            <file>$PROJ_DIR$\Release\Obj\stm8l15x_flash.__cstat.et</file>
+            <file>$PROJ_DIR$\Release\Obj\stm8l15x_i2c.pbi</file>
+            <file>$PROJ_DIR$\Release\Obj\stm8l15x_adc.pbi</file>
+            <file>$PROJ_DIR$\Release\Obj\stm8l15x_rtc.__cstat.et</file>
+            <file>$PROJ_DIR$\Release\Obj\stm8l15x_pwr.__cstat.et</file>
+            <file>$PROJ_DIR$\Release\Obj\ebyte_port.pbi</file>
+            <file>$PROJ_DIR$\Release\Obj\ebyte_kfifo.pbi</file>
+            <file>$PROJ_DIR$\Release\Obj\stm8l15x_rst.__cstat.et</file>
+            <file>$PROJ_DIR$\Release\Obj\stm8l15x_tim1.__cstat.et</file>
+            <file>$PROJ_DIR$\Release\Obj\stm8l15x_wfe.__cstat.et</file>
+            <file>$PROJ_DIR$\Release\Obj\stm8l15x_dma.__cstat.et</file>
+            <file>$PROJ_DIR$\ebyte\ebyte_core.h</file>
+            <file>$TOOLKIT_DIR$\inc\c\xencoding_limits.h</file>
+            <file>$TOOLKIT_DIR$\inc\c\ycheck.h</file>
+            <file>$PROJ_DIR$\..\..\..\1_Middleware\Kfifo\ebyte_kfifo.h</file>
+            <file>$TOOLKIT_DIR$\inc\c\DLib_Product.h</file>
+            <file>$PROJ_DIR$\..\..\..\2_Ebyte_Board_Support\E15-EVB02\board.h</file>
+            <file>$TOOLKIT_DIR$\inc\c\stdarg.h</file>
+            <file>$TOOLKIT_DIR$\inc\c\DLib_Threads.h</file>
+            <file>$PROJ_DIR$\..\..\..\2_Ebyte_Board_Support\E15-EVB02\board_mini_printf.h</file>
+            <file>$TOOLKIT_DIR$\inc\c\DLib_Defaults.h</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_wfe.c</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_tim3.c</file>
+            <file>$TOOLKIT_DIR$\lib\dlstm8smn.h</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_usart.c</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_tim2.c</file>
+            <file>$PROJ_DIR$\stm8l15x_it.c</file>
+            <file>$PROJ_DIR$\stm8l15x_it.h</file>
+            <file>$TOOLKIT_DIR$\inc\c\yvals.h</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_wwdg.c</file>
+            <file>$PROJ_DIR$\..\..\..\1_Middleware\Kfifo\ebyte_kfifo.c</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_tim1.c</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_tim5.c</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_tim4.c</file>
+            <file>$PROJ_DIR$\main.c</file>
+            <file>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_syscfg.c</file>
+        </outputs>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_spi.c</name>
+            <outputs>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 65</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 75</file>
+                </tool>
+            </outputs>
+        </file>
+        <file>
+            <name>[ROOT_NODE]</name>
+            <outputs>
+                <tool>
+                    <name>ILINK</name>
+                    <file> 48</file>
+                </tool>
+            </outputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\2_Ebyte_Board_Support\E15-EVB02\board.c</name>
+            <outputs>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 39</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 40</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCSTM8</name>
+                    <file> 112</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 112 115</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\2_Ebyte_Board_Support\E15-EVB02\board_button.c</name>
+            <outputs>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 83</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 27</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCSTM8</name>
+                    <file> 112</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 115 112</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\2_Ebyte_Board_Support\E15-EVB02\board_mini_printf.c</name>
+            <outputs>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 95</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 37</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCSTM8</name>
+                    <file> 113 109 124 116 119 111 108 114</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 119 115 124 109 108 111 113 116 114</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_lcd.c</name>
+            <outputs>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 30</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 71</file>
+                </tool>
+            </outputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_pwr.c</name>
+            <outputs>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 100</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 53</file>
+                </tool>
+            </outputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\ebyte\ebyte_core.c</name>
+            <outputs>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 54</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 36</file>
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+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCSTM8</name>
+                    <file> 107 21</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 107 21</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_adc.c</name>
+            <outputs>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 43</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 98</file>
+                </tool>
+            </outputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_clk.c</name>
+            <outputs>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 29</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 66</file>
+                </tool>
+            </outputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_itc.c</name>
+            <outputs>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 33</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 49</file>
+                </tool>
+            </outputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_rst.c</name>
+            <outputs>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 103</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 32</file>
+                </tool>
+            </outputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_irtim.c</name>
+            <outputs>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 94</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 79</file>
+                </tool>
+            </outputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_iwdg.c</name>
+            <outputs>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 78</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 58</file>
+                </tool>
+            </outputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_rtc.c</name>
+            <outputs>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 99</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 87</file>
+                </tool>
+            </outputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_comp.c</name>
+            <outputs>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 67</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 82</file>
+                </tool>
+            </outputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_dac.c</name>
+            <outputs>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 51</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 73</file>
+                </tool>
+            </outputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_dma.c</name>
+            <outputs>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 106</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 93</file>
+                </tool>
+            </outputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_aes.c</name>
+            <outputs>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 42</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 61</file>
+                </tool>
+            </outputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_flash.c</name>
+            <outputs>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 96</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 89</file>
+                </tool>
+            </outputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_beep.c</name>
+            <outputs>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 64</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 25</file>
+                </tool>
+            </outputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_exti.c</name>
+            <outputs>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 72</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 60</file>
+                </tool>
+            </outputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_gpio.c</name>
+            <outputs>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 46</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 68</file>
+                </tool>
+            </outputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_i2c.c</name>
+            <outputs>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 84</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 97</file>
+                </tool>
+            </outputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\ebyte\E22xMx\ebyte_callback.c</name>
+            <outputs>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 57</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 85</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCSTM8</name>
+                    <file> 77 31</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 77 31</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\ebyte\E22xMx\ebyte_port.c</name>
+            <outputs>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 70</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 101</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCSTM8</name>
+                    <file> 31</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 31</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\ebyte\E22xMx\ebyte_e22x.c</name>
+            <outputs>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 81</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 34</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCSTM8</name>
+                    <file> 52</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 77 52 31</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_wfe.c</name>
+            <outputs>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 105</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 55</file>
+                </tool>
+            </outputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_tim3.c</name>
+            <outputs>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 45</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 74</file>
+                </tool>
+            </outputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_usart.c</name>
+            <outputs>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 35</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 63</file>
+                </tool>
+            </outputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_tim2.c</name>
+            <outputs>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 24</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 92</file>
+                </tool>
+            </outputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\stm8l15x_it.c</name>
+            <outputs>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 91</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 47</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCSTM8</name>
+                    <file> 123</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_wwdg.c</name>
+            <outputs>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 26</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 69</file>
+                </tool>
+            </outputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\1_Middleware\Kfifo\ebyte_kfifo.c</name>
+            <outputs>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 38</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 102</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCSTM8</name>
+                    <file> 110</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_tim1.c</name>
+            <outputs>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 104</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 44</file>
+                </tool>
+            </outputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_tim5.c</name>
+            <outputs>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 56</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 62</file>
+                </tool>
+            </outputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_tim4.c</name>
+            <outputs>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 59</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 90</file>
+                </tool>
+            </outputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\main.c</name>
+            <outputs>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 28</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 50</file>
+                </tool>
+            </outputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_syscfg.c</name>
+            <outputs>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 41</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 76</file>
+                </tool>
+            </outputs>
+        </file>
+        <forcedrebuild>
+            <name>[MULTI_TOOL]</name>
+            <tool>ILINK</tool>
+        </forcedrebuild>
+        <forcedrebuild>
+            <name>[REBUILD_ALL]</name>
+        </forcedrebuild>
+    </configuration>
+</project>
diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/project.ewd b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/project.ewd
new file mode 100755
index 0000000..d10be78
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/project.ewd
@@ -0,0 +1,454 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<project>
+    <fileVersion>3</fileVersion>
+    <configuration>
+        <name>Debug</name>
+        <toolchain>
+            <name>STM8</name>
+        </toolchain>
+        <debug>1</debug>
+        <settings>
+            <name>C-SPY</name>
+            <archiveVersion>1</archiveVersion>
+            <data>
+                <version>1</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>CSpyMandatory</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CSpyInput</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CSpyRunToEnable</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CSpyRunToName</name>
+                    <state>main</state>
+                </option>
+                <option>
+                    <name>CSpyMacOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CSpyMacFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>DynDriver</name>
+                    <state>STLINK_STM8</state>
+                </option>
+                <option>
+                    <name>CSpyDDFOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CSpyDDFFile</name>
+                    <state>$TOOLKIT_DIR$\config\ddf\iostm8.ddf</state>
+                </option>
+                <option>
+                    <name>CSpyEnableExtraOptions</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CSpyExtraOptions</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CSpyImagesSuppressCheck1</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CSpyImagesPath1</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CSpyImagesSuppressCheck2</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CSpyImagesPath2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CSpyImagesSuppressCheck3</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CSpyImagesPath3</name>
+                    <state></state>
+                </option>
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+                    <state></state>
+                </option>
+                <option>
+                    <name>CSpyImagesOffset3</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CSpyImagesUse1</name>
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+                </option>
+                <option>
+                    <name>CSpyImagesUse2</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CSpyImagesUse3</name>
+                    <state>0</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>SIMULATOR_STM8</name>
+            <archiveVersion>1</archiveVersion>
+            <data>
+                <version>0</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>SimMandatory</name>
+                    <state>1</state>
+                </option>
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+        </settings>
+        <settings>
+            <name>STICE_STM8</name>
+            <archiveVersion>3</archiveVersion>
+            <data>
+                <version>2</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
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+                    <state>0</state>
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+                <option>
+                    <name>STiceSuppressLoad</name>
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+                <option>
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+                    <state>0</state>
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+                <option>
+                    <name>STiceLogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
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+                <option>
+                    <name>STiceUseSwim</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>STiceOptionBytesSetupFileOver</name>
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+        <settings>
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+                <wantNonLocal>1</wantNonLocal>
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+                <option>
+                    <name>STlinkOptionBytesSetupFile</name>
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+                <option>
+                    <name>STlinkEraseMemory</name>
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+        <debuggerPlugins>
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+            <plugin>
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+            <plugin>
+                <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
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+    </configuration>
+    <configuration>
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+        <toolchain>
+            <name>STM8</name>
+        </toolchain>
+        <debug>0</debug>
+        <settings>
+            <name>C-SPY</name>
+            <archiveVersion>1</archiveVersion>
+            <data>
+                <version>1</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>CSpyMandatory</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CSpyInput</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CSpyRunToEnable</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CSpyRunToName</name>
+                    <state>main</state>
+                </option>
+                <option>
+                    <name>CSpyMacOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CSpyMacFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>DynDriver</name>
+                    <state>SIMULATOR_STM8</state>
+                </option>
+                <option>
+                    <name>CSpyDDFOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CSpyDDFFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CSpyEnableExtraOptions</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CSpyExtraOptions</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CSpyImagesSuppressCheck1</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CSpyImagesPath1</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CSpyImagesSuppressCheck2</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CSpyImagesPath2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CSpyImagesSuppressCheck3</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CSpyImagesPath3</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CSpyImagesOffset1</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CSpyImagesOffset2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CSpyImagesOffset3</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CSpyImagesUse1</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CSpyImagesUse2</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CSpyImagesUse3</name>
+                    <state>0</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>SIMULATOR_STM8</name>
+            <archiveVersion>1</archiveVersion>
+            <data>
+                <version>0</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>SimMandatory</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>STICE_STM8</name>
+            <archiveVersion>3</archiveVersion>
+            <data>
+                <version>2</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>STiceMandatory</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>STiceSuppressLoad</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>STiceVerifyLoad</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>STiceLogFileOver</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>STiceLogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>STiceUseSwim</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>STiceOptionBytesSetupFileOver</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>STiceOptionBytesSetupFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>STiceEraseMemory</name>
+                    <state>0</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>STLINK_STM8</name>
+            <archiveVersion>3</archiveVersion>
+            <data>
+                <version>2</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>STlinkMandatory</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>STlinkSuppressLoad</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>STlinkVerifyLoad</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>STlinkLogFileOver</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>STlinkLogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>STlinkOptionBytesSetupFileOver</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>STlinkOptionBytesSetupFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>STlinkEraseMemory</name>
+                    <state>0</state>
+                </option>
+            </data>
+        </settings>
+        <debuggerPlugins>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
+                <loadFlag>1</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+        </debuggerPlugins>
+    </configuration>
+</project>
diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/project.ewp b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/project.ewp
new file mode 100755
index 0000000..2679097
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/project.ewp
@@ -0,0 +1,1783 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<project>
+    <fileVersion>3</fileVersion>
+    <configuration>
+        <name>Debug</name>
+        <toolchain>
+            <name>STM8</name>
+        </toolchain>
+        <debug>1</debug>
+        <settings>
+            <name>General</name>
+            <archiveVersion>4</archiveVersion>
+            <data>
+                <version>2</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>GenDeviceSelectMenu</name>
+                    <state>STM8L151G4	STM8L151G4</state>
+                </option>
+                <option>
+                    <name>GenCodeModel</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenDataModel</name>
+                    <version>0</version>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>GOutputBinary</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>ExePath</name>
+                    <state>Debug\Exe</state>
+                </option>
+                <option>
+                    <name>ObjPath</name>
+                    <state>Debug\Obj</state>
+                </option>
+                <option>
+                    <name>ListPath</name>
+                    <state>Debug\List</state>
+                </option>
+                <option>
+                    <name>GenRuntimeLibSelect</name>
+                    <version>0</version>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>GenRuntimeLibSelectSlave</name>
+                    <version>0</version>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>GenRTDescription</name>
+                    <state>Use the normal configuration of the C/EC++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>
+                </option>
+                <option>
+                    <name>GenRTConfigPath</name>
+                    <state>$TOOLKIT_DIR$\LIB\dlstm8smn.h</state>
+                </option>
+                <option>
+                    <name>GenLibInFormatter</name>
+                    <version>0</version>
+                    <state>5</state>
+                </option>
+                <option>
+                    <name>GenLibInFormatterDescription</name>
+                    <state>No specifier n, no float, no scan set, no assignment suppressing.</state>
+                </option>
+                <option>
+                    <name>GenLibOutFormatter</name>
+                    <version>0</version>
+                    <state>5</state>
+                </option>
+                <option>
+                    <name>GenLibOutFormatterDescription</name>
+                    <state>No specifier a or A, no specifier n, no float.</state>
+                </option>
+                <option>
+                    <name>GenStackSize</name>
+                    <state>0x100</state>
+                </option>
+                <option>
+                    <name>GenHeapSize</name>
+                    <state>0x100</state>
+                </option>
+                <option>
+                    <name>GeneralEnableMisra</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GeneralMisraVerbose</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GeneralMisraVer</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GeneralMisraRules04</name>
+                    <version>0</version>
+                    <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
+                </option>
+                <option>
+                    <name>GeneralMisraRules98</name>
+                    <version>0</version>
+                    <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
+                </option>
+                <option>
+                    <name>GenMathFunctionVariant</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenMathFunctionDescription</name>
+                    <state>Default variants of cos, sin, tan, log, log10, pow, and exp.</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>ICCSTM8</name>
+            <archiveVersion>3</archiveVersion>
+            <data>
+                <version>9</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>IccRequirePrototypes</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IccLanguageConformance</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IccCharIs</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IccMultibyteSupport</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IccOptLevel</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IccOptStrategy</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IccOptLevelSlave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IccOptAllowList</name>
+                    <version>0</version>
+                    <state>000000</state>
+                </option>
+                <option>
+                    <name>IccGenerateDebugInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IccOutputFile</name>
+                    <state>$FILE_BNAME$.o</state>
+                </option>
+                <option>
+                    <name>IccCodeModel</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IccDataModel</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IccObjPrefix</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IccLibConfigHeader</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCDefines</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCPreprocFile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCPreprocComments</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCPreprocLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCListCFile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCListCMnemonics</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCListCMessages</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCListAssFile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCListAssSource</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCEnableRemarks</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCDiagSuppress</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCDiagRemark</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCDiagWarning</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCDiagError</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCDiagWarnAreErr</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCompilerRuntimeInfo</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>PreInclude</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCIncludePath2</name>
+                    <state>$PROJ_DIR$\..\..\..\2_Ebyte_Board_Support\E15-EVB02</state>
+                    <state>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\inc</state>
+                    <state>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers</state>
+                    <state>$PROJ_DIR$\..\..\..\1_Middleware\Kfifo</state>
+                    <state>$PROJ_DIR$\ebyte</state>
+                    <state>$PROJ_DIR$\..\..\..\1_Middleware\Produce</state>
+                    <state>$PROJ_DIR$\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx</state>
+                </option>
+                <option>
+                    <name>CCStdIncCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CompilerMisraOverride</name>
+                    <state>0</state>
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+                <option>
+                    <name>CompilerMisraRules04</name>
+                    <version>0</version>
+                    <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
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+                    <name>CompilerMisraRules98</name>
+                    <version>0</version>
+                    <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
+                </option>
+                <option>
+                    <name>IccUseExtraOptions</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IccExtraOptions</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IccLang</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IccCDialect</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IccAllowVLA</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IccCppDialect</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IccNoVregs</name>
+                    <version>0</version>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IccOptNoSizeConstraints</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IccCppInlineSemantics</name>
+                    <state>0</state>
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+                    <name>IccStaticDestr</name>
+                    <state>1</state>
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+                <option>
+                    <name>IccFloatSemantics</name>
+                    <state>0</state>
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+            </data>
+        </settings>
+        <settings>
+            <name>ASTM8</name>
+            <archiveVersion>3</archiveVersion>
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+                <version>2</version>
+                <wantNonLocal>1</wantNonLocal>
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+                    <state>1</state>
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+                    <name>AsmDebugInfo</name>
+                    <state>1</state>
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+                    <name>AsmListMacroDefinitions</name>
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+                    <name>AsmListAssembledOnly</name>
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+                    <state></state>
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+                    <name>AsmPreprocComment</name>
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+                    <state></state>
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+                    <state>100</state>
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+                    <name>AsmObjPrefix</name>
+                    <state>1</state>
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+                    <state>$FILE_BNAME$.o</state>
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+                <option>
+                    <name>AsmUseExtraOptions</name>
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+                    <version>2</version>
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+                <option>
+                    <name>OCOutputOverride</name>
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+                <option>
+                    <name>OOCOutputFile</name>
+                    <state>project.hex</state>
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+                <option>
+                    <name>OOCCommandLineProducer</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OOCObjCopyEnable</name>
+                    <state>1</state>
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+            </data>
+        </settings>
+        <settings>
+            <name>CUSTOM</name>
+            <archiveVersion>3</archiveVersion>
+            <data>
+                <extensions></extensions>
+                <cmdline></cmdline>
+                <hasPrio>0</hasPrio>
+            </data>
+        </settings>
+        <settings>
+            <name>BICOMP</name>
+            <archiveVersion>0</archiveVersion>
+            <data />
+        </settings>
+        <settings>
+            <name>BUILDACTION</name>
+            <archiveVersion>1</archiveVersion>
+            <data>
+                <prebuild></prebuild>
+                <postbuild></postbuild>
+            </data>
+        </settings>
+        <settings>
+            <name>ILINK</name>
+            <archiveVersion>4</archiveVersion>
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+                    <name>IlinkInputFileSlave</name>
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+                    <state>project.out</state>
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+                    <name>IlinkDebugInfoEnable</name>
+                    <state>1</state>
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+                    <name>IlinkKeepSymbols</name>
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+                    <state></state>
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+                    <name>IlinkMapFile</name>
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+                    <state>$TOOLKIT_DIR$\config\lnkstm8l151g4.icf</state>
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+                    <state>__iar_program_start</state>
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+                    <name>IlinkLogRedirSymbols</name>
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+                    <name>IlinkLogUnusedFragments</name>
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+                    <name>IarchiveOutput</name>
+                    <state>###Unitialized###</state>
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+                    <state>UnspecifiedSTM8	STM8 - Unspecified</state>
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+                    <name>GenRTConfigPath</name>
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+                <debug>0</debug>
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+                    <name>IlinkLibIOConfig</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>XLinkMisraHandler</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkInputFileSlave</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkOutputFile</name>
+                    <state>project.out</state>
+                </option>
+                <option>
+                    <name>IlinkDebugInfoEnable</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkKeepSymbols</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinaryFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinarySymbol</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinarySegment</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinaryAlign</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkDefines</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkConfigDefines</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkMapFile</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkLogFile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogInitialization</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogModule</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogSection</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogVeneer</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkIcfOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkIcfFile</name>
+                    <state>lnk0t.icf</state>
+                </option>
+                <option>
+                    <name>IlinkIcfFileSlave</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkEnableRemarks</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkSuppressDiags</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkTreatAsRem</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkTreatAsWarn</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkTreatAsErr</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkWarningsAreErrors</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkStackSize</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkHeapSize</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkUseExtraOptions</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkExtraOptions</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkAutoLibEnable</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkAdditionalLibs</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkOverrideProgramEntryLabel</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkProgramEntryLabelSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkProgramEntryLabel</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>DoFill</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>FillerByte</name>
+                    <state>0xFF</state>
+                </option>
+                <option>
+                    <name>FillerStart</name>
+                    <state>0x0</state>
+                </option>
+                <option>
+                    <name>FillerEnd</name>
+                    <state>0x0</state>
+                </option>
+                <option>
+                    <name>CrcSize</name>
+                    <version>0</version>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CrcAlign</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CrcPoly</name>
+                    <state>0x11021</state>
+                </option>
+                <option>
+                    <name>CrcCompl</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CrcBitOrder</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CrcInitialValue</name>
+                    <state>0x0</state>
+                </option>
+                <option>
+                    <name>DoCrc</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CrcFullSize</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkCspyDebugSupportEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkCspyBufferedWrite</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogAutoLibSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogRedirSymbols</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogUnusedFragments</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkCrcReverseByteOrder</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkCrcUseAsInput</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CrcAlgorithm</name>
+                    <version>1</version>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CrcUnitSize</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkOptMergeDuplSections</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkIcfFile_AltDefault</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkLogCallGraph</name>
+                    <state>0</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>IARCHIVE</name>
+            <archiveVersion>3</archiveVersion>
+            <data>
+                <version>0</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>IarchiveInputs</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IarchiveOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IarchiveOutput</name>
+                    <state>###Unitialized###</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>BILINK</name>
+            <archiveVersion>0</archiveVersion>
+            <data />
+        </settings>
+    </configuration>
+    <group>
+        <name>board</name>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\2_Ebyte_Board_Support\E15-EVB02\board.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\2_Ebyte_Board_Support\E15-EVB02\board_button.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\2_Ebyte_Board_Support\E15-EVB02\board_mini_printf.c</name>
+        </file>
+    </group>
+    <group>
+        <name>drivers/ebyte</name>
+        <group>
+            <name>CMT2310A</name>
+            <file>
+                <name>$PROJ_DIR$\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx\cmt2310a_410mhz.c</name>
+            </file>
+            <file>
+                <name>$PROJ_DIR$\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx\cmt2310a_433mhz.c</name>
+            </file>
+            <file>
+                <name>$PROJ_DIR$\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx\cmt2310a_868mhz.c</name>
+            </file>
+            <file>
+                <name>$PROJ_DIR$\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx\cmt2310a_915mhz.c</name>
+            </file>
+            <file>
+                <name>$PROJ_DIR$\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx\ebyte_e48x.c</name>
+            </file>
+            <file>
+                <name>$PROJ_DIR$\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx\radio.c</name>
+            </file>
+            <file>
+                <name>$PROJ_DIR$\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx\radio_hal.c</name>
+            </file>
+            <file>
+                <name>$PROJ_DIR$\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx\radio_mac.c</name>
+            </file>
+            <file>
+                <name>$PROJ_DIR$\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx\radio_phy.c</name>
+            </file>
+            <file>
+                <name>$PROJ_DIR$\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx\radio_spi.c</name>
+            </file>
+        </group>
+        <group>
+            <name>sub</name>
+            <file>
+                <name>$PROJ_DIR$\ebyte\ebyte_callback.c</name>
+            </file>
+            <file>
+                <name>$PROJ_DIR$\ebyte\ebyte_conf.h</name>
+            </file>
+            <file>
+                <name>$PROJ_DIR$\ebyte\ebyte_port.c</name>
+            </file>
+        </group>
+        <file>
+            <name>$PROJ_DIR$\ebyte\ebyte_core.c</name>
+        </file>
+    </group>
+    <group>
+        <name>drivers/mcu</name>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_adc.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_aes.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_beep.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_clk.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_comp.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_dac.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_dma.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_exti.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_flash.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_gpio.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_i2c.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_irtim.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_itc.c</name>
+            <excluded>
+                <configuration>Debug</configuration>
+            </excluded>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_iwdg.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_lcd.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_pwr.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_rst.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_rtc.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_spi.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_syscfg.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_tim1.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_tim2.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_tim3.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_tim4.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_tim5.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_usart.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_wfe.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_wwdg.c</name>
+        </file>
+    </group>
+    <group>
+        <name>main</name>
+        <file>
+            <name>$PROJ_DIR$\main.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\stm8l15x_it.c</name>
+        </file>
+    </group>
+    <group>
+        <name>middleware</name>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\1_Middleware\Produce\ebyte_debug.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\1_Middleware\Kfifo\ebyte_kfifo.c</name>
+        </file>
+    </group>
+</project>
diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/project.ewt b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/project.ewt
new file mode 100755
index 0000000..d7ea52f
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/project.ewt
@@ -0,0 +1,2268 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<project>
+    <fileVersion>3</fileVersion>
+    <configuration>
+        <name>Debug</name>
+        <toolchain>
+            <name>STM8</name>
+        </toolchain>
+        <debug>1</debug>
+        <settings>
+            <name>C-STAT</name>
+            <archiveVersion>260</archiveVersion>
+            <data>
+                <version>260</version>
+                <cstatargs>
+                    <useExtraArgs>0</useExtraArgs>
+                    <extraArgs></extraArgs>
+                    <analyzeTimeoutEnabled>1</analyzeTimeoutEnabled>
+                    <analyzeTimeout>600</analyzeTimeout>
+                    <enableParallel>0</enableParallel>
+                    <parallelThreads>6</parallelThreads>
+                    <enableFalsePositives>0</enableFalsePositives>
+                    <messagesLimitEnabled>1</messagesLimitEnabled>
+                    <messagesLimit>100</messagesLimit>
+                </cstatargs>
+                <cstat_settings>
+                    <cstat_version>1.4.5</cstat_version>
+                    <checks_tree>
+                        <package name="STDCHECKS" enabled="true">
+                            <group enabled="true" name="ARR">
+                                <check name="ARR-inv-index-pos" enabled="true" />
+                                <check name="ARR-inv-index-ptr-pos" enabled="true" />
+                                <check name="ARR-inv-index-ptr" enabled="true" />
+                                <check name="ARR-inv-index" enabled="true" />
+                                <check name="ARR-neg-index" enabled="true" />
+                                <check name="ARR-uninit-index" enabled="true" />
+                            </group>
+                            <group enabled="true" name="ATH">
+                                <check name="ATH-cmp-float" enabled="true" />
+                                <check name="ATH-cmp-unsign-neg" enabled="true" />
+                                <check name="ATH-cmp-unsign-pos" enabled="true" />
+                                <check name="ATH-div-0-assign" enabled="true" />
+                                <check name="ATH-div-0-cmp-aft" enabled="false" />
+                                <check name="ATH-div-0-cmp-bef" enabled="true" />
+                                <check name="ATH-div-0-interval" enabled="true" />
+                                <check name="ATH-div-0-pos" enabled="true" />
+                                <check name="ATH-div-0-unchk-global" enabled="true" />
+                                <check name="ATH-div-0-unchk-local" enabled="true" />
+                                <check name="ATH-div-0-unchk-param" enabled="true" />
+                                <check name="ATH-div-0" enabled="true" />
+                                <check name="ATH-inc-bool" enabled="true" />
+                                <check name="ATH-malloc-overrun" enabled="true" />
+                                <check name="ATH-neg-check-nonneg" enabled="true" />
+                                <check name="ATH-neg-check-pos" enabled="true" />
+                                <check name="ATH-new-overrun" enabled="true" />
+                                <check name="ATH-overflow-cast" enabled="false" />
+                                <check name="ATH-overflow" enabled="true" />
+                                <check name="ATH-shift-bounds" enabled="true" />
+                                <check name="ATH-shift-neg" enabled="true" />
+                                <check name="ATH-sizeof-by-sizeof" enabled="true" />
+                            </group>
+                            <group enabled="true" name="CAST">
+                                <check name="CAST-old-style" enabled="false" />
+                            </group>
+                            <group enabled="true" name="COMMA">
+                                <check name="COMMA-overload" enabled="false" />
+                            </group>
+                            <group enabled="true" name="COMMENT">
+                                <check name="COMMENT-nested" enabled="true" />
+                            </group>
+                            <group enabled="true" name="CONST">
+                                <check name="CONST-member-ret" enabled="true" />
+                            </group>
+                            <group enabled="true" name="COP">
+                                <check name="COP-alloc-ctor" enabled="false" />
+                                <check name="COP-assign-op-ret" enabled="true" />
+                                <check name="COP-assign-op-self" enabled="true" />
+                                <check name="COP-assign-op" enabled="true" />
+                                <check name="COP-copy-ctor" enabled="true" />
+                                <check name="COP-dealloc-dtor" enabled="false" />
+                                <check name="COP-dtor" enabled="true" />
+                                <check name="COP-init-order" enabled="true" />
+                                <check name="COP-init-uninit" enabled="true" />
+                                <check name="COP-member-uninit" enabled="true" />
+                            </group>
+                            <group enabled="true" name="CPU">
+                                <check name="CPU-ctor-call-virt" enabled="true" />
+                                <check name="CPU-ctor-implicit" enabled="false" />
+                                <check name="CPU-delete-void" enabled="true" />
+                                <check name="CPU-dtor-call-virt" enabled="true" />
+                                <check name="CPU-malloc-class" enabled="true" />
+                                <check name="CPU-nonvirt-dtor" enabled="true" />
+                                <check name="CPU-return-ref-to-class-data" enabled="true" />
+                            </group>
+                            <group enabled="true" name="DECL">
+                                <check name="DECL-implicit-int" enabled="false" />
+                            </group>
+                            <group enabled="true" name="DEFINE">
+                                <check name="DEFINE-hash-multiple" enabled="true" />
+                            </group>
+                            <group enabled="true" name="ENUM">
+                                <check name="ENUM-bounds" enabled="false" />
+                            </group>
+                            <group enabled="true" name="EXP">
+                                <check name="EXP-cond-assign" enabled="true" />
+                                <check name="EXP-dangling-else" enabled="true" />
+                                <check name="EXP-loop-exit" enabled="true" />
+                                <check name="EXP-main-ret-int" enabled="false" />
+                                <check name="EXP-null-stmt" enabled="false" />
+                                <check name="EXP-stray-semicolon" enabled="false" />
+                            </group>
+                            <group enabled="true" name="EXPR">
+                                <check name="EXPR-const-overflow" enabled="true" />
+                            </group>
+                            <group enabled="true" name="FPT">
+                                <check name="FPT-cmp-null" enabled="true" />
+                                <check name="FPT-literal" enabled="false" />
+                                <check name="FPT-misuse" enabled="true" />
+                            </group>
+                            <group enabled="true" name="FUNC">
+                                <check name="FUNC-implicit-decl" enabled="false" />
+                                <check name="FUNC-unprototyped-all" enabled="false" />
+                                <check name="FUNC-unprototyped-used" enabled="true" />
+                            </group>
+                            <group enabled="true" name="INCLUDE">
+                                <check name="INCLUDE-c-file" enabled="false" />
+                            </group>
+                            <group enabled="true" name="INT">
+                                <check name="INT-use-signed-as-unsigned-pos" enabled="false" />
+                                <check name="INT-use-signed-as-unsigned" enabled="true" />
+                            </group>
+                            <group enabled="true" name="ITR">
+                                <check name="ITR-end-cmp-aft" enabled="true" />
+                                <check name="ITR-end-cmp-bef" enabled="true" />
+                                <check name="ITR-invalidated" enabled="true" />
+                                <check name="ITR-mismatch-alg" enabled="false" />
+                                <check name="ITR-store" enabled="false" />
+                                <check name="ITR-uninit" enabled="true" />
+                            </group>
+                            <group enabled="true" name="LIB">
+                                <check name="LIB-bsearch-overrun-pos" enabled="false" />
+                                <check name="LIB-bsearch-overrun" enabled="false" />
+                                <check name="LIB-fn-unsafe" enabled="false" />
+                                <check name="LIB-fread-overrun-pos" enabled="false" />
+                                <check name="LIB-fread-overrun" enabled="true" />
+                                <check name="LIB-memchr-overrun-pos" enabled="false" />
+                                <check name="LIB-memchr-overrun" enabled="true" />
+                                <check name="LIB-memcpy-overrun-pos" enabled="false" />
+                                <check name="LIB-memcpy-overrun" enabled="true" />
+                                <check name="LIB-memset-overrun-pos" enabled="false" />
+                                <check name="LIB-memset-overrun" enabled="true" />
+                                <check name="LIB-putenv" enabled="false" />
+                                <check name="LIB-qsort-overrun-pos" enabled="false" />
+                                <check name="LIB-qsort-overrun" enabled="false" />
+                                <check name="LIB-return-const" enabled="true" />
+                                <check name="LIB-return-error" enabled="true" />
+                                <check name="LIB-return-leak" enabled="true" />
+                                <check name="LIB-return-neg" enabled="true" />
+                                <check name="LIB-return-null" enabled="true" />
+                                <check name="LIB-sprintf-overrun" enabled="false" />
+                                <check name="LIB-std-sort-overrun-pos" enabled="false" />
+                                <check name="LIB-std-sort-overrun" enabled="true" />
+                                <check name="LIB-strcat-overrun-pos" enabled="false" />
+                                <check name="LIB-strcat-overrun" enabled="true" />
+                                <check name="LIB-strcpy-overrun-pos" enabled="false" />
+                                <check name="LIB-strcpy-overrun" enabled="true" />
+                                <check name="LIB-strncat-overrun-pos" enabled="false" />
+                                <check name="LIB-strncat-overrun" enabled="true" />
+                                <check name="LIB-strncmp-overrun-pos" enabled="false" />
+                                <check name="LIB-strncmp-overrun" enabled="true" />
+                                <check name="LIB-strncpy-overrun-pos" enabled="false" />
+                                <check name="LIB-strncpy-overrun" enabled="true" />
+                            </group>
+                            <group enabled="true" name="LOGIC">
+                                <check name="LOGIC-overload" enabled="false" />
+                            </group>
+                            <group enabled="true" name="MEM">
+                                <check name="MEM-delete-array-op" enabled="true" />
+                                <check name="MEM-delete-op" enabled="true" />
+                                <check name="MEM-double-free-alias" enabled="true" />
+                                <check name="MEM-double-free-some" enabled="true" />
+                                <check name="MEM-double-free" enabled="true" />
+                                <check name="MEM-free-field" enabled="true" />
+                                <check name="MEM-free-fptr" enabled="true" />
+                                <check name="MEM-free-no-alloc-struct" enabled="false" />
+                                <check name="MEM-free-no-alloc" enabled="false" />
+                                <check name="MEM-free-no-use" enabled="true" />
+                                <check name="MEM-free-op" enabled="true" />
+                                <check name="MEM-free-struct-field" enabled="true" />
+                                <check name="MEM-free-variable-alias" enabled="true" />
+                                <check name="MEM-free-variable" enabled="true" />
+                                <check name="MEM-leak-alias" enabled="true" />
+                                <check name="MEM-leak" enabled="false" />
+                                <check name="MEM-malloc-arith" enabled="false" />
+                                <check name="MEM-malloc-diff-type" enabled="true" />
+                                <check name="MEM-malloc-sizeof-ptr" enabled="true" />
+                                <check name="MEM-malloc-sizeof" enabled="true" />
+                                <check name="MEM-malloc-strlen" enabled="false" />
+                                <check name="MEM-realloc-diff-type" enabled="true" />
+                                <check name="MEM-return-free" enabled="true" />
+                                <check name="MEM-return-no-assign" enabled="true" />
+                                <check name="MEM-stack-global-field" enabled="true" />
+                                <check name="MEM-stack-global" enabled="true" />
+                                <check name="MEM-stack-param-ref" enabled="true" />
+                                <check name="MEM-stack-param" enabled="true" />
+                                <check name="MEM-stack-pos" enabled="true" />
+                                <check name="MEM-stack-ref" enabled="true" />
+                                <check name="MEM-stack" enabled="true" />
+                                <check name="MEM-use-free-all" enabled="true" />
+                                <check name="MEM-use-free-some" enabled="true" />
+                            </group>
+                            <group enabled="true" name="PTR">
+                                <check name="PTR-arith-field" enabled="true" />
+                                <check name="PTR-arith-stack" enabled="true" />
+                                <check name="PTR-arith-var" enabled="true" />
+                                <check name="PTR-cmp-str-lit" enabled="true" />
+                                <check name="PTR-null-assign-fun-pos" enabled="false" />
+                                <check name="PTR-null-assign-pos" enabled="false" />
+                                <check name="PTR-null-assign" enabled="true" />
+                                <check name="PTR-null-cmp-aft" enabled="true" />
+                                <check name="PTR-null-cmp-bef-fun" enabled="true" />
+                                <check name="PTR-null-cmp-bef" enabled="true" />
+                                <check name="PTR-null-fun-pos" enabled="true" />
+                                <check name="PTR-null-literal-pos" enabled="false" />
+                                <check name="PTR-overload" enabled="false" />
+                                <check name="PTR-singleton-arith-pos" enabled="false" />
+                                <check name="PTR-singleton-arith" enabled="true" />
+                                <check name="PTR-unchk-param-some" enabled="true" />
+                                <check name="PTR-unchk-param" enabled="false" />
+                                <check name="PTR-uninit-pos" enabled="false" />
+                                <check name="PTR-uninit" enabled="true" />
+                            </group>
+                            <group enabled="true" name="RED">
+                                <check name="RED-alloc-zero-bytes" enabled="false" />
+                                <check name="RED-case-reach" enabled="false" />
+                                <check name="RED-cmp-always" enabled="false" />
+                                <check name="RED-cmp-never" enabled="false" />
+                                <check name="RED-cond-always" enabled="false" />
+                                <check name="RED-cond-const-assign" enabled="true" />
+                                <check name="RED-cond-const-expr" enabled="false" />
+                                <check name="RED-cond-const" enabled="false" />
+                                <check name="RED-cond-never" enabled="false" />
+                                <check name="RED-dead" enabled="true" />
+                                <check name="RED-expr" enabled="false" />
+                                <check name="RED-func-no-effect" enabled="false" />
+                                <check name="RED-local-hides-global" enabled="true" />
+                                <check name="RED-local-hides-local" enabled="false" />
+                                <check name="RED-local-hides-member" enabled="false" />
+                                <check name="RED-local-hides-param" enabled="true" />
+                                <check name="RED-no-effect" enabled="false" />
+                                <check name="RED-self-assign" enabled="true" />
+                                <check name="RED-unused-assign" enabled="true" />
+                                <check name="RED-unused-param" enabled="false" />
+                                <check name="RED-unused-return-val" enabled="false" />
+                                <check name="RED-unused-val" enabled="false" />
+                                <check name="RED-unused-var-all" enabled="true" />
+                            </group>
+                            <group enabled="true" name="RESOURCE">
+                                <check name="RESOURCE-deref-file" enabled="false" />
+                                <check name="RESOURCE-double-close" enabled="true" />
+                                <check name="RESOURCE-file-no-close-all" enabled="true" />
+                                <check name="RESOURCE-file-pos-neg" enabled="false" />
+                                <check name="RESOURCE-file-use-after-close" enabled="true" />
+                                <check name="RESOURCE-implicit-deref-file" enabled="false" />
+                                <check name="RESOURCE-write-ronly-file" enabled="true" />
+                            </group>
+                            <group enabled="true" name="SIZEOF">
+                                <check name="SIZEOF-side-effect" enabled="true" />
+                            </group>
+                            <group enabled="true" name="SPC">
+                                <check name="SPC-order" enabled="true" />
+                                <check name="SPC-uninit-arr-all" enabled="false" />
+                                <check name="SPC-uninit-struct-field-heap" enabled="true" />
+                                <check name="SPC-uninit-struct-field" enabled="false" />
+                                <check name="SPC-uninit-struct" enabled="true" />
+                                <check name="SPC-uninit-var-all" enabled="true" />
+                                <check name="SPC-uninit-var-some" enabled="true" />
+                                <check name="SPC-volatile-reads" enabled="false" />
+                                <check name="SPC-volatile-writes" enabled="false" />
+                            </group>
+                            <group enabled="true" name="STRUCT">
+                                <check name="STRUCT-signed-bit" enabled="false" />
+                            </group>
+                            <group enabled="true" name="SWITCH">
+                                <check name="SWITCH-fall-through" enabled="true" />
+                            </group>
+                            <group enabled="true" name="UNION">
+                                <check name="UNION-overlap-assign" enabled="true" />
+                                <check name="UNION-type-punning" enabled="true" />
+                            </group>
+                        </package>
+                        <package name="CERT" enabled="false">
+                            <group enabled="true" name="CERT-EXP">
+                                <check name="CERT-EXP19-C" enabled="true" />
+                            </group>
+                            <group enabled="true" name="CERT-FIO">
+                                <check name="CERT-FIO37-C" enabled="true" />
+                                <check name="CERT-FIO38-C" enabled="true" />
+                            </group>
+                            <group enabled="true" name="CERT-SIG">
+                                <check name="CERT-SIG31-C" enabled="true" />
+                            </group>
+                        </package>
+                        <package name="SECURITY" enabled="false">
+                            <group enabled="true" name="SEC-BUFFER">
+                                <check name="SEC-BUFFER-memory-leak-alias" enabled="true" />
+                                <check name="SEC-BUFFER-memory-leak" enabled="false" />
+                                <check name="SEC-BUFFER-memset-overrun-pos" enabled="false" />
+                                <check name="SEC-BUFFER-memset-overrun" enabled="true" />
+                                <check name="SEC-BUFFER-qsort-overrun-pos" enabled="false" />
+                                <check name="SEC-BUFFER-qsort-overrun" enabled="true" />
+                                <check name="SEC-BUFFER-sprintf-overrun" enabled="true" />
+                                <check name="SEC-BUFFER-std-sort-overrun-pos" enabled="false" />
+                                <check name="SEC-BUFFER-std-sort-overrun" enabled="true" />
+                                <check name="SEC-BUFFER-strcat-overrun-pos" enabled="false" />
+                                <check name="SEC-BUFFER-strcat-overrun" enabled="true" />
+                                <check name="SEC-BUFFER-strcpy-overrun-pos" enabled="false" />
+                                <check name="SEC-BUFFER-strcpy-overrun" enabled="true" />
+                                <check name="SEC-BUFFER-strncat-overrun-pos" enabled="false" />
+                                <check name="SEC-BUFFER-strncat-overrun" enabled="true" />
+                                <check name="SEC-BUFFER-strncmp-overrun-pos" enabled="false" />
+                                <check name="SEC-BUFFER-strncmp-overrun" enabled="true" />
+                                <check name="SEC-BUFFER-strncpy-overrun-pos" enabled="false" />
+                                <check name="SEC-BUFFER-strncpy-overrun" enabled="true" />
+                                <check name="SEC-BUFFER-tainted-alloc-size" enabled="true" />
+                                <check name="SEC-BUFFER-tainted-copy-length" enabled="true" />
+                                <check name="SEC-BUFFER-tainted-copy" enabled="true" />
+                                <check name="SEC-BUFFER-tainted-index" enabled="true" />
+                                <check name="SEC-BUFFER-tainted-offset" enabled="true" />
+                                <check name="SEC-BUFFER-use-after-free-all" enabled="true" />
+                                <check name="SEC-BUFFER-use-after-free-some" enabled="true" />
+                            </group>
+                            <group enabled="true" name="SEC-DIV-0">
+                                <check name="SEC-DIV-0-compare-after" enabled="true" />
+                                <check name="SEC-DIV-0-compare-before" enabled="true" />
+                                <check name="SEC-DIV-0-tainted" enabled="true" />
+                            </group>
+                            <group enabled="true" name="SEC-FILEOP">
+                                <check name="SEC-FILEOP-open-no-close" enabled="true" />
+                                <check name="SEC-FILEOP-path-traversal" enabled="false" />
+                                <check name="SEC-FILEOP-use-after-close" enabled="true" />
+                            </group>
+                            <group enabled="true" name="SEC-INJECTION">
+                                <check name="SEC-INJECTION-sql" enabled="false" />
+                                <check name="SEC-INJECTION-xpath" enabled="false" />
+                            </group>
+                            <group enabled="true" name="SEC-LOOP">
+                                <check name="SEC-LOOP-tainted-bound" enabled="true" />
+                            </group>
+                            <group enabled="true" name="SEC-NULL">
+                                <check name="SEC-NULL-assignment-fun-pos" enabled="false" />
+                                <check name="SEC-NULL-assignment" enabled="true" />
+                                <check name="SEC-NULL-cmp-aft" enabled="true" />
+                                <check name="SEC-NULL-cmp-bef-fun" enabled="true" />
+                                <check name="SEC-NULL-cmp-bef" enabled="true" />
+                                <check name="SEC-NULL-literal-pos" enabled="false" />
+                            </group>
+                            <group enabled="true" name="SEC-STRING">
+                                <check name="SEC-STRING-format-string" enabled="true" />
+                                <check name="SEC-STRING-hard-coded-credentials" enabled="false" />
+                            </group>
+                        </package>
+                        <package name="MISRAC2004" enabled="false">
+                            <group enabled="true" name="MISRAC2004-1">
+                                <check name="MISRAC2004-1.1" enabled="true" />
+                                <check name="MISRAC2004-1.2_a" enabled="true" />
+                                <check name="MISRAC2004-1.2_b" enabled="true" />
+                                <check name="MISRAC2004-1.2_c" enabled="true" />
+                                <check name="MISRAC2004-1.2_d" enabled="true" />
+                                <check name="MISRAC2004-1.2_e" enabled="true" />
+                                <check name="MISRAC2004-1.2_f" enabled="true" />
+                                <check name="MISRAC2004-1.2_g" enabled="true" />
+                                <check name="MISRAC2004-1.2_h" enabled="true" />
+                                <check name="MISRAC2004-1.2_i" enabled="true" />
+                                <check name="MISRAC2004-1.2_j" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC2004-2">
+                                <check name="MISRAC2004-2.1" enabled="true" />
+                                <check name="MISRAC2004-2.2" enabled="true" />
+                                <check name="MISRAC2004-2.3" enabled="true" />
+                                <check name="MISRAC2004-2.4" enabled="false" />
+                            </group>
+                            <group enabled="true" name="MISRAC2004-5">
+                                <check name="MISRAC2004-5.2" enabled="true" />
+                                <check name="MISRAC2004-5.3" enabled="true" />
+                                <check name="MISRAC2004-5.4" enabled="true" />
+                                <check name="MISRAC2004-5.5" enabled="false" />
+                                <check name="MISRAC2004-5.6" enabled="false" />
+                            </group>
+                            <group enabled="true" name="MISRAC2004-6">
+                                <check name="MISRAC2004-6.1" enabled="true" />
+                                <check name="MISRAC2004-6.3" enabled="false" />
+                                <check name="MISRAC2004-6.4" enabled="true" />
+                                <check name="MISRAC2004-6.5" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC2004-7">
+                                <check name="MISRAC2004-7.1" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC2004-8">
+                                <check name="MISRAC2004-8.1" enabled="true" />
+                                <check name="MISRAC2004-8.2" enabled="true" />
+                                <check name="MISRAC2004-8.5_a" enabled="true" />
+                                <check name="MISRAC2004-8.5_b" enabled="true" />
+                                <check name="MISRAC2004-8.12" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC2004-9">
+                                <check name="MISRAC2004-9.1_a" enabled="true" />
+                                <check name="MISRAC2004-9.1_b" enabled="true" />
+                                <check name="MISRAC2004-9.1_c" enabled="true" />
+                                <check name="MISRAC2004-9.2" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC2004-10">
+                                <check name="MISRAC2004-10.1_a" enabled="true" />
+                                <check name="MISRAC2004-10.1_b" enabled="true" />
+                                <check name="MISRAC2004-10.1_c" enabled="true" />
+                                <check name="MISRAC2004-10.1_d" enabled="true" />
+                                <check name="MISRAC2004-10.2_a" enabled="true" />
+                                <check name="MISRAC2004-10.2_b" enabled="true" />
+                                <check name="MISRAC2004-10.2_c" enabled="true" />
+                                <check name="MISRAC2004-10.2_d" enabled="true" />
+                                <check name="MISRAC2004-10.3" enabled="true" />
+                                <check name="MISRAC2004-10.4" enabled="true" />
+                                <check name="MISRAC2004-10.5" enabled="true" />
+                                <check name="MISRAC2004-10.6" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC2004-11">
+                                <check name="MISRAC2004-11.1" enabled="true" />
+                                <check name="MISRAC2004-11.3" enabled="false" />
+                                <check name="MISRAC2004-11.4" enabled="false" />
+                                <check name="MISRAC2004-11.5" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC2004-12">
+                                <check name="MISRAC2004-12.1" enabled="false" />
+                                <check name="MISRAC2004-12.2_a" enabled="true" />
+                                <check name="MISRAC2004-12.2_b" enabled="true" />
+                                <check name="MISRAC2004-12.2_c" enabled="true" />
+                                <check name="MISRAC2004-12.3" enabled="true" />
+                                <check name="MISRAC2004-12.4" enabled="true" />
+                                <check name="MISRAC2004-12.6_a" enabled="false" />
+                                <check name="MISRAC2004-12.6_b" enabled="false" />
+                                <check name="MISRAC2004-12.7" enabled="true" />
+                                <check name="MISRAC2004-12.8" enabled="true" />
+                                <check name="MISRAC2004-12.9" enabled="true" />
+                                <check name="MISRAC2004-12.10" enabled="true" />
+                                <check name="MISRAC2004-12.11" enabled="false" />
+                                <check name="MISRAC2004-12.12_a" enabled="true" />
+                                <check name="MISRAC2004-12.12_b" enabled="true" />
+                                <check name="MISRAC2004-12.13" enabled="false" />
+                            </group>
+                            <group enabled="true" name="MISRAC2004-13">
+                                <check name="MISRAC2004-13.1" enabled="true" />
+                                <check name="MISRAC2004-13.2_a" enabled="false" />
+                                <check name="MISRAC2004-13.2_b" enabled="false" />
+                                <check name="MISRAC2004-13.2_c" enabled="false" />
+                                <check name="MISRAC2004-13.2_d" enabled="false" />
+                                <check name="MISRAC2004-13.2_e" enabled="false" />
+                                <check name="MISRAC2004-13.3" enabled="true" />
+                                <check name="MISRAC2004-13.4" enabled="true" />
+                                <check name="MISRAC2004-13.5" enabled="true" />
+                                <check name="MISRAC2004-13.6" enabled="true" />
+                                <check name="MISRAC2004-13.7_a" enabled="true" />
+                                <check name="MISRAC2004-13.7_b" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC2004-14">
+                                <check name="MISRAC2004-14.1" enabled="true" />
+                                <check name="MISRAC2004-14.2" enabled="true" />
+                                <check name="MISRAC2004-14.3" enabled="true" />
+                                <check name="MISRAC2004-14.4" enabled="true" />
+                                <check name="MISRAC2004-14.5" enabled="true" />
+                                <check name="MISRAC2004-14.6" enabled="true" />
+                                <check name="MISRAC2004-14.7" enabled="true" />
+                                <check name="MISRAC2004-14.8_a" enabled="true" />
+                                <check name="MISRAC2004-14.8_b" enabled="true" />
+                                <check name="MISRAC2004-14.8_c" enabled="true" />
+                                <check name="MISRAC2004-14.8_d" enabled="true" />
+                                <check name="MISRAC2004-14.9" enabled="true" />
+                                <check name="MISRAC2004-14.10" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC2004-15">
+                                <check name="MISRAC2004-15.0" enabled="true" />
+                                <check name="MISRAC2004-15.1" enabled="true" />
+                                <check name="MISRAC2004-15.2" enabled="true" />
+                                <check name="MISRAC2004-15.3" enabled="true" />
+                                <check name="MISRAC2004-15.4" enabled="true" />
+                                <check name="MISRAC2004-15.5" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC2004-16">
+                                <check name="MISRAC2004-16.1" enabled="true" />
+                                <check name="MISRAC2004-16.2_a" enabled="true" />
+                                <check name="MISRAC2004-16.2_b" enabled="true" />
+                                <check name="MISRAC2004-16.3" enabled="true" />
+                                <check name="MISRAC2004-16.5" enabled="true" />
+                                <check name="MISRAC2004-16.7" enabled="true" />
+                                <check name="MISRAC2004-16.8" enabled="true" />
+                                <check name="MISRAC2004-16.9" enabled="true" />
+                                <check name="MISRAC2004-16.10" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC2004-17">
+                                <check name="MISRAC2004-17.1_a" enabled="true" />
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+                                <check name="MISRAC2004-17.1_c" enabled="true" />
+                                <check name="MISRAC2004-17.4_a" enabled="true" />
+                                <check name="MISRAC2004-17.4_b" enabled="true" />
+                                <check name="MISRAC2004-17.5" enabled="true" />
+                                <check name="MISRAC2004-17.6_a" enabled="true" />
+                                <check name="MISRAC2004-17.6_b" enabled="true" />
+                                <check name="MISRAC2004-17.6_c" enabled="true" />
+                                <check name="MISRAC2004-17.6_d" enabled="true" />
+                            </group>
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+                                <check name="MISRAC2004-18.1" enabled="true" />
+                                <check name="MISRAC2004-18.2" enabled="true" />
+                                <check name="MISRAC2004-18.4" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC2004-19">
+                                <check name="MISRAC2004-19.2" enabled="false" />
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+                                <check name="MISRAC2004-19.12" enabled="true" />
+                                <check name="MISRAC2004-19.13" enabled="false" />
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+                                <check name="MEM-malloc-sizeof" enabled="true" />
+                                <check name="MEM-malloc-strlen" enabled="false" />
+                                <check name="MEM-realloc-diff-type" enabled="true" />
+                                <check name="MEM-return-free" enabled="true" />
+                                <check name="MEM-return-no-assign" enabled="true" />
+                                <check name="MEM-stack-global-field" enabled="true" />
+                                <check name="MEM-stack-global" enabled="true" />
+                                <check name="MEM-stack-param-ref" enabled="true" />
+                                <check name="MEM-stack-param" enabled="true" />
+                                <check name="MEM-stack-pos" enabled="true" />
+                                <check name="MEM-stack-ref" enabled="true" />
+                                <check name="MEM-stack" enabled="true" />
+                                <check name="MEM-use-free-all" enabled="true" />
+                                <check name="MEM-use-free-some" enabled="true" />
+                            </group>
+                            <group enabled="true" name="PTR">
+                                <check name="PTR-arith-field" enabled="true" />
+                                <check name="PTR-arith-stack" enabled="true" />
+                                <check name="PTR-arith-var" enabled="true" />
+                                <check name="PTR-cmp-str-lit" enabled="true" />
+                                <check name="PTR-null-assign-fun-pos" enabled="false" />
+                                <check name="PTR-null-assign-pos" enabled="false" />
+                                <check name="PTR-null-assign" enabled="true" />
+                                <check name="PTR-null-cmp-aft" enabled="true" />
+                                <check name="PTR-null-cmp-bef-fun" enabled="true" />
+                                <check name="PTR-null-cmp-bef" enabled="true" />
+                                <check name="PTR-null-fun-pos" enabled="true" />
+                                <check name="PTR-null-literal-pos" enabled="false" />
+                                <check name="PTR-overload" enabled="false" />
+                                <check name="PTR-singleton-arith-pos" enabled="false" />
+                                <check name="PTR-singleton-arith" enabled="true" />
+                                <check name="PTR-unchk-param-some" enabled="true" />
+                                <check name="PTR-unchk-param" enabled="false" />
+                                <check name="PTR-uninit-pos" enabled="false" />
+                                <check name="PTR-uninit" enabled="true" />
+                            </group>
+                            <group enabled="true" name="RED">
+                                <check name="RED-alloc-zero-bytes" enabled="false" />
+                                <check name="RED-case-reach" enabled="false" />
+                                <check name="RED-cmp-always" enabled="false" />
+                                <check name="RED-cmp-never" enabled="false" />
+                                <check name="RED-cond-always" enabled="false" />
+                                <check name="RED-cond-const-assign" enabled="true" />
+                                <check name="RED-cond-const-expr" enabled="false" />
+                                <check name="RED-cond-const" enabled="false" />
+                                <check name="RED-cond-never" enabled="false" />
+                                <check name="RED-dead" enabled="true" />
+                                <check name="RED-expr" enabled="false" />
+                                <check name="RED-func-no-effect" enabled="false" />
+                                <check name="RED-local-hides-global" enabled="true" />
+                                <check name="RED-local-hides-local" enabled="false" />
+                                <check name="RED-local-hides-member" enabled="false" />
+                                <check name="RED-local-hides-param" enabled="true" />
+                                <check name="RED-no-effect" enabled="false" />
+                                <check name="RED-self-assign" enabled="true" />
+                                <check name="RED-unused-assign" enabled="true" />
+                                <check name="RED-unused-param" enabled="false" />
+                                <check name="RED-unused-return-val" enabled="false" />
+                                <check name="RED-unused-val" enabled="false" />
+                                <check name="RED-unused-var-all" enabled="true" />
+                            </group>
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+                                <check name="RESOURCE-deref-file" enabled="false" />
+                                <check name="RESOURCE-double-close" enabled="true" />
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+                                <check name="RESOURCE-file-pos-neg" enabled="false" />
+                                <check name="RESOURCE-file-use-after-close" enabled="true" />
+                                <check name="RESOURCE-implicit-deref-file" enabled="false" />
+                                <check name="RESOURCE-write-ronly-file" enabled="true" />
+                            </group>
+                            <group enabled="true" name="SIZEOF">
+                                <check name="SIZEOF-side-effect" enabled="true" />
+                            </group>
+                            <group enabled="true" name="SPC">
+                                <check name="SPC-order" enabled="true" />
+                                <check name="SPC-uninit-arr-all" enabled="false" />
+                                <check name="SPC-uninit-struct-field-heap" enabled="true" />
+                                <check name="SPC-uninit-struct-field" enabled="false" />
+                                <check name="SPC-uninit-struct" enabled="true" />
+                                <check name="SPC-uninit-var-all" enabled="true" />
+                                <check name="SPC-uninit-var-some" enabled="true" />
+                                <check name="SPC-volatile-reads" enabled="false" />
+                                <check name="SPC-volatile-writes" enabled="false" />
+                            </group>
+                            <group enabled="true" name="STRUCT">
+                                <check name="STRUCT-signed-bit" enabled="false" />
+                            </group>
+                            <group enabled="true" name="SWITCH">
+                                <check name="SWITCH-fall-through" enabled="true" />
+                            </group>
+                            <group enabled="true" name="UNION">
+                                <check name="UNION-overlap-assign" enabled="true" />
+                                <check name="UNION-type-punning" enabled="true" />
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+                            <group enabled="true" name="CERT-EXP">
+                                <check name="CERT-EXP19-C" enabled="true" />
+                            </group>
+                            <group enabled="true" name="CERT-FIO">
+                                <check name="CERT-FIO37-C" enabled="true" />
+                                <check name="CERT-FIO38-C" enabled="true" />
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+                            <group enabled="true" name="CERT-SIG">
+                                <check name="CERT-SIG31-C" enabled="true" />
+                            </group>
+                        </package>
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+                            <group enabled="true" name="SEC-BUFFER">
+                                <check name="SEC-BUFFER-memory-leak-alias" enabled="true" />
+                                <check name="SEC-BUFFER-memory-leak" enabled="false" />
+                                <check name="SEC-BUFFER-memset-overrun-pos" enabled="false" />
+                                <check name="SEC-BUFFER-memset-overrun" enabled="true" />
+                                <check name="SEC-BUFFER-qsort-overrun-pos" enabled="false" />
+                                <check name="SEC-BUFFER-qsort-overrun" enabled="true" />
+                                <check name="SEC-BUFFER-sprintf-overrun" enabled="true" />
+                                <check name="SEC-BUFFER-std-sort-overrun-pos" enabled="false" />
+                                <check name="SEC-BUFFER-std-sort-overrun" enabled="true" />
+                                <check name="SEC-BUFFER-strcat-overrun-pos" enabled="false" />
+                                <check name="SEC-BUFFER-strcat-overrun" enabled="true" />
+                                <check name="SEC-BUFFER-strcpy-overrun-pos" enabled="false" />
+                                <check name="SEC-BUFFER-strcpy-overrun" enabled="true" />
+                                <check name="SEC-BUFFER-strncat-overrun-pos" enabled="false" />
+                                <check name="SEC-BUFFER-strncat-overrun" enabled="true" />
+                                <check name="SEC-BUFFER-strncmp-overrun-pos" enabled="false" />
+                                <check name="SEC-BUFFER-strncmp-overrun" enabled="true" />
+                                <check name="SEC-BUFFER-strncpy-overrun-pos" enabled="false" />
+                                <check name="SEC-BUFFER-strncpy-overrun" enabled="true" />
+                                <check name="SEC-BUFFER-tainted-alloc-size" enabled="true" />
+                                <check name="SEC-BUFFER-tainted-copy-length" enabled="true" />
+                                <check name="SEC-BUFFER-tainted-copy" enabled="true" />
+                                <check name="SEC-BUFFER-tainted-index" enabled="true" />
+                                <check name="SEC-BUFFER-tainted-offset" enabled="true" />
+                                <check name="SEC-BUFFER-use-after-free-all" enabled="true" />
+                                <check name="SEC-BUFFER-use-after-free-some" enabled="true" />
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+                                <check name="SEC-DIV-0-compare-after" enabled="true" />
+                                <check name="SEC-DIV-0-compare-before" enabled="true" />
+                                <check name="SEC-DIV-0-tainted" enabled="true" />
+                            </group>
+                            <group enabled="true" name="SEC-FILEOP">
+                                <check name="SEC-FILEOP-open-no-close" enabled="true" />
+                                <check name="SEC-FILEOP-path-traversal" enabled="false" />
+                                <check name="SEC-FILEOP-use-after-close" enabled="true" />
+                            </group>
+                            <group enabled="true" name="SEC-INJECTION">
+                                <check name="SEC-INJECTION-sql" enabled="false" />
+                                <check name="SEC-INJECTION-xpath" enabled="false" />
+                            </group>
+                            <group enabled="true" name="SEC-LOOP">
+                                <check name="SEC-LOOP-tainted-bound" enabled="true" />
+                            </group>
+                            <group enabled="true" name="SEC-NULL">
+                                <check name="SEC-NULL-assignment-fun-pos" enabled="false" />
+                                <check name="SEC-NULL-assignment" enabled="true" />
+                                <check name="SEC-NULL-cmp-aft" enabled="true" />
+                                <check name="SEC-NULL-cmp-bef-fun" enabled="true" />
+                                <check name="SEC-NULL-cmp-bef" enabled="true" />
+                                <check name="SEC-NULL-literal-pos" enabled="false" />
+                            </group>
+                            <group enabled="true" name="SEC-STRING">
+                                <check name="SEC-STRING-format-string" enabled="true" />
+                                <check name="SEC-STRING-hard-coded-credentials" enabled="false" />
+                            </group>
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+                                <check name="MISRAC2004-1.2_h" enabled="true" />
+                                <check name="MISRAC2004-1.2_i" enabled="true" />
+                                <check name="MISRAC2004-1.2_j" enabled="true" />
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+                                <check name="MISRAC2004-2.4" enabled="false" />
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+                                <check name="MISRAC2004-5.6" enabled="false" />
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+                                <check name="MISRAC2004-7.1" enabled="true" />
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+                                <check name="MISRAC2004-8.1" enabled="true" />
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+                                <check name="MISRAC2004-9.1_c" enabled="true" />
+                                <check name="MISRAC2004-9.2" enabled="true" />
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+                                <check name="MISRAC2004-11.5" enabled="true" />
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+                                <check name="MISRAC2004-13.3" enabled="true" />
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+                                <check name="MISRAC++2008-5-2-7" enabled="true" />
+                                <check name="MISRAC++2008-5-2-9" enabled="false" />
+                                <check name="MISRAC++2008-5-2-10" enabled="false" />
+                                <check name="MISRAC++2008-5-2-11_a" enabled="true" />
+                                <check name="MISRAC++2008-5-2-11_b" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-5-3">
+                                <check name="MISRAC++2008-5-3-1" enabled="true" />
+                                <check name="MISRAC++2008-5-3-2_a" enabled="true" />
+                                <check name="MISRAC++2008-5-3-2_b" enabled="true" />
+                                <check name="MISRAC++2008-5-3-3" enabled="true" />
+                                <check name="MISRAC++2008-5-3-4" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-5-8">
+                                <check name="MISRAC++2008-5-8-1" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-5-14">
+                                <check name="MISRAC++2008-5-14-1" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-5-18">
+                                <check name="MISRAC++2008-5-18-1" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-5-19">
+                                <check name="MISRAC++2008-5-19-1" enabled="false" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-6-2">
+                                <check name="MISRAC++2008-6-2-1" enabled="true" />
+                                <check name="MISRAC++2008-6-2-2" enabled="true" />
+                                <check name="MISRAC++2008-6-2-3" enabled="false" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-6-3">
+                                <check name="MISRAC++2008-6-3-1_a" enabled="true" />
+                                <check name="MISRAC++2008-6-3-1_b" enabled="true" />
+                                <check name="MISRAC++2008-6-3-1_c" enabled="true" />
+                                <check name="MISRAC++2008-6-3-1_d" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-6-4">
+                                <check name="MISRAC++2008-6-4-1" enabled="true" />
+                                <check name="MISRAC++2008-6-4-2" enabled="true" />
+                                <check name="MISRAC++2008-6-4-3" enabled="true" />
+                                <check name="MISRAC++2008-6-4-4" enabled="true" />
+                                <check name="MISRAC++2008-6-4-5" enabled="true" />
+                                <check name="MISRAC++2008-6-4-6" enabled="true" />
+                                <check name="MISRAC++2008-6-4-7" enabled="true" />
+                                <check name="MISRAC++2008-6-4-8" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-6-5">
+                                <check name="MISRAC++2008-6-5-1_a" enabled="true" />
+                                <check name="MISRAC++2008-6-5-2" enabled="true" />
+                                <check name="MISRAC++2008-6-5-3" enabled="true" />
+                                <check name="MISRAC++2008-6-5-4" enabled="true" />
+                                <check name="MISRAC++2008-6-5-6" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-6-6">
+                                <check name="MISRAC++2008-6-6-1" enabled="true" />
+                                <check name="MISRAC++2008-6-6-2" enabled="true" />
+                                <check name="MISRAC++2008-6-6-4" enabled="true" />
+                                <check name="MISRAC++2008-6-6-5" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-7-1">
+                                <check name="MISRAC++2008-7-1-1" enabled="true" />
+                                <check name="MISRAC++2008-7-1-2" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-7-2">
+                                <check name="MISRAC++2008-7-2-1" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-7-4">
+                                <check name="MISRAC++2008-7-4-3" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-7-5">
+                                <check name="MISRAC++2008-7-5-1_a" enabled="true" />
+                                <check name="MISRAC++2008-7-5-1_b" enabled="true" />
+                                <check name="MISRAC++2008-7-5-2_a" enabled="true" />
+                                <check name="MISRAC++2008-7-5-2_b" enabled="true" />
+                                <check name="MISRAC++2008-7-5-2_c" enabled="true" />
+                                <check name="MISRAC++2008-7-5-2_d" enabled="true" />
+                                <check name="MISRAC++2008-7-5-4_a" enabled="false" />
+                                <check name="MISRAC++2008-7-5-4_b" enabled="false" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-8-0">
+                                <check name="MISRAC++2008-8-0-1" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-8-4">
+                                <check name="MISRAC++2008-8-4-1" enabled="true" />
+                                <check name="MISRAC++2008-8-4-3" enabled="true" />
+                                <check name="MISRAC++2008-8-4-4" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-8-5">
+                                <check name="MISRAC++2008-8-5-1_a" enabled="true" />
+                                <check name="MISRAC++2008-8-5-1_b" enabled="true" />
+                                <check name="MISRAC++2008-8-5-1_c" enabled="true" />
+                                <check name="MISRAC++2008-8-5-2" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-9-3">
+                                <check name="MISRAC++2008-9-3-1" enabled="true" />
+                                <check name="MISRAC++2008-9-3-2" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-9-5">
+                                <check name="MISRAC++2008-9-5-1" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-9-6">
+                                <check name="MISRAC++2008-9-6-2" enabled="true" />
+                                <check name="MISRAC++2008-9-6-3" enabled="true" />
+                                <check name="MISRAC++2008-9-6-4" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-12-1">
+                                <check name="MISRAC++2008-12-1-1_a" enabled="true" />
+                                <check name="MISRAC++2008-12-1-1_b" enabled="true" />
+                                <check name="MISRAC++2008-12-1-3" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-16-0">
+                                <check name="MISRAC++2008-16-0-3" enabled="true" />
+                                <check name="MISRAC++2008-16-0-4" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-16-2">
+                                <check name="MISRAC++2008-16-2-2" enabled="true" />
+                                <check name="MISRAC++2008-16-2-3" enabled="true" />
+                                <check name="MISRAC++2008-16-2-4" enabled="true" />
+                                <check name="MISRAC++2008-16-2-5" enabled="false" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-16-3">
+                                <check name="MISRAC++2008-16-3-1" enabled="true" />
+                                <check name="MISRAC++2008-16-3-2" enabled="false" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-17-0">
+                                <check name="MISRAC++2008-17-0-1" enabled="true" />
+                                <check name="MISRAC++2008-17-0-3" enabled="true" />
+                                <check name="MISRAC++2008-17-0-5" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-18-0">
+                                <check name="MISRAC++2008-18-0-1" enabled="true" />
+                                <check name="MISRAC++2008-18-0-2" enabled="true" />
+                                <check name="MISRAC++2008-18-0-3" enabled="true" />
+                                <check name="MISRAC++2008-18-0-4" enabled="true" />
+                                <check name="MISRAC++2008-18-0-5" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-18-2">
+                                <check name="MISRAC++2008-18-2-1" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-18-4">
+                                <check name="MISRAC++2008-18-4-1" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-18-7">
+                                <check name="MISRAC++2008-18-7-1" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-19-3">
+                                <check name="MISRAC++2008-19-3-1" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-27-0">
+                                <check name="MISRAC++2008-27-0-1" enabled="true" />
+                            </group>
+                        </package>
+                    </checks_tree>
+                </cstat_settings>
+            </data>
+        </settings>
+    </configuration>
+    <group>
+        <name>board</name>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\2_Ebyte_Board_Support\E15-EVB02\board.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\2_Ebyte_Board_Support\E15-EVB02\board_button.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\2_Ebyte_Board_Support\E15-EVB02\board_mini_printf.c</name>
+        </file>
+    </group>
+    <group>
+        <name>drivers/ebyte</name>
+        <group>
+            <name>CMT2310A</name>
+            <file>
+                <name>$PROJ_DIR$\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx\cmt2310a_410mhz.c</name>
+            </file>
+            <file>
+                <name>$PROJ_DIR$\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx\cmt2310a_433mhz.c</name>
+            </file>
+            <file>
+                <name>$PROJ_DIR$\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx\cmt2310a_868mhz.c</name>
+            </file>
+            <file>
+                <name>$PROJ_DIR$\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx\cmt2310a_915mhz.c</name>
+            </file>
+            <file>
+                <name>$PROJ_DIR$\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx\ebyte_e48x.c</name>
+            </file>
+            <file>
+                <name>$PROJ_DIR$\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx\radio.c</name>
+            </file>
+            <file>
+                <name>$PROJ_DIR$\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx\radio_hal.c</name>
+            </file>
+            <file>
+                <name>$PROJ_DIR$\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx\radio_mac.c</name>
+            </file>
+            <file>
+                <name>$PROJ_DIR$\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx\radio_phy.c</name>
+            </file>
+            <file>
+                <name>$PROJ_DIR$\..\..\..\3_Ebyte_WirelessModule_Drivers\E48xMx\radio_spi.c</name>
+            </file>
+        </group>
+        <group>
+            <name>sub</name>
+            <file>
+                <name>$PROJ_DIR$\ebyte\ebyte_callback.c</name>
+            </file>
+            <file>
+                <name>$PROJ_DIR$\ebyte\ebyte_conf.h</name>
+            </file>
+            <file>
+                <name>$PROJ_DIR$\ebyte\ebyte_port.c</name>
+            </file>
+        </group>
+        <file>
+            <name>$PROJ_DIR$\ebyte\ebyte_core.c</name>
+        </file>
+    </group>
+    <group>
+        <name>drivers/mcu</name>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_adc.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_aes.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_beep.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_clk.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_comp.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_dac.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_dma.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_exti.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_flash.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_gpio.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_i2c.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_irtim.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_itc.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_iwdg.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_lcd.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_pwr.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_rst.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_rtc.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_spi.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_syscfg.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_tim1.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_tim2.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_tim3.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_tim4.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_tim5.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_usart.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_wfe.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\4_STM8_L15x_StdPeriph_Drivers\src\stm8l15x_wwdg.c</name>
+        </file>
+    </group>
+    <group>
+        <name>main</name>
+        <file>
+            <name>$PROJ_DIR$\main.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\stm8l15x_it.c</name>
+        </file>
+    </group>
+    <group>
+        <name>middleware</name>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\1_Middleware\Produce\ebyte_debug.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\1_Middleware\Kfifo\ebyte_kfifo.c</name>
+        </file>
+    </group>
+</project>
diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/project.eww b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/project.eww
new file mode 100755
index 0000000..1f54bcd
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/project.eww
@@ -0,0 +1,7 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<workspace>
+    <project>
+        <path>$WS_DIR$\project.ewp</path>
+    </project>
+    <batchBuild />
+</workspace>
diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/settings/project.Debug.cspy.bat b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/settings/project.Debug.cspy.bat
new file mode 100755
index 0000000..2718b7f
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/settings/project.Debug.cspy.bat
@@ -0,0 +1,40 @@
+@REM This batch file has been generated by the IAR Embedded Workbench
+@REM C-SPY Debugger, as an aid to preparing a command line for running
+@REM the cspybat command line utility using the appropriate settings.
+@REM
+@REM Note that this file is generated every time a new debug session
+@REM is initialized, so you may want to move or rename the file before
+@REM making changes.
+@REM
+@REM You can launch cspybat by typing the name of this batch file followed
+@REM by the name of the debug file (usually an ELF/DWARF or UBROF file).
+@REM
+@REM Read about available command line parameters in the C-SPY Debugging
+@REM Guide. Hints about additional command line parameters that may be
+@REM useful in specific cases:
+@REM   --download_only   Downloads a code image without starting a debug
+@REM                     session afterwards.
+@REM   --silent          Omits the sign-on message.
+@REM   --timeout         Limits the maximum allowed execution time.
+@REM 
+
+
+@echo off 
+
+if not "%~1" == "" goto debugFile 
+
+@echo on 
+
+"D:\software\IAR_EW\IAR_STM8_310\common\bin\cspybat" -f "D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\settings\project.Debug.general.xcl" --backend -f "D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\settings\project.Debug.driver.xcl" 
+
+@echo off 
+goto end 
+
+:debugFile 
+
+@echo on 
+
+"D:\software\IAR_EW\IAR_STM8_310\common\bin\cspybat" -f "D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\settings\project.Debug.general.xcl" "--debug_file=%~1" --backend -f "D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\settings\project.Debug.driver.xcl" 
+
+@echo off 
+:end
\ No newline at end of file
diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/settings/project.Debug.cspy.ps1 b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/settings/project.Debug.cspy.ps1
new file mode 100755
index 0000000..b30e6e9
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/settings/project.Debug.cspy.ps1
@@ -0,0 +1,31 @@
+param([String]$debugfile = "");
+
+# This powershell file has been generated by the IAR Embedded Workbench
+# C - SPY Debugger, as an aid to preparing a command line for running
+# the cspybat command line utility using the appropriate settings.
+#
+# Note that this file is generated every time a new debug session
+# is initialized, so you may want to move or rename the file before
+# making changes.
+#
+# You can launch cspybat by typing Powershell.exe -File followed by the name of this batch file, followed
+# by the name of the debug file (usually an ELF / DWARF or UBROF file).
+#
+# Read about available command line parameters in the C - SPY Debugging
+# Guide. Hints about additional command line parameters that may be
+# useful in specific cases :
+#   --download_only   Downloads a code image without starting a debug
+#                     session afterwards.
+#   --silent          Omits the sign - on message.
+#   --timeout         Limits the maximum allowed execution time.
+#
+
+
+if ($debugfile -eq "")
+{
+& "D:\software\IAR_EW\IAR_STM8_310\common\bin\cspybat" -f "D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\settings\project.Debug.general.xcl" --backend -f "D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\settings\project.Debug.driver.xcl" 
+}
+else
+{
+& "D:\software\IAR_EW\IAR_STM8_310\common\bin\cspybat" -f "D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\settings\project.Debug.general.xcl" --debug_file=$debugfile --backend -f "D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\settings\project.Debug.driver.xcl" 
+}
diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/settings/project.Debug.driver.xcl b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/settings/project.Debug.driver.xcl
new file mode 100755
index 0000000..d49d16a
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/settings/project.Debug.driver.xcl
@@ -0,0 +1,11 @@
+"-p" 
+
+"D:\software\IAR_EW\IAR_STM8_310\stm8\config\ddf\iostm8l151g4.ddf" 
+
+"--mcuname" 
+
+"STM8L151G4" 
+
+
+
+
diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/settings/project.Debug.general.xcl b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/settings/project.Debug.general.xcl
new file mode 100755
index 0000000..ea4b03f
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/settings/project.Debug.general.xcl
@@ -0,0 +1,11 @@
+"D:\software\IAR_EW\IAR_STM8_310\stm8\bin\stm8proc.dll" 
+
+"D:\software\IAR_EW\IAR_STM8_310\stm8\bin\stm8stlink.dll" 
+
+"D:\Project_UART\E48\E48-XXXM20S\PROGRAM_FILE\E15-EVB02-E48-DEMO\0_Project\IAR_for_Stm8\Uart_PingPong\Debug\Exe\project.out" 
+
+--plugin "D:\software\IAR_EW\IAR_STM8_310\stm8\bin\stm8bat.dll" 
+
+
+
+
diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/settings/project.Release.cspy.bat b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/settings/project.Release.cspy.bat
new file mode 100755
index 0000000..5133303
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/settings/project.Release.cspy.bat
@@ -0,0 +1,40 @@
+@REM This batch file has been generated by the IAR Embedded Workbench
+@REM C-SPY Debugger, as an aid to preparing a command line for running
+@REM the cspybat command line utility using the appropriate settings.
+@REM
+@REM Note that this file is generated every time a new debug session
+@REM is initialized, so you may want to move or rename the file before
+@REM making changes.
+@REM
+@REM You can launch cspybat by typing the name of this batch file followed
+@REM by the name of the debug file (usually an ELF/DWARF or UBROF file).
+@REM
+@REM Read about available command line parameters in the C-SPY Debugging
+@REM Guide. Hints about additional command line parameters that may be
+@REM useful in specific cases:
+@REM   --download_only   Downloads a code image without starting a debug
+@REM                     session afterwards.
+@REM   --silent          Omits the sign-on message.
+@REM   --timeout         Limits the maximum allowed execution time.
+@REM 
+
+
+@echo off 
+
+if not "%~1" == "" goto debugFile 
+
+@echo on 
+
+"F:\01_JH_Software\IAR\Install_ForStm8\common\bin\cspybat" -f "E:\Ebyte_Product\0_Ebyte\E15\E15-EVB02\Software\2021-05-06-Project\0_Project\IAR_for_Stm8\Uart_PingPong\settings\project.Release.general.xcl" --backend -f "E:\Ebyte_Product\0_Ebyte\E15\E15-EVB02\Software\2021-05-06-Project\0_Project\IAR_for_Stm8\Uart_PingPong\settings\project.Release.driver.xcl" 
+
+@echo off 
+goto end 
+
+:debugFile 
+
+@echo on 
+
+"F:\01_JH_Software\IAR\Install_ForStm8\common\bin\cspybat" -f "E:\Ebyte_Product\0_Ebyte\E15\E15-EVB02\Software\2021-05-06-Project\0_Project\IAR_for_Stm8\Uart_PingPong\settings\project.Release.general.xcl" "--debug_file=%~1" --backend -f "E:\Ebyte_Product\0_Ebyte\E15\E15-EVB02\Software\2021-05-06-Project\0_Project\IAR_for_Stm8\Uart_PingPong\settings\project.Release.driver.xcl" 
+
+@echo off 
+:end
\ No newline at end of file
diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/settings/project.Release.cspy.ps1 b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/settings/project.Release.cspy.ps1
new file mode 100755
index 0000000..ad54f25
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/settings/project.Release.cspy.ps1
@@ -0,0 +1,31 @@
+param([String]$debugfile = "");
+
+# This powershell file has been generated by the IAR Embedded Workbench
+# C - SPY Debugger, as an aid to preparing a command line for running
+# the cspybat command line utility using the appropriate settings.
+#
+# Note that this file is generated every time a new debug session
+# is initialized, so you may want to move or rename the file before
+# making changes.
+#
+# You can launch cspybat by typing Powershell.exe -File followed by the name of this batch file, followed
+# by the name of the debug file (usually an ELF / DWARF or UBROF file).
+#
+# Read about available command line parameters in the C - SPY Debugging
+# Guide. Hints about additional command line parameters that may be
+# useful in specific cases :
+#   --download_only   Downloads a code image without starting a debug
+#                     session afterwards.
+#   --silent          Omits the sign - on message.
+#   --timeout         Limits the maximum allowed execution time.
+#
+
+
+if ($debugfile -eq "")
+{
+& "F:\01_JH_Software\IAR\Install_ForStm8\common\bin\cspybat" -f "E:\Ebyte_Product\0_Ebyte\E15\E15-EVB02\Software\2021-05-06-Project\0_Project\IAR_for_Stm8\Uart_PingPong\settings\project.Release.general.xcl" --backend -f "E:\Ebyte_Product\0_Ebyte\E15\E15-EVB02\Software\2021-05-06-Project\0_Project\IAR_for_Stm8\Uart_PingPong\settings\project.Release.driver.xcl" 
+}
+else
+{
+& "F:\01_JH_Software\IAR\Install_ForStm8\common\bin\cspybat" -f "E:\Ebyte_Product\0_Ebyte\E15\E15-EVB02\Software\2021-05-06-Project\0_Project\IAR_for_Stm8\Uart_PingPong\settings\project.Release.general.xcl" --debug_file=$debugfile --backend -f "E:\Ebyte_Product\0_Ebyte\E15\E15-EVB02\Software\2021-05-06-Project\0_Project\IAR_for_Stm8\Uart_PingPong\settings\project.Release.driver.xcl" 
+}
diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/settings/project.Release.driver.xcl b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/settings/project.Release.driver.xcl
new file mode 100755
index 0000000..41e459f
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/settings/project.Release.driver.xcl
@@ -0,0 +1,7 @@
+"-p" 
+
+"F:\01_JH_Software\IAR\Install_ForStm8\stm8\config\ddf\iostm8.ddf" 
+
+
+
+
diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/settings/project.Release.general.xcl b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/settings/project.Release.general.xcl
new file mode 100755
index 0000000..3253b97
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/settings/project.Release.general.xcl
@@ -0,0 +1,11 @@
+"F:\01_JH_Software\IAR\Install_ForStm8\stm8\bin\stm8proc.dll" 
+
+"F:\01_JH_Software\IAR\Install_ForStm8\stm8\bin\stm8sim.dll" 
+
+"E:\Ebyte_Product\0_Ebyte\E15\E15-EVB02\Software\2021-05-06-Project\0_Project\IAR_for_Stm8\Uart_PingPong\Release\Exe\project.out" 
+
+--plugin "F:\01_JH_Software\IAR\Install_ForStm8\stm8\bin\stm8bat.dll" 
+
+
+
+
diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/settings/project.dbgdt b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/settings/project.dbgdt
new file mode 100755
index 0000000..d1ce11a
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/settings/project.dbgdt
@@ -0,0 +1,1079 @@
+<?xml version="1.0"?>
+<Project>
+    <WindowStorage>
+        <ChildIdMap>
+            <TB_DEBUG>34048</TB_DEBUG>
+            <TB_MAIN>34049</TB_MAIN>
+            <WIN_AUTO>34050</WIN_AUTO>
+            <WIN_BREAKPOINTS>34051</WIN_BREAKPOINTS>
+            <WIN_BUILD>34052</WIN_BUILD>
+            <WIN_CALL_GRAPH>34053</WIN_CALL_GRAPH>
+            <WIN_CALL_STACK>34054</WIN_CALL_STACK>
+            <WIN_CODE_COVERAGE>34055</WIN_CODE_COVERAGE>
+            <WIN_CORES>34056</WIN_CORES>
+            <WIN_CUSTOM_SFR>34057</WIN_CUSTOM_SFR>
+            <WIN_C_STAT>34058</WIN_C_STAT>
+            <WIN_DATA_LOG>34059</WIN_DATA_LOG>
+            <WIN_DATA_STAT>34060</WIN_DATA_STAT>
+            <WIN_DEBUGGER_MACROS>34061</WIN_DEBUGGER_MACROS>
+            <WIN_DEBUG_LOG>34062</WIN_DEBUG_LOG>
+            <WIN_DISASSEMBLY>34063</WIN_DISASSEMBLY>
+            <WIN_FIND_ALL_DECLARATIONS>34064</WIN_FIND_ALL_DECLARATIONS>
+            <WIN_FIND_ALL_REFERENCES>34065</WIN_FIND_ALL_REFERENCES>
+            <WIN_FIND_IN_FILES>34066</WIN_FIND_IN_FILES>
+            <WIN_FIND_IN_SLIDING_TRACE>34067</WIN_FIND_IN_SLIDING_TRACE>
+            <WIN_IMAGES>34068</WIN_IMAGES>
+            <WIN_INTERRUPT_LOG>34069</WIN_INTERRUPT_LOG>
+            <WIN_INTERRUPT_STAT>34070</WIN_INTERRUPT_STAT>
+            <WIN_LOCALS>34071</WIN_LOCALS>
+            <WIN_MACRO_EVAL>34072</WIN_MACRO_EVAL>
+            <WIN_MACRO_REGISTRATION>34073</WIN_MACRO_REGISTRATION>
+            <WIN_MEMORY_1>34074</WIN_MEMORY_1>
+            <WIN_MEMORY_2>34075</WIN_MEMORY_2>
+            <WIN_MEMORY_3>34076</WIN_MEMORY_3>
+            <WIN_MEMORY_4>34077</WIN_MEMORY_4>
+            <WIN_PHYSICAL_BREAKPOINTS>34078</WIN_PHYSICAL_BREAKPOINTS>
+            <WIN_PROFILING2>34079</WIN_PROFILING2>
+            <WIN_QUICK_WATCH>34080</WIN_QUICK_WATCH>
+            <WIN_REGISTER_1>34081</WIN_REGISTER_1>
+            <WIN_REGISTER_2>34082</WIN_REGISTER_2>
+            <WIN_REGISTER_3>34083</WIN_REGISTER_3>
+            <WIN_REGISTER_4>34084</WIN_REGISTER_4>
+            <WIN_REGISTER_GROUPS>34085</WIN_REGISTER_GROUPS>
+            <WIN_SELECT_AMBIGUOUS_DEFINITIONS>34086</WIN_SELECT_AMBIGUOUS_DEFINITIONS>
+            <WIN_SLIDING_FUNCTION_TRACE>34087</WIN_SLIDING_FUNCTION_TRACE>
+            <WIN_SLIDING_TRACE_WINDOW>34088</WIN_SLIDING_TRACE_WINDOW>
+            <WIN_SOURCE_BROWSER>34089</WIN_SOURCE_BROWSER>
+            <WIN_STACK_1>34090</WIN_STACK_1>
+            <WIN_STACK_2>34091</WIN_STACK_2>
+            <WIN_STATICS>34092</WIN_STATICS>
+            <WIN_STATIC_WATCH>34093</WIN_STATIC_WATCH>
+            <WIN_SYMBOLIC_MEMORY>34094</WIN_SYMBOLIC_MEMORY>
+            <WIN_SYMBOLS>34095</WIN_SYMBOLS>
+            <WIN_TERM_IO>34096</WIN_TERM_IO>
+            <WIN_TIMELINE_GRAPH>34097</WIN_TIMELINE_GRAPH>
+            <WIN_TOOL_OUTPUT>34098</WIN_TOOL_OUTPUT>
+            <WIN_TRACE_EXPR>34099</WIN_TRACE_EXPR>
+            <WIN_TS_INTERRUPT_AVAILABLE>34100</WIN_TS_INTERRUPT_AVAILABLE>
+            <WIN_TS_INTERRUPT_CONFIG>34101</WIN_TS_INTERRUPT_CONFIG>
+            <WIN_TS_INTERRUPT_STATUS>34102</WIN_TS_INTERRUPT_STATUS>
+            <WIN_WATCH_1>34103</WIN_WATCH_1>
+            <WIN_WATCH_2>34104</WIN_WATCH_2>
+            <WIN_WATCH_3>34105</WIN_WATCH_3>
+            <WIN_WATCH_4>34106</WIN_WATCH_4>
+            <WIN_WORKSPACE>34107</WIN_WORKSPACE>
+            <WIN_DATA_SAMPLE>34108</WIN_DATA_SAMPLE>
+            <WIN_DATA_SAMPLE_SETUP>34109</WIN_DATA_SAMPLE_SETUP>
+            <WIN_WALLTIMELINE_GRAPH>34110</WIN_WALLTIMELINE_GRAPH>
+        </ChildIdMap>
+        <Desktop>
+            <IarPane-34048>
+                <ToolBarCmdIds>
+                    <item>34390</item>
+                    <item>34323</item>
+                    <item>34398</item>
+                    <item>34400</item>
+                    <item>34397</item>
+                    <item>34320</item>
+                    <item>34321</item>
+                    <item>34324</item>
+                    <item>0</item>
+                </ToolBarCmdIds>
+            </IarPane-34048>
+            <IarPane-34049>
+                <ToolBarCmdIds>
+                    <item>57600</item>
+                    <item>57601</item>
+                    <item>57603</item>
+                    <item>33024</item>
+                    <item>0</item>
+                    <item>57607</item>
+                    <item>0</item>
+                    <item>57635</item>
+                    <item>57634</item>
+                    <item>57637</item>
+                    <item>0</item>
+                    <item>57643</item>
+                    <item>57644</item>
+                    <item>0</item>
+                    <item>33090</item>
+                    <item>33057</item>
+                    <item>57636</item>
+                    <item>57640</item>
+                    <item>57641</item>
+                    <item>33026</item>
+                    <item>33065</item>
+                    <item>33063</item>
+                    <item>33064</item>
+                    <item>33053</item>
+                    <item>33054</item>
+                    <item>0</item>
+                    <item>33035</item>
+                    <item>33036</item>
+                    <item>34399</item>
+                    <item>0</item>
+                    <item>33055</item>
+                    <item>33056</item>
+                    <item>33094</item>
+                    <item>0</item>
+                </ToolBarCmdIds>
+            </IarPane-34049>
+            <ControlBarVersion>
+                <Major>14</Major>
+                <Minor>32</Minor>
+            </ControlBarVersion>
+            <MFCToolBarParameters>
+                <Tooltips>1</Tooltips>
+                <ShortcutKeys>1</ShortcutKeys>
+                <LargeIcons>0</LargeIcons>
+                <MenuAnimation>0</MenuAnimation>
+                <RecentlyUsedMenus>1</RecentlyUsedMenus>
+                <MenuShadows>1</MenuShadows>
+                <ShowAllMenusAfterDelay>1</ShowAllMenusAfterDelay>
+                <CommandsUsage>1C0200001F005984000001000000138600000100000040E100000100000019800000010000002CE100000300000026810000010000001086000021010000488100000100000015810000010000000481000002000000AF0600000100000020810000010000000C810000010000001D810000420000000D800000010000005E8400000600000001DE00000F0000002BE10000020000001481000001000000558400000300000000810000010000001F810000010000000E8100000100000000E1000002000000148600000B0000000584000001000000118600002700000002840000010000004681000070000000108400000B0000001E81000006000000</CommandsUsage>
+            </MFCToolBarParameters>
+            <CommandManager>
+                <CommandsWithoutImages>08000D8400000F84000008840000FFFFFFFF54840000328100001C81000009840000</CommandsWithoutImages>
+                <MenuUserImages>04000E8400007E00000030840000800000000B8100004D0000000D8100004F000000</MenuUserImages>
+            </CommandManager>
+            <Pane-59393>
+                <ID>0</ID>
+                <RectRecentFloat>0A0000000A0000006E0000006E000000</RectRecentFloat>
+                <RectRecentDocked>00000000DE03000080070000F1030000</RectRecentDocked>
+                <RecentFrameAlignment>4096</RecentFrameAlignment>
+                <RecentRowIndex>0</RecentRowIndex>
+                <IsFloating>0</IsFloating>
+                <MRUWidth>32767</MRUWidth>
+                <PinState>0</PinState>
+            </Pane-59393>
+            <BasePane-59393>
+                <IsVisible>1</IsVisible>
+            </BasePane-59393>
+            <Pane-34050>
+                <ID>34050</ID>
+                <RectRecentFloat>00000000170000000601000078010000</RectRecentFloat>
+                <RectRecentDocked>00000000000000000601000061010000</RectRecentDocked>
+                <RecentFrameAlignment>16384</RecentFrameAlignment>
+                <RecentRowIndex>0</RecentRowIndex>
+                <IsFloating>0</IsFloating>
+                <MRUWidth>32767</MRUWidth>
+                <PinState>0</PinState>
+            </Pane-34050>
+            <BasePane-34050>
+                <IsVisible>0</IsVisible>
+            </BasePane-34050>
+            <IarPane-34050 />
+            <Pane-34051>
+                <ID>34051</ID>
+                <RectRecentFloat>000000001700000022010000C8000000</RectRecentFloat>
+                <RectRecentDocked>000000000000000022010000B1000000</RectRecentDocked>
+                <RecentFrameAlignment>32768</RecentFrameAlignment>
+                <RecentRowIndex>0</RecentRowIndex>
+                <IsFloating>0</IsFloating>
+                <MRUWidth>32767</MRUWidth>
+                <PinState>0</PinState>
+            </Pane-34051>
+            <BasePane-34051>
+                <IsVisible>0</IsVisible>
+            </BasePane-34051>
+            <Pane--1>
+                <ID>4294967295</ID>
+                <RectRecentFloat>000000004B0000000701000040030000</RectRecentFloat>
+                <RectRecentDocked>00000000340000000701000029030000</RectRecentDocked>
+                <RecentFrameAlignment>4096</RecentFrameAlignment>
+                <RecentRowIndex>0</RecentRowIndex>
+                <IsFloating>0</IsFloating>
+                <MRUWidth>32767</MRUWidth>
+                <PinState>0</PinState>
+            </Pane--1>
+            <BasePane--1>
+                <IsVisible>1</IsVisible>
+            </BasePane--1>
+            <Pane-34052>
+                <ID>34052</ID>
+                <RectRecentFloat>000000001700000022010000C8000000</RectRecentFloat>
+                <RectRecentDocked>04000000450300007C070000C4030000</RectRecentDocked>
+                <RecentFrameAlignment>32768</RecentFrameAlignment>
+                <RecentRowIndex>0</RecentRowIndex>
+                <IsFloating>0</IsFloating>
+                <MRUWidth>32767</MRUWidth>
+                <PinState>0</PinState>
+            </Pane-34052>
+            <BasePane-34052>
+                <IsVisible>0</IsVisible>
+            </BasePane-34052>
+            <Pane-34062>
+                <ID>34062</ID>
+                <RectRecentFloat>000000001700000022010000C8000000</RectRecentFloat>
+                <RectRecentDocked>000000004103000080070000DE030000</RectRecentDocked>
+                <RecentFrameAlignment>4096</RecentFrameAlignment>
+                <RecentRowIndex>0</RecentRowIndex>
+                <IsFloating>0</IsFloating>
+                <MRUWidth>32767</MRUWidth>
+                <PinState>0</PinState>
+            </Pane-34062>
+            <BasePane-34062>
+                <IsVisible>1</IsVisible>
+            </BasePane-34062>
+            <Pane-34064>
+                <ID>34064</ID>
+                <RectRecentFloat>000000001700000022010000C8000000</RectRecentFloat>
+                <RectRecentDocked>04000000450300007C070000C4030000</RectRecentDocked>
+                <RecentFrameAlignment>4096</RecentFrameAlignment>
+                <RecentRowIndex>0</RecentRowIndex>
+                <IsFloating>0</IsFloating>
+                <MRUWidth>32767</MRUWidth>
+                <PinState>0</PinState>
+            </Pane-34064>
+            <BasePane-34064>
+                <IsVisible>0</IsVisible>
+            </BasePane-34064>
+            <Pane-34065>
+                <ID>34065</ID>
+                <RectRecentFloat>000000001700000022010000C8000000</RectRecentFloat>
+                <RectRecentDocked>04000000450300007C070000C4030000</RectRecentDocked>
+                <RecentFrameAlignment>4096</RecentFrameAlignment>
+                <RecentRowIndex>0</RecentRowIndex>
+                <IsFloating>0</IsFloating>
+                <MRUWidth>32767</MRUWidth>
+                <PinState>0</PinState>
+            </Pane-34065>
+            <BasePane-34065>
+                <IsVisible>0</IsVisible>
+            </BasePane-34065>
+            <Pane-34066>
+                <ID>34066</ID>
+                <RectRecentFloat>000000001700000022010000C8000000</RectRecentFloat>
+                <RectRecentDocked>04000000450300007C070000C4030000</RectRecentDocked>
+                <RecentFrameAlignment>4096</RecentFrameAlignment>
+                <RecentRowIndex>0</RecentRowIndex>
+                <IsFloating>0</IsFloating>
+                <MRUWidth>32767</MRUWidth>
+                <PinState>0</PinState>
+            </Pane-34066>
+            <BasePane-34066>
+                <IsVisible>0</IsVisible>
+            </BasePane-34066>
+            <Pane-34086>
+                <ID>34086</ID>
+                <RectRecentFloat>000000001700000022010000C8000000</RectRecentFloat>
+                <RectRecentDocked>04000000450300007C070000C4030000</RectRecentDocked>
+                <RecentFrameAlignment>4096</RecentFrameAlignment>
+                <RecentRowIndex>0</RecentRowIndex>
+                <IsFloating>0</IsFloating>
+                <MRUWidth>32767</MRUWidth>
+                <PinState>0</PinState>
+            </Pane-34086>
+            <BasePane-34086>
+                <IsVisible>0</IsVisible>
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diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/settings/project.dnx b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/settings/project.dnx
new file mode 100755
index 0000000..2988ffc
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/settings/project.dnx
@@ -0,0 +1,103 @@
+<?xml version="1.0"?>
+<settings>
+    <Stack>
+        <FillEnabled>0</FillEnabled>
+        <OverflowWarningsEnabled>1</OverflowWarningsEnabled>
+        <WarningThreshold>90</WarningThreshold>
+        <SpWarningsEnabled>1</SpWarningsEnabled>
+        <WarnLogOnly>1</WarnLogOnly>
+        <UseTrigger>1</UseTrigger>
+        <TriggerName>main</TriggerName>
+        <LimitSize>0</LimitSize>
+        <ByteLimit>50</ByteLimit>
+    </Stack>
+    <Trace1>
+        <Enabled>0</Enabled>
+        <ShowSource>1</ShowSource>
+    </Trace1>
+    <DebugChecksum>
+        <Checksum>138367307</Checksum>
+    </DebugChecksum>
+    <CodeCoverage>
+        <Enabled>_ 0</Enabled>
+    </CodeCoverage>
+    <Disassembly>
+        <InstrCount>0</InstrCount>
+        <MixedMode>1</MixedMode>
+    </Disassembly>
+    <DriverProfiling>
+        <Enabled>0</Enabled>
+        <Mode>1</Mode>
+        <Graph>0</Graph>
+        <Symbiont>0</Symbiont>
+        <Exclusions />
+    </DriverProfiling>
+    <CallStackLog>
+        <Enabled>0</Enabled>
+    </CallStackLog>
+    <CallStackStripe>
+        <ShowTiming>1</ShowTiming>
+    </CallStackStripe>
+    <CallStack>
+        <ShowArgs>0</ShowArgs>
+    </CallStack>
+    <InterruptLog>
+        <LogEnabled>0</LogEnabled>
+        <GraphEnabled>0</GraphEnabled>
+        <ShowTimeLog>1</ShowTimeLog>
+        <SumEnabled>0</SumEnabled>
+        <ShowTimeSum>1</ShowTimeSum>
+        <SumSortOrder>0</SumSortOrder>
+    </InterruptLog>
+    <DataLog>
+        <LogEnabled>0</LogEnabled>
+        <GraphEnabled>0</GraphEnabled>
+        <ShowTimeLog>1</ShowTimeLog>
+        <SumEnabled>0</SumEnabled>
+        <ShowTimeSum>1</ShowTimeSum>
+    </DataLog>
+    <Breakpoints2>
+        <Count>0</Count>
+    </Breakpoints2>
+    <Interrupts>
+        <Enabled>1</Enabled>
+    </Interrupts>
+    <MemConfig>
+        <Base>1</Base>
+        <Manual>0</Manual>
+        <Ddf>1</Ddf>
+        <TypeViol>0</TypeViol>
+        <Stop>1</Stop>
+    </MemConfig>
+    <Simulator>
+        <Freq>16000000</Freq>
+        <FreqHi>0</FreqHi>
+        <MultiCoreRunAll>1</MultiCoreRunAll>
+    </Simulator>
+    <DataSample>
+        <LogEnabled>0</LogEnabled>
+        <GraphEnabled>0</GraphEnabled>
+        <ShowTimeLog>1</ShowTimeLog>
+    </DataSample>
+    <LogFile>
+        <LoggingEnabled>_ 0</LoggingEnabled>
+        <LogFile>_ ""</LogFile>
+        <Category>_ 0</Category>
+    </LogFile>
+    <TermIOLog>
+        <LoggingEnabled>_ 0</LoggingEnabled>
+        <LogFile>_ ""</LogFile>
+    </TermIOLog>
+    <Breakpoints>
+        <Bp0>_ "STD_CODE" "{$PROJ_DIR$\stm8l15x_it.c}.472.8" 1 0 0 0 "" 0 ""</Bp0>
+        <Count>1</Count>
+    </Breakpoints>
+    <Aliases>
+        <Count>0</Count>
+        <SuppressDialog>0</SuppressDialog>
+    </Aliases>
+    <DebuggerSettings>
+        <DisableInterruptsWhenStepping>0</DisableInterruptsWhenStepping>
+        <LeaveTargetRunning>0</LeaveTargetRunning>
+    </DebuggerSettings>
+</settings>
diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/settings/project.wsdt b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/settings/project.wsdt
new file mode 100755
index 0000000..c04d5f3
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/settings/project.wsdt
@@ -0,0 +1,358 @@
+<?xml version="1.0"?>
+<Workspace>
+    <ConfigDictionary>
+        <CurrentConfigs>
+            <Project>project/Debug</Project>
+        </CurrentConfigs>
+    </ConfigDictionary>
+    <WindowStorage>
+        <ChildIdMap>
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+            <WIN_BREAKPOINTS>34049</WIN_BREAKPOINTS>
+            <WIN_BUILD>34050</WIN_BUILD>
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+            <WIN_CUSTOM_SFR>34052</WIN_CUSTOM_SFR>
+            <WIN_C_STAT>34053</WIN_C_STAT>
+            <WIN_DEBUG_LOG>34054</WIN_DEBUG_LOG>
+            <WIN_FIND_ALL_DECLARATIONS>34055</WIN_FIND_ALL_DECLARATIONS>
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+            </MDIClientArea-0>
+        </MDIWindows>
+    </WindowStorage>
+</Workspace>
diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/stm8l15x_it.c b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/stm8l15x_it.c
new file mode 100755
index 0000000..af2d59f
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/stm8l15x_it.c
@@ -0,0 +1,553 @@
+/**
+  ******************************************************************************
+  * @file    stm8l15x_it.c
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    09/28/2010
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all peripherals interrupt service routine.
+  ******************************************************************************
+  * @copy
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm8l15x_it.h"
+#include "ebyte_kfifo.h"
+#include "ebyte_core.h"
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+static uint8_t Uart_isInRecvState = 0;
+static uint8_t Uart_isContinuousRecv = 0;
+static uint32_t Uart_TickCounter = 0;
+extern uint8_t Uart_isRecvReady;
+
+static uint16_t Button1_TickCounter = 0;
+static uint16_t Button2_TickCounter = 0;
+
+
+extern Ebyte_FIFO_t hfifo;
+extern uint8_t FIFO_isTimeCheckReady;
+static uint32_t FIFO_TickCounter = 0;
+/* Private function prototypes -----------------------------------------------*/
+void IT_Timer_ButtonCheck(void);
+void IT_Timer_UartCheck(void);
+/* Private functions ---------------------------------------------------------*/
+
+/** @addtogroup IT_Functions
+  * @{
+  */
+
+#ifdef _COSMIC_
+/**
+  * @brief Dummy interrupt routine
+  * @par Parameters:
+  * None
+  * @retval
+  * None
+*/
+INTERRUPT_HANDLER(NonHandledInterrupt, 0)
+{
+  /* In order to detect unexpected events during development,
+     it is recommended to set a breakpoint on the following instruction.
+  */
+}
+#endif
+
+/**
+  * @brief TRAP interrupt routine
+  * @par Parameters:
+  * None
+  * @retval
+  * None
+*/
+INTERRUPT_HANDLER_TRAP(TRAP_IRQHandler)
+{
+  /* In order to detect unexpected events during development,
+     it is recommended to set a breakpoint on the following instruction.
+  */
+}
+
+/**
+  * @brief FLASH Interrupt routine.
+  * @param  None
+  * @retval None
+  */
+INTERRUPT_HANDLER(FLASH_IRQHandler, 1)
+{
+  /* In order to detect unexpected events during development,
+     it is recommended to set a breakpoint on the following instruction.
+  */
+}
+
+/**
+  * @brief DMA1 channel0 and channel1 Interrupt routine.
+  * @param  None
+  * @retval None
+  */
+INTERRUPT_HANDLER(DMA1_CHANNEL0_1_IRQHandler, 2)
+{
+  /* In order to detect unexpected events during development,
+     it is recommended to set a breakpoint on the following instruction.
+  */
+}
+
+/**
+  * @brief DMA1 channel2 and channel3 Interrupt routine.
+  * @param  None
+  * @retval None
+  */
+INTERRUPT_HANDLER(DMA1_CHANNEL2_3_IRQHandler, 3)
+{
+  /* In order to detect unexpected events during development,
+     it is recommended to set a breakpoint on the following instruction.
+  */
+}
+
+/**
+  * @brief RTC / CSS_LSE Interrupt routine.
+  * @param  None
+  * @retval None
+  */
+INTERRUPT_HANDLER(RTC_CSSLSE_IRQHandler, 4)
+{
+  /* In order to detect unexpected events during development,
+     it is recommended to set a breakpoint on the following instruction.
+  */
+}
+
+/**
+  * @brief External IT PORTE/F and PVD Interrupt routine.
+  * @param  None
+  * @retval None
+  */
+INTERRUPT_HANDLER(EXTIE_F_PVD_IRQHandler, 5)
+{
+  /* In order to detect unexpected events during development,
+     it is recommended to set a breakpoint on the following instruction.
+  */
+}
+
+/**
+  * @brief External IT PORTB / PORTG Interrupt routine.
+  * @param  None
+  * @retval None
+  */
+INTERRUPT_HANDLER(EXTIB_G_IRQHandler, 6)
+{
+  /* In order to detect unexpected events during development,
+     it is recommended to set a breakpoint on the following instruction.
+  */
+}
+
+/**
+  * @brief External IT PORTD /PORTH Interrupt routine.
+  * @param  None
+  * @retval None
+  */
+INTERRUPT_HANDLER(EXTID_H_IRQHandler, 7)
+{
+  /* In order to detect unexpected events during development,
+     it is recommended to set a breakpoint on the following instruction.
+  */
+}
+
+/**
+  * @brief External IT PIN0 Interrupt routine.
+  * @param  None
+  * @retval None
+  */
+INTERRUPT_HANDLER(EXTI0_IRQHandler, 8)
+{
+  /* In order to detect unexpected events during development,
+     it is recommended to set a breakpoint on the following instruction.
+  */
+
+}
+
+/**
+  * @brief External IT PIN1 Interrupt routine.
+  * @param  None
+  * @retval None
+  */
+INTERRUPT_HANDLER(EXTI1_IRQHandler, 9)
+{
+  /* In order to detect unexpected events during development,
+     it is recommended to set a breakpoint on the following instruction.
+  */
+}
+
+/**
+  * @brief External IT PIN2 Interrupt routine.
+  * @param  None
+  * @retval None
+  */
+INTERRUPT_HANDLER(EXTI2_IRQHandler, 10)
+{
+  /* In order to detect unexpected events during development,
+     it is recommended to set a breakpoint on the following instruction.
+  */
+//    Ebyte_BSP_LedControl( BSP_LED_1, ON );
+//    Ebyte_E49x_InterruptTrigger();
+    EXTI_ClearITPendingBit(EXTI_IT_Pin2);
+}
+
+/**
+  * @brief External IT PIN3 Interrupt routine.
+  * @param  None
+  * @retval None
+  */
+
+INTERRUPT_HANDLER(EXTI3_IRQHandler, 11)
+{
+  /* In order to detect unexpected events during development,
+     it is recommended to set a breakpoint on the following instruction.
+  */
+    EXTI_ClearITPendingBit(EXTI_IT_Pin3);  
+}
+
+/**
+  * @brief External IT PIN4 Interrupt routine.
+  * @param  None
+  * @retval None
+  */
+INTERRUPT_HANDLER(EXTI4_IRQHandler, 12)
+{
+  /* In order to detect unexpected events during development,
+     it is recommended to set a breakpoint on the following instruction.
+  */
+  EXTI_ClearITPendingBit(EXTI_IT_Pin4);  
+}
+
+/**
+  * @brief External IT PIN5 Interrupt routine.
+  * @param  None
+  * @retval None
+  */
+INTERRUPT_HANDLER(EXTI5_IRQHandler, 13)
+{
+  /* In order to detect unexpected events during development,
+     it is recommended to set a breakpoint on the following instruction.
+  */
+    EXTI_ClearITPendingBit(EXTI_IT_Pin5);
+}
+
+/**
+  * @brief External IT PIN6 Interrupt routine.
+  * @param  None
+  * @retval None
+  */
+INTERRUPT_HANDLER(EXTI6_IRQHandler, 14)
+{
+  /* In order to detect unexpected events during development,
+     it is recommended to set a breakpoint on the following instruction.
+  */
+}
+
+/**
+  * @brief External IT PIN7 Interrupt routine.
+  * @param  None
+  * @retval None
+  */
+INTERRUPT_HANDLER(EXTI7_IRQHandler, 15)
+{
+  /* In order to detect unexpected events during development,
+     it is recommended to set a breakpoint on the following instruction.
+  */
+}
+
+/**
+  * @brief LCD /AES Interrupt routine.
+  * @param  None
+  * @retval None
+  */
+INTERRUPT_HANDLER(LCD_AES_IRQHandler, 16)
+{
+  /* In order to detect unexpected events during development,
+     it is recommended to set a breakpoint on the following instruction.
+  */
+}
+
+/**
+  * @brief CLK switch/CSS/TIM1 break Interrupt routine.
+  * @param  None
+  * @retval None
+  */
+INTERRUPT_HANDLER(SWITCH_CSS_BREAK_DAC_IRQHandler, 17)
+{
+  /* In order to detect unexpected events during development,
+     it is recommended to set a breakpoint on the following instruction.
+  */
+}
+
+/**
+  * @brief ADC1/Comparator Interrupt routine.
+  * @param  None
+  * @retval None
+  */
+INTERRUPT_HANDLER(ADC1_COMP_IRQHandler, 18)
+{
+  /* In order to detect unexpected events during development,
+     it is recommended to set a breakpoint on the following instruction.
+  */
+  /* Clear the comparator1 event flag */
+  COMP_ClearFlag(COMP_Selection_COMP1);
+}
+
+/**
+  * @brief TIM2 Update/Overflow/Trigger/Break /USART2 TX Interrupt routine.
+  * @param  None
+  * @retval None
+  */
+INTERRUPT_HANDLER(TIM2_UPD_OVF_TRG_BRK_USART2_TX_IRQHandler, 19)
+{
+  /* In order to detect unexpected events during development,
+     it is recommended to set a breakpoint on the following instruction.
+  */
+}
+
+/**
+  * @brief Timer2 Capture/Compare / USART2 RX Interrupt routine.
+  * @param  None
+  * @retval None
+  */
+INTERRUPT_HANDLER(TIM2_CC_USART2_RX_IRQHandler, 20)
+{
+  /* In order to detect unexpected events during development,
+     it is recommended to set a breakpoint on the following instruction.
+  */
+}
+
+/**
+  * @brief Timer3 Update/Overflow/Trigger/Break Interrupt routine.
+  * @param  None
+  * @retval None
+  */
+INTERRUPT_HANDLER(TIM3_UPD_OVF_TRG_BRK_USART3_TX_IRQHandler, 21)
+{
+  /* °´¼ü¼ì²â */
+  IT_Timer_ButtonCheck();
+  
+  /* ´®¿Ú״̬¼ì²â */
+  IT_Timer_UartCheck();
+  
+  /* ¶¨Ê±Æ÷ÑÓʱ¸¨Öú¼ÆËã */
+  Ebyte_BSP_TimerDecrement();
+  
+  TIM3_ClearITPendingBit(TIM3_IT_Update);
+}
+
+/**
+  * @brief Timer3 Capture/Compare /USART3 RX Interrupt routine.
+  * @param  None
+  * @retval None
+  */
+INTERRUPT_HANDLER(TIM3_CC_USART3_RX_IRQHandler, 22)
+{
+  /* In order to detect unexpected events during development,
+     it is recommended to set a breakpoint on the following instruction.
+  */
+}
+
+/**
+  * @brief TIM1 Update/Overflow/Trigger/Commutation Interrupt routine.
+  * @param  None
+  * @retval None
+  */
+INTERRUPT_HANDLER(TIM1_UPD_OVF_TRG_COM_IRQHandler, 23)
+{
+  /* In order to detect unexpected events during development,
+     it is recommended to set a breakpoint on the following instruction.
+  */
+}
+
+/**
+  * @brief TIM1 Capture/Compare Interrupt routine.
+  * @param  None
+  * @retval None
+  */
+INTERRUPT_HANDLER(TIM1_CC_IRQHandler, 24)
+{
+  /* In order to detect unexpected events during development,
+     it is recommended to set a breakpoint on the following instruction.
+  */
+}
+
+/**
+  * @brief TIM4 Update/Overflow/Trigger Interrupt routine.
+  * @param  None
+  * @retval None
+  */
+INTERRUPT_HANDLER(TIM4_UPD_OVF_TRG_IRQHandler, 25)
+{
+
+}
+
+/**
+  * @brief SPI1 Interrupt routine.
+  * @param  None
+  * @retval None
+  */
+INTERRUPT_HANDLER(SPI1_IRQHandler, 26)
+{
+  /* In order to detect unexpected events during development,
+     it is recommended to set a breakpoint on the following instruction.
+  */
+}
+
+/**
+  * @brief USART1 TX / TIM5 Update/Overflow/Trigger/Break Interrupt  routine.
+  * @param  None
+  * @retval None
+  */
+INTERRUPT_HANDLER(USART1_TX_TIM5_UPD_OVF_TRG_BRK_IRQHandler, 27)
+{
+  /* In order to detect unexpected events during development,
+     it is recommended to set a breakpoint on the following instruction.
+  */
+}
+
+/**
+  * @brief USART1 RX / Timer5 Capture/Compare Interrupt routine.
+  * @param  None
+  * @retval None
+  */
+INTERRUPT_HANDLER(USART1_RX_TIM5_CC_IRQHandler, 28)
+{
+  
+  /* Ê×Ö¡ÅÐ¶Ï ×´Ì¬»ú ´¥·¢¶¨Ê±Æ÷¼Æʱ 10msºóδÊÕµ½ÏÂÒ»×Ö½ÚÔò¶ÏÖ¡  */
+  if( !Uart_isInRecvState )
+  {
+      Uart_isInRecvState =  1;
+  }
+  Uart_isContinuousRecv = 1;  
+
+  /* ½ÓÊÕ´®¿ÚÊý¾Ý 1 Byte */
+  uint8_t temp = USART_ReceiveData8(USART1) ;
+  
+  /* дÈ뻺´æ¶ÓÁÐ 1 Byte */
+  Ebyte_FIFO_Write( &hfifo, &temp, 1 );
+
+  /* Çå³ýÖжϱêʶ */
+  USART_ClearITPendingBit( USART1, USART_IT_RXNE );  
+}
+
+/**
+  * @brief I2C1 / SPI2 Interrupt routine.
+  * @param  None
+  * @retval None
+  */
+INTERRUPT_HANDLER(I2C1_SPI2_IRQHandler, 29)
+{
+  /* In order to detect unexpected events during development,
+     it is recommended to set a breakpoint on the following instruction.
+  */
+
+}
+
+/* !
+ * @brief ¶¨Ê±Æ÷ÖÐ¶Ï ×´Ì¬»ú ¸¨Öú°´¼ü¼ì²â
+ */
+void IT_Timer_ButtonCheck(void)
+{
+    /* Èç¹û°´¼ü1±»°´Ï */
+  if( !Ebyte_BSP_ReadButton( BSP_BUTTON_1 ) )
+  {
+    Button1_TickCounter++;
+  }
+  else
+  {
+    if( Button1_TickCounter > 1000 )  // 1Ãë ³¤°´
+    {
+       Ebyte_BTN_FIFO_Push( &BSP_BTN_FIFO, BTN_1_LONG);
+    }
+    else if( Button1_TickCounter > 50 ) //50ºÁÃë ¶Ì°´
+    {
+       Ebyte_BTN_FIFO_Push( &BSP_BTN_FIFO, BTN_1_SHORT);
+    }
+    else {} //50ºÁÃëÒÔÏ  ÈÏΪÊǶ¶¶¯ ²»²Ù×÷
+    
+    Button1_TickCounter=0;   
+  }
+  
+  /* Èç¹û°´¼ü2±»°´Ï */
+  if( !Ebyte_BSP_ReadButton( BSP_BUTTON_2 ) )
+  {
+    Button2_TickCounter++;
+  }
+  else
+  {
+    if( Button2_TickCounter > 1000 )  // 1Ãë ³¤°´
+    {
+       Ebyte_BTN_FIFO_Push( &BSP_BTN_FIFO, BTN_2_LONG);
+    }
+    else if( Button2_TickCounter > 50 ) //50ºÁÃë ¶Ì°´
+    {
+       Ebyte_BTN_FIFO_Push( &BSP_BTN_FIFO, BTN_2_SHORT);
+    }
+    else {} //50ºÁÃëÒÔÏ  ÈÏΪÊǶ¶¶¯ ²»²Ù×÷
+    
+    Button2_TickCounter=0;   
+  }    
+}
+
+/* !
+ * @brief ¶¨Ê±Æ÷ÖÐ¶Ï ×´Ì¬»ú ¸¨Öúʱ¼ä¶ÏÖ¡
+ */
+void IT_Timer_UartCheck(void)
+{
+  /* ´®¿Ú½ÓÊÕµ½µÚÒ»×Ö½ÚÆð¾Í¿ªÊ¼¼Æʱ */
+  if( Uart_isInRecvState )
+  {
+     Uart_TickCounter++;
+  
+     /* ³¬¹ý10msûÓнÓÊÕµ½µÚ¶þ×Ö½Ú ¾ÍÈÏΪ¶ÏÖ¡ */
+     if( Uart_TickCounter > 10 )
+     {
+        /* ֪ͨÖ÷º¯Êý½ÓÊÕµ½Ò»Ö¡ */
+        Uart_isRecvReady ++;
+        /* Í£Ö¹¼Æʱ */
+        Uart_isInRecvState = 0;
+        Uart_TickCounter = 0;
+     }
+     
+     /* ¸´Î»FIFO³¬Ê±¼ì²â */
+     FIFO_TickCounter = 0;
+  }
+  else
+  {
+      /* Èç¹ûÔÚ´®¿ÚûÓнÓÊÕÊý¾Ýʱ »¹´æÔÚûÓз¢ËÍÍêµÄÖ¡ 500msºó³¬Ê±¼ì²â³ÉÁ¢ ÇåËãFIFOÖеÄÊý¾Ý */
+      if(  (!Uart_isInRecvState)  &&  Uart_isRecvReady )
+      {
+          FIFO_TickCounter++;
+          if( FIFO_TickCounter > 500)
+          {
+              FIFO_isTimeCheckReady=1;
+              Uart_isRecvReady = 0;
+              FIFO_TickCounter = 0;
+          }
+      }
+  }
+  
+  /* ´®¿Úÿ½ÓÊÕµ½1¸ö×Ö½Ú¾ÍÖØмÆÊý */
+  if( Uart_isInRecvState && Uart_isContinuousRecv )
+  {
+    Uart_TickCounter = 0;
+    Uart_isContinuousRecv = 0;
+  }
+}
+
+/**
+  * @}
+  */
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
\ No newline at end of file
diff --git a/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/stm8l15x_it.h b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/stm8l15x_it.h
new file mode 100755
index 0000000..29891cc
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/0_Project/IAR_for_Stm8/Uart_PingPong/stm8l15x_it.h
@@ -0,0 +1,73 @@
+/**
+  ******************************************************************************
+  * @file    stm8l15x_it.h
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    09/28/2010
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @copy
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM8L15x_IT_H
+#define __STM8L15x_IT_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm8l15x.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+#ifdef _COSMIC_
+ void _stext(void); /* RESET startup routine */
+ INTERRUPT void NonHandledInterrupt(void);
+#endif /* _COSMIC_ */
+
+#ifndef _RAISONANCE_
+ INTERRUPT void TRAP_IRQHandler(void); /* TRAP */
+ INTERRUPT void FLASH_IRQHandler(void); /* FLASH EOP/PG_DIS */
+ INTERRUPT void DMA1_CHANNEL0_1_IRQHandler(void); /* DMA1 Channel0/1*/
+ INTERRUPT void DMA1_CHANNEL2_3_IRQHandler(void); /*DMA1 Channel2/3*/
+ INTERRUPT void RTC_CSSLSE_IRQHandler(void); /* RTC /CSS_LSE */
+ INTERRUPT void EXTIE_F_PVD_IRQHandler(void); /*EXTI PORTE/EXTI PORTF/PVD*/
+ INTERRUPT void EXTIB_G_IRQHandler(void); /* EXTI PORTB / EXTI PORTG */
+ INTERRUPT void EXTID_H_IRQHandler(void); /* EXTI PORTD / EXTI PORTH*/
+ INTERRUPT void EXTI0_IRQHandler(void); /* EXTI PIN0 */
+ INTERRUPT void EXTI1_IRQHandler(void); /* EXTI PIN1 */
+ INTERRUPT void EXTI2_IRQHandler(void); /* EXTI PIN2 */
+ INTERRUPT void EXTI3_IRQHandler(void); /* EXTI PIN3 */
+ INTERRUPT void EXTI4_IRQHandler(void); /* EXTI PIN4 */
+ INTERRUPT void EXTI5_IRQHandler(void); /* EXTI PIN5 */
+ INTERRUPT void EXTI6_IRQHandler(void); /* EXTI PIN6 */
+ INTERRUPT void EXTI7_IRQHandler(void); /* EXTI PIN7 */
+ INTERRUPT void LCD_AES_IRQHandler(void); /* LCD /AES */
+ INTERRUPT void SWITCH_CSS_BREAK_DAC_IRQHandler(void); /* Switch CLK/CSS/TIM1 Break/DAC */
+ INTERRUPT void ADC1_COMP_IRQHandler(void); /*ADC1/COMP*/
+ INTERRUPT void TIM2_UPD_OVF_TRG_BRK_USART2_TX_IRQHandler(void); /* TIM2 UPD/OVF/TRG/BRK / USART2 TX */
+ INTERRUPT void TIM2_CC_USART2_RX_IRQHandler(void); /* TIM2 CAP / USART2 RX */
+ INTERRUPT void TIM3_UPD_OVF_TRG_BRK_USART3_TX_IRQHandler(void); /* TIM3 UPD/OVF/TRG/BRK /USART3 TX*/
+ INTERRUPT void TIM3_CC_USART3_RX_IRQHandler(void); /* TIM3 CAP/ USART3 RX */
+ INTERRUPT void TIM1_UPD_OVF_TRG_COM_IRQHandler(void);/* TIM1 UPD/OVF/TRG/COM */
+ INTERRUPT void TIM1_CC_IRQHandler(void);/* TIM1 CAP*/
+ INTERRUPT void TIM4_UPD_OVF_TRG_IRQHandler(void); /* TIM4 UPD/OVF/TRI */
+ INTERRUPT void SPI1_IRQHandler(void); /* SPI1 */
+ INTERRUPT void USART1_TX_TIM5_UPD_OVF_TRG_BRK_IRQHandler(void); /* USART1 TX / TIM5 UPD/OVF/TRG/BRK */
+ INTERRUPT void USART1_RX_TIM5_CC_IRQHandler(void); /* USART1 RX / TIM5 CAP */
+ INTERRUPT void I2C1_SPI2_IRQHandler(void); /* I2C1 / SPI2 */
+#endif /* _RAISONANCE_ */
+
+#endif /* __STM8L15x_IT_H */
+
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
\ No newline at end of file
diff --git a/NSPE/WIFI_IOT/bsp/drivers/1_Middleware/Kfifo/ebyte_kfifo.c b/NSPE/WIFI_IOT/bsp/drivers/1_Middleware/Kfifo/ebyte_kfifo.c
new file mode 100755
index 0000000..700e12b
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/1_Middleware/Kfifo/ebyte_kfifo.c
@@ -0,0 +1,107 @@
+
+/* Includes ------------------------------------------------------------------*/
+#include "ebyte_kfifo.h"
+
+uint8_t Ebyte_FIFO_Init( Ebyte_FIFO_t *fifo, uint16_t size )
+{
+    uint8_t result = 0;
+
+    if( ( size & ( size - 1 ) ) != 0 ) //Warning ! Size must be 2^n ! Please view linux kfifo
+    {
+        result = 1;
+    }
+
+    fifo->size = size;
+    fifo->in = 0;
+    fifo->out = 0;
+    return result;
+}
+
+uint8_t Ebyte_FIFO_Write( Ebyte_FIFO_t *fifo, uint8_t *pData, uint16_t length )
+{
+    uint8_t result = 0;
+
+    uint32_t i, j;
+    uint16_t endLength, orgLength;
+    uint8_t *pFifoBuffer;
+
+    orgLength = length;
+    /* calculate the length of data that can be written */
+    length = MIN( length, fifo->size - fifo->in + fifo->out );
+    /* first put the data starting from fifo->in to buffer end */
+    endLength  = MIN( length, fifo->size - ( fifo->in & ( fifo->size - 1 ) ) );
+    pFifoBuffer = fifo->buffer + ( fifo->in & ( fifo->size - 1 ) );
+    for( i = 0; i < endLength; i++ )
+    {
+        *( pFifoBuffer++ ) = *( pData++ );
+    }
+    /* then put the rest (if any) at the beginning of the buffer */
+    j = length - endLength;
+    if ( j > 0 )
+    {
+        pFifoBuffer = fifo->buffer;
+
+        for( i = 0; i < j; i++ )
+        {
+            *( pFifoBuffer++ ) = *( pData++ );
+        }
+    }
+
+    fifo->in += length;
+    if( length < orgLength )
+    {
+        result = 1; // Means fifo is full , some data can not be written in
+    }
+    return result;
+}
+
+uint8_t Ebyte_FIFO_Read( Ebyte_FIFO_t *fifo, uint8_t *pData,  uint16_t length )
+{
+    uint8_t result = 0;
+    uint16_t i, j;
+    uint16_t endLength, orgLength;
+    uint8_t *pFifoBuffer;
+
+    orgLength = length;
+    length  = MIN( length, fifo->in - fifo->out );
+    /* first get the data from fifo->out until the end of the buffer */
+    endLength = MIN( length, fifo->size - ( fifo->out & ( fifo->size - 1 ) ) );
+    pFifoBuffer = fifo->buffer + ( fifo->out & ( fifo->size - 1 ) );
+    for( i = 0; i < endLength; i++ )
+    {
+        *( pData++ ) = *( pFifoBuffer++ );
+    }
+    /* then get the rest (if any) from the beginning of the buffer */
+    j = length - endLength;
+    if ( j > 0 )
+    {
+        pFifoBuffer = fifo->buffer;
+
+        for( i = 0; i < j; i++ )
+        {
+            *( pData++ ) = *( pFifoBuffer++ ) ;
+        }
+    }
+    fifo->out += length;
+    if( length < orgLength )
+    {
+        result = 1; //  not enough data
+    }
+    return result;
+}
+
+uint8_t Ebyte_FIFO_GetDataLength( Ebyte_FIFO_t *fifo, uint16_t *pLength )
+{
+    uint8_t result = 0;
+    *pLength = ( fifo->in - fifo->out );
+    return result;
+}
+
+uint8_t Ebyte_FIFO_Clear( Ebyte_FIFO_t *fifo )
+{
+    uint8_t result = 0;
+    fifo->in = 0;
+    fifo->out = 0;
+    return result;
+}
+
diff --git a/NSPE/WIFI_IOT/bsp/drivers/1_Middleware/Kfifo/ebyte_kfifo.h b/NSPE/WIFI_IOT/bsp/drivers/1_Middleware/Kfifo/ebyte_kfifo.h
new file mode 100755
index 0000000..015406a
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/1_Middleware/Kfifo/ebyte_kfifo.h
@@ -0,0 +1,19 @@
+#include "board.h"
+
+#define MIN(a, b) (((a) < (b)) ? (a) : (b))
+#define EBYTE_FIFO_SIZE 64  //  Warning ! Size must be 2^n ! Please view linux kfifo
+
+typedef struct
+{
+    uint32_t in;
+    uint32_t out;
+    uint32_t size;
+    uint8_t buffer[EBYTE_FIFO_SIZE];
+
+} Ebyte_FIFO_t;
+
+uint8_t Ebyte_FIFO_Init( Ebyte_FIFO_t *fifo, uint16_t size );
+uint8_t Ebyte_FIFO_Write( Ebyte_FIFO_t *fifo, uint8_t *pData, uint16_t length );
+uint8_t Ebyte_FIFO_GetDataLength( Ebyte_FIFO_t *fifo, uint16_t *pLength );
+uint8_t Ebyte_FIFO_Read( Ebyte_FIFO_t *fifo, uint8_t *pData,  uint16_t length );
+uint8_t Ebyte_FIFO_Clear( Ebyte_FIFO_t *fifo );
diff --git a/NSPE/WIFI_IOT/bsp/drivers/1_Middleware/Produce/ebyte_debug.c b/NSPE/WIFI_IOT/bsp/drivers/1_Middleware/Produce/ebyte_debug.c
new file mode 100755
index 0000000..9166a72
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/1_Middleware/Produce/ebyte_debug.c
@@ -0,0 +1,122 @@
+/**
+  **********************************************************************************
+  * @file      board.c
+  * @brief     E15-EVB02 ¼ì²âģʽ     
+  * @details   ÏêÇéÇë²Î¼û https://www.ebyte.com/       
+  * @author    JiangHeng     
+  * @date      2021-05-20     
+  * @version   1.0.0     
+  **********************************************************************************
+  * @copyright BSD License 
+  *            ³É¶¼ÒÚ°ÛÌصç×ӿƼ¼ÓÐÏÞ¹«Ë¾  
+  *   ______   ____   __     __  _______   ______ 
+  *  |  ____| |  _ \  \ \   / / |__   __| |  ____|
+  *  | |__    | |_) |  \ \_/ /     | |    | |__   
+  *  |  __|   |  _ <    \   /      | |    |  __|  
+  *  | |____  | |_) |    | |       | |    | |____ 
+  *  |______| |____/     |_|       |_|    |______| 
+  *
+  **********************************************************************************
+  */
+
+#include "ebyte_core.h"
+#include "ebyte_debug.h"
+
+extern unsigned char PC_isConnected;
+
+const unsigned char SimulatedCommandsButton1[5] = { EBYTE_CMD_PACKAGE_START,
+                                                    EBYTE_CMD_PACKAGE_START,
+                                                    EBYTE_CMD_PACKAGE_START, 
+                                                    EBYTE_CMD_TEST_BUTTON,
+                                                    0x01
+                                                    };
+
+const unsigned char SimulatedCommandsButton2[5] = { EBYTE_CMD_PACKAGE_START,
+                                                    EBYTE_CMD_PACKAGE_START,
+                                                    EBYTE_CMD_PACKAGE_START, 
+                                                    EBYTE_CMD_TEST_BUTTON,
+                                                    0x02
+                                                    };
+const unsigned char SimulatedCommandsWireless1[5] = { EBYTE_CMD_PACKAGE_START,
+                                                      EBYTE_CMD_PACKAGE_START,
+                                                      EBYTE_CMD_PACKAGE_START, 
+                                                      EBYTE_CMD_TEST_WIRELESS,
+                                                      0x01
+                                                      };      
+const unsigned char SimulatedCommandsWireless2[5] = { EBYTE_CMD_PACKAGE_START,
+                                                      EBYTE_CMD_PACKAGE_START,
+                                                      EBYTE_CMD_PACKAGE_START, 
+                                                      EBYTE_CMD_TEST_WIRELESS,
+                                                      0x02
+                                                      };   
+
+
+/* !
+ * @brief ²âÊÔÃüÁî¼ì²é
+ * 
+ * @param rxBuffer ¿ÉÄܺ¬ÓÐÃüÁîµÄÊý¾Ý°ü 
+ * @param length rxBufferÊý¾Ý³¤¶È
+ * @param txBuffer ÏìÓ¦Êý¾Ý°ü   ³¤¶È>10
+ * @param tLength ÏìÓ¦Êý¾Ý°ü³¤¶È
+ * @return 0:δ¼ì²âµ½ÃüÁî 1:¼ì²âµ½ÁËÃüÁî
+ */
+unsigned char  Ebyte_DEBUG_CommandEcho( unsigned char *rxBuffer , unsigned char length, unsigned char *txBuffer, unsigned char *tLength)
+{
+    unsigned char result = 0;
+    unsigned char *p;
+    unsigned char tmp,version;
+    unsigned long name;
+    
+    /* Ö»¹ØÐĹ̶¨³¤¶ÈΪ10µÄÊý¾ÝÖ¡ ¼ä¸ôʱ¼ä³¤ Õ³°ü¼¸ÂʺÜС*/
+    if( length == EBYTE_CMD_PACKAGE_LENGTH )
+    {
+        p = rxBuffer;
+        
+        if( *p++== EBYTE_CMD_PACKAGE_START &&  *p++== EBYTE_CMD_PACKAGE_START &&  *p++== EBYTE_CMD_PACKAGE_START)
+        {
+            /* Êý¾ÝÌåµÚÒ»×Ö½Ú Ö¸ÁîÂë  */
+            tmp = *p;
+            switch( tmp )
+            {
+              case EBYTE_CMD_TEST_MODE:
+                
+                  name = Ebyte_RF.GetName();
+                  version = Ebyte_RF.GetDriverVersion();
+                    
+                  *txBuffer++ = EBYTE_CMD_PACKAGE_START;
+                  *txBuffer++ = EBYTE_CMD_PACKAGE_START;
+                  *txBuffer++ = EBYTE_CMD_PACKAGE_START;
+                  *txBuffer++ = EBYTE_CMD_TEST_MODE;
+                  *txBuffer++ = (unsigned char)(name>>24);
+                  *txBuffer++ = (unsigned char)(name>>16);
+                  *txBuffer++ = (unsigned char)(name>>8);
+                  *txBuffer++ = (unsigned char)(name);
+                  *txBuffer++ = version;
+                  
+                  *tLength    = EBYTE_CMD_PACKAGE_LENGTH;
+                  PC_isConnected = 1; //ģʽ±ä¸ü
+              break;
+            case EBYTE_CMD_TEST_BUTTON:
+                  *txBuffer++ = EBYTE_CMD_PACKAGE_START;
+                  *txBuffer++ = EBYTE_CMD_PACKAGE_START;
+                  *txBuffer++ = EBYTE_CMD_PACKAGE_START;
+                  *txBuffer++ = EBYTE_CMD_TEST_BUTTON;
+                  *txBuffer   = *++p;
+                  *tLength    = EBYTE_CMD_PACKAGE_LENGTH;
+              break;
+            case EBYTE_CMD_TEST_WIRELESS:
+                  *txBuffer++ = EBYTE_CMD_PACKAGE_START;
+                  *txBuffer++ = EBYTE_CMD_PACKAGE_START;
+                  *txBuffer++ = EBYTE_CMD_PACKAGE_START;
+                  *txBuffer++ = EBYTE_CMD_TEST_WIRELESS;
+                  *txBuffer   = *++p;
+                  *tLength    = EBYTE_CMD_PACKAGE_LENGTH;
+              break;
+            }
+            
+            result = 1;
+        }
+    }
+    
+    return result;
+}
\ No newline at end of file
diff --git a/NSPE/WIFI_IOT/bsp/drivers/1_Middleware/Produce/ebyte_debug.h b/NSPE/WIFI_IOT/bsp/drivers/1_Middleware/Produce/ebyte_debug.h
new file mode 100755
index 0000000..a9cbc1c
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/1_Middleware/Produce/ebyte_debug.h
@@ -0,0 +1,14 @@
+
+
+#define EBYTE_CMD_PACKAGE_START 0xC5
+#define EBYTE_CMD_PACKAGE_LENGTH 0x0A
+#define EBYTE_CMD_TEST_MODE 0x01
+#define EBYTE_CMD_TEST_BUTTON 0x02
+#define EBYTE_CMD_TEST_WIRELESS 0x03
+
+extern const unsigned char SimulatedCommandsButton1[5];
+extern const unsigned char SimulatedCommandsButton2[5];
+extern const unsigned char SimulatedCommandsWireless1[5];
+extern const unsigned char SimulatedCommandsWireless2[5];
+
+unsigned char  Ebyte_DEBUG_CommandEcho( unsigned char *rxBuffer , unsigned char length, unsigned char *txBuffer, unsigned char *tLength);
\ No newline at end of file
diff --git a/NSPE/WIFI_IOT/bsp/drivers/2_Ebyte_Board_Support/E15-EVB02/board.c b/NSPE/WIFI_IOT/bsp/drivers/2_Ebyte_Board_Support/E15-EVB02/board.c
new file mode 100755
index 0000000..aaa8fb8
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/2_Ebyte_Board_Support/E15-EVB02/board.c
@@ -0,0 +1,311 @@
+/**
+  **********************************************************************************
+  * @file      board.c
+  * @brief     E15-EVB02 °å¼¶Èí¼þÇý¶¯²ã     
+  * @details   ÏêÇéÇë²Î¼û https://www.ebyte.com/       
+  * @author    JiangHeng     
+  * @date      2021-05-06     
+  * @version   1.0.0     
+  **********************************************************************************
+  * @copyright BSD License 
+  *            ³É¶¼ÒÚ°ÛÌصç×ӿƼ¼ÓÐÏÞ¹«Ë¾  
+  *   ______   ____   __     __  _______   ______ 
+  *  |  ____| |  _ \  \ \   / / |__   __| |  ____|
+  *  | |__    | |_) |  \ \_/ /     | |    | |__   
+  *  |  __|   |  _ <    \   /      | |    |  __|  
+  *  | |____  | |_) |    | |       | |    | |____ 
+  *  |______| |____/     |_|       |_|    |______| 
+  *
+  **********************************************************************************
+  */
+
+#include "board.h"
+#include "ebyte_conf.h"
+
+BSP_BTN_FIFO_t BSP_BTN_FIFO;    
+      
+
+/*!< @brief ¸¨ÖúÑÓʱ¼ÆËã ÓÃÓÚ¶¨Ê±Æ÷ÖÐ¶Ï µÝ¼õ */
+volatile uint32_t Ebyte_TimerDelayCounter = 0;
+
+/* !
+ * @brief ÄÚ²¿Ê±ÖÓ³õʼ»¯
+ */
+void Ebyte_BSP_HSI_Init(void)
+{
+  /* ÄÚ²¿ 16M HSI ʱÖÓ */ 
+  CLK_SYSCLKSourceConfig( CLK_SYSCLKSource_HSI );
+  
+  /* 1·ÖƵ  16M/1 */
+  CLK_SYSCLKDivConfig( CLK_SYSCLKDiv_1 );
+}
+
+
+
+
+
+
+
+
+void Ebyte_BSP_E48xGPIO_Init(void)
+{
+//    GPIO_Init( BSP_GPIO_PORT_E48_GP0, BSP_GPIO_PIN_E48_GP0, GPIO_Mode_In_PU_No_IT ); 
+    GPIO_Init( BSP_GPIO_PORT_E48_NIRQ, BSP_GPIO_PIN_E48_NIRQ, GPIO_Mode_In_PU_No_IT );
+    GPIO_Init( BSP_GPIO_PORT_E48_GP3, BSP_GPIO_PIN_E48_GP3, GPIO_Mode_In_PU_No_IT );
+    GPIO_Init( BSP_GPIO_PORT_E48_GP4, BSP_GPIO_PIN_E48_GP4, GPIO_Mode_In_FL_No_IT ); 
+    GPIO_Init( BSP_GPIO_PORT_E48_GP5, BSP_GPIO_PIN_E48_GP5, GPIO_Mode_In_PU_No_IT );
+}
+/* !
+ * @brief ³õʼ»¯ËùÓÐIO
+ * 
+ * @note  Ä¿±êÓ²¼þ: EBYTE E15-EVB02 
+ */
+void Ebyte_BSP_GPIO_Init(void)
+{
+    /* ÎÞÏßÄ£¿é״̬¿ØÖÆ */   
+    Ebyte_BSP_E48xGPIO_Init();      
+    /* LED */
+    GPIO_Init( BSP_GPIO_PORT_LED_1, BSP_GPIO_PIN_LED_1, GPIO_Mode_Out_PP_Low_Slow );
+    GPIO_Init( BSP_GPIO_PORT_LED_2, BSP_GPIO_PIN_LED_2, GPIO_Mode_Out_PP_Low_Slow );   
+       
+    /* °´¼ü */
+    GPIO_Init( BSP_GPIO_PORT_BUTTON_1, BSP_GPIO_PIN_BUTTON_1, GPIO_Mode_In_PU_No_IT ); 
+
+    GPIO_Init( BSP_GPIO_PORT_BUTTON_2, BSP_GPIO_PIN_BUTTON_2, GPIO_Mode_In_PU_No_IT );     
+}
+
+/* !
+ * @brief ͨÐÅ´®¿Ú³õʼ»¯
+ * 
+ * @note  Çë×¢Ò⣬²»Í¬µÄMCU¿ÉÄÜÎÞÐè¶Ë¿ÚÓ³Éä
+ */
+void Ebyte_BSP_UART_Init( void )
+{
+    /* ʱÖÓ */
+    CLK_PeripheralClockConfig( BSP_USER_UART_CLOCK, ENABLE);
+    
+    /* GPIO */
+    GPIO_ExternalPullUpConfig( BSP_GPIO_PORT_UART_TX, BSP_GPIO_PIN_UART_TX, ENABLE );
+    GPIO_ExternalPullUpConfig( BSP_GPIO_PORT_UART_RX, BSP_GPIO_PIN_UART_RX, ENABLE );
+
+    /* ¶Ë¿ÚÖØÓ³Éä  */
+    SYSCFG_REMAPPinConfig( REMAP_Pin_USART1TxRxPortA, ENABLE ); 
+    
+    /* »ù´¡²ÎÊýÅäÖà E15-EVB02ĬÈϲ¨ÌØÂÊ9600 8N1 */
+    USART_Init( BSP_USER_UART, BSP_USER_UART_BAUDRATE, USART_WordLength_8b, USART_StopBits_1, BSP_USER_UART_PARITY,  (USART_Mode_TypeDef)(USART_Mode_Rx | USART_Mode_Tx ));//ÔÊÐí½ÓÊպͷ¢ËÍ
+    
+    /* ´ò¿ª½ÓÊÕÖÐ¶Ï */;
+    USART_ITConfig( BSP_USER_UART, USART_IT_RXNE, ENABLE );
+     
+    /* ´®¿Ú ʹÄÜ */
+    USART_Cmd( BSP_USER_UART, ENABLE);
+}
+
+void Ebyte_BSP_ThreeLinesSPI_Init()
+{
+    /* ºÏ²¢µ½ÁËE49 GPIO³õʼ»¯ÖÐ */
+}
+
+/* !
+ * @brief ÎÞÏßÄ£¿éͨÐÅSPI½Ó¿Ú³õʼ»¯º¯Êý
+ */
+void Ebyte_BSP_SPI_Init( void )
+{
+    /* ʱÖÓ */
+    CLK_PeripheralClockConfig( CLK_Peripheral_SPI1, ENABLE);
+    
+    /* GPIO */
+    GPIO_Init( BSP_GPIO_PORT_SPI_NSS,  BSP_GPIO_PIN_SPI_NSS,  GPIO_Mode_Out_PP_High_Slow); //Ƭѡ CS
+    GPIO_ExternalPullUpConfig( BSP_GPIO_PORT_SPI_SCK, BSP_GPIO_PIN_SPI_MOSI | BSP_GPIO_PIN_SPI_MISO | BSP_GPIO_PIN_SPI_SCK, ENABLE); // MOSI MISO SCK   
+    
+    /* ²ÎÊýÅäÖà */
+    SPI_Init(  BSP_RF_SPI, 
+               SPI_FirstBit_MSB,                 //´Ó¸ßλ¿ªÊ¼´«Êä
+               SPI_BaudRatePrescaler_8,          //16M/2 SCKËÙÂÊ
+               SPI_Mode_Master,                  //Ö÷»úģʽ
+               SPI_CPOL_Low,                     //¸ù¾Ý CPOL=0  
+               SPI_CPHA_1Edge,                   //¸ù¾Ý CPHA=0  µÚÒ»¸öʱÖÓ±ßÑزÉÑùÊý¾Ý
+               SPI_Direction_2Lines_FullDuplex,  //È«Ë«¹¤
+               SPI_NSS_Soft,                     //Èí¼þ¿ØÖÆ´Ó»úCSƬѡ
+               0x07);                            //CRC²ÎÊý
+    
+    /* ʹÄÜ */
+    SPI_Cmd( BSP_RF_SPI, ENABLE );
+}
+
+/* !
+ * @brief RFÄ£¿éSPIͨÐÅÊÕ/·¢º¯Êý
+ * 
+ * @param data ·¢ËÍÊý¾Ý  
+ * @return ½ÓÊÕÊý¾Ý 
+ * @note stm8l SPI¿âº¯ÊýÖеÄSPI_SendData()/SPI_ReceiveData() ²»ÄÜÖ±½ÓʹÓÃ
+ */
+uint8_t Ebyte_BSP_SpiTransAndRecv( uint8_t data )
+{
+    BSP_RF_SPI->DR = data;
+    while ((BSP_RF_SPI->SR & SPI_FLAG_TXE) == RESET);
+    
+    while ((BSP_RF_SPI->SR & SPI_FLAG_RXNE) == RESET);
+    return BSP_RF_SPI->DR;
+}
+
+/* !
+ * @brief ¶¨Ê±Æ÷³õʼ»¯
+ *
+ * @note  ʹÓÃÁËTIM3²úÉú1msÖÜÆÚÐÔÖжÏ
+ *        TIM3µÄÖ÷ʱÖÓΪHSI 16MHz, 128·ÖƵ¼´Îª 16 MHz / 128 = 125 000 Hz
+ *        Ä¿±ê¶¨Ê±1ms ¼ÆÊýÖÜÆÚ¼´Îª ( 0.001 x 125000 - 1) = 124 
+ */
+void Ebyte_BSP_TIMER_Init( void )
+{
+    /* ʱÖÓ */
+    CLK_PeripheralClockConfig( CLK_Peripheral_TIM3, ENABLE); 
+    
+    /* ²ÎÊý */
+    TIM3_TimeBaseInit( TIM3_Prescaler_128 , TIM3_CounterMode_Up, 124);
+    
+    /* ÔÊÐíÖÐ¶Ï */
+    TIM3_ClearFlag(TIM3_FLAG_Update);
+    TIM3_ITConfig(TIM3_IT_Update, ENABLE);
+    
+    /* ʹÄÜ */
+    TIM3_Cmd(ENABLE);
+}       
+
+/* !
+ * @brief E15-EVB02 °åÔØ×ÊÔ´³õʼ»¯
+ * 
+ * @note  ÄÚ²¿Ê±ÖÓHSI  x 16MHz
+ *        Óû§Í¨ÐÅ´®¿Ú x USART1
+ *        ÎÞÏßÄ£¿éͨÐÅ½Ó¿Ú x SPI1
+ *        ¶¨Ê±Æ÷  x TIM3
+ *        °´¼ü    x 2
+ *        ָʾµÆ  x 2
+ */
+void Ebyte_BSP_Init( void )
+{
+    /* ʱÖÓ     ³õʼ»¯ */
+    Ebyte_BSP_HSI_Init();
+    
+    /* IO       ³õʼ»¯ */
+    Ebyte_BSP_GPIO_Init();
+    
+    /* ´®¿Ú     ³õʼ»¯ */
+    Ebyte_BSP_UART_Init();
+  
+    /* SPI½Ó¿Ú  ³õʼ»¯   */
+    Ebyte_BSP_SPI_Init();
+
+    
+    /* ¶¨Ê±Æ÷   ³õʼ»¯ */
+    Ebyte_BSP_TIMER_Init();
+    
+    /* °´¼üʼþ¶ÓÁÐ ³õʼ»¯ */
+    Ebyte_BTN_FIFO_Init( &BSP_BTN_FIFO );
+    
+    
+    
+
+}
+
+/* !
+ * @brief ¿ØÖÆLED ¿ª/¹Ø/·­×ª
+ * 
+ * @param LEDx  °åÔØÁ½¿Å·¢¹â¶þ¼«¹Ü
+ *              @arg BSP_LED_1 : LED1
+ *              @arg BSP_LED_2 : LED2 
+ * 
+ * @param ctl   ¿ª / ¹Ø
+ *              @arg OFF     : ¹Ø
+ *              @arg ON      : ¿ª  
+ *              @arg TOGGLE  : ·­×ª 
+ */
+void Ebyte_BSP_LedControl( BSP_LED_t LEDx , BSP_LED_Ctl_t ctl)
+{
+    if( TOGGLE == ctl )
+    {
+      switch( LEDx )
+      {
+        case BSP_LED_1 : GPIO_ToggleBits( BSP_GPIO_PORT_LED_1, BSP_GPIO_PIN_LED_1); break;
+        case BSP_LED_2 : GPIO_ToggleBits( BSP_GPIO_PORT_LED_2, BSP_GPIO_PIN_LED_2); break;
+        default: break;
+      }    
+    }
+    else
+    {
+      switch( LEDx )
+      {
+        case BSP_LED_1 : GPIO_WriteBit( BSP_GPIO_PORT_LED_1, BSP_GPIO_PIN_LED_1, (BitAction)ctl); break;
+        case BSP_LED_2 : GPIO_WriteBit( BSP_GPIO_PORT_LED_2, BSP_GPIO_PIN_LED_2, (BitAction)ctl); break;
+        default: break;
+      }    
+    }
+
+}
+
+
+/* !
+ * @brief »ùÓÚ¶¨Ê±Æ÷µÄºÁÃëÑÓʱº¯Êý
+ * 
+ * @param nTime µ¥Î»:ºÁÃë
+ */
+void Ebyte_BSP_DelayMs( volatile uint32_t nTime )
+{
+    Ebyte_TimerDelayCounter = nTime;
+    
+    while( Ebyte_TimerDelayCounter !=0 );
+}
+
+/* !
+ * @brief ¸¨ÖúºÁÃëÑÓʱ¼ÆËã ¶¨Ê±Æ÷Öжϵ÷ÓÃ
+ */
+void Ebyte_BSP_TimerDecrement(void)
+{
+
+  
+    if( Ebyte_TimerDelayCounter != 0 ) 
+    {
+        Ebyte_TimerDelayCounter--;
+    }
+}
+
+
+/* !
+ * @brief ¶ÁÈ¡°´¼ü״̬
+ * 
+ * @param btn ¶ÔÓ¦µÄ°´¼ü±àºÅ
+ *            @arg BSP_BUTTON_1 :°´¼ü1 
+ *            @arg BSP_BUTTON_2 :°´¼ü2
+ * @return 0:°´¼ü±»°´Ï  ·Ç0:°´¼üδ°´Ï 
+ * @note  °åÔØ°´¼üδ°´ÏÂʱ IO´¦ÓÚÉÏÀ­×´Ì¬ ¼´Îª1£»°´ÏºóIO½ÓµØ ¼´Îª0
+ */
+uint8_t Ebyte_BSP_ReadButton( BSP_BUTTON_t btn )
+{
+    BitStatus result = RESET;
+    
+    switch ( btn )
+    {
+      case BSP_BUTTON_1: result = GPIO_ReadInputDataBit( BSP_GPIO_PORT_BUTTON_1 , BSP_GPIO_PIN_BUTTON_1); break;
+      case BSP_BUTTON_2: result = GPIO_ReadInputDataBit( BSP_GPIO_PORT_BUTTON_2 , BSP_GPIO_PIN_BUTTON_2); break;
+      default : break;
+    }
+    
+    return result;
+}
+
+
+/* !
+ * @brief ´®¿Ú·¢Ëͺ¯Êý
+ */
+void Ebyte_BSP_UartTransmit( uint8_t *buffer , uint16_t length )
+{
+  
+    uint8_t i;
+    
+    for( i = 0; i < length; i++ )
+    {
+        while ( USART_GetFlagStatus( USART1, USART_FLAG_TXE ) == RESET );
+        USART_SendData8( USART1, *buffer++ );
+    }  
+}
+
diff --git a/NSPE/WIFI_IOT/bsp/drivers/2_Ebyte_Board_Support/E15-EVB02/board.h b/NSPE/WIFI_IOT/bsp/drivers/2_Ebyte_Board_Support/E15-EVB02/board.h
new file mode 100755
index 0000000..44439c4
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/2_Ebyte_Board_Support/E15-EVB02/board.h
@@ -0,0 +1,172 @@
+/**
+  **********************************************************************************
+  * @file      board.h
+  * @brief     E15-EVB02 °å¼¶Èí¼þÇý¶¯²ã     
+  * @details   ÏêÇéÇë²Î¼û https://www.ebyte.com/       
+  * @author    JiangHeng     
+  * @date      2021-05-06     
+  * @version   1.0.0     
+  **********************************************************************************
+  * @copyright BSD License 
+  *            ³É¶¼ÒÚ°ÛÌصç×ӿƼ¼ÓÐÏÞ¹«Ë¾  
+  *   ______   ____   __     __  _______   ______ 
+  *  |  ____| |  _ \  \ \   / / |__   __| |  ____|
+  *  | |__    | |_) |  \ \_/ /     | |    | |__   
+  *  |  __|   |  _ <    \   /      | |    |  __|  
+  *  | |____  | |_) |    | |       | |    | |____ 
+  *  |______| |____/     |_|       |_|    |______| 
+  *
+  **********************************************************************************
+  */
+
+#include "stm8l15x_conf.h"
+#include "board_mini_printf.h"
+
+/* Òý½ÅÅäÖà LED   */
+#define BSP_GPIO_PORT_LED_1       GPIOC
+#define BSP_GPIO_PIN_LED_1        GPIO_Pin_6
+
+#define BSP_GPIO_PORT_LED_2       GPIOC
+#define BSP_GPIO_PIN_LED_2        GPIO_Pin_5
+
+/* Òý½ÅÅäÖà °´¼ü */
+#define BSP_GPIO_PORT_BUTTON_1    GPIOA
+#define BSP_GPIO_PIN_BUTTON_1     GPIO_Pin_4
+
+#define BSP_GPIO_PORT_BUTTON_2    GPIOA
+#define BSP_GPIO_PIN_BUTTON_2     GPIO_Pin_5
+
+/* Òý½ÅÅäÖà SPIͨÐÅ½Ó¿Ú */
+#define BSP_GPIO_PORT_SPI_NSS     GPIOB
+#define BSP_GPIO_PIN_SPI_NSS      GPIO_Pin_4
+
+#define BSP_GPIO_PORT_SPI_MOSI    GPIOB
+#define BSP_GPIO_PIN_SPI_MOSI     GPIO_Pin_6
+
+#define BSP_GPIO_PORT_SPI_MISO    GPIOB
+#define BSP_GPIO_PIN_SPI_MISO     GPIO_Pin_7
+
+#define BSP_GPIO_PORT_SPI_SCK     GPIOB
+#define BSP_GPIO_PIN_SPI_SCK      GPIO_Pin_5
+
+/* Òý½ÅÅäÖà ͨÐÅ´®¿Ú */
+#define BSP_GPIO_PORT_UART_TX     GPIOA
+#define BSP_GPIO_PIN_UART_TX      GPIO_Pin_2
+
+#define BSP_GPIO_PORT_UART_RX     GPIOA
+#define BSP_GPIO_PIN_UART_RX      GPIO_Pin_3
+
+/* Òý½ÅÅäÖà EBYTEÎÞÏßÄ£¿é¿ØÖÆ */
+
+
+/* E48 */
+#define BSP_GPIO_PORT_E48_GP0   GPIOC
+#define BSP_GPIO_PIN_E48_GP0    GPIO_Pin_1
+#define BSP_GPIO_PORT_E48_NIRQ  GPIOD
+#define BSP_GPIO_PIN_E48_NIRQ   GPIO_Pin_4
+#define BSP_GPIO_PORT_E48_GP3   GPIOC
+#define BSP_GPIO_PIN_E48_GP3    GPIO_Pin_3
+#define BSP_GPIO_PORT_E48_GP4   GPIOC
+#define BSP_GPIO_PIN_E48_GP4    GPIO_Pin_1
+#define BSP_GPIO_PORT_E48_GP5   GPIOC
+#define BSP_GPIO_PIN_E48_GP5    GPIO_Pin_2
+
+
+
+/* ²ÎÊýÅäÖà SPI */
+#define BSP_RF_SPI                  SPI1
+#define BSP_RF_SPI_CLOCK            CLK_Peripheral_SPI1
+#define Ebyte_BSP_RfSpiSelected()   GPIO_WriteBit( BSP_GPIO_PORT_SPI_NSS , BSP_GPIO_PIN_SPI_NSS, RESET )
+#define Ebyte_BSP_RfSpiUnselected() GPIO_WriteBit( BSP_GPIO_PORT_SPI_NSS , BSP_GPIO_PIN_SPI_NSS, SET )
+
+/* ²ÎÊýÅäÖà ÎÞÏßÄ£¿é¿ØÖÆIO */
+
+/* E07 */
+#define Ebyte_BSP_RfBusyIoRead()  GPIO_ReadInputDataBit( BSP_GPIO_PORT_BUSY , BSP_GPIO_PIN_BUSY)
+#define Ebyte_BSP_RfGdo0IoRead()  GPIO_ReadInputDataBit( BSP_GPIO_PORT_E07_GDO0 , BSP_GPIO_PIN_E07_GDO0)
+#define Ebyte_BSP_RfGdo1IoRead()  GPIO_ReadInputDataBit( BSP_GPIO_PORT_E07_GDO1 , BSP_GPIO_PIN_E07_GDO1)
+/* E10 */
+#define Ebyte_BSP_E10IrqIoRead()  GPIO_ReadInputDataBit( BSP_GPIO_PORT_E10_IRQ , BSP_GPIO_PIN_E10_IRQ)
+#define Ebyte_BSP_E10Dio2Read()   GPIO_ReadInputDataBit( BSP_GPIO_PORT_E10_DIO2 , BSP_GPIO_PIN_E10_DIO2)
+#define Ebyte_BSP_E10Dio3Read()   GPIO_ReadInputDataBit( BSP_GPIO_PORT_E10_DIO3 , BSP_GPIO_PIN_E10_DIO3)
+#define Ebyte_BSP_E10SdnIoLow()   GPIO_WriteBit( BSP_GPIO_PORT_E10_SDN , BSP_GPIO_PIN_E10_SDN, RESET )
+#define Ebyte_BSP_E10SdnIoHigh()  GPIO_WriteBit( BSP_GPIO_PORT_E10_SDN , BSP_GPIO_PIN_E10_SDN, SET )
+/* E49 */
+#define Ebyte_BSP_E49Dio1IoRead() GPIO_ReadInputDataBit( BSP_GPIO_PORT_E49_DIO1 , BSP_GPIO_PIN_E49_DIO1) 
+#define Ebyte_BSP_E49Dio2IoRead() GPIO_ReadInputDataBit( BSP_GPIO_PORT_E49_DIO2 , BSP_GPIO_PIN_E49_DIO2) 
+#define Ebyte_BSP_E49FcsbIoLow()  GPIO_WriteBit( BSP_GPIO_PORT_E49_FCSB , BSP_GPIO_PIN_E49_FCSB, RESET ) 
+#define Ebyte_BSP_E49FcsbIoHigh() GPIO_WriteBit( BSP_GPIO_PORT_E49_FCSB , BSP_GPIO_PIN_E49_FCSB, SET ) 
+#define Ebyte_BSP_E49CsbIoLow()   GPIO_WriteBit( BSP_GPIO_PORT_E49_CSB , BSP_GPIO_PIN_E49_CSB, RESET )
+#define Ebyte_BSP_E49CsbIoHigh()  GPIO_WriteBit( BSP_GPIO_PORT_E49_CSB , BSP_GPIO_PIN_E49_CSB, SET ) 
+#define Ebyte_BSP_E49SlckIoLow()  GPIO_WriteBit( BSP_GPIO_PORT_E49_SLCK , BSP_GPIO_PIN_E49_SLCK, RESET ) 
+#define Ebyte_BSP_E49SlckIoHigh() GPIO_WriteBit( BSP_GPIO_PORT_E49_SLCK , BSP_GPIO_PIN_E49_SLCK, SET ) 
+#define Ebyte_BSP_E49SdioIoLow()  GPIO_WriteBit( BSP_GPIO_PORT_E49_SDIO , BSP_GPIO_PIN_E49_SDIO, RESET ) 
+#define Ebyte_BSP_E49SdioIoHigh() GPIO_WriteBit( BSP_GPIO_PORT_E49_SDIO , BSP_GPIO_PIN_E49_SDIO, SET ) 
+#define Ebyte_BSP_E49SdioIoOutput()  GPIO_Init( BSP_GPIO_PORT_E49_SDIO, BSP_GPIO_PIN_E49_SDIO, GPIO_Mode_Out_PP_High_Fast )
+#define Ebyte_BSP_E49SdioIoInput()   GPIO_Init( BSP_GPIO_PORT_E49_SDIO, BSP_GPIO_PIN_E49_SDIO, GPIO_Mode_In_FL_No_IT )
+#define Ebyte_BSP_E49SdioIoRead()    GPIO_ReadInputDataBit( BSP_GPIO_PORT_E49_SDIO , BSP_GPIO_PIN_E49_SDIO) 
+
+/* E48 */
+#define Ebyte_BSP_E48GPIO4Read()    GPIO_ReadInputDataBit( BSP_GPIO_PORT_E48_GP4 , BSP_GPIO_PIN_E48_GP4) 
+
+/* È«¾ÖÖÐ¶Ï */
+#define Ebyte_BSP_GlobalIntEnable()                __enable_interrupt()
+#define Ebyte_BSP_GlobalIntDisable()               __disable_interrupt()
+
+/* ²ÎÊýÅäÖà UART */
+#define BSP_USER_UART             USART1
+#define BSP_USER_UART_CLOCK       CLK_Peripheral_USART1
+#define BSP_USER_UART_BAUDRATE    9600                  //²¨ÌØÂÊ
+#define BSP_USER_UART_PARITY      USART_Parity_No       //USART_Parity_No:ÎÞУÑé  USART_Parity_Even:ÆæУÑé  USART_Parity_Odd:żУÑé     
+#define BSP_USER_UART_IRQ         USART1_RX_IRQn        //ÖжÏÀàÐÍ
+#define BSP_USER_UART_IRQ_LEVEL   ITC_PriorityLevel_2   //ÓÅÏȼ¶
+
+
+/* ²ÎÊýÅäÖà °´¼üʼþ¶ÓÁÐ */
+#define BSP_BTN_FIFO_LENGTH       16
+
+/* ²ÎÊýÅäÖà µ÷ÊÔ´òÓ¡ÐÅÏ¢ ¹Ø±Õ´òÓ¡ÐèҪעÊ͵ôºê¶¨Òå EBYTE_DEBUG */
+#define EBYTE_DEBUG 
+    
+#ifdef EBYTE_DEBUG
+#define DEBUG(format, ...)  mprintf(format, ##__VA_ARGS__)  
+#else
+#define DEBUG(...)     
+#endif
+    
+typedef enum { BSP_LED_1 = 0, BSP_LED_2 } BSP_LED_t;
+typedef enum { OFF = 0, ON , TOGGLE} BSP_LED_Ctl_t;
+typedef enum { UART_8N1 = 0, UART_8O1, UART_8E1 } BSP_UART_Parity_t;
+
+typedef enum { BSP_BUTTON_1 = 0, BSP_BUTTON_2 } BSP_BUTTON_t;
+typedef enum
+{
+    BTN_1_SHORT, //°´¼ü1 ¶Ì°´ 
+    BTN_1_LONG,	 //°´¼ü1 ³¤°´ 
+    BTN_2_SHORT, //°´¼ü2 ¶Ì°´ 
+    BTN_2_LONG,	 //°´¼ü2 ³¤°´ 
+}BSP_BTN_EVENT_t;
+
+typedef struct
+{
+    uint8_t fifoLen   ;
+    uint8_t fifoRead  ;
+    uint8_t fifoWrite ;
+    uint8_t buff[BSP_BTN_FIFO_LENGTH];
+}BSP_BTN_FIFO_t;
+
+extern BSP_BTN_FIFO_t BSP_BTN_FIFO;
+
+void Ebyte_BSP_Init( void );
+void Ebyte_BTN_FIFO_Init(BSP_BTN_FIFO_t *fifo);
+void Ebyte_BSP_DelayMs( volatile uint32_t nTime );
+void Ebyte_BSP_TimerDecrement(void);
+void Ebyte_BSP_LedControl( BSP_LED_t LEDx , BSP_LED_Ctl_t ctl);
+void Ebyte_BSP_UartTransmit( uint8_t *buffer , uint16_t length );
+
+uint8_t Ebyte_BSP_ReadButton( BSP_BUTTON_t btn );
+uint8_t Ebyte_BSP_SpiTransAndRecv( uint8_t data );
+
+uint8_t Ebyte_BTN_FIFO_Push(BSP_BTN_FIFO_t *fifo, BSP_BTN_EVENT_t event);
+uint8_t Ebyte_BTN_FIFO_Pop(BSP_BTN_FIFO_t *fifo, BSP_BTN_EVENT_t *event);
+uint32_t Ebyte_BSP_TimerGetTick(void);
\ No newline at end of file
diff --git a/NSPE/WIFI_IOT/bsp/drivers/2_Ebyte_Board_Support/E15-EVB02/board_button.c b/NSPE/WIFI_IOT/bsp/drivers/2_Ebyte_Board_Support/E15-EVB02/board_button.c
new file mode 100755
index 0000000..e4472e3
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/2_Ebyte_Board_Support/E15-EVB02/board_button.c
@@ -0,0 +1,96 @@
+/**
+  **********************************************************************************
+  * @file      board_button.c
+  * @brief     ͨÓà °´¼ü¶ÓÁÐÇý¶¯¿â         
+  * @author    JiangHeng     
+  * @date      2021-05-06     
+  * @version   1.0.0     
+  **********************************************************************************
+  * @copyright BSD License 
+  *            ³É¶¼ÒÚ°ÛÌصç×ӿƼ¼ÓÐÏÞ¹«Ë¾  
+  *   ______   ____   __     __  _______   ______ 
+  *  |  ____| |  _ \  \ \   / / |__   __| |  ____|
+  *  | |__    | |_) |  \ \_/ /     | |    | |__   
+  *  |  __|   |  _ <    \   /      | |    |  __|  
+  *  | |____  | |_) |    | |       | |    | |____ 
+  *  |______| |____/     |_|       |_|    |______| 
+  *
+  **********************************************************************************
+  */
+
+#include "board.h"
+
+/* !
+ * @brief °´¼ü¶ÓÁгõʼ»¯
+ * 
+ * @param fifo Ö¸Ïò°´¼üʼþ¶ÓÁнṹÌåµÄÖ¸Õë
+ */
+void Ebyte_BTN_FIFO_Init(BSP_BTN_FIFO_t *fifo)
+{
+    fifo->fifoLen   = 0;
+    fifo->fifoRead  = 0;
+    fifo->fifoWrite = 0;
+}
+
+/* !
+ * @brief °´¼ü¶ÓÁÐÈë¶Ó 
+ * 
+ * @param  fifo  Ö¸Ïò°´¼üʼþ¶ÓÁнṹÌåµÄÖ¸Õë
+ * @param  event °´¼üµÄʼþ  Ö÷ҪΪ¸÷°´¼üµÄ¶Ì°´/³¤°´
+ * @return 0:Õý³£  1:¶ÓÁÐÒç³ö
+ * @note   Èë¶ÓλÖÿÉÑ­»·µ«²»»á¸²¸ÇÒÑÈë¶ÓÊý¾Ý£¬¶ÓÂúʱ»áµ¼ÖÂÊý¾Ý¶ªÊ§£¡
+ */
+uint8_t Ebyte_BTN_FIFO_Push(BSP_BTN_FIFO_t *fifo, BSP_BTN_EVENT_t event)
+{
+    /* Èë¶ÓÊý¾Ý°ü³¤¶ÈÔ¤ÏÈ×ÔÔö */
+    fifo->fifoLen++;
+
+    /* Èç¹ûÈë¶Ó³¤¶È´óÓÚÁËÉ趨³¤¶È */
+    if(fifo->fifoLen > BSP_BTN_FIFO_LENGTH)
+    {
+        fifo->fifoLen = BSP_BTN_FIFO_LENGTH;//Èë¶Ó³¤¶È²»ÔÙÔö¼Ó
+        return 1; 
+    }
+    
+    /* Õý³£Èë¶Ó */
+    fifo->buff[fifo->fifoWrite] = event;
+    
+    /* Èç¹ûÈë¶ÓλÖÃÒѾ­µ½Á˶Óβ */
+    if(++fifo->fifoWrite >= BSP_BTN_FIFO_LENGTH)
+    {
+        fifo->fifoWrite = 0; //ÄÇôÏÂÒ»¸öÈë¶ÓÊý¾Ý½«»Øµ½¶ÓÊ׿ªÊ¼Èë¶Ó
+    }
+
+    return 0;
+
+}
+
+/* !
+ * @brief °´¼ü¶ÓÁгö¶Ó
+ * 
+ * @param fifo  Ö¸Ïò°´¼üʼþ¶ÓÁнṹÌåµÄÖ¸Õë
+ * @param event °´¼üµÄʼþ  Ö÷ҪΪ¸÷°´¼üµÄ¶Ì°´/³¤°´
+ * @return 0:Õý³£  1:¶ÓÁÐΪ¿Õ
+ */
+uint8_t Ebyte_BTN_FIFO_Pop(BSP_BTN_FIFO_t *fifo, BSP_BTN_EVENT_t *event)
+{
+    /* Èç¹ûÈë¶Ó³¤¶ÈΪ0 ¼´¿Õ¶ÓÁÐ */
+    if(fifo->fifoLen == 0)
+    {
+        return 1;
+    }
+    
+    /* Èë¶ÓÊý¾Ý³¤¶È×Ô¼õ */
+    fifo->fifoLen--;
+
+    /* Õý³£³ö¶Ó */
+    *event =  (BSP_BTN_EVENT_t )(fifo->buff[fifo->fifoRead]);
+
+    /* Èç¹û³ö¶ÓλÖÃÒѾ­µ½Á˶Óβ */
+    if(++fifo->fifoRead >= BSP_BTN_FIFO_LENGTH)
+    {
+        fifo->fifoRead = 0;//ÄÇôÏÂÒ»´Î½«´Ó¶ÓÊ׿ªÊ¼³ö¶Ó
+    }
+
+    return 0;
+}
diff --git a/NSPE/WIFI_IOT/bsp/drivers/2_Ebyte_Board_Support/E15-EVB02/board_button.h b/NSPE/WIFI_IOT/bsp/drivers/2_Ebyte_Board_Support/E15-EVB02/board_button.h
new file mode 100755
index 0000000..d3f5a12
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/2_Ebyte_Board_Support/E15-EVB02/board_button.h
@@ -0,0 +1 @@
+
diff --git a/NSPE/WIFI_IOT/bsp/drivers/2_Ebyte_Board_Support/E15-EVB02/board_mini_printf.c b/NSPE/WIFI_IOT/bsp/drivers/2_Ebyte_Board_Support/E15-EVB02/board_mini_printf.c
new file mode 100755
index 0000000..905dc2c
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/2_Ebyte_Board_Support/E15-EVB02/board_mini_printf.c
@@ -0,0 +1,200 @@
+#include "stdarg.h"
+#include "stm8l15x_usart.h"
+#include "board_mini_printf.h"
+
+/* !
+ * @brief Ä¿±êÓ²¼þ´®¿ÚͨÐŽӿÚ
+ * 
+ * @param data дÈëµÄÊý¾Ý 1 Byte
+ */
+static void send_uart_data(uint8_t data)
+{
+  while (USART_GetFlagStatus(USART1, USART_FLAG_TXE) == RESET);
+  USART_SendData8(USART1,data);
+}
+ 
+/*
+  ¹¦ÄÜ£º½«intÐÍÊý¾ÝתΪ2£¬8£¬10£¬16½øÖÆ×Ö·û´®
+  ²ÎÊý£ºvalue --- ÊäÈëµÄintÕûÐÍÊý
+        str --- ´æ´¢×ª»»µÄ×Ö·û´®
+        radix --- ½øÖÆÀàÐÍÑ¡Ôñ
+  ×¢Ò⣺8λµ¥Æ¬»úint×Ö½ÚÖ»Õ¼2¸ö×Ö½Ú
+*/
+static char *sky_itoa(int value, char *str, unsigned int radix)
+{
+  char list[] = "0123456789ABCDEF";
+  unsigned int tmp_value;
+  int i = 0, j, k = 0;
+//  if (NULL == str) {
+  if (0 == str) {
+//    return NULL;
+    return 0;
+  }
+  if (2 != radix && 8 != radix && 10 != radix && 16 != radix) {
+//    return NULL;
+    return 0;
+  }
+  if (radix == 10 && value < 0) {
+    //Ê®½øÖÆÇÒΪ¸ºÊý
+    tmp_value = (unsigned int)(0 - value);
+    str[i++] = '-';
+    k = 1;
+  } else {
+    tmp_value = (unsigned int)value;
+  }
+  //Êý¾Ýת»»Îª×Ö·û´®£¬ÄæÐò´æ´¢
+  do {
+    str[i ++] = list[tmp_value%radix];
+    tmp_value /= radix;
+  } while(tmp_value);
+  str[i] = '\0';
+  //½«ÄæÐò×Ö·û´®×ª»»ÎªÕýÐò
+  char tmp;
+  for (j = k; j < (i+k)/2; j++) {
+    tmp = str[j];
+    str[j] = str[i-j-1+k];
+    str[i-j-1+k] = tmp;
+  }
+  return str;
+}
+ 
+/*
+  ¹¦ÄÜ£º½«doubleÐÍÊý¾ÝתΪ×Ö·û´®
+  ²ÎÊý£ºvalue --- ÊäÈëµÄdouble¸¡µãÊý
+        str --- ´æ´¢×ª»»µÄ×Ö·û´®
+        eps --- ±£ÁôСÊýλѡÔñ£¬ÖÁÉÙ±£ÁôÒ»¸öСÊýλ,ÖÁ¶à±£Áô4¸öСÊýλ
+  ×¢Ò⣺8λµ¥Æ¬»úint×Ö½ÚÖ»Õ¼2¸ö×Ö½Ú
+*/
+static void sky_ftoa(double value, char *str, unsigned int eps)
+{
+  unsigned int integer;
+  double decimal;
+  char list[] = "0123456789";
+  int i = 0, j, k = 0;
+  //½«ÕûÊý¼°Ð¡Êý²¿·ÖÌáÈ¡³öÀ´
+  if (value < 0) {
+    decimal = (double)(((int)value) - value);
+    integer = (unsigned int)(0 - value);
+    str[i ++] = '-';
+    k = 1;
+  } else {
+    integer = (unsigned int)(value);
+    decimal = (double)(value - integer);
+  }
+  //ÕûÊý²¿·ÖÊý¾Ýת»»Îª×Ö·û´®£¬ÄæÐò´æ´¢
+  do {
+    str[i ++] = list[integer%10];
+    integer /= 10;
+  } while(integer);
+  str[i] = '\0';
+  //½«ÄæÐò×Ö·û´®×ª»»ÎªÕýÐò
+  char tmp;
+  for (j = k; j < (i+k)/2; j++) {
+    tmp = str[j];
+    str[j] = str[i-j-1+k];
+    str[i-j-1+k] = tmp;
+  }
+  //´¦ÀíСÊý²¿·Ö
+  if (eps < 1 || eps > 4) {
+    eps = 4;
+  }
+  
+  //¾«¶ÈÎÊÌ⣬·ÀÖ¹ÊäÈë1.2Êä³ö1.19µÈÇé¿ö
+  double pp = 0.1;
+  for (j = 0; j <= eps; j++) {
+    pp *= 0.1;
+  }
+  decimal += pp;
+  while (eps) {
+    decimal *= 10;
+    eps --;
+  }
+  int tmp_decimal = (int)decimal;
+  str[i ++] = '.';
+  k = i;
+  //ÕûÊý²¿·ÖÊý¾Ýת»»Îª×Ö·û´®£¬ÄæÐò´æ´¢
+  do {
+    str[i ++] = list[tmp_decimal%10];
+    tmp_decimal /= 10;
+  } while(tmp_decimal);
+  str[i] = '\0';
+  //½«ÄæÐò×Ö·û´®×ª»»ÎªÕýÐò
+  for (j = k; j < (i+k)/2; j++) {
+    tmp = str[j];
+    str[j] = str[i-j-1+k];
+    str[i-j-1+k] = tmp;
+  }
+  str[i] = '\0';
+}
+ 
+ 
+void mprintf(char * Data, ...)
+{
+  const char *s;
+  int d;   
+  char buf[16];
+  uint8_t txdata;
+  va_list ap;
+  va_start(ap, Data);
+  while ( * Data != 0 ) {				                          
+    if ( * Data == 0x5c )  {									  
+      switch ( *++Data ) {
+        case 'r':							          
+          txdata = 0x0d;
+          send_uart_data(txdata);
+          Data ++;
+          break;
+        case 'n':							          
+          txdata = 0x0a;
+          send_uart_data(txdata);
+          Data ++;
+          break;
+        default:
+          Data ++;
+          break;
+      }			 
+    } else if ( * Data == '%') {									  
+      switch ( *++Data ) {				
+      case 's':										 
+        s = va_arg(ap, const char *);
+        for ( ; *s; s++) {
+          send_uart_data(*((uint8_t *)s));
+        }				
+        Data++;				
+        break;
+      case 'd':			
+        d = va_arg(ap, int);					
+        sky_itoa(d, buf, 10);					
+        for (s = buf; *s; s++) {
+          send_uart_data(*((uint8_t *)s));
+        }					
+        Data++;				
+        break;
+      case 'x': {
+        d = va_arg(ap, int);					
+        sky_itoa(d, buf, 16);					
+        for (s = buf; *s; s++) {
+          send_uart_data(*((uint8_t *)s));
+        }					
+        Data++;			
+        break;
+      }
+      case 'f': {
+        double num = va_arg(ap, double);					
+        sky_ftoa(num, buf, 4);
+        for (s = buf; *s; s++) {
+          send_uart_data(*((uint8_t *)s));
+        }					
+        Data++;			
+        break;
+      }
+      default:
+        Data++;				
+        break;				
+      }		 
+    } else {
+        send_uart_data(*((uint8_t *)Data));
+        Data++;
+    }
+  }
+}
\ No newline at end of file
diff --git a/NSPE/WIFI_IOT/bsp/drivers/2_Ebyte_Board_Support/E15-EVB02/board_mini_printf.h b/NSPE/WIFI_IOT/bsp/drivers/2_Ebyte_Board_Support/E15-EVB02/board_mini_printf.h
new file mode 100755
index 0000000..a4de959
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/2_Ebyte_Board_Support/E15-EVB02/board_mini_printf.h
@@ -0,0 +1,2 @@
+
+void mprintf(char * Data, ...);
\ No newline at end of file
diff --git a/NSPE/WIFI_IOT/bsp/drivers/3_Ebyte_WirelessModule_Drivers/E48xMx/CMT2310A_def.h b/NSPE/WIFI_IOT/bsp/drivers/3_Ebyte_WirelessModule_Drivers/E48xMx/CMT2310A_def.h
new file mode 100755
index 0000000..f4d5a20
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/3_Ebyte_WirelessModule_Drivers/E48xMx/CMT2310A_def.h
@@ -0,0 +1,578 @@
+/*
+ * THE FOLLOWING FIRMWARE IS PROVIDED: (1) "AS IS" WITH NO WARRANTY; AND
+ * (2)TO ENABLE ACCESS TO CODING INFORMATION TO GUIDE AND FACILITATE CUSTOMER.
+ * CONSEQUENTLY, CMOSTEK SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR
+ * CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
+ * OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
+ * CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * Copyright (C) CMOSTEK SZ.
+ */
+
+/*!
+ * @file    CMT2310A_def.h
+ * @brief   CMT2310A transceiver RF chip driver
+ *
+ * @version 1.0
+ * @date    Dec 7 2021
+ * @author  CMOSTEK R&D
+ */
+
+
+#ifndef __CMT2310A_DEF_H
+
+#define __CMT2310A_DEF_H
+
+//Exit State
+#define     EXIT_TO_SLEEP                   1
+#define     EXIT_TO_READY                   2
+#define     EXIT_TO_TFS                     3
+#define     EXIT_TO_TX                      4
+#define     EXIT_TO_RFS                     5
+#define     EXIT_TO_RX                      6
+
+//Prefxi select
+#define     TX_PREFIX_SEL_0                 0
+#define     TX_PREFIX_SEL_1                 1
+#define     TX_PREFIX_SEL_PREAMBLE          2
+
+//## interrupt source config
+typedef union
+{
+    struct
+    {
+        uint8_t  PKT_DONE_EN:         1;      //pkt_done_en               //bit0
+        uint8_t  CRC_PASS_EN:         1;      //crc_pass_en               //bit1
+        uint8_t  ADDR_PASS_EN:        1;      //node_address_pass_en      //bit2
+        uint8_t  SYNC_PASS_EN:        1;      //sync_pass_en              //bit3
+        uint8_t  PREAM_PASS_EN:       1;      //preamble_pass_en          //bit4
+        uint8_t  TX_DONE_EN:          1;      //tx_done_en                //bit5
+        uint8_t  RX_TOUT_EN:          1;      //rx_timeout_en             //bit6
+        uint8_t  SLP_TOUT_EN:         1;      //sleep_timeout_en          //bit7
+
+        uint8_t  LD_STOP_EN:          1;      //ld_stop_en(PLL lock detect)//bit0
+        uint8_t  LBD_STOP_EN:         1;      //lbd_stop_en               //bit1
+        uint8_t  LBD_STAT_EN:         1;      //lbd_status_en             //bit2
+        uint8_t  PKT_ERR_EN:          1;      //pkt_err_en                //bit3
+        uint8_t  RSSI_COLL_EN:        1;      //rssi_collision_en         //bit4
+        uint8_t  OP_CMD_FAILED_EN:    1;      //op_cmd_failed_en          //bit5
+        uint8_t  RSSI_PJD_EN:         1;      //rssi_pjd_valid_en         //bit6
+        uint8_t  RESV_2_1:            1;      //reserve, don't used       //bit7
+
+        uint8_t  SEQ_MATCH_EN:        1;      //seq_match_en              //bit0
+        uint8_t  NACK_RECV_EN:        1;      //nack_recv_en              //bit1
+        uint8_t  TX_RESEND_DONE_EN:   1;      //tx_resend_done_en         //bit2
+        uint8_t  ACK_RECV_FAILED_EN:  1;      //ack_recv_failed_en        //bit3
+        uint8_t  TX_DC_DONE_EN:       1;      //tx_dc_done_en             //bit4
+        uint8_t  CSMA_DONE_EN:        1;      //csma_max_en               //bit5
+        uint8_t  CCA_STAT_EN:         1;      //cca_status_en             //bit6
+        uint8_t  API_DONE_EN:         1;      //api_done_en               //bit7
+
+        uint8_t  TX_FIFO_TH_EN:       1;      //tx_fifo_threshold_en      //bit0
+        uint8_t  TX_FIFO_NMTY_EN:     1;      //tx_fifo_non_empty_en      //bit1
+        uint8_t  TX_FIFO_FULL_EN:     1;      //tx_fifo_full_en           //bit2
+        uint8_t  RX_FIFO_OVF_EN:      1;      //rx_fifo_overflow_en       //bit3
+        uint8_t  RESV_4_1:            1;      //reserve, don't used       //bit4
+        uint8_t  RX_FIFO_TH_EN:       1;      //rx_fifo_threshold_en      //bit5
+        uint8_t  RX_FIFO_NMTY_EN:     1;      //rx_fifo_non_empty_en      //bit6
+        uint8_t  RX_FIFO_FULL_EN:     1;      //rx_fifo_full_en           //bit7
+    } _BITS;
+    struct
+    {
+        uint8_t INT_CTL1_REG;                 //CTL_REG_18, 0x12
+        uint8_t INT_CTL2_REG;                 //CTL_REG_21, 0x15
+        uint8_t INT_CTL3_REG;                 //CTL_REG_23, 0x17
+        uint8_t INT_CTL4_REG;                 //CTL_REG_14, 0x0E
+    } _BYTE;
+} INT_SRC_CFG;
+
+//## interrupt flag
+typedef union
+{
+    struct
+    {
+        uint8_t  RESV_3:              3;      //reserve, don't used       //bit0/1/2
+        uint8_t  TX_DONE_FLG:         1;      //tx_done_flag              //bit3
+        uint8_t  RX_TMO_FLG:          1;      //rx_timer_timeout_flag     //bit4
+        uint8_t  SLEEP_TMO_FLG:       1;      //sleep_timer_timeout_flag  //bit5
+        uint8_t  RESV_2:              2;      //reserve, don't used       //bit6/7
+
+        uint8_t  PKT_DONE_FLG:        1;      //pkt_done_flag             //bit0
+        uint8_t  CRC_PASS_FLG:        1;      //crc_pass_flag             //bit1
+        uint8_t  ADDR_PASS_FLG:       1;      //addr_pass_flag            //bit2
+        uint8_t  SYNC_PASS_FLG:       1;      //sync_pass_flag            //bit3
+        uint8_t  PREAM_PASS_FLG:      1;      //preamble_pass_flag        //bit4
+        uint8_t  SYNC1_PASS_FLG:      1;      //sync1_pass_flag           //bit5
+        uint8_t  RESV_2_2:            2;      //reserve, don't used       //bit6/7
+
+        uint8_t  LBD_STATUS_FLG:      1;      //lbd_status_flag           //bit0
+        uint8_t  PKT_ERR_FLG:         1;      //pkt_err_flag              //bit1
+        uint8_t  RSSI_COLL_FLG:       1;      //rssi_collision_flag       //bit2
+        uint8_t  OP_CMD_FAILED_FLG:   1;      //op_cmd_failed_flag        //bit3
+        uint8_t  ANT_LOCK_FLG:        1;      //ant_lock_flag             //bit4
+        uint8_t  RESV_3_3:            3;      //reserve, don't used       //bit5/6/7
+
+        uint8_t  SEQ_MATCH_FLG:       1;      //seq_match_flag            //bit0
+        uint8_t  NACK_RECV_FLG:       1;      //nack_recv_flag            //bit1
+        uint8_t  TX_RESEND_DONE_FLG:  1;      //tx_resend_max_flag        //bit2
+        uint8_t  ACK_RECV_FAILED_FLG: 1;      //ack_recv_failed_flag      //bit3
+        uint8_t  TX_DC_DONE_FLG:      1;      //tx_dc_done_flag           //bit4
+        uint8_t  CSMA_DONE_FLG:       1;      //csma_done_flag            //bit5
+        uint8_t  CCA_STATUS_FLG:      1;      //cca_status_flag           //bit6
+        uint8_t  API_DONE_FLG:        1;      //api_done_flag             //bit7
+    } _BITS;
+    struct
+    {
+        uint8_t INT_FLAG1_REG;                //CTL_REG_24, 0x18
+        uint8_t INT_FLAG2_REG;                //CTL_REG_26, 0x1A
+        uint8_t INT_FLAG3_REG;                //CTL_REG_30, 0x1E
+        uint8_t INT_FLAG4_REG;                //CTL_REG_32, 0x20
+    } _BYTE;
+} INT_SRC_FLG;
+
+//## interrupt clear
+typedef union
+{
+    struct
+    {
+        uint8_t  TX_DONE_CLR:         1;      //tx_done_clr                   //bit0
+        uint8_t  RX_TMO_CLR:          1;      //rx_timer_timeout_clr          //bit1
+        uint8_t  SLEEP_TMO_CLR:       1;      //sleep_timer_timeout_clr       //bit2
+        uint8_t  RESV_5:              5;      //reserve, don't used           //bit3-7
+
+        uint8_t  PKT_DONE_CLR:        1;      //pkt_done_clr                  //bit0
+        uint8_t  CRC_PASS_CLR:        1;      //crc_pass_clr                  //bit1
+        uint8_t  ADDR_PASS_CLR:       1;      //addr_pass_clr                 //bit2
+        uint8_t  SYNC_PASS_CLR:       1;      //sync_pass_clr                 //bit3
+        uint8_t  PREAM_PASS_CLR:      1;      //preamble_pass_clr             //bit4
+        uint8_t  RESV_3:              3;      //reserve, don't used           //bit5/6/7
+
+        uint8_t  LBD_STAT_CLR:        1;      //lbd_status_clr                //bit0
+        uint8_t  PKT_ERR_CLR:         1;      //packet_err_clr                //bit1
+        uint8_t  RSSI_COLL_CLR:       1;      //rssi_collision_clr            //bit2
+        uint8_t  OP_CMD_FAILED_CLR:   1;      //op_cmd_failed_clr             //bit3
+        uint8_t  ANT_LOCK_CLR:        1;      //antenna_lock_clr              //bit4
+        uint8_t  RESV_2_3:            3;      //reserve, don't used           //bit5/6/7
+
+        uint8_t  SEQ_MATCH_CLR:       1;      //seq_match_clr                 //bit0
+        uint8_t  NACK_RECV_CLR:       1;      //nack_recv_clr                 //bit1
+        uint8_t  TX_RESEND_DONE_CLR:  1;      //tx_resend_done_clr            //bit2
+        uint8_t  ACK_RECV_FAILED_CLR: 1;      //ack_recv_failed_clr           //bit3
+        uint8_t  TX_DC_DONE_CLR:      1;      //tx_dc_done_clr                //bit4
+        uint8_t  CSMA_DONE_CLR:       1;      //csma_done_clr                 //bit5
+        uint8_t  CCA_STATUS_CLR:      1;      //cca_status_clr                //bit6
+        uint8_t  API_DONE_CLR:        1;      //api_done_clr                  //bit7
+    } _BITS;
+    struct
+    {
+        uint8_t INT_CLR1_REG;                 //CTL_REG_24, 0x18
+        uint8_t INT_CLR2_REG;                 //CTL_REG_25, 0x19
+        uint8_t INT_CLR3_REG;                 //CTL_REG_29, 0x1D
+        uint8_t INT_CLR4_REG;                 //CTL_REG_31, 0x1F
+    } _BYTE;
+} INT_SRC_CLR;
+
+//## fifo status flag
+typedef union
+{
+    struct
+    {
+        uint8_t  TX_FIFO_TH_FLG:      1;      //tx_fifo_threshold_flag        //bit0
+        uint8_t  TX_FIFO_NMTY_FLG:    1;      //tx_fifo_non_empty_flag        //bit1
+        uint8_t  TX_FIFO_FULL_FLG:    1;      //tx_fifo_full_flag             //bit2
+        uint8_t  RX_FIFO_OVF_FLG:     1;      //rx_fifo_overflow_flag         //bit3
+        uint8_t  RESV_1:              1;      //reserve, don't used           //bit4
+        uint8_t  RX_FIFO_TH_FLG:      1;      //rx_fifo_threshold_flag        //bit5
+        uint8_t  RX_FIFO_NMTY_FLG:    1;      //rx_fifo_non_empty_flag        //bit6
+        uint8_t  RX_FIFO_FULL_FLG:    1;      //rx_fifo_full_flag             //bit7
+    } _BITS;
+    uint8_t FIFO_FLG_REG;                     //CTL_REG_28, 0x1c
+} FIFO_STATUS_FLG;
+
+
+//## packet preamble config
+typedef struct                                      //Packet Preamble
+{
+    uint8_t PREAM_LENG_UNIT;                  //0=preamble unit as 8bits,   !0=preamble unit as 4bits (nibble mode)
+    uint8_t PREAM_VALUE;                      //preamble value
+    uint8_t RX_PREAM_SIZE;                    //rx preamble length, range: 0-31, 0==disable rx preamble detect
+    uint16_t TX_PREAM_SIZE;               //tx preamble length                    //## note: for arm mcu uint16_t is 16bits
+} PREAMBLE_CFG;
+
+//## packet syncword config
+typedef struct
+{
+    union
+    {
+        struct
+        {
+            uint8_t  SYNC_MAN_EN:     1;      //sync word manchester coding enable
+            uint8_t  SYNC_SIZE:       3;      // n+1 bytes
+            uint8_t  SYNC_TOL:        3;      // n bits tolerence error
+            uint8_t  SYNC_MODE_SEL:   1;      // 0: compatible S2LP;  1: compatible 802.15.4
+        } _BITS;
+        uint8_t SYNC_CFG_REG;                 //CTL_REG_44, 0x2c
+    } SYN_CFG_u;
+    uint8_t SYNC_VALUE[8];                    //CTL_REG_45-CTL_REG_53, 0x2D-0x34
+    uint8_t SYNC_FEC_VALUE[8];                //CTL_REG_53-CTL_REG_60, 0x35-0x3C
+    uint8_t SYNC_VALUE_SEL;                   // 0: select SYN_VAL;  !0: select SYN_FEC_VAL
+} SYNC_CFG;
+
+//## packet node address config
+typedef struct
+{
+    union
+    {
+        struct
+        {
+            uint8_t  ADDR_DET_MODE:   2;      //node address mode: 0,disable;  1,only match;  2,add all 0;  3,add all 1 & 0
+            uint8_t  ADDR_SIZE:       2;      // n+1 bytes
+            uint8_t  ADDR_ERR_MASK:   1;      // 0: trigger PKT_ERR flag, when node address not match, and reset decode;   1: non-reset decode, when node address not match
+            uint8_t  ADDR_FREE_EN:    1;      // 0: disable;   1: enable node address match as stand-alone working
+            uint8_t  ADDR_SPLIT_MODE: 1;      // 0: disable, dest_addr==node_addr;    1: enable, node_addr==src_addr+des_addr
+            uint8_t  RESV_1:          1;
+        } _BITS;
+        uint8_t ADDR_CFG_REG;                 //CTL_REG_64, 0x40
+    } ADDR_CFG_u;
+    uint8_t SRC_ADDR[2];                      //CTL_REG_65, CTL_REG_66
+    uint8_t DEST_ADDR[2];                     //CTL_REG_67, CTL_REG_68
+    uint8_t SRC_BITMASK[2];                   //CTL_REG_69, CTL_REG_70
+    uint8_t DEST_BITMASK[2];                  //CTL_REG_71, CTL_REG_72
+} ADDR_CFG;
+
+//## packet crc config
+typedef struct
+{
+    union
+    {
+        struct
+        {
+            uint8_t  CRC_EN:              1;  // 0:disable CRC;                       1:enable CRC
+            uint8_t  CRC_BIT_ORDER:       1;  // 0:crc result MSB output first;       1:crc result LSB output first;      active unit is byte
+            uint8_t  CRC_REFIN:           1;  // 0:normal input;                      1:inverse input;
+            uint8_t  CRC_RANGE:           1;  // 0:whole payload;                     1:only data
+            uint8_t  CRC_BIT_INV:         1;  // 0:crc result non-invert;             1:crc result all bits invert
+            uint8_t  CRC_BYTE_SWAP:       1;  // 0:crc result HighByte output first;  1:crc result LowByte output first
+            uint8_t  CRC_SIZE:            2;  // 0:crc8;  1:crc16;  2:crc24;  3:crc32
+            uint8_t  CRC_REFOUT:          1;  // 0:result whole bit MSB->LSB          1:result whole bit LSB->MSB
+            uint8_t  CRCERR_CLR_FIFO_EN:  1;  // 0:disable                            1:enable when crc error, clear fifo function
+            uint8_t  RESV_6:              6;
+        } _BITS;
+        uint16_t CRC_CFG_REG;             //CTL_REG_73, 0x49 & CTL_REG_82[7] & CTL_REG_84[7]
+    } CRC_CFG_u;
+    union                                           //CTL_REG_74-CTL_REG_77, 0x4A-0x4D          //## note: for arm mcu uint32_t is 32bits
+    {
+        uint8_t u8_SEED[4];
+        uint32_t  u32_SEED;
+    } CRC_SEED_u;
+    union                                           //CTL_REG_78-CTL_REG_81, 0x4E-0x51          //## note: for arm mcu uint32_t is 32bits
+    {
+        uint8_t u8_POLY[4];
+        uint32_t  u32_POLY;
+    } CRC_POLY_u;
+} CRC_CFG;
+
+//## packet encode/decode format config
+typedef struct
+{
+    union
+    {
+        struct
+        {
+            uint8_t   MANCH_EN:           1;  // 0:disable manchester coding;         1:enable manchester coding
+            uint8_t   MANCH_TYPE:         1;  // 0: 2'b01=1, 2'b10=0;                 1: 2'b01=0, 2'b10=1
+            uint8_t   WHITEN_EN:          1;  // 0:disable whiten coding;             1:enable whiten coding
+            uint8_t   WHITEN_TYPE:        2;  // 0:PN9-CCITT,  1:PN9-IBM,   2:PN7,    3:NA
+            uint8_t   WHITEN_SEED_TYP:    1;  // 0:compatible A7139;                  1:customer seed;          note: when select PN7 active
+            uint8_t   RESV_2:             2;
+            uint8_t   FEC_EN:             1;  // 0:disable FEC Coding;                1:enable FEC Coding
+            uint8_t   FEC_RSC_NRNSC_SEL:  1;  // 0:RSC Mode;                          1:NRNSC Mode
+            uint8_t   RESV_5:             5;
+            uint8_t   FEC_TICC:           1;  // 0:ui invert ouput in FEC calucate;   1:ui non-invert ouput in FEC calucate
+        } _BITS;
+        uint16_t CODING_CFG_REG;          // CTL_REG_82, 0x52 & CTL_REG_93, 0x5D
+    } CODING_FORMAT_CFG_u;
+    uint16_t WHITEN_SEED;                 // CTL_REG_83, 0x53 & CTL_REG_82[6]
+    uint16_t FEC_PAD_CODE;                // CTL_REG_94, 0x5E & CTL_REG_93[6:2], 0x5D
+} CODING_FORMAT_CFG;
+
+//## frame struct config
+typedef struct
+{
+    uint8_t DATA_MODE;                        //0: direct mode;           2: packet mode;      1&3: na
+    union
+    {
+        struct
+        {
+            uint8_t   PKT_TYPE:           1;  //0: fixed length;          1: variable length
+            uint8_t   PAYLOAD_BIT_ORDER:  1;  //0: MSB output first;      1: LSB output first
+            uint8_t   ADDR_LEN_CONF:      1;  //0: node_addr+length;      1: length+node_addr
+            uint8_t   ADDR_FIELD_EN:      1;  //0: disable;               1: enable address field
+            uint8_t   PAGGYBACKING_EN:    1;  //0: disable                1: enable
+            uint8_t   LENGTH_SIZE:        1;  //0: length range 1 byte;   1: length range 2 bytes
+            uint8_t   RESV_1_2:           1;
+            uint8_t   INTERLEAVE_EN:      1;  //0: disable interleave     1: enable interleave
+        } _BITS;
+        uint8_t FRAME_CFG1_REG;               //CTL_REG_63, 0x3F
+    } FRAME_CFG1_u;
+    union
+    {
+        struct
+        {
+            uint8_t   TX_PREFIX_TYPE:     2;  //0:transmit_0;     1:transmit_1;       2:transmit_preamble     3:NA
+            uint8_t   SEQNUM_EN:          1;  //0:disable;        1:enable;     note: SEQ_NUM is the same with FCS1
+            uint8_t   SEQNUM_AUTO_INC:    1;  //0:disable SEQNUM increase;    1:enable
+            uint8_t   SEQNUM_SIZE:        1;  //0:1byte for SEQNUM;           1:2bytes for SEQNUM
+            uint8_t   SEQNUM_MACH_EN:     1;  //0:disable;                    1:enable compare with local SEQNUM, when TX_ACK enable
+            uint8_t   FCS2_EN:            1;  //0:not include FCS2 filed;     1:include FCS2 filed
+            uint8_t   RESV_1:             1;
+        } _BITS;
+        uint8_t FRAME_CFG2_REG;               //CTL_REG_84, 0x54
+    } FRAME_CFG2_u;
+
+    uint16_t TX_PKT_NUM;                  //CTL_REG_85, 0x55[7:0] & CTL_REG_86, 0x56[15:8]
+    uint16_t SEQNUM_TX_IN;                //CTL_REG_88/87, 0x58[15:8], 0x57[7:0]
+    uint16_t SEQNUM_TX_CURRENT_OUT;       //CTL_REG_39/38, 0x27[15:8]/0x26[7:0]
+    uint8_t      TX_PKT_GAP;                  //CTL_REG_89, 0x59
+    uint8_t      FCS2_TX_IN;                  //CTL_REG_91, 0x5B
+    uint8_t      FCS2_RX_OUT;                 //CTL_REG_92, 0x5C
+    uint16_t PAYLOAD_LENGTH;              //CTL_REG_62/61, 0x3E[15:8], 0x3D[7:0]
+} FRAME_CFG;
+
+//## Wi-SUN V1.0 packet format compatible
+typedef union
+{
+    struct
+    {
+        uint8_t  WISUN_DW:            1;      // 0:not whiten,                        1: whiten
+        uint8_t  WISUN_FCS:           1;      // 0:CRC-32 for PSDU,                   1: CRC-16 for PSDU
+        uint8_t  RESV_2:              2;      //
+        uint8_t  WISUN_MS:            1;      // default for 0
+        uint8_t  WHITEN_WISUN:        1;      // 0: for normal used,                  1: for Wi-SUN whitenning
+        uint8_t  WISUN_ALLIN:         1;      // 0: WISUN_FCS & WISUN_DW not active,  1: FCS & DW depend on WISUN_FCS & WISUN_DW,
+        uint8_t  LENGTH_MODE:         1;      // 0: for normal used,                  1: for Wi-SUN used, PSDU length filed is 11bits
+    } _BITS;
+    uint8_t WI_SUN_REG;                       //CTL_REG_111, 0x6F
+} WI_SUN_CFG;
+
+//## working mode
+typedef struct
+{
+    union
+    {
+        struct
+        {
+            uint8_t   TX_DC_EN:           1;  //0:disable TxDutyCycle;    1:enable
+            uint8_t   TX_DC_PERSIST_EN:   1;  //0:run TX_DC_TIMES;        1:always run until this bit set 0
+            uint8_t   TX_ACK_EN:          1;  //0:disable                 1:enable
+            uint8_t   TX_AUTO_HOP_EN:     1;  //0:disable                 1:enable tx frequency auto hopping
+            uint8_t   TX_EXIT_STATE:      3;  //1:Sleep, 2:Ready, 3:TFS, 4:TX, 5:RFS, 6:RX, other Sleep
+            uint8_t   RESV:               1;
+        } _BITS;
+        uint8_t WORK_MODE_CFG1_REG;           //CTL_REG_96, 0x60
+    } WORK_MODE_CFG1_u;
+
+    union
+    {
+        struct
+        {
+            uint8_t   RX_DC_EN:           1;  //0:disable RxDutyCycle;    1:enable
+            uint8_t   RX_AUTO_HOP_EN:     1;  //0:disable RxAutoHop;      1:enable
+            uint8_t   RX_ACK_EN:          1;  //0:disable                 1:enable
+            uint8_t   RX_TIMER_EN:        1;  //0:disable                 1:enable
+            uint8_t   RX_EXIT_STATE:      3;  //1:Sleep, 2:Ready, 3:TFS, 4:TX, 5:RFS, 6:RX, other Sleep
+            uint8_t   CSMA_EN:            1;  //0:disable                 1:enable
+        } _BITS;
+        uint8_t WORK_MODE_CFG2_REG;           //CTL_REG_97, 0x61
+    } WORK_MODE_CFG2_u;
+
+    union
+    {
+        struct
+        {
+            uint8_t   SLP_MODE:           4;  //14 items for select
+            uint8_t   RX_HOP_SLP_MODE:    3;  //7 items for select
+            uint8_t   PKT_DONE_EXIT_EN:   1;  //0:keep on current state;      1:depends on RX_EXIT_STATE
+        } _BITS;
+        uint8_t WORK_MODE_CFG3_REG;           //CTL_REG_98, 0x62
+    } WORK_MODE_CFG3_u;
+
+    union
+    {
+        struct
+        {
+            uint8_t   LFCLK_OUT_EN:       1;  //0:disable;    1:enable LFCLK output to GPIO4
+            uint8_t   LFCLK_SEL:          1;  //0:LFOSC;      1:LFXO (32768Hz)
+            uint8_t   RESV_1:             1;  //
+            uint8_t   SLEEP_TIMER_EN:     1;  //0:disable     1:enable
+            uint8_t   TIMER_RAND_MODE:    2;  //00:random R,   01:random M,   10:both M&R random,   11:depends on config value
+            uint8_t   RESV_2:             2;
+        } _BITS;
+        uint8_t WORK_MODE_CFG4_REG;           //CTL_REG_105, 0x69
+    } WORK_MODE_CFG4_u;
+
+    union
+    {
+        struct
+        {
+            uint8_t   CSMA_CCA_WIN_SEL:   2;  //00:32symbol,  01:64symbol,  10:128symbol,   11:256symbol
+            uint8_t   CSMA_CCA_INT_SEL:   2;  //00:PJD,       01:RSSI,      10:PJD & RSSI,  11:NA
+            uint8_t   CSMA_PERSIST_EN:    1;  //0:auto exit when reach max & channel still busy,  1:keep on work until send out
+            uint8_t   CSMA_CCA_MODE:      3;  //000:idle,     001:>=1 RSSI,          010:>=1 PJD,          011:>=1 RSSI or PJD,
+            //100:>=1 SYNC, 101:>=1 SYNC or RSSI,  110:>=1 SYNC or PJD,  111:>=1 SYNC or PJD or RSSI
+        } _BITS;
+        uint8_t WORK_MODE_CFG5_REG;           //CTL_REG_106, 0x6A
+    } WORK_MODE_CFG5_u;
+
+    union
+    {
+        struct
+        {
+            uint8_t   RESV_5:             5;
+            uint8_t   FREQ_SW_STATE:      1;  //0:switch to RFS/TFS, and then to the next channel;   1:switch to RDY, and then to the next channel;
+            uint8_t   RX_HOP_PERSIST:     1;  //0:depend on TX/RX_EXIT_STATE,                        1:go on next cycle from 0 label
+            uint8_t   FREQ_HOP_MANU_EN:   1;  //0:auto hopping mode;  1:hopping by manual
+
+        } _BITS;
+        uint8_t WORK_MODE_CFG6_REG;
+    } WORK_MODE_CFG6_u;                         //CTL_REG_22, 0x16
+
+    uint8_t      FREQ_CHANL_NANU;             //CTL_REG_3,  0x03, frequency hopping by manual, set channel number
+    uint8_t      FREQ_DONE_TIMES;             //CTL_REG_11, 0x0B, auto frequency hopping times have done
+    uint8_t      FREQ_SPACE;                  //CTL_REG_12, 0x0C, auto frequency channel interval
+    uint8_t      FREQ_TIMES;                  //CTL_REG_13, 0x0D, auto frequency hopping set range, 1-64
+
+    uint16_t SLEEP_TIMER_M;               //CTL_REG_100[7:5]|CLT_REG_99, 11bits, 0x64,0x63
+    uint8_t      SLEEP_TIMER_R;               //CTL_REG_100[4:0], 0x64
+    uint16_t RX_TIMER_T1_M;               //CTL_REG_102[7:5]|CLT_REG_101, 11bits, 0x66, 0x65
+    uint8_t      RX_TIMER_T1_R;               //CTL_REG_102[4:0], 0x66
+    uint16_t RX_TIMER_T2_M;               //CTL_REG_104[7:5]|CLT_REG_103, 11bits, 0x68, 0x67
+    uint8_t      RX_TIMER_T2_R;               //CTL_REG_104[4:0], 0x68
+    uint16_t RX_TIMER_CSMA_M;             //CTL_REG_108[7:5]|CLT_REG_107, 11bits, 0x6C,0x6B
+    uint8_t      RX_TIMER_CSMA_R;             //CTL_REG_108[4:0], 0x6C
+    uint8_t      TX_DC_TIMES;                 //CTL_REG_110, 0x6E, tx duty cycle, set maximum times
+    uint8_t      TX_DC_DONE_TIMES;            //CTL_REG_112, 0x70, tx duty cycle, times have done
+    uint8_t      TX_RS_TIMES;                 //CTL_REG_113, 0x71, tx ack mode, set maximum times
+    uint8_t      TX_RS_DONE_TIMES;            //CLT_REG_114, 0x72, tx ack mode, times have done
+    uint8_t      CSMA_TIMES;                  //CTL_REG_115, 0x73, csma, set maximum times
+    uint8_t      CSMA_DONE_TIMES;             //CTL_REG_116, 0x74, csma, times have done
+    uint16_t SLEEP_TIMER_CSMA_M;          //CTL_REG_119[7:5]|CTL_REG_118, 11bits
+    uint8_t      SLEEP_TIMER_CSMA_R;          //CTL_REG_119, 0x77[4:0]
+} WORK_MODE_CFG;
+
+//## RSSI config (in page1)
+typedef struct
+{
+    union
+    {
+        struct
+        {
+            uint8_t   COLL_DET_EN:        1;  //0: disable,        1: enable collision detect;
+            uint8_t   RESV_1:             1;
+            uint8_t   RSSI_UPDATE_SEL:    2;  //0:always update,   1:when PREAM_OK,   2:when SYNC_OK,     3:when PKT_DONE
+            uint8_t   COLL_STEP_SEL:      2;  //0:6dB,             1:10dB,            2:16dB              3:20dB
+            uint8_t   RESV_2:             2;
+        } _BITS;
+        uint8_t RSSI_CFG_REG;                 //RX_RSSI_REG_00, 0x62, page1
+    } FRAME_CFG1_u;
+    uint8_t      RSSI_ABS_TH;                 //RX_RSSI_REG_01, 0x63, page1
+} RSSI_CFG;
+
+
+//## Antenna config (in page0 & page1)
+typedef struct
+{
+    union
+    {
+        struct
+        {
+            uint8_t   ANT_SELECT:         1;  //0: antenna1,                  1: antenna2, for antenna diversity manual mode
+            uint8_t   ANT_DIV_MANU:       1;  //0: auto antenna diversity,    1: manual antenna diversity
+            uint8_t   RESV_6:             6;
+        } _BITS;
+        uint8_t ANT_CFG1_REG;                 // CTL_REG_02, 0x02, page0
+    } ANT_CFG1_u;
+
+    union
+    {
+        struct
+        {
+            uint8_t   ANT_INSTR:          1;  //0: antenna1 was used,         1: antenna2 was used, for indicate which antenna was used in antenna diversity auto mode
+            uint8_t   RESV_7:             6;
+        } _BITS;
+        uint8_t ANT_CFG2_REG;                 // CTL_REG_14, 0x0E, page0
+    } ANT_CFG2_u;
+
+    union
+    {
+        struct
+        {
+            uint8_t   ANT_DIV_EN:         1;  //0: disable,               1: enable antenna diversity
+            uint8_t   ANT_SW_DIS:         1;  //0: enable,                1: disable antenna diversity switch
+            uint8_t   ANT_WAIT_PMB:       2;  //0: RX_PREAM_SIZE x1.5,    1: RX_PREAM_SIZE x2,    2: RX_PREAM_SIZE x2.5,     3: RX_PREAM_SIZE x3
+            uint8_t   RESV_4:             4;
+        } _BITS;
+        uint8_t RX_ANTD_REG;                  //RX_ANTD_REG_00, 0x67, page1
+    } ANT_CFG3_u;
+} ANT_DIV_CFG;
+
+//## CDR Tracing (in page1)
+typedef struct
+{
+    union
+    {
+        struct
+        {
+            uint8_t   CDR_MODE:           2;  //0:tracing,  1:counting,  2:manchester,  3:no_cdr
+            uint8_t   CDR_RANGE_SEL:      2;  //0:+/-6.3%,  1:+/-9.4%,   2:+/-12.5%,    3:+/-15.6%
+            uint8_t   CDR_AVG_SEL:        3;  //0:48/64,    1:32/64      2:24/64        3:16/64,    4:11/64     5:8/64     6:6/64     7:4/64
+            uint8_t   CDR_DET_SEL:        1;  //0:mode0,    1:mode1(recommand)
+        } _BITS;
+        uint8_t CDR_CFG0_REG;                 //RX_CDR_REG_00, 0x44, page1
+    } CDR_CFG0_u;
+    union
+    {
+        struct
+        {
+            uint8_t   RESV_3:             3;  //CDR_BR_TH<18:16>
+            uint8_t   CDR_3RD_EN:         1;  //0:disable,   1:enable
+            uint8_t   CDR_4TH_EN:         1;  //0:disable,   1:enable
+            uint8_t   RESV_3_2:           3;  //0:mode0,     1:mode1(recommend)
+        } _BITS;
+        uint8_t CDR_CFG1_REG;                 //RX_CDR_REG_00, 0x44, page1
+    } CDR_CFG1_u;
+    uint32_t      CDR_BR_TH;                    //RX_CDR_REG_03<18:16> & RX_CDR_REG_02<15:8> & RX_CDR_REG_01<7:0>, page1(0x47,0x45,0x46)
+} CDR_TRACING_CFG;
+
+enum CDR_MODE
+{
+    CDR_SEL_TRACING    = 0,
+    CDR_SEL_COUNTING   = 1,
+    CDR_SEL_MANCHESTER = 2,
+    CDR_SEL_RAW        = 3,
+};
+
+typedef struct
+{
+    INT_SRC_CFG         int_src_en;
+    INT_SRC_FLG         int_src_flag;
+    INT_SRC_CLR         int_src_clear;
+    FIFO_STATUS_FLG     fifo_status_flag;
+    PREAMBLE_CFG        preamble_cfg;
+    SYNC_CFG            sync_cfg;
+    ADDR_CFG            addr_cfg;
+    CRC_CFG             crc_cfg;
+    CODING_FORMAT_CFG   coding_format_cfg;
+    FRAME_CFG           frame_cfg;
+    WI_SUN_CFG          wi_sun_cfg;
+    WORK_MODE_CFG       word_mode_cfg;
+    RSSI_CFG            rssi_cfg;
+    ANT_DIV_CFG         antenna_cfg;
+    CDR_TRACING_CFG     cdr_tracing_cfg;
+} CMT2310A_CFG;
+
+#endif
+
+//******************************************************************************
+//* EOF (not truncated)
+//******************************************************************************
diff --git a/NSPE/WIFI_IOT/bsp/drivers/3_Ebyte_WirelessModule_Drivers/E48xMx/CMT2310A_def.h.orig b/NSPE/WIFI_IOT/bsp/drivers/3_Ebyte_WirelessModule_Drivers/E48xMx/CMT2310A_def.h.orig
new file mode 100755
index 0000000..dbe96ed
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/3_Ebyte_WirelessModule_Drivers/E48xMx/CMT2310A_def.h.orig
@@ -0,0 +1,578 @@
+/*
+ * THE FOLLOWING FIRMWARE IS PROVIDED: (1) "AS IS" WITH NO WARRANTY; AND
+ * (2)TO ENABLE ACCESS TO CODING INFORMATION TO GUIDE AND FACILITATE CUSTOMER.
+ * CONSEQUENTLY, CMOSTEK SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR
+ * CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
+ * OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
+ * CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * Copyright (C) CMOSTEK SZ.
+ */
+
+/*!
+ * @file    CMT2310A_def.h
+ * @brief   CMT2310A transceiver RF chip driver
+ *
+ * @version 1.0
+ * @date    Dec 7 2021
+ * @author  CMOSTEK R&D
+ */
+ 
+
+#ifndef __CMT2310A_DEF_H
+
+	#define __CMT2310A_DEF_H
+	
+	//Exit State
+	#define		EXIT_TO_SLEEP					1
+	#define		EXIT_TO_READY					2
+	#define		EXIT_TO_TFS						3
+	#define		EXIT_TO_TX						4
+	#define		EXIT_TO_RFS						5
+	#define		EXIT_TO_RX						6
+
+	//Prefxi select
+	#define		TX_PREFIX_SEL_0					0
+	#define		TX_PREFIX_SEL_1					1
+	#define		TX_PREFIX_SEL_PREAMBLE			2
+
+	//## interrupt source config
+	typedef union					
+		{
+	 	struct 
+	 		{
+	 		uint8_t  PKT_DONE_EN: 		1;		//pkt_done_en				//bit0
+	 		uint8_t  CRC_PASS_EN: 		1;	 	//crc_pass_en				//bit1
+	 		uint8_t  ADDR_PASS_EN: 		1;		//node_address_pass_en		//bit2
+	 		uint8_t  SYNC_PASS_EN: 		1;		//sync_pass_en				//bit3
+	 		uint8_t  PREAM_PASS_EN: 		1;		//preamble_pass_en			//bit4
+	 		uint8_t  TX_DONE_EN:  		1;		//tx_done_en				//bit5
+	 		uint8_t  RX_TOUT_EN:  		1;		//rx_timeout_en				//bit6	
+	 		uint8_t  SLP_TOUT_EN: 		1;		//sleep_timeout_en			//bit7		
+                                            	
+	 		uint8_t  LD_STOP_EN:	 		1;		//ld_stop_en(PLL lock detect)//bit0
+	 		uint8_t  LBD_STOP_EN:  		1;		//lbd_stop_en				//bit1
+	 		uint8_t  LBD_STAT_EN:  		1;		//lbd_status_en				//bit2	
+	 		uint8_t  PKT_ERR_EN:   		1;		//pkt_err_en				//bit3
+	 		uint8_t  RSSI_COLL_EN: 		1;		//rssi_collision_en			//bit4			
+	 		uint8_t  OP_CMD_FAILED_EN:	1;		//op_cmd_failed_en			//bit5
+	 		uint8_t  RSSI_PJD_EN: 		1;		//rssi_pjd_valid_en			//bit6
+	 		uint8_t  RESV_2_1:   			1;		//reserve, don't used		//bit7
+	 		
+	 		uint8_t  SEQ_MATCH_EN: 		1;		//seq_match_en				//bit0
+	 		uint8_t  NACK_RECV_EN:		1;		//nack_recv_en				//bit1
+	 		uint8_t  TX_RESEND_DONE_EN:	1;		//tx_resend_done_en			//bit2
+	 		uint8_t  ACK_RECV_FAILED_EN:	1;		//ack_recv_failed_en		//bit3
+	 		uint8_t  TX_DC_DONE_EN:		1;		//tx_dc_done_en				//bit4
+	 		uint8_t  CSMA_DONE_EN: 		1;		//csma_max_en				//bit5
+	 		uint8_t  CCA_STAT_EN: 		1;		//cca_status_en				//bit6
+	 		uint8_t  API_DONE_EN:	 		1;		//api_done_en				//bit7
+	 		
+	 		uint8_t  TX_FIFO_TH_EN:		1;		//tx_fifo_threshold_en		//bit0
+	 		uint8_t  TX_FIFO_NMTY_EN:		1;		//tx_fifo_non_empty_en		//bit1
+	 		uint8_t  TX_FIFO_FULL_EN:		1;		//tx_fifo_full_en 			//bit2
+	 		uint8_t  RX_FIFO_OVF_EN:		1;		//rx_fifo_overflow_en		//bit3
+	 		uint8_t  RESV_4_1:			1;		//reserve, don't used		//bit4
+	 		uint8_t  RX_FIFO_TH_EN:		1;		//rx_fifo_threshold_en		//bit5
+	 		uint8_t  RX_FIFO_NMTY_EN:		1;		//rx_fifo_non_empty_en		//bit6
+	 		uint8_t  RX_FIFO_FULL_EN:		1;		//rx_fifo_full_en  			//bit7
+	 		}_BITS;
+	 	struct
+	 		{
+		 	uint8_t INT_CTL1_REG;					//CTL_REG_18, 0x12
+		 	uint8_t INT_CTL2_REG;					//CTL_REG_21, 0x15
+	 		uint8_t INT_CTL3_REG;					//CTL_REG_23, 0x17
+	 		uint8_t INT_CTL4_REG;					//CTL_REG_14, 0x0E
+	 		}_BYTE;
+		}INT_SRC_CFG;
+
+	//## interrupt flag
+	typedef union
+		{
+	 	struct 
+	 		{
+	 		uint8_t  RESV_3:   			3;		//reserve, don't used		//bit0/1/2						
+	 		uint8_t  TX_DONE_FLG: 		1;	 	//tx_done_flag				//bit3
+	 		uint8_t  RX_TMO_FLG: 			1;		//rx_timer_timeout_flag		//bit4
+	 		uint8_t  SLEEP_TMO_FLG: 		1;		//sleep_timer_timeout_flag	//bit5
+	 		uint8_t  RESV_2:   			2;		//reserve, don't used		//bit6/7			
+        
+	 		uint8_t  PKT_DONE_FLG:		1;		//pkt_done_flag				//bit0
+	 		uint8_t  CRC_PASS_FLG: 		1;		//crc_pass_flag				//bit1
+	 		uint8_t  ADDR_PASS_FLG:		1;		//addr_pass_flag			//bit2
+	 		uint8_t  SYNC_PASS_FLG: 		1;		//sync_pass_flag			//bit3
+	 		uint8_t  PREAM_PASS_FLG:		1;		//preamble_pass_flag		//bit4
+	 		uint8_t  SYNC1_PASS_FLG:		1;		//sync1_pass_flag			//bit5
+	 		uint8_t  RESV_2_2: 			2;		//reserve, don't used		//bit6/7					
+        
+			uint8_t  LBD_STATUS_FLG:		1;		//lbd_status_flag			//bit0
+			uint8_t  PKT_ERR_FLG:			1;		//pkt_err_flag				//bit1
+			uint8_t  RSSI_COLL_FLG:		1;		//rssi_collision_flag		//bit2
+			uint8_t  OP_CMD_FAILED_FLG:	1;		//op_cmd_failed_flag		//bit3
+			uint8_t  ANT_LOCK_FLG:		1;		//ant_lock_flag				//bit4
+			uint8_t  RESV_3_3:  	 		3;		//reserve, don't used		//bit5/6/7					
+				
+			uint8_t  SEQ_MATCH_FLG:		1;		//seq_match_flag			//bit0
+			uint8_t  NACK_RECV_FLG:		1;		//nack_recv_flag			//bit1
+			uint8_t  TX_RESEND_DONE_FLG:	1;		//tx_resend_max_flag		//bit2	
+			uint8_t  ACK_RECV_FAILED_FLG:	1;		//ack_recv_failed_flag		//bit3
+			uint8_t  TX_DC_DONE_FLG:		1;		//tx_dc_done_flag			//bit4
+			uint8_t  CSMA_DONE_FLG:		1;		//csma_done_flag			//bit5
+			uint8_t  CCA_STATUS_FLG:		1;		//cca_status_flag			//bit6	
+			uint8_t  API_DONE_FLG: 		1;		//api_done_flag				//bit7
+	 		}_BITS;
+	 	struct
+	 		{
+	 		uint8_t INT_FLAG1_REG;				//CTL_REG_24, 0x18
+	 		uint8_t INT_FLAG2_REG;				//CTL_REG_26, 0x1A
+	 		uint8_t INT_FLAG3_REG;				//CTL_REG_30, 0x1E
+			uint8_t INT_FLAG4_REG;				//CTL_REG_32, 0x20
+			}_BYTE;
+		}INT_SRC_FLG;
+
+	//## interrupt clear
+	typedef union 					
+		{
+	 	struct 
+	 		{
+			uint8_t  TX_DONE_CLR: 		1;		//tx_done_clr					//bit0
+	 		uint8_t  RX_TMO_CLR: 			1;		//rx_timer_timeout_clr			//bit1
+			uint8_t  SLEEP_TMO_CLR:		1;		//sleep_timer_timeout_clr		//bit2
+	 		uint8_t  RESV_5:    			5;		//reserve, don't used			//bit3-7
+
+	 		uint8_t  PKT_DONE_CLR:		1;		//pkt_done_clr            		//bit0  
+	 		uint8_t  CRC_PASS_CLR:		1;		//crc_pass_clr                  //bit1  
+	 		uint8_t  ADDR_PASS_CLR:		1;		//addr_pass_clr                 //bit2  
+	 		uint8_t  SYNC_PASS_CLR:		1;		//sync_pass_clr                 //bit3
+	 		uint8_t  PREAM_PASS_CLR:		1;		//preamble_pass_clr				//bit4
+	 		uint8_t  RESV_3: 				3;		//reserve, don't used			//bit5/6/7
+
+			uint8_t  LBD_STAT_CLR:		1;		//lbd_status_clr                //bit0
+			uint8_t  PKT_ERR_CLR: 		1;		//packet_err_clr                //bit1
+			uint8_t  RSSI_COLL_CLR:		1;		//rssi_collision_clr            //bit2
+			uint8_t  OP_CMD_FAILED_CLR:	1;		//op_cmd_failed_clr             //bit3
+			uint8_t  ANT_LOCK_CLR:	 	1;		//antenna_lock_clr              //bit4
+			uint8_t  RESV_2_3:   			3;		//reserve, don't used			//bit5/6/7
+				
+			uint8_t  SEQ_MATCH_CLR: 		1;		//seq_match_clr                	//bit0
+			uint8_t  NACK_RECV_CLR:		1;		//nack_recv_clr                 //bit1
+			uint8_t  TX_RESEND_DONE_CLR:  1;		//tx_resend_done_clr            //bit2
+			uint8_t  ACK_RECV_FAILED_CLR: 1;		//ack_recv_failed_clr           //bit3
+			uint8_t  TX_DC_DONE_CLR:		1;		//tx_dc_done_clr                //bit4
+			uint8_t  CSMA_DONE_CLR: 		1;		//csma_done_clr					//bit5
+			uint8_t  CCA_STATUS_CLR:		1;		//cca_status_clr                //bit6
+			uint8_t  API_DONE_CLR: 		1;		//api_done_clr                  //bit7
+	 		}_BITS;
+		struct
+			{
+	 		uint8_t INT_CLR1_REG;					//CTL_REG_24, 0x18
+	 		uint8_t INT_CLR2_REG;					//CTL_REG_25, 0x19
+	 		uint8_t INT_CLR3_REG;					//CTL_REG_29, 0x1D
+			uint8_t INT_CLR4_REG;					//CTL_REG_31, 0x1F
+			}_BYTE;					
+		}INT_SRC_CLR;
+
+	//## fifo status flag
+	typedef union 					
+		{
+	 	struct 
+	 		{
+	 		uint8_t  TX_FIFO_TH_FLG:  	1;	 	//tx_fifo_threshold_flag		//bit0
+	 		uint8_t  TX_FIFO_NMTY_FLG: 	1;		//tx_fifo_non_empty_flag		//bit1
+	 		uint8_t  TX_FIFO_FULL_FLG:  	1;		//tx_fifo_full_flag				//bit2	
+			uint8_t  RX_FIFO_OVF_FLG:		1;		//rx_fifo_overflow_flag			//bit3
+	 		uint8_t  RESV_1:    			1;		//reserve, don't used			//bit4
+	 		uint8_t  RX_FIFO_TH_FLG:  	1;		//rx_fifo_threshold_flag		//bit5
+	 		uint8_t  RX_FIFO_NMTY_FLG: 	1;		//rx_fifo_non_empty_flag		//bit6
+	 		uint8_t  RX_FIFO_FULL_FLG:   	1;		//rx_fifo_full_flag				//bit7
+	 		}_BITS;
+	 	uint8_t FIFO_FLG_REG;						//CTL_REG_28, 0x1c
+		}FIFO_STATUS_FLG;
+
+
+	//## packet preamble config
+	typedef struct										//Packet Preamble 
+		{
+		uint8_t PREAM_LENG_UNIT;					//0=preamble unit as 8bits,   !0=preamble unit as 4bits (nibble mode)
+		uint8_t PREAM_VALUE;						//preamble value
+	   	uint8_t RX_PREAM_SIZE;					//rx preamble length, range: 0-31, 0==disable rx preamble detect
+	    uint16_t TX_PREAM_SIZE;				//tx preamble length					//## note: for arm mcu uint16_t is 16bits
+		}PREAMBLE_CFG;
+
+	//## packet syncword config		
+	typedef struct
+		{
+		union
+			{
+	 		struct 
+	 			{
+	 			uint8_t  SYNC_MAN_EN: 	1;	 	//sync word manchester coding enable
+	 			uint8_t  SYNC_SIZE: 		3;		// n+1 bytes
+	 			uint8_t  SYNC_TOL:   	 	3;		// n bits tolerence error 
+	 			uint8_t  SYNC_MODE_SEL:	1;		// 0: compatible S2LP;  1: compatible 802.15.4
+	 			}_BITS;
+	 		uint8_t SYNC_CFG_REG;					//CTL_REG_44, 0x2c		
+			}SYN_CFG_u;
+		uint8_t SYNC_VALUE[8];					//CTL_REG_45-CTL_REG_53, 0x2D-0x34
+		uint8_t SYNC_FEC_VALUE[8];				//CTL_REG_53-CTL_REG_60, 0x35-0x3C
+		uint8_t SYNC_VALUE_SEL;					// 0: select SYN_VAL;  !0: select SYN_FEC_VAL
+		}SYNC_CFG;
+
+	//## packet node address config
+	typedef struct
+		{
+		union
+			{	
+	 		struct 
+	 			{
+	 			uint8_t  ADDR_DET_MODE: 	2;	 	//node address mode: 0,disable;  1,only match;  2,add all 0;  3,add all 1 & 0
+	 			uint8_t  ADDR_SIZE: 	 	2;		// n+1 bytes
+	 			uint8_t  ADDR_ERR_MASK: 	1;		// 0: trigger PKT_ERR flag, when node address not match, and reset decode;   1: non-reset decode, when node address not match
+	 			uint8_t  ADDR_FREE_EN: 	1;		// 0: disable;   1: enable node address match as stand-alone working
+	 			uint8_t  ADDR_SPLIT_MODE:	1;		// 0: disable, dest_addr==node_addr;    1: enable, node_addr==src_addr+des_addr
+	 			uint8_t  RESV_1:       	1;
+	 			}_BITS;
+			uint8_t ADDR_CFG_REG;					//CTL_REG_64, 0x40
+			}ADDR_CFG_u;
+		uint8_t SRC_ADDR[2];						//CTL_REG_65, CTL_REG_66
+		uint8_t DEST_ADDR[2];						//CTL_REG_67, CTL_REG_68
+		uint8_t SRC_BITMASK[2];					//CTL_REG_69, CTL_REG_70
+		uint8_t DEST_BITMASK[2];					//CTL_REG_71, CTL_REG_72
+		}ADDR_CFG;
+
+	//## packet crc config
+	typedef struct
+		{
+		union
+			{	
+			struct
+				{
+				uint8_t  CRC_EN:		  		1;	// 0:disable CRC;                       1:enable CRC
+				uint8_t  CRC_BIT_ORDER:		1;	// 0:crc result MSB output first;  		1:crc result LSB output first; 		active unit is byte
+				uint8_t  CRC_REFIN: 			1;	// 0:normal input;                  	1:inverse input;
+				uint8_t  CRC_RANGE:   		1;	// 0:whole payload;                 	1:only data
+				uint8_t  CRC_BIT_INV:  		1;	// 0:crc result non-invert;	    		1:crc result all bits invert
+				uint8_t  CRC_BYTE_SWAP:		1;	// 0:crc result HighByte output first;  1:crc result LowByte output first
+				uint8_t  CRC_SIZE:     		2;	// 0:crc8;  1:crc16;  2:crc24;  3:crc32
+				uint8_t  CRC_REFOUT:			1;	// 0:result whole bit MSB->LSB   		1:result whole bit LSB->MSB 
+				uint8_t  CRCERR_CLR_FIFO_EN: 	1;	// 0:disable                            1:enable when crc error, clear fifo function
+				uint8_t  RESV_6:       		6;		
+				}_BITS;
+			uint16_t CRC_CFG_REG;				//CTL_REG_73, 0x49 & CTL_REG_82[7] & CTL_REG_84[7] 
+			}CRC_CFG_u;
+		union											//CTL_REG_74-CTL_REG_77, 0x4A-0x4D			//## note: for arm mcu uint32_t is 32bits
+			{
+			uint8_t u8_SEED[4];
+			uint32_t  u32_SEED;	
+			}CRC_SEED_u;	
+		union											//CTL_REG_78-CTL_REG_81, 0x4E-0x51			//## note: for arm mcu uint32_t is 32bits
+			{
+			uint8_t u8_POLY[4];
+			uint32_t  u32_POLY;						
+			}CRC_POLY_u;	
+		}CRC_CFG;
+
+	//## packet encode/decode format config
+	typedef struct
+		{
+		union
+			{
+			struct
+				{
+				uint8_t 	MANCH_EN:			1;	// 0:disable manchester coding;			1:enable manchester coding
+				uint8_t   MANCH_TYPE: 		1;	// 0: 2'b01=1, 2'b10=0;					1: 2'b01=0, 2'b10=1
+				uint8_t   WHITEN_EN:			1;	// 0:disable whiten coding; 			1:enable whiten coding	
+				uint8_t	WHITEN_TYPE:		2;	// 0:PN9-CCITT,  1:PN9-IBM,   2:PN7,    3:NA
+				uint8_t   WHITEN_SEED_TYP: 	1;	// 0:compatible A7139;					1:customer seed;    	  note: when select PN7 active
+				uint8_t   RESV_2:  		  	2;
+				uint8_t 	FEC_EN:				1;	// 0:disable FEC Coding;				1:enable FEC Coding
+				uint8_t 	FEC_RSC_NRNSC_SEL:	1;	// 0:RSC Mode;							1:NRNSC Mode
+				uint8_t 	RESV_5:			 	5;
+				uint8_t 	FEC_TICC:			1;	// 0:ui invert ouput in FEC calucate;	1:ui non-invert ouput in FEC calucate
+				}_BITS;
+			uint16_t CODING_CFG_REG;			// CTL_REG_82, 0x52 & CTL_REG_93, 0x5D
+			}CODING_FORMAT_CFG_u;	
+		uint16_t WHITEN_SEED;					// CTL_REG_83, 0x53 & CTL_REG_82[6]
+		uint16_t FEC_PAD_CODE;				// CTL_REG_94, 0x5E & CTL_REG_93[6:2], 0x5D 
+		}CODING_FORMAT_CFG;
+	
+	//## frame struct config
+	typedef struct
+		{
+		uint8_t DATA_MODE;						//0: direct mode;   		2: packet mode;  	 1&3: na	
+		union
+			{
+			struct
+				{
+				uint8_t 	PKT_TYPE:			1;	//0: fixed length;			1: variable length
+				uint8_t  	PAYLOAD_BIT_ORDER:	1;	//0: MSB output first;		1: LSB output first
+				uint8_t   ADDR_LEN_CONF:  	1;	//0: node_addr+length;		1: length+node_addr
+				uint8_t 	ADDR_FIELD_EN:		1;	//0: disable;   			1: enable address field
+				uint8_t 	PAGGYBACKING_EN:	1;	//0: disable 				1: enable
+				uint8_t 	LENGTH_SIZE:		1;	//0: length range 1 byte;   1: length range 2 bytes
+				uint8_t 	RESV_1_2:			1;		
+				uint8_t  	INTERLEAVE_EN:		1;	//0: disable interleave		1: enable interleave	
+				}_BITS;
+			uint8_t FRAME_CFG1_REG;				//CTL_REG_63, 0x3F
+			}FRAME_CFG1_u;
+		union
+			{
+			struct
+				{
+				uint8_t	TX_PREFIX_TYPE:		2;	//0:transmit_0;  	1:transmit_1; 		2:transmit_preamble		3:NA
+				uint8_t	SEQNUM_EN:			1;	//0:disable;		1:enable;     note: SEQ_NUM is the same with FCS1 
+				uint8_t 	SEQNUM_AUTO_INC:	1; 	//0:disable SEQNUM increase;	1:enable 
+				uint8_t	SEQNUM_SIZE:		1;	//0:1byte for SEQNUM;			1:2bytes for SEQNUM
+				uint8_t	SEQNUM_MACH_EN:		1;	//0:disable;					1:enable compare with local SEQNUM, when TX_ACK enable
+				uint8_t	FCS2_EN:			1;	//0:not include FCS2 filed;		1:include FCS2 filed
+				uint8_t 	RESV_1:				1;	
+				}_BITS;
+			uint8_t FRAME_CFG2_REG;				//CTL_REG_84, 0x54
+			}FRAME_CFG2_u;
+		
+		uint16_t TX_PKT_NUM;					//CTL_REG_85, 0x55[7:0] & CTL_REG_86, 0x56[15:8]
+		uint16_t SEQNUM_TX_IN;				//CTL_REG_88/87, 0x58[15:8], 0x57[7:0]		
+		uint16_t SEQNUM_TX_CURRENT_OUT;		//CTL_REG_39/38, 0x27[15:8]/0x26[7:0]
+		uint8_t 	   TX_PKT_GAP;					//CTL_REG_89, 0x59
+		uint8_t 	   FCS2_TX_IN;					//CTL_REG_91, 0x5B
+		uint8_t 	   FCS2_RX_OUT;					//CTL_REG_92, 0x5C
+		uint16_t PAYLOAD_LENGTH;				//CTL_REG_62/61, 0x3E[15:8], 0x3D[7:0]
+		}FRAME_CFG;
+
+	//## Wi-SUN V1.0 packet format compatible
+	typedef union 					
+		{
+	 	struct 
+	 		{
+	 		uint8_t  WISUN_DW:  			1;	 	// 0:not whiten, 						1: whiten
+	 		uint8_t  WISUN_FCS: 			1;		// 0:CRC-32 for PSDU,   				1: CRC-16 for PSDU
+	 		uint8_t  RESV_2:  			2;		// 
+			uint8_t  WISUN_MS:			1;		// default for 0
+	 		uint8_t  WHITEN_WISUN:  		1;		// 0: for normal used, 					1: for Wi-SUN whitenning
+	 		uint8_t  WISUN_ALLIN:  		1;		// 0: WISUN_FCS & WISUN_DW not active, 	1: FCS & DW depend on WISUN_FCS & WISUN_DW, 
+	 		uint8_t  LENGTH_MODE: 		1;		// 0: for normal used, 					1: for Wi-SUN used, PSDU length filed is 11bits
+	 		}_BITS;
+	 	uint8_t WI_SUN_REG;						//CTL_REG_111, 0x6F
+		}WI_SUN_CFG;	
+	
+	//## working mode
+	typedef struct		
+		{
+		union											
+			{
+			struct
+				{
+				uint8_t	TX_DC_EN:			1;	//0:disable TxDutyCycle;	1:enable
+				uint8_t	TX_DC_PERSIST_EN:	1;	//0:run TX_DC_TIMES;		1:always run until this bit set 0
+				uint8_t 	TX_ACK_EN:			1;	//0:disable					1:enable
+				uint8_t	TX_AUTO_HOP_EN:		1;	//0:disable 				1:enable tx frequency auto hopping
+				uint8_t	TX_EXIT_STATE: 		3;	//1:Sleep, 2:Ready, 3:TFS, 4:TX, 5:RFS, 6:RX, other Sleep
+				uint8_t	RESV:				1;
+				}_BITS;
+			uint8_t WORK_MODE_CFG1_REG;			//CTL_REG_96, 0x60
+			}WORK_MODE_CFG1_u;			
+
+		union
+			{
+			struct
+				{
+				uint8_t	RX_DC_EN:			1;	//0:disable RxDutyCycle;	1:enable
+				uint8_t	RX_AUTO_HOP_EN:		1;	//0:disable RxAutoHop;		1:enable
+				uint8_t 	RX_ACK_EN:			1;	//0:disable					1:enable
+				uint8_t	RX_TIMER_EN:		1;	//0:disable					1:enable
+				uint8_t	RX_EXIT_STATE: 		3;	//1:Sleep, 2:Ready, 3:TFS, 4:TX, 5:RFS, 6:RX, other Sleep
+				uint8_t	CSMA_EN:			1;	//0:disable					1:enable
+				}_BITS;			
+			uint8_t WORK_MODE_CFG2_REG;			//CTL_REG_97, 0x61
+			}WORK_MODE_CFG2_u;	
+	
+		union
+			{
+			struct
+				{
+				uint8_t	SLP_MODE:			4;	//14 items for select 
+				uint8_t	RX_HOP_SLP_MODE:	3;	//7 items for select 
+				uint8_t 	PKT_DONE_EXIT_EN: 	1;	//0:keep on current state;		1:depends on RX_EXIT_STATE
+				}_BITS;			
+			uint8_t WORK_MODE_CFG3_REG;			//CTL_REG_98, 0x62
+			}WORK_MODE_CFG3_u;			
+
+		union
+			{
+			struct
+				{
+				uint8_t	LFCLK_OUT_EN:		1;	//0:disable;	1:enable LFCLK output to GPIO4
+				uint8_t	LFCLK_SEL:			1;	//0:LFOSC;		1:LFXO (32768Hz)
+				uint8_t 	RESV_1: 			1;	//
+				uint8_t 	SLEEP_TIMER_EN:		1;	//0:disable		1:enable
+				uint8_t	TIMER_RAND_MODE:	2;	//00:random R,   01:random M,   10:both M&R random,   11:depends on config value
+				uint8_t 	RESV_2: 			2;	
+				}_BITS;			
+			uint8_t WORK_MODE_CFG4_REG;			//CTL_REG_105, 0x69
+			}WORK_MODE_CFG4_u;			
+
+		union
+			{
+			struct
+				{
+				uint8_t	CSMA_CCA_WIN_SEL:	2;	//00:32symbol,  01:64symbol,  10:128symbol,   11:256symbol
+				uint8_t   CSMA_CCA_INT_SEL:	2;	//00:PJD, 		01:RSSI,   	  10:PJD & RSSI,  11:NA
+				uint8_t 	CSMA_PERSIST_EN:	1;	//0:auto exit when reach max & channel still busy, 	1:keep on work until send out  
+				uint8_t 	CSMA_CCA_MODE:		3;	//000:idle,     001:>=1 RSSI,          010:>=1 PJD,          011:>=1 RSSI or PJD,   
+														//100:>=1 SYNC, 101:>=1 SYNC or RSSI,  110:>=1 SYNC or PJD,  111:>=1 SYNC or PJD or RSSI
+				}_BITS;			
+			uint8_t WORK_MODE_CFG5_REG;			//CTL_REG_106, 0x6A
+			}WORK_MODE_CFG5_u;			
+
+		union
+			{
+			struct
+				{
+				uint8_t	RESV_5:             5;
+				uint8_t   FREQ_SW_STATE:      1;	//0:switch to RFS/TFS, and then to the next channel;   1:switch to RDY, and then to the next channel;
+				uint8_t 	RX_HOP_PERSIST:     1;	//0:depend on TX/RX_EXIT_STATE, 					   1:go on next cycle from 0 label
+				uint8_t 	FREQ_HOP_MANU_EN: 	1;	//0:auto hopping mode;  1:hopping by manual
+				
+				}_BITS;
+			uint8_t WORK_MODE_CFG6_REG;
+			}WORK_MODE_CFG6_u;							//CTL_REG_22, 0x16
+			
+		uint8_t 	   FREQ_CHANL_NANU;				//CTL_REG_3,  0x03, frequency hopping by manual, set channel number
+		uint8_t 	   FREQ_DONE_TIMES;				//CTL_REG_11, 0x0B, auto frequency hopping times have done
+		uint8_t      FREQ_SPACE;					//CTL_REG_12, 0x0C, auto frequency channel interval
+		uint8_t      FREQ_TIMES;					//CTL_REG_13, 0x0D, auto frequency hopping set range, 1-64
+		
+		uint16_t SLEEP_TIMER_M;				//CTL_REG_100[7:5]|CLT_REG_99, 11bits, 0x64,0x63
+		uint8_t	   SLEEP_TIMER_R;				//CTL_REG_100[4:0], 0x64
+		uint16_t RX_TIMER_T1_M;				//CTL_REG_102[7:5]|CLT_REG_101, 11bits, 0x66, 0x65
+		uint8_t	   RX_TIMER_T1_R;				//CTL_REG_102[4:0], 0x66	
+		uint16_t RX_TIMER_T2_M;				//CTL_REG_104[7:5]|CLT_REG_103, 11bits, 0x68, 0x67
+		uint8_t	   RX_TIMER_T2_R;				//CTL_REG_104[4:0], 0x68			
+		uint16_t RX_TIMER_CSMA_M;				//CTL_REG_108[7:5]|CLT_REG_107, 11bits, 0x6C,0x6B
+		uint8_t	   RX_TIMER_CSMA_R;				//CTL_REG_108[4:0], 0x6C
+		uint8_t	   TX_DC_TIMES;					//CTL_REG_110, 0x6E, tx duty cycle, set maximum times
+		uint8_t	   TX_DC_DONE_TIMES;			//CTL_REG_112, 0x70, tx duty cycle, times have done
+		uint8_t	   TX_RS_TIMES;					//CTL_REG_113, 0x71, tx ack mode, set maximum times
+		uint8_t  	   TX_RS_DONE_TIMES;			//CLT_REG_114, 0x72, tx ack mode, times have done 
+		uint8_t	   CSMA_TIMES;					//CTL_REG_115, 0x73, csma, set maximum times
+		uint8_t 	   CSMA_DONE_TIMES;				//CTL_REG_116, 0x74, csma, times have done
+		uint16_t SLEEP_TIMER_CSMA_M;			//CTL_REG_119[7:5]|CTL_REG_118, 11bits
+		uint8_t	   SLEEP_TIMER_CSMA_R;			//CTL_REG_119, 0x77[4:0]
+		}WORK_MODE_CFG;		
+		
+	//## RSSI config (in page1)
+	typedef struct
+		{
+		union
+			{
+			struct
+				{
+				uint8_t 	COLL_DET_EN:		1;	//0: disable, 		 1: enable collision detect;			
+				uint8_t  	RESV_1:				1;	
+				uint8_t   RSSI_UPDATE_SEL:  	2;	//0:always update,   1:when PREAM_OK,   2:when SYNC_OK,     3:when PKT_DONE
+				uint8_t 	COLL_STEP_SEL:		2;	//0:6dB, 			 1:10dB,  			2:16dB			 	3:20dB		
+				uint8_t 	RESV_2:				2;		
+				}_BITS;
+			uint8_t RSSI_CFG_REG;					//RX_RSSI_REG_00, 0x62, page1
+			}FRAME_CFG1_u;
+		uint8_t 	   RSSI_ABS_TH;					//RX_RSSI_REG_01, 0x63, page1
+		}RSSI_CFG;
+
+
+	//## Antenna config (in page0 & page1)	
+	typedef struct
+		{
+		union
+			{
+			struct
+				{
+				uint8_t 	ANT_SELECT:			1;	//0: antenna1, 					1: antenna2, for antenna diversity manual mode
+				uint8_t  	ANT_DIV_MANU:		1;	//0: auto antenna diversity, 	1: manual antenna diversity
+				uint8_t 	RESV_6:				6;		
+				}_BITS;
+			uint8_t ANT_CFG1_REG;					// CTL_REG_02, 0x02, page0
+			}ANT_CFG1_u;
+
+		union
+			{
+			struct
+				{
+				uint8_t 	ANT_INSTR:			1;	//0: antenna1 was used, 		1: antenna2 was used, for indicate which antenna was used in antenna diversity auto mode
+				uint8_t 	RESV_7:				6;		
+				}_BITS;
+			uint8_t ANT_CFG2_REG;					// CTL_REG_14, 0x0E, page0
+			}ANT_CFG2_u;
+
+		union
+			{
+			struct
+				{
+				uint8_t 	ANT_DIV_EN:			1;	//0: disable, 				1: enable antenna diversity
+				uint8_t  	ANT_SW_DIS:			1;	//0: enable,				1: disable antenna diversity switch 
+				uint8_t   ANT_WAIT_PMB:  		2;	//0: RX_PREAM_SIZE x1.5,    1: RX_PREAM_SIZE x2,    2: RX_PREAM_SIZE x2.5,     3: RX_PREAM_SIZE x3
+				uint8_t 	RESV_4:				4;		
+				}_BITS;
+			uint8_t RX_ANTD_REG;					//RX_ANTD_REG_00, 0x67, page1
+			}ANT_CFG3_u;
+		}ANT_DIV_CFG;	
+
+	//## CDR Tracing (in page1)
+	typedef struct
+		{
+		union
+			{
+			struct
+				{
+				uint8_t 	CDR_MODE:			2;	//0:tracing,  1:counting,  2:manchester,  3:no_cdr
+				uint8_t  	CDR_RANGE_SEL:		2;	//0:+/-6.3%,  1:+/-9.4%,   2:+/-12.5%,    3:+/-15.6%
+				uint8_t   CDR_AVG_SEL:  		3;	//0:48/64,    1:32/64      2:24/64        3:16/64,    4:11/64     5:8/64     6:6/64     7:4/64
+				uint8_t 	CDR_DET_SEL:		1;	//0:mode0,    1:mode1(recommand)	
+				}_BITS;
+			uint8_t CDR_CFG0_REG;					//RX_CDR_REG_00, 0x44, page1
+			}CDR_CFG0_u;
+		union
+			{
+			struct
+				{
+				uint8_t 	RESV_3:				3;	//CDR_BR_TH<18:16>
+				uint8_t  	CDR_3RD_EN:			1;	//0:disable,   1:enable
+				uint8_t   CDR_4TH_EN:  		1;	//0:disable,   1:enable
+				uint8_t 	RESV_3_2:			3;	//0:mode0,     1:mode1(recommend)	
+				}_BITS;
+			uint8_t CDR_CFG1_REG;					//RX_CDR_REG_00, 0x44, page1
+			}CDR_CFG1_u;
+		uint32_t 	  CDR_BR_TH;					//RX_CDR_REG_03<18:16> & RX_CDR_REG_02<15:8> & RX_CDR_REG_01<7:0>, page1(0x47,0x45,0x46)
+		}CDR_TRACING_CFG;
+		
+	enum CDR_MODE
+		{
+		CDR_SEL_TRACING    = 0,
+		CDR_SEL_COUNTING   = 1, 
+		CDR_SEL_MANCHESTER = 2,
+		CDR_SEL_RAW        = 3,
+		};
+	
+	typedef struct
+		{
+		INT_SRC_CFG 		int_src_en;
+		INT_SRC_FLG			int_src_flag;
+		INT_SRC_CLR   		int_src_clear;
+		FIFO_STATUS_FLG		fifo_status_flag;
+		PREAMBLE_CFG		preamble_cfg;
+		SYNC_CFG			sync_cfg;
+		ADDR_CFG			addr_cfg;
+		CRC_CFG				crc_cfg;
+		CODING_FORMAT_CFG	coding_format_cfg;
+		FRAME_CFG			frame_cfg;
+		WI_SUN_CFG			wi_sun_cfg;
+		WORK_MODE_CFG		word_mode_cfg;	
+		RSSI_CFG			rssi_cfg;
+		ANT_DIV_CFG			antenna_cfg;
+		CDR_TRACING_CFG		cdr_tracing_cfg;	
+		}CMT2310A_CFG;
+	
+#endif
+
+//******************************************************************************
+//* EOF (not truncated)
+//******************************************************************************
diff --git a/NSPE/WIFI_IOT/bsp/drivers/3_Ebyte_WirelessModule_Drivers/E48xMx/CMT2310A_reg.h b/NSPE/WIFI_IOT/bsp/drivers/3_Ebyte_WirelessModule_Drivers/E48xMx/CMT2310A_reg.h
new file mode 100755
index 0000000..88385b1
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/3_Ebyte_WirelessModule_Drivers/E48xMx/CMT2310A_reg.h
@@ -0,0 +1,1229 @@
+/*
+ * THE FOLLOWING FIRMWARE IS PROVIDED: (1) "AS IS" WITH NO WARRANTY; AND
+ * (2)TO ENABLE ACCESS TO CODING INFORMATION TO GUIDE AND FACILITATE CUSTOMER.
+ * CONSEQUENTLY, CMOSTEK SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR
+ * CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
+ * OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
+ * CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * Copyright (C) CMOSTEK SZ.
+ */
+
+/*!
+ * @file    CMT2310A_reg.h
+ * @brief   CMT2310A transceiver RF chip driver
+ *
+ * @version 1.0
+ * @date    Dec 7 2021
+ * @author  CMOSTEK R&D
+ */
+ 
+
+#ifndef __CMT2310A_REG_H
+
+	#define 	__CMT2310A_REG_H
+
+	#define 		CMT2310A_PAGE0_SIZE         (0x77-0x28+1)
+	#define 		CMT2310A_PAGE1_SIZE         (0xef-0x80+1)
+	#define 		CMT2310A_PAGE2_SIZE         (0x3f-0x00+1)
+
+//---------------------- CUS PAGE0 defines -------------------------------
+//------------------------------------------------------------------------	
+	#define 		CMT2310A_CTL_REG_00         	0x00					// PU_BOOT<7:0>
+		#define		CMT2310A_REBOOT					0x03
+							                    	
+	#define 		CMT2310A_CTL_REG_01         	0x01					// radio chip status switch
+		#define		CMT2310A_GO_SLEEP				(1<<0)					// radio go sleep
+		#define		CMT2310A_GO_READY				(1<<1)					// radio go ready
+		#define		CMT2310A_GO_TX					(1<<2)					// radio go tx
+		#define		CMT2310A_GO_RX					(1<<3)					// radio go rx 
+		#define		CMT2310A_GO_TFS					(1<<4)					// radio go tfs
+		#define		CMT2310A_GO_RFS					(1<<5)					// radio go rfs
+	                                            	
+	#define 		CMT2310A_CTL_REG_02         	0x02					// Antenna Diversity
+		#define		CMT2310A_ANT_DIV_MANU			(1<<1)					// 0=disable antenna diversity,  1=enable antenna diversity
+		#define		CMT2310A_ANT_SELECT				(1<<0)					// 0=select antenna_1,           1=select antenna_2,  when antenna diversity manual active
+	                                            	
+	#define 		CMT2310A_CTL_REG_03         	0x03					// frequencry channel value, by manual set
+	                                            	
+	#define 		CMT2310A_CTL_REG_04         	0x04					// gpio ctrl 0
+		#define		CMT2310A_TX_DIN_EN				(1<<6)					// 0=disable TX_DATA input to GPIO,  1=enable TX_DATA input to GPIO
+                                                	
+		#define		CMT2310A_GPIO1_SEL				(7<<3)					// masker
+		#define		CMT2310A_GPIO1_DCLK				(0<<3)					// gpio1 as DCLK
+		#define		CMT2310A_GPIO1_INT1				(1<<3)					// gpio1 as INT1
+		#define		CMT2310A_GPIO1_INT2				(2<<3)					// gpio1 as INT2
+		#define		CMT2310A_GPIO1_DOUT				(3<<3)					// goio1 as DOUT	
+	                                            	
+		#define		CMT2310A_GPIO0_SEL				(7<<0)					// masker
+		#define		CMT2310A_GPIO0_DOUT				(0<<0)					// gpio0 as DOUT
+		#define		CMT2310A_GPIO0_INT1				(1<<0)					// gpio0 as INT1
+		#define		CMT2310A_GPIO0_INT2				(2<<0)					// gpio0 as INT2
+		#define		CMT2310A_GPIO0_DCLK				(3<<0)					// goio0 as DCLK
+		#define		CMT2310A_GPIO0_INT3				(6<<0)					// gpio0 as INT3
+		                                        	
+	#define 		CMT2310A_CTL_REG_05         	0x05					// gpio ctrl 1
+		#define		CMT2310A_TX_DIN_SEL				(3<<6)					// masker
+		#define		CMT2310A_TX_DIN_GPIO3			(0<<6)					// TX_DIN from GPIO3
+		#define		CMT2310A_TX_DIN_GPIO4			(1<<6)					// TX_DIN from GPIO4
+		#define		CMT2310A_TX_DIN_nIRQ			(2<<6)					// TX_DIN from nIRQ
+	                                            	
+		#define		CMT2310A_GPIO3_SEL				(7<<3)					//masker
+		#define		CMT2310A_GPIO3_INT2				(0<<3)					// gpio3 as INT2
+		#define		CMT2310A_GPIO3_INT1				(1<<3)					// gpio3 as INT1	
+		#define		CMT2310A_GPIO3_DCLK				(2<<3)					// gpio3 as DCLK	
+		#define		CMT2310A_GPIO3_DOUT				(3<<3)					// gpio3 as DOUT
+		#define		CMT2310A_GPIO3_DIN				(5<<3)					// gpio3 as DIN (TX_DIN)
+		                                        	
+		#define		CMT2310A_GPIO2_SEL				(7<<0)					//masker
+		#define		CMT2310A_GPIO2_INT1				(0<<0)					// gpio2 as INT1
+		#define		CMT2310A_GPIO2_INT2				(1<<0)					// gpio2 as INT2
+		#define		CMT2310A_GPIO2_DCLK				(2<<0)					// gpio2 as DCLK
+		#define		CMT2310A_GPIO2_DOUT				(3<<0)					// gpio2 as DOUT
+		#define		CMT2310A_GPIO2_INT3				(6<<0)					// gpio2 as INT3
+			                                            	
+	#define 		CMT2310A_CTL_REG_06         	0x06					// gpio ctrl 2
+		#define		CMT2310A_DIG_CLKOUT_EN			(1<<6)					// 0=bypass,  1=enable digital clock out to GPIO4
+                                                	
+		#define		CMT2310A_GPIO5_SEL				(7<<3)					//masker
+		#define		CMT2310A_GPIO5_nRST				(0<<3)					// gpio5 as nRST
+		#define		CMT2310A_GPIO5_INT1				(1<<3)					// goio5 as INT1
+		#define		CMT2310A_GPIO5_INT2				(2<<3)					// gpio5 as INT2
+		#define		CMT2310A_GPIO5_DOUT				(3<<3)					// gpio5 as DOUT
+		#define		CMT2310A_GPIO5_DCLK				(4<<3)					// gpio5 as DCLK
+		                                        	
+		#define		CMT2310A_GPIO4_SEL				(7<<0)					//masker
+		#define		CMT2310A_GPIO4_DOUT				(0<<0)					// gpio4 as DOUT
+		#define		CMT2310A_GPIO4_INT1				(1<<0)					// gpio4 as INT1
+		#define		CMT2310A_GPIO4_INT2				(2<<0)					// gpio4 as INT2
+		#define		CMT2310A_GPIO4_DCLK				(3<<0)					// gpio4 as DCLK
+		#define		CMT2310A_GPIO4_DIN				(5<<0)					// gpio4 as DIN (TX_DIN)
+		                                        	
+	#define 		CMT2310A_CTL_REG_07        		0x07					// nIRQ select
+		#define		CMT2310A_CTL_REG_07_MASK		(3<<6)
+		#define		CMT2310A_LFXO_PAD_EN			(1<<5)					// 0=disable,       1=enable GPIO2 & GPIO3 as 32.768kHz crystal pin
+		#define		CMT2310A_API_STOP				(1<<4)					// 0=API go on,     1=stop API
+		#define		CMT2310A_SPI_3W_EN				(1<<3)					// 0=select SPI-4,  1=select SPI-3
+		                                        	
+		#define		CMT2310A_nIRQ_SEL				(7<<0)					//masker
+		#define		CMT2310A_nIRQ_INT1				(0<<0)					// nIRQ as INT1
+		#define		CMT2310A_nIRQ_INT2				(1<<0)					// nIRQ as INT2
+		#define		CMT2310A_nIRQ_DCLK				(2<<0)					// nIRQ as DCLK
+		#define		CMT2310A_nIRQ_DOUT				(3<<0)					// nIRQ as DOUT
+		#define		CMT2310A_nIRQ_TCXO				(4<<0)					// nIRQ as TCXO control pin
+		#define		CMT2310A_nIRQ_DIN				(5<<0)					// nIRQ as DIN (TX_DIN)	
+		                                        	
+	#define 		CMT2310A_CTL_REG_08        		0x08					//API Command interface
+		#define		CMT2310A_API_CMD_REG			0x08
+		                                        	
+	#define 		CMT2310A_CTL_REG_09        		0x09
+		#define		CMT2310A_API_CMD_FLAG			(1<<7)					//API Command flag
+		#define		CMT2310A_API_RESP_MASK			0x7F					//API Respond value
+                                                	
+	#define 		CMT2310A_CTL_REG_10         	0x0A					// radio status register 	(-RO)
+		#define		CMT2310A_CHIP_MODE_STA_REG		0x0A					// 	
+		#define		CMT2310A_STATE_IS_IDLE			0x00					// radio is in idle
+		#define		CMT2310A_STATE_IS_SLEEP			0x81					// radio is in sleep
+		#define		CMT2310A_STATE_IS_READY			0x82					// radio is in ready
+		#define		CMT2310A_STATE_IS_RFS			0x84					// radio is in RFS
+		#define		CMT2310A_STATE_IS_TFS			0x88					// radio is in TFS
+		#define		CMT2310A_STATE_IS_RX			0x90					// radio is in RX
+		#define		CMT2310A_STATE_IS_TX			0xA0					// radio is in TX
+	                                            	
+	#define 		CMT2310A_CTL_REG_11         	0x0B					// auto frequencry hopping done times		
+																			// range 0-63
+                                                	
+	#define 		CMT2310A_CTL_REG_12         	0x0C					// auto frequencry hopping channel space	
+		#define		CMT2310A_FREQ_SPACE_REG			0x0C					
+			                                    	
+	#define 		CMT2310A_CTL_REG_13         	0x0D					// auto frequencry hopping times
+		#define		CMT2310A_FREQ_TIMES_REG			0x0D					// range 1-64(n+1)	
+                                                	
+	#define 		CMT2310A_CTL_REG_14         	0x0E					// fifo status interrupt control register 
+		#define		CMT2310A_RX_FIFO_FULL_EN		(1<<7)					// 0=disable,  1=enable rx fifo full interrupt
+		#define		CMT2310A_RX_FIFO_NMTY_EN		(1<<6)					// 0=disable,  1=enable rx fifo non-empty interrupt
+		#define		CMT2310A_RX_FIFO_TH_EN			(1<<5)					// 0=disable,  1=enable rx fifo threshold interrupt
+		#define		CMT2310A_RX_FIFO_OVF_EN			(1<<3)					// 0=disable,  1=enable rx fifo overflow interrupt
+		#define		CMT2310A_TX_FIFO_FULL_EN		(1<<2)					// 0=disable,  1=enable tx fifo full interrupt
+		#define		CMT2310A_TX_FIFO_NMTY_EN		(1<<1)					// 0=disable,  1=enable tx fifo non-empty interrupt
+		#define		CMT2310A_TX_FIFO_TH_EN			(1<<0)					// 0=disable,  1=enable tx fifo threshold interrupt
+		                                        	
+	#define 		CMT2310A_CTL_REG_15         	0x0F					// antenna diversity indicate
+		#define		CMT2310A_ANT_INSTR				(1<<0)					// indicate antenna diversity lock which antenna
+                                                	
+
+	#define 		CMT2310A_CTL_REG_16         	0x10					// interrupt1 selection
+		#define		CMT2310A_INT1_SEL_REG			0x10
+		#define		CMT2310A_INT1_SEL_MASK			0x3F
+
+	#define 		CMT2310A_CTL_REG_17             0x11					// interrupt2 selection	
+		#define		CMT2310A_INT2_SEL_REG			0x11
+		#define		CMT2310A_INT1_POLAR				(1<<7)					// int1 polar selection, 0=high acitve,  1=low acitve;
+		#define		CMT2310A_INT2_POLAR				(1<<6)					// int1 polar selection, 0=high acitve,  1=low acitve;
+		#define		CMT2310A_INT2_SEL_MASK			0x3F
+
+		#define		CMT2310A_INT_MIX				(0<<0)					// all interrupt mixed together
+		#define		CMT2310A_INT_ANT_LOCK			(1<<0)					// antenna locked
+		#define		CMT2310A_INT_RSSI_PJD_VALID		(2<<0)					// rssi and/or pjd valid
+		#define		CMT2310A_INT_PREAM_PASS			(3<<0)					// preamble detected
+		#define		CMT2310A_INT_SYNC_PASS			(4<<0)					// sync word detected
+		#define		CMT2310A_INT_ADDR_PASS			(5<<0)					// node address detected
+		#define		CMT2310A_INT_CRC_PASS			(6<<0)					// crc ok detected 
+		#define		CMT2310A_INT_PKT_OK				(7<<0)					// packet received detected
+		#define		CMT2310A_INT_PKT_DONE			(8<<0)					// packet received detected, even wrong packet or collision
+		#define		CMT2310A_INT_SLEEP_TMO			(9<<0)					// sleep timer time-out
+		#define		CMT2310A_INT_RX_TMO				(10<<0)					// rx timer time-out
+		#define		CMT2310A_INT_RX_FIFO_NMTY		(11<<0)					// rx fifo non-empty
+		#define		CMT2310A_INT_RX_FIFO_TH			(12<<0)					// rx fifo threshold
+		#define		CMT2310A_INT_RX_FIFO_FULL		(13<<0)					// rx fifo full
+		#define		CMT2310A_INT_RX_FIFO_WBYTE		(14<<0)					// rx fifo write byte trigger
+		#define		CMT2310A_INT_RX_FIFO_OVF		(15<<0)					// rx fifo overflow
+		#define		CMT2310A_INT_TX_DONE			(16<<0)					// tx done
+		#define		CMT2310A_INT_TX_FIFO_NMTY		(17<<0)					// tx fifo non-empty
+		#define		CMT2310A_INT_TX_FIFO_TH			(18<<0)					// tx fifo threshold
+		#define		CMT2310A_INT_TX_FIFO_FULL		(19<<0)					// tx fifo full
+		#define		CMT2310A_INT_STATE_IS_READY		(20<<0)					// state is ready
+		#define		CMT2310A_INT_STATE_IS_FS		(21<<0)					// state is FS
+		#define		CMT2310A_INT_STATE_IS_RX		(22<<0)					// state is rx
+		#define		CMT2310A_INT_STATE_IS_TX		(23<<0)					// state is tx
+		#define		CMT2310A_INT_LBD_STATUS			(24<<0)					// LBD status
+		#define		CMT2310A_INT_API_CMD_FAILED		(25<<0)					// API Command failed
+		#define		CMT2310A_INT_API_DONE			(26<<0)					// API execute finish
+		#define		CMT2310A_INT_TX_DC_DONE			(27<<0)					// ??
+		#define		CMT2310A_INT_ACK_RECV_FAILED	(28<<0)					// ack recieve failed
+		#define		CMT2310A_INT_TX_RESEND_DONE		(29<<0)					// tx re-send done
+		#define		CMT2310A_INT_NACK_RECV			(30<<0)					// non-ack received
+		#define		CMT2310A_INT_SEQ_MATCH			(31<<0)					// sequence number match
+		#define		CMT2310A_INT_CSMA_DONE			(32<<0)					// CSMA done
+		#define		CMT2310A_INT_CCA_STATUS			(33<<0)					// CCA status match
+		
+
+	#define 		CMT2310A_CTL_REG_18             0x12					// interrupt enable control 1
+		#define		CMT2310A_INT_CTL1_REG			0x12			
+		#define		CMT2310A_SLEEP_TMO_EN			(1<<7)					// 0=disable, 1=enable sleep timer time-out
+		#define		CMT2310A_RX_TMO_EN				(1<<6)					// 0=disable, 1=enable rx timer time-out
+		#define		CMT2310A_TX_DONE_EN				(1<<5)					// 0=disable, 1=enable tx done 
+		#define		CMT2310A_PREAM_PASS_EN			(1<<4)					// 0=disable, 1=enable preamble detect
+		#define		CMT2310A_SYNC_PASS_EN			(1<<3)					// 0=disable, 1=enable syncword detect
+		#define		CMT2310A_ADDR_PASS_EN			(1<<2)					// 0=disable, 1=enable node address detect
+		#define		CMT2310A_CRC_PASS_EN			(1<<1)					// 0=disable, 1=enable packet crc detect
+		#define		CMT2310A_PKT_DONE_EN			(1<<0)					// 0=disable, 1=enable packet received done
+
+	#define 		CMT2310A_CTL_REG_19             0x13					// interrupt enable control 2
+		#define		CMT2310A_INT3_POLAR				(1<<7)					// int1 polar selection, 0=high acitve,  1=low acitve;		
+		#define		CMT2310A_PD_FIFO				(1<<6)					// 0=retain fifo in sleep,   1=not retain fifo in sleep
+		#define		CMT2310A_FIFO_TH_BIT8			(1<<5)					// fifo threshold bit8
+		#define		CMT2310A_FIFO_AUTO_CLR_RX_EN	(1<<4)					// 0=not clear fifo,  1=clear fifo, when trigger go to rx
+		#define		CMT2310A_FIFO_AUTO_RES_TX_EN	(1<<3)					// 0=auto restore tx fifo,    1=don't auto restore tx fifo, when tx done. (if TX_PKT_NUM is not 0, should be set this bit) 
+		#define		CMT2310A_FIFO_TX_TEST_EN		(1<<2)					// 0=tx fifo only write,      1=tx fifo can be read.  suggest only for testing, normal useage should be clear this bit
+		#define		CMT2310A_FIFO_MERGE_EN			(1<<1)					// 0=split fifo to tx and rx, 1=fifo merge together 
+		#define		CMT2310A_FIFO_TX_RX_SEL			(1<<0)					// 0=fifo for tx useage, 	  1=fifo for rx useage, when CMT2310A_FIFO_MERGE_EN=1
+
+	#define 		CMT2310A_CTL_REG_20             0x14					// fifo threshold value
+		#define		CMT2310A_FIFO_TH_REG			0x14
+	
+	#define 		CMT2310A_CTL_REG_21             0x15					// interrupt enable control 3 
+		#define		CMT2310A_RSSI_PJD_VALID_EN		(1<<6)					// 0=disable, 1=enable RSSI and/or PJD valid interrupt
+		#define		CMT2310A_OP_CMD_FAILED_EN		(1<<5)					// 0=disable, 1=enable API Command failed interrupt		
+		#define		CMT2310A_RSSI_COLL_EN			(1<<4)					// 0=disable, 1=enable signal collision interrupt
+		#define		CMT2310A_PKT_ERR_EN				(1<<3)					// 0=disable, 1=enable packet recieve error interrupt
+		#define		CMT2310A_LBD_STATUS_EN			(1<<2)					// 0=disable, 1=enable LBD status interrupt
+		#define		CMT2310A_LBD_STOP_EN			(1<<1)					// 0=disable, 1=enable LBD stop interrupt
+		#define		CMT2310A_LD_STOP_EN				(1<<0)					// 0=disable, 1=enable PLL lock detect interrupt
+
+	#define 		CMT2310A_CTL_REG_22             0x16					// function enable config 0		
+		#define		CMT2310A_FREQ_HOP_MANU_EN		(1<<7)					// 0=disable, 1=enable manual frequencry hopping
+		#define		CMT2310A_RX_HOP_PERSIST			(1<<6)					// 0=finish,  1=on going, Rx auto frequencry hopping
+		#define		CMT2310A_FREQ_SW_STATE			(1<<5)					// 0=return to READY,  1=return to RFS,  for Rx auto frequencry hopping mode, every times after RX time-out state
+		#define		CMT2310A_TX_DATA_INV			(1<<4)					// 0=don't invert,     1=invert, for TX data input from GPIO
+		#define		CMT2310A_PA_DIFF_SEL			(1<<3)					// 0=single-end PA,    1=differential-end PA,  for CMT2310A need select single-end PA
+		#define		CMT2310A_TRX_SWT_INV			(1<<2)					// 0=don't invert,     1=invert for TX/RX antenna switch
+		#define		CMT2310A_TRX_SWT_EN				(1<<1)					// 0=disable, 1=enable TX/RX antenna switch
+		#define		CMT2310A_ANT_LOCK_EN			(1<<0)					// 0=disable, 1=enable antenna diversity lock interrupt
+
+	#define 		CMT2310A_CTL_REG_23             0x17					// interrupt enable control 4		
+		#define		CMT2310A_API_DONE_EN			(1<<7)					// 0=disable, 1=enable API done interrupt
+		#define		CMT2310A_CCA_STATUS_EN			(1<<6)					// 0=disable, 1=enable CCA status interrupt
+		#define		CMT2310A_CSMA_DONE_EN			(1<<5)					// 0=disable, 1=enable CSMA done interrupt
+		#define		CMT2310A_TX_DC_DONE_EN			(1<<4)					// 0=disable, 1=enable TX DutyCycle done interrupt
+		#define		CMT2310A_ACK_RECV_FAILED_EN		(1<<3)					// 0=disable, 1=enable ACK received failed interrupt
+		#define		CMT2310A_TX_RESEND_DONE_EN		(1<<2)					// 0=disable, 1=enable TX re-send done interrupt
+		#define		CMT2310A_NACK_RECV_EN			(1<<1)					// 0=disable, 1=enable no ACK received interrupt
+		#define		CMT2310A_SEQ_MATCH_EN			(1<<0)					// 0=disable, 1=enable sequence number match interrupt
+	
+	#define 		CMT2310A_CTL_REG_24             0x18					// interrupt flag & clear control 1
+		#define		CMT2310A_SLEEP_TMO_FLG			(1<<5)					// sleep timer time-out flag
+		#define		CMT2310A_RX_TMO_FLG				(1<<4)					// rx timer time-out flag
+		#define		CMT2310A_TX_DONE_FLG			(1<<3)					// tx done flag
+		#define		CMT2310A_SLEEP_TMO_CLR			(1<<2)					// set '1' to clear Sleep timer time-out flag 
+		#define		CMT2310A_RX_TMO_CLR				(1<<1)					// set '1' to clear Rx timer time-out flag
+		#define		CMT2310A_TX_DONE_CLR			(1<<0)					// set '1' to clear TX done flag
+	
+	#define 		CMT2310A_CTL_REG_25             0x19					// interrupt flag & clear control 2
+		#define		CMT2310A_PREAM_PASS_CLR			(1<<4)					// set '1' to clear PREAM_PASS flag
+		#define		CMT2310A_SYNC_PASS_CLR			(1<<3)					// set '1' to clear SYNC_PASS flag
+		#define		CMT2310A_ADDR_PASS_CLR			(1<<2)					// set '1' to clear ADDR_PASS flag
+		#define		CMT2310A_CRC_PASS_CLR			(1<<1)					// set '1' to clear CRC_PASS flag
+		#define		CMT2310A_PKT_DONE_CLR			(1<<0)					// set '1' to clear PKT_DONE flag
+		
+	#define 		CMT2310A_CTL_REG_26             0x1A					// interrupt flag & clear control 3	(-RO)
+		#define		CMT2310A_SYNC1_PASS_FLG			(1<<5)					// sync-word1 match interrupt flag
+		#define		CMT2310A_PREAM_PASS_FLG			(1<<4)					// preamlbe pass interrupt flag
+		#define		CMT2310A_SYNC_PASS_FLG			(1<<3)					// sync-word match interrupt flag
+		#define		CMT2310A_ADDR_PASS_FLG			(1<<2)					// node address match interrupt flag
+		#define		CMT2310A_CRC_PASS_FLG			(1<<1)					// packet crc pass interrupt flag
+		#define		CMT2310A_PKT_DONE_FLG			(1<<0)					// packet done interrupt flag	
+
+	#define 		CMT2310A_CTL_REG_27             0x1B					// fifo control 1, fifo clear
+		#define		CMT2310A_TX_FIFO_RESTORE		(1<<2)					// 0=disable, 1=enable 
+		#define		CMT2310A_RX_FIFO_CLR			(1<<1)					// set '1' to clear Rx FIFO
+		#define		CMT2310A_TX_FIFO_CLR			(1<<0)					// set '1' to clear Tx FIFO
+			
+	#define 		CMT2310A_CTL_REG_28             0x1C					// fifo control 2, fifo flag		(-RO)
+		#define		CMT2310A_RX_FIFO_FULL_FLG		(1<<7)					// 
+		#define		CMT2310A_RX_FIFO_NMTY_FLG		(1<<6)					//
+		#define		CMT2310A_RX_FIFO_TH_FLG			(1<<5)					//
+		#define		CMT2310A_RX_FIFO_OVF_FLG		(1<<3)					//
+		#define		CMT2310A_TX_FIFO_FULL_FLG		(1<<2)					//
+		#define		CMT2310A_TX_FIFO_NMTY_FLG		(1<<1)					//
+		#define		CMT2310A_TX_FIFO_TH_FLG			(1<<0)					//
+		
+	#define 		CMT2310A_CTL_REG_29             0x1D					// auxrl function clear control			
+		#define		CMT2310A_ANT_LOCK_CLR			(1<<4)					// set '1' to clear antenna lock
+		#define		CMT2310A_OP_CMD_FAILED_CLR		(1<<3)					// set '1' to clear command operate failed 
+		#define		CMT2310A_RSSI_COLL_CLR			(1<<2)					// set '1' to clear rssi collision
+		#define		CMT2310A_PKT_ERR_CLR			(1<<1)					// set '1' to clear packet receive error
+		#define		CMT2310A_LBD_STATUS_CLR			(1<<0)					// set '1' to clear LBD status
+
+	#define 		CMT2310A_CTL_REG_30             0x1E					// auxrl function flag				(-RO)
+		#define		CMT2310A_ANT_LOCK_FLG			(1<<4)					//
+		#define		CMT2310A_OP_CMD_FAILED_FLG		(1<<3)					//
+		#define		CMT2310A_RSSI_COLL_FLG			(1<<2)					//
+		#define		CMT2310A_PKT_ERR_FLG			(1<<1)					//
+		#define		CMT2310A_LBD_STATUS_FLG			(1<<0)					//
+
+	#define 		CMT2310A_CTL_REG_31             0x1F					// mac function clear control
+		#define		CMT2310A_API_DONE_CLR			(1<<7)					// set '1' to clear API done
+		#define		CMT2310A_CCA_STATUS_CLR			(1<<6)					// set '1' to clear CCA status
+		#define		CMT2310A_CSMA_DONE_CLR			(1<<5)					// set '1' to clear CSMA done
+		#define		CMT2310A_TX_DC_DONE_CLR			(1<<4)					// set '1' to clear TX_DC_DONE
+		#define		CMT2310A_ACK_RECV_FAILED_CLR	(1<<3)					// set '1' to clear ACK receive failed
+		#define		CMT2310A_TX_RESEND_DONE_CLR		(1<<2)					// set '1' to clear Tx resend done
+		#define		CMT2310A_NACK_RECV_CLR			(1<<1)					// set '1' to clear NACK receive 
+		#define		CMT2310A_SEQ_MATCH_CLR			(1<<0)					// set '1' to clear sequence number match
+
+	#define 		CMT2310A_CTL_REG_32             0x20					// mac function flag					(-RO)			
+		#define		CMT2310A_API_DONE_FLG			(1<<7)					//		
+		#define		CMT2310A_CCA_STATUS_FLG			(1<<6)					//
+		#define		CMT2310A_CSMA_DONE_FLG		    (1<<5)					//
+		#define		CMT2310A_TX_DC_DONE_FLG			(1<<4)					//
+		#define		CMT2310A_ACK_RECV_FAILED_FLG	(1<<3)					//
+		#define		CMT2310A_TX_RESEND_DONE_FLG		(1<<2)					//
+		#define		CMT2310A_NACK_RECV_FLG			(1<<1)					//
+		#define		CMT2310A_SEQ_MATCH_FLG			(1<<0)					//
+	
+	#define 		CMT2310A_CTL_REG_33             0x21					// RSSI value minimum	  				(-RO)
+		#define		CMT2310A_RSSI_MIN_REG			0x21
+	
+	#define 		CMT2310A_CTL_REG_34             0x22					// RSSI value							(-RO)	
+		#define		CMT2310A_RSSI_REG				0x22					
+
+	#define 		CMT2310A_CTL_REG_35             0x23					// LBD value							(-RO)
+		#define		CMT2310A_LBD_REG				0x23
+
+	#define 		CMT2310A_CTL_REG_36             0x24					// temperature value					(-RO)
+		#define		CMT2310A_TEMP_REG				0x24
+
+	#define 		CMT2310A_CTL_REG_37             0x25					// frequence channel current active 	(-RO)
+		#define		CMT2310A_FREQ_CHANL_ACT_REG		0x25
+		
+	#define 		CMT2310A_CTL_REG_38             0x26					// sequence number tx out[7:0]			(-RO)
+	#define 		CMT2310A_CTL_REG_39             0x27					// sequence number tx out[15:8]			(-RO)
+		#define		CMT2310A_SEQNUM_TX_OUT_L_REG	0x26
+		#define		CMT2310A_SEQNUM_TX_OUT_H_REG	0x27
+//--------------------------------- packet config -----------------------------
+	#define 		CMT2310A_CTL_REG_40             0x28					// rx preamble size[4:0] + preamble length unit + data mode[1:0]
+		#define		CMT2310A_RX_PREAM_SIZE_MASK		0xF8					// rx preamble detect length, 0=don't detect
+		#define		CMT2310A_PREAM_LENG_UNIIT		(1<<2)					// 0=8bits/unit,  1=4bits/unit (nibble)
+		
+		#define		CMT2310A_DATA_MODE_MASK			(3<<0)
+		#define		CMT2310A_DIRECT_MODE			(0<<0)					// Direct mode
+		#define		CMT2310A_PACKET_MODE			(2<<0)					// Packet mode
+
+	#define 		CMT2310A_CTL_REG_41             0x29					// tx preamble size[7:0]
+	#define 		CMT2310A_CTL_REG_42             0x2A					// tx preamble size[15:8]
+		#define		CMT2310A_TX_PREAM_SIZE_L_REG	0x29					// when TX_PREAM_SIZE=0, means do not send preamble
+		#define		CMT2310A_TX_PREAM_SIZE_H_REG	0x2A
+	
+	#define 		CMT2310A_CTL_REG_43             0x2B					// preamble value
+		#define		CMT2310A_PREAM_VALUE_REG		0x2B					// when PREAM_LENG_UNIIT = 0, 8bits active
+																			// when PREAM_LENG_UNIIT = 1, 4bits(LSB) active
+	#define 		CMT2310A_CTL_REG_44             0x2C					// sync control, sync_mode_sel + sync_tolerance[2:0] + sync_size[2:0] + sync_man_en
+		#define		CMT2310A_SYNC_CTL_REG			0x2C
+		#define		CMT2310A_SYNC_MODE_SEL			(1<<7)					// 0=compatible S2LP,   1=compatible 802.15.4
+		#define		CMT2310A_SYNC_TOL_MASK			(7<<4)
+		#define		CMT2310A_SYNC_SIZE_MASK			(7<<1)					// n+1 for SyncWord length
+		#define		CMT2310A_SYNC_MAN_EN			(1<<0)					// 0=disable, 1=enable SyncWord manchester encoding
+	
+	#define 		CMT2310A_CTL_REG_45             0x2D					// sync value 0 [7:0]		send last
+		#define		CMT2310A_SYNC_VALUE_7_REG		0x2D
+	#define 		CMT2310A_CTL_REG_46             0x2E					// sync value 1 [15:8]
+		#define		CMT2310A_SYNC_VALUE_6_REG		0x2E
+	#define 		CMT2310A_CTL_REG_47             0x2F					// sync value 2 [23:16]
+		#define		CMT2310A_SYNC_VALUE_5_REG		0x2F
+	#define 		CMT2310A_CTL_REG_48             0x30					// sync value 3 [31:24]
+		#define		CMT2310A_SYNC_VALUE_4_REG		0x30
+	#define 		CMT2310A_CTL_REG_49             0x31					// sync value 4 [39:32]
+		#define		CMT2310A_SYNC_VALUE_3_REG		0x31
+	#define 		CMT2310A_CTL_REG_50             0x32					// sync value 5 [47:40]
+		#define		CMT2310A_SYNC_VALUE_2_REG		0x32	
+	#define 		CMT2310A_CTL_REG_51             0x33					// sync value 6 [55:48]
+		#define		CMT2310A_SYNC_VALUE_1_REG		0x33
+	#define 		CMT2310A_CTL_REG_52             0x34					// sync value 7 [63:56]  	send first
+		#define		CMT2310A_SYNC_VALUE_0_REG		0x34	
+	
+	#define 		CMT2310A_CTL_REG_53             0x35					// sync fec value 0 [7:0]
+		#define		CMT2310A_FEC_SYNC_7_REG			0x35
+	#define 		CMT2310A_CTL_REG_54             0x36					// sync fec value 1 [15:8]
+		#define		CMT2310A_FEC_SYNC_6_REG			0x36
+	#define 		CMT2310A_CTL_REG_55             0x37					// sync fec value 2 [23:16]
+		#define		CMT2310A_FEC_SYNC_5_REG			0x37
+	#define 		CMT2310A_CTL_REG_56             0x38					// sync fec value 3 [31:24]
+		#define		CMT2310A_FEC_SYNC_4_REG			0x38
+	#define 		CMT2310A_CTL_REG_57             0x39					// sync fec value 4 [39:32]
+		#define		CMT2310A_FEC_SYNC_3_REG			0x39
+	#define 		CMT2310A_CTL_REG_58             0x3A					// sync fec value 5 [47:40]
+		#define		CMT2310A_FEC_SYNC_2_REG			0x3A
+	#define 		CMT2310A_CTL_REG_59             0x3B					// sync fec value 6 [55:48]
+		#define		CMT2310A_FEC_SYNC_1_REG			0x3B
+	#define 		CMT2310A_CTL_REG_60             0x3C					// sync fec	value 7 [63:56]
+		#define		CMT2310A_FEC_SYNC_0_REG			0x3C	
+	
+	#define 		CMT2310A_CTL_REG_61             0x3D					// payload length [7:0]
+	#define 		CMT2310A_CTL_REG_62             0x3E					// payload length [15:8]
+		#define		CMT2310A_PAYLOAD_LENGTH_L_REG	0x3D
+		#define		CMT2310A_PAYLOAD_LENGTH_H_REG	0x3E
+	
+	#define 		CMT2310A_CTL_REG_63             0x3F					// packet config 1,  interleave_en  +        x        +  length_size + piggybacking_en + x + addr_leng_conf + payload_bit_order + pkt_type
+		#define		CMT2310A_INTERLEAVE_EN			(1<<7)					// 0=disable,  	1=enable interleave
+		#define		CMT2310A_LENGTH_SIZE			(1<<5)					// 0=1Byte, for up to 255 bytes variable length packet£¬  
+		 																	// 1=2Bytes, for up to 65535 bytes variable length packet
+		#define		CMT2310A_PAGGYBACKING_EN		(1<<4)					// 0=disable,  	1=enable for auto paggy backing payload for auto-ack
+		#define		CMT2310A_ADDR_FIELD_EN			(1<<3)					// 0=disable,   1=enable for node address field
+		#define		CMT2310A_ADDR_LEN_CONF			(1<<2)					// 0=node address before length filed, 	1=node address after length filed.  Note! It is affect payload length
+		#define		CMT2310A_PAYLOAD_BIT_ORDER		(1<<1)					// 0=MSB first, 1=LSB first for decode (payload+crc filed)
+		#define		CMT2310A_PKT_TYPE				(1<<0)					// 0=fixed length packet,  	1=variable length packet
+
+	#define 		CMT2310A_CTL_REG_64             0x40					// packet config 2,  sync_value_sel + addr_split_mode + addr_free_en +  addr_err_mask  +   addr_size[1:0]   + addr_det_mode[1:0]
+		#define		CMT2310A_SYNC_VALUE_SEL			(1<<7)					// 0=select SYNC_VALUE,  	1=select SYNC_FEC_VALUE,  only for TX used
+		#define		CMT2310A_ADDR_SPLIT_MODE		(1<<6)					// 0=only DEST_ADDR filed active, 	1=DEST_ADDR+SRC_ADDR filed both active  
+		#define		CMT2310A_ADDR_FREE_EN			(1<<5)					// 0=disable,  	1=enable ADDR detect stand-alone
+		#define		CMT2310A_ADDR_ERR_MASK			(1<<4)					// 0=allow, 	1=not allow for reset decoding when ADDR mis-matching
+		#define		CMT2310A_ADDR_SIZE_MASK			(3<<2)					//
+		
+		#define		CMT2310A_ADDR_DET_MODE_MASK		(3<<0)					
+		#define		CMT2310A_ADDR_DET_DISABLE		(0<<0)					// disable node address detect
+		#define		CMT2310A_ADDR_DET_MATCH			(1<<0)					// rx only detect ADDR_VALUE,    tx send ADDR_VALUE
+		#define		CMT2310A_ADDR_DET_BOARDCAST_0	(2<<0)					// rx detect ADDR_VALUE & all-0, tx send ADDR_VALUE
+		#define		CMT2310A_ADDR_DET_BOARDCAST_ALL	(3<<0)					// rx detect ADDR_VALUE & all-0 & all-1,  tx send ADDR_VALUE
+			
+
+	#define 		CMT2310A_CTL_REG_65             0x41					// SRC_ADDR  [7:0]
+	#define 		CMT2310A_CTL_REG_66             0x42					// SRC_ADDR  [15:8]
+		#define		CMT2310A_SRC_ADDR_L_REG			0x41
+		#define		CMT2310A_SRC_ADDR_H_REG			0x42
+		
+	#define 		CMT2310A_CTL_REG_67             0x43					// DEST_ADDR [7:0]
+	#define 		CMT2310A_CTL_REG_68             0x44					// DEST_ADDR [15:8]
+		#define		CMT2310A_DEST_ADDR_L_REG		0x43
+		#define		CMT2310A_DEST_ADDR_H_REG		0x44
+
+	#define 		CMT2310A_CTL_REG_69             0x45					// SRC_BITMASK [7:0]
+	#define 		CMT2310A_CTL_REG_70             0x46					// SRC_BITMASK [15:8]
+		#define		CMT2310A_SRC_BITMASK_L_REG		0x45
+		#define		CMT2310A_SRC_BITMASK_H_REG		0x46
+	
+	#define 		CMT2310A_CTL_REG_71             0x47					// DEST_BITMASK [7:0]
+	#define 		CMT2310A_CTL_REG_72             0x48					// DEST_BITMASK [15:8]
+		#define		CMT2310A_DEST_BITMASK_L_REG		0x47
+		#define		CMT2310A_DEST_BITMASK_H_REG		0x48
+	
+	#define 		CMT2310A_CTL_REG_73             0x49					// crc config,       crc_size[1:0]  +  crc_byte_swap   + crc_bit_inv  +   crc_range   +  crc_refin  +  crc_bit_order  +  crc_en 
+		#define		CMT2310A_CRC_CFG_REG			0x49
+		#define		CMT2310A_CRC_SIZE_MASK			(3<<6)
+		#define		CMT2310A_CRC_SLE_CRC8			(0<<6)					// select crc-8
+		#define		CMT2310A_CRC_SLE_CRC16			(1<<6)					// select crc-16
+		#define		CMT2310A_CRC_SLE_CRC24			(2<<6)					// select crc-24
+		#define		CMT2310A_CRC_SLE_CRC32			(3<<6)					// select crc-32
+		
+		#define		CMT2310A_CRC_BYTE_SWAP			(1<<5)					// crc16 for example, 0=[15:8]+[7:0],  1=[7:0]+[15:8],   
+		#define		CMT2310A_CRC_BIT_INV			(1<<4)					// 0=disable,  		  1=enable for crc result inver	
+		#define		CMT2310A_CRC_RANGE				(1<<3)					// 0=whole payload,   1=only data
+		#define		CMT2310A_CRC_REFIN				(1<<2)					// 0=normal bit input flow,  1=inver bit input flow, for byte as unit
+		#define		CMT2310A_CRC_BIT_ORDER			(1<<1)					// 0=MSB send first,  1=LSB send first
+		#define		CMT2310A_CRC_EN					(1<<0)					// 0=disable, 		  1=enable CRC function
+			
+	#define 		CMT2310A_CTL_REG_74             0x4A					// crc seed 0 [7:0]
+	#define 		CMT2310A_CTL_REG_75             0x4B					// crc seed 1 [15:8]
+	#define 		CMT2310A_CTL_REG_76             0x4C					// crc seed 2 [23:16]
+	#define 		CMT2310A_CTL_REG_77             0x4D					// crc seed 3 [31:24]
+		#define		CMT2310A_CRC_SEED_0_REG			0x4A
+		#define		CMT2310A_CRC_SEED_1_REG			0x4B
+		#define		CMT2310A_CRC_SEED_2_REG			0x4C
+		#define		CMT2310A_CRC_SEED_3_REG			0x4D
+
+	#define 		CMT2310A_CTL_REG_78             0x4E					// crc polynomial 0 [7:0]
+	#define 		CMT2310A_CTL_REG_79             0x4F					// crc polynomial 1 [15:8]
+	#define 		CMT2310A_CTL_REG_80             0x50					// crc polynomial 2 [23:16]
+	#define 		CMT2310A_CTL_REG_81             0x51					// crc polynomial 3 [31:24]
+		#define		CMT2310A_CRC_POLY_0_REG			0x4E
+		#define		CMT2310A_CRC_POLY_1_REG			0x4F
+		#define		CMT2310A_CRC_POLY_2_REG			0x50
+		#define		CMT2310A_CRC_POLY_3_REG			0x51
+
+	#define 		CMT2310A_CTL_REG_82             0x52					// coding config,    crc_refout  +  whiten_seed[8]  +  whiten_seed_type  +  whiten_type[1:0]  +  whiten_en  +  manch_type  + manch_en
+		#define		CMT2310A_CRC_REFOUT				(1<<7)					// 0=MSB->LSB,  1=LSB->MSB, crc result turn over, byte as unit
+		#define		CMT2310A_WHITEN_SEED_B8			(1<<6)					// whiten_seed[8]
+		#define		CMT2310A_WHITEN_SEED_TYPE		(1<<5)					// 0=compatible A7139 PN7 seed,  1=PN7 seed by whien_seed
+		
+		#define		CMT2310A_WHITEN_TYPE_MASK		(3<<3)
+		#define		CMT2310A_WHITEN_PN9_CCITT		(0<<3)					// whiten type select PN9 CCITT
+		#define		CMT2310A_WHITEN_PN9_IBM			(1<<3)					// whiten type select PN9 IBM
+		#define		CMT2310A_WHITEN_PN7				(2<<3)					// whiten type select PN7
+		
+		#define		CMT2310A_WHITEN_EN				(1<<2)					// 0=disable, 1=enable whien encoding/decoding
+		
+		#define		CMT2310A_MANCH_TYPE				(1<<1)					// 0= 2'b01 as logic'1', 2'b10 as logic'0'
+																			// 1= 2'b10 as logic'1', 2'b01 as logic'0'	
+																			
+		#define		CMT2310A_MANCH_EN				(1<<0)					// 0=disable, 1=enable	manchester encoding/decoding
+
+	#define 		CMT2310A_CTL_REG_83             0x53					// whiten seed [7:0]
+		#define		CMT2310A_WHITEN_SEED_REG		0x53
+	
+	#define 		CMT2310A_CTL_REG_84             0x54					// packet config 3,  crc_err_clr_fifo_en + fcs2_en  +  seqnum_match_en  +  seqnum_size  +  seqnum_auto_inc  +  seqnum_en  +  tx_prefix_type[1:0]
+		#define		CMT2310A_CRCERR_CLR_FIFO_EN		(1<<7)					// 0=not clear,  1=clear Rx FIFO, when receive packet with CRC mis-matching
+		#define		CMT2310A_FCS2_EN				(1<<6)					// 0=disable,    1=enable FCS2 filed
+		#define		CMT2310A_SEQNUM_MATCH_EN		(1<<5)					// 0=disable,    1=enable matching for TX_ACK used, receive ack packet matching seqnum number which sent by local
+		#define		CMT2310A_SEQNUM_SIZE			(1<<4)					// 0=1Byte,      1=2Byte for sequence number filed
+		#define		CMT2310A_SEQNUM_AUTO_INC		(1<<3)					// 0=disable, 	 1=enable sequence number auto increase in TX, step=1
+		#define		CMT2310A_SEQNUM_EN				(1<<2)					// 0=disable,    1=enable sequence number filed (FCS1)
+
+		#define		CMT2310A_TX_PREFIX_TYPE_MASK	(3<<0)
+		#define		CMT2310A_TX_PREFIX_IS_0			(0<<0)					// tx prefix = 0
+		#define		CMT2310A_TX_PREFIX_IS_1			(1<<0)					// tx prefix = 1
+		#define		CMT2310A_TX_PREFIX_IS_PREAM		(2<<0)					// tx prefix = preamble
+
+
+
+	#define	 		CMT2310A_CTL_REG_85             0x55					// tx packet number [7:0]
+	#define 		CMT2310A_CTL_REG_86             0x56					// tx packet number [15:8]			
+		#define		CMT2310A_TX_PKT_NUM_L_REG		0x55
+		#define		CMT2310A_TX_PKT_NUM_H_REG		0x56	
+	
+	#define 		CMT2310A_CTL_REG_87             0x57					// sequence number tx inital value [7:0]
+	#define 		CMT2310A_CTL_REG_88             0x58					// sequence number tx inital value [15:8]
+		#define		CMT2310A_SEQNUM_TX_IN_L_REG		0x57
+		#define		CMT2310A_SEQNUM_TX_IN_H_REG		0x58	
+	
+	#define 		CMT2310A_CTL_REG_89             0x59					// tx packet gap [7:0]
+		#define		CMT2310A_TX_PKT_GAP_REG			0x59
+
+	#define 		CMT2310A_CTL_REG_90             0x5A					// Rssi calibrate offset
+		#define		CMT2310A_RSSI_CAL_OFFSET_REG	0x5A
+		
+	#define 		CMT2310A_CTL_REG_91             0x5B					// tx side FCS2 filed inital value [7:0]
+		#define		CMT2310A_FCS2_TX_IN_REG			0x5B				
+	
+	#define 		CMT2310A_CTL_REG_92             0x5C					// rx side FCC2 filed receive value [7:0]					(-RO)
+		#define		CMT2310A_FCS2_RX_OUT_REG		0x5C
+	
+	#define 		CMT2310A_CTL_REG_93             0x5D					// fec config 1, FEC_TICC  +  fec_padding_code[12:8]  +  fec_rcs_nrnsc_sel  + fec_en 
+		#define		CMT2310A_FEC_TICC				(1<<7)					// 0=invert, 	1=not invert, for FEC ui
+		#define 	CMT2310A_FEC_PAD_CODE_H_MASK	(0x1F<<2)				// fec_padding_code[12:8]
+		#define		CMT2310A_FEC_RSC_NRNSC_SEL		(1<<1)					// 0=RSC mode,  1=NRNSC mode
+		#define		CMT2310A_FEC_EN					(1<<0)					// 0=disable,   1=enable FEC encoding/decoding
+
+	#define 		CMT2310A_CTL_REG_94             0x5E					// fec config 2,   fec_padding_code[7:0]
+		#define		CMT2310A_FEC_PAD_CODE_L_REG		0x5E
+	
+	#define 		CMT2310A_CTL_REG_95             0x5F					// 4-FSK config,   4fsk_3_level[1:0]  +  4fsk_2_level[1:0]  +  4fsk_1_level[1:0]  +  4fsk_0_level[1:0]
+		#define		CMT2310A_MAP_4FSK_LEVEL_REG		0x5F
+//--------------------------------- system control config --------------------------------
+	#define 		CMT2310A_CTL_REG_96             0x60					// sysctrl 1,      fw_nk_sel  +  tx_exit_state[2:0]  +      x      +  tx_ack_en  +  tx_dc_persist_en  +  tx_dc_en
+
+		#define		CMT2310A_TX_EXIT_STATE_MASK		(7<<4)					// tx done exit state masker
+		#define		CMT2310A_TX_EXIT_TO_SLEEP		(1<<4)					// tx done exit to sleep
+		#define		CMT2310A_TX_EXIT_TO_READY		(2<<4)					// tx done exit to ready
+		#define		CMT2310A_TX_EXIT_TO_TFS			(3<<4)					// tx done exit to TFS
+		#define		CMT2310A_TX_EXIT_TO_TX			(4<<4)					// tx done exit to TX 
+		#define		CMT2310A_TX_EXIT_TO_RFS			(5<<4)					// tx done exit to RFS
+		#define		CMT2310A_TX_EXIT_TO_RX			(6<<4)					// tx done exit to RX 
+																			// others to sleep, & only for packet mode tx done
+		#define		CMT2310A_TX_AUTO_HOP_EN			(1<<3)					// 0=disable, 	1=enable tx auto hopping
+		#define		CMT2310A_TX_ACK_EN				(1<<2)					// 0=disable, 	1=enable tx ack function
+		#define		CMT2310A_TX_DC_PERSIST_EN		(1<<1)					// 0=auto exit tx duty-cycle when reach TX_DC_TIMES,  1=hold on until set this bit to '0'
+		#define		CMT2310A_TX_DC_EN				(1<<0)					// 0=disable,  	1=enable tx duty-cycle function
+
+	#define 		CMT2310A_CTL_REG_97             0x61					// sysctrl 2,      csma_en    +  rx_exit_state[2:0]  + timer_rx_en +  rx_ack_en  +   rx_auto_hop_en   +  rx_dc_en
+		#define		CMT2310A_CSMA_EN				(1<<7)					// 0=disable, 	1=enable CSMA
+
+		#define		CMT2310A_RX_EXIT_STATE_MASK		(7<<4)					// rx done exit state masker
+		#define		CMT2310A_RX_EXIT_TO_SLEEP		(1<<4)					// rx done exit to sleep
+		#define		CMT2310A_RX_EXIT_TO_READY		(2<<4)					// rx done exit to ready
+		#define		CMT2310A_RX_EXIT_TO_TFS			(3<<4)					// rx done exit to TFS
+		#define		CMT2310A_RX_EXIT_TO_TX			(4<<4)					// rx done exit to TX 
+		#define		CMT2310A_RX_EXIT_TO_RFS			(5<<4)					// rx done exit to RFS
+		#define		CMT2310A_RX_EXIT_TO_RX			(6<<4)					// rx done exit to RX 
+																			// others to sleep, & only for packet mode rx done
+		#define		CMT2310A_RX_TIMER_EN			(1<<3)					// 0=disable, 	1=enable rx timer
+		#define		CMT2310A_RX_ACK_EN				(1<<2)					// 0=disable, 	1=enable rx ack function
+		#define		CMT2310A_RX_AUTO_HOP_EN			(1<<1)					// 0=disable,   1=enable rx auto hopping function
+		#define		CMT2310A_RX_DC_EN				(1<<0)					// 0=disable, 	1=enable rx duty-cycle function
+
+	#define 		CMT2310A_CTL_REG_98             0x62					// sysctrl 3,      pkt_done_exit_en  +  rx_hop_slp_mode[2:0]  +  slp_mode[3:0]
+		#define		CMT2310A_PKT_DONE_EXIT_EN		(1<<7)					// 0=keep current, 	1=depends on RX_EXIT_STATE
+		#define		CMT2310A_RX_HOP_SLP_MODE_MASK	(7<<4)					// rx hopping supper low power mode selection
+		#define		CMT2310A_SLP_MODE_MASK			(15<<0)					// rx supper low power mode selection
+	
+	#define 		CMT2310A_CTL_REG_99             0x63                    // sysctrl 4,      timer_m_sleep [7:0]
+	#define 		CMT2310A_CTL_REG_100            0x64					// sysctrl 5, 	   timer_m_sleep [10:8]  +  timer_r_sleep [4:0]
+		#define		CMT2310A_SLEEP_TIMER_M_REG		0x63					// Tsleep = M*2^(R+1)*31.25us, R from 0 to 26
+		#define		CMT2310A_SLEEP_TIMER_R_REG		0x64					
+		#define		CMT2310A_SLEEP_TIMER_M_H_MASK	(7<<5)					
+		
+	#define 		CMT2310A_CTL_REG_101            0x65					// sysctrl 6,      timer_m_rx_T1 [7:0] 
+	#define 		CMT2310A_CTL_REG_102            0x66					// sysctrl 7,      timer_m_rx_T1 [10:8]  +  timer_r_rx_T1 [4:0]
+		#define		CMT2310A_RX_TIMER_T1_M_REG		0x65					// Trx_t1 = M*2^(R+1)*20us, R from 0 to 21, 
+		#define		CMT2310A_RX_TIMER_T1_R_REG		0x66					
+		#define		CMT2310A_RX_TIMER_T1_M_H_MASK	(7<<5)
+
+	#define 		CMT2310A_CTL_REG_103            0x67					// sysctrl 8, 	   timer_m_rx_T2 [7:0] 	
+	#define 		CMT2310A_CTL_REG_104            0x68					// sysctrl 9,      timer_m_rx_T2 [10:8]  +  timer_r_rx_T2 [4:0]
+		#define		CMT2310A_RX_TIMER_T2_M_REG		0x67					// Trx_t1 = M*2^(R+1)*20us, R from 0 to 21, 
+		#define		CMT2310A_RX_TIMER_T2_R_REG		0x68
+		#define		CMT2310A_RX_TIMER_T2_M_H_MASK	(7<<5)
+
+	#define 		CMT2310A_CTL_REG_105            0x69					// sysctrl 10,     tx_allow_rx  +  pup_done_state  +  timer_random_mode[1:0]  +  timer_sleep_en  +  rx_allow_tx  +  lfclk_sel  +  lfclk_out_en(lfosc/lfxo)
+
+		#define		CMT2310A_TIMER_RAND_MODE_MASK	(3<<4)					// CSMA mode, CSMA sleep timer random selection:
+		#define		CMT2310A_TIMER_RAND_R			(0<<4)					// select random R 
+		#define		CMT2310A_TIMER_RAND_M 			(1<<4)					// select random M 
+		#define		CMT2310A_TIMER_RAND_M_R			(2<<4)					// select random both R & M
+		#define		CMT2310A_TIMER_RAND_OFF			(3<<4)					// select random off, used fixed value
+	
+		#define		CMT2310A_SLEEP_TIMER_EN			(1<<3)					// 0=disable, 	1=enable sleep timer
+		#define		CMT2310A_LFCLK_SEL				(1<<1)					// 0=internal LFOSC,  	1=LFXO (32768Hz)
+		#define		CMT2310A_LFCLK_OUT_EN			(1<<0)					// 0=disable, 	1=enable GPIO4 for LFCLK out, priority lower than DIG_CLKOUT_EN, but higher than GPIO4_SEL
+
+	#define 		CMT2310A_CTL_REG_106            0x6A					// sysctrl 11,     cca_mode[2:0]  +  csma_persist_en  +  cca_int_sel[1:0]  +  cca_win_sel[1:0]
+		#define		CMT2310A_CSMA_CCA_MODE_MASK		(7<<5)
+		#define		CMT2310A_CSMA_CCA_DISABLE		(0<<5)					// 0= channel is always idle
+		#define		CMT2310A_CSMA_CCA_RSSI			(1<<5)					// 1= active >=1 of 4 times detect window, by Rssi
+		#define		CMT2310A_CSMA_CCA_PJD			(2<<5)					// 2= active >=1 of 4 times detect window, by PJD
+		#define		CMT2310A_CSMA_CCA_RSSI_PJD		(3<<5)					// 3= active >=1 of 4 times detect window, by PJD or Rssi
+		#define		CMT2310A_CSMA_CCA_SYNC			(4<<5)					// 4= detected sync word
+		#define		CMT2310A_CSMA_CCA_SYNC_RSSI		(5<<5)					// 5= detected sync word, or active >=1 of 4 times detect window, by Rssi
+		#define		CMT2310A_CSMA_CCA_SYNC_PJD		(6<<5)					// 6= detected sync word, or active >=1 of 4 times detect window, by PJD
+		#define		CMT2310A_CSMA_CCA_SYNC_RSSI_PJD	(7<<5)					// 7= detected sync word, or active >=1 of 4 times detect window, by PJD or Rssi
+		
+		#define		CMT2310A_CSMA_PERSIST_EN		(1<<4)					// 0=auto exit when reach max & channel still busy, 	1=keep on work until send out  
+		
+		#define		CMT2310A_CCA_INT_SEL_MASK		(3<<2)
+		#define		CMT2310A_CCA_INT_BY_PJD			(0<<2)					// CSMA_CCA interrupt condition by PJD
+		#define		CMT2310A_CCA_INT_BY_RSSI		(1<<2)					// CSMA_CCA interrupt condition by RSSI
+		#define		CMT2310A_CCA_INT_BY_PJD_RSSI	(2<<2)					// CSMA_CCA interrupt condition by PJD & RSSI
+		
+		#define		CMT2310A_CCA_WIN_SEL_MASK		(3<<0)
+		#define		CMT2310A_CCA_WIN_32_SYMBOL		(0<<0)					// CSMA detect window select 32symbols
+		#define		CMT2310A_CCA_WIN_64_SYMBOL		(1<<0)					// CSMA detect window select 64symbols
+		#define		CMT2310A_CCA_WIN_128_SYMBOL		(2<<0)					// CSMA detect window select 128symbols
+		#define		CMT2310A_CCA_WIN_256_SYMBOL		(3<<0)					// CSMA detect window select 256symbols
+	
+	
+	#define 		CMT2310A_CTL_REG_107            0x6B					// sysctrl 12, 	   timer_m_rx_csma [7:0]
+	#define 		CMT2310A_CTL_REG_108            0x6C					// sysctrl 13,     timer_m_rx_csma [10:8]  +  timer_r_rx_csma [4:0]
+		#define		CMT2310A_RX_TIMER_CSMA_M_REG	0x6B					// Trx_csma = M*2^(R+1)*20us, R from 0 to 21, 
+		#define		CMT2310A_RX_TIMER_CSMA_R_REG	0x6C
+		#define		CMT2310A_RX_TIMER_CSMA_M_H_MASK	(15<<4)		
+		
+	#define 		CMT2310A_CTL_REG_109            0x6D					// low battery detect threshold, lbd_th[7:0]
+		#define		CMT2310A_LBD_TH_REG				0x6D
+
+	#define 		CMT2310A_CTL_REG_110            0x6E					// sysctrl 14,     tx_dc_timer [7:0]
+		#define		CMT2310A_TX_DC_TIMES_REG		0x6E					
+
+	#define 		CMT2310A_CTL_REG_111            0x6F					// 
+		#define		CMT2310A_LENGTH_MODE			(1<<7)					// 0=normal, length filed as payload length,  	1=as Wi-SUN mode
+		#define		CMT2310A_WISUN_ALLIN			(1<<6)
+		#define		CMT2310A_WHITEN_WISUN			(1<<5)
+		#define		CMT2310A_WISUN_MS				(1<<4)
+		#define		CMT2310A_WISUN_FCS				(1<<1)
+		#define		CMT2310A_WISUN_DW				(1<<0)
+	
+	#define 		CMT2310A_CTL_REG_112            0x70					// sysctrl 15,     tx_dc_done_timer [7:0]		(-RO)	
+		#define		CMT2310A_TX_DC_DONE_TIMES_REG	0x70
+		
+	#define 		CMT2310A_CTL_REG_113            0x71					// sysctrl 16,     tx_resend_timer [7:0]
+		#define		CMT2310A_TX_RS_TIMES_REG		0x71
+
+	#define 		CMT2310A_CTL_REG_114            0x72					// sysctrl 17,     tx_resend_done_timer [7:0]	(-RO)
+		#define		CMT2310A_TX_RS_DONE_TIMES_REG	0x72
+
+	#define 		CMT2310A_CTL_REG_115            0x73					// sysctrl 18,     csma_timer [7:0]
+		#define		CMT2310A_CSMA_TIMES_REG			0x73
+		
+	#define 		CMT2310A_CTL_REG_116            0x74					// sysctrl 19,     csma_done_timer [7:0]		(-RO)
+		#define		CMT2310A_CSMA_DONE_TIMES_REG	0x74
+
+	#define 		CMT2310A_CTL_REG_117            0x75					
+
+	#define 		CMT2310A_CTL_REG_118            0x76					// sysctrl 20, 	   timer_m_sleep_csma [7:0]
+	#define 		CMT2310A_CTL_REG_119            0x77					// sysctrl 21, 	   timer_m_sleep_csma [10:8]  +  timer_r_sleep_csma [4:0]
+		#define		CMT2310A_SLEEP_TIMER_CSMA_M_REG	0x76					// Tsleep_timer_csma = M*2^(R+1)*31.25us, R from 0 to 26,
+		#define		CMT2310A_SLEEP_TIMER_CSMA_R_REG	0x77
+
+	#define			CMT2310A_FIFO_RW_PORT_REG		0x7A					// FIFO R/W interface
+	#define			CMT2310A_FIFO_RW_PORT			0x7A
+	
+	#define			CMT2310A_CRW_PORT_REG			0x7B	
+	#define			CMT2310A_CRW_PORT				0x7B
+
+	#define			CMT2310A_CLT_REG_126			0x7E
+	#define 		CMT2310A_PAGE_CTL_REG	        0x7E					// hv_page_sel
+		#define		CMT2310A_PAGE_SEL_MASK			(3<<6)
+		#define		CMT2310A_PAGE_0					(0<<6)					// 0=page 0
+		#define		CMT2310A_PAGE_1					(1<<6)					// 1=page 1
+		#define		CMT2310A_PAGE_2					(2<<6)					// 2=page 2
+
+	#define 		CMT2310A_SOFT_RST               0x7F					// soft_reset
+
+
+// --------------------------- CUS PAGE1 defines -----------------------------------------
+	#define 		CMT2310A_CMT_REG_00             0x00              		// export by RFPDK
+	#define 		CMT2310A_CMT_REG_01             0x01                    // export by RFPDK
+	#define 		CMT2310A_CMT_REG_02             0x02                    // export by RFPDK
+	#define 		CMT2310A_CMT_REG_03             0x03                    // export by RFPDK
+	#define 		CMT2310A_CMT_REG_04             0x04                    // export by RFPDK
+	#define 		CMT2310A_CMT_REG_05             0x05                    // export by RFPDK
+	#define 		CMT2310A_CMT_REG_06             0x06                    // export by RFPDK
+	#define 		CMT2310A_CMT_REG_07             0x07                    // export by RFPDK
+	#define 		CMT2310A_CMT_REG_08             0x08                    // export by RFPDK
+	#define 		CMT2310A_CMT_REG_09             0x09                    // export by RFPDK
+	#define 		CMT2310A_CMT_REG_10             0x0A                    // export by RFPDK
+	#define 		CMT2310A_CMT_REG_11             0x0B                    // export by RFPDK
+	#define 		CMT2310A_CMT_REG_12             0x0C                    // export by RFPDK
+	#define 		CMT2310A_CMT_REG_13             0x0D                    // export by RFPDK
+	#define 		CMT2310A_CMT_REG_14             0x0E                    // export by RFPDK
+	#define 		CMT2310A_CMT_REG_15             0x0F                    // export by RFPDK
+	#define 		CMT2310A_TX_FREQ_REG_00         0x10                    // export by RFPDK
+	#define 		CMT2310A_TX_FREQ_REG_01         0x11                    // export by RFPDK
+	#define 		CMT2310A_TX_FREQ_REG_02         0x12                    // export by RFPDK
+	#define 		CMT2310A_TX_FREQ_REG_03         0x13                    // export by RFPDK
+	#define 		CMT2310A_TX_MODE_REG_00         0x14                    // export by RFPDK
+	#define 		CMT2310A_TX_DR_REG_00           0x15                    // export by RFPDK
+	#define 		CMT2310A_TX_DR_REG_01           0x16                    // export by RFPDK
+	#define 		CMT2310A_TX_DR_REG_02           0x17                    // export by RFPDK
+	#define 		CMT2310A_TX_DR_REG_03           0x18                    // export by RFPDK
+	#define 		CMT2310A_TX_DR_REG_04           0x19                    // export by RFPDK
+	#define 		CMT2310A_TX_DR_REG_05           0x1A                    // export by RFPDK
+	#define 		CMT2310A_TX_DEV_REG_00          0x1B                    // export by RFPDK
+	#define 		CMT2310A_TX_DEV_REG_01          0x1C                    // export by RFPDK
+	#define 		CMT2310A_TX_DEV_REG_02          0x1D                    // export by RFPDK
+	#define 		CMT2310A_TX_PWR_REG_00          0x1E                    // export by RFPDK
+	#define 		CMT2310A_TX_PWR_REG_01          0x1F                    // export by RFPDK
+	#define 		CMT2310A_TX_PWR_REG_02          0x20                    // export by RFPDK
+	#define 		CMT2310A_TX_PWR_REG_03          0x21                    // export by RFPDK
+	#define 		CMT2310A_TX_PWR_REG_04          0x22                    // export by RFPDK
+	#define 		CMT2310A_TX_PWR_REG_05          0x23                    // export by RFPDK
+	#define 		CMT2310A_TX_PWR_REG_06          0x24                    // export by RFPDK
+	#define 		CMT2310A_TX_MISC_REG_00         0x25                    // export by RFPDK
+	#define 		CMT2310A_TX_MISC_REG_01         0x26                    // export by RFPDK
+	#define 		CMT2310A_TX_MISC_REG_02         0x27                    // export by RFPDK
+	#define 		CMT2310A_TX_RESEV_00            0x28                    // export by RFPDK
+	#define 		CMT2310A_TX_RESEV_01            0x29                    // export by RFPDK
+	#define 		CMT2310A_TX_RESEV_02            0x2A                    // export by RFPDK
+	#define 		CMT2310A_TX_RESEV_03            0x2B                    // export by RFPDK
+	#define 		CMT2310A_TX_RESEV_04            0x2C                    // export by RFPDK
+	#define 		CMT2310A_TX_RESEV_05            0x2D                    // export by RFPDK
+	#define 		CMT2310A_TX_RESEV_06            0x2E                    // export by RFPDK
+	#define 		CMT2310A_TX_RESEV_07            0x2F                    // export by RFPDK
+	#define 		CMT2310A_RX_FREQ_REG_00         0x30                    // export by RFPDK
+	#define 		CMT2310A_RX_FREQ_REG_01         0x31                    // export by RFPDK
+	#define 		CMT2310A_RX_FREQ_REG_02         0x32                    // export by RFPDK
+	#define 		CMT2310A_RX_FREQ_REG_03         0x33                    // export by RFPDK
+	#define 		CMT2310A_RX_FREQ_REG_04         0x34                    // export by RFPDK
+	#define 		CMT2310A_RX_IRF_REG_00          0x35                    // export by RFPDK
+	#define 		CMT2310A_RX_IRF_REG_01          0x36                    // export by RFPDK
+	#define 		CMT2310A_RX_IRF_REG_02          0x37                    // export by RFPDK
+	#define 		CMT2310A_RX_IRF_REG_03          0x38                    // export by RFPDK
+	#define 		CMT2310A_RX_PWR_REG_00          0x39                    // export by RFPDK
+	#define 		CMT2310A_RX_PWR_REG_01          0x3A                    // export by RFPDK
+	#define 		CMT2310A_RX_PWR_REG_02          0x3B                    // export by RFPDK
+	#define 		CMT2310A_RX_DR_REG_00           0x3C                    // export by RFPDK
+	#define 		CMT2310A_RX_DR_REG_01           0x3D                    // export by RFPDK
+	#define 		CMT2310A_RX_DR_REG_02           0x3E                    // export by RFPDK
+	#define 		CMT2310A_RX_DR_REG_03           0x3F                    // export by RFPDK
+	#define 		CMT2310A_RX_DR_REG_04           0x40                    // export by RFPDK
+	#define 		CMT2310A_RX_DR_REG_05           0x41                    // export by RFPDK
+	#define 		CMT2310A_RX_DR_REG_06           0x42                    // export by RFPDK
+	#define 		CMT2310A_RX_DR_REG_07           0x43                    // export by RFPDK
+	#define 		CMT2310A_RX_CDR_REG_00          0x44                    // export by RFPDK
+	#define 		CMT2310A_RX_CDR_REG_01          0x45                    // export by RFPDK
+	#define 		CMT2310A_RX_CDR_REG_02          0x46                    // export by RFPDK
+	#define 		CMT2310A_RX_CDR_REG_03          0x47                    // export by RFPDK
+	#define 		CMT2310A_RX_CHNL_REG_00         0x48                    // export by RFPDK
+	#define 		CMT2310A_RX_CHNL_REG_01         0x49                    // export by RFPDK
+	#define 		CMT2310A_RX_CHNL_REG_02         0x4A                    // export by RFPDK
+	#define 		CMT2310A_RX_AGC_REG_00          0x4B                    // export by RFPDK
+	#define 		CMT2310A_RX_AGC_REG_01          0x4C                    // export by RFPDK
+	#define 		CMT2310A_RX_AGC_REG_02          0x4D                    // export by RFPDK
+	#define 		CMT2310A_RX_AGC_REG_03          0x4E                    // export by RFPDK
+	#define 		CMT2310A_RX_AGC_REG_04          0x4F                    // export by RFPDK
+	#define 		CMT2310A_RX_AGC_REG_05          0x50                    // export by RFPDK
+	#define 		CMT2310A_RX_AGC_REG_06          0x51                    // export by RFPDK
+	#define 		CMT2310A_RX_2FSK_REG_00         0x52                    // export by RFPDK
+	#define 		CMT2310A_RX_2FSK_REG_01         0x53                    // export by RFPDK
+	#define 		CMT2310A_RX_2FSK_REG_02         0x54                    // export by RFPDK
+	#define 		CMT2310A_RX_2FSK_REG_03         0x55                    // export by RFPDK
+	#define 		CMT2310A_RX_AFC_REG_00          0x56                    // export by RFPDK
+	#define 		CMT2310A_RX_AFC_REG_01          0x57                    // export by RFPDK
+	#define 		CMT2310A_RX_AFC_REG_02          0x58                    // export by RFPDK
+	#define 		CMT2310A_RX_AFC_REG_03          0x59                    // export by RFPDK
+	#define 		CMT2310A_RX_4FSK_REG_00         0x5A                    // export by RFPDK
+	#define 		CMT2310A_RX_4FSK_REG_01         0x5B                    // export by RFPDK
+	#define 		CMT2310A_RX_4FSK_REG_02         0x5C                    // export by RFPDK
+	#define 		CMT2310A_RX_4FSK_REG_03         0x5D                    // export by RFPDK
+	#define 		CMT2310A_RX_OOK_REG_00          0x5E                    // export by RFPDK
+	#define 		CMT2310A_RX_OOK_REG_01          0x5F                    // export by RFPDK
+	#define 		CMT2310A_RX_OOK_REG_02          0x60                    // export by RFPDK
+	#define 		CMT2310A_RX_OOK_REG_03          0x61					// export by RFPDK	
+		
+	#define 		CMT2310A_RX_RSSI_REG_00         0x62					// rf_rssi_reg 0, 	coll_handle[1:0] + coll_step_sel[1:0] + rssi_update_sel[1:0] + nc + coll_det_en
+
+		#define		CMT2310A_COLL_STEP_SEL_MASK		(3<<4)					
+		#define		CMT2310A_COLL_STEP_SEL_6dB		(0<<4)					// collision select 6dB
+		#define		CMT2310A_COLL_STEP_SEL_10dB		(1<<4)					// collision select 10dB
+		#define		CMT2310A_COLL_STEP_SEL_16dB		(2<<4)					// collision select	16dB
+		#define		CMT2310A_COLL_STEP_SEL_20dB		(3<<4)					// collision select	20dB
+	
+		#define		CMT2310A_RSSI_UPDATE_SEL_MASK	(3<<2)
+		#define		CMT2310A_RSSI_UPDATE_ALWAYS		(0<<2)					// rssi update always on
+		#define		CMT2310A_RSSI_UPDATE_PREAM_OK	(1<<2)					// rssi	update by preamble detected		
+		#define		CMT2310A_RSSI_UPDATE_SYNC_OK	(2<<2)					// rssi update by syncword detected
+		#define		CMT2310A_RSSI_UPDATE_PKT_DONE	(3<<2)					// rssi update by packet done
+		
+		#define		CMT2310A_COLL_DET_EN			(1<<0)					// 0=disable,  	1=enable collision detect
+
+	#define 		CMT2310A_RX_RSSI_REG_01         0x63	 				// rf_rssi_reg 1, 	rssi_absolute_th[7:0]
+		#define		CMT2310A_RSSI_ABS_TH_REG		0x63
+
+	#define 		CMT2310A_RX_DOUT_REG_00         0x64					// rf_dout_reg, 	nc + nc + nc + dout_adjust_sel[2:0] + dout_adjust_mode + dout_adjust_en
+		#define		CMT2310A_DOUT_ADJUST_SEL_MASK	(7<<2)
+		#define		CMT2310A_DOUT_ADJUST_3_33		(0<<2)
+		#define		CMT2310A_DOUT_ADJUST_6_66		(1<<2)
+		#define		CMT2310A_DOUT_ADJUST_9_99		(2<<2)					
+		#define		CMT2310A_DOUT_ADJUST_13_32		(3<<2)
+		#define		CMT2310A_DOUT_ADJUST_16_65		(4<<2)
+		#define		CMT2310A_DOUT_ADJUST_19_98		(5<<2)
+		#define		CMT2310A_DOUT_ADJUST_23_21		(6<<2)
+		#define		CMT2310A_DOUT_ADJUST_26_64		(7<<2)
+		
+		#define		CMT2310A_DOUT_ADJUST_MODE		(1<<1)					// 0=+1 duty, 	1=-1 duty
+		#define		CMT2310A_DOUT_ADJUST_EN			(1<<0)					// 0=disable, 	1=enable dout adjust
+		
+
+	#define 		CMT2310A_RX_ANTD_REG_00         0x67					// rf_ant_reg		nc + nc + nc + nc + ant_wait_pmb[1:0] + ant_sw_dis + ant_div_en
+		#define		CMT2310A_ANT_WAIT_PMB_MASK		(3<<2)
+		#define		CMT2310A_ANT_WAIT_1_5_UNIT		(0<<2)					// wait preamble size *1.5, when antenna calibrate
+		#define		CMT2310A_ANT_WAIT_2_UNIT		(1<<2)					// wait preamble size *2, when antenna calibrate
+		#define		CMT2310A_ANT_WAIT_2_5_UNIT		(2<<2)					// wait preamble size *2.5, when antenna calibrate
+		#define		CMT2310A_ANT_WAIT_3_UNIT		(3<<2)					// wait preamble size *3, when antenna calibrate
+	
+		#define		CMT2310A_ANT_SW_DIS				(1<<1)					// 0=enable, 	1=bypass antenna switch
+		#define		CMT2310A_ANT_DIV_EN				(1<<0)					// 0=disable, 	1=enable antenna diversity
+
+// --------------------------- CUS PAGE2 defines -----------------------------------------
+
+	#define 		CMT2310A_FREQ_CHANL_00          0x00
+	#define 		CMT2310A_FREQ_CHANL_01          0x01
+	#define 		CMT2310A_FREQ_CHANL_02          0x02
+	#define 		CMT2310A_FREQ_CHANL_03          0x03
+	#define 		CMT2310A_FREQ_CHANL_04          0x04
+	#define 		CMT2310A_FREQ_CHANL_05          0x05
+	#define 		CMT2310A_FREQ_CHANL_06          0x06
+	#define 		CMT2310A_FREQ_CHANL_07          0x07
+	#define 		CMT2310A_FREQ_CHANL_08          0x08
+	#define 		CMT2310A_FREQ_CHANL_09          0x09
+	#define 		CMT2310A_FREQ_CHANL_10          0x0A
+	#define 		CMT2310A_FREQ_CHANL_11          0x0B
+	#define 		CMT2310A_FREQ_CHANL_12          0x0C
+	#define 		CMT2310A_FREQ_CHANL_13          0x0D
+	#define 		CMT2310A_FREQ_CHANL_14          0x0E
+	#define 		CMT2310A_FREQ_CHANL_15          0x0F
+	#define 		CMT2310A_FREQ_CHANL_16          0x10
+	#define 		CMT2310A_FREQ_CHANL_17          0x11
+	#define 		CMT2310A_FREQ_CHANL_18          0x12
+	#define 		CMT2310A_FREQ_CHANL_19          0x13
+	#define 		CMT2310A_FREQ_CHANL_20          0x14
+	#define 		CMT2310A_FREQ_CHANL_21          0x15
+	#define 		CMT2310A_FREQ_CHANL_22          0x16
+	#define 		CMT2310A_FREQ_CHANL_23          0x17
+	#define 		CMT2310A_FREQ_CHANL_24          0x18
+	#define 		CMT2310A_FREQ_CHANL_25          0x19
+	#define 		CMT2310A_FREQ_CHANL_26          0x1A
+	#define 		CMT2310A_FREQ_CHANL_27          0x1B
+	#define 		CMT2310A_FREQ_CHANL_28          0x1C
+	#define 		CMT2310A_FREQ_CHANL_29          0x1D
+	#define 		CMT2310A_FREQ_CHANL_30          0x1E
+	#define 		CMT2310A_FREQ_CHANL_31          0x1F
+	#define 		CMT2310A_FREQ_CHANL_32          0x20
+	#define 		CMT2310A_FREQ_CHANL_33          0x21
+	#define 		CMT2310A_FREQ_CHANL_34          0x22
+	#define 		CMT2310A_FREQ_CHANL_35          0x23
+	#define 		CMT2310A_FREQ_CHANL_36          0x24
+	#define 		CMT2310A_FREQ_CHANL_37          0x25
+	#define 		CMT2310A_FREQ_CHANL_38          0x26
+	#define 		CMT2310A_FREQ_CHANL_39          0x27
+	#define 		CMT2310A_FREQ_CHANL_40          0x28
+	#define 		CMT2310A_FREQ_CHANL_41          0x29
+	#define 		CMT2310A_FREQ_CHANL_42          0x2A
+	#define 		CMT2310A_FREQ_CHANL_43          0x2B
+	#define 		CMT2310A_FREQ_CHANL_44          0x2C
+	#define 		CMT2310A_FREQ_CHANL_45          0x2D
+	#define 		CMT2310A_FREQ_CHANL_46          0x2E
+	#define 		CMT2310A_FREQ_CHANL_47          0x2F
+	#define 		CMT2310A_FREQ_CHANL_48          0x30
+	#define 		CMT2310A_FREQ_CHANL_49          0x31
+	#define 		CMT2310A_FREQ_CHANL_50          0x32
+	#define 		CMT2310A_FREQ_CHANL_51          0x33
+	#define 		CMT2310A_FREQ_CHANL_52          0x34
+	#define 		CMT2310A_FREQ_CHANL_53          0x35
+	#define 		CMT2310A_FREQ_CHANL_54          0x36
+	#define 		CMT2310A_FREQ_CHANL_55          0x37
+	#define 		CMT2310A_FREQ_CHANL_56          0x38
+	#define 		CMT2310A_FREQ_CHANL_57          0x39
+	#define 		CMT2310A_FREQ_CHANL_58          0x3A
+	#define 		CMT2310A_FREQ_CHANL_59          0x3B
+	#define 		CMT2310A_FREQ_CHANL_60          0x3C
+	#define 		CMT2310A_FREQ_CHANL_61          0x3D
+	#define 		CMT2310A_FREQ_CHANL_62          0x3E
+	#define 		CMT2310A_FREQ_CHANL_63          0x3F
+	
+	#define			CMT2310A_CHIP_VERSION_00		0x40
+	#define			CMT2310A_CHIP_VERSION_01		0x41
+	#define			CMT2310A_CHIP_VERSION_02		0x42
+
+// -------------------------------- Marco defines ----------------------------------------- 
+	#define 		VAL_BIT0                        0x01
+	#define 		VAL_BIT1                        0x02
+	#define 		VAL_BIT2                        0x04
+	#define 		VAL_BIT3                        0x08
+	#define 		VAL_BIT4                        0x10
+	#define 		VAL_BIT5                        0x20
+	#define 		VAL_BIT6                        0x40
+	#define 		VAL_BIT7                        0x80
+	        		
+	#define 		BIT0                            0
+	#define 		BIT1                            1
+	#define 		BIT2                            2
+	#define 		BIT3                            3
+	#define 		BIT4                            4
+	#define 		BIT5                            5
+	#define 		BIT6                            6
+	#define 		BIT7                            7 
+
+	//## CMT2310A_CTL_REG_00 registers
+	#define 		M_BOOT_MAIN                     VAL_BIT1
+	#define 		M_POWERUP                     	VAL_BIT0
+
+	//## CMT2310A_CTL_REG_01 registers
+	#define 		M_GO_RXFS                     	VAL_BIT5
+	#define 		M_GO_TXFS                     	VAL_BIT4
+	#define 		M_GO_RX                       	VAL_BIT3
+	#define 		M_GO_TX                       	VAL_BIT2
+	#define 		M_GO_READY                    	VAL_BIT1
+	#define 		M_GO_SLEEP                    	VAL_BIT0
+
+	//##  CMT2310A_CTL_REG_02 registers 
+	#define 		M_MCU_GPIO_EN                   VAL_BIT2
+	#define 		M_ANT_DIV_MANU                  VAL_BIT1
+	#define 		M_ANT_SELECT                    VAL_BIT0
+
+	//## CMT2310A_CTL_REG_04 registers
+	#define 		M_TX_DIN_EN                  	VAL_BIT6
+	#define	 		M_GPIO1_SEL                    	(VAL_BIT5|VAL_BIT4|VAL_BIT3)
+	#define 		M_GPIO0_SEL                     (VAL_BIT2|VAL_BIT1|VAL_BIT0)
+	
+	//## CMT2310A_CTL_REG_05 registers
+	#define 		M_TX_DIN_SEL                   	(VAL_BIT7|VAL_BIT6)
+	#define 		M_GPIO3_SEL                     (VAL_BIT5|VAL_BIT4|VAL_BIT3)
+	#define 		M_GPIO2_SEL                     (VAL_BIT2|VAL_BIT1|VAL_BIT0)
+	
+	//## CMT2310A_CTL_REG_06 registers
+	#define 		M_DIG_CLKOUT_EN                	VAL_BIT6
+	#define 		M_GPIO5_SEL                     (VAL_BIT5|VAL_BIT4|VAL_BIT3)
+	#define 		M_GPIO4_SEL                     (VAL_BIT2|VAL_BIT1|VAL_BIT0)
+	
+	//## CMT2310A_CTL_REG_07 registers     
+	#define 		M_LFXO_PAD_EN                  	VAL_BIT5
+	#define 		M_API_STOP                     	VAL_BIT4
+	#define 		M_SPI_3W_EN                    	VAL_BIT3
+	#define 		M_NIRQ_SEL                     	(VAL_BIT2|VAL_BIT1|VAL_BIT0)
+
+	//## CMT2310A_CTL_REG_09 registers
+	#define 		M_API_CMD_FLAG                  VAL_BIT7
+	#define 		M_API_RESP                      (VAL_BIT6|VAL_BIT5|VAL_BIT4|VAL_BIT3|VAL_BIT2|VAL_BIT1|VAL_BIT0)
+	
+	//## CMT2310A_CTL_REG_10 registers
+	#define 		M_STATE_IS_TX                   VAL_BIT5
+	#define 		M_STATE_IS_RX                   VAL_BIT4
+	#define 		M_STATE_IS_TFS                  VAL_BIT3
+	#define 		M_STATE_IS_RFS                  VAL_BIT2
+	#define 		M_STATE_IS_READY                VAL_BIT1
+	#define 		M_STATE_IS_SLEEP                VAL_BIT0
+	
+	//## CMT2310A_CTL_REG_14 registers
+	#define 		M_RX_FIFO_FULL_RX_EN            VAL_BIT7
+	#define 		M_RX_FIFO_NMTY_RX_EN            VAL_BIT6
+	#define 		M_RX_FIFO_TH_RX_EN              VAL_BIT5
+	#define 		M_RX_FIFO_OVF_EN                VAL_BIT3
+	#define 		M_TX_FIFO_FULL_EN               VAL_BIT2
+	#define 		M_TX_FIFO_NMTY_EN               VAL_BIT1
+	#define 		M_TX_FIFO_TH_EN                 VAL_BIT0
+
+	//## CMT2310A_CTL_REG_15 registers
+ 	#define 		M_ANT_INSTR                     VAL_BIT0
+
+	//## CMT2310A_CTL_REG_16 registers
+	#define 		M_INT1_SEL                      (VAL_BIT5|VAL_BIT4|VAL_BIT3|VAL_BIT2|VAL_BIT1|VAL_BIT0)
+
+	//## CMT2310A_CTL_REG_17 registers
+	#define 		M_INT1_POLAR    	           	VAL_BIT7
+	#define 		M_INT2_POLAR                   	VAL_BIT6
+	#define 		M_INT2_SEL                      (VAL_BIT5|VAL_BIT4|VAL_BIT3|VAL_BIT2|VAL_BIT1|VAL_BIT0)
+	
+	//## CMT2310A_CTL_REG_18 registers
+	#define 		M_SLEEP_TMO_EN                 	VAL_BIT7
+	#define 		M_RX_TMO_EN                    	VAL_BIT6
+	#define 		M_TX_DONE_EN                   	VAL_BIT5
+	#define 		M_PREAM_PASS_EN                	VAL_BIT4
+	#define 		M_SYNC_PASS_EN                 	VAL_BIT3
+	#define 		M_ADDR_PASS_EN                 	VAL_BIT2
+	#define 		M_CRC_PASS_EN                  	VAL_BIT1
+	#define 		M_PKT_DONE_EN                  	VAL_BIT0
+	
+	//## CMT2310A_CTL_REG_19 registers
+	#define 		M_PD_FIFO                    	VAL_BIT6
+	#define 		M_FIFO_TH_8         	    	VAL_BIT5
+	#define 		M_FIFO_AUTO_CLR_RX_EN        	VAL_BIT4
+	#define 		M_FIFO_AUTO_RES_TX_EN        	VAL_BIT3
+	#define 		M_FIFO_TX_TEST_EN            	VAL_BIT2
+	#define 		M_FIFO_MERGE_EN              	VAL_BIT1
+	#define 		M_FIFO_TX_RX_SEL             	VAL_BIT0
+	
+	//## CMT2310A_CTL_REG_21 registers
+	#define 		M_RSSI_PJD_VALID_EN             VAL_BIT6
+	#define 		M_OP_CMD_FAILED_EN              VAL_BIT5
+	#define 		M_RSSI_COLL_EN                  VAL_BIT4
+	#define 		M_PKT_ERR_EN                    VAL_BIT3
+	#define 		M_LBD_STATUS_EN                 VAL_BIT2
+	#define 		M_LBD_STOP_EN                   VAL_BIT1
+	#define 		M_LD_STOP_EN                    VAL_BIT0
+	
+	//## CMT2310A_CTL_REG_22 registers                    
+	#define 		M_FREQ_HOP_MANU_EN              VAL_BIT7
+	#define 		M_RX_HOP_PERSIST                VAL_BIT5
+	#define 		M_FREQ_SW_STATE                 VAL_BIT6
+	#define 		M_TX_DATA_INV                   VAL_BIT4
+	#define 		M_PA_DIFF_SEL                   VAL_BIT3
+	#define 		M_TRX_SWT_INV                   VAL_BIT2
+	#define 		M_TRX_SWT_EN                    VAL_BIT1
+	#define 		M_ANT_LOCK_EN                   VAL_BIT0
+	
+	//## CMT2310A_CTL_REG_23 registers
+	#define 		M_API_DONE_EN                 	VAL_BIT7
+	#define 		M_CCA_STATUS_EN               	VAL_BIT6
+	#define 		M_CSMA_DONE_EN                 	VAL_BIT5
+	#define 		M_TX_DC_DONE_EN                	VAL_BIT4
+	#define 		M_ACK_RECV_FAILED_EN          	VAL_BIT3
+	#define 		M_TX_RESEND_DONE_EN            	VAL_BIT2
+	#define 		M_NACK_RECV_EN                	VAL_BIT1
+	#define 		M_SEQ_MATCH_EN                	VAL_BIT0
+	
+	//## CMT2310A_CTL_REG_24 registers 
+	#define 		M_SLEEP_TMO_FLG              	VAL_BIT5
+	#define 		M_RX_TMO_FLG                 	VAL_BIT4
+	#define 		M_TX_DONE_FLG                	VAL_BIT3
+	#define 		M_TX_DONE_CLR                	VAL_BIT2
+	#define 		M_RX_TMO_CLR                 	VAL_BIT1
+	#define 		M_SLEEP_TMO_CLR              	VAL_BIT0 
+	
+	//## CMT2310A_CTL_REG_25 registers
+	#define 		M_PREAM_PASS_CLR               	VAL_BIT4
+	#define 		M_SYNC_PASS_CLR                	VAL_BIT3
+	#define 		M_ADDR_PASS_CLR                	VAL_BIT2
+	#define 		M_CRC_PASS_CLR                 	VAL_BIT1
+	#define 		M_PKT_DONE_CLR                 	VAL_BIT0
+	
+	//## CMT2310A_CTL_REG_26 registers
+	#define 		M_SYNC1_PASS_FLG                VAL_BIT5
+	#define 		M_PREAM_PASS_FLG                VAL_BIT4
+	#define 		M_SYNC_PASS_FLG                 VAL_BIT3
+	#define 		M_ADDR_PASS_FLG                 VAL_BIT2
+	#define 		M_CRC_PASS_FLG                  VAL_BIT1
+	#define 		M_PKT_DONE_FLG                  VAL_BIT0
+	
+	//## CMT2310A_CTL_REG_27 registers
+	#define 		M_TX_FIFO_RESTORE             	VAL_BIT2
+	#define 		M_RX_FIFO_CLR                 	VAL_BIT1
+	#define 		M_TX_FIFO_CLR                 	VAL_BIT0
+	
+	//## CMT2310A_CTL_REG_28 registers
+	#define 		M_RX_FIFO_FULL_FLG            	VAL_BIT7
+	#define 		M_RX_FIFO_NMTY_FLG            	VAL_BIT6
+	#define 		M_RX_FIFO_TH_FLG              	VAL_BIT5
+	#define 		M_RX_FIFO_OVF_FLG             	VAL_BIT3
+	#define 		M_TX_FIFO_FULL_FLG            	VAL_BIT2
+	#define 		M_TX_FIFO_NMTY_FLG            	VAL_BIT1
+	#define 		M_TX_FIFO_TH_FLG              	VAL_BIT0
+	
+	//## CMT2310A_CTL_REG_29 registers 
+	#define 		M_ANT_LOCK_CLR                    VAL_BIT4
+	#define 		M_OP_CMD_FAILED_CLR               VAL_BIT3
+	#define 		M_RSSI_COLL_CLR                   VAL_BIT2
+	#define 		M_PKT_ERR_CLR                     VAL_BIT1
+	#define 		M_LBD_STATUS_CLR                  VAL_BIT0
+	
+	//## CMT2310A_CTL_REG_30 registers
+	#define 		M_ANT_LOCK_FLG                    VAL_BIT4
+	#define 		M_OP_CMD_FAILED_FLG               VAL_BIT3
+	#define 		M_RSSI_COLL_FLG                   VAL_BIT2
+	#define 		M_PKT_ERR_FLG                     VAL_BIT1
+	#define 		M_LBD_STATUS_FLG                  VAL_BIT0
+
+	
+	//## CMT2310A_CTL_REG_31 registers
+	#define 		M_API_DONE_CLR                    VAL_BIT7
+	#define 		M_CCA_STATUS_CLR                  VAL_BIT6
+	#define 		M_CSMA_DONE_CLR                   VAL_BIT5
+	#define 		M_TX_DC_DONE_CLR                  VAL_BIT4
+	#define 		M_ACK_RECV_FAILED_CLR             VAL_BIT3
+	#define 		M_TX_RESEND_DONE_CLR              VAL_BIT2
+	#define 		M_NACK_RECV_CLR                   VAL_BIT1
+	#define 		M_SEQ_MATCH_CLR                   VAL_BIT0
+	
+	//##  CMT2310A_CTL_REG_32 registers
+	#define 		M_API_DONE_FLG                    VAL_BIT7
+	#define 		M_CCA_STATUS_FLG                  VAL_BIT6
+	#define 		M_CSMA_DONE_FLG                   VAL_BIT5
+	#define 		M_TX_DC_DONE_FLG                  VAL_BIT4
+	#define 		M_ACK_RECV_FAILED_FLG             VAL_BIT3
+	#define 		M_TX_RESEND_DONE_FLG              VAL_BIT2
+	#define 		M_NACK_RECV_FLG                   VAL_BIT1
+	#define 		M_SEQ_MATCH_FLG                   VAL_BIT0
+
+	//## CMT2310A_CTL_REG_126 registers 
+	#define 		M_HV_PAGE_SEL                     (VAL_BIT7|VAL_BIT6)
+
+	//##  CMT2310A STATE 
+	#define 		STATE_IS_IDLE                	0x00 
+	#define 		STATE_IS_SLEEP               	0x81 
+	#define 		STATE_IS_READY               	0x82
+	#define 		STATE_IS_RFS                 	0x84
+	#define 		STATE_IS_TFS                 	0x88
+	#define 		STATE_IS_RX                  	0x90
+	#define 		STATE_IS_TX                  	0xA0
+	
+	//##  GPIO0_SEL 
+	#define 		GPIO0_SEL_DOUT                	0x00
+	#define 		GPIO0_SEL_INT1                	0x01 
+	#define 		GPIO0_SEL_INT2                	0x02 
+	#define 		GPIO0_SEL_DCLK                	0x03 
+	
+	//##  GPIO1_SEL 
+	#define 		GPIO1_SEL_DCLK                	0x00
+	#define 		GPIO1_SEL_INT1                	0x01 
+	#define 		GPIO1_SEL_INT2                	0x02 
+	#define 		GPIO1_SEL_DOUT                	0x03 
+	
+	//##  GPIO2_SEL 
+	#define 		GPIO2_SEL_INT1                 	0x00
+	#define 		GPIO2_SEL_INT2                 	0x01 
+	#define 		GPIO2_SEL_DCLK                 	0x02 
+	#define 		GPIO2_SEL_DOUT                 	0x03 
+	
+	//##  GPIO3_SEL 
+	#define 		GPIO3_SEL_INT2                	0x00
+	#define 		GPIO3_SEL_INT1                	0x01 
+	#define 		GPIO3_SEL_DCLK                	0x02 
+	#define 		GPIO3_SEL_DOUT                	0x03 
+	#define 		GPIO3_SEL_DIN                 	0x05 
+	
+	//##  GPIO4_SEL 
+	#define 		GPIO4_SEL_DOUT                	0x00
+	#define 		GPIO4_SEL_INT1                	0x01 
+	#define 		GPIO4_SEL_INT2                	0x02 
+	#define 		GPIO4_SEL_DCLK                	0x03 
+	#define 		GPIO4_SEL_DIN                 	0x05 
+	
+	//## GPIO5_SEL 
+	#define 		GPIO5_SEL_RSTN                	0x00
+	#define 		GPIO5_SEL_INT1                	0x01 
+	#define 		GPIO5_SEL_INT2                	0x02 
+	#define 		GPIO5_SEL_DOUT                	0x03 
+	#define 		GPIO5_SEL_DCLK                	0x04 
+	
+	//## TX_DIN_SEL 
+	#define 		TX_DIN_SEL_GPIO3              	0x00
+	#define 		TX_DIN_SEL_GPIO4              	0x01 
+	#define 		TX_DIN_SEL_NIRQ               	0x02
+	
+	//## NIRQ_SEL
+	#define 		NIRQ_SEL_INT1                 	0x00
+	#define 		NIRQ_SEL_INT2                 	0x01 
+	#define 		NIRQ_SEL_DCLK                 	0x02 
+	#define 		NIRQ_SEL_DOUT                 	0x03 
+	#define 		NIRQ_SEL_DIN                  	0x04
+	
+	//## INT1/2_SEL 
+	#define 		INT_SRC_MIX                     0x00
+	#define 		INT_SRC_ANT_LOCK                0x01
+	#define 		INT_SRC_RSSI_PJD_VALID          0x02
+	#define 		INT_SRC_PREAM_PASS              0x03
+	#define 		INT_SRC_SYNC_PASS               0x04
+	#define 		INT_SRC_ADDR_PASS               0x05
+	#define 		INT_SRC_CRC_PASS                0x06
+	#define 		INT_SRC_PKT_OK                  0x07
+	#define 		INT_SRC_PKT_DONE                0x08
+	#define 		INT_SRC_SLEEP_TMO               0x09
+	#define 		INT_SRC_RX_TMO                  0x0A
+	#define 		INT_SRC_RX_FIFO_NMTY            0x0B
+	#define 		INT_SRC_RX_FIFO_TH              0x0C
+	#define 		INT_SRC_RX_FIFO_FULL            0x0D
+	#define 		INT_SRC_RX_FIFO_WBYTE           0x0E
+	#define 		INT_SRC_RX_FIFO_OVF             0x0F
+	#define 		INT_SRC_TX_DONE                 0x10
+	#define 		INT_SRC_TX_FIFO_NMTY            0x11
+	#define 		INT_SRC_TX_FIFO_TH              0x12
+	#define 		INT_SRC_TX_FIFO_FULL            0x13
+	#define 		INT_SRC_STATE_IS_READY          0x14
+	#define 		INT_SRC_STATE_IS_FS             0x15
+	#define 		INT_SRC_STATE_IS_RX             0x16
+	#define 		INT_SRC_STATE_IS_TX             0x17
+	#define 		INT_SRC_LBD_STATUS              0x18
+	#define 		INT_SRC_API_CMD_FAILED          0x19
+	#define 		INT_SRC_API_DONE                0x1A
+	#define 		INT_SRC_TX_DC_DONE              0x1B
+	#define 		INT_SRC_ACK_RECV_FAILED         0x1C
+	#define 		INT_SRC_TX_RESEND_DONE          0x1D
+	#define 		INT_SRC_NACK_RECV               0x1E
+	#define 		INT_SRC_SEQ_MATCH               0x1F
+	#define 		INT_SRC_CSMA_DONE               0x20
+	#define 		INT_SRC_CCA_STATUS              0x21
+
+#endif
+
+//******************************************************************************
+//* EOF (not truncated)
+//******************************************************************************
diff --git a/NSPE/WIFI_IOT/bsp/drivers/3_Ebyte_WirelessModule_Drivers/E48xMx/cmt2310a_410mhz.c b/NSPE/WIFI_IOT/bsp/drivers/3_Ebyte_WirelessModule_Drivers/E48xMx/cmt2310a_410mhz.c
new file mode 100755
index 0000000..f0b9254
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/3_Ebyte_WirelessModule_Drivers/E48xMx/cmt2310a_410mhz.c
@@ -0,0 +1,428 @@
+#include "radio_hal.h"
+#include "CMT2310A_reg.h"
+#include "CMT2310A_def.h"
+
+/****************************************************************************
+;---------------------------------------
+;  CMT2310A Configuration File
+;  Generated by CMOSTEK RFPDK 1.54
+;  2023.12.07 13:35
+;---------------------------------------
+; Mode                       = Advanced
+; Part Number                = CMT2310A
+; Frequency                  = 410.000 MHz
+; DC-DC                      = Off
+; Demodulation               = GFSK
+; Xtal Cap Load              = 2
+; Data Rate                  = 2.400 kbps
+; Deviation                  = 4.800 kHz
+; Tx Xtal Tol.               = 10 ppm
+; Rx Xtal Tol.               = 10 ppm
+; TRx Matching Network Type  = 20 dBm
+; Tx Power                   = +20 dBm
+; Gaussian BT                = 0.5
+; PA Ramp                    = On-Autosel Rampstep
+; PA Ramp Step               = NA
+; RF Performance             = NA
+; Output Drive Capability    = 0.5mA
+; Rx Duty-Cycle              = Off
+; Tx Duty-Cycle              = Off
+; Sleep Timer                = Off
+; Sleep Time                 = NA
+; Rx Timer                   = Off
+; Rx Time T1                 = NA
+; Rx Time T2                 = NA
+; Rx Exit State              = STBY
+; Tx Exit State              = STBY
+; TX Duty Cycle Persist      = Off
+; Packet Done Exit           = Off
+; TX Duty-Cycle Times        = 0
+; SLP Mode                   = Mode 0
+; RSSI Valid Source          = RSSI Compare
+; PJD Window                 = NA
+; RSSI Compare TH            = -127 dBm
+; CDR Type                   = Counting
+; AFC                        = autosel
+; FSK2 Data Map              = 0:F-low 1:F-high
+; FSK4 Data Map              = NA
+; FSK4 RX Data Map           = NA
+; CDR Type                   = Counting
+; CDR Range Sel FSK          = NA
+; Channel BW                 = autosel
+; Baseband BW FSK            = autosel
+; Data Mode                  = Packet
+; Packet Mode                = Normal
+; PiggyBacking               = Disable
+; Manchester                 = Disable
+; Manchester Type            = NA
+; Whitening                  = Disable
+; Whiten Type                = NA
+; Whiten Seed Type           = NA
+; Whiten Seed                = NA
+; FEC                        = Disable
+; FEC Type                   = NA
+; FEC Padding Code           = NA
+; crc err clear fifo         = Not Clear
+; Tx Packet Gap              = 32 symbol(s)
+; Tx Packet Number           = 1 packet(s)
+; Tx Prefix Type             = 0
+; Packet Type                = Fixed Length
+; Address-Length Position    = NA
+; Length Size                = 1-byte
+; Payload Bit Order          = Start from msb
+; Address Field              = Disable
+; Preamble Rx Size           = 2
+; Preamble Tx Size           = 8
+; Preamble Value             = 170
+; Preamble Unit              = 8-bit
+; Sync Size                  = 3-byte
+; Sync Format                = S2LP
+; Sync Value                 = 3003605
+; Sync Manchester            = Disable
+; Sync Value Selection       = Sync Value
+; Sync FEC Value             = 3003605
+; Sync Tolerance             = None
+; Address Detect Mode        = None
+; Address Split Mode         = NA
+; Address Size               = NA
+; Address Err Mask           = NA
+; Address Free               = NA
+; Dest Addr Value            = NA
+; Src Addr Value             = NA
+; Dest Addr Bit Mask         = NA
+; Src Addr Bit Mask          = NA
+; Sequence Num               = None
+; Sequence Num Match         = off
+; Sequence Num Mode          = NA
+; Sequence Num Value         = NA
+; FCS2                       = None
+; FCS2 Value                 = NA
+; Payload Length             = 32
+; CRC Options                = None
+; CRC Swap                   = NA
+; CRC Seed                   = NA
+; CRC Bit Invert             = NA
+; CRC Range                  = NA
+; CRC Polynomial             = NA
+; CRC Bit Order              = NA
+; CRC Refin                  = NA
+; CRC_Refout                 = NA
+; Frequency Hopping Mode     = Mode 2
+; Freq Hopping Space         = 10 kHz
+; Hopping Channels           = 10
+; CSMA Mode                  = Disable
+; CSMA RSSI Detection        = NA
+; Hopping Persist            = Disable
+; Hopping Intermediate State = TRFS
+; CSMA Sleep Timer Random    = NA
+; CSMA Rx Time               = NA
+; CSMA Sleep Time M          = NA
+; CSMA Sleep Time R          = NA
+; CSMA Persist               = NA
+; CSMA Detect Times          = NA
+; Tx Auto Hopping            = Disable
+; Rx Auto Hopping            = Disable
+; Auto Acknowledge           = off
+; Auto Resend                = off
+; Maximum Resend Times       = 1
+; RSSI Detect Mode           = always
+; LFOSC LFXO Sel             = LFOSC(32kHz)
+; LF Clock Out               = off
+; Dout Mute                  = disable
+; Dout Mute Sel              = NA
+; dout adjust mode           = disable
+; Dout Adjust Percentage     = NA
+; LBD Threshold              = 2.4 v
+; Antenna Diversity          = off
+; Antenna Switch Mode        = NA
+; Collision Detect           = off
+; Collision Step             = NA
+; RSSI Offset dB             = NA
+; RSSI Offset Sel            = autosel
+; i_fir_bb_bw_for_cal_freq   = 1
+
+;---------------------------------------
+;  The following are the Register contents
+;---------------------------------------
+
+*****************************************************************************/
+
+#if (PRODUCT_FREQUENCY == CM2310A_410MHZ)
+
+/* [CMT page0] */
+const uint8_t g_cmt2310a_page0[CMT2310A_PAGE0_SIZE] = {
+    0x12,
+    0x08,
+    0x00,
+    0xAA,
+    0x04,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0xD5,
+    0xD4,
+    0x2D,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0xD5,
+    0xD4,
+    0x2D,
+    0x1F,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x2D,
+    0x00,
+    0x00,
+    0x00,
+    0x2D,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x45,
+    0x1F,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x08,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x1F,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0xE4,
+    0x20,
+    0x20,
+    0x20,
+    0x01,
+    0x00,
+    0xD0,
+    0xE0,
+    0xE2,
+    0x84,
+    0x30,
+    0x04,
+    0xD0,
+    0xE0,
+    0x80,
+    0x00,
+    0x41,
+    0x00,
+    0x01,
+    0x00,
+    0x02,
+    0x00,
+    0x00,
+    0x03,
+    0x04,
+};   
+
+/* [CMT page1] */
+const uint8_t g_cmt2310a_page1[CMT2310A_PAGE1_SIZE] = {
+    0x10,
+    0x06,
+    0x00,
+    0xFF,
+    0x00,
+    0xCD,
+    0x02,
+    0x28,
+    0x50,
+    0x87,
+    0x31,
+    0x5B,
+    0x08,
+    0x00,
+    0xFF,
+    0x00,
+    0x66,
+    0x00,
+    0x00,
+    0x08,
+    0xB4,
+    0xEA,
+    0x04,
+    0xE0,
+    0x20,
+    0x08,
+    0x05,
+    0x8D,
+    0x06,
+    0x00,
+    0xA0,
+    0x7F,
+    0x00,
+    0x18,
+    0x00,
+    0x00,
+    0x1F,
+    0xE4,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0xCA,
+    0x66,
+    0x00,
+    0x80,
+    0xD8,
+    0x63,
+    0x00,
+    0x80,
+    0x0F,
+    0x64,
+    0x06,
+    0x02,
+    0xEA,
+    0x04,
+    0x00,
+    0x36,
+    0x01,
+    0x20,
+    0xC8,
+    0x63,
+    0xA1,
+    0x15,
+    0x34,
+    0x58,
+    0x40,
+    0xD2,
+    0x74,
+    0xF0,
+    0x0F,
+    0x01,
+    0x17,
+    0xE6,
+    0x54,
+    0x08,
+    0x39,
+    0xE6,
+    0x27,
+    0x0C,
+    0x01,
+    0xB4,
+    0x06,
+    0x0F,
+    0x00,
+    0x4C,
+    0x00,
+    0x00,
+    0xF6,
+    0x00,
+    0x00,
+    0x00,
+    0x10,
+    0x81,
+    0x00,
+    0x00,
+    0x47,
+    0x12,
+    0x25,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+};   
+
+//#define CMT2310A_AUTO_HOP_ENABLE
+#ifdef  CMT2310A_AUTO_HOP_ENABLE
+#define freq_space_val           0x0A
+#define freq_times_val           0x0A
+#define freq_switch_state_val    0x01
+#define freq_hop_persist_val     0x00
+
+/* [CMT page2] */
+const uint8_t g_cmt2310a_page2[CMT2310A_PAGE2_SIZE] = {
+     0x00,
+     0x00,
+     0x00,
+     0x00,
+     0x00,
+     0x00,
+     0x00,
+     0x00,
+     0x00,
+     0x00,
+     0x00,
+     0x00,
+     0x00,
+     0x00,
+     0x00,
+     0x00,
+     0x00,
+     0x00,
+     0x00,
+     0x00,
+     0x00,
+     0x00,
+     0x00,
+     0x00,
+     0x00,
+     0x00,
+     0x00,
+     0x00,
+     0x00,
+     0x00,
+     0x00,
+     0x00,
+     0x00,
+     0x00,
+     0x00,
+     0x00,
+     0x00,
+     0x00,
+     0x00,
+     0x00,
+     0x00,
+     0x00,
+     0x00,
+     0x00,
+     0x00,
+     0x00,
+     0x00,
+     0x00,
+     0x00,
+     0x00,
+     0x00,
+     0x00,
+     0x00,
+     0x00,
+     0x00,
+     0x00,
+     0x00,
+     0x00,
+     0x00,
+     0x00,
+     0x00,
+     0x00,
+     0x00,
+     0x00,
+};   
+#endif 
+ 
+#endif  
diff --git a/NSPE/WIFI_IOT/bsp/drivers/3_Ebyte_WirelessModule_Drivers/E48xMx/cmt2310a_433mhz.c b/NSPE/WIFI_IOT/bsp/drivers/3_Ebyte_WirelessModule_Drivers/E48xMx/cmt2310a_433mhz.c
new file mode 100755
index 0000000..8a4d8c7
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/3_Ebyte_WirelessModule_Drivers/E48xMx/cmt2310a_433mhz.c
@@ -0,0 +1,351 @@
+#include "radio_hal.h"
+#include "CMT2310A_reg.h"
+#include "CMT2310A_def.h"
+
+
+/****************************************************************************
+;---------------------------------------
+;  CMT2310A Configuration File
+;  Generated by CMOSTEK RFPDK 1.53_Update4
+;  2023.01.14 10:34
+;---------------------------------------
+; Mode                       = Advanced
+; Part Number                = CMT2310A
+; Frequency                  = 433.920 MHz
+; DC-DC                      = Off
+; Demodulation               = GFSK
+; Xtal Cap Load              = 2
+; Data Rate                  = 2.400 kbps
+; Deviation                  = 4.800 kHz
+; Tx Xtal Tol.               = 10 ppm
+; Rx Xtal Tol.               = 10 ppm
+; TRx Matching Network Type  = 20 dBm
+; Tx Power                   = +20 dBm
+; Gaussian BT                = 0.5
+; PA Ramp                    = On-Autosel Rampstep
+; PA Ramp Step               = NA
+; RF Performance             = NA
+; Output Drive Capability    = 0.5mA
+; Rx Duty-Cycle              = Off
+; Tx Duty-Cycle              = Off
+; Sleep Timer                = Off
+; Sleep Time                 = NA
+; Rx Timer                   = Off
+; Rx Time T1                 = NA
+; Rx Time T2                 = NA
+; Rx Exit State              = STBY
+; Tx Exit State              = STBY
+; TX Duty Cycle Persist      = Off
+; Packet Done Exit           = Off
+; TX Duty-Cycle Times        = 0
+; SLP Mode                   = Mode 0
+; RSSI Valid Source          = RSSI Compare
+; PJD Window                 = NA
+; RSSI Compare TH            = -127 dBm
+; CDR Type                   = Counting
+; AFC                        = autosel
+; FSK2 Data Map              = 0:F-low 1:F-high
+; FSK4 Data Map              = NA
+; FSK4 RX Data Map           = NA
+; CDR Type                   = Counting
+; CDR Range Sel FSK          = NA
+; Channel BW                 = autosel
+; Baseband BW FSK            = autosel
+; Data Mode                  = Packet
+; Packet Mode                = Normal
+; PiggyBacking               = Disable
+; Manchester                 = Disable
+; Manchester Type            = NA
+; Whitening                  = Disable
+; Whiten Type                = NA
+; Whiten Seed Type           = NA
+; Whiten Seed                = NA
+; FEC                        = Disable
+; FEC Type                   = NA
+; FEC Padding Code           = NA
+; crc err clear fifo         = Not Clear
+; Tx Packet Gap              = 32 symbol(s)
+; Tx Packet Number           = 1 packet(s)
+; Tx Prefix Type             = 0
+; Packet Type                = Fixed Length
+; Address-Length Position    = NA
+; Length Size                = 1-byte
+; Payload Bit Order          = Start from msb
+; Address Field              = Disable
+; Preamble Rx Size           = 2
+; Preamble Tx Size           = 8
+; Preamble Value             = 170
+; Preamble Unit              = 8-bit
+; Sync Size                  = 3-byte
+; Sync Format                = S2LP
+; Sync Value                 = 3003605
+; Sync Manchester            = Disable
+; Sync Value Selection       = Sync Value
+; Sync FEC Value             = 3003605
+; Sync Tolerance             = None
+; Address Detect Mode        = None
+; Address Split Mode         = NA
+; Address Size               = NA
+; Address Err Mask           = NA
+; Address Free               = NA
+; Dest Addr Value            = NA
+; Src Addr Value             = NA
+; Dest Addr Bit Mask         = NA
+; Src Addr Bit Mask          = NA
+; Sequence Num               = None
+; Sequence Num Match         = off
+; Sequence Num Mode          = NA
+; Sequence Num Value         = NA
+; FCS2                       = None
+; FCS2 Value                 = NA
+; Payload Length             = 32
+; CRC Options                = None
+; CRC Swap                   = NA
+; CRC Seed                   = NA
+; CRC Bit Invert             = NA
+; CRC Range                  = NA
+; CRC Polynomial             = NA
+; CRC Bit Order              = NA
+; CRC Refin                  = NA
+; CRC_Refout                 = NA
+; Frequency Hopping Mode     = Mode 2
+; Freq Hopping Space         = 10 kHz
+; Hopping Channels           = 10
+; CSMA Mode                  = Disable
+; CSMA RSSI Detection        = NA
+; Hopping Persist            = Disable
+; Hopping Intermediate State = TRFS
+; CSMA Sleep Timer Random    = NA
+; CSMA Rx Time               = NA
+; CSMA Sleep Time M          = NA
+; CSMA Sleep Time R          = NA
+; CSMA Persist               = NA
+; CSMA Detect Times          = NA
+; Tx Auto Hopping            = Disable
+; Rx Auto Hopping            = Disable
+; Auto Acknowledge           = off
+; Auto Resend                = off
+; Maximum Resend Times       = 1
+; RSSI Detect Mode           = always
+; LFOSC LFXO Sel             = LFOSC(32kHz)
+; LF Clock Out               = off
+; Dout Mute                  = disable
+; Dout Mute Sel              = NA
+; dout adjust mode           = disable
+; Dout Adjust Percentage     = NA
+; LBD Threshold              = 2.4 v
+; Antenna Diversity          = off
+; Antenna Switch Mode        = NA
+; Collision Detect           = off
+; Collision Step             = NA
+; RSSI Offset dB             = NA
+; RSSI Offset Sel            = autosel
+
+;---------------------------------------
+;  The following are the Register contents
+;---------------------------------------
+
+*****************************************************************************/
+
+#if (PRODUCT_FREQUENCY == CM2310A_433MHZ)
+/* [CMT page0] */
+const uint8_t g_cmt2310a_page0[CMT2310A_PAGE0_SIZE] = {
+    0x12,
+    0x08,
+    0x00,
+    0xAA,
+    0x04,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0xD5,
+    0xD4,
+    0x2D,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0xD5,
+    0xD4,
+    0x2D,
+    0x1F,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x2D,
+    0x00,
+    0x00,
+    0x00,
+    0x2D,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x45,
+    0x1F,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x08,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x1F,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0xE4,
+    0x20,
+    0x20,
+    0x20,
+    0x01,
+    0x00,
+    0xD0,
+    0xE0,
+    0xE2,
+    0x84,
+    0x30,
+    0x04,
+    0xD0,
+    0xE0,
+    0x80,
+    0x00,
+    0x41,
+    0x00,
+    0x01,
+    0x00,
+    0x02,
+    0x00,
+    0x00,
+    0x03,
+    0x04,
+};   
+
+/* [CMT page1] */
+const uint8_t g_cmt2310a_page1[CMT2310A_PAGE1_SIZE] = {
+    0x10,
+    0x06,
+    0x00,
+    0xFF,
+    0x00,
+    0xCD,
+    0x02,
+    0x28,
+    0x50,
+    0x87,
+    0x31,
+    0x5B,
+    0x08,
+    0x00,
+    0xFF,
+    0x00,
+    0x6C,
+    0x14,
+    0xAE,
+    0x07,
+    0xB4,
+    0xEA,
+    0x04,
+    0xE0,
+    0x20,
+    0x08,
+    0x05,
+    0x8D,
+    0x06,
+    0x00,
+    0xA0,
+    0x7F,
+    0x00,
+    0x18,
+    0x00,
+    0x00,
+    0x1F,
+    0xE4,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0xCA,
+    0x6C,
+    0x14,
+    0x2E,
+    0xD8,
+    0x6B,
+    0x00,
+    0x80,
+    0x0F,
+    0x64,
+    0x06,
+    0x02,
+    0xEA,
+    0x04,
+    0x00,
+    0x36,
+    0x01,
+    0x20,
+    0xC8,
+    0x63,
+    0xA1,
+    0x15,
+    0x34,
+    0x58,
+    0x40,
+    0xD2,
+    0x74,
+    0xF0,
+    0x0F,
+    0x01,
+    0x17,
+    0xE6,
+    0x54,
+    0x08,
+    0x39,
+    0xE2,
+    0x27,
+    0x0C,
+    0x01,
+    0xB4,
+    0x06,
+    0x0F,
+    0x0E,
+    0x4C,
+    0x00,
+    0x00,
+    0xF6,
+    0x00,
+    0x00,
+    0x00,
+    0x10,
+    0x81,
+    0x00,
+    0x00,
+    0x47,
+    0x12,
+    0x25,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+};   
+
+#endif
diff --git a/NSPE/WIFI_IOT/bsp/drivers/3_Ebyte_WirelessModule_Drivers/E48xMx/cmt2310a_868mhz.c b/NSPE/WIFI_IOT/bsp/drivers/3_Ebyte_WirelessModule_Drivers/E48xMx/cmt2310a_868mhz.c
new file mode 100755
index 0000000..8c186a0
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/3_Ebyte_WirelessModule_Drivers/E48xMx/cmt2310a_868mhz.c
@@ -0,0 +1,352 @@
+#include "radio_hal.h"
+#include "CMT2310A_reg.h"
+#include "CMT2310A_def.h"
+
+
+
+/****************************************************************************
+;---------------------------------------
+;  CMT2310A Configuration File
+;  Generated by CMOSTEK RFPDK 1.53_Update4
+;  2023.01.14 10:34
+;---------------------------------------
+; Mode                       = Advanced
+; Part Number                = CMT2310A
+; Frequency                  = 868.000 MHz
+; DC-DC                      = Off
+; Demodulation               = GFSK
+; Xtal Cap Load              = 2
+; Data Rate                  = 2.400 kbps
+; Deviation                  = 4.800 kHz
+; Tx Xtal Tol.               = 10 ppm
+; Rx Xtal Tol.               = 10 ppm
+; TRx Matching Network Type  = 20 dBm
+; Tx Power                   = +20 dBm
+; Gaussian BT                = 0.5
+; PA Ramp                    = On-Autosel Rampstep
+; PA Ramp Step               = NA
+; RF Performance             = NA
+; Output Drive Capability    = 0.5mA
+; Rx Duty-Cycle              = Off
+; Tx Duty-Cycle              = Off
+; Sleep Timer                = Off
+; Sleep Time                 = NA
+; Rx Timer                   = Off
+; Rx Time T1                 = NA
+; Rx Time T2                 = NA
+; Rx Exit State              = STBY
+; Tx Exit State              = STBY
+; TX Duty Cycle Persist      = Off
+; Packet Done Exit           = Off
+; TX Duty-Cycle Times        = 0
+; SLP Mode                   = Mode 0
+; RSSI Valid Source          = RSSI Compare
+; PJD Window                 = NA
+; RSSI Compare TH            = -127 dBm
+; CDR Type                   = Counting
+; AFC                        = autosel
+; FSK2 Data Map              = 0:F-low 1:F-high
+; FSK4 Data Map              = NA
+; FSK4 RX Data Map           = NA
+; CDR Type                   = Counting
+; CDR Range Sel FSK          = NA
+; Channel BW                 = autosel
+; Baseband BW FSK            = autosel
+; Data Mode                  = Packet
+; Packet Mode                = Normal
+; PiggyBacking               = Disable
+; Manchester                 = Disable
+; Manchester Type            = NA
+; Whitening                  = Disable
+; Whiten Type                = NA
+; Whiten Seed Type           = NA
+; Whiten Seed                = NA
+; FEC                        = Disable
+; FEC Type                   = NA
+; FEC Padding Code           = NA
+; crc err clear fifo         = Not Clear
+; Tx Packet Gap              = 32 symbol(s)
+; Tx Packet Number           = 1 packet(s)
+; Tx Prefix Type             = 0
+; Packet Type                = Fixed Length
+; Address-Length Position    = NA
+; Length Size                = 1-byte
+; Payload Bit Order          = Start from msb
+; Address Field              = Disable
+; Preamble Rx Size           = 2
+; Preamble Tx Size           = 8
+; Preamble Value             = 170
+; Preamble Unit              = 8-bit
+; Sync Size                  = 3-byte
+; Sync Format                = S2LP
+; Sync Value                 = 3003605
+; Sync Manchester            = Disable
+; Sync Value Selection       = Sync Value
+; Sync FEC Value             = 3003605
+; Sync Tolerance             = None
+; Address Detect Mode        = None
+; Address Split Mode         = NA
+; Address Size               = NA
+; Address Err Mask           = NA
+; Address Free               = NA
+; Dest Addr Value            = NA
+; Src Addr Value             = NA
+; Dest Addr Bit Mask         = NA
+; Src Addr Bit Mask          = NA
+; Sequence Num               = None
+; Sequence Num Match         = off
+; Sequence Num Mode          = NA
+; Sequence Num Value         = NA
+; FCS2                       = None
+; FCS2 Value                 = NA
+; Payload Length             = 32
+; CRC Options                = None
+; CRC Swap                   = NA
+; CRC Seed                   = NA
+; CRC Bit Invert             = NA
+; CRC Range                  = NA
+; CRC Polynomial             = NA
+; CRC Bit Order              = NA
+; CRC Refin                  = NA
+; CRC_Refout                 = NA
+; Frequency Hopping Mode     = Mode 2
+; Freq Hopping Space         = 10 kHz
+; Hopping Channels           = 10
+; CSMA Mode                  = Disable
+; CSMA RSSI Detection        = NA
+; Hopping Persist            = Disable
+; Hopping Intermediate State = TRFS
+; CSMA Sleep Timer Random    = NA
+; CSMA Rx Time               = NA
+; CSMA Sleep Time M          = NA
+; CSMA Sleep Time R          = NA
+; CSMA Persist               = NA
+; CSMA Detect Times          = NA
+; Tx Auto Hopping            = Disable
+; Rx Auto Hopping            = Disable
+; Auto Acknowledge           = off
+; Auto Resend                = off
+; Maximum Resend Times       = 1
+; RSSI Detect Mode           = always
+; LFOSC LFXO Sel             = LFOSC(32kHz)
+; LF Clock Out               = off
+; Dout Mute                  = disable
+; Dout Mute Sel              = NA
+; dout adjust mode           = disable
+; Dout Adjust Percentage     = NA
+; LBD Threshold              = 2.4 v
+; Antenna Diversity          = off
+; Antenna Switch Mode        = NA
+; Collision Detect           = off
+; Collision Step             = NA
+; RSSI Offset dB             = NA
+; RSSI Offset Sel            = autosel
+
+;---------------------------------------
+;  The following are the Register contents
+;---------------------------------------
+
+*****************************************************************************/
+
+#if ( PRODUCT_FREQUENCY == CM2310A_868MHZ)
+/* [CMT page0] */
+const uint8_t g_cmt2310a_page0[CMT2310A_PAGE0_SIZE] = {
+    0x12,
+    0x08,
+    0x00,
+    0xAA,
+    0x04,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0xD5,
+    0xD4,
+    0x2D,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0xD5,
+    0xD4,
+    0x2D,
+    0x1F,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x2D,
+    0x00,
+    0x00,
+    0x00,
+    0x2D,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x45,
+    0x1F,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x08,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x1F,
+    0x04,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0xE4,
+    0x20,
+    0x20,
+    0x20,
+    0x01,
+    0x00,
+    0xD0,
+    0xE0,
+    0xE2,
+    0x84,
+    0x30,
+    0x04,
+    0xD0,
+    0xE0,
+    0x80,
+    0x00,
+    0x41,
+    0x00,
+    0x01,
+    0x00,
+    0x02,
+    0x00,
+    0x00,
+    0x03,
+    0x04,
+};   
+
+/* [CMT page1] */
+const uint8_t g_cmt2310a_page1[CMT2310A_PAGE1_SIZE] = {
+    0x10,
+    0x06,
+    0x00,
+    0xFF,
+    0x00,
+    0xCD,
+    0x02,
+    0x20,
+    0x50,
+    0x87,
+    0x31,
+    0x5B,
+    0x08,
+    0x00,
+    0xFF,
+    0x00,
+    0x6C,
+    0x00,
+    0x00,
+    0x08,
+    0xB4,
+    0xEA,
+    0x04,
+    0xE0,
+    0x20,
+    0x08,
+    0x05,
+    0x47,
+    0x03,
+    0x00,
+    0x91,
+    0x7F,
+    0x00,
+    0x18,
+    0x00,
+    0x00,
+    0x1F,
+    0xE4,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0xC0,
+    0x6C,
+    0x00,
+    0x40,
+    0xD8,
+    0x6B,
+    0x00,
+    0xC0,
+    0x0F,
+    0x64,
+    0x06,
+    0x02,
+    0xEA,
+    0x04,
+    0x00,
+    0x36,
+    0x01,
+    0x20,
+    0xC8,
+    0x63,
+    0xA1,
+    0x15,
+    0x34,
+    0x58,
+    0x40,
+    0xC3,
+    0x74,
+    0xF0,
+    0x0F,
+    0x01,
+    0x17,
+    0xE6,
+    0x54,
+    0x08,
+    0x39,
+    0xE2,
+    0x14,
+    0x18,
+    0x01,
+    0xB4,
+    0x06,
+    0x0F,
+    0x07,
+    0x4C,
+    0x00,
+    0x00,
+    0xF6,
+    0x00,
+    0x00,
+    0x00,
+    0x10,
+    0x81,
+    0x00,
+    0x00,
+    0x47,
+    0x12,
+    0x25,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+};   
+
+#endif
\ No newline at end of file
diff --git a/NSPE/WIFI_IOT/bsp/drivers/3_Ebyte_WirelessModule_Drivers/E48xMx/cmt2310a_915mhz.c b/NSPE/WIFI_IOT/bsp/drivers/3_Ebyte_WirelessModule_Drivers/E48xMx/cmt2310a_915mhz.c
new file mode 100755
index 0000000..ba5559a
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/3_Ebyte_WirelessModule_Drivers/E48xMx/cmt2310a_915mhz.c
@@ -0,0 +1,352 @@
+#include "radio_hal.h"
+#include "CMT2310A_reg.h"
+#include "CMT2310A_def.h"
+
+
+
+/****************************************************************************
+;---------------------------------------
+;  CMT2310A Configuration File
+;  Generated by CMOSTEK RFPDK 1.53_Update4
+;  2023.01.14 10:34
+;---------------------------------------
+; Mode                       = Advanced
+; Part Number                = CMT2310A
+; Frequency                  = 915.000 MHz
+; DC-DC                      = Off
+; Demodulation               = GFSK
+; Xtal Cap Load              = 2
+; Data Rate                  = 2.400 kbps
+; Deviation                  = 4.800 kHz
+; Tx Xtal Tol.               = 10 ppm
+; Rx Xtal Tol.               = 10 ppm
+; TRx Matching Network Type  = 20 dBm
+; Tx Power                   = +20 dBm
+; Gaussian BT                = 0.5
+; PA Ramp                    = On-Autosel Rampstep
+; PA Ramp Step               = NA
+; RF Performance             = NA
+; Output Drive Capability    = 0.5mA
+; Rx Duty-Cycle              = Off
+; Tx Duty-Cycle              = Off
+; Sleep Timer                = Off
+; Sleep Time                 = NA
+; Rx Timer                   = Off
+; Rx Time T1                 = NA
+; Rx Time T2                 = NA
+; Rx Exit State              = STBY
+; Tx Exit State              = STBY
+; TX Duty Cycle Persist      = Off
+; Packet Done Exit           = Off
+; TX Duty-Cycle Times        = 0
+; SLP Mode                   = Mode 0
+; RSSI Valid Source          = RSSI Compare
+; PJD Window                 = NA
+; RSSI Compare TH            = -127 dBm
+; CDR Type                   = Counting
+; AFC                        = autosel
+; FSK2 Data Map              = 0:F-low 1:F-high
+; FSK4 Data Map              = NA
+; FSK4 RX Data Map           = NA
+; CDR Type                   = Counting
+; CDR Range Sel FSK          = NA
+; Channel BW                 = autosel
+; Baseband BW FSK            = autosel
+; Data Mode                  = Packet
+; Packet Mode                = Normal
+; PiggyBacking               = Disable
+; Manchester                 = Disable
+; Manchester Type            = NA
+; Whitening                  = Disable
+; Whiten Type                = NA
+; Whiten Seed Type           = NA
+; Whiten Seed                = NA
+; FEC                        = Disable
+; FEC Type                   = NA
+; FEC Padding Code           = NA
+; crc err clear fifo         = Not Clear
+; Tx Packet Gap              = 32 symbol(s)
+; Tx Packet Number           = 1 packet(s)
+; Tx Prefix Type             = 0
+; Packet Type                = Fixed Length
+; Address-Length Position    = NA
+; Length Size                = 1-byte
+; Payload Bit Order          = Start from msb
+; Address Field              = Disable
+; Preamble Rx Size           = 2
+; Preamble Tx Size           = 8
+; Preamble Value             = 170
+; Preamble Unit              = 8-bit
+; Sync Size                  = 3-byte
+; Sync Format                = S2LP
+; Sync Value                 = 3003605
+; Sync Manchester            = Disable
+; Sync Value Selection       = Sync Value
+; Sync FEC Value             = 3003605
+; Sync Tolerance             = None
+; Address Detect Mode        = None
+; Address Split Mode         = NA
+; Address Size               = NA
+; Address Err Mask           = NA
+; Address Free               = NA
+; Dest Addr Value            = NA
+; Src Addr Value             = NA
+; Dest Addr Bit Mask         = NA
+; Src Addr Bit Mask          = NA
+; Sequence Num               = None
+; Sequence Num Match         = off
+; Sequence Num Mode          = NA
+; Sequence Num Value         = NA
+; FCS2                       = None
+; FCS2 Value                 = NA
+; Payload Length             = 32
+; CRC Options                = None
+; CRC Swap                   = NA
+; CRC Seed                   = NA
+; CRC Bit Invert             = NA
+; CRC Range                  = NA
+; CRC Polynomial             = NA
+; CRC Bit Order              = NA
+; CRC Refin                  = NA
+; CRC_Refout                 = NA
+; Frequency Hopping Mode     = Mode 2
+; Freq Hopping Space         = 10 kHz
+; Hopping Channels           = 10
+; CSMA Mode                  = Disable
+; CSMA RSSI Detection        = NA
+; Hopping Persist            = Disable
+; Hopping Intermediate State = TRFS
+; CSMA Sleep Timer Random    = NA
+; CSMA Rx Time               = NA
+; CSMA Sleep Time M          = NA
+; CSMA Sleep Time R          = NA
+; CSMA Persist               = NA
+; CSMA Detect Times          = NA
+; Tx Auto Hopping            = Disable
+; Rx Auto Hopping            = Disable
+; Auto Acknowledge           = off
+; Auto Resend                = off
+; Maximum Resend Times       = 1
+; RSSI Detect Mode           = always
+; LFOSC LFXO Sel             = LFOSC(32kHz)
+; LF Clock Out               = off
+; Dout Mute                  = disable
+; Dout Mute Sel              = NA
+; dout adjust mode           = disable
+; Dout Adjust Percentage     = NA
+; LBD Threshold              = 2.4 v
+; Antenna Diversity          = off
+; Antenna Switch Mode        = NA
+; Collision Detect           = off
+; Collision Step             = NA
+; RSSI Offset dB             = NA
+; RSSI Offset Sel            = autosel
+
+;---------------------------------------
+;  The following are the Register contents
+;---------------------------------------
+
+*****************************************************************************/
+
+#if (PRODUCT_FREQUENCY == CM2310A_915MHZ)
+/* [CMT page0] */
+const uint8_t g_cmt2310a_page0[CMT2310A_PAGE0_SIZE] = {
+    0x12,
+    0x08,
+    0x00,
+    0xAA,
+    0x04,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0xD5,
+    0xD4,
+    0x2D,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0xD5,
+    0xD4,
+    0x2D,
+    0x1F,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x2D,
+    0x00,
+    0x00,
+    0x00,
+    0x2D,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x45,
+    0x1F,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x08,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x1F,
+    0x04,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0xE4,
+    0x20,
+    0x20,
+    0x20,
+    0x01,
+    0x00,
+    0xD0,
+    0xE0,
+    0xE2,
+    0x84,
+    0x30,
+    0x04,
+    0xD0,
+    0xE0,
+    0x80,
+    0x00,
+    0x41,
+    0x00,
+    0x01,
+    0x00,
+    0x02,
+    0x00,
+    0x00,
+    0x03,
+    0x04,
+};   
+
+/* [CMT page1] */
+const uint8_t g_cmt2310a_page1[CMT2310A_PAGE1_SIZE] = {
+    0x10,
+    0x06,
+    0x00,
+    0xFF,
+    0x00,
+    0xCD,
+    0x02,
+    0x20,
+    0x50,
+    0x87,
+    0x31,
+    0x5B,
+    0x08,
+    0x00,
+    0xFF,
+    0x00,
+    0x72,
+    0x00,
+    0x00,
+    0x06,
+    0xB4,
+    0xEA,
+    0x04,
+    0xE0,
+    0x20,
+    0x08,
+    0x05,
+    0x47,
+    0x03,
+    0x00,
+    0x88,
+    0x7F,
+    0x00,
+    0x18,
+    0x00,
+    0x00,
+    0x14,
+    0xE4,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0xC0,
+    0x72,
+    0x00,
+    0x40,
+    0xD6,
+    0x73,
+    0x00,
+    0xC0,
+    0x0F,
+    0x64,
+    0x06,
+    0x02,
+    0xEA,
+    0x04,
+    0x00,
+    0x36,
+    0x01,
+    0x20,
+    0xC8,
+    0x63,
+    0xA1,
+    0x15,
+    0x34,
+    0x58,
+    0x40,
+    0xC3,
+    0x74,
+    0xF0,
+    0x0F,
+    0x01,
+    0x17,
+    0xE6,
+    0x54,
+    0x08,
+    0x39,
+    0xE2,
+    0x14,
+    0x18,
+    0x01,
+    0xB4,
+    0x06,
+    0x0F,
+    0x07,
+    0x4C,
+    0x00,
+    0x00,
+    0xF6,
+    0x00,
+    0x00,
+    0x00,
+    0x10,
+    0x81,
+    0x00,
+    0x00,
+    0x47,
+    0x12,
+    0x25,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+};   
+
+#endif
\ No newline at end of file
diff --git a/NSPE/WIFI_IOT/bsp/drivers/3_Ebyte_WirelessModule_Drivers/E48xMx/ebyte_e48x.c b/NSPE/WIFI_IOT/bsp/drivers/3_Ebyte_WirelessModule_Drivers/E48xMx/ebyte_e48x.c
new file mode 100755
index 0000000..090b332
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/3_Ebyte_WirelessModule_Drivers/E48xMx/ebyte_e48x.c
@@ -0,0 +1,91 @@
+#include "ebyte_e48x.h"
+#include "ebyte_callback.h"
+
+
+/* ¸¨Öúʶ±ðÄ£¿éÀà±ð */
+#define EBYTE_E48_NAME_TYPE 0x00000048
+
+/* ¸¨Öúʶ±ðÄ£¿éƵ¶Î */
+#if defined(EBYTE_E48_433M20S)
+
+  #define EBYTE_E48_FREQUENCY_TYPE 0x00000433 
+
+#elif defined(EBYTE_E48_900M20S)
+
+  #define EBYTE_E48_FREQUENCY_TYPE 0x00000900 
+
+#endif 
+
+/* ¸¨Öúʶ±ðÇý¶¯³ÌÐò°æ±¾ºÅ */
+#define EBYTE_E48_PROGRAM_TYPE 0x10 
+
+#include "board.h"
+
+uint8_t rf_rxbuffer[200];
+uint8_t rf_rxsize;
+uint8_t radio_rece_data_flag;
+
+
+void Ebyte_E48x_Init( void )
+{
+  vRadioCheckLink();
+  vRadioInit();
+}
+
+void Ebyte_E48x_SendPayload( uint8_t *payload, uint8_t size, uint32_t timeout )
+{
+    vRadioTransmit( payload, size );
+}
+
+
+void Ebyte_E48x_SetRx( uint32_t timeout )
+{
+  vRadioReceive();
+}
+
+void Ebyte_E48x_SetSleep( uint8_t  cmd )
+{
+  return;
+}
+
+
+void Ebyte_E48x_IntOrPollTask( void )
+{
+  radio_rece_data_flag = GPIO_ReadInputDataBit( BSP_GPIO_PORT_E48_GP4 , BSP_GPIO_PIN_E48_GP4);
+  /* ÓнÓÊÕÊý¾Ý */
+  if( radio_rece_data_flag != RESET )
+  {
+      vRadioGetPacket(rf_rxbuffer,&rf_rxsize);
+      Ebyte_Port_ReceiveCallback(0x0002,rf_rxbuffer,rf_rxsize);
+  }
+}
+
+
+void Ebyte_E48x_InterruptTrigger( void )
+{
+
+
+}
+
+/* !
+ * @brief »ñÈ¡Ä£¿éÀàÐÍ
+ * 
+ * @return 32λµÄ±àÂë 
+ * @note ¸ß16λ´ú±íÄ£¿éÃû ÀýÈç0x0220 ´ú±íE22Ä£¿é
+ *       µÍ16λ´ú±íƵ¶ÎÃû ÀýÈç0x0400 ´ú±í400Ƶ¶Î
+ */
+uint32_t Ebyte_E48x_GetName(void)
+{
+  return  (  ( (uint32_t)EBYTE_E48_NAME_TYPE << 16 ) | (uint32_t)EBYTE_E48_FREQUENCY_TYPE);
+}
+
+/* !
+ * @brief »ñÈ¡Ä£¿é³ÌÐò°æ±¾
+ * 
+ * @return 8λµÄ±àÂë 
+ * @note ÀýÈç0x10 ´ú±íV1.0
+ */
+uint8_t Ebyte_E48x_GetDriverVersion(void)
+{
+  return  EBYTE_E48_PROGRAM_TYPE;
+}
\ No newline at end of file
diff --git a/NSPE/WIFI_IOT/bsp/drivers/3_Ebyte_WirelessModule_Drivers/E48xMx/ebyte_e48x.h b/NSPE/WIFI_IOT/bsp/drivers/3_Ebyte_WirelessModule_Drivers/E48xMx/ebyte_e48x.h
new file mode 100755
index 0000000..265c5b2
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/3_Ebyte_WirelessModule_Drivers/E48xMx/ebyte_e48x.h
@@ -0,0 +1,23 @@
+#ifndef _EBYTE_E48X_H_
+#define _EBYTE_E48X_H_
+
+
+#include "radio.h"
+#include "radio_hal.h"
+#include "radio_mac.h"
+#include "radio_phy.h"
+#include "radio_spi.h"
+
+#include "ebyte_conf.h"
+
+void Ebyte_E48x_Init( void );
+void Ebyte_E48x_SendPayload( uint8_t *payload, uint8_t size, uint32_t timeout );
+void Ebyte_E48x_SetRx( uint32_t timeout );
+void Ebyte_E48x_SetSleep( uint8_t  cmd );
+void Ebyte_E48x_IntOrPollTask( void );
+void Ebyte_E48x_InterruptTrigger( void );
+uint32_t Ebyte_E48x_GetName(void);
+uint8_t Ebyte_E48x_GetDriverVersion(void);
+
+
+#endif
\ No newline at end of file
diff --git a/NSPE/WIFI_IOT/bsp/drivers/3_Ebyte_WirelessModule_Drivers/E48xMx/radio.c b/NSPE/WIFI_IOT/bsp/drivers/3_Ebyte_WirelessModule_Drivers/E48xMx/radio.c
new file mode 100755
index 0000000..1b0c271
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/3_Ebyte_WirelessModule_Drivers/E48xMx/radio.c
@@ -0,0 +1,404 @@
+#include "radio.h"
+#include "board.h"
+CMT2310A_CFG    g_radio;                    //
+
+uint8_t g_reg_read_buf[128];
+uint32_t g_chip_id = 0;
+
+//Éú³ÉµÄÅäÖÃÎļþµÄ270~276ÐУ¬¶ÔÓ¦µÄ7¸ö¹¦ÂÊÅäÖüĴæÆ÷
+const uint8_t cmt2310a_power[55][7] = {
+  {0x20,0x1B,0x00,0x3A,0x00,0x00,0x01 }, /* cmt2310a_params13-0.h */
+  {0x25,0x1B,0x00,0x3A,0x00,0x00,0x01 }, /* cmt2310a_params13-1.h */
+  {0x68,0x1B,0x00,0x3A,0x00,0x00,0x05 }, /* cmt2310a_params13-10.h */
+  {0x36,0x2D,0x00,0x22,0x00,0x00,0x07 }, /* cmt2310a_params13-11.h */
+  {0x40,0x2D,0x00,0x22,0x00,0x00,0x08 }, /* cmt2310a_params13-12.h */
+  {0x4D,0x2D,0x00,0x22,0x00,0x00,0x0C }, /* cmt2310a_params13-13.h */
+  {0x2A,0x1B,0x00,0x3A,0x00,0x00,0x01 }, /* cmt2310a_params13-2.h */
+  {0x30,0x1B,0x00,0x3A,0x00,0x00,0x01 }, /* cmt2310a_params13-3.h */
+  {0x35,0x1B,0x00,0x3A,0x00,0x00,0x01 }, /* cmt2310a_params13-4.h */
+  {0x3A,0x1B,0x00,0x3A,0x00,0x00,0x02 }, /* cmt2310a_params13-5.h */
+  {0x41,0x1B,0x00,0x3A,0x00,0x00,0x02 }, /* cmt2310a_params13-6.h */
+  {0x48,0x1B,0x00,0x3A,0x00,0x00,0x02 }, /* cmt2310a_params13-7.h */
+  {0x50,0x1B,0x00,0x3A,0x00,0x00,0x03 }, /* cmt2310a_params13-8.h */
+  {0x5B,0x1B,0x00,0x3A,0x00,0x00,0x04 }, /* cmt2310a_params13-9.h */
+  {0x1C,0x1B,0x00,0x3A,0x00,0x00,0x01 }, /* cmt2310a_params13-N1.h */
+  {0x19,0x12,0x00,0x57,0x00,0x00,0x01 }, /* cmt2310a_params13-N10.h */
+  {0x19,0x1B,0x00,0x3A,0x00,0x00,0x01 }, /* cmt2310a_params13-N2.h */
+  {0x16,0x1B,0x00,0x3A,0x00,0x00,0x01 }, /* cmt2310a_params13-N3.h */
+  {0x35,0x12,0x00,0x57,0x00,0x00,0x02 }, /* cmt2310a_params13-N4.h */
+  {0x2F,0x12,0x00,0x57,0x00,0x00,0x02 }, /* cmt2310a_params13-N5.h */
+  {0x29,0x12,0x00,0x57,0x00,0x00,0x02 }, /* cmt2310a_params13-N6.h */
+  {0x25,0x12,0x00,0x57,0x00,0x00,0x01 }, /* cmt2310a_params13-N7.h */
+  {0x20,0x12,0x00,0x57,0x00,0x00,0x01 }, /* cmt2310a_params13-N8.h */
+  {0x1C,0x12,0x00,0x57,0x00,0x00,0x01 }, /* cmt2310a_params13-N9.h */
+  {0x2A,0x1F,0x00,0x32,0x00,0x00,0x01 }, /* cmt2310a_params20-0.h */
+  {0x2F,0x1F,0x00,0x32,0x00,0x00,0x01 }, /* cmt2310a_params20-1.h */
+  {0x39,0x3F,0x00,0x18,0x00,0x00,0x06 }, /* cmt2310a_params20-10.h */
+  {0x40,0x3F,0x00,0x18,0x00,0x00,0x07 }, /* cmt2310a_params20-11.h */
+  {0x49,0x3F,0x00,0x18,0x00,0x00,0x08 }, /* cmt2310a_params20-12.h */
+  {0x53,0x3F,0x00,0x18,0x00,0x00,0x0A }, /* cmt2310a_params20-13.h */
+  {0x5F,0x3F,0x00,0x18,0x00,0x00,0x0C }, /* cmt2310a_params20-14.h */
+  {0x70,0x3F,0x00,0x18,0x00,0x00,0x0F }, /* cmt2310a_params20-15.h */
+  {0x85,0x3F,0x00,0x18,0x00,0x00,0x14 }, /* cmt2310a_params20-16.h */
+  {0x50,0x7F,0x00,0x18,0x00,0x00,0x12 }, /* cmt2310a_params20-17.h */
+  {0x69,0x7F,0x00,0x18,0x00,0x00,0x18 }, /* cmt2310a_params20-18.h */
+  {0x80,0x7F,0x00,0x18,0x00,0x00,0x1C }, /* cmt2310a_params20-19.h */
+  {0x35,0x1F,0x00,0x32,0x00,0x00,0x01 }, /* cmt2310a_params20-2.h */
+  {0xA0,0x7F,0x00,0x18,0x00,0x00,0x1F }, /* cmt2310a_params20-20.h */
+  {0x3C,0x1F,0x00,0x32,0x00,0x00,0x01 }, /* cmt2310a_params20-3.h */
+  {0x42,0x1F,0x00,0x32,0x00,0x00,0x01 }, /* cmt2310a_params20-4.h */
+  {0x49,0x1F,0x00,0x32,0x00,0x00,0x02 }, /* cmt2310a_params20-5.h */
+  {0x54,0x1F,0x00,0x32,0x00,0x00,0x02 }, /* cmt2310a_params20-6.h */
+  {0x5F,0x1F,0x00,0x32,0x00,0x00,0x03 }, /* cmt2310a_params20-7.h */
+  {0x6B,0x1F,0x00,0x32,0x00,0x00,0x03 }, /* cmt2310a_params20-8.h */
+  {0x33,0x3F,0x00,0x18,0x00,0x00,0x05 }, /* cmt2310a_params20-9.h */
+  {0x25,0x1F,0x00,0x32,0x00,0x00,0x01 }, /* cmt2310a_params20-N1.h */
+  {0x1A,0x16,0x00,0x47,0x00,0x00,0x01 }, /* cmt2310a_params20-N10.h */
+  {0x21,0x1F,0x00,0x32,0x00,0x00,0x01 }, /* cmt2310a_params20-N2.h */
+  {0x1D,0x1F,0x00,0x32,0x00,0x00,0x01 }, /* cmt2310a_params20-N3.h */
+  {0x36,0x16,0x00,0x47,0x00,0x00,0x01 }, /* cmt2310a_params20-N4.h */
+  {0x30,0x16,0x00,0x47,0x00,0x00,0x01 }, /* cmt2310a_params20-N5.h */
+  {0x2A,0x16,0x00,0x47,0x00,0x00,0x01 }, /* cmt2310a_params20-N6.h */
+  {0x25,0x16,0x00,0x47,0x00,0x00,0x01 }, /* cmt2310a_params20-N7.h */
+  {0x21,0x16,0x00,0x47,0x00,0x00,0x01 }, /* cmt2310a_params20-N8.h */
+  {0x1D,0x16,0x00,0x47,0x00,0x00,0x01 } /* cmt2310a_params20-N9.h */
+};
+/******************************
+**Name:  vRadioInit
+**Func:  Radio config spi & reset
+**Input: None
+*Output: None
+********************************/
+void vRadioInit( void )
+{
+    byte fw_rev;	
+    vRadioSoftReset();
+    vRadioConfigPageReg( 0, g_cmt2310a_page0, CMT2310A_PAGE0_SIZE );    //config page 0
+    vRadioConfigPageReg( 1, g_cmt2310a_page1, CMT2310A_PAGE1_SIZE );    //config page 1
+    vRadioSetNirq( CMT2310A_nIRQ_TCXO ); //for TCXO need cofig as nIRQ pin at first
+    vRadioTcxoDrvSel( 0 );              //drive power
+    
+    fw_rev = (byte)g_chip_id;			//dealwith Xtal
+    switch(fw_rev)
+    {
+      case 0xC0: 
+        vRadioXoWaitCfg(RADIO_CGU_DIV4); 
+         break;
+      default:
+        break;
+    }	
+    
+    vRadioPowerUpBoot();
+    delay1ms( 10 );
+    bRadioGoStandby();
+    delay1ms( 2 );
+    bRadioApiCommand( 0x02 );           //
+    delay1ms( 10 );
+    bRadioApiCommand( 0x01 );           //IR Calibration, need some times
+    vRadioCapLoad( 2 );                 //Xo Cap
+    //GPIOn default setting
+    vRadioSetGpio0( CMT2310A_GPIO0_INT3 );
+    vRadioSetGpio1( CMT2310A_GPIO1_INT2 );
+    vRadioSetGpio2( CMT2310A_GPIO2_DCLK );
+    vRadioSetGpio3( CMT2310A_GPIO3_DOUT );
+    vRadioSetGpio4( CMT2310A_GPIO4_INT1 );
+    vRadioSetGpio5( CMT2310A_GPIO5_nRST );
+    //INT1 = RX_FIFO_WBYTE,   INT2 = PKT_DONE
+    vRadioSetInt1Sel( INT_SRC_RX_FIFO_WBYTE );
+    vRadioSetInt2Sel( INT_SRC_PKT_DONE );
+    vRadioSetInt1Polar( FALSE );
+    vRadioSetInt2Polar( FALSE );
+    vRadioSetInt3Polar( FALSE );
+    //interrupt source enable config
+    g_radio.int_src_en._BITS.PKT_DONE_EN        = 1;
+    g_radio.int_src_en._BITS.CRC_PASS_EN        = 1;
+    g_radio.int_src_en._BITS.ADDR_PASS_EN       = 0;
+    g_radio.int_src_en._BITS.SYNC_PASS_EN       = 1;
+    g_radio.int_src_en._BITS.PREAM_PASS_EN      = 1;
+    g_radio.int_src_en._BITS.TX_DONE_EN         = 1;
+    g_radio.int_src_en._BITS.RX_TOUT_EN         = 1;
+    g_radio.int_src_en._BITS.LD_STOP_EN         = 0;
+    g_radio.int_src_en._BITS.LBD_STOP_EN        = 0;
+    g_radio.int_src_en._BITS.LBD_STAT_EN        = 0;
+    g_radio.int_src_en._BITS.PKT_ERR_EN         = 0;
+    g_radio.int_src_en._BITS.RSSI_COLL_EN       = 0;
+    g_radio.int_src_en._BITS.OP_CMD_FAILED_EN   = 0;
+    g_radio.int_src_en._BITS.RSSI_PJD_EN        = 0;
+    g_radio.int_src_en._BITS.SEQ_MATCH_EN       = 0;
+    g_radio.int_src_en._BITS.NACK_RECV_EN       = 0;
+    g_radio.int_src_en._BITS.TX_RESEND_DONE_EN  = 0;
+    g_radio.int_src_en._BITS.ACK_RECV_FAILED_EN = 0;
+    g_radio.int_src_en._BITS.TX_DC_DONE_EN      = 0;
+    g_radio.int_src_en._BITS.CSMA_DONE_EN       = 0;
+    g_radio.int_src_en._BITS.CCA_STAT_EN        = 0;
+    g_radio.int_src_en._BITS.API_DONE_EN        = 0;
+    g_radio.int_src_en._BITS.TX_FIFO_TH_EN      = 1;
+    g_radio.int_src_en._BITS.TX_FIFO_NMTY_EN    = 1;
+    g_radio.int_src_en._BITS.TX_FIFO_FULL_EN    = 1;
+    g_radio.int_src_en._BITS.RX_FIFO_OVF_EN     = 1;
+    g_radio.int_src_en._BITS.RX_FIFO_TH_EN      = 1;
+    g_radio.int_src_en._BITS.RX_FIFO_NMTY_EN    = 1;
+    g_radio.int_src_en._BITS.RX_FIFO_FULL_EN    = 1;
+    vRadioInterruptSoucreCfg( &g_radio.int_src_en );
+    //packet preamble config
+    g_radio.preamble_cfg.PREAM_LENG_UNIT = 0;                   //8-bits mode
+    g_radio.preamble_cfg.PREAM_VALUE     = 0xAA;                //
+    g_radio.preamble_cfg.RX_PREAM_SIZE   = 2;                   //
+    g_radio.preamble_cfg.TX_PREAM_SIZE   = 16;
+    vRadioCfgPreamble( &g_radio.preamble_cfg );
+    //packet syncword config
+    g_radio.sync_cfg.SYN_CFG_u._BITS.SYNC_MAN_EN   = 0;         //disable syncword manchester coding
+    g_radio.sync_cfg.SYN_CFG_u._BITS.SYNC_SIZE     = 2;         //enable 3 bytes for syncword
+    g_radio.sync_cfg.SYN_CFG_u._BITS.SYNC_TOL      = 0;
+    g_radio.sync_cfg.SYN_CFG_u._BITS.SYNC_MODE_SEL = 0;         //normal packet
+    g_radio.sync_cfg.SYNC_VALUE[0] = 0xAA;
+    g_radio.sync_cfg.SYNC_VALUE[1] = 0x2D;
+    g_radio.sync_cfg.SYNC_VALUE[2] = 0xD4;
+    g_radio.sync_cfg.SYNC_VALUE_SEL = 0;                        //select SYN_VAL
+    vRadioCfgSyncWord( &g_radio.sync_cfg );
+    //packet node address config
+    g_radio.addr_cfg.ADDR_CFG_u._BITS.ADDR_DET_MODE = 0;        //disable Node Address
+    vRadioCfgNodeAddr( &g_radio.addr_cfg );
+    //packet crc config
+    g_radio.crc_cfg.CRC_CFG_u._BITS.CRC_EN         = 1;         //enable crc
+    g_radio.crc_cfg.CRC_CFG_u._BITS.CRC_BIT_ORDER  = 0;
+    g_radio.crc_cfg.CRC_CFG_u._BITS.CRC_REFIN      = 0;
+    g_radio.crc_cfg.CRC_CFG_u._BITS.CRC_RANGE      = 0;
+    g_radio.crc_cfg.CRC_CFG_u._BITS.CRC_BIT_INV    = 0;
+    g_radio.crc_cfg.CRC_CFG_u._BITS.CRC_BYTE_SWAP  = 0;
+    g_radio.crc_cfg.CRC_CFG_u._BITS.CRC_REFOUT     = 0;         //whole payload
+    g_radio.crc_cfg.CRC_CFG_u._BITS.CRCERR_CLR_FIFO_EN  = 0;    //note: need ative FIFO_AUTO_CLR_RX_EN = 1 or call vRadioFifoAutoClearGoRx(1)
+    g_radio.crc_cfg.CRC_CFG_u._BITS.CRC_SIZE       = 1;         //crc-16 mode
+    g_radio.crc_cfg.CRC_POLY_u.u32_POLY = 0x10210000;
+    g_radio.crc_cfg.CRC_SEED_u.u32_SEED = 0x00000000;
+    vRadioCfgCrc( &g_radio.crc_cfg );
+    //packet coding format
+    g_radio.coding_format_cfg.CODING_FORMAT_CFG_u._BITS.MANCH_EN          = 0;
+    g_radio.coding_format_cfg.CODING_FORMAT_CFG_u._BITS.MANCH_TYPE        = 0;
+    g_radio.coding_format_cfg.CODING_FORMAT_CFG_u._BITS.WHITEN_EN         = 0;
+    g_radio.coding_format_cfg.CODING_FORMAT_CFG_u._BITS.WHITEN_TYPE       = 0;
+    g_radio.coding_format_cfg.CODING_FORMAT_CFG_u._BITS.WHITEN_SEED_TYP   = 0;
+    g_radio.coding_format_cfg.CODING_FORMAT_CFG_u._BITS.FEC_EN            = 0;
+    g_radio.coding_format_cfg.CODING_FORMAT_CFG_u._BITS.FEC_RSC_NRNSC_SEL = 0;
+    g_radio.coding_format_cfg.CODING_FORMAT_CFG_u._BITS.FEC_TICC          = 0;
+    g_radio.coding_format_cfg.WHITEN_SEED  = 0x01FF;
+    g_radio.coding_format_cfg.FEC_PAD_CODE = 0;
+    vRadioCfgCodeFormat( &g_radio.coding_format_cfg );
+    //packet frame format
+    g_radio.frame_cfg.DATA_MODE = 2;                                //0=direct mode,    2=packet mode
+    g_radio.frame_cfg.FRAME_CFG1_u._BITS.PKT_TYPE          = 1;     //0=fixd-length packet mode 1=¿É±ä³¤
+    g_radio.frame_cfg.FRAME_CFG1_u._BITS.PAYLOAD_BIT_ORDER = 0;     //msb first 
+    g_radio.frame_cfg.FRAME_CFG1_u._BITS.ADDR_LEN_CONF     = 0;
+    g_radio.frame_cfg.FRAME_CFG1_u._BITS.PAGGYBACKING_EN   = 0;
+    g_radio.frame_cfg.FRAME_CFG1_u._BITS.LENGTH_SIZE       = 0;
+    g_radio.frame_cfg.FRAME_CFG1_u._BITS.INTERLEAVE_EN     = 0;     //note: when FEC enable, INTERLEAVE_EN should be set 1
+    g_radio.frame_cfg.FRAME_CFG2_u._BITS.TX_PREFIX_TYPE    = TX_PREFIX_SEL_PREAMBLE;        //transmit preamble
+    g_radio.frame_cfg.FRAME_CFG2_u._BITS.SEQNUM_EN         = 0;
+    g_radio.frame_cfg.FRAME_CFG2_u._BITS.SEQNUM_AUTO_INC   = 0;
+    g_radio.frame_cfg.FRAME_CFG2_u._BITS.SEQNUM_SIZE       = 0;
+    g_radio.frame_cfg.FRAME_CFG2_u._BITS.SEQNUM_MACH_EN    = 0;
+    g_radio.frame_cfg.FRAME_CFG2_u._BITS.FCS2_EN           = 0;
+    g_radio.frame_cfg.TX_PKT_NUM     = 0;
+    g_radio.frame_cfg.TX_PKT_GAP     = 0;
+    g_radio.frame_cfg.FCS2_TX_IN     = 0;
+    g_radio.frame_cfg.PAYLOAD_LENGTH = UHF_LEN;
+    vRadioCfgFrameFormat( &g_radio.frame_cfg );
+    //Run Mode Config
+    g_radio.word_mode_cfg.WORK_MODE_CFG1_u._BITS.TX_DC_EN          = 0;
+    g_radio.word_mode_cfg.WORK_MODE_CFG1_u._BITS.TX_ACK_EN         = 0;
+    g_radio.word_mode_cfg.WORK_MODE_CFG1_u._BITS.TX_DC_PERSIST_EN  = 0;
+    g_radio.word_mode_cfg.WORK_MODE_CFG1_u._BITS.TX_AUTO_HOP_EN    = 0;
+    g_radio.word_mode_cfg.WORK_MODE_CFG1_u._BITS.TX_EXIT_STATE     = EXIT_TO_READY;
+    g_radio.word_mode_cfg.WORK_MODE_CFG2_u._BITS.RX_DC_EN          = 0;
+    g_radio.word_mode_cfg.WORK_MODE_CFG2_u._BITS.RX_AUTO_HOP_EN    = 0;
+    g_radio.word_mode_cfg.WORK_MODE_CFG2_u._BITS.RX_ACK_EN         = 0;
+    g_radio.word_mode_cfg.WORK_MODE_CFG2_u._BITS.RX_TIMER_EN       = 0;
+    g_radio.word_mode_cfg.WORK_MODE_CFG2_u._BITS.RX_EXIT_STATE     = EXIT_TO_READY;
+    g_radio.word_mode_cfg.WORK_MODE_CFG2_u._BITS.CSMA_EN           = 0;
+    g_radio.word_mode_cfg.WORK_MODE_CFG3_u._BITS.PKT_DONE_EXIT_EN  = 0;         //depend on RX_EXIT_STATE
+    g_radio.word_mode_cfg.WORK_MODE_CFG3_u._BITS.RX_HOP_SLP_MODE   = 0;
+    g_radio.word_mode_cfg.WORK_MODE_CFG3_u._BITS.SLP_MODE          = 0;
+    g_radio.word_mode_cfg.WORK_MODE_CFG4_u._BITS.LFCLK_OUT_EN      = 0;
+    g_radio.word_mode_cfg.WORK_MODE_CFG4_u._BITS.LFCLK_SEL         = 0;
+    g_radio.word_mode_cfg.WORK_MODE_CFG4_u._BITS.SLEEP_TIMER_EN    = 0;
+    g_radio.word_mode_cfg.WORK_MODE_CFG4_u._BITS.TIMER_RAND_MODE   = 0;
+    g_radio.word_mode_cfg.WORK_MODE_CFG5_u._BITS.CSMA_CCA_MODE     = 0;
+    g_radio.word_mode_cfg.WORK_MODE_CFG5_u._BITS.CSMA_CCA_WIN_SEL  = 0;
+    g_radio.word_mode_cfg.WORK_MODE_CFG5_u._BITS.CSMA_CCA_INT_SEL  = 0;
+    g_radio.word_mode_cfg.WORK_MODE_CFG5_u._BITS.CSMA_PERSIST_EN   = 0;
+    
+    g_radio.word_mode_cfg.WORK_MODE_CFG6_u._BITS.FREQ_HOP_MANU_EN  = 1;//ʹÄÜÊÖ¶¯¿ìËÙÌøƵ£¬²»Ê¹ÄÜÊÖ¶¯ÌøƵÎÞ·¨Ê¹ÓÃ
+    
+    g_radio.word_mode_cfg.FREQ_CHANL_NANU  = 92;//ÊÖ¶¯ÌøƵÐŵÀ0~255
+    g_radio.word_mode_cfg.FREQ_DONE_TIMES  = 0;
+    g_radio.word_mode_cfg.FREQ_SPACE       = 250;//ÌøƵÐŵÀ¼ä¸ô0~255 KHz
+    g_radio.word_mode_cfg.FREQ_TIMES       = 0;
+    g_radio.word_mode_cfg.SLEEP_TIMER_M    = 0;
+    g_radio.word_mode_cfg.SLEEP_TIMER_R    = 0;
+    g_radio.word_mode_cfg.RX_TIMER_T1_M    = 0;                 //M*2^(R+1)*5us=M*2^R*10us,
+    g_radio.word_mode_cfg.RX_TIMER_T1_R    = 0;                 //R=7, unit=0.64ms
+    g_radio.word_mode_cfg.RX_TIMER_T2_M    = 0;
+    g_radio.word_mode_cfg.RX_TIMER_T2_R    = 0;
+    g_radio.word_mode_cfg.RX_TIMER_CSMA_M  = 0;
+    g_radio.word_mode_cfg.RX_TIMER_CSMA_R  = 0;
+    g_radio.word_mode_cfg.TX_DC_TIMES      = 0;
+    g_radio.word_mode_cfg.TX_RS_TIMES      = 0;
+    g_radio.word_mode_cfg.CSMA_TIMES       = 0;
+    g_radio.word_mode_cfg.SLEEP_TIMER_CSMA_M = 0;
+    g_radio.word_mode_cfg.SLEEP_TIMER_CSMA_R = 0;
+    vRadioCfgWorkMode( &g_radio.word_mode_cfg );
+    //FIFO Init
+    vRadioFifoMerge( FALSE );
+    vRadioSetFifoTH( 30 );
+    vRadioClearRxFifo();                                        //reset & clear fifo
+    vRadioClearTxFifo();
+    vRadioFifoAutoClearGoRx( TRUE );                            //when crc error, need to auto clear fifo, should enable
+    vRadioRssiUpdateSel( CMT2310A_RSSI_UPDATE_ALWAYS );
+    vRadioSetAntSwitch( FALSE, FALSE );                         //
+    vRadioDcdcCfg( TRUE );                                      //dc-dc off
+}
+
+void vRadioClearInterrupt( void )
+{
+    vRadioInterruptSoucreFlag( &g_radio.int_src_flag );
+    g_radio.int_src_clear._BITS.SLEEP_TMO_CLR = g_radio.int_src_flag._BITS.SLEEP_TMO_FLG;
+    g_radio.int_src_clear._BITS.RX_TMO_CLR    = g_radio.int_src_flag._BITS.RX_TMO_FLG;
+    g_radio.int_src_clear._BITS.TX_DONE_CLR   = g_radio.int_src_flag._BITS.TX_DONE_FLG;
+    g_radio.int_src_clear._BITS.PKT_DONE_CLR  = g_radio.int_src_flag._BITS.PKT_DONE_FLG;
+    g_radio.int_src_clear._BITS.CRC_PASS_CLR  = g_radio.int_src_flag._BITS.CRC_PASS_FLG;
+    g_radio.int_src_clear._BITS.ADDR_PASS_CLR = g_radio.int_src_flag._BITS.ADDR_PASS_FLG;
+    g_radio.int_src_clear._BITS.SYNC_PASS_CLR = g_radio.int_src_flag._BITS.SYNC_PASS_FLG | g_radio.int_src_flag._BITS.SYNC1_PASS_FLG;
+    g_radio.int_src_clear._BITS.PREAM_PASS_CLR = g_radio.int_src_flag._BITS.PREAM_PASS_FLG;
+    g_radio.int_src_clear._BITS.LBD_STAT_CLR      = g_radio.int_src_flag._BITS.LBD_STATUS_FLG;
+    g_radio.int_src_clear._BITS.PKT_ERR_CLR       = g_radio.int_src_flag._BITS.PKT_ERR_FLG;
+    g_radio.int_src_clear._BITS.RSSI_COLL_CLR     = g_radio.int_src_flag._BITS.RSSI_COLL_FLG;
+    g_radio.int_src_clear._BITS.OP_CMD_FAILED_CLR = g_radio.int_src_flag._BITS.OP_CMD_FAILED_FLG;
+    g_radio.int_src_clear._BITS.ANT_LOCK_CLR      = g_radio.int_src_flag._BITS.ANT_LOCK_FLG;
+    g_radio.int_src_clear._BITS.SEQ_MATCH_CLR       = g_radio.int_src_flag._BITS.SEQ_MATCH_FLG;
+    g_radio.int_src_clear._BITS.NACK_RECV_CLR       = g_radio.int_src_flag._BITS.NACK_RECV_FLG;
+    g_radio.int_src_clear._BITS.TX_RESEND_DONE_CLR  = g_radio.int_src_flag._BITS.TX_RESEND_DONE_FLG ;
+    g_radio.int_src_clear._BITS.ACK_RECV_FAILED_CLR = g_radio.int_src_flag._BITS.ACK_RECV_FAILED_FLG;
+    g_radio.int_src_clear._BITS.TX_DC_DONE_CLR      = g_radio.int_src_flag._BITS.TX_DC_DONE_FLG;
+    g_radio.int_src_clear._BITS.CSMA_DONE_CLR       = g_radio.int_src_flag._BITS.CSMA_DONE_FLG;
+    g_radio.int_src_clear._BITS.CCA_STATUS_CLR      = g_radio.int_src_flag._BITS.CCA_STATUS_FLG;
+    g_radio.int_src_clear._BITS.API_DONE_CLR        = g_radio.int_src_flag._BITS.API_DONE_FLG;
+    vRadioInterruptSoucreClear( &g_radio.int_src_clear );
+}
+
+void vRadioReadAllStatus( void )
+{
+    bRadioGetState();                                   //read work status
+    vRadioFifoGetStatus( &g_radio.fifo_status_flag );   //read fifo status
+    vRadioInterruptSoucreFlag( &g_radio.int_src_flag ); //read interrupt flag
+    bRadioReadReg( CMT2310A_CTL_REG_04 );               //get GPIO1/GPIO0 selection
+    bRadioReadReg( CMT2310A_CTL_REG_05 );               //get GPIO3/GPIO2 selection
+    bRadioReadReg( CMT2310A_CTL_REG_06 );               //get GPIO5/GPIO4 selection
+    bRadioReadReg( CMT2310A_CTL_REG_16 );               //get INT1 selection
+    bRadioReadReg( CMT2310A_CTL_REG_17 );               //get INT2 selection
+}
+
+void vRadioCmpReg( byte const wr_ptr[], byte rd_ptr[], byte cmp_ptr[], byte length )
+{
+    byte i;
+    for( i = 0; i < length; i++ )
+    {
+        if( wr_ptr[i] != rd_ptr[i] )
+        {
+            cmp_ptr[i] = 0xFF;
+        }
+        else
+        {
+            cmp_ptr[i] = 0x00;
+        }
+    }
+}
+
+void vRadioGoTxInit( void )
+{
+}
+
+void vRadioGoRxInit( void )
+{
+}
+
+void vRadioReceive(void)
+{
+    g_radio.frame_cfg.PAYLOAD_LENGTH = UHF_LEN;
+    vRadioSetPayloadLength(&g_radio.frame_cfg);
+    vRadioSetInt1Sel(CMT2310A_INT_PKT_DONE);
+    vRadioSetInt2Sel(CMT2310A_INT_RX_FIFO_WBYTE);
+    bRadioGoRx();	
+}
+
+void vRadioTransmit(uint8_t* buffer, uint8_t length )
+{
+    vRadioSetInt1Sel( CMT2310A_INT_TX_DONE );
+    vRadioSetInt2Sel( CMT2310A_INT_TX_FIFO_NMTY );
+    g_radio.frame_cfg.PAYLOAD_LENGTH = length;
+    vRadioSetPayloadLength( &g_radio.frame_cfg );
+    vRadioWriteFifo( buffer, length );
+    //  vRadioReadTxFifo(radio_rx_buf, 20);
+    //  vRadioManualResetTxFifoPointer();
+    bRadioGoTx();
+    
+    while ( GPIO_ReadInputDataBit( BSP_GPIO_PORT_E48_GP4 , BSP_GPIO_PIN_E48_GP4) == RESET);
+    bRadioGoStandby();
+    vRadioClearTxFifo();
+    vRadioClearInterrupt();  
+    
+    vRadioReceive();	
+}
+
+uint8_t vRadioGetPacket(uint8_t *buffer,uint8_t *length)
+{
+    uint8_t rx_length;
+  
+    if( g_radio.crc_cfg.CRC_CFG_u._BITS.CRC_EN == 1 )
+    {
+        vRadioInterruptSoucreFlag( &g_radio.int_src_flag );
+        if( g_radio.int_src_flag._BITS.CRC_PASS_FLG == 1 )
+        {
+//            g_rx_count++;
+        }
+    }
+    else
+    {
+//        g_rx_count++;
+    }
+    
+    vRadioReadFifo(&rx_length, 1);
+    
+    vRadioReadFifo(buffer, rx_length);
+    *length = rx_length;
+    vRadioClearRxFifo();	
+    vRadioClearInterrupt(); 
+    bRadioGoRx();	 
+    
+    return 0;
+}
+
+
+void vRadioCheckLink(void)
+{
+  uint8_t i = 0;
+  while(1)
+  {
+    vRadioSoftReset();
+    vRadioPowerUpBoot();				
+    delay1ms(10);
+    g_chip_id = lRadioChipVersion();	
+    if(0x00231000==(g_chip_id&0x00FFFF00)) break;
+
+    DEBUG( "Link Error.....\r\n" );
+    delay1ms(500);
+    i++;
+    if(i >= 20) while(1); 
+  }
+  DEBUG( "Link Device:E48-XXXM20S....\r\n" );
+}
+
+void vRadioSetFreqChannel(uint8_t channel)
+{
+  bRadioGoStandby();
+  bRadioWriteReg( CMT2310A_CTL_REG_03, channel);
+}
\ No newline at end of file
diff --git a/NSPE/WIFI_IOT/bsp/drivers/3_Ebyte_WirelessModule_Drivers/E48xMx/radio.h b/NSPE/WIFI_IOT/bsp/drivers/3_Ebyte_WirelessModule_Drivers/E48xMx/radio.h
new file mode 100755
index 0000000..bd38a19
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/3_Ebyte_WirelessModule_Drivers/E48xMx/radio.h
@@ -0,0 +1,39 @@
+
+
+#ifndef __RADIO_H
+
+#define __RADIO_H
+
+#include "radio_phy.h"
+#include "radio_mac.h"
+#include "CMT2310A_def.h"
+#include "CMT2310A_reg.h"
+
+#define     UHF_LEN             30                  //
+
+
+extern const uint8_t g_cmt2310a_page0[CMT2310A_PAGE0_SIZE];
+extern const uint8_t g_cmt2310a_page1[CMT2310A_PAGE1_SIZE];
+extern const uint8_t g_cmt2310a_page2[CMT2310A_PAGE2_SIZE];
+
+extern void vRadioInit( void );
+extern void vRadioClearInterrupt( void );
+extern void vRadioReadAllStatus( void );
+extern void vRadioCmpReg( byte const wr_ptr[], byte rd_ptr[], byte cmp_ptr[], byte length );
+extern void vRadioGoTxInit( void );
+extern void vRadioGoRxInit( void );
+
+extern void vRadioTransmit(uint8_t* buffer, uint8_t length );
+extern void vRadioReceive(void);
+extern uint8_t vRadioGetPacket(uint8_t *buffer,uint8_t *length);
+
+
+extern void vRadioCheckLink(void);
+
+extern void vRadioSetFreqChannel(uint8_t channel);
+
+#endif
+
+
+
+
diff --git a/NSPE/WIFI_IOT/bsp/drivers/3_Ebyte_WirelessModule_Drivers/E48xMx/radio_hal.c b/NSPE/WIFI_IOT/bsp/drivers/3_Ebyte_WirelessModule_Drivers/E48xMx/radio_hal.c
new file mode 100755
index 0000000..19a7b1a
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/3_Ebyte_WirelessModule_Drivers/E48xMx/radio_hal.c
@@ -0,0 +1,612 @@
+#include "radio_hal.h"
+
+void delay1ms(uint16_t cnt)
+{
+    Ebyte_Port_DelayMs(cnt);
+}
+
+void delay10us(uint32_t cnt)
+{
+    uint8_t i;
+  
+    while( cnt-- )
+    {
+        i = 20;
+        while(i--)
+        {
+          asm("nop");
+        }
+    }    
+}
+
+/******************************
+**Name:  vRadioGpioInit
+**Func:  Radio SPI-4 and GPIO config
+**Input: None
+*Output: None
+********************************/
+void vRadioGpioInit( void )
+{
+    vSpiMasterInit();           //init spi-4 gpio
+}
+
+
+/******************************
+**Name: bRadioReadReg
+**Func: radio read one register
+**Input: None
+*Output: read out data
+********************************/
+uint8_t bRadioReadReg( uint8_t addr )
+{
+    return( bSpiReadByte( addr ) );
+}
+
+/******************************
+**Name: bRadioWriteReg
+**Func: radio write one register
+**Input: None
+*Output: old data
+********************************/
+uint8_t bRadioWriteReg( uint8_t addr, uint8_t reg_dat )
+{
+    return( bSpiWriteByte( addr, reg_dat ) );
+}
+
+/******************************
+**Name: bRadioSetReg
+**Func: radio set some bits of register
+**Input: None
+*Output: old data
+********************************/
+uint8_t bRadioSetReg( uint8_t addr, uint8_t set_bits, uint8_t mask_bits )
+{
+    uint8_t tmp_dat;
+    tmp_dat  = bSpiReadByte( addr );
+    tmp_dat &= ( ~mask_bits );
+    tmp_dat |= ( set_bits & mask_bits );
+    return( bSpiWriteByte( addr, tmp_dat ) );
+}
+
+/******************************
+**Name: vRadioLoadRegs
+**Func: radio read some registers
+**Input: None
+*Output: None
+********************************/
+void vRadioLoadRegs( uint8_t sta_adr, uint8_t* ptr_buf, uint8_t length )
+{
+    uint8_t i;
+    for( i = 0; i < length; i++ )
+    {
+        ptr_buf[i] = bSpiReadByte( sta_adr++ );
+    }
+}
+
+/******************************
+**Name: vRadioStoreRegs
+**Func: radio write some registers
+**Input: None
+*Output: None
+********************************/
+void vRadioStoreRegs( uint8_t sta_adr, uint8_t* ptr_buf, uint8_t length )
+{
+    uint8_t i;
+    for( i = 0; i < length; i++ )
+    {
+        bSpiWriteByte( sta_adr++, ptr_buf[i] );
+    }
+}
+
+/******************************
+**Name: vRadioBurstReadRegs
+**Func: radio read some registers, just for
+**      Page0, start from 0x28, Packet Config Area & System Config Area, bank 5~15
+**      Page1, start from 0x00
+**Input: None
+*Output: None
+********************************/
+void vRadioBurstReadRegs( uint8_t* ptr_buf, uint8_t length )
+{
+    vSpiBurstRead( CMT2310A_CRW_PORT, ptr_buf, length );
+}
+
+/******************************
+**Name: vRadioBurstWriteRegs
+**Func: radio write some registers, just for
+**      Page0, start from 0x28, Packet Config Area & System Config Area, bank 5~15
+**      Page1, start from 0x00
+**Input: None
+*Output: None
+********************************/
+void vRadioBurstWriteRegs( uint8_t* ptr_buf, uint8_t length )
+{
+    vSpiBurstWrite( CMT2310A_CRW_PORT, ptr_buf, length );
+}
+
+/******************************
+**Name: vRadioReadFifo
+**Func: radio read FIFO
+**Input: None
+*Output: None
+********************************/
+void vRadioReadFifo( uint8_t* ptr_fifo, uint8_t length )
+{
+    uint8_t tmp;
+    tmp = bRadioReadReg( CMT2310A_CTL_REG_19 );
+    if( tmp & M_FIFO_MERGE_EN )                         //when fifo merge
+    {
+        tmp &= ( ~M_FIFO_TX_RX_SEL );
+        bRadioWriteReg( CMT2310A_CTL_REG_19, tmp );
+    }
+    vSpiBurstRead( CMT2310A_FIFO_RW_PORT, ptr_fifo, length );
+}
+
+
+/******************************
+**Name: vRadioWriteFifo
+**Func: radio write FIFO
+**Input: None
+*Output: None
+********************************/
+void vRadioWriteFifo( uint8_t* ptr_fifo, uint8_t length )
+{
+    uint8_t tmp;
+    tmp = bRadioReadReg( CMT2310A_CTL_REG_19 );
+    if( tmp & M_FIFO_MERGE_EN )                         //when fifo merge
+    {
+        tmp &= ( ~M_FIFO_TX_RX_SEL );
+        bRadioWriteReg( CMT2310A_CTL_REG_19, tmp );     //TX FIFO
+    }
+    vSpiBurstWrite( CMT2310A_FIFO_RW_PORT, ptr_fifo, length );
+}
+
+/******************************
+**Name: vRadioReadTxFifo
+**Func: radio read FIFO
+**Input: None
+*Output: None
+********************************/
+void vRadioReadTxFifo( uint8_t* ptr_fifo, uint8_t length )
+{
+    uint8_t tmp;
+    tmp = bRadioReadReg( CMT2310A_CTL_REG_19 );
+    if( tmp & M_FIFO_MERGE_EN )                         //when fifo merge
+    {
+        tmp &= ( ~M_FIFO_TX_RX_SEL );
+    }
+    tmp |= M_FIFO_TX_TEST_EN;
+    bRadioWriteReg( CMT2310A_CTL_REG_19, tmp );
+    vSpiBurstRead( CMT2310A_FIFO_RW_PORT, ptr_fifo, length );
+    tmp &= ( ~M_FIFO_TX_TEST_EN );
+    bRadioWriteReg( CMT2310A_CTL_REG_19, tmp );
+}
+
+//######################################################################
+//                       GPIO
+//######################################################################
+/******************************
+**Name:  vRadioSpiModeSel
+**Func:  Radio SPI-4 or SPI-3 Select
+**Input: FALSE: select SPI-4
+*        TRUE: select SPI-3
+*Output: None
+**note:  should be point to page0
+********************************/
+void vRadioSpiModeSel( boolean_t spi_mod )
+{
+    if( spi_mod )
+    {
+        bRadioSetReg( CMT2310A_CTL_REG_07, M_SPI_3W_EN, VAL_BIT3 );
+    }
+    else
+    {
+        bRadioSetReg( CMT2310A_CTL_REG_07, 0, VAL_BIT3 );
+    }
+}
+
+/******************************
+**Name:  vRadioSetTxDin
+**Func:  Radio tx_din enable or disable
+**Input: cfg_din,  FALSE: disable
+*                  TRUE:  enable
+*        pin_sel,  CMT2310A_TX_DIN_GPIO3: GPIO3 as Tx Din
+*                  CMT2310A_TX_DIN_GPIO4: GPIO4 as Tx Din
+*                  CMT2310A_TX_DIN_nIRQ:  NIRQ as Tx Din
+*Output: None
+********************************/
+void vRadioSetTxDin( boolean_t cfg_din, uint8_t pin_sel )
+{
+    bRadioSetReg( CMT2310A_CTL_REG_05, pin_sel, CMT2310A_TX_DIN_SEL );
+    if( cfg_din )
+    {
+        bRadioSetReg( CMT2310A_CTL_REG_04, CMT2310A_TX_DIN_EN, CMT2310A_TX_DIN_EN );
+        vRadioRegPageSel( 1 );
+        bRadioSetReg( CMT2310A_TX_DR_REG_02, ( 0 << 7 ), ( 1 << 7 ) );
+        vRadioRegPageSel( 0 );
+    }
+    else
+    {
+        bRadioSetReg( CMT2310A_CTL_REG_04, 0, CMT2310A_TX_DIN_EN );
+        vRadioRegPageSel( 1 );
+        bRadioSetReg( CMT2310A_TX_DR_REG_02, ( 1 << 7 ), ( 1 << 7 ) );
+        vRadioRegPageSel( 0 );
+    }
+}
+
+/******************************
+**Name:  vRadioSetDclk
+**Func:  Radio digital clkout enable or disable
+**Input: FALSE: disable
+*        TRUE:  enable
+*Output: None
+* note:  only active on GPIO4, and priority high over than other function on GPIO4
+********************************/
+void vRadioSetDigClkOut( boolean_t cfg_out )
+{
+    if( cfg_out )
+    {
+        bRadioSetReg( CMT2310A_CTL_REG_06, CMT2310A_DIG_CLKOUT_EN, CMT2310A_DIG_CLKOUT_EN );
+    }
+    else
+    {
+        bRadioSetReg( CMT2310A_CTL_REG_06, 0, CMT2310A_DIG_CLKOUT_EN );
+    }
+}
+
+/******************************
+**Name:  vRadioSetLfxoPad
+**Func:  Radio enable or disable exteral 32768Hz xo connect
+**       when enable this functiong, GPIO2 & GPIO3 as lfxo connect pin
+**Input: FALSE: disable
+*        TRUE:  enable
+*Output: None
+* note:  only active on GPIO2 & GPIO3, and priority high over than other function on GPIO2 & GPIO3
+********************************/
+void vRadioSetLfxoPad( boolean_t cfg_lfxo )
+{
+    if( cfg_lfxo )
+    {
+        bRadioSetReg( CMT2310A_CTL_REG_07, CMT2310A_LFXO_PAD_EN, CMT2310A_LFXO_PAD_EN );
+    }
+    else
+    {
+        bRadioSetReg( CMT2310A_CTL_REG_07, 0, CMT2310A_LFXO_PAD_EN );
+    }
+}
+
+/******************************
+**Name:  vRadioSetGpio0
+**Func:  Radio config GPIO0
+**Input: CMT2310A_GPIO0_DOUT
+*        CMT2310A_GPIO0_INT1
+*        CMT2310A_GPIO0_INT2
+*        CMT2310A_GPIO0_DCLK
+*        CMT2310A_GPIO0_INT3
+*Output: None
+********************************/
+void vRadioSetGpio0( uint8_t gpio0_sel )
+{
+    bRadioSetReg( CMT2310A_CTL_REG_04, gpio0_sel, CMT2310A_GPIO0_SEL );
+}
+
+/******************************
+**Name:  vRadioSetGpio1
+**Func:  Radio config GPIO1
+**Input: CMT2310A_GPIO1_DCLK
+*        CMT2310A_GPIO1_INT1
+*        CMT2310A_GPIO1_INT2
+*        CMT2310A_GPIO1_DOUT
+*Output: None
+********************************/
+void vRadioSetGpio1( uint8_t gpio1_sel )
+{
+    bRadioSetReg( CMT2310A_CTL_REG_04, gpio1_sel, CMT2310A_GPIO1_SEL );
+}
+
+/******************************
+**Name:  vRadioSetGpio2
+**Func:  Radio config GPIO2
+**Input: CMT2310A_GPIO2_INT1
+*        CMT2310A_GPIO2_INT2
+*        CMT2310A_GPIO2_DCLK
+*        CMT2310A_GPIO2_DOUT
+*        CMT2310A_GPIO2_INT3
+*Output: None
+********************************/
+void vRadioSetGpio2( uint8_t gpio2_sel )
+{
+    bRadioSetReg( CMT2310A_CTL_REG_05, gpio2_sel, CMT2310A_GPIO2_SEL );
+}
+
+/******************************
+**Name:  vRadioSetGpio3
+**Func:  Radio config GPIO3
+**Input: CMT2310A_GPIO3_INT2
+*        CMT2310A_GPIO3_INT1
+*        CMT2310A_GPIO3_DCLK
+*        CMT2310A_GPIO3_DOUT
+*        CMT2310A_GPIO3_DIN
+*Output: None
+********************************/
+void vRadioSetGpio3( uint8_t gpio3_sel )
+{
+    bRadioSetReg( CMT2310A_CTL_REG_05, gpio3_sel, CMT2310A_GPIO3_SEL );
+}
+
+/******************************
+**Name:  vRadioSetGpio4
+**Func:  Radio config GPIO4
+**Input: CMT2310A_GPIO4_DOUT
+*        CMT2310A_GPIO4_INT1
+*        CMT2310A_GPIO4_INT2
+*        CMT2310A_GPIO4_DCLK
+*        CMT2310A_GPIO4_DIN
+*Output: None
+********************************/
+void vRadioSetGpio4( uint8_t gpio4_sel )
+{
+    bRadioSetReg( CMT2310A_CTL_REG_06, gpio4_sel, CMT2310A_GPIO4_SEL );
+}
+
+/******************************
+**Name:  vRadioSetGpio5
+**Func:  Radio config GPIO5
+**Input: CMT2310A_GPIO5_nRST
+*        CMT2310A_GPIO5_INT1
+*        CMT2310A_GPIO5_INT2
+*        CMT2310A_GPIO5_DOUT
+*        CMT2310A_GPIO5_DCLK
+*Output: None
+********************************/
+void vRadioSetGpio5( uint8_t gpio5_sel )
+{
+    bRadioSetReg( CMT2310A_CTL_REG_06, gpio5_sel, CMT2310A_GPIO5_SEL );
+}
+
+/******************************
+**Name:  vRadioSetNirq
+**Func:  Radio config NIRQ pin
+**Input: CMT2310A_nIRQ_INT1
+*        CMT2310A_nIRQ_INT2
+*        CMT2310A_nIRQ_DCLK
+*        CMT2310A_nIRQ_DOUT
+*        CMT2310A_nIRQ_DIN
+*Output: None
+********************************/
+void vRadioSetNirq( uint8_t nirq_sel )
+{
+    bRadioSetReg( CMT2310A_CTL_REG_07, nirq_sel, CMT2310A_nIRQ_SEL );
+}
+
+/******************************
+**Name:  vRadioTcxoDrvSel
+**Func:  Radio set TCXO drive power, nIRQ pin
+**Input:  0=strengh
+          3=week
+*Output: None
+********************************/
+void vRadioTcxoDrvSel( uint8_t drv_sel )
+{
+    vRadioRegPageSel( 1 );
+    switch( drv_sel & 0x03 )
+    {
+        case 0:
+            bRadioSetReg( CMT2310A_CMT_REG_05, ( 0 << 6 ), ( 3 << 6 ) );
+            break;
+        case 1:
+            bRadioSetReg( CMT2310A_CMT_REG_05, ( 1 << 6 ), ( 3 << 6 ) );
+            break;
+        case 2:
+            bRadioSetReg( CMT2310A_CMT_REG_05, ( 2 << 6 ), ( 3 << 6 ) );
+            break;
+        default:
+            bRadioSetReg( CMT2310A_CMT_REG_05, ( 3 << 6 ), ( 3 << 6 ) );
+            break;
+    }
+    vRadioRegPageSel( 0 );
+}
+
+
+//######################################################################
+//                      Auxrl
+//######################################################################
+
+/******************************
+**Name:  vRadioRegPageSel
+**Func:  Radio register page select(page0, page1, page2)
+**Input:   1: select page 1
+*          0: select page 0
+*          2: select page 2
+*Output: None
+********************************/
+void vRadioRegPageSel( uint8_t page_sel )
+{
+    page_sel &= 0x03;
+    switch( page_sel )
+    {
+        case 2:
+            bRadioSetReg( CMT2310A_PAGE_CTL_REG, CMT2310A_PAGE_2, CMT2310A_PAGE_SEL_MASK );
+            break;
+        case 1:
+            bRadioSetReg( CMT2310A_PAGE_CTL_REG, CMT2310A_PAGE_1, CMT2310A_PAGE_SEL_MASK );
+            break;
+        case 0:
+        default:
+            bRadioSetReg( CMT2310A_PAGE_CTL_REG, CMT2310A_PAGE_0, CMT2310A_PAGE_SEL_MASK );
+            break;
+    }
+}
+
+/******************************
+**Name:  vRadioPowerUpBoot
+**Func:  Radio power up boot start
+**Input: None
+*Output: None
+********************************/
+void vRadioPowerUpBoot( void )
+{
+    bSpiWriteByte( CMT2310A_CTL_REG_00,  CMT2310A_REBOOT );
+}
+
+/******************************
+**Name:  vRadioSoftReset
+**Func:  Radio soft reset
+**Input: None
+*Output: None
+********************************/
+void vRadioSoftReset( void )
+{
+    uint8_t i;
+    bRadioWriteReg( CMT2310A_SOFT_RST, 0xFF );
+    for( i = 0; i < 20; i++ )
+    {
+        delay10us( 100 );
+    }
+}
+
+/******************************
+**Name:  vRadioSetPaOutputMode
+**Func:  Radio config PA output mode
+**Input: cfg_en
+*               FALSE: single ended PA output mode
+*               TRUE:  differential PA output mode
+*Output: None
+********************************/
+void vRadioSetPaOutputMode( boolean_t cfg_en )
+{
+    if( cfg_en )
+    {
+        bRadioSetReg( CMT2310A_CTL_REG_22, CMT2310A_PA_DIFF_SEL, CMT2310A_PA_DIFF_SEL );
+    }
+    else
+    {
+        bRadioSetReg( CMT2310A_CTL_REG_22, 0, CMT2310A_PA_DIFF_SEL );
+    }
+}
+
+/******************************
+**Name:  vRadioSetTxDataInverse
+**Func:  Radio config Tx Data inverse
+**Input: cfg_en
+*               FALSE: normal
+*               TRUE:  inverse
+*Output: None
+********************************/
+void vRadioSetTxDataInverse( boolean_t cfg_en )
+{
+    if( cfg_en )
+    {
+        bRadioSetReg( CMT2310A_CTL_REG_22, CMT2310A_TX_DATA_INV, CMT2310A_TX_DATA_INV );
+    }
+    else
+    {
+        bRadioSetReg( CMT2310A_CTL_REG_22, 0, CMT2310A_TX_DATA_INV );
+    }
+}
+
+/******************************
+**Name:  vRadioSetAntSwitch
+**Func:  Radio config GPIO0 & GPIO1 as antenna switch control
+**Input: cfg_en,     FALSE: disable antenna switch function
+*                    TRUE:  enable antenna switch function
+*
+*                                      GPIO0     GPIO1
+*        cfg_polar,  FALSE: RX_STATE     1         0
+*                           TX_STATE     0         1
+*
+*                    TRUE:  RX_STATE     0         1
+*                           TX_STATE     1         0
+*Output: None
+* note:  priority high over than other function on GPIO0 & GPIO1
+********************************/
+void vRadioSetAntSwitch( boolean_t cfg_en, boolean_t cfg_polar )
+{
+    uint8_t cfg_tmp = 0;
+    if( cfg_en )
+    {
+        cfg_tmp |= CMT2310A_TRX_SWT_EN;
+    }
+    if( cfg_polar )
+    {
+        cfg_tmp |= CMT2310A_TRX_SWT_INV;
+    }
+    bRadioSetReg( CMT2310A_CTL_REG_22, cfg_tmp, ( CMT2310A_TRX_SWT_EN | CMT2310A_TRX_SWT_INV ) );
+}
+
+/******************************
+**Name:  vRadioDcdcCfg
+**Func:  Radio DC-DC config
+**Input: cfg_en
+*               FALSE: normal
+*               TRUE:  inverse
+*Output: None
+********************************/
+void vRadioDcdcCfg( boolean_t on_off )
+{
+    vRadioRegPageSel( 1 );
+    if( on_off )                        //Buck_sel = 1;
+    {
+        bRadioSetReg( CMT2310A_CMT_REG_01, 0x10, 0x10 );
+    }
+    else
+    {
+        bRadioSetReg( CMT2310A_CMT_REG_01, 0x00, 0x10 );
+    }
+    vRadioRegPageSel( 0 );
+}
+
+/******************************
+**Name:  vRadioCapLoad
+**Func:  Radio Set Cap load value
+**Input: cap value, range 0-31
+*Output: None
+********************************/
+void vRadioCapLoad( uint8_t cap_value )
+{
+    cap_value &= 0x1F;
+    vRadioRegPageSel( 1 );
+    bRadioSetReg( CMT2310A_CMT_REG_06, cap_value, 0x1F );
+    vRadioRegPageSel( 0 );
+}
+
+/******************************
+**Name:  vRadioLfoscCfg
+**Func:  Radio Set LFOSC
+**Input: TRUE:  enable
+**       FALSE: disable
+*Output: None
+********************************/
+void vRadioLfoscCfg( boolean_t on_off )
+{
+    vRadioRegPageSel( 1 );
+    if( on_off )
+    {
+        bRadioSetReg( CMT2310A_CMT_REG_13, 0x38, 0x38 );
+    }
+    else
+    {
+        bRadioSetReg( CMT2310A_CMT_REG_13, 0x00, 0x38 );
+    }
+    vRadioRegPageSel( 0 );
+}
+
+/******************************
+**Name:  vRadioXoWaitCfg
+**Func:  Radio Set xtal wait for pu_boot
+**Input:
+                           pu_boot(us)  slp2rdy(us)
+         RADIO_CGU_DIV1->    1344          584
+         RADIO_CGU_DIV4->    3972         1013
+         RADIO_CGU_DIV8->    6624         1586
+*Output: None
+********************************/
+void vRadioXoWaitCfg( uint8_t div_sel )
+{
+    div_sel  &= 0x03;
+    div_sel <<= 6;
+    vRadioRegPageSel( 0 );
+    bRadioSetReg( CMT2310A_CTL_REG_07, div_sel, CMT2310A_CTL_REG_07_MASK );
+    vRadioRegPageSel( 0 );
+}
+
diff --git a/NSPE/WIFI_IOT/bsp/drivers/3_Ebyte_WirelessModule_Drivers/E48xMx/radio_hal.h b/NSPE/WIFI_IOT/bsp/drivers/3_Ebyte_WirelessModule_Drivers/E48xMx/radio_hal.h
new file mode 100755
index 0000000..c4f8f05
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/3_Ebyte_WirelessModule_Drivers/E48xMx/radio_hal.h
@@ -0,0 +1,86 @@
+
+
+#ifndef __RADIO_HAL_H
+
+#define __RADIO_HAL_H
+
+#include "stm8l15x.h"
+#include "ebyte_port.h"
+
+
+//»ù´¡ÆµµãÖ»ÄÜ´ÓÒÔÏÂÑ¡Ôñ
+#define CM2310A_410MHZ  0
+#define CM2310A_433MHZ  1
+#define CM2310A_868MHZ  2
+#define CM2310A_915MHZ  3
+
+#define PRODUCT_FREQUENCY  CM2310A_410MHZ//Ñ¡Ôñ»ù´¡Æµµã
+
+#include "radio_spi.h"
+#include "CMT2310A_def.h"
+#include "CMT2310A_reg.h"
+
+#define     RADIO_CGU_DIV1      0
+#define     RADIO_CGU_DIV4      1
+#define     RADIO_CGU_DIV8      2
+
+#ifndef TRUE
+/** Value is true (boolean_t type) */
+#define TRUE        ((boolean_t) 1u)
+#endif
+
+#ifndef FALSE
+/** Value is false (boolean_t type) */
+#define FALSE       ((boolean_t) 0u)
+#endif
+typedef uint8_t   boolean_t;
+typedef uint8_t   byte;
+
+extern void          vRadioGpioInit( void );
+
+extern uint8_t bRadioReadReg( uint8_t addr );
+extern uint8_t bRadioWriteReg( uint8_t addr, uint8_t reg_dat );
+extern uint8_t bRadioSetReg( uint8_t addr, uint8_t set_bits, uint8_t mask_bits );
+
+extern void          vRadioLoadRegs( uint8_t sta_adr, uint8_t* ptr_buf, uint8_t length );
+extern void          vRadioStoreRegs( uint8_t sta_adr, uint8_t* ptr_buf, uint8_t length );
+
+extern void          vRadioBurstReadRegs( uint8_t* ptr_buf, uint8_t length );
+extern void          vRadioBurstWriteRegs( uint8_t* ptr_buf, uint8_t length );
+
+extern void          vRadioReadFifo( uint8_t* ptr_fifo, uint8_t length );
+extern void          vRadioWriteFifo( uint8_t* ptr_fifo, uint8_t length );
+extern void          vRadioReadTxFifo( uint8_t* ptr_fifo, uint8_t length );
+
+
+extern void          vRadioSpiModeSel( boolean_t spi_mod );
+extern void          vRadioSetTxDin( boolean_t cfg_din, uint8_t pin_sel );
+extern void          vRadioSetDigClkOut( boolean_t cfg_out );
+extern void          vRadioSetLfxoPad( boolean_t cfg_lfxo );
+extern void          vRadioSetGpio0( uint8_t gpio0_sel );
+extern void          vRadioSetGpio1( uint8_t gpio1_sel );
+extern void          vRadioSetGpio2( uint8_t gpio2_sel );
+extern void          vRadioSetGpio3( uint8_t gpio3_sel );
+extern void          vRadioSetGpio4( uint8_t gpio4_sel );
+extern void          vRadioSetGpio5( uint8_t gpio5_sel );
+extern void          vRadioSetNirq( uint8_t nirq_sel );
+extern void          vRadioTcxoDrvSel( uint8_t drv_sel );
+
+extern void          vRadioRegPageSel( uint8_t page_sel );
+extern void          vRadioPowerUpBoot( void );
+extern void          vRadioSoftReset( void );
+extern void          vRadioSetPaOutputMode( boolean_t cfg_en );
+extern void          vRadioSetTxDataInverse( boolean_t cfg_en );
+extern void          vRadioSetAntSwitch( boolean_t cfg_en, boolean_t cfg_polar );
+
+extern void          vRadioDcdcCfg( boolean_t on_off );
+extern void          vRadioCapLoad( uint8_t cap_value );
+extern void          vRadioLfoscCfg( boolean_t on_off );
+extern void          vRadioXoWaitCfg( uint8_t div_sel );
+
+extern void          delay1ms(uint16_t cnt);
+extern void          delay10us(uint32_t cnt);
+#endif
+
+
+
diff --git a/NSPE/WIFI_IOT/bsp/drivers/3_Ebyte_WirelessModule_Drivers/E48xMx/radio_mac.c b/NSPE/WIFI_IOT/bsp/drivers/3_Ebyte_WirelessModule_Drivers/E48xMx/radio_mac.c
new file mode 100755
index 0000000..b076edd
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/3_Ebyte_WirelessModule_Drivers/E48xMx/radio_mac.c
@@ -0,0 +1,482 @@
+#include "radio_mac.h"
+
+/******************************
+**Name:  bRadioGetCurrentChannl
+**Func:  Radio get current active channl number
+**Input: None
+*Output: channl number
+********************************/
+uint8_t bRadioGetCurrentChannl( void )
+{
+    return( bRadioReadReg( CMT2310A_FREQ_CHANL_ACT_REG ) );
+}
+
+/******************************
+**Name:  vRadioSetTxSeqNumber
+**Func:  Radio set transmit sequence number
+**Input: transmit init sequence number
+*Output: None
+********************************/
+void vRadioSetTxSeqNumberInitValue( FRAME_CFG* frm_cfg )
+{
+    bRadioWriteReg( CMT2310A_SEQNUM_TX_IN_L_REG, ( uint8_t )( ( *frm_cfg ).SEQNUM_TX_IN ) );
+    bRadioWriteReg( CMT2310A_SEQNUM_TX_IN_H_REG, ( uint8_t )( ( ( *frm_cfg ).SEQNUM_TX_IN ) >> 8 ) );
+}
+
+/******************************
+**Name:  wRadioGetTxSeqNumber
+**Func:  Radio get current transmit sequence number
+**Input: None
+*Output: current transmit sequence number
+********************************/
+uint16_t  wRadioGetTxSeqNumberCurrent( FRAME_CFG* frm_cfg )
+{
+    uint16_t  seq_num = 0;
+    seq_num   = bRadioReadReg( CMT2310A_SEQNUM_TX_OUT_H_REG );
+    seq_num <<= 8;
+    seq_num  |= bRadioReadReg( CMT2310A_SEQNUM_TX_OUT_L_REG );
+    ( *frm_cfg ).SEQNUM_TX_CURRENT_OUT = seq_num;
+    return( ( *frm_cfg ).SEQNUM_TX_CURRENT_OUT = seq_num );
+}
+
+
+/******************************
+**Name:  vRadioSetTxFCS2
+**Func:  Radio set transmit packet FCS2 value
+**Input: transmit FCS2
+*Output: None
+********************************/
+void vRadioSetTxFCS2( FRAME_CFG* frm_cfg )
+{
+    bRadioWriteReg( CMT2310A_FCS2_TX_IN_REG, ( *frm_cfg ).FCS2_TX_IN );
+}
+
+/******************************
+**Name:  vRadioGetRxFCS2
+**Func:  Radio get receive packet FCS2 value
+**Input: None
+*Output: receive FCS2
+********************************/
+uint8_t bRadioGetRxFCS2( FRAME_CFG* frm_cfg )
+{
+    ( *frm_cfg ).FCS2_RX_OUT = bRadioReadReg( CMT2310A_FCS2_RX_OUT_REG );
+    return( ( *frm_cfg ).FCS2_RX_OUT );
+}
+
+/******************************
+**Name:  vRadioSetPayloadLength
+**Func:  Radio config payload length
+**Input: length
+*Output: None
+********************************/
+void vRadioSetPayloadLength( FRAME_CFG* frm_cfg )
+{
+    uint16_t  len;
+    if( ( *frm_cfg ).PAYLOAD_LENGTH != 0 )
+    {
+        len = ( *frm_cfg ).PAYLOAD_LENGTH - 1;
+        bRadioWriteReg( CMT2310A_PAYLOAD_LENGTH_L_REG, ( byte )len );
+        bRadioWriteReg( CMT2310A_PAYLOAD_LENGTH_H_REG, ( byte )( len >> 8 ) );
+    }
+}
+
+/******************************
+**Name:  wRadioGetPayloadLength
+**Func:  Radio get payload length
+**Input: None
+*Output: payload length
+********************************/
+uint16_t  vRadioGetPayloadLength( FRAME_CFG* frm_cfg )
+{
+    uint16_t  length = 0;
+    length   = bRadioReadReg( CMT2310A_PAYLOAD_LENGTH_H_REG );
+    length <<= 8;
+    length  |= bRadioReadReg( CMT2310A_PAYLOAD_LENGTH_L_REG );
+    ( *frm_cfg ).PAYLOAD_LENGTH = length + 1;
+    return( length );
+}
+
+//######################################################################
+//                       Packet config
+//######################################################################
+/******************************
+**Name:  vRadioCfgPreamble
+**Func:  Radio config preamble
+**Input: preamble struct
+*Output: None
+********************************/
+void vRadioCfgPreamble( PREAMBLE_CFG* prm_ptr )
+{
+    uint8_t cfg_tmp;
+    cfg_tmp = bRadioReadReg( CMT2310A_CTL_REG_40 );
+    if( ( *prm_ptr ).PREAM_LENG_UNIT == 0 )
+    {
+        cfg_tmp &= ( ~CMT2310A_PREAM_LENG_UNIIT );
+    }
+    else
+    {
+        cfg_tmp |= CMT2310A_PREAM_LENG_UNIIT;
+    }
+    cfg_tmp &= ( ~CMT2310A_RX_PREAM_SIZE_MASK );
+    cfg_tmp |= ( ( ( ( *prm_ptr ).RX_PREAM_SIZE ) << 3 )&CMT2310A_RX_PREAM_SIZE_MASK );
+    bRadioWriteReg( CMT2310A_CTL_REG_40, cfg_tmp );
+    bRadioWriteReg( CMT2310A_CTL_REG_41, ( uint8_t )( ( *prm_ptr ).TX_PREAM_SIZE ) );
+    bRadioWriteReg( CMT2310A_CTL_REG_42, ( uint8_t )( ( *prm_ptr ).TX_PREAM_SIZE >> 8 ) );
+    bRadioWriteReg( CMT2310A_CTL_REG_43, ( *prm_ptr ).PREAM_VALUE );
+}
+
+/******************************
+**Name:  vRadioCfgSyncWord
+**Func:  Radio config sync word
+**Input: sync word struct
+*Output: None
+********************************/
+void vRadioCfgSyncWord( SYNC_CFG* sync_ptr )
+{
+    uint8_t i;
+    uint8_t adr;
+    bRadioWriteReg( CMT2310A_CTL_REG_44, ( *sync_ptr ).SYN_CFG_u.SYNC_CFG_REG );
+    for( i = 0, adr = CMT2310A_CTL_REG_52; i < 8; i++, adr-- )
+    {
+        bRadioWriteReg( adr, ( *sync_ptr ).SYNC_VALUE[i] );
+        bRadioWriteReg( ( adr + 8 ), ( *sync_ptr ).SYNC_FEC_VALUE[i] );
+    }
+    if( ( *sync_ptr ).SYNC_VALUE_SEL == 0 )
+    {
+        bRadioSetReg( CMT2310A_CTL_REG_64, 0, CMT2310A_SYNC_VALUE_SEL );
+    }
+    else
+    {
+        bRadioSetReg( CMT2310A_CTL_REG_64, CMT2310A_SYNC_VALUE_SEL, CMT2310A_SYNC_VALUE_SEL );
+    }
+}
+
+/******************************
+**Name:  vRadioCfgNodeAddr
+**Func:  Radio config node address
+**Input: node address struct
+*Output: None
+********************************/
+void vRadioCfgNodeAddr( ADDR_CFG* node_addr_ptr )
+{
+    uint8_t cfg_tmp;
+    cfg_tmp  = bRadioReadReg( CMT2310A_CTL_REG_64 );
+    cfg_tmp &= 0x80;
+    cfg_tmp |= ( ( *node_addr_ptr ).ADDR_CFG_u.ADDR_CFG_REG & 0x7F );
+    bRadioWriteReg( CMT2310A_CTL_REG_64, cfg_tmp );
+    bRadioWriteReg( CMT2310A_SRC_ADDR_L_REG, ( *node_addr_ptr ).SRC_ADDR[0] );
+    bRadioWriteReg( CMT2310A_SRC_ADDR_H_REG, ( *node_addr_ptr ).SRC_ADDR[1] );
+    bRadioWriteReg( CMT2310A_DEST_ADDR_L_REG, ( *node_addr_ptr ).DEST_ADDR[0] );
+    bRadioWriteReg( CMT2310A_DEST_ADDR_H_REG, ( *node_addr_ptr ).DEST_ADDR[1] );
+    bRadioWriteReg( CMT2310A_SRC_BITMASK_L_REG, ( *node_addr_ptr ).SRC_BITMASK[0] );
+    bRadioWriteReg( CMT2310A_SRC_BITMASK_H_REG, ( *node_addr_ptr ).SRC_BITMASK[1] );
+    bRadioWriteReg( CMT2310A_DEST_BITMASK_L_REG, ( *node_addr_ptr ).DEST_BITMASK[0] );
+    bRadioWriteReg( CMT2310A_DEST_BITMASK_H_REG, ( *node_addr_ptr ).DEST_BITMASK[1] );
+}
+
+/******************************
+**Name:  vRadioCfgCrc
+**Func:  Radio config crc
+**Input: crc struct
+*Output: None
+********************************/
+void vRadioCfgCrc( CRC_CFG* crc_ptr )
+{
+    uint8_t i, adr;
+    bRadioWriteReg( CMT2310A_CTL_REG_73, ( uint8_t )( ( *crc_ptr ).CRC_CFG_u.CRC_CFG_REG ) );
+    for( i = 0, adr = CMT2310A_CTL_REG_74; i < 4; i++, adr++ )
+    {
+        bRadioWriteReg( adr, ( *crc_ptr ).CRC_SEED_u.u8_SEED[i] );
+        bRadioWriteReg( ( adr + 4 ), ( *crc_ptr ).CRC_POLY_u.u8_POLY[i] );
+    }
+    if( ( *crc_ptr ).CRC_CFG_u._BITS.CRC_REFOUT )
+    {
+        bRadioSetReg( CMT2310A_CTL_REG_82, CMT2310A_CRC_REFOUT, CMT2310A_CRC_REFOUT );
+    }
+    else
+    {
+        bRadioSetReg( CMT2310A_CTL_REG_82, 0, CMT2310A_CRC_REFOUT );
+    }
+    if( ( *crc_ptr ).CRC_CFG_u._BITS.CRCERR_CLR_FIFO_EN )
+    {
+        bRadioSetReg( CMT2310A_CTL_REG_84, CMT2310A_CRCERR_CLR_FIFO_EN, CMT2310A_CRCERR_CLR_FIFO_EN );
+    }
+    else
+    {
+        bRadioSetReg( CMT2310A_CTL_REG_84, 0, CMT2310A_CRCERR_CLR_FIFO_EN );
+    }
+}
+
+/******************************
+**Name:  vRadioCfgCodeFormat
+**Func:  Radio config code format
+**Input: code format struct
+*Output: None
+********************************/
+void vRadioCfgCodeFormat( CODING_FORMAT_CFG* code_format_ptr )
+{
+    uint8_t cfg_tmp;
+    cfg_tmp  = bRadioReadReg( CMT2310A_CTL_REG_82 );
+    cfg_tmp &= 0x80;
+    cfg_tmp |= ( ( *code_format_ptr ).CODING_FORMAT_CFG_u.CODING_CFG_REG & 0x3F );
+    if( ( *code_format_ptr ).WHITEN_SEED & 0x0100 )
+    {
+        cfg_tmp |= CMT2310A_WHITEN_SEED_B8;
+    }
+    bRadioWriteReg( CMT2310A_CTL_REG_82, cfg_tmp );
+    bRadioWriteReg( CMT2310A_CTL_REG_83, ( uint8_t )( ( *code_format_ptr ).WHITEN_SEED ) );
+    cfg_tmp  = ( ( *code_format_ptr ).CODING_FORMAT_CFG_u.CODING_CFG_REG >> 8 );
+    cfg_tmp &= ( ~CMT2310A_FEC_PAD_CODE_H_MASK );
+    cfg_tmp |= ( ( uint8_t )( ( ( *code_format_ptr ).FEC_PAD_CODE ) >> 6 )&CMT2310A_FEC_PAD_CODE_H_MASK );
+    bRadioWriteReg( CMT2310A_CTL_REG_93, cfg_tmp );
+    bRadioWriteReg( CMT2310A_CTL_REG_94, ( uint8_t )( ( *code_format_ptr ).FEC_PAD_CODE ) );
+}
+
+/******************************
+**Name:  vRadioCfgFrameFormat
+**Func:  Radio config frame format
+**Input: frame format struct
+*Output: None
+********************************/
+void vRadioCfgFrameFormat( FRAME_CFG* frame_format_ptr )
+{
+    uint8_t cfg_tmp;
+    bRadioSetReg( CMT2310A_CTL_REG_40, ( *frame_format_ptr ).DATA_MODE, CMT2310A_DATA_MODE_MASK );
+    bRadioWriteReg( CMT2310A_CTL_REG_63, ( *frame_format_ptr ).FRAME_CFG1_u.FRAME_CFG1_REG );
+    cfg_tmp  = bRadioReadReg( CMT2310A_CTL_REG_84 );
+    cfg_tmp &= 0x80;
+    cfg_tmp |= ( ( *frame_format_ptr ).FRAME_CFG2_u.FRAME_CFG2_REG & 0x7F );
+    bRadioWriteReg( CMT2310A_CTL_REG_84, cfg_tmp );
+    bRadioWriteReg( CMT2310A_TX_PKT_NUM_L_REG, ( uint8_t )( *frame_format_ptr ).TX_PKT_NUM );
+    bRadioWriteReg( CMT2310A_TX_PKT_NUM_H_REG, ( uint8_t )( ( *frame_format_ptr ).TX_PKT_NUM >> 8 ) );
+    bRadioWriteReg( CMT2310A_SEQNUM_TX_IN_L_REG, ( uint8_t )( *frame_format_ptr ).SEQNUM_TX_IN );
+    bRadioWriteReg( CMT2310A_SEQNUM_TX_IN_H_REG, ( uint8_t )( ( *frame_format_ptr ).SEQNUM_TX_IN >> 8 ) );
+    bRadioWriteReg( CMT2310A_TX_PKT_GAP_REG, ( *frame_format_ptr ).TX_PKT_GAP );
+    bRadioWriteReg( CMT2310A_FCS2_TX_IN_REG, ( *frame_format_ptr ).FCS2_TX_IN );
+    bRadioWriteReg( CMT2310A_FCS2_RX_OUT_REG, ( *frame_format_ptr ).FCS2_RX_OUT );
+}
+
+/******************************
+**Name:  vRadioCfgFrameFormat
+**Func:  Radio config frame format
+**Input: frame format struct
+*Output: None
+********************************/
+void  vRadioCfgWiSunFormat( WI_SUN_CFG* wi_sun_ptr )
+{
+    bRadioWriteReg( CMT2310A_CTL_REG_111, ( *wi_sun_ptr ).WI_SUN_REG );
+}
+
+/******************************
+**Name:  vRadioCdrTracingModeCfg
+**Func:  Radio config cdr tracing config
+**Input: cdr tracing
+*Output: None
+********************************/
+void vRadioCdrTracingModeCfg( CDR_TRACING_CFG* cdr_ptr )
+{
+    vRadioRegPageSel( 1 );
+    bRadioWriteReg( CMT2310A_RX_CDR_REG_00, ( *cdr_ptr ).CDR_CFG0_u.CDR_CFG0_REG );
+    ( *cdr_ptr ).CDR_CFG1_u.CDR_CFG1_REG &= 0xF8;
+    ( *cdr_ptr ).CDR_CFG1_u.CDR_CFG1_REG |= ( ( uint8_t )( ( *cdr_ptr ).CDR_BR_TH >> 16 ) & 0x07 );
+    bRadioSetReg( CMT2310A_RX_CDR_REG_03, ( *cdr_ptr ).CDR_CFG1_u.CDR_CFG1_REG, 0x1F );
+    bRadioWriteReg( CMT2310A_RX_CDR_REG_01, ( uint8_t )( *cdr_ptr ).CDR_BR_TH );
+    bRadioWriteReg( CMT2310A_RX_CDR_REG_02, ( uint8_t )( ( *cdr_ptr ).CDR_BR_TH >> 8 ) );
+    vRadioRegPageSel( 0 );
+}
+
+
+//######################################################################
+//                       System control
+//######################################################################
+void vRadioCfgWorkMode( WORK_MODE_CFG* run_mode_ptr )
+{
+    bRadioWriteReg( CMT2310A_CTL_REG_03, ( *run_mode_ptr ).FREQ_CHANL_NANU );
+    bRadioWriteReg( CMT2310A_CTL_REG_12, ( *run_mode_ptr ).FREQ_SPACE );
+    bRadioWriteReg( CMT2310A_CTL_REG_13, ( *run_mode_ptr ).FREQ_TIMES );
+    bRadioWriteReg( CMT2310A_CTL_REG_96, ( *run_mode_ptr ).WORK_MODE_CFG1_u.WORK_MODE_CFG1_REG );
+    bRadioWriteReg( CMT2310A_CTL_REG_97, ( *run_mode_ptr ).WORK_MODE_CFG2_u.WORK_MODE_CFG2_REG );
+    bRadioWriteReg( CMT2310A_CTL_REG_98, ( *run_mode_ptr ).WORK_MODE_CFG3_u.WORK_MODE_CFG3_REG );
+    bRadioWriteReg( CMT2310A_CTL_REG_105, ( *run_mode_ptr ).WORK_MODE_CFG4_u.WORK_MODE_CFG4_REG );
+    bRadioWriteReg( CMT2310A_CTL_REG_106, ( *run_mode_ptr ).WORK_MODE_CFG5_u.WORK_MODE_CFG5_REG );
+    bRadioSetReg( CMT2310A_CTL_REG_22, ( *run_mode_ptr ).WORK_MODE_CFG6_u.WORK_MODE_CFG6_REG, 0xC0 );
+    bRadioWriteReg( CMT2310A_CTL_REG_99, ( uint8_t )( ( *run_mode_ptr ).SLEEP_TIMER_M ) );
+    bRadioWriteReg( CMT2310A_CTL_REG_100, ( ( ( uint8_t )( ( *run_mode_ptr ).SLEEP_TIMER_M >> 3 ) ) & 0xE0 ) | ( ( *run_mode_ptr ).SLEEP_TIMER_R & 0x1F ) );
+    bRadioWriteReg( CMT2310A_CTL_REG_101, ( uint8_t )( ( *run_mode_ptr ).RX_TIMER_T1_M ) );
+    bRadioWriteReg( CMT2310A_CTL_REG_102, ( ( ( uint8_t )( ( *run_mode_ptr ).RX_TIMER_T1_M >> 3 ) ) & 0xE0 ) | ( ( *run_mode_ptr ).RX_TIMER_T1_R & 0x1F ) );
+    bRadioWriteReg( CMT2310A_CTL_REG_103, ( uint8_t )( ( *run_mode_ptr ).RX_TIMER_T2_M ) );
+    bRadioWriteReg( CMT2310A_CTL_REG_104, ( ( ( uint8_t )( ( *run_mode_ptr ).RX_TIMER_T2_M >> 3 ) ) & 0xE0 ) | ( ( *run_mode_ptr ).RX_TIMER_T2_R & 0x1F ) );
+    bRadioWriteReg( CMT2310A_CTL_REG_107, ( uint8_t )( ( *run_mode_ptr ).RX_TIMER_CSMA_M ) );
+    bRadioWriteReg( CMT2310A_CTL_REG_108, ( ( ( uint8_t )( ( *run_mode_ptr ).RX_TIMER_CSMA_M >> 3 ) ) & 0xE0 ) | ( ( *run_mode_ptr ).RX_TIMER_CSMA_R & 0x1F ) );
+    bRadioWriteReg( CMT2310A_CTL_REG_110, ( *run_mode_ptr ).TX_DC_TIMES );
+    bRadioWriteReg( CMT2310A_CTL_REG_113, ( *run_mode_ptr ).TX_RS_TIMES );
+    bRadioWriteReg( CMT2310A_CTL_REG_115, ( *run_mode_ptr ).CSMA_TIMES );
+    bRadioWriteReg( CMT2310A_CTL_REG_118, ( uint8_t )( ( *run_mode_ptr ).SLEEP_TIMER_CSMA_M ) );
+    bRadioWriteReg( CMT2310A_CTL_REG_119, ( ( ( uint8_t )( ( *run_mode_ptr ).SLEEP_TIMER_CSMA_M >> 3 ) ) & 0xE0 ) | ( ( *run_mode_ptr ).SLEEP_TIMER_CSMA_R & 0x1F ) );
+}
+
+void vRadioReadRunModeCfg( void )
+{
+    bRadioReadReg( CMT2310A_CTL_REG_11 );
+    bRadioReadReg( CMT2310A_CTL_REG_12 );
+    bRadioReadReg( CMT2310A_CTL_REG_13 );
+    bRadioReadReg( CMT2310A_CTL_REG_96 );
+    bRadioReadReg( CMT2310A_CTL_REG_97 );
+    bRadioReadReg( CMT2310A_CTL_REG_98 );
+    bRadioReadReg( CMT2310A_CTL_REG_105 );
+    bRadioReadReg( CMT2310A_CTL_REG_106 );
+    bRadioReadReg( CMT2310A_CTL_REG_99 );
+    bRadioReadReg( CMT2310A_CTL_REG_100 );
+    bRadioReadReg( CMT2310A_CTL_REG_101 );
+    bRadioReadReg( CMT2310A_CTL_REG_102 );
+    bRadioReadReg( CMT2310A_CTL_REG_103 );
+    bRadioReadReg( CMT2310A_CTL_REG_104 );
+    bRadioReadReg( CMT2310A_CTL_REG_107 );
+    bRadioReadReg( CMT2310A_CTL_REG_108 );
+    bRadioReadReg( CMT2310A_CTL_REG_110 );
+    bRadioReadReg( CMT2310A_CTL_REG_113 );
+    bRadioReadReg( CMT2310A_CTL_REG_115 );
+    bRadioReadReg( CMT2310A_CTL_REG_118 );
+    bRadioReadReg( CMT2310A_CTL_REG_119 );
+}
+
+uint8_t bRadioGetTxDutyCycleDoneTimes( WORK_MODE_CFG* run_mode_ptr )
+{
+    ( *run_mode_ptr ).TX_DC_DONE_TIMES = bRadioReadReg( CMT2310A_CTL_REG_112 );
+    return( ( *run_mode_ptr ).TX_DC_DONE_TIMES );
+}
+
+uint8_t bRadioGetTxResendDoneTimes( WORK_MODE_CFG* run_mode_ptr )
+{
+    ( *run_mode_ptr ).TX_RS_DONE_TIMES = bRadioReadReg( CMT2310A_CTL_REG_114 );
+    return( ( *run_mode_ptr ).TX_RS_DONE_TIMES );
+}
+
+uint8_t bRadioGetCMSADoneTimes( WORK_MODE_CFG* run_mode_ptr )
+{
+    ( *run_mode_ptr ).CSMA_DONE_TIMES = bRadioReadReg( CMT2310A_CTL_REG_116 );
+    return( ( *run_mode_ptr ).CSMA_DONE_TIMES );
+}
+
+void vRadioSendWithAck( boolean_t w_ack, FRAME_CFG* frame_format_ptr )
+{
+    uint8_t tmp;
+    tmp = bRadioReadReg( CMT2310A_FCS2_TX_IN_REG );
+    if( w_ack )
+    {
+        ( *frame_format_ptr ).FCS2_TX_IN = tmp | 0x80;
+    }
+    else
+    {
+        ( ( *frame_format_ptr ) ).FCS2_TX_IN = tmp & 0x7F;
+    }
+    bRadioWriteReg( CMT2310A_FCS2_TX_IN_REG, ( ( *frame_format_ptr ) ).FCS2_TX_IN );
+}
+
+
+
+void vRadioEnableTxAck( boolean_t en_flg, WORK_MODE_CFG* run_mode_ptr )
+{
+    if( en_flg )
+    {
+        ( *run_mode_ptr ).WORK_MODE_CFG1_u._BITS.TX_ACK_EN   = 1;       //enable TX_ACK
+        ( *run_mode_ptr ).WORK_MODE_CFG2_u._BITS.RX_TIMER_EN = 1;
+    }
+    else
+    {
+        ( *run_mode_ptr ).WORK_MODE_CFG1_u._BITS.TX_ACK_EN   = 0;       //disable TX_ACK
+        ( *run_mode_ptr ).WORK_MODE_CFG2_u._BITS.RX_TIMER_EN = 0;
+    }
+    vRadioCfgWorkMode( run_mode_ptr );
+}
+
+
+void vRadioEnableRxAck( boolean_t en_flg, WORK_MODE_CFG* run_mode_ptr )
+{
+    if( en_flg )
+    {
+        ( *run_mode_ptr ).WORK_MODE_CFG2_u._BITS.RX_ACK_EN = 1;    //enable RX_ACK
+    }
+    else
+    {
+        ( *run_mode_ptr ).WORK_MODE_CFG2_u._BITS.RX_ACK_EN = 0;    //disable RX_ACK
+    }
+    vRadioCfgWorkMode( run_mode_ptr );
+}
+
+
+uint8_t bRadioGetFreqChanl( void )
+{
+    return( bRadioReadReg( CMT2310A_FREQ_CHANL_ACT_REG ) );
+}
+
+uint8_t bRadioGetHopDoneTimes( void )
+{
+    return( bRadioReadReg( CMT2310A_CTL_REG_11 ) );
+}
+
+
+void vRadioCsmaEnable( boolean_t on_off, WORK_MODE_CFG* run_mode_ptr )
+{
+    if( on_off )
+    {
+        ( *run_mode_ptr ).WORK_MODE_CFG2_u._BITS.RX_TIMER_EN = 1;
+        if( ( *run_mode_ptr ).CSMA_TIMES != 0 )
+        {
+            ( *run_mode_ptr ).WORK_MODE_CFG4_u._BITS.SLEEP_TIMER_EN = 1;
+        }
+        ( *run_mode_ptr ).WORK_MODE_CFG2_u._BITS.CSMA_EN = 1;
+    }
+    else
+    {
+        ( *run_mode_ptr ).WORK_MODE_CFG2_u._BITS.RX_TIMER_EN = 0;
+        ( *run_mode_ptr ).WORK_MODE_CFG4_u._BITS.SLEEP_TIMER_EN = 0;
+        ( *run_mode_ptr ).WORK_MODE_CFG2_u._BITS.CSMA_EN = 0;
+    }
+    vRadioCfgWorkMode( run_mode_ptr );
+}
+
+void vRadioSetRssiAbsThValue( int8_t rssi )
+{
+    vRadioRegPageSel( 1 );
+    bRadioWriteReg( CMT2310A_RSSI_ABS_TH_REG, ( uint8_t )rssi );
+    vRadioRegPageSel( 0 );
+}
+
+void vRadioSetPjdDetWin( uint8_t pjd_win )            //0:4-jump,  1:6-jump,   2:8-jump,   3:10-jump
+{
+    pjd_win  &= 0x03;
+    pjd_win <<= 4;
+    vRadioRegPageSel( 1 );                                  //CMT2310A_RX_2FSK_REG_01 is in bank1
+    bRadioSetReg( CMT2310A_RX_2FSK_REG_01, pjd_win, 0x30 );
+    vRadioRegPageSel( 0 );
+}
+
+
+
+
+
+
+
+
+
+//
+//void vRadioSetFreq(const byte  *ptr)
+//{
+//  byte i;
+//  byte adr;
+//  vRadioRegPageSel(1);
+//  adr = CMT2310A_TX_FREQ_REG_00;
+//  for(i=0; i<4; i++)
+//      bSpiWriteByte(adr++, ptr[i]);
+//
+//  adr = CMT2310A_RX_FREQ_REG_01;
+//  for( ; i<8; i++)
+//      bSpiWriteByte(adr++, ptr[i]);
+//  vRadioRegPageSel(0);
+//}
+//
+
+
+
+
diff --git a/NSPE/WIFI_IOT/bsp/drivers/3_Ebyte_WirelessModule_Drivers/E48xMx/radio_mac.h b/NSPE/WIFI_IOT/bsp/drivers/3_Ebyte_WirelessModule_Drivers/E48xMx/radio_mac.h
new file mode 100755
index 0000000..89deed2
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/3_Ebyte_WirelessModule_Drivers/E48xMx/radio_mac.h
@@ -0,0 +1,49 @@
+#ifndef __RADIO_MAC_H
+
+#define __RADIO_MAC_H
+	
+#include "radio_hal.h"	
+#include "CMT2310A_def.h"
+#include "CMT2310A_reg.h"
+
+
+extern uint8_t  bRadioGetCurrentChannl(void);
+
+extern void     vRadioSetTxSeqNumberInitValue(FRAME_CFG *frm_cfg);
+extern uint16_t wRadioGetTxSeqNumberCurrent(FRAME_CFG *frm_cfg);
+extern void     vRadioSetTxFCS2(FRAME_CFG *frm_cfg);
+extern uint8_t  bRadioGetRxFCS2(FRAME_CFG *frm_cfg);
+extern void     vRadioSetPayloadLength(FRAME_CFG *frm_cfg);
+extern uint16_t vRadioGetPayloadLength(FRAME_CFG *frm_cfg);
+
+
+extern void     vRadioCfgPreamble(PREAMBLE_CFG *prm_ptr);
+extern void     vRadioCfgSyncWord(SYNC_CFG *sync_ptr);
+extern void     vRadioCfgNodeAddr(ADDR_CFG *node_addr_ptr);
+extern void     vRadioCfgCrc(CRC_CFG *crc_ptr);
+extern void     vRadioCfgCodeFormat(CODING_FORMAT_CFG *code_format_ptr);
+extern void     vRadioCfgFrameFormat(FRAME_CFG *frame_format_ptr);
+extern void     vRadioCfgWiSunFormat(WI_SUN_CFG *wi_sun_ptr);
+extern void     vRadioCdrTracingModeCfg(CDR_TRACING_CFG *cdr_ptr);
+
+extern void     vRadioCfgWorkMode(WORK_MODE_CFG *run_mode_ptr);
+extern void     vRadioReadRunModeCfg(void);
+extern uint8_t  bRadioGetTxDutyCycleDoneTimes(WORK_MODE_CFG *run_mode_ptr);
+extern uint8_t  bRadioGetTxResendDoneTimes(WORK_MODE_CFG *run_mode_ptr);
+extern uint8_t  bRadioGetCMSADoneTimes(WORK_MODE_CFG *run_mode_ptr);
+
+
+extern void     vRadioSendWithAck(boolean_t w_ack, FRAME_CFG *frame_format_ptr);
+extern void     vRadioEnableTxAck(boolean_t en_flg, WORK_MODE_CFG *run_mode_ptr);
+extern void     vRadioEnableRxAck(boolean_t en_flg, WORK_MODE_CFG *run_mode_ptr);
+extern uint8_t  bRadioGetFreqChanl(void);
+extern uint8_t  bRadioGetHopDoneTimes(void);
+extern void     vRadioCsmaEnable(boolean_t on_off, WORK_MODE_CFG *run_mode_ptr);
+extern void     vRadioSetRssiAbsThValue(int8_t rssi);
+extern void     vRadioSetPjdDetWin(uint8_t pjd_win);
+
+
+
+#endif	
+
+
diff --git a/NSPE/WIFI_IOT/bsp/drivers/3_Ebyte_WirelessModule_Drivers/E48xMx/radio_phy.c b/NSPE/WIFI_IOT/bsp/drivers/3_Ebyte_WirelessModule_Drivers/E48xMx/radio_phy.c
new file mode 100755
index 0000000..23bc3d2
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/3_Ebyte_WirelessModule_Drivers/E48xMx/radio_phy.c
@@ -0,0 +1,645 @@
+#include "radio_phy.h"
+
+/******************************
+**Name:  vRadioSetInterruptSel
+**Func:  Radio config INT1 & INT2 pin seleciton
+**Input: int1_sel, int2_sel,
+**
+**      CMT2310A_INT_MIX                (0<<0)                  // all interrupt mixed together
+**      CMT2310A_INT_ANT_LOCK           (1<<0)                  // antenna locked
+**      CMT2310A_INT_RSSI_PJD_VALID     (2<<0)                  // rssi and/or pjd valid
+**      CMT2310A_INT_PREAM_PASS         (3<<0)                  // preamble detected
+**      CMT2310A_INT_SYNC_PASS          (4<<0)                  // sync word detected
+**      CMT2310A_INT_ADDR_PASS          (5<<0)                  // node address detected
+**      CMT2310A_INT_CRC_PASS           (6<<0)                  // crc ok detected
+**      CMT2310A_INT_PKT_OK             (7<<0)                  // packet received detected
+**      CMT2310A_INT_PKT_DONE           (8<<0)                  // packet received detected, even wrong packet or collision
+**      CMT2310A_INT_SLEEP_TMO          (9<<0)                  // sleep timer time-out
+**      CMT2310A_INT_RX_TMO             (10<<0)                 // rx timer time-out
+**      CMT2310A_INT_RX_FIFO_NMTY       (11<<0)                 // rx fifo non-empty
+**      CMT2310A_INT_RX_FIFO_TH         (12<<0)                 // rx fifo threshold
+**      CMT2310A_INT_RX_FIFO_FULL       (13<<0)                 // rx fifo full
+**      CMT2310A_INT_RX_FIFO_WBYTE      (14<<0)                 // rx fifo write byte trigger
+**      CMT2310A_INT_RX_FIFO_OVF        (15<<0)                 // rx fifo overflow
+**      CMT2310A_INT_TX_DONE            (16<<0)                 // tx done
+**      CMT2310A_INT_TX_FIFO_NMTY       (17<<0)                 // tx fifo non-empty
+**      CMT2310A_INT_TX_FIFO_TH         (18<<0)                 // tx fifo threshold
+**      CMT2310A_INT_TX_FIFO_FULL       (19<<0)                 // tx fifo full
+**      CMT2310A_INT_STATE_IS_READY     (20<<0)                 // state is ready
+**      CMT2310A_INT_STATE_IS_FS        (21<<0)                 // state is FS
+**      CMT2310A_INT_STATE_IS_RX        (22<<0)                 // state is rx
+**      CMT2310A_INT_STATE_IS_TX        (23<<0)                 // state is tx
+**      CMT2310A_INT_LBD_STATUS         (24<<0)                 // LBD status
+**      CMT2310A_INT_API_CMD_FAILED     (25<<0)                 // API Command failed
+**      CMT2310A_INT_API_DONE           (26<<0)                 // API execute finish
+**      CMT2310A_INT_TX_DC_DONE         (27<<0)                 // ??
+**      CMT2310A_INT_ACK_RECV_FAILED    (28<<0)                 // ack recieve failed
+**      CMT2310A_INT_TX_RESEND_DONE     (29<<0)                 // tx re-send done
+**      CMT2310A_INT_NACK_RECV          (30<<0)                 // non-ack received
+**      CMT2310A_INT_SEQ_MATCH          (31<<0)                 // sequence number match
+**      CMT2310A_INT_CSMA_DONE          (32<<0)                 // CSMA done
+**      CMT2310A_INT_CCA_STATUS         (33<<0)                 // CCA status match
+**
+*Output: None
+********************************/
+void vRadioSetInt1Sel( uint8_t int1_sel )
+{
+    bRadioSetReg( CMT2310A_INT1_SEL_REG, int1_sel, CMT2310A_INT1_SEL_MASK );
+}
+
+void vRadioSetInt2Sel( uint8_t int2_sel )
+{
+    bRadioSetReg( CMT2310A_INT2_SEL_REG, int2_sel, CMT2310A_INT2_SEL_MASK );
+}
+
+/******************************
+**Name:  vRadioSetInterruptPolar
+**Func:  Radio config INT pin out polar mode
+**Input: int1_polar, FALSE: ative-high, normal-low
+*                    TRUE:  ative-low,  normal-high
+*        int2_polar, FALSE: ative-high, normal-low
+*                    TRUE:  ative-low,  normal-high
+*        int3_polar, FALSE: ative-high, normal-low
+*                    TRUE:  ative-low,  normal-high
+*Output: None
+********************************/
+void vRadioSetInt1Polar( boolean_t int1_polar )
+{
+    if( int1_polar )
+    {
+        bRadioSetReg( CMT2310A_CTL_REG_17, CMT2310A_INT1_POLAR, CMT2310A_INT1_POLAR );
+    }
+    else
+    {
+        bRadioSetReg( CMT2310A_CTL_REG_17, 0, CMT2310A_INT1_POLAR );
+    }
+}
+
+void vRadioSetInt2Polar( boolean_t int2_polar )
+{
+    if( int2_polar )
+    {
+        bRadioSetReg( CMT2310A_CTL_REG_17, CMT2310A_INT2_POLAR, CMT2310A_INT2_POLAR );
+    }
+    else
+    {
+        bRadioSetReg( CMT2310A_CTL_REG_17, 0, CMT2310A_INT2_POLAR );
+    }
+}
+
+void vRadioSetInt3Polar( boolean_t int3_polar )
+{
+    if( int3_polar )
+    {
+        bRadioSetReg( CMT2310A_CTL_REG_19, CMT2310A_INT3_POLAR, CMT2310A_INT3_POLAR );
+    }
+    else
+    {
+        bRadioSetReg( CMT2310A_CTL_REG_19, 0, CMT2310A_INT3_POLAR );
+    }
+}
+
+//######################################################################
+//                       RSSI
+//######################################################################
+
+/******************************
+**Name:  vRadioRssiUpdateSel
+**Func:  Radio rssi update select
+**Input: CMT2310A_RSSI_UPDATE_ALWAYS   ---- always
+**       CMT2310A_RSSI_UPDATE_PREAM_OK ---- when preamble ok
+**       CMT2310A_RSSI_UPDATE_SYNC_OK  ---- when sync ok
+**       CMT2310A_RSSI_UPDATE_PKT_DONE ---- when pkt done
+*Output: None
+********************************/
+void vRadioRssiUpdateSel( uint8_t sel )
+{
+    vRadioRegPageSel( 1 );              //CMT2310A_RX_RSSI_REG_00 is in page1
+    bRadioSetReg( CMT2310A_RX_RSSI_REG_00, sel, CMT2310A_RSSI_UPDATE_SEL_MASK );
+    vRadioRegPageSel( 0 );
+}
+
+
+/******************************
+**Name:  bRadioGetRssi
+**Func:  Radio get rssi value
+**Input: None
+*Output: rssi with sign
+********************************/
+uint8_t bRadioGetRssi( void )
+{
+    return( bRadioReadReg( CMT2310A_CTL_REG_34 ) );
+}
+
+/******************************
+**Name:  vRadioRssiConfig
+**Func:  Radio config Rssi
+**Input: None
+*Output: None
+********************************/
+void vRadioRssiConfig( RSSI_CFG rssi_cfg )
+{
+    vRadioRegPageSel( 1 );
+    bRadioSetReg( CMT2310A_RX_RSSI_REG_00, rssi_cfg.FRAME_CFG1_u.RSSI_CFG_REG, ( CMT2310A_COLL_STEP_SEL_MASK | CMT2310A_RSSI_UPDATE_SEL_MASK | CMT2310A_COLL_DET_EN ) );
+    bRadioWriteReg( CMT2310A_RSSI_ABS_TH_REG, rssi_cfg.RSSI_ABS_TH );
+    vRadioRegPageSel( 0 );
+}
+
+/******************************
+**Name:  vRadioRssiCalOffset
+**Func:  Radio config Rssi calibrate offset
+**Input: None
+*Output: None
+********************************/
+void vRadioRssiCalOffset( uint8_t cal_offset )
+{
+    vRadioRegPageSel( 0 );
+    bRadioWriteReg( CMT2310A_RSSI_CAL_OFFSET_REG, cal_offset );
+}
+
+
+
+//######################################################################
+//                       Misc
+//######################################################################
+/******************************
+**Name:  bRadioGetLbdValue
+**Func:  Radio get LBD value
+**Input: None
+*Output: LBD value
+********************************/
+uint8_t bRadioGetLbdValue( void )
+{
+    return( bRadioReadReg( CMT2310A_LBD_REG ) );
+}
+
+/******************************
+**Name:  vRadioSetLbdTH
+**Func:  Radio get LBD threshold value
+**Input: LBD threshold value
+*Output: None
+********************************/
+void vRadioSetLbdTH( uint8_t lbd_th )
+{
+    bRadioWriteReg( CMT2310A_LBD_TH_REG, lbd_th );
+}
+
+/******************************
+**Name:  bRadioGetTemperature
+**Func:  Radio get Temperature value
+**Input: None
+*Output:
+********************************/
+uint8_t bRadioGetTemperature( void )
+{
+    return( bRadioReadReg( CMT2310A_TEMP_REG ) );
+}
+
+/******************************
+**Name:  bRadioApiCommand
+**Func:  Radio get Temperature value
+**Input: api_cmd, API command code
+*Output:
+* note:  only support 0x01 command code
+********************************/
+boolean_t bRadioApiCommand( uint8_t api_cmd )
+{
+    uint16_t i;
+    bRadioWriteReg( CMT2310A_API_CMD_REG, api_cmd );
+    api_cmd |= CMT2310A_API_CMD_FLAG;
+    for( i = 0; i < 500; i++ )
+    {
+        delay1ms( 2 );
+        if( bRadioReadReg( CMT2310A_CTL_REG_09 ) == api_cmd )
+        {
+            return( TRUE );
+        }
+    }
+    return( FALSE );
+}
+
+/******************************
+**Name:  vRadioCdrModeCfg
+**Func:  Radio set CDR mode
+**Input: enum CDR_MODE
+*Output:
+********************************/
+void vRadioCdrModeCfg( enum CDR_MODE cdr_mode )
+{
+    vRadioRegPageSel( 1 );
+    bRadioSetReg( CMT2310A_RX_CDR_REG_00, cdr_mode, 0x03 );
+    vRadioRegPageSel( 0 );
+}
+
+/******************************
+**Name:  vRadioTxRampCfg
+**Func:  Radio set tx ramp
+**Input:
+**       tx_ramp_en: TRUE = enable; FALSE = disable
+**       tx_ramp_step: ramp value, about 1.9us/step
+*Output:
+********************************/
+void vRadioTxRampCfg( boolean_t tx_ramp_en, uint16_t  tx_ramp_step )
+{
+    vRadioRegPageSel( 1 );
+    if( tx_ramp_en )
+    {
+        bRadioSetReg( CMT2310A_TX_MODE_REG_00, ( 1 << 2 ), ( 1 << 2 ) );
+        bRadioWriteReg( CMT2310A_TX_PWR_REG_03, ( uint8_t )tx_ramp_step );
+        bRadioSetReg( CMT2310A_TX_PWR_REG_05, ( uint8_t )( ( tx_ramp_step >> 4 ) & 0xF0 ), 0xF0 );
+    }
+    else
+    {
+        bRadioSetReg( CMT2310A_TX_MODE_REG_00, ( 0 << 2 ), ( 1 << 2 ) );
+    }
+    vRadioRegPageSel( 0 );
+}
+
+/******************************
+**Name:  vRadioTxGaussianCfg
+**Func:  Radio set tx with Gaussian
+**Input:
+**       tx_gaus_en: TRUE = enable; FALSE = disable
+**       tx_gaus_bt: 0=0.3, 1=0.5, 2=0.8, 3=1.0
+*Output:
+********************************/
+void vRadioTxGaussianCfg( boolean_t tx_gaus_en, uint8_t tx_gaus_bt )
+{
+    uint8_t tmp = 0;
+    tmp   = ( tx_gaus_bt & 0x03 );
+    tmp <<= 5;
+    if( tx_gaus_en )
+    {
+        tmp |= 0x10;
+    }
+    vRadioRegPageSel( 1 );
+    bRadioSetReg( CMT2310A_TX_MODE_REG_00, tmp, 0x70 );
+    vRadioRegPageSel( 0 );
+}
+
+/******************************
+**Name:  vRadioAfcCfg
+**Func:  Radio set afc
+**Input:
+**       afc_en: TRUE = enable; FALSE = disable
+*Output:
+********************************/
+void vRadioAfcCfg( boolean_t afc_en )
+{
+    vRadioRegPageSel( 1 );
+    if( afc_en )
+    {
+        bRadioSetReg( CMT2310A_RX_AFC_REG_00, 0x01, 0x01 );
+    }
+    else
+    {
+        bRadioSetReg( CMT2310A_RX_AFC_REG_00, 0x00, 0x01 );
+    }
+    vRadioRegPageSel( 0 );
+}
+
+
+//######################################################################
+//                       Work State
+//######################################################################
+/******************************
+**Name:  bRadioGetState
+**Func:  Radio state
+**Input: None
+*Output: Radio State
+*        CMT2310A_STATE_IS_IDLE | CMT2310A_STATE_IS_SLEEP | CMT2310A_STATE_IS_READY | CMT2310A_STATE_IS_RFS | CMT2310A_STATE_IS_TFS | CMT2310A_STATE_IS_RX | CMT2310A_STATE_IS_TX
+* note:  page0
+********************************/
+uint8_t bRadioGetState( void )
+{
+    return( bRadioReadReg( CMT2310A_CHIP_MODE_STA_REG ) );
+}
+
+uint8_t bRadioSwitchWaiting( uint8_t targ_state )
+{
+    uint8_t i = 0;
+    do
+    {
+        delay10us( 2 );                     //Ô¼26us£¬¼ÓÉÏSPI·ÃÎÊÔ¼8us£¬ºÏ¼Æ33us²éѯһ´Î
+        if( bRadioGetState() == targ_state )
+        {
+            break;
+        }
+        i++;
+    }
+    while( i < 60 );
+    return( i );
+}
+
+uint8_t bRadioGoSleep( void )
+{
+    bRadioWriteReg( CMT2310A_CTL_REG_01, CMT2310A_GO_SLEEP );
+    return( bRadioSwitchWaiting( CMT2310A_STATE_IS_SLEEP ) );
+}
+
+uint8_t bRadioGoStandby( void )
+{
+    bRadioWriteReg( CMT2310A_CTL_REG_01, CMT2310A_GO_READY );
+    delay10us( 3 );
+    bRadioWriteReg( CMT2310A_CTL_REG_01, CMT2310A_GO_READY );
+    return( bRadioSwitchWaiting( CMT2310A_STATE_IS_READY ) );
+}
+
+uint8_t bRadioGoTx( void )
+{
+    bRadioWriteReg( CMT2310A_CTL_REG_01, CMT2310A_GO_TX );
+    return( bRadioSwitchWaiting( CMT2310A_STATE_IS_TX ) );
+}
+
+uint8_t bRadioGoRx( void )
+{
+    bRadioWriteReg( CMT2310A_CTL_REG_01, CMT2310A_GO_RX );
+    return( bRadioSwitchWaiting( CMT2310A_STATE_IS_RX ) );
+}
+
+uint8_t bRadioGoTxFS( void )
+{
+    bRadioWriteReg( CMT2310A_CTL_REG_01, CMT2310A_GO_TFS );
+    return( bRadioSwitchWaiting( CMT2310A_STATE_IS_TFS ) );
+}
+
+uint8_t bRadioGoRxFS( void )
+{
+    bRadioWriteReg( CMT2310A_CTL_REG_01, CMT2310A_GO_RFS );
+    return( bRadioSwitchWaiting( CMT2310A_STATE_IS_RFS ) );
+}
+
+//######################################################################
+//                       FIFO Control
+//######################################################################
+/******************************
+**Name:  vRadioSetFifoTH
+**Func:  Radio set fifo threshold value
+**Input: fifo_th
+*Output: None
+********************************/
+void vRadioSetFifoTH( uint16_t fifo_th )
+{
+    if( fifo_th >= 256 )
+    {
+        bRadioSetReg( CMT2310A_CTL_REG_19, CMT2310A_FIFO_TH_BIT8, CMT2310A_FIFO_TH_BIT8 );
+    }
+    else
+    {
+        bRadioSetReg( CMT2310A_CTL_REG_19, 0, CMT2310A_FIFO_TH_BIT8 );
+    }
+    bRadioWriteReg( CMT2310A_CTL_REG_20, ( uint8_t )fifo_th );
+}
+
+/******************************
+**Name:  vRadioFifoRetent
+**Func:  Radio set fifo retent
+**Input: cfg_en, FALSE: disable fifo retention
+*                TRUE:  enable fifo retention
+*Output: None
+* note:  fifo retention function active in sleep
+********************************/
+void vRadioFifoRetent( boolean_t cfg_en )
+{
+    if( cfg_en )
+    {
+        bRadioSetReg( CMT2310A_CTL_REG_19, 0, CMT2310A_PD_FIFO );
+    }
+    else
+    {
+        bRadioSetReg( CMT2310A_CTL_REG_19, CMT2310A_PD_FIFO, CMT2310A_PD_FIFO );
+    }
+}
+
+/******************************
+**Name:  vRadioFifoAutoClearBeforeRx
+**Func:  Radio set fifo auto clear when entry to Rx
+**Input: cfg_en, FALSE: disable fifo auto clear
+*                TRUE:  enable fifo auto clear
+*Output: None
+********************************/
+void vRadioFifoAutoClearGoRx( boolean_t cfg_en )
+{
+    if( cfg_en )
+    {
+        bRadioSetReg( CMT2310A_CTL_REG_19, CMT2310A_FIFO_AUTO_CLR_RX_EN, CMT2310A_FIFO_AUTO_CLR_RX_EN );
+    }
+    else
+    {
+        bRadioSetReg( CMT2310A_CTL_REG_19, 0, CMT2310A_FIFO_AUTO_CLR_RX_EN );
+    }
+}
+
+/******************************
+**Name:  vRadioFifoAutoRestoreWhenTxDone
+**Func:  Radio set fifo auto re-store when after Tx
+**Input: cfg_en, FALSE: disable fifo auto re-store
+*                TRUE:  enable fifo auto re-store
+*Output: None
+* none:  if need repeat send packet, this function should be enable
+********************************/
+void vRadioFifoAutoRestoreWhenTxDone( boolean_t cfg_en )
+{
+    if( cfg_en )
+    {
+        bRadioSetReg( CMT2310A_CTL_REG_19, CMT2310A_FIFO_AUTO_RES_TX_EN, CMT2310A_FIFO_AUTO_RES_TX_EN );
+    }
+    else
+    {
+        bRadioSetReg( CMT2310A_CTL_REG_19, 0, CMT2310A_FIFO_AUTO_RES_TX_EN );
+    }
+}
+
+/******************************
+**Name:  vRadioFifoMerge
+**Func:  Radio set fifo merge together
+**Input: cfg_en, FALSE: disable fifo merge, 128B for Tx, and 128B for Rx
+*                TRUE:  enable fifo merge, 256B for Tx or Rx
+*Output: None
+********************************/
+void vRadioFifoMerge( boolean_t cfg_en )
+{
+    if( cfg_en )
+    {
+        bRadioSetReg( CMT2310A_CTL_REG_19, CMT2310A_FIFO_MERGE_EN, CMT2310A_FIFO_MERGE_EN );
+    }
+    else
+    {
+        bRadioSetReg( CMT2310A_CTL_REG_19, 0, CMT2310A_FIFO_MERGE_EN );
+    }
+}
+
+/******************************
+**Name:  vRadioFifoTRxUsageSel
+**Func:  Radio set fifo used for Tx or Rx
+**Input: cfg_tx, FALSE: used for Rx
+*                TRUE:  used for Tx
+*Output: None
+* note:  when FIFO merge together active
+********************************/
+void vRadioFifoTRxUsageSel( boolean_t cfg_tx )
+{
+    if( cfg_tx )
+    {
+        bRadioSetReg( CMT2310A_CTL_REG_19, CMT2310A_FIFO_TX_RX_SEL, CMT2310A_FIFO_TX_RX_SEL );    //for rx
+    }
+    else
+    {
+        bRadioSetReg( CMT2310A_CTL_REG_19, 0, CMT2310A_FIFO_TX_RX_SEL );    //for tx
+    }
+}
+
+
+/******************************
+**Name:  vRadioFifoGetStatus
+**Func:  Radio get fifo status
+**Input: fifo_status
+*Output: None
+********************************/
+void vRadioFifoGetStatus( FIFO_STATUS_FLG* fifo_status )
+{
+    ( *fifo_status ).FIFO_FLG_REG = bRadioReadReg( CMT2310A_CTL_REG_28 );
+}
+
+/******************************
+**Name:  vRadioClearTxFifo
+**Func:  Radio clear tx fifo
+**Input: None
+*Output: None
+********************************/
+void vRadioClearTxFifo( void )
+{
+    bRadioSetReg( CMT2310A_CTL_REG_27, CMT2310A_TX_FIFO_CLR, CMT2310A_TX_FIFO_CLR );
+}
+
+/******************************
+**Name:  vRadioClearRxFifo
+**Func:  Radio clear rx fifo
+**Input: None
+*Output: None
+********************************/
+void vRadioClearRxFifo( void )
+{
+    bRadioSetReg( CMT2310A_CTL_REG_27, CMT2310A_RX_FIFO_CLR, CMT2310A_RX_FIFO_CLR );
+}
+
+/******************************
+**Name:  vRadioManualResetTxFifoPointer
+**Func:  Radio manual store tx fifo, tx fifo pointer reset
+*        can be resend the same message
+**Input: None
+*Output: None
+********************************/
+void vRadioManualResetTxFifoPointer( void )
+{
+    bRadioSetReg( CMT2310A_CTL_REG_27, CMT2310A_TX_FIFO_RESTORE, CMT2310A_TX_FIFO_RESTORE );
+}
+
+//######################################################################
+//                       Interrupt Control
+//######################################################################
+/******************************
+**Name:  vRadioInterruptSoucreCfg
+**Func:  Radio set interrupt source config
+**Input: int_src_ctrl
+*Output: None
+********************************/
+void vRadioInterruptSoucreCfg( INT_SRC_CFG* int_src_ctrl )
+{
+    bRadioWriteReg( CMT2310A_CTL_REG_18, ( *int_src_ctrl )._BYTE.INT_CTL1_REG );
+    bRadioWriteReg( CMT2310A_CTL_REG_21, ( *int_src_ctrl )._BYTE.INT_CTL2_REG );
+    bRadioWriteReg( CMT2310A_CTL_REG_23, ( *int_src_ctrl )._BYTE.INT_CTL3_REG );
+    bRadioWriteReg( CMT2310A_CTL_REG_14, ( *int_src_ctrl )._BYTE.INT_CTL4_REG );
+}
+
+/******************************
+**Name:  vRadioInterruptSoucreFlag
+**Func:  Radio get interrupt source flag
+**Input: int_src_flag
+*Output: None
+********************************/
+void vRadioInterruptSoucreFlag( INT_SRC_FLG* int_src_flag )
+{
+    ( *int_src_flag )._BYTE.INT_FLAG1_REG = bRadioReadReg( CMT2310A_CTL_REG_24 );
+    ( *int_src_flag )._BYTE.INT_FLAG2_REG = bRadioReadReg( CMT2310A_CTL_REG_26 );
+    ( *int_src_flag )._BYTE.INT_FLAG3_REG = bRadioReadReg( CMT2310A_CTL_REG_30 );
+    ( *int_src_flag )._BYTE.INT_FLAG4_REG = bRadioReadReg( CMT2310A_CTL_REG_32 );
+}
+
+/******************************
+**Name:  vRadioInterruptSoucreClear
+**Func:  Radio clear interrupt source
+**Input: int_src_clr
+*Output: None
+********************************/
+void vRadioInterruptSoucreClear( INT_SRC_CLR* int_src_clr )
+{
+    bRadioWriteReg( CMT2310A_CTL_REG_24, ( *int_src_clr )._BYTE.INT_CLR1_REG );
+    bRadioWriteReg( CMT2310A_CTL_REG_25, ( *int_src_clr )._BYTE.INT_CLR2_REG );
+    bRadioWriteReg( CMT2310A_CTL_REG_29, ( *int_src_clr )._BYTE.INT_CLR3_REG );
+    bRadioWriteReg( CMT2310A_CTL_REG_31, ( *int_src_clr )._BYTE.INT_CLR4_REG );
+}
+
+
+
+
+//######################################################################
+//                       Config
+//######################################################################
+
+/******************************
+**Name:  vRadioConfigPageReg
+**Func:  Radio config page 0/1 regsisters
+*        page0, start address from 0x28
+*        page1, start address from 0x00
+**Input: page_sel: Page0, Page1
+*        reg_ptr:
+*        reg_len:
+*Output: None
+* note:  Page2 is not support burst mode
+********************************/
+void vRadioConfigPageReg( byte page_sel, uint8_t const reg_ptr[], uint8_t reg_len )
+{
+    vRadioRegPageSel( page_sel );
+    vRadioBurstWriteRegs( ( byte* )reg_ptr, reg_len );
+    vRadioRegPageSel( 0 );
+}
+
+void vRadioReadPageReg( byte page_sel, uint8_t reg_ptr[], uint8_t reg_len )
+{
+    vRadioRegPageSel( page_sel );
+    vRadioBurstReadRegs( reg_ptr, reg_len );
+    vRadioRegPageSel( 0 );
+}
+
+
+boolean_t bRadioIsExist( void )
+{
+    uint8_t back, dat;
+    back = bRadioReadReg( CMT2310A_CTL_REG_12 );
+    bRadioWriteReg( CMT2310A_CTL_REG_12, 0xAA );
+    dat = bRadioReadReg( CMT2310A_CTL_REG_12 );
+    bRadioWriteReg( CMT2310A_CTL_REG_12, back );
+    if( 0xAA == dat )
+    {
+        return( TRUE );
+    }
+    else
+    {
+        return( FALSE );
+    }
+}
+//0x00231000
+uint32_t lRadioChipVersion( void )
+{
+    uint32_t chip_ver = 0;
+    vRadioRegPageSel( 2 );
+    chip_ver   = bRadioReadReg( CMT2310A_CHIP_VERSION_00 );
+    chip_ver <<= 8;
+    chip_ver  |= bRadioReadReg( CMT2310A_CHIP_VERSION_01 );
+    chip_ver <<= 8;
+    chip_ver  |= bRadioReadReg( CMT2310A_CHIP_VERSION_02 );
+    vRadioRegPageSel( 0 );
+    return( chip_ver );
+}
+
diff --git a/NSPE/WIFI_IOT/bsp/drivers/3_Ebyte_WirelessModule_Drivers/E48xMx/radio_phy.h b/NSPE/WIFI_IOT/bsp/drivers/3_Ebyte_WirelessModule_Drivers/E48xMx/radio_phy.h
new file mode 100755
index 0000000..e6fe564
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/3_Ebyte_WirelessModule_Drivers/E48xMx/radio_phy.h
@@ -0,0 +1,64 @@
+#ifndef __RADIO_PHY_H
+
+#define __RADIO_PHY_H
+#include "stm8l15x.h"
+#include "radio_hal.h"
+#include "CMT2310A_def.h"
+#include "CMT2310A_reg.h"
+
+
+extern void     vRadioSetInt1Sel( uint8_t int1_sel );
+extern void     vRadioSetInt2Sel( uint8_t int2_sel );
+extern void     vRadioSetInt1Polar( boolean_t int1_polar );
+extern void     vRadioSetInt2Polar( boolean_t int2_polar );
+extern void     vRadioSetInt3Polar( boolean_t int3_polar );
+
+
+extern void     vRadioRssiUpdateSel( uint8_t sel );
+extern uint8_t  bRadioGetRssi( void );
+extern void     vRadioRssiConfig( RSSI_CFG rssi_cfg );
+extern void     vRadioRssiCalOffset( uint8_t cal_offset );
+
+extern uint8_t  bRadioGetLbdValue( void );
+extern void     vRadioSetLbdTH( uint8_t lbd_th );
+extern uint8_t  bRadioGetTemperature( void );
+extern boolean_t        bRadioApiCommand( uint8_t api_cmd );
+extern void     vRadioCdrModeCfg( enum CDR_MODE cdr_mode );
+extern void     vRadioTxRampCfg( boolean_t tx_ramp_en, uint16_t  tx_ramp_step );
+extern void     vRadioTxGaussianCfg( boolean_t tx_gaus_en, uint8_t tx_gaus_bt );
+extern void     vRadioAfcCfg( boolean_t afc_en );
+
+extern uint8_t  bRadioGetState( void );
+extern uint8_t  bRadioGoSleep( void );
+extern uint8_t  bRadioGoStandby( void );
+extern uint8_t  bRadioGoTx( void );
+extern uint8_t  bRadioGoRx( void );
+extern uint8_t  bRadioGoTxFS( void );
+extern uint8_t  bRadioGoRxFS( void );
+
+
+extern void     vRadioSetFifoTH( uint16_t fifo_th );
+extern void     vRadioFifoRetent( boolean_t cfg_en );
+extern void     vRadioFifoAutoClearGoRx( boolean_t cfg_en );
+extern void     vRadioFifoAutoRestoreWhenTxDone( boolean_t cfg_en );
+extern void     vRadioFifoMerge( boolean_t cfg_en );
+extern void     vRadioFifoTRxUsageSel( boolean_t cfg_tx );
+extern void     vRadioFifoGetStatus( FIFO_STATUS_FLG* fifo_status );
+extern void     vRadioClearTxFifo( void );
+extern void     vRadioClearRxFifo( void );
+extern void     vRadioManualResetTxFifoPointer( void );
+  
+extern void     vRadioInterruptSoucreCfg( INT_SRC_CFG* int_src_ctrl );
+extern void     vRadioInterruptSoucreFlag( INT_SRC_FLG* int_src_flag );
+extern void     vRadioInterruptSoucreClear( INT_SRC_CLR* int_src_clr );
+  
+  
+extern void     vRadioConfigPageReg( byte page_sel, uint8_t const reg_ptr[], uint8_t reg_len );
+extern void     vRadioReadPageReg( byte page_sel, uint8_t reg_ptr[], uint8_t reg_len );
+extern boolean_t        bRadioIsExist( void );
+extern uint32_t lRadioChipVersion( void );
+
+#endif
+
+
+
diff --git a/NSPE/WIFI_IOT/bsp/drivers/3_Ebyte_WirelessModule_Drivers/E48xMx/radio_spi.c b/NSPE/WIFI_IOT/bsp/drivers/3_Ebyte_WirelessModule_Drivers/E48xMx/radio_spi.c
new file mode 100755
index 0000000..9c23b0e
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/3_Ebyte_WirelessModule_Drivers/E48xMx/radio_spi.c
@@ -0,0 +1,108 @@
+#include "radio_spi.h"
+
+/******************************
+**Name: vSpiMasterInit
+**Func: SPI Master
+**Input: None
+*Output: None
+********************************/
+void vSpiMasterInit( void )
+{
+    /* ÒѾ­³õʼ»¯ÁËSPI ÕâÀïÌø¹ý*/
+}
+
+
+uint8_t bSpiWriteByte( uint8_t spi_adr, uint8_t spi_dat )
+{
+    uint8_t ret;
+  
+    spi_adr &= 0x7F;
+  
+    /* SPI Ƭѡ CS */
+#if EBYTE_PORT_SPI_CS_SOFTWARE
+    Ebyte_Port_SpiCsIoControl( 0 );
+#endif
+    
+    Ebyte_Port_SpiTransmitAndReceivce(spi_adr);
+    
+    ret = Ebyte_Port_SpiTransmitAndReceivce(spi_dat);
+    
+    /* SPI Ƭѡ CS */
+#if EBYTE_PORT_SPI_CS_SOFTWARE
+    Ebyte_Port_SpiCsIoControl( 1 );
+#endif
+    
+    return ret;
+}
+
+uint8_t bSpiReadByte( uint8_t spi_adr )
+{
+    uint8_t ret;
+  
+    spi_adr |= 0x80;
+  
+    /* SPI Ƭѡ CS */
+#if EBYTE_PORT_SPI_CS_SOFTWARE
+    Ebyte_Port_SpiCsIoControl( 0 );
+#endif
+    
+    Ebyte_Port_SpiTransmitAndReceivce(spi_adr);
+    
+    ret = Ebyte_Port_SpiTransmitAndReceivce(0x00);
+    
+    /* SPI Ƭѡ CS */
+#if EBYTE_PORT_SPI_CS_SOFTWARE
+    Ebyte_Port_SpiCsIoControl( 1 );
+#endif
+    
+    return ret;
+}
+
+void vSpiBurstWrite( uint8_t spi_adr, uint8_t spi_dat[], uint8_t spi_length )
+{
+    uint8_t i;
+    
+    spi_adr &= 0x7F;  
+    
+        /* SPI Ƭѡ CS */
+#if EBYTE_PORT_SPI_CS_SOFTWARE
+    Ebyte_Port_SpiCsIoControl( 0 );
+#endif
+    
+    Ebyte_Port_SpiTransmitAndReceivce(spi_adr);
+    
+    for(i=0; i<spi_length; i++)
+    {
+        Ebyte_Port_SpiTransmitAndReceivce(spi_dat[i]);
+    }
+    
+    /* SPI Ƭѡ CS */
+#if EBYTE_PORT_SPI_CS_SOFTWARE
+    Ebyte_Port_SpiCsIoControl( 1 );
+#endif
+}
+
+void vSpiBurstRead( uint8_t spi_adr, uint8_t spi_dat[], uint8_t spi_length )
+{
+    uint8_t i;
+    
+    spi_adr |= 0x80;
+    
+    /* SPI Ƭѡ CS */
+#if EBYTE_PORT_SPI_CS_SOFTWARE
+    Ebyte_Port_SpiCsIoControl( 0 );
+#endif
+    
+    Ebyte_Port_SpiTransmitAndReceivce(spi_adr);  
+    
+    for(i=0; i<spi_length; i++)
+    {
+       spi_dat[i] = Ebyte_Port_SpiTransmitAndReceivce(0x00);
+    }    
+  
+    /* SPI Ƭѡ CS */
+#if EBYTE_PORT_SPI_CS_SOFTWARE
+    Ebyte_Port_SpiCsIoControl( 1 );
+#endif
+}
+
diff --git a/NSPE/WIFI_IOT/bsp/drivers/3_Ebyte_WirelessModule_Drivers/E48xMx/radio_spi.h b/NSPE/WIFI_IOT/bsp/drivers/3_Ebyte_WirelessModule_Drivers/E48xMx/radio_spi.h
new file mode 100755
index 0000000..3660ca0
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/3_Ebyte_WirelessModule_Drivers/E48xMx/radio_spi.h
@@ -0,0 +1,16 @@
+#ifndef __RADIO_SPI_H
+
+#define __RADIO_SPI_H
+
+#include "stm8l15x.h"
+
+#include "ebyte_port.h"
+extern void vSpiMasterInit( void );
+extern uint8_t bSpiWriteByte( uint8_t spi_adr, uint8_t spi_dat );
+extern uint8_t bSpiReadByte( uint8_t spi_adr );
+extern void vSpiBurstWrite( uint8_t spi_adr, uint8_t spi_dat[], uint8_t spi_length );
+extern void vSpiBurstRead( uint8_t spi_adr, uint8_t spi_dat[], uint8_t spi_length );
+
+#endif
+
+
diff --git a/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x.h b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x.h
new file mode 100755
index 0000000..94c056d
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x.h
@@ -0,0 +1,3024 @@
+/**
+  ******************************************************************************
+  * @file    stm8l15x.h
+  * @author  MCD Application Team
+  * @version V1.6.0
+  * @date    28-June-2013
+  * @brief   This file contains all the peripheral register's definitions, bits
+  *          definitions and memory mapping for STM8L15x devices.
+  ******************************************************************************
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ****************************************************************************** 
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM8L15x_H
+ #define __STM8L15x_H
+
+/** @addtogroup STM8L15x_StdPeriph_Driver
+  * @{
+  */ 
+/* Uncomment the line below according to the target STM8L15x device used in your
+   application
+  */
+/* #define STM8L15X_LD */     /*!< STM8L15X_LD: STM8L15x Low density devices */
+#define STM8L15X_MD     /*!< STM8L15X_MD: STM8L15x Medium density devices */
+/* #define STM8L15X_MDP */    /*!< STM8L15X_MDP: STM8L15x Medium density plus devices */
+/* #define STM8L15X_HD */     /*!< STM8L15X_HD: STM8L15x/16x High density devices */
+/* #define STM8L05X_LD_VL  */  /*!< STM8L05X_LD_VL: STM8L051xx3 Low density value line devices */
+/* #define STM8L05X_MD_VL */  /*!< STM8L05X_MD_VL: STM8L052xx6 Medium density value line devices */
+/* #define STM8L05X_HD_VL */  /*!< STM8L05X_HD_VL: STM8L052xx8 High density value line devices */
+/* #define STM8AL31_L_MD */   /*!< STM8AL31_L_MD: STM8AL3x Medium density devices */
+
+
+/*  Tip: To avoid modifying this file each time you need to switch between these
+        devices, you can define the device in your toolchain compiler preprocessor.
+
+ - Low density STM8L15x devices are STM8L151C3, STM8L151K3, STM8L151G3, STM8L151F3,
+   STM8L151C2, STM8L151K2, STM8L151G2 and STM8L151F2 microcontrollers where the 
+   Flash memory density ranges between 4 and 8 Kbytes.
+ - Medium density STM8L15x devices are STM8L151C4, STM8L151C6, STM8L152C4,
+   STM8L152C6, STM8L151K4, STM8L151K6, STM8L152K4, STM8L152K6, STM8L151G4,
+   STM8L151G6, STM8L152G4 and STM8L152G6 microcontrollers where the Flash memory
+   density ranges between 16 and 32 Kbytes.
+ - Medium density Plus devices are STM8L151R6, STM8L152R6 microcontrollers where
+  the Flash memory density is fixed and equal to 32 Kbytes and a wider range of
+  peripheral than the medium density devices.
+ - High density STM8L15x devices are STM8L151x8, STM8L152x8, STM8L162R8 and STM8L162M8
+   microcontrollers where the Flash memory density is fixed and equal to 64 Kbytes with 
+   the same peripheral set than Medium Density Plus devices.
+ - Value line low density STM8L05xx devices are STM8L051x3 microcontrollers
+   with 8-KB Flash
+ - Value line medium density STM8L05xx devices are STM8L052x6 microcontrollers 
+   with 32-KB Flash
+ - Value line high density STM8L05xx devices: STM8L052x8 microcontrollers
+   with 64-KB Flash
+ - Medium density STM8AL31xx/STM8AL3Lxx devices: STM8AL3168, STM8AL3166, 
+   STM8AL3148,STM8AL3146, STM8AL3138, STM8AL3136, STM8AL3L68, STM8AL3L66, 
+   STM8AL3L48, STM8AL3L46 microcontrollers with 8-KB, 16-KB or 32-KB Flash
+ */
+
+#if !defined (STM8L15X_MD) && !defined (STM8L15X_MDP) && !defined (STM8L15X_HD) && !defined (STM8L15X_LD) \
+&& !defined (STM8L05X_LD_VL) && !defined (STM8L05X_MD_VL) && !defined (STM8L05X_HD_VL) && !defined (STM8AL31_L_MD)
+ #error "Please select first the target STM8L device used in your application (in stm8l15x.h file)"
+#endif
+
+/******************************************************************************/
+/*                   Library configuration section                            */
+/******************************************************************************/
+/* Check the used compiler */
+#if defined(__CSMC__)
+ #define _COSMIC_
+#elif defined(__RCSTM8__)
+ #define _RAISONANCE_
+#elif defined(__ICCSTM8__)
+ #define _IAR_
+#else
+ #error "Unsupported Compiler!"          /* Compiler defines not found */
+#endif
+
+#if !defined  USE_STDPERIPH_DRIVER
+/* Comment the line below if you will not use the peripherals drivers.
+   In this case, these drivers will not be included and the application code will be
+   based on direct access to peripherals registers */
+ #define USE_STDPERIPH_DRIVER
+#endif
+
+/**
+ * @brief In the following line adjust the value of External High Speed oscillator (HSE)
+   used in your application
+
+   Tip: To avoid modifying this file each time you need to use different HSE, you
+        can define the HSE value in your toolchain compiler preprocessor.
+  */
+#if !defined  HSE_VALUE
+ #define HSE_VALUE   ((uint32_t)16000000) /*!< Typical Value of the HSE in Hz */
+#endif /* HSE_VALUE */
+
+/**
+  * @brief Definition of External Low Speed oscillator (LSE) frequency
+  */
+#if !defined  LSE_VALUE
+ #define LSE_VALUE   ((uint32_t)32768)   /*!< Typical Value of the LSE in Hz */
+#endif /* LSE_VALUE */
+/**
+  * @brief Definition of Device on-chip RC oscillator frequencies
+  */
+#if !defined  HSI_VALUE 
+ #define HSI_VALUE   ((uint32_t)16000000) /*!< Typical Value of the HSI in Hz */
+#endif /* HSI_VALUE */
+
+#if !defined  LSI_VALUE
+ #define LSI_VALUE   ((uint32_t)38000)    /*!< Typical Value of the LSI in Hz */
+#endif /* LSI_VALUE */
+
+#ifdef _COSMIC_
+ #define FAR  @far
+ #define NEAR @near
+ #define TINY @tiny
+ #define EEPROM @eeprom
+ #define CONST  const
+#elif defined (_RAISONANCE_) /* __RCSTM8__ */
+ #define FAR  far
+ #define NEAR data
+ #define TINY page0
+ #define EEPROM eeprom
+ #define CONST  code
+ #if defined (STM8L15X_MD) || defined (STM8L15X_MDP) || defined (STM8L05X_MD_VL) || \
+ defined (STM8AL31_L_MD)
+  /*!< Used with memory Models for code less than 64K */
+  #define MEMCPY memcpy
+ #elif defined (STM8L15X_HD) || defined (STM8L05X_HD_VL)
+   /*!< Used with memory Models for code higher than 64K */
+  #define MEMCPY fmemcpy
+ #endif /* STM8L15X_MD or STM8L15X_MDP or STM8L05X_MD_VL or STM8AL31_L_MD*/ 
+#else /*_IAR_*/
+ #define FAR  __far
+ #define NEAR __near
+ #define TINY __tiny
+ #define EEPROM __eeprom
+ #define CONST  const
+#endif /* __CSMC__ */
+
+/**
+  * @brief Legacy definition
+  */
+#define __CONST  CONST
+
+#if defined (STM8L15X_MD) || defined (STM8L15X_MDP) || defined (STM8L15X_LD) || \
+defined (STM8L05X_LD_VL) || defined (STM8L05X_MD_VL) || defined (STM8AL31_L_MD)
+/*!< Used with memory Models for code smaller than 64K */
+ #define PointerAttr NEAR
+ #define MemoryAddressCast uint16_t
+#elif defined (STM8L15X_HD) || defined (STM8L05X_HD_VL)
+/*!< Used with memory Models for code higher than 64K */
+ #define PointerAttr FAR
+ #define MemoryAddressCast uint32_t
+#endif /* STM8L15X_MD or STM8L15X_MDP or STM8L15X_LD or STM8L05X_LD_VL or STM8L05X_MD_VL
+          or STM8AL31_L_MD */
+
+/* Uncomment the line below to enable the FLASH functions execution from RAM */
+#if !defined (RAM_EXECUTION)
+/* #define RAM_EXECUTION  (1) */
+#endif /* RAM_EXECUTION */
+
+#ifdef RAM_EXECUTION
+ #ifdef _COSMIC_
+   #define IN_RAM(a) a
+ #elif defined (_RAISONANCE_) /* __RCSTM8__ */
+   #define IN_RAM(a) a inram
+ #else /*_IAR_*/
+  #define IN_RAM(a) __ramfunc a
+ #endif /* _COSMIC_ */
+#else 
+  #define IN_RAM(a) a
+#endif /* RAM_EXECUTION */
+
+/*!< [31:16] STM8L15X Standard Peripheral Library main version */
+#define __STM8L15X_STDPERIPH_VERSION_MAIN   ((uint8_t)0x01) /*!< [31:24] main version */                                  
+#define __STM8L15X_STDPERIPH_VERSION_SUB1   ((uint8_t)0x06) /*!< [23:16] sub1 version */
+#define __STM8L15X_STDPERIPH_VERSION_SUB2   ((uint8_t)0x00) /*!< [15:8]  sub2 version */
+#define __STM8L15X_STDPERIPH_VERSION_RC     ((uint8_t)0x00) /*!< [7:0]  release candidate */ 
+#define __STM8L15X_STDPERIPH_VERSION       ( (__STM8L15X_STDPERIPH_VERSION_MAIN << 24)\
+                                          |(__STM8L15X_STDPERIPH_VERSION_SUB1 << 16)\
+                                          |(__STM8L15X_STDPERIPH_VERSION_SUB2 << 8)\
+                                          |(__STM8L15X_STDPERIPH_VERSION_RC))
+
+/******************************************************************************/
+
+/* Includes ------------------------------------------------------------------*/
+
+/* Exported types and constants ----------------------------------------------*/
+
+/** @addtogroup Exported_types
+  * @{
+  */
+
+/**
+ * IO definitions
+ *
+ * define access restrictions to peripheral registers
+ */
+#define     __I     volatile const   /*!< defines 'read only' permissions     */
+#define     __O     volatile         /*!< defines 'write only' permissions    */
+#define     __IO    volatile         /*!< defines 'read / write' permissions  */
+
+/*!< Signed integer types  */
+typedef   signed char     int8_t;
+typedef   signed short    int16_t;
+typedef   signed long     int32_t;
+
+/*!< Unsigned integer types  */
+typedef unsigned char     uint8_t;
+typedef unsigned short    uint16_t;
+typedef unsigned long     uint32_t;
+
+/*!< STM8Lx Standard Peripheral Library old types (maintained for legacy purpose) */
+
+typedef int32_t  s32;
+typedef int16_t s16;
+typedef int8_t  s8;
+
+typedef uint32_t  u32;
+typedef uint16_t u16;
+typedef uint8_t  u8;
+
+
+typedef enum {FALSE = 0, TRUE = !FALSE} bool;
+
+typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus, BitStatus, BitAction;
+
+typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
+
+#define U8_MAX     (255)
+#define S8_MAX     (127)
+#define S8_MIN     (-128)
+#define U16_MAX    (65535u)
+#define S16_MAX    (32767)
+#define S16_MIN    (-32768)
+#define U32_MAX    (4294967295uL)
+#define S32_MAX    (2147483647)
+#define S32_MIN    (-2147483648uL)
+
+/**
+  * @}
+  */
+
+/** @addtogroup MAP_FILE_Exported_Types_and_Constants
+  * @{
+  */
+
+/******************************************************************************/
+/*                          IP registers structures                           */
+/******************************************************************************/
+
+/*----------------------------------------------------------------------------*/
+/**
+  * @brief General Purpose I/Os (GPIO)
+  */
+typedef struct GPIO_struct
+{
+  __IO uint8_t ODR; /*!< Output Data Register */
+  __IO uint8_t IDR; /*!< Input Data Register */
+  __IO uint8_t DDR; /*!< Data Direction Register */
+  __IO uint8_t CR1; /*!< Configuration Register 1 */
+  __IO uint8_t CR2; /*!< Configuration Register 2 */
+}
+GPIO_TypeDef;
+
+/** @addtogroup GPIO_Registers_Reset_Value
+  * @{
+  */
+#define GPIO_ODR_RESET_VALUE ((uint8_t)0x00)
+#define GPIO_DDR_RESET_VALUE ((uint8_t)0x00)
+#define GPIO_CR1_RESET_VALUE ((uint8_t)0x00)
+#define GPIO_CR2_RESET_VALUE ((uint8_t)0x00)
+/**
+  * @}
+  */
+/*----------------------------------------------------------------------------*/
+
+/**
+  * @brief Real-Time Clock (RTC) peripheral registers.
+  */
+typedef struct RTC_struct
+{
+  __IO uint8_t TR1; /*!<  Time  Register  1*/
+  __IO uint8_t TR2; /*!<  Time  Register  2*/
+  __IO uint8_t TR3; /*!<  Time  Register  3*/
+
+  uint8_t RESERVED0;
+
+  __IO uint8_t DR1; /*!<  Date  Register  1*/
+  __IO uint8_t DR2; /*!<  Date  Register  2*/
+  __IO uint8_t DR3; /*!<  Date  Register  3*/
+
+  uint8_t RESERVED1;
+
+  __IO uint8_t CR1; /*!<  Control  Register  1*/
+  __IO uint8_t CR2; /*!<  Control  Register  2*/
+  __IO uint8_t CR3; /*!<  Control  Register  3*/
+
+  uint8_t RESERVED2;
+
+  __IO uint8_t ISR1; /*!<  Initialisation and Status  Register 1 */
+  __IO uint8_t ISR2; /*!<  Initialisation and Status  Register 2 */
+
+  uint8_t RESERVED3;
+  uint8_t RESERVED4;
+
+  __IO uint8_t SPRERH; /*!<  Synchronous Prediv high  Register  */
+  __IO uint8_t SPRERL; /*!<  Synchronous Prediv Low Register  */
+  __IO uint8_t APRER;  /*!<  Asynchronous Prediv  Register  */
+
+  uint8_t RESERVED5;
+
+  __IO uint8_t WUTRH; /*!<  Wake-Up Timer High Register  */
+  __IO uint8_t WUTRL; /*!<  Wake-Up Timer  Low Register  */
+
+  uint8_t RESERVED6;
+
+  __IO uint8_t SSRH; /*!< Sub Second High Register  */
+  __IO uint8_t SSRL; /*!< Sub Second Low Register  */
+
+  __IO uint8_t WPR;  /*!< Write Protection Register  */
+
+  __IO uint8_t SHIFTRH; /*!< Shift control High Register  */
+  __IO uint8_t SHIFTRL; /*!<  Shift control Low Register  */
+
+  __IO uint8_t ALRMAR1; /*!<  ALARM A  Register 1  */
+  __IO uint8_t ALRMAR2; /*!<  ALARM A  Register 2 */
+  __IO uint8_t ALRMAR3; /*!<  ALARM A  Register 3 */
+  __IO uint8_t ALRMAR4; /*!<  ALARM A  Register 4 */
+
+  uint8_t RESERVED7[4];
+
+  __IO uint8_t ALRMASSRH; /*!<  ALARM A Subsecond Register High */
+  __IO uint8_t ALRMASSRL; /*!<  ALARM A Subsecond Register Low  */
+  __IO uint8_t ALRMASSMSKR; /*!<  ALARM A Subsecond Mask Register  */
+
+  uint8_t RESERVED8[3];
+
+  __IO uint8_t CALRH; /*!<  Calibration register high  */
+  __IO uint8_t CALRL; /*!<  Calibration register low  */
+
+  __IO uint8_t TCR1; /*!<  Tamper control register 1   */
+  __IO uint8_t TCR2; /*!<  Tamper control register 2  */
+}
+RTC_TypeDef;
+
+/** @addtogroup RTC_Registers_Reset_Value
+  * @{
+  */
+#define RTC_TR1_RESET_VALUE       ((uint8_t)0x00)
+#define RTC_TR2_RESET_VALUE       ((uint8_t)0x00)
+#define RTC_TR3_RESET_VALUE       ((uint8_t)0x00)
+
+#define RTC_DR1_RESET_VALUE       ((uint8_t)0x01)
+#define RTC_DR2_RESET_VALUE       ((uint8_t)0x21)
+#define RTC_DR3_RESET_VALUE       ((uint8_t)0x00)
+
+#define RTC_CR1_RESET_VALUE       ((uint8_t)0x00)
+#define RTC_CR2_RESET_VALUE       ((uint8_t)0x00)
+#define RTC_CR3_RESET_VALUE       ((uint8_t)0x00)
+
+#define RTC_ISR1_RESET_VALUE      ((uint8_t)0x07)
+#define RTC_ISR2_RESET_VALUE      ((uint8_t)0x00)
+
+#define RTC_SPRERH_RESET_VALUE    ((uint8_t)0x00)
+#define RTC_SPRERL_RESET_VALUE    ((uint8_t)0xFF)
+#define RTC_APRER_RESET_VALUE     ((uint8_t)0x7F)
+
+#define RTC_WUTRH_RESET_VALUE     ((uint8_t)0xFF)
+#define RTC_WUTRL_RESET_VALUE     ((uint8_t)0xFF)
+
+#define RTC_WPR_RESET_VALUE       ((uint8_t)0x00)
+
+#define RTC_ALRMAR1_RESET_VALUE   ((uint8_t)0x00)
+#define RTC_ALRMAR2_RESET_VALUE   ((uint8_t)0x00)
+#define RTC_ALRMAR3_RESET_VALUE   ((uint8_t)0x00)
+#define RTC_ALRMAR4_RESET_VALUE   ((uint8_t)0x00)
+
+#define RTC_SHIFTRH_RESET_VALUE   ((uint8_t)0x00)
+#define RTC_SHIFTRL_RESET_VALUE   ((uint8_t)0x00)
+
+#define RTC_ALRMASSRH_RESET_VALUE   ((uint8_t)0x00)
+#define RTC_ALRMASSRL_RESET_VALUE   ((uint8_t)0x00)
+#define RTC_ALRMASSMSKR_RESET_VALUE   ((uint8_t)0x00)
+
+#define RTC_CALRH_RESET_VALUE   ((uint8_t)0x00)
+#define RTC_CALRL_RESET_VALUE   ((uint8_t)0x00)
+
+#define RTC_TCR1_RESET_VALUE   ((uint8_t)0x00)
+#define RTC_TCR2_RESET_VALUE   ((uint8_t)0x00)
+
+/**
+  * @}
+  */
+
+/** @addtogroup RTC_Registers_Bits_Definition
+  * @{
+  */
+
+/* Bits definition for RTC_TR1 register*/
+#define RTC_TR1_ST               ((uint8_t)0x70)
+#define RTC_TR1_SU               ((uint8_t)0x0F)
+
+/* Bits definition for RTC_TR2 register*/
+#define RTC_TR2_MNT              ((uint8_t)0x70)
+#define RTC_TR2_MNU              ((uint8_t)0x0F)
+
+/* Bits definition for RTC_TR3 register*/
+#define RTC_TR3_PM               ((uint8_t)0x40)
+#define RTC_TR3_HT               ((uint8_t)0x30)
+#define RTC_TR3_HU               ((uint8_t)0x0F)
+
+/* Bits definition for RTC_DR1 register*/
+#define RTC_DR1_DT               ((uint8_t)0x30)
+#define RTC_DR1_DU               ((uint8_t)0x0F)
+
+/* Bits definition for RTC_DR2 register*/
+#define RTC_DR2_WDU              ((uint8_t)0xE0)
+#define RTC_DR2_MT               ((uint8_t)0x10)
+#define RTC_DR2_MU               ((uint8_t)0x0F)
+
+/* Bits definition for RTC_DR3 register*/
+#define RTC_DR3_YT               ((uint8_t)0xF0)
+#define RTC_DR3_YU               ((uint8_t)0x0F)
+
+/* Bits definition for RTC_CR1 register*/
+#define RTC_CR1_FMT              ((uint8_t)0x40)
+#define RTC_CR1_RATIO            ((uint8_t)0x20)
+#define RTC_CR1_WUCKSEL          ((uint8_t)0x07)
+#define RTC_CR1_BYPSHAD           ((uint8_t)0x10)
+
+
+/* Bits definition for RTC_CR2 register*/
+#define RTC_CR2_WUTIE            ((uint8_t)0x40)
+#define RTC_CR2_ALRAIE           ((uint8_t)0x10)
+#define RTC_CR2_WUTE             ((uint8_t)0x04)
+#define RTC_CR2_ALRAE            ((uint8_t)0x01)
+#define RTC_CR2_ALRIE            ((uint8_t)0x20)
+
+
+
+/* Bits definition for RTC_CR3 register*/
+#define RTC_CR3_COE              ((uint8_t)0x80)
+#define RTC_CR3_OSEL             ((uint8_t)0x60)
+#define RTC_CR3_POL              ((uint8_t)0x10)
+#define RTC_CR3_COSEL            ((uint8_t)0x08)
+#define RTC_CR3_BCK              ((uint8_t)0x04)
+#define RTC_CR3_SUB1H            ((uint8_t)0x02)
+#define RTC_CR3_ADD1H            ((uint8_t)0x01)
+
+
+/* Bits definition for RTC_ISR1 register*/
+#define RTC_ISR1_INIT            ((uint8_t)0x80)
+#define RTC_ISR1_INITF           ((uint8_t)0x40)
+#define RTC_ISR1_RSF             ((uint8_t)0x20)
+#define RTC_ISR1_INITS           ((uint8_t)0x10)
+#define RTC_ISR1_SHPF            ((uint8_t)0x08)
+#define RTC_ISR1_WUTWF           ((uint8_t)0x04)
+#define RTC_ISR1_RECALPF         ((uint8_t)0x02)
+#define RTC_ISR1_ALRAWF          ((uint8_t)0x01)
+
+
+/* Bits definition for RTC_ISR2 register*/
+#define RTC_ISR2_WUTF            ((uint8_t)0x04)
+#define RTC_ISR2_ALRAF           ((uint8_t)0x01)
+#define RTC_ISR2_TAMP3F          ((uint8_t)0x80)
+#define RTC_ISR2_TAMP2F          ((uint8_t)0x40)
+#define RTC_ISR2_TAMP1F          ((uint8_t)0x20)
+
+/* Bits definition for RTC_SHIFTRH register*/
+#define RTC_SHIFTRH_ADD1S        ((uint8_t)0x80)
+#define RTC_SHIFTRH_SUBFS        ((uint8_t)0x7F)
+
+/* Bits definition for RTC_SHIFTRL register*/
+#define RTC_SHIFTRL_SUBFS        ((uint8_t)0xFF)
+
+
+/* Bits definition for RTC_ALRMAR1 register*/
+#define RTC_ALRMAR1_MSK1         ((uint8_t)0x80)
+#define RTC_ALRMAR1_ST           ((uint8_t)0x70)
+#define RTC_ALRMAR1_SU           ((uint8_t)0x0F)
+
+/* Bits definition for RTC_ALRMAR2 register*/
+#define RTC_ALRMAR2_MSK2         ((uint8_t)0x80)
+#define RTC_ALRMAR2_MNT          ((uint8_t)0x70)
+#define RTC_ALRMAR2_MNU          ((uint8_t)0x0F)
+
+/* Bits definition for RTC_ALRMAR3 register*/
+#define RTC_ALRMAR3_MSK3         ((uint8_t)0x80)
+#define RTC_ALRMAR3_PM           ((uint8_t)0x40)
+#define RTC_ALRMAR3_HT           ((uint8_t)0x30)
+#define RTC_ALRMAR3_HU           ((uint8_t)0x0F)
+
+/* Bits definition for RTC_ALRMAR4 register*/
+#define RTC_ALRMAR4_MSK4         ((uint8_t)0x80)
+#define RTC_ALRMAR4_WDSEL        ((uint8_t)0x40)
+#define RTC_ALRMAR4_DT           ((uint8_t)0x30)
+#define RTC_ALRMAR4_DU           ((uint8_t)0x0F)
+
+/* Bits definition for RTC_ALRMASSRH register*/
+#define RTC_ALRMASSRH_ALSS         ((uint8_t)0x7F)
+
+/* Bits definition for RTC_ALRMASSRL register*/
+#define RTC_ALRMASSRL_ALSS         ((uint8_t)0xFF)
+
+/* Bits definition for RTC_ALRMASSMSKR register*/
+#define RTC_ALRMASSMSKR_MASKSS   ((uint8_t)0x1F)
+
+
+/* Bits definition for RTC_CALRH register*/
+#define RTC_CALRH_CALP          ((uint8_t)0x80)
+#define RTC_CALRH_CALW8         ((uint8_t)0x40)
+#define RTC_CALRH_CALW16        ((uint8_t)0x20)
+#define RTC_CALRH_CALWx         ((uint8_t)0x60)
+#define RTC_CALRH_CALM          ((uint8_t)0x01)
+
+/* Bits definition for RTC_CALRL register*/
+#define RTC_CALRL_CALM          ((uint8_t)0xFF)
+
+/* Bits definition for RTC_TCR1 register*/
+#define RTC_TCR1_TAMP3LEVEL     ((uint8_t)0x40)
+#define RTC_TCR1_TAMP3E         ((uint8_t)0x20)
+#define RTC_TCR1_TAMP2LEVEL     ((uint8_t)0x10)
+#define RTC_TCR1_TAMP2E         ((uint8_t)0x08)
+#define RTC_TCR1_TAMP1LEVEL     ((uint8_t)0x04)
+#define RTC_TCR1_TAMP1E         ((uint8_t)0x02)
+#define RTC_TCR1_TAMPIE         ((uint8_t)0x01)
+
+/* Bits definition for RTC_TCR2 register*/
+#define RTC_TCR2_TAMPPUDIS         ((uint8_t)0x80)
+#define RTC_TCR2_TAMPPRCH          ((uint8_t)0x60)
+#define RTC_TCR2_TAMPFLT           ((uint8_t)0x18)
+#define RTC_TCR2_TAMPFREQ          ((uint8_t)0x07)
+
+
+/*RTC special defines */
+#define RTC_WPR_EnableKey        ((uint8_t)0xFF)
+#define RTC_WPR_DisableKey1      ((uint8_t)0xCA)
+#define RTC_WPR_DisableKey2      ((uint8_t)0x53)
+
+/**
+  * @}
+  */
+
+/**
+  * @brief CSS on LSE registers.
+  */
+typedef struct CSSLSE_struct
+{
+  __IO uint8_t CSR; /*!<  Control and Status Register*/
+}
+CSSLSE_TypeDef;
+
+/** @addtogroup CSSLSE_Registers_Reset_Value
+  * @{
+  */
+#define CSSLSE_CSR_RESET_VALUE       ((uint8_t)0x00)
+
+/**
+  * @}
+  */
+
+/** @addtogroup CSSLSE_Registers_Bits_Definition
+  * @{
+  */
+
+/* Bits definition for CSSLSE_CSR register*/
+#define CSSLSE_CSR_SWITCHF            ((uint8_t)0x10)
+#define CSSLSE_CSR_CSSF               ((uint8_t)0x08)
+#define CSSLSE_CSR_CSSIE              ((uint8_t)0x04)
+#define CSSLSE_CSR_SWITCHEN           ((uint8_t)0x02)
+#define CSSLSE_CSR_CSSEN              ((uint8_t)0x01)
+
+/**
+  * @}
+  */
+/*----------------------------------------------------------------------------*/
+/**
+  * @brief Beeper (BEEP) peripheral registers.
+  */
+
+typedef struct BEEP_struct
+{
+  __IO uint8_t CSR1; /*!< BEEP Control status register1 */
+  uint8_t RSERVED1;
+  uint8_t RESERVED2;
+  __IO uint8_t CSR2; /*!< BEEP Control status register2 */
+}
+BEEP_TypeDef;
+
+/** @addtogroup BEEP_Registers_Reset_Value
+  * @{
+  */
+#define BEEP_CSR1_RESET_VALUE ((uint8_t)0x00)
+#define BEEP_CSR2_RESET_VALUE ((uint8_t)0x1F)
+
+/**
+  * @}
+  */
+
+/** @addtogroup BEEP_Registers_Bits_Definition
+  * @{
+  */
+
+#define BEEP_CSR1_MSR     ((uint8_t)0x01) /*!< Measurement enable mask */
+
+#define BEEP_CSR2_BEEPSEL ((uint8_t)0xC0) /*!< Beeper frequency selection mask */
+#define BEEP_CSR2_BEEPEN  ((uint8_t)0x20) /*!< Beeper enable mask */
+#define BEEP_CSR2_BEEPDIV ((uint8_t)0x1F) /*!< Beeper Divider prescalar mask */
+
+/**
+  * @}
+  */
+
+/*----------------------------------------------------------------------------ok*/
+
+/**
+  * @brief Configuration Registers (CFG)
+  */
+
+typedef struct CFG_struct
+{
+  __IO uint8_t GCR; /*!< Global Configuration register */
+}
+CFG_TypeDef;
+
+/** @addtogroup CFG_Registers_Reset_Value
+  * @{
+  */
+
+#define CFG_GCR_RESET_VALUE ((uint8_t)0x00)
+
+/**
+  * @}
+  */
+
+/** @addtogroup CFG_Registers_Bits_Definition
+  * @{
+  */
+
+#define CFG_GCR_SWD ((uint8_t)0x01) /*!< Swim disable bit mask */
+#define CFG_GCR_AL  ((uint8_t)0x02) /*!< Activation Level bit mask */
+
+/**
+  * @}
+  */
+/*----------------------------------------------------------------------------ok*/
+
+/**
+  * @brief SYSCFG
+  */
+
+typedef struct SYSCFG_struct
+{
+  __IO uint8_t RMPCR3; /*!< Remap control register 3 */
+  __IO uint8_t RMPCR1; /*!< Remap control register 1 */
+  __IO uint8_t RMPCR2; /*!< Remap control register 2 */
+}
+SYSCFG_TypeDef;
+
+/** @addtogroup SYSCFG_Registers_Reset_Value
+  * @{
+  */
+#define SYSCFG_RMPCR1_RESET_VALUE ((uint8_t)0x0C)
+#define SYSCFG_RMPCR2_RESET_VALUE ((uint8_t)0x00)
+#define SYSCFG_RMPCR3_RESET_VALUE ((uint8_t)0x00)
+
+/**
+  * @}
+  */
+
+/** @addtogroup SYSCFG_Registers_Bits_Definition
+  * @{
+  */
+
+/* For DMA Channel Mapping*/
+#define SYSCFG_RMPCR1_ADC1DMA_REMAP     ((uint8_t)0x03) /*!< ADC1 DMA channel remapping */
+#define SYSCFG_RMPCR1_TIM4DMA_REMAP     ((uint8_t)0x0C) /*!< TIM4 DMA channel remapping */
+
+
+/* For GPIO Reapping*/
+#define SYSCFG_RMPCR1_USART1TR_REMAP    ((uint8_t)0x30) /*!< USART1_TX and USART1_RX remapping */
+#define SYSCFG_RMPCR1_USART1CK_REMAP    ((uint8_t)0x40) /*!< USART1_CK remapping */
+#define SYSCFG_RMPCR1_SPI1_REMAP        ((uint8_t)0x80) /*!< SPI1 remapping */
+
+#define SYSCFG_RMPCR2_ADC1TRIG_REMAP    ((uint8_t)0x01) /*!< ADC1 External Trigger remap */
+#define SYSCFG_RMPCR2_TIM2TRIG_REMAP    ((uint8_t)0x02) /*!< TIM2 Trigger remap */
+#define SYSCFG_RMPCR2_TIM3TRIG_REMAP1   ((uint8_t)0x04) /*!< TIM3 Trigger remap 1 */
+#define SYSCFG_RMPCR2_TIM2TRIG_LSE      ((uint8_t)0x08) /*!< TIM2 Trigger remap to LSE */
+#define SYSCFG_RMPCR2_TIM3TRIG_LSE      ((uint8_t)0x10) /*!< TIM3 Trigger remap to LSE */
+#define SYSCFG_RMPCR2_SPI2_REMAP        ((uint8_t)0x20) /*!< SPI2 remapping */
+#define SYSCFG_RMPCR2_TIM3TRIG_REMAP2   ((uint8_t)0x40) /*!< TIM3 Trigger remap 2 */
+#define SYSCFG_RMPCR2_TIM23BKIN_REMAP   ((uint8_t)0x80) /*!< TIM2 & TIM3 Break input remap */
+
+#define SYSCFG_RMPCR3_SPI1_REMAP        ((uint8_t)0x01) /*!< SPI1 remapping */
+#define SYSCFG_RMPCR3_USART3TR_REMAP    ((uint8_t)0x02) /*!< USART3_TX and USART3_RX remapping */
+#define SYSCFG_RMPCR3_USART3CK_REMAP    ((uint8_t)0x04) /*!< USART3_CK remapping */
+#define SYSCFG_RMPCR3_TIM3CH1_REMAP     ((uint8_t)0x08) /*!< TIM3 channel 1 remapping */
+#define SYSCFG_RMPCR3_TIM3CH2_REMAP     ((uint8_t)0x10) /*!< TIM3 channel 2 remapping */
+#define SYSCFG_RMPCR3_CCO_REMAP         ((uint8_t)0x20) /*!< CCO remapping */
+
+/**
+  * @}
+  */
+/*----------------------------------------------------------------------------ok*/
+
+/**
+  * @brief Clock Controller (CLK)
+  */
+typedef struct CLK_struct
+{
+  __IO uint8_t CKDIVR;      /*!< Clock Master Divider Register */
+  __IO uint8_t CRTCR;  /*!< RTC Clock selection Register */
+  __IO uint8_t ICKCR;     /*!< Internal Clocks Control Register */
+  __IO uint8_t PCKENR1;  /*!< Peripheral Clock Gating Register 1 */
+  __IO uint8_t PCKENR2;  /*!< Peripheral Clock Gating Register 2 */
+  __IO uint8_t CCOR;       /*!< Configurable Clock Output Register */
+  __IO uint8_t ECKCR;     /*!< External Clocks Control Register */
+  __IO uint8_t SCSR;     /*!< System clock status Register */
+  __IO uint8_t SWR;      /*!< System clock Switch Register */
+  __IO uint8_t SWCR;     /*!< Switch Control Register */
+  __IO uint8_t CSSR;     /*!< Clock Security Sytem Register */
+  __IO uint8_t CBEEPR;     /*!< Clock BEEP Register */
+  __IO uint8_t HSICALR;     /*!< HSI Calibration Register */
+  __IO uint8_t HSITRIMR; /*!< HSI clock Calibration Trimmer Register */
+  __IO uint8_t HSIUNLCKR; /*!< HSI Unlock  Register */
+  __IO uint8_t REGCSR;  /*!< Main regulator control status register */
+  __IO uint8_t PCKENR3;  /*!< Peripheral Clock Gating Register 3 */
+}
+CLK_TypeDef;
+
+/** @addtogroup CLK_Registers_Reset_Value
+  * @{
+  */
+#define CLK_CKDIVR_RESET_VALUE    ((uint8_t)0x03)
+#define CLK_CRTCR_RESET_VALUE     ((uint8_t)0x00)
+#define CLK_ICKCR_RESET_VALUE     ((uint8_t)0x11)
+#define CLK_PCKENR1_RESET_VALUE   ((uint8_t)0x00)
+#define CLK_PCKENR2_RESET_VALUE   ((uint8_t)0x80)
+#define CLK_PCKENR3_RESET_VALUE   ((uint8_t)0x00)
+#define CLK_CCOR_RESET_VALUE      ((uint8_t)0x00)
+#define CLK_ECKCR_RESET_VALUE     ((uint8_t)0x00)
+#define CLK_SCSR_RESET_VALUE      ((uint8_t)0x01)
+#define CLK_SWR_RESET_VALUE       ((uint8_t)0x01)
+#define CLK_SWCR_RESET_VALUE      ((uint8_t)0x00)
+#define CLK_CSSR_RESET_VALUE      ((uint8_t)0x00)
+#define CLK_CBEEPR_RESET_VALUE    ((uint8_t)0x00)
+#define CLK_HSICALR_RESET_VALUE   ((uint8_t)0x00)
+#define CLK_HSITRIMR_RESET_VALUE  ((uint8_t)0x00)
+#define CLK_HSIUNLCKR_RESET_VALUE ((uint8_t)0x00)
+#define CLK_REGCSR_RESET_VALUE    ((uint8_t)0xB9)
+/**
+  * @}
+  */
+
+/** @addtogroup CLK_Registers_Bits_Definition
+  * @{
+  */
+
+#define CLK_CKDIVR_CKM            ((uint8_t)0x07) /*!< System clock prescaler mask */
+
+#define CLK_CRTCR_RTCDIV          ((uint8_t)0xE0) /*!< RTC clock prescaler  mask*/
+#define CLK_CRTCR_RTCSEL          ((uint8_t)0x1E) /*!< RTC clock output selection  mask */
+#define CLK_CRTCR_RTCSWBSY        ((uint8_t)0x01) /*!< RTC clock switch busy */
+
+#define CLK_ICKCR_BEEPAHALT       ((uint8_t)0x40) /*!< BEEP clock Active Halt/Halt mode */
+#define CLK_ICKCR_FHWU            ((uint8_t)0x20) /*!< Fast Wake-up from Active Halt/Halt mode */
+#define CLK_ICKCR_SAHALT          ((uint8_t)0x10) /*!< Slow Active-halt mode */
+#define CLK_ICKCR_LSIRDY          ((uint8_t)0x08) /*!< Low speed internal RC oscillator ready */
+#define CLK_ICKCR_LSION           ((uint8_t)0x04) /*!< Low speed internal RC oscillator enable */
+#define CLK_ICKCR_HSIRDY          ((uint8_t)0x02) /*!< High speed internal RC oscillator ready */
+#define CLK_ICKCR_HSION           ((uint8_t)0x01) /*!< High speed internal RC oscillator enable */
+
+#define CLK_PCKENR1_TIM2          ((uint8_t)0x01) /*!< Timer 2 clock enable */
+#define CLK_PCKENR1_TIM3          ((uint8_t)0x02) /*!< Timer 3 clock enable */
+#define CLK_PCKENR1_TIM4          ((uint8_t)0x04) /*!< Timer 4 clock enable */
+#define CLK_PCKENR1_I2C1          ((uint8_t)0x08) /*!< I2C1 clock enable */
+#define CLK_PCKENR1_SPI1          ((uint8_t)0x10) /*!< SPI1 clock enable */
+#define CLK_PCKENR1_USART1        ((uint8_t)0x20) /*!< USART1 clock enable */
+#define CLK_PCKENR1_BEEP          ((uint8_t)0x40) /*!< BEEP clock enable */
+#define CLK_PCKENR1_DAC           ((uint8_t)0x80) /*!< DAC clock enable */
+
+#define CLK_PCKENR2_ADC1          ((uint8_t)0x01) /*!< ADC1 clock enable */
+#define CLK_PCKENR2_TIM1          ((uint8_t)0x02) /*!< TIM1 clock enable */
+#define CLK_PCKENR2_RTC           ((uint8_t)0x04) /*!< RTC clock enable */
+#define CLK_PCKENR2_LCD           ((uint8_t)0x08) /*!< LCD clock enable */
+#define CLK_PCKENR2_DMA1          ((uint8_t)0x10) /*!< DMA1 clock enable */
+#define CLK_PCKENR2_COMP          ((uint8_t)0x20) /*!< Comparator clock enable */
+#define CLK_PCKENR2_BOOTROM       ((uint8_t)0x80) /*!< Boot ROM clock enable */
+
+#define CLK_PCKENR3_AES           ((uint8_t)0x01) /*!< AES clock enable */
+#define CLK_PCKENR3_TIM5          ((uint8_t)0x02) /*!< Timer 5 clock enable */
+#define CLK_PCKENR3_SPI2          ((uint8_t)0x04) /*!< SPI2 clock enable */
+#define CLK_PCKENR3_UASRT2        ((uint8_t)0x08) /*!< USART2 clock enable */
+#define CLK_PCKENR3_USART3        ((uint8_t)0x10) /*!< USART3 clock enable */
+
+#define CLK_CCOR_CCODIV           ((uint8_t)0xE0) /*!< Configurable Clock output prescaler */
+#define CLK_CCOR_CCOSEL           ((uint8_t)0x1E) /*!< Configurable clock output selection */
+#define CLK_CCOR_CCOSWBSY         ((uint8_t)0x01) /*!< Configurable clock output switch busy  flag */
+
+#define CLK_ECKCR_LSEBYP          ((uint8_t)0x20) /*!< Low speed external clock bypass */
+#define CLK_ECKCR_HSEBYP          ((uint8_t)0x10) /*!< High speed external clock bypass */
+#define CLK_ECKCR_LSERDY          ((uint8_t)0x08) /*!< Low speed external crystal oscillator ready */
+#define CLK_ECKCR_LSEON           ((uint8_t)0x04) /*!< Low speed external crystal oscillator enable */
+#define CLK_ECKCR_HSERDY          ((uint8_t)0x02) /*!< High speed external crystal oscillator ready */
+#define CLK_ECKCR_HSEON           ((uint8_t)0x01) /*!< High speed external crystal oscillator enable */
+
+#define CLK_SCSR_CKM              ((uint8_t)0x0F) /*!< System clock status bits */
+
+#define CLK_SWR_SWI               ((uint8_t)0x0F) /*!< System clock selection bits */
+
+#define CLK_SWCR_SWIF             ((uint8_t)0x08) /*!< Clock switch interrupt flag */
+#define CLK_SWCR_SWIEN            ((uint8_t)0x04) /*!< Clock switch interrupt enable */
+#define CLK_SWCR_SWEN             ((uint8_t)0x02) /*!< Switch start/stop */
+#define CLK_SWCR_SWBSY            ((uint8_t)0x01) /*!< Switch busy */
+
+#define CLK_CSSR_CSSDGON          ((uint8_t)0x10) /*!< Clock security sytem deglitcher system */
+#define CLK_CSSR_CSSD             ((uint8_t)0x08) /*!< Clock security sytem detection */
+#define CLK_CSSR_CSSDIE           ((uint8_t)0x04) /*!< Clock security system detection interrupt enable */
+#define CLK_CSSR_AUX              ((uint8_t)0x02) /*!< Auxiliary oscillator connected to master clock */
+#define CLK_CSSR_CSSEN            ((uint8_t)0x01) /*!< Clock security system enable */
+
+#define CLK_CBEEPR_CLKBEEPSEL     ((uint8_t)0x06) /*!< Configurable BEEP clock source selection */
+#define CLK_CBEEPR_BEEPSWBSY      ((uint8_t)0x01) /*!< BEEP clock busy in switch  */
+
+#define CLK_HSICALR_HSICAL        ((uint8_t)0xFF) /*!<  Copy of otpion byte trimming HSI oscillator */
+
+#define CLK_HSITRIMR_HSITRIM      ((uint8_t)0xFF) /*!< High speed internal oscillator trimmer */
+
+#define CLK_HSIUNLCKR_HSIUNLCK    ((uint8_t)0xFF) /*!< High speed internal oscillator trimmer unlock  */
+
+#define CLK_REGCSR_EEREADY        ((uint8_t)0x80) /*!< Flash program memory and Data EEPROM ready */
+#define CLK_REGCSR_EEBUSY         ((uint8_t)0x40) /*!< Flash program memory and Data EEPROM busy */
+#define CLK_REGCSR_LSEPD          ((uint8_t)0x20) /*!< LSE power-down */
+#define CLK_REGCSR_HSEPD          ((uint8_t)0x10) /*!< HSE power-down */
+#define CLK_REGCSR_LSIPD          ((uint8_t)0x08) /*!< LSI power-down */
+#define CLK_REGCSR_HSIPD          ((uint8_t)0x04) /*!< HSI power-down */
+#define CLK_REGCSR_REGOFF         ((uint8_t)0x02) /*!< Main regulator OFF */
+#define CLK_REGCSR_REGREADY       ((uint8_t)0x01) /*!< Main regulator ready */
+
+/**
+  * @}
+  */
+/*----------------------------------------------------------------------------ok*/
+
+/**
+  * @brief Comparator interface (COMP)
+  */
+
+typedef struct COMP_struct
+{
+  __IO uint8_t CSR1;   /*!< Control status register 1  */
+  __IO uint8_t CSR2;   /*!< Control status register 2  */
+  __IO uint8_t CSR3;   /*!< Control status register 3  */
+  __IO uint8_t CSR4;   /*!< Control status register 4  */
+  __IO uint8_t CSR5;   /*!< Control status register 5  */
+}
+COMP_TypeDef;
+
+
+/** @addtogroup COMP_Registers_Reset_Value
+  * @{
+  */
+#define COMP_CSR1_RESET_VALUE  ((uint8_t)0x00)
+#define COMP_CSR2_RESET_VALUE  ((uint8_t)0x00)
+#define COMP_CSR3_RESET_VALUE  ((uint8_t)0xC0)
+#define COMP_CSR4_RESET_VALUE  ((uint8_t)0x00)
+#define COMP_CSR5_RESET_VALUE  ((uint8_t)0x00)
+
+/**
+  * @}
+  */
+
+/** @addtogroup COMP_Registers_Bits_Definition
+  * @{
+  */
+
+/* CSR1 */
+#define COMP_CSR1_IE1        ((uint8_t)0x20) /*!<  Comparator 1 Interrupt Enable Mask. */
+#define COMP_CSR1_EF1        ((uint8_t)0x10) /*!<  Comparator 1 Event Flag Mask. */
+#define COMP_CSR1_CMP1OUT    ((uint8_t)0x08) /*!<  Comparator 1 Ouptput Mask. */
+#define COMP_CSR1_STE        ((uint8_t)0x04) /*!<  Schmitt trigger enable Mask. */
+#define COMP_CSR1_CMP1       ((uint8_t)0x03) /*!<  Comparator 1 Configuration Mask. */
+
+/* CSR2 */
+#define COMP_CSR2_IE2        ((uint8_t)0x20) /*!<  Comparator 2 Interrupt Enable Mask. */
+#define COMP_CSR2_EF2        ((uint8_t)0x10) /*!<  Comparator 2 Event Flag Mask. */
+#define COMP_CSR2_CMP2OUT    ((uint8_t)0x08) /*!<  Comparator 2 Ouptput Mask. */
+#define COMP_CSR2_SPEED      ((uint8_t)0x04) /*!<  Comparator 2 speed modeMask. */
+#define COMP_CSR2_CMP2       ((uint8_t)0x03) /*!<  Comparator 2 Configuration Mask. */
+
+/* CSR3 */
+#define COMP_CSR3_OUTSEL     ((uint8_t)0xC0) /*!<  Comparator 2 output selection Mask. */
+#define COMP_CSR3_INSEL      ((uint8_t)0x38) /*!<  Inversion input selection Mask. */
+#define COMP_CSR3_VREFEN     ((uint8_t)0x04) /*!<  Internal reference voltage Enable Mask. */
+#define COMP_CSR3_WNDWE      ((uint8_t)0x02) /*!<  Window Mode Enable Mask. */
+#define COMP_CSR3_VREFOUTEN  ((uint8_t)0x01) /*!<  VREF Output Enable Mask. */
+
+/* CSR4 */
+#define COMP_CSR4_NINVTRIG   ((uint8_t)0x38) /*!<  COMP2 non-inverting input Mask. */
+#define COMP_CSR4_INVTRIG    ((uint8_t)0x07) /*!<  COMP2 inverting input Mask. */
+
+/* CSR5 */
+#define COMP_CSR5_DACTRIG    ((uint8_t)0x38) /*!<  DAC outputs Mask. */
+#define COMP_CSR5_VREFTRIG   ((uint8_t)0x07) /*!<  VREF outputs Mask. */
+
+/**
+  * @}
+  */
+
+/*----------------------------------------------------------------------------ok*/
+
+/**
+  * @brief External Interrupt Controller (EXTI)
+  */
+typedef struct EXTI_struct
+{
+  __IO uint8_t CR1;           /*!<  The four LSB EXTI  pin sensitivity */
+  __IO uint8_t CR2;           /*!<  The four MSB EXTI  pin sensitivity */
+  __IO uint8_t CR3;           /*!<  EXTI port B & port D sensitivity */
+  __IO uint8_t SR1;           /*!<  Pins Status flag register 1 */
+  __IO uint8_t SR2;           /*!<  Ports Status flage register 2 */
+  __IO uint8_t CONF1;         /*!<  Port interrupt selector */
+  uint8_t RESERVED[4];  /*!<  reserved area */
+  __IO uint8_t CR4;           /*!<  EXTI port G & port H sensitivity */
+  __IO uint8_t CONF2;         /*!<  Port interrupt selector */
+}
+EXTI_TypeDef;
+
+/** @addtogroup EXTI_Registers_Reset_Value
+  * @{
+  */
+
+#define EXTI_CR1_RESET_VALUE   ((uint8_t)0x00)
+#define EXTI_CR2_RESET_VALUE   ((uint8_t)0x00)
+#define EXTI_CR3_RESET_VALUE   ((uint8_t)0x00)
+#define EXTI_CONF1_RESET_VALUE ((uint8_t)0x00)
+#define EXTI_SR1_RESET_VALUE   ((uint8_t)0x00)
+#define EXTI_SR2_RESET_VALUE   ((uint8_t)0x00)
+#define EXTI_CR4_RESET_VALUE   ((uint8_t)0x00)
+#define EXTI_CONF2_RESET_VALUE ((uint8_t)0x00)
+
+/**
+  * @}
+  */
+
+/** @addtogroup EXTI_Registers_Bits_Definition
+  * @{
+  */
+/* CR1 */
+#define EXTI_CR1_P3IS      ((uint8_t)0xC0) /*!< EXTI Pin 3 external interrupt sensitivity bit Mask */
+#define EXTI_CR1_P2IS      ((uint8_t)0x30) /*!< EXTI Pin 2 external interrupt sensitivity bit Mask */
+#define EXTI_CR1_P1IS      ((uint8_t)0x0C) /*!< EXTI Pin 1  external interrupt sensitivity bit Mask */
+#define EXTI_CR1_P0IS      ((uint8_t)0x03) /*!< EXTI Pin 0 external interrupt sensitivity bit Mask */
+
+/* CR2 */
+#define EXTI_CR2_P7IS      ((uint8_t)0xC0) /*!< EXTI Pin 7 external interrupt sensitivity bit Mask */
+#define EXTI_CR2_P6IS      ((uint8_t)0x30) /*!< EXTI Pin 6 external interrupt sensitivity bit Mask */
+#define EXTI_CR2_P5IS      ((uint8_t)0x0C) /*!< EXTI Pin 5  external interrupt sensitivity bit Mask */
+#define EXTI_CR2_P4IS      ((uint8_t)0x03) /*!< EXTI Pin 4 external interrupt sensitivity bit Mask */
+
+/* CR3 */
+#define EXTI_CR3_PBIS      ((uint8_t)0x03) /*!< EXTI PORTB external interrupt sensitivity bits Mask */
+#define EXTI_CR3_PDIS      ((uint8_t)0x0C) /*!< EXTI PORTD external interrupt sensitivity bits Mask */
+#define EXTI_CR3_PEIS      ((uint8_t)0x30) /*!< EXTI PORTE external interrupt sensitivity bits Mask */
+#define EXTI_CR3_PFIS      ((uint8_t)0xC0) /*!< EXTI PORTF external interrupt sensitivity bits Mask */
+
+/* CONF1 */
+#define EXTI_CONF1_PBLIS   ((uint8_t)0x01) /*!< EXTI PORTB low interrupt selector bit Mask */
+#define EXTI_CONF1_PBHIS   ((uint8_t)0x02) /*!< EXTI PORTB high interrupt selector bit Mask */
+#define EXTI_CONF1_PDLIS   ((uint8_t)0x04) /*!< EXTI PORTD low interrupt selector bit Mask */
+#define EXTI_CONF1_PDHIS   ((uint8_t)0x08) /*!< EXTI PORTD high interrupt selector bit Mask */
+#define EXTI_CONF1_PELIS   ((uint8_t)0x10) /*!< EXTI PORTE low interrupt selector bit Mask */
+#define EXTI_CONF1_PEHIS   ((uint8_t)0x20) /*!< EXTI PORTE high interrupt selector bit Mask */
+#define EXTI_CONF1_PFLIS   ((uint8_t)0x40) /*!< EXTI PORTF low interrupt selector bit Mask */
+#define EXTI_CONF1_PFES    ((uint8_t)0x80) /*!< EXTI PORTF or PORTE interrupt selector bit Mask */
+
+/* CR4 */
+#define EXTI_CR4_PGIS      ((uint8_t)0x03) /*!< EXTI PORTG external interrupt sensitivity bits Mask */
+#define EXTI_CR4_PHIS      ((uint8_t)0x0C) /*!< EXTI PORTH external interrupt sensitivity bits Mask */
+
+/* CONF2 */
+#define EXTI_CONF2_PFHIS   ((uint8_t)0x01) /*!< EXTI PORTF high interrupt selector bit Mask */
+#define EXTI_CONF2_PGLIS   ((uint8_t)0x02) /*!< EXTI PORTG low interrupt selector bit Mask */
+#define EXTI_CONF2_PGHIS   ((uint8_t)0x04) /*!< EXTI PORTG high interrupt selector bit Mask */
+#define EXTI_CONF2_PHLIS   ((uint8_t)0x08) /*!< EXTI PORTH low interrupt selector bit Mask */
+#define EXTI_CONF2_PHHIS   ((uint8_t)0x10) /*!< EXTI PORTH high interrupt selector bit Mask */
+#define EXTI_CONF2_PGBS    ((uint8_t)0x20) /*!< EXTI PORTB or PORTG interrupt selector bit Mask */
+#define EXTI_CONF2_PHDS    ((uint8_t)0x40) /*!< EXTI PORTD or PORTH interrupt selector bit Mask */
+
+/**
+  * @}
+  */
+
+/*----------------------------------------------------------------------------ok*/
+
+/**
+  * @brief FLASH and Data EEPROM
+  */
+typedef struct FLASH_struct
+{
+  __IO uint8_t CR1;        /*!< Flash control register 1 */
+  __IO uint8_t CR2;        /*!< Flash control register 2 */
+  __IO uint8_t PUKR;       /*!< Flash program memory unprotection register */
+  __IO uint8_t DUKR;       /*!< Data EEPROM unprotection register */
+  __IO uint8_t IAPSR;      /*!< Flash in-application programming status register */
+}
+FLASH_TypeDef;
+
+/** @addtogroup FLASH_Registers_Reset_Value
+  * @{
+  */
+#define FLASH_CR1_RESET_VALUE    ((uint8_t)0x00)
+#define FLASH_CR2_RESET_VALUE    ((uint8_t)0x00)
+#define FLASH_PUKR_RESET_VALUE   ((uint8_t)0xAE)
+#define FLASH_DUKR_RESET_VALUE   ((uint8_t)0x56)
+#define FLASH_IAPSR_RESET_VALUE  ((uint8_t)0x40)
+
+
+/**
+  * @}
+  */
+
+/** @addtogroup FLASH_Registers_Bits_Definition
+  * @{
+  */
+#define FLASH_CR1_EEPM           ((uint8_t)0x08) /*!< Flash low power selection during Run and Low power run mode Mask */
+#define FLASH_CR1_WAITM          ((uint8_t)0x04) /*!< Flash low power selection during Wait and Low power wait mode Mask */
+#define FLASH_CR1_IE             ((uint8_t)0x02) /*!< Flash Interrupt enable Mask */
+#define FLASH_CR1_FIX            ((uint8_t)0x01) /*!< Fix programming time Mask */
+
+#define FLASH_CR2_OPT            ((uint8_t)0x80) /*!< Enable write access to option bytes*/
+#define FLASH_CR2_WPRG           ((uint8_t)0x40) /*!< Word write once Mask */
+#define FLASH_CR2_ERASE          ((uint8_t)0x20) /*!< Erase block Mask */
+#define FLASH_CR2_FPRG           ((uint8_t)0x10) /*!< Fast programming mode Mask */
+#define FLASH_CR2_PRG            ((uint8_t)0x01) /*!< Program block Mask */
+
+#define FLASH_IAPSR_HVOFF        ((uint8_t)0x40) /*!< End of high voltage flag Mask */
+#define FLASH_IAPSR_DUL          ((uint8_t)0x08) /*!< Data EEPROM unlocked flag Mask */
+#define FLASH_IAPSR_EOP          ((uint8_t)0x04) /*!< End of operation flag Mask */
+#define FLASH_IAPSR_PUL          ((uint8_t)0x02) /*!< Program memory unlocked flag Mask */
+#define FLASH_IAPSR_WR_PG_DIS    ((uint8_t)0x01) /*!< Write attempted to protected page Mask */
+
+#define FLASH_PUKR_PUK           ((uint8_t)0xFF) /*!< Flash Program memory unprotection mask */
+
+#define FLASH_DUKR_DUK           ((uint8_t)0xFF) /*!< Data EEPROM unprotection mask */
+
+
+/**
+  * @}
+  */
+
+/*----------------------------------------------------------------------------*/
+
+/**
+  * @brief Inter-Integrated Circuit (I2C)
+  */
+typedef struct I2C_struct
+{
+  __IO uint8_t CR1;    /*!< I2C control register 1 */
+  __IO uint8_t CR2;    /*!< I2C control register 2 */
+  __IO uint8_t FREQR;  /*!< I2C frequency register */
+  __IO uint8_t OARL;   /*!< I2C own address register 1 LSB */
+  __IO uint8_t OARH;   /*!< I2C own address register 1 MSB */
+  __IO uint8_t OAR2;   /*!< I2C own address register 2 */
+  __IO uint8_t DR;     /*!< I2C data register */
+  __IO uint8_t SR1;    /*!< I2C status register 1 */
+  __IO uint8_t SR2;    /*!< I2C status register 2 */
+  __IO uint8_t SR3;    /*!< I2C status register 3 */
+  __IO uint8_t ITR;    /*!< I2C interrupt & DMA register */
+  __IO uint8_t CCRL;   /*!< I2C clock control register low */
+  __IO uint8_t CCRH;   /*!< I2C clock control register high */
+  __IO uint8_t TRISER; /*!< I2C maximum rise time register */
+  __IO uint8_t PECR;   /*!< I2CPacket Error Checking register */
+}
+I2C_TypeDef;
+
+/** @addtogroup I2C_Registers_Reset_Value
+  * @{
+  */
+#define I2C_CR1_RESET_VALUE    ((uint8_t)0x00)
+#define I2C_CR2_RESET_VALUE    ((uint8_t)0x00)
+#define I2C_FREQR_RESET_VALUE  ((uint8_t)0x00)
+#define I2C_OARL_RESET_VALUE   ((uint8_t)0x00)
+#define I2C_OARH_RESET_VALUE   ((uint8_t)0x00)
+#define I2C_OAR2_RESET_VALUE   ((uint8_t)0x00)
+#define I2C_DR_RESET_VALUE     ((uint8_t)0x00)
+#define I2C_SR1_RESET_VALUE    ((uint8_t)0x00)
+#define I2C_SR2_RESET_VALUE    ((uint8_t)0x00)
+#define I2C_SR3_RESET_VALUE    ((uint8_t)0x00)
+#define I2C_ITR_RESET_VALUE    ((uint8_t)0x00)
+#define I2C_CCRL_RESET_VALUE   ((uint8_t)0x00)
+#define I2C_CCRH_RESET_VALUE   ((uint8_t)0x00)
+#define I2C_TRISER_RESET_VALUE ((uint8_t)0x02)
+#define I2C_PECR_RESET_VALUE   ((uint8_t)0x00)
+
+/**
+  * @}
+  */
+
+/** @addtogroup I2C_Registers_Bits_Definition
+  * @{
+  */
+
+#define I2C_CR1_NOSTRETCH   ((uint8_t)0x80) /*!< Clock Stretching Disable (Slave mode) */
+#define I2C_CR1_ENGC        ((uint8_t)0x40) /*!< General Call Enable */
+#define I2C_CR1_ENPEC       ((uint8_t)0x20) /*!< PEC Enable */
+#define I2C_CR1_ARP         ((uint8_t)0x10) /*!< ARP Enable */
+#define I2C_CR1_SMBTYPE     ((uint8_t)0x08) /*!< SMBus type */
+#define I2C_CR1_SMBUS       ((uint8_t)0x02) /*!< SMBus mode */
+#define I2C_CR1_PE          ((uint8_t)0x01) /*!< Peripheral Enable */
+
+#define I2C_CR2_SWRST       ((uint8_t)0x80) /*!< Software Reset */
+#define I2C_CR2_ALERT       ((uint8_t)0x20) /*!< SMBus Alert*/
+#define I2C_CR2_PEC         ((uint8_t)0x10) /*!< Packet Error Checking */
+#define I2C_CR2_POS         ((uint8_t)0x08) /*!< Acknowledge */
+#define I2C_CR2_ACK         ((uint8_t)0x04) /*!< Acknowledge Enable */
+#define I2C_CR2_STOP        ((uint8_t)0x02) /*!< Stop Generation */
+#define I2C_CR2_START       ((uint8_t)0x01) /*!< Start Generation */
+
+#define I2C_FREQR_FREQ      ((uint8_t)0x3F) /*!< Peripheral Clock Frequency */
+
+#define I2C_OARL_ADD        ((uint8_t)0xFE) /*!< Interface Address bits [7..1] */
+#define I2C_OARL_ADD0       ((uint8_t)0x01) /*!< Interface Address bit0 */
+
+#define I2C_OARH_ADDMODE    ((uint8_t)0x80) /*!< Addressing Mode (Slave mode) */
+#define I2C_OARH_ADDCONF    ((uint8_t)0x40) /*!< Address mode configuration */
+#define I2C_OARH_ADD        ((uint8_t)0x06) /*!< Interface Address bits [9..8] */
+
+#define I2C_OAR2_ADD2       ((uint8_t)0xFE) /*!< Interface Address bits [7..1] */
+#define I2C_OAR2_ENDUAL     ((uint8_t)0x01) /*!< Dual addressing mode enable */
+
+#define I2C_DR_DR           ((uint8_t)0xFF) /*!< Data Register */
+
+#define I2C_SR1_TXE         ((uint8_t)0x80) /*!< Data Register Empty (transmitters) */
+#define I2C_SR1_RXNE        ((uint8_t)0x40) /*!< Data Register not Empty (receivers) */
+#define I2C_SR1_STOPF       ((uint8_t)0x10) /*!< Stop detection (Slave mode) */
+#define I2C_SR1_ADD10       ((uint8_t)0x08) /*!< 10-bit header sent (Master mode) */
+#define I2C_SR1_BTF         ((uint8_t)0x04) /*!< Byte Transfer Finished */
+#define I2C_SR1_ADDR        ((uint8_t)0x02) /*!< Address sent (master mode)/matched (slave mode) */
+#define I2C_SR1_SB          ((uint8_t)0x01) /*!< Start Bit (Master mode) */
+
+#define I2C_SR2_SMBALERT    ((uint8_t)0x80) /*!< SMBus Alert */
+#define I2C_SR2_TIMEOUT     ((uint8_t)0x40) /*!< Time out or TLow error */
+#define I2C_SR2_WUFH        ((uint8_t)0x20) /*!< Wake-up from Halt */
+#define I2C_SR2_PECERR      ((uint8_t)0x10) /*!< PEC error in reception */
+#define I2C_SR2_OVR         ((uint8_t)0x08) /*!< Overrun/Underrun */
+#define I2C_SR2_AF          ((uint8_t)0x04) /*!< Acknowledge Failure */
+#define I2C_SR2_ARLO        ((uint8_t)0x02) /*!< Arbitration Lost (master mode) */
+#define I2C_SR2_BERR        ((uint8_t)0x01) /*!< Bus Error */
+
+#define I2C_SR3_DUALF       ((uint8_t)0x80) /*!< Dual flag (Slave mode) */
+#define I2C_SR3_SMBHOST     ((uint8_t)0x40) /*!< SMBus Host Header (Slave mode) */
+#define I2C_SR3_SMBDEFAULT  ((uint8_t)0x20) /*!< SMBus Default Header (Slave mode) */
+#define I2C_SR3_GENCALL     ((uint8_t)0x10) /*!< General Call Header (Slave mode) */
+#define I2C_SR3_TRA         ((uint8_t)0x04) /*!< Transmitter/Receiver */
+#define I2C_SR3_BUSY        ((uint8_t)0x02) /*!< Bus Busy */
+#define I2C_SR3_MSL         ((uint8_t)0x01) /*!< Master/Slave */
+
+#define I2C_ITR_LAST        ((uint8_t)0x10) /*!< DMA Last transfer */
+#define I2C_ITR_DMAEN       ((uint8_t)0x08) /*!< DMA request Enable */
+#define I2C_ITR_ITBUFEN     ((uint8_t)0x04) /*!< Buffer Interrupt Enable */
+#define I2C_ITR_ITEVTEN     ((uint8_t)0x02) /*!< Event Interrupt Enable */
+#define I2C_ITR_ITERREN     ((uint8_t)0x01) /*!< Error Interrupt Enable */
+
+#define I2C_CCRL_CCR        ((uint8_t)0xFF) /*!< Clock Control Register (Master mode) */
+
+#define I2C_CCRH_FS         ((uint8_t)0x80) /*!< Master Mode Selection */
+#define I2C_CCRH_DUTY       ((uint8_t)0x40) /*!< Fast Mode Duty Cycle */
+#define I2C_CCRH_CCR        ((uint8_t)0x0F) /*!< Clock Control Register in Fast/Standard mode (Master mode) bits [11..8] */
+
+#define I2C_TRISER_TRISE    ((uint8_t)0x3F) /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+#define I2C_PECR_PEC        ((uint8_t)0xFF) /*!< Packet error checking */
+
+/**
+  * @}
+  */
+
+/*----------------------------------------------------------------------------*/
+
+/**
+  * @brief IR digital interface (IRTIM)
+  */
+typedef struct IRTIM_struct
+{
+  __IO uint8_t CR; /*!< control register */
+}
+IRTIM_TypeDef;
+/** @addtogroup IRTIM_Registers_Reset_Value
+  * @{
+  */
+#define IRTIM_CR_RESET_VALUE    ((uint8_t)0x00)
+
+
+/**
+* @}
+*/
+
+/** @addtogroup IRTIM_Registers_Bits_Definition
+  * @{
+  */
+/* CR*/
+#define IRTIM_CR_EN     ((uint8_t)0x01) /*!< IRTIM_OUT enable Mask. */
+#define IRTIM_CR_HSEN   ((uint8_t)0x02) /*!< High sink open drain buffer enable Mask */
+
+/**
+  * @}
+  */
+
+/*----------------------------------------------------------------------------*/
+
+/**
+  * @brief Interrupt Controller (ITC)
+  */
+typedef struct ITC_struct
+{
+  __IO uint8_t ISPR1; /*!<  Interrupt Software Priority register 1 */
+  __IO uint8_t ISPR2; /*!<  Interrupt Software Priority register 2 */
+  __IO uint8_t ISPR3; /*!<  Interrupt Software Priority register 3 */
+  __IO uint8_t ISPR4; /*!<  Interrupt Software Priority register 4 */
+  __IO uint8_t ISPR5; /*!<  Interrupt Software Priority register 5 */
+  __IO uint8_t ISPR6; /*!<  Interrupt Software Priority register 6 */
+  __IO uint8_t ISPR7; /*!<  Interrupt Software Priority register 7 */
+  __IO uint8_t ISPR8; /*!<  Interrupt Software Priority register 8 */
+}
+ITC_TypeDef;
+
+/** @addtogroup ITC_Registers_Reset_Value
+  * @{
+  */
+#define ITC_SPRX_RESET_VALUE ((uint8_t)0xFF) /*!< Reset value of Software Priority registers 0 to 7 */
+/**
+  * @}
+  */
+
+/*----------------------------------------------------------------------------*/
+
+/**
+  * @brief Internal Low Speed Watchdog (IWDG)
+  */
+typedef struct IWDG_struct
+{
+  __IO uint8_t KR;  /*!<  Low Speed Watchdog Key Register */
+  __IO uint8_t PR;  /*!<  Low Speed Watchdog Prescaler Register */
+  __IO uint8_t RLR; /*!<  Low Speed Watchdog Reload Register */
+}
+IWDG_TypeDef;
+
+/** @addtogroup IWDG_Registers_Reset_Value
+  * @{
+  */
+#define IWDG_RLR_RESET_VALUE    ((uint8_t)0xFF)  /*! <Reload Register Default Value */
+#define IWDG_PR_RESET_VALUE     ((uint8_t)0x00)  /*! <Prescaler Register Default Value */
+/**
+  * @}
+  */
+/*----------------------------------------------------------------------------*/
+
+
+/**
+  * @brief Wait For Event (WFE) peripheral registers.
+  */
+/** @addtogroup WFE_Registers
+  * @{
+  */
+typedef struct WFE_struct
+{
+  __IO uint8_t CR1;  /*!<  Wait for event control register 1 */
+  __IO uint8_t CR2;  /*!<  Wait for event control register 2 */
+  __IO uint8_t CR3;  /*!<  Wait for event control register 3 */
+  __IO uint8_t CR4;  /*!<  Wait for event control register 4 */
+}
+WFE_TypeDef;
+/**
+  * @}
+  */
+/** @addtogroup WFE_Registers_Reset_Value
+  * @{
+  */
+
+#define WFE_CRX_RESET_VALUE ((uint8_t)0x00) /*!< Reset value wait for event control register */
+/**
+  * @}
+  */
+
+/** @addtogroup WFE_Registers_Bits_Definition
+  * @{
+  */
+
+#define WFE_CR1_EXTI_EV3      ((uint8_t)0x80)  /*!< External interrupt event 3 Mask */
+#define WFE_CR1_EXTI_EV2      ((uint8_t)0x40)  /*!< External interrupt event 2 Mask */
+#define WFE_CR1_EXTI_EV1      ((uint8_t)0x20)  /*!< External interrupt event 1 Mask */
+#define WFE_CR1_EXTI_EV0      ((uint8_t)0x10)  /*!< External interrupt event 0 Mask */
+#define WFE_CR1_TIM1_EV1      ((uint8_t)0x08)  /*!< TIM1 event 1 Mask */
+#define WFE_CR1_TIM1_EV0      ((uint8_t)0x04)  /*!< TIM1 event 0 Mask */
+#define WFE_CR1_TIM2_EV1      ((uint8_t)0x02)  /*!< TIM2 event 1 Mask */
+#define WFE_CR1_TIM2_EV0      ((uint8_t)0x01)  /*!< TIM2 event 0 Mask */
+
+#define WFE_CR2_ADC1_COMP_EV  ((uint8_t)0x80)  /*!< ADC / COMP event Mask*/
+#define WFE_CR2_EXTI_EVEF     ((uint8_t)0x40)  /*!< External interrupt event on Port E or Port F Mask */
+#define WFE_CR2_EXTI_EVDH     ((uint8_t)0x20)  /*!< External interrupt event on Port D or Port H Mask */
+#define WFE_CR2_EXTI_EVBG     ((uint8_t)0x10)  /*!< External interrupt event on Port B or Port G Mask */
+#define WFE_CR2_EXTI_EV7      ((uint8_t)0x08)  /*!< External interrupt event 7 Mask */
+#define WFE_CR2_EXTI_EV6      ((uint8_t)0x04)  /*!< External interrupt event 6 Mask */
+#define WFE_CR2_EXTI_EV5      ((uint8_t)0x02)  /*!< External interrupt event 5 Mask */
+#define WFE_CR2_EXTI_EV4      ((uint8_t)0x01)  /*!< External interrupt event 4 Mask */
+
+#define WFE_CR3_DMA1CH23_EV   ((uint8_t)0x80)  /*!< DMA1 channel 2 and 3 interrupt event Mask */
+#define WFE_CR3_DMA1CH01_EV   ((uint8_t)0x40)  /*!< DMA1 channel 0 and 1 interrupt event Mask */
+#define WFE_CR3_USART1_EV     ((uint8_t)0x20)  /*!< USART1 Rx and Tx interrupt event Mask */
+#define WFE_CR3_I2C1_EV       ((uint8_t)0x10)  /*!< I2C1 Rx and Tx interrupt event Mask */
+#define WFE_CR3_SPI1_EV       ((uint8_t)0x08)  /*!< SPI1 Rx and Tx interrupt event Mask */
+#define WFE_CR3_TIM4_EV       ((uint8_t)0x04)  /*!< TIM4 event Mask */
+#define WFE_CR3_TIM3_EV1      ((uint8_t)0x02)  /*!< TIM3 event 1 Mask */
+#define WFE_CR3_TIM3_EV0      ((uint8_t)0x01)  /*!< TIM3 event 0 Mask */
+
+#define WFE_CR4_AES_EV        ((uint8_t)0x40)  /*!< AES event Mask */
+#define WFE_CR4_TIM5_EV1      ((uint8_t)0x20)  /*!< TIM5 event 1 Mask */
+#define WFE_CR4_TIM5_EV0      ((uint8_t)0x10)  /*!< TIM5 event 0 Mask */
+#define WFE_CR4_USART3_EV     ((uint8_t)0x08)  /*!< USART3 Rx and Tx interrupt event Mask */
+#define WFE_CR4_USART2_EV     ((uint8_t)0x04)  /*!< USART2 Rx and Tx interrupt event Mask */
+#define WFE_CR4_SPI2_EV       ((uint8_t)0x02)  /*!< SPI2 Rx and Tx interrupt event Mask */
+#define WFE_CR4_RTC_CSS_EV    ((uint8_t)0x01)  /*!< RTC or CSS on LSE interrupt event Mask */
+
+
+/**
+  * @}
+  */
+
+/*----------------------------------------------------------------------------*/
+/**
+  * @brief Option Bytes (OPT)
+  */
+typedef struct OPT_struct
+{
+  __IO uint8_t ROP;        /*!< Read-out protection*/
+  uint8_t  RESERVED1;
+  __IO uint8_t UBC;        /*!< User Boot code size*/
+  uint8_t  RESERVED2;
+  uint8_t  RESERVED3;
+  uint8_t  RESERVED4;
+  uint8_t  RESERVED5;
+  __IO uint8_t PCODESIZE;
+  __IO uint8_t WDG;        /*!< Independent and Window watchdog option */
+  __IO uint8_t XTSTARTUP;  /*!< HSE and LSE option */
+  __IO uint8_t BOR;        /*!< Brownout option */
+}
+OPT_TypeDef;
+
+/**
+  * @}
+  */
+/*----------------------------------------------------------------------------*/
+
+/**
+  * @brief Reset Controller (RST)
+  */
+typedef struct RST_struct
+{
+  __IO uint8_t CR;  /*!< Multiplex Reset Pad */
+  __IO uint8_t SR;  /*!< Reset status register */
+
+}
+RST_TypeDef;
+/**
+  * @}
+  */
+
+/** @addtogroup RST_Registers_Reset_Value
+  * @{
+  */
+
+#define RST_CR_RESET_VALUE    ((uint8_t)0x00) /*!< Reset pin configuration register  1 reset value */
+#define RST_SR_RESET_VALUE    ((uint8_t)0x01) /*!< Reset status register 2 reset value */
+
+/**
+  * @}
+  */
+
+/** @addtogroup RST_Registers_Bits_Definition
+  * @{
+  */
+#define RST_SR_BORF           ((uint8_t)0x20) /*!< Brownout reset flag mask           */
+#define RST_SR_WWDGF          ((uint8_t)0x10) /*!< Window Watchdog reset flag mask */
+#define RST_SR_SWIMF          ((uint8_t)0x08) /*!< SWIM reset flag mask            */
+#define RST_SR_ILLOPF         ((uint8_t)0x04) /*!< Illegal opcode reset flag mask    */
+#define RST_SR_IWDGF          ((uint8_t)0x02) /*!< Independent Watchdog reset flag mask    */
+#define RST_SR_PORF           ((uint8_t)0x01) /*!< Power On Reset (POR) flag mask    */
+
+/**
+  * @}
+  */
+/*----------------------------------------------------------------------------*/
+
+/**
+  * @brief Power Control (PWR)
+  */
+typedef struct PWR_struct
+{
+  __IO uint8_t CSR1;          /*!< PWR control status register 1 */
+  __IO uint8_t CSR2;          /*!< PWR control status register 2 */
+
+}
+PWR_TypeDef;
+/**
+  * @}
+  */
+
+/** @addtogroup PWR_Registers_Reset_Value
+  * @{
+  */
+
+#define PWR_CSR1_RESET_VALUE    ((uint8_t)0x00) /*!< Control Status Register 1 reset value */
+#define PWR_CSR2_RESET_VALUE    ((uint8_t)0x00) /*!< Control Status Register 2 reset value */
+
+/**
+  * @}
+  */
+
+/** @addtogroup PWR_Registers_Bits_Definition
+  * @{
+  */
+#define PWR_CSR1_PVDOF          ((uint8_t)0x40) /*!< PVD output flag mask         */
+#define PWR_CSR1_PVDIF          ((uint8_t)0x20) /*!< PVD interrupt flag mask */
+#define PWR_CSR1_PVDIEN         ((uint8_t)0x10) /*!< PVD interrupt enable mask            */
+#define PWR_CSR1_PLS            ((uint8_t)0x0E) /*!< PVD Level thresholds selector mask    */
+#define PWR_CSR1_PVDE           ((uint8_t)0x01) /*!< Power Voltage Detector (PVD) enable mask */
+
+
+#define PWR_CSR2_FWU            ((uint8_t)0x04) /*!< Fast wake up configuration mask */
+#define PWR_CSR2_ULP            ((uint8_t)0x02) /*!< Ultra Low power configuration mask  */
+#define PWR_CR2_VREFINTF        ((uint8_t)0x01) /*!< Internal reference voltage status flag mask  */
+/**
+  * @}
+  */
+/*----------------------------------------------------------------------------*/
+
+/**
+  * @brief Routing Interface (RI)
+  */
+typedef struct RI_struct
+{
+  uint8_t RESERVED;
+  __IO uint8_t ICR1;   /*!< Timer input capture routing register 1 */
+  __IO uint8_t ICR2;   /*!< Timer input capture routing register 2 */
+  __IO uint8_t IOIR1;  /*!< I/O input register 1 */
+  __IO uint8_t IOIR2;  /*!< I/O input register 2 */
+  __IO uint8_t IOIR3;  /*!< I/O input register 3 */
+  __IO uint8_t IOCMR1; /*!< I/O control mode register 1 */
+  __IO uint8_t IOCMR2; /*!< I/O control mode register 2 */
+  __IO uint8_t IOCMR3; /*!< I/O control mode register 3 */
+  __IO uint8_t IOSR1;  /*!< I/O switch register 1*/
+  __IO uint8_t IOSR2;  /*!< I/O switch register 2*/
+  __IO uint8_t IOSR3;  /*!< I/O switch register 3*/
+  __IO uint8_t IOGCR;  /*!< I/O group control register */
+  __IO uint8_t ASCR1;  /*!< Analog Switch Control register 1 */
+  __IO uint8_t ASCR2;  /*!< Analog Switch Control register 2 */
+  __IO uint8_t RCR;    /*!< Resistor control register  */
+  uint8_t RESERVED1[16];
+  __IO uint8_t CR;     /*!< Control Register  */
+  __IO uint8_t IOMR1;   /*!< IO Mask Register 1 */
+  __IO uint8_t IOMR2;   /*!< IO Mask Register 2 */
+  __IO uint8_t IOMR3;   /*!< IO Mask Register 3 */
+  __IO uint8_t IOMR4;   /*!< IO Mask Register 4*/
+  __IO uint8_t IOIR4;  /*!< I/O input register 4 */
+  __IO uint8_t IOCMR4; /*!< I/O control mode register 4 */
+  __IO uint8_t IOSR4;  /*!< I/O switch register 4 */
+}RI_TypeDef;
+/**
+  * @}
+  */
+
+/** @addtogroup RI_Registers_Reset_Value
+  * @{
+  */
+
+#define RI_ICR1_RESET_VALUE     ((uint8_t)0x00) /*!< Timer input capture routing register 1 reset value */
+#define RI_ICR2_RESET_VALUE     ((uint8_t)0x00) /*!< Timer input capture routing register 2 reset value */
+
+#define RI_IOCMR1_RESET_VALUE   ((uint8_t)0x00) /*!< I/O control mode register 1 reset value */
+#define RI_IOCMR2_RESET_VALUE   ((uint8_t)0x00) /*!< I/O control mode register 2 reset value */
+#define RI_IOCMR3_RESET_VALUE   ((uint8_t)0x00) /*!< I/O control mode register 3 reset value */
+
+#define RI_IOSR1_RESET_VALUE    ((uint8_t)0x00) /*!< I/O switch register 1 reset value */
+#define RI_IOSR2_RESET_VALUE    ((uint8_t)0x00) /*!< I/O switch register 2 reset value */
+#define RI_IOSR3_RESET_VALUE    ((uint8_t)0x00) /*!< I/O switch register 3 reset value */
+
+#define RI_IOGCR_RESET_VALUE    ((uint8_t)0xFF) /*!< IO group control register reset value */
+
+#define RI_ASCR1_RESET_VALUE    ((uint8_t)0x00) /*!< Analog switch register 1 reset value */
+#define RI_ASCR2_RESET_VALUE    ((uint8_t)0x00) /*!< Analog switch register 2 reset value */
+#define RI_RCR_RESET_VALUE      ((uint8_t)0x00) /*!< Resistor control register reset value */
+
+#define RI_IOCMR4_RESET_VALUE   ((uint8_t)0x00) /*!< I/O control mode register 4 reset value */
+#define RI_IOSR4_RESET_VALUE    ((uint8_t)0x00) /*!< I/O switch register 4 reset value */
+
+/**
+  * @}
+  */
+
+/** @addtogroup RI_Registers_Bits_Definition
+  * @{
+  */
+#define RI_ICR1_IC2CS          ((uint8_t)0x1F) /*!< TIM1 Input Capture 2 I/O selection mask */
+
+#define RI_ICR2_IC3CS          ((uint8_t)0x1F) /*!< TIM1 Input Capture 3 I/O selection mask */
+
+#define RI_IOIR1_CH1I          ((uint8_t)0x01) /*!< Channel 1 I/O pin input value */
+#define RI_IOIR1_CH4I          ((uint8_t)0x02) /*!< Channel 4 I/O pin input value */
+#define RI_IOIR1_CH7I          ((uint8_t)0x04) /*!< Channel 7 I/O pin input value */
+#define RI_IOIR1_CH10I         ((uint8_t)0x08) /*!< Channel 10 I/O pin input value */
+#define RI_IOIR1_CH13I         ((uint8_t)0x10) /*!< Channel 13 I/O pin input value */
+#define RI_IOIR1_CH16I         ((uint8_t)0x20) /*!< Channel 16 I/O pin input value */
+#define RI_IOIR1_CH19I         ((uint8_t)0x40) /*!< Channel 19 I/O pin input value */
+#define RI_IOIR1_CH22I         ((uint8_t)0x80) /*!< Channel 22 I/O pin input value */
+
+#define RI_IOIR2_CH2I          ((uint8_t)0x01) /*!< Channel 2 I/O pin input value */
+#define RI_IOIR2_CH5I          ((uint8_t)0x02) /*!< Channel 5 I/O pin input value */
+#define RI_IOIR2_CH8I          ((uint8_t)0x04) /*!< Channel 8 I/O pin input value */
+#define RI_IOIR2_CH11I         ((uint8_t)0x08) /*!< Channel 11 I/O pin input value */
+#define RI_IOIR2_CH14I         ((uint8_t)0x10) /*!< Channel 14 I/O pin input value */
+#define RI_IOIR2_CH17I         ((uint8_t)0x20) /*!< Channel 17 I/O pin input value */
+#define RI_IOIR2_CH20I         ((uint8_t)0x40) /*!< Channel 20 I/O pin input value */
+#define RI_IOIR2_CH23I         ((uint8_t)0x80) /*!< Channel 23 I/O pin input value */
+
+#define RI_IOIR3_CH3I          ((uint8_t)0x01) /*!< Channel 3 I/O pin input value */
+#define RI_IOIR3_CH6I          ((uint8_t)0x02) /*!< Channel 6 I/O pin input value */
+#define RI_IOIR3_CH9I          ((uint8_t)0x04) /*!< Channel 9 I/O pin input value */
+#define RI_IOIR3_CH12I         ((uint8_t)0x08) /*!< Channel 12 I/O pin input value */
+#define RI_IOIR3_CH15I         ((uint8_t)0x10) /*!< Channel 15 I/O pin input value */
+#define RI_IOIR3_CH18I         ((uint8_t)0x20) /*!< Channel 18 I/O pin input value */
+#define RI_IOIR3_CH21I         ((uint8_t)0x40) /*!< Channel 21 I/O pin input value */
+#define RI_IOIR3_CH24I         ((uint8_t)0x80) /*!< Channel 24 I/O pin input value */
+
+#define RI_IOCMR1_CH1M          ((uint8_t)0x01) /*!< Channel 1 I/O control mode */
+#define RI_IOCMR1_CH4M          ((uint8_t)0x02) /*!< Channel 4 I/O control mode */
+#define RI_IOCMR1_CH7M          ((uint8_t)0x04) /*!< Channel 7 I/O control mode */
+#define RI_IOCMR1_CH10M         ((uint8_t)0x08) /*!< Channel 10 I/O control mode */
+#define RI_IOCMR1_CH13M         ((uint8_t)0x10) /*!< Channel 13 I/O control mode */
+#define RI_IOCMR1_CH16M         ((uint8_t)0x20) /*!< Channel 16 I/O control mode */
+#define RI_IOCMR1_CH19M         ((uint8_t)0x40) /*!< Channel 19 I/O control mode */
+#define RI_IOCMR1_CH22M         ((uint8_t)0x80) /*!< Channel 22 I/O control mode */
+
+#define RI_IOCMR2_CH2M          ((uint8_t)0x01) /*!< Channel 2 I/O control mode */
+#define RI_IOCMR2_CH5M          ((uint8_t)0x02) /*!< Channel 5 I/O control mode */
+#define RI_IOCMR2_CH8M          ((uint8_t)0x04) /*!< Channel 8 I/O control mode */
+#define RI_IOCMR2_CH11M         ((uint8_t)0x08) /*!< Channel 11 I/O control mode */
+#define RI_IOCMR2_CH14M         ((uint8_t)0x10) /*!< Channel 14 I/O control mode */
+#define RI_IOCMR2_CH17M         ((uint8_t)0x20) /*!< Channel 17 I/O control mode */
+#define RI_IOCMR2_CH20M         ((uint8_t)0x40) /*!< Channel 20 I/O control mode */
+#define RI_IOCMR2_CH23M         ((uint8_t)0x80) /*!< Channel 23 I/O control mode */
+
+#define RI_IOCMR3_CH3M          ((uint8_t)0x01) /*!< Channel 3 I/O control mode */
+#define RI_IOCMR3_CH6M          ((uint8_t)0x02) /*!< Channel 6 I/O control mode */
+#define RI_IOCMR3_CH9M          ((uint8_t)0x04) /*!< Channel 9 I/O control mode */
+#define RI_IOCMR3_CH12M         ((uint8_t)0x08) /*!< Channel 12 I/O control mode */
+#define RI_IOCMR3_CH15M         ((uint8_t)0x10) /*!< Channel 15 I/O control mode */
+#define RI_IOCMR3_CH18M         ((uint8_t)0x20) /*!< Channel 18 I/O control mode */
+#define RI_IOCMR3_CH21M         ((uint8_t)0x40) /*!< Channel 21 I/O control mode */
+#define RI_IOCMR3_CH24M         ((uint8_t)0x80) /*!< Channel 24 I/O control mode */
+
+#define RI_IOSR1_CH1E          ((uint8_t)0x01) /*!< Channel 1 I/O switch control */
+#define RI_IOSR1_CH4E          ((uint8_t)0x02) /*!< Channel 4 I/O switch control */
+#define RI_IOSR1_CH7E          ((uint8_t)0x04) /*!< Channel 7 I/O switch control */
+#define RI_IOSR1_CH10E         ((uint8_t)0x08) /*!< Channel 10 I/O switch control */
+#define RI_IOSR1_CH13E         ((uint8_t)0x10) /*!< Channel 13 I/O switch control */
+#define RI_IOSR1_CH16E         ((uint8_t)0x20) /*!< Channel 16 I/O switch control */
+#define RI_IOSR1_CH19E         ((uint8_t)0x40) /*!< Channel 19 I/O switch control */
+#define RI_IOSR1_CH22E         ((uint8_t)0x80) /*!< Channel 22 I/O switch control */
+
+#define RI_IOSR2_CH2E          ((uint8_t)0x01) /*!< Channel 2 I/O switch control */
+#define RI_IOSR2_CH5E          ((uint8_t)0x02) /*!< Channel 5 I/O switch control */
+#define RI_IOSR2_CH8E          ((uint8_t)0x04) /*!< Channel 8 I/O switch control */
+#define RI_IOSR2_CH11E         ((uint8_t)0x08) /*!< Channel 11 I/O switch control */
+#define RI_IOSR2_CH14E         ((uint8_t)0x10) /*!< Channel 14 I/O switch control */
+#define RI_IOSR2_CH17E         ((uint8_t)0x20) /*!< Channel 17 I/O switch control */
+#define RI_IOSR2_CH20E         ((uint8_t)0x40) /*!< Channel 20 I/O switch control */
+#define RI_IOSR2_CH23E         ((uint8_t)0x80) /*!< Channel 23 I/O switch control */
+
+#define RI_IOSR3_CH3E          ((uint8_t)0x01) /*!< Channel 3 I/O switch control */
+#define RI_IOSR3_CH6E          ((uint8_t)0x02) /*!< Channel 6 I/O switch control */
+#define RI_IOSR3_CH9E          ((uint8_t)0x04) /*!< Channel 9 I/O switch control */
+#define RI_IOSR3_CH12E         ((uint8_t)0x08) /*!< Channel 12 I/O switch control */
+#define RI_IOSR3_CH15E         ((uint8_t)0x10) /*!< Channel 15 I/O switch control */
+#define RI_IOSR3_CH18E         ((uint8_t)0x20) /*!< Channel 18 I/O switch control */
+#define RI_IOSR3_CH21E         ((uint8_t)0x40) /*!< Channel 21 I/O switch control */
+#define RI_IOSR3_CH24E         ((uint8_t)0x80) /*!< Channel 24 I/O switch control */
+
+#define RI_IOGCR_IOM1          ((uint8_t)0x03) /*!< I/O mode 1 */
+#define RI_IOGCR_IOM2          ((uint8_t)0x0C) /*!< I/O mode 2 */
+#define RI_IOGCR_IOM3          ((uint8_t)0x30) /*!< I/O mode 3 */
+#define RI_IOGCR_IOM4          ((uint8_t)0xC0) /*!< I/O mode 4 */
+
+#define RI_ASCR1_AS0           ((uint8_t)0x01) /*!< Analog switch AS0 control */
+#define RI_ASCR1_AS1           ((uint8_t)0x02) /*!< Analog switch AS1 control */
+#define RI_ASCR1_AS2           ((uint8_t)0x04) /*!< Analog switch AS2 control */
+#define RI_ASCR1_AS3           ((uint8_t)0x08) /*!< Analog switch AS3 control */
+#define RI_ASCR1_AS4           ((uint8_t)0x10) /*!< Analog switch AS4 control */
+#define RI_ASCR1_AS5           ((uint8_t)0x20) /*!< Analog switch AS5 control */
+#define RI_ASCR1_AS6           ((uint8_t)0x40) /*!< Analog switch AS6 control */
+#define RI_ASCR1_AS7           ((uint8_t)0x80) /*!< Analog switch AS7 control */
+
+#define RI_ASCR2_AS8           ((uint8_t)0x01) /*!< Analog switch AS8 control */
+#define RI_ASCR2_AS9           ((uint8_t)0x02) /*!< Analog switch AS9 control */
+#define RI_ASCR2_AS10          ((uint8_t)0x04) /*!< Analog switch AS10 control */
+#define RI_ASCR2_AS11          ((uint8_t)0x08) /*!< Analog switch AS11 control */
+#define RI_ASCR2_AS14          ((uint8_t)0x40) /*!< Analog switch AS14 control */
+
+#define RI_RCR_400KPD          ((uint8_t)0x08) /*!< 400K pull-down resistor Mask. */
+#define RI_RCR_10KPD           ((uint8_t)0x04) /*!< 10K pull-down resistor Mask. */
+#define RI_RCR_400KPU          ((uint8_t)0x02) /*!< 400K pull-up resistor Mask. */
+#define RI_RCR_10KPU           ((uint8_t)0x01) /*!< 10K pull-up resistor Mask. */
+
+#define RI_IOSR4_CH29E         ((uint8_t)0x01) /*!< Channel 29 I/O switch control */
+#define RI_IOSR4_CH26E         ((uint8_t)0x02) /*!< Channel 26 I/O switch control */
+#define RI_IOSR4_CH27E         ((uint8_t)0x40) /*!< Channel 27 I/O switch control */
+#define RI_IOSR4_CH28E         ((uint8_t)0x80) /*!< Channel 28 I/O switch control */
+
+/**
+  * @}
+  */
+/*----------------------------------------------------------------------------ok*/
+
+/**
+  * @brief Serial Peripheral Interface (SPI)
+  */
+typedef struct SPI_struct
+{
+  __IO uint8_t CR1;    /*!< SPI control register 1 */
+  __IO uint8_t CR2;    /*!< SPI control register 2 */
+  __IO uint8_t CR3;    /*!< SPI DMA and interrupt control register */
+  __IO uint8_t SR;     /*!< SPI status register */
+  __IO uint8_t DR;     /*!< SPI data I/O register */
+  __IO uint8_t CRCPR;  /*!< SPI CRC polynomial register */
+  __IO uint8_t RXCRCR; /*!< SPI Rx CRC register */
+  __IO uint8_t TXCRCR; /*!< SPI Tx CRC register */
+}
+SPI_TypeDef;
+
+/** @addtogroup SPI_Registers_Reset_Value
+  * @{
+  */
+
+#define SPI_CR1_RESET_VALUE    ((uint8_t)0x00) /*!< Control Register 1 reset value */
+#define SPI_CR2_RESET_VALUE    ((uint8_t)0x00) /*!< Control Register 2 reset value */
+#define SPI_CR3_RESET_VALUE    ((uint8_t)0x00) /*!< DMA and Interrupt Control Register reset value */
+#define SPI_SR_RESET_VALUE     ((uint8_t)0x02) /*!< Status Register reset value */
+#define SPI_DR_RESET_VALUE     ((uint8_t)0x00) /*!< Data Register reset value */
+#define SPI_CRCPR_RESET_VALUE  ((uint8_t)0x07) /*!< Polynomial Register reset value */
+#define SPI_RXCRCR_RESET_VALUE ((uint8_t)0x00) /*!< RX CRC Register reset value */
+#define SPI_TXCRCR_RESET_VALUE ((uint8_t)0x00) /*!< TX CRC Register reset value */
+
+/**
+  * @}
+  */
+
+/** @addtogroup SPI_Registers_Bits_Definition
+  * @{
+  */
+
+#define SPI_CR1_LSBFIRST ((uint8_t)0x80) /*!< Frame format mask */
+#define SPI_CR1_SPE      ((uint8_t)0x40) /*!< Enable bits mask */
+#define SPI_CR1_BR       ((uint8_t)0x38) /*!< Baud rate control mask */
+#define SPI_CR1_MSTR     ((uint8_t)0x04) /*!< Master Selection mask */
+#define SPI_CR1_CPOL     ((uint8_t)0x02) /*!< Clock Polarity mask */
+#define SPI_CR1_CPHA     ((uint8_t)0x01) /*!< Clock Phase mask */
+
+#define SPI_CR2_BDM      ((uint8_t)0x80) /*!< Bi-directional data mode enable mask */
+#define SPI_CR2_BDOE     ((uint8_t)0x40) /*!< Output enable in bi-directional mode mask */
+#define SPI_CR2_CRCEN    ((uint8_t)0x20) /*!< Hardware CRC calculation enable mask */
+#define SPI_CR2_CRCNEXT  ((uint8_t)0x10) /*!< Transmit CRC next mask */
+#define SPI_CR2_RXONLY   ((uint8_t)0x04) /*!< Receive only mask */
+#define SPI_CR2_SSM      ((uint8_t)0x02) /*!< Software slave management mask */
+#define SPI_CR2_SSI      ((uint8_t)0x01) /*!< Internal slave select mask */
+
+#define SPI_CR3_TXIE     ((uint8_t)0x80) /*!< Tx buffer empty interrupt enable mask */
+#define SPI_CR3_RXIE     ((uint8_t)0x40) /*!< Rx buffer empty interrupt enable mask */
+#define SPI_CR3_ERRIE    ((uint8_t)0x20) /*!< Error interrupt enable mask */
+#define SPI_CR3_WKIE     ((uint8_t)0x10) /*!< Wake-up interrupt enable mask */
+#define SPI_CR3_TXDMAEN  ((uint8_t)0x02) /*!< Tx Buffer DMA enable mask */
+#define SPI_CR3_RXDMAEN  ((uint8_t)0x01) /*!< Rx Buffer DMA enable mask */
+
+#define SPI_SR_BSY       ((uint8_t)0x80) /*!< Busy flag */
+#define SPI_SR_OVR       ((uint8_t)0x40) /*!< Overrun flag */
+#define SPI_SR_MODF      ((uint8_t)0x20) /*!< Mode fault */
+#define SPI_SR_CRCERR    ((uint8_t)0x10) /*!< CRC error flag */
+#define SPI_SR_WKUP      ((uint8_t)0x08) /*!< Wake-Up flag */
+#define SPI_SR_TXE       ((uint8_t)0x02) /*!< Transmit buffer empty */
+#define SPI_SR_RXNE      ((uint8_t)0x01) /*!< Receive buffer not empty */
+/**
+  * @}
+  */
+
+/*----------------------------------------------------------------------------ok*/
+
+/**
+  * @brief Advanced 16 bit timer with complementary PWM outputs (TIM1)
+  */
+typedef struct TIM1_struct
+{
+  __IO uint8_t CR1;   /*!< control register 1 */
+  __IO uint8_t CR2;   /*!< control register 2 */
+  __IO uint8_t SMCR;  /*!< Synchro mode control register */
+  __IO uint8_t ETR;   /*!< external trigger register */
+  __IO uint8_t DER;   /*!< DMA requests enable register */
+  __IO uint8_t IER;   /*!< interrupt enable register*/
+  __IO uint8_t SR1;   /*!< status register 1 */
+  __IO uint8_t SR2;   /*!< status register 2 */
+  __IO uint8_t EGR;   /*!< event generation register */
+  __IO uint8_t CCMR1; /*!< CC mode register 1 */
+  __IO uint8_t CCMR2; /*!< CC mode register 2 */
+  __IO uint8_t CCMR3; /*!< CC mode register 3 */
+  __IO uint8_t CCMR4; /*!< CC mode register 4 */
+  __IO uint8_t CCER1; /*!< CC enable register 1 */
+  __IO uint8_t CCER2; /*!< CC enable register 2 */
+  __IO uint8_t CNTRH; /*!< counter high */
+  __IO uint8_t CNTRL; /*!< counter low */
+  __IO uint8_t PSCRH; /*!< prescaler high */
+  __IO uint8_t PSCRL; /*!< prescaler low */
+  __IO uint8_t ARRH;  /*!< auto-reload register high */
+  __IO uint8_t ARRL;  /*!< auto-reload register low */
+  __IO uint8_t RCR;   /*!< Repetition Counter register */
+  __IO uint8_t CCR1H; /*!< capture/compare register 1 high */
+  __IO uint8_t CCR1L; /*!< capture/compare register 1 low */
+  __IO uint8_t CCR2H; /*!< capture/compare register 2 high */
+  __IO uint8_t CCR2L; /*!< capture/compare register 2 low */
+  __IO uint8_t CCR3H; /*!< capture/compare register 3 high */
+  __IO uint8_t CCR3L; /*!< capture/compare register 3 low */
+  __IO uint8_t CCR4H; /*!< capture/compare register 3 high */
+  __IO uint8_t CCR4L; /*!< capture/compare register 3 low */
+  __IO uint8_t BKR;   /*!< Break Register */
+  __IO uint8_t DTR;   /*!< dead-time register */
+  __IO uint8_t OISR;  /*!< Output idle register */
+  __IO uint8_t DCR1;  /*!< DMA control register 1 */
+  __IO uint8_t DCR2;  /*!< DMA control register 2 */
+  __IO uint8_t DMAR;  /*!< DMA Address for brust mode */
+}
+TIM1_TypeDef;
+
+/** @addtogroup TIM1_Registers_Reset_Value
+  * @{
+  */
+#define TIM1_CR1_RESET_VALUE   ((uint8_t)0x00)
+#define TIM1_CR2_RESET_VALUE   ((uint8_t)0x00)
+#define TIM1_SMCR_RESET_VALUE  ((uint8_t)0x00)
+#define TIM1_ETR_RESET_VALUE   ((uint8_t)0x00)
+#define TIM1_DER_RESET_VALUE   ((uint8_t)0x00)
+#define TIM1_IER_RESET_VALUE   ((uint8_t)0x00)
+#define TIM1_SR1_RESET_VALUE   ((uint8_t)0x00)
+#define TIM1_SR2_RESET_VALUE   ((uint8_t)0x00)
+#define TIM1_EGR_RESET_VALUE   ((uint8_t)0x00)
+#define TIM1_CCMR1_RESET_VALUE ((uint8_t)0x00)
+#define TIM1_CCMR2_RESET_VALUE ((uint8_t)0x00)
+#define TIM1_CCMR3_RESET_VALUE ((uint8_t)0x00)
+#define TIM1_CCMR4_RESET_VALUE ((uint8_t)0x00)
+#define TIM1_CCER1_RESET_VALUE ((uint8_t)0x00)
+#define TIM1_CCER2_RESET_VALUE ((uint8_t)0x00)
+#define TIM1_CNTRH_RESET_VALUE ((uint8_t)0x00)
+#define TIM1_CNTRL_RESET_VALUE ((uint8_t)0x00)
+#define TIM1_PSCRH_RESET_VALUE ((uint8_t)0x00)
+#define TIM1_PSCRL_RESET_VALUE ((uint8_t)0x00)
+#define TIM1_ARRH_RESET_VALUE  ((uint8_t)0xFF)
+#define TIM1_ARRL_RESET_VALUE  ((uint8_t)0xFF)
+#define TIM1_RCR_RESET_VALUE   ((uint8_t)0x00)
+#define TIM1_CCR1H_RESET_VALUE ((uint8_t)0x00)
+#define TIM1_CCR1L_RESET_VALUE ((uint8_t)0x00)
+#define TIM1_CCR2H_RESET_VALUE ((uint8_t)0x00)
+#define TIM1_CCR2L_RESET_VALUE ((uint8_t)0x00)
+#define TIM1_CCR3H_RESET_VALUE ((uint8_t)0x00)
+#define TIM1_CCR3L_RESET_VALUE ((uint8_t)0x00)
+#define TIM1_CCR4H_RESET_VALUE ((uint8_t)0x00)
+#define TIM1_CCR4L_RESET_VALUE ((uint8_t)0x00)
+#define TIM1_BKR_RESET_VALUE   ((uint8_t)0x00)
+#define TIM1_DTR_RESET_VALUE   ((uint8_t)0x00)
+#define TIM1_OISR_RESET_VALUE  ((uint8_t)0x00)
+#define TIM1_DCR1_RESET_VALUE  ((uint8_t)0x00)
+#define TIM1_DCR2_RESET_VALUE  ((uint8_t)0x00)
+#define TIM1_DMAR_RESET_VALUE  ((uint8_t)0x00)
+
+/**
+  * @}
+  */
+
+/** @addtogroup TIM1_Registers_Bits_Definition
+  * @{
+  */
+/* CR1*/
+#define TIM1_CR1_ARPE    ((uint8_t)0x80) /*!< Auto-Reload Preload Enable mask. */
+#define TIM1_CR1_CMS     ((uint8_t)0x60) /*!< Center-aligned Mode Selection mask. */
+#define TIM1_CR1_DIR     ((uint8_t)0x10) /*!< Direction mask. */
+#define TIM1_CR1_OPM     ((uint8_t)0x08) /*!< One Pulse Mode mask. */
+#define TIM1_CR1_URS     ((uint8_t)0x04) /*!< Update Request Source mask. */
+#define TIM1_CR1_UDIS    ((uint8_t)0x02) /*!< Update DIsable mask. */
+#define TIM1_CR1_CEN     ((uint8_t)0x01) /*!< Counter Enable mask. */
+/* CR2*/
+#define TIM1_CR2_TI1S    ((uint8_t)0x80) /*!< TI1 selection  */
+#define TIM1_CR2_MMS     ((uint8_t)0x70) /*!< MMS Selection mask. */
+#define TIM1_CR2_CCDS    ((uint8_t)0x08) /*!< Capture/Compare DMA Selection */
+#define TIM1_CR2_CCUS    ((uint8_t)0x04) /*!< Capture/Compare Control Update Selection mask. */
+#define TIM1_CR2_CCPC    ((uint8_t)0x01) /*!< Capture/Compare Preloaded Control mask. */
+/* SMCR*/
+#define TIM1_SMCR_MSM    ((uint8_t)0x80) /*!< Master/Slave Mode mask. */
+#define TIM1_SMCR_TS     ((uint8_t)0x70) /*!< Trigger Selection mask. */
+#define TIM1_SMCR_OCCS   ((uint8_t)0x08) /*!< OCREFCLR Selection mask. */
+#define TIM1_SMCR_SMS    ((uint8_t)0x07) /*!< Slave Mode Selection mask. */
+/* ETR*/
+#define TIM1_ETR_ETP     ((uint8_t)0x80) /*!< External Trigger Polarity mask. */
+#define TIM1_ETR_ECE     ((uint8_t)0x40) /*!< External Clock mask. */
+#define TIM1_ETR_ETPS    ((uint8_t)0x30) /*!< External Trigger Prescaler mask. */
+#define TIM1_ETR_ETF     ((uint8_t)0x0F) /*!< External Trigger Filter mask. */
+/* DER*/
+#define TIM1_DER_COMDE   ((uint8_t)0x20) /*!< Commutation DMA request Enable  mask.*/
+#define TIM1_DER_CC4DE   ((uint8_t)0x10) /*!< Capture/Compare 4 DMA request Enable  mask.*/
+#define TIM1_DER_CC3DE   ((uint8_t)0x08) /*!< Capture/Compare 3 DMA request Enable  mask.*/
+#define TIM1_DER_CC2DE   ((uint8_t)0x04) /*!< Capture/Compare 2 DMA request Enable  mask.*/
+#define TIM1_DER_CC1DE   ((uint8_t)0x02) /*!< Capture/Compare 1 DMA request Enable  mask.*/
+#define TIM1_DER_UDE     ((uint8_t)0x01) /*!< Update DMA request Enable  mask. */
+/* IER*/
+#define TIM1_IER_BIE     ((uint8_t)0x80) /*!< Break Interrupt Enable mask. */
+#define TIM1_IER_TIE     ((uint8_t)0x40) /*!< Trigger Interrupt Enable mask. */
+#define TIM1_IER_COMIE   ((uint8_t)0x20) /*!< Commutation Interrupt Enable mask.*/
+#define TIM1_IER_CC4IE   ((uint8_t)0x10) /*!< Capture/Compare 4 Interrupt Enable mask. */
+#define TIM1_IER_CC3IE   ((uint8_t)0x08) /*!< Capture/Compare 3 Interrupt Enable mask. */
+#define TIM1_IER_CC2IE   ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Enable mask. */
+#define TIM1_IER_CC1IE   ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Enable mask. */
+#define TIM1_IER_UIE     ((uint8_t)0x01) /*!< Update Interrupt Enable mask. */
+/* SR1*/
+#define TIM1_SR1_BIF     ((uint8_t)0x80) /*!< Break Interrupt Flag mask. */
+#define TIM1_SR1_TIF     ((uint8_t)0x40) /*!< Trigger Interrupt Flag mask. */
+#define TIM1_SR1_COMIF   ((uint8_t)0x20) /*!< Commutation Interrupt Flag mask. */
+#define TIM1_SR1_CC4IF   ((uint8_t)0x10) /*!< Capture/Compare 4 Interrupt Flag mask. */
+#define TIM1_SR1_CC3IF   ((uint8_t)0x08) /*!< Capture/Compare 3 Interrupt Flag mask. */
+#define TIM1_SR1_CC2IF   ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Flag mask. */
+#define TIM1_SR1_CC1IF   ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Flag mask. */
+#define TIM1_SR1_UIF     ((uint8_t)0x01) /*!< Update Interrupt Flag mask. */
+/* SR2*/
+#define TIM1_SR2_CC4OF   ((uint8_t)0x10) /*!< Capture/Compare 4 Overcapture Flag mask. */
+#define TIM1_SR2_CC3OF   ((uint8_t)0x08) /*!< Capture/Compare 3 Overcapture Flag mask. */
+#define TIM1_SR2_CC2OF   ((uint8_t)0x04) /*!< Capture/Compare 2 Overcapture Flag mask. */
+#define TIM1_SR2_CC1OF   ((uint8_t)0x02) /*!< Capture/Compare 1 Overcapture Flag mask. */
+/*EGR*/
+#define TIM1_EGR_BG      ((uint8_t)0x80) /*!< Break Generation mask. */
+#define TIM1_EGR_TG      ((uint8_t)0x40) /*!< Trigger Generation mask. */
+#define TIM1_EGR_COMG    ((uint8_t)0x20) /*!< Capture/Compare Control Update Generation mask. */
+#define TIM1_EGR_CC4G    ((uint8_t)0x10) /*!< Capture/Compare 4 Generation mask. */
+#define TIM1_EGR_CC3G    ((uint8_t)0x08) /*!< Capture/Compare 3 Generation mask. */
+#define TIM1_EGR_CC2G    ((uint8_t)0x04) /*!< Capture/Compare 2 Generation mask. */
+#define TIM1_EGR_CC1G    ((uint8_t)0x02) /*!< Capture/Compare 1 Generation mask. */
+#define TIM1_EGR_UG      ((uint8_t)0x01) /*!< Update Generation mask. */
+/*CCMR*/
+#define TIM1_CCMR_ICxPSC ((uint8_t)0x0C) /*!< Input Capture x Prescaler mask. */
+#define TIM1_CCMR_ICxF   ((uint8_t)0xF0) /*!< Input Capture x Filter mask. */
+#define TIM1_CCMR_OCM    ((uint8_t)0x70) /*!< Output Compare x Mode mask. */
+#define TIM1_CCMR_OCxPE  ((uint8_t)0x08) /*!< Output Compare x Preload Enable mask. */
+#define TIM1_CCMR_OCxFE  ((uint8_t)0x04) /*!< Output Compare x Fast Enable mask. */
+#define TIM1_CCMR_CCxS   ((uint8_t)0x03) /*!< Capture/Compare x Selection mask. */
+#define TIM1_CCMR_OCxCE  ((uint8_t)0x80) /*!< Output Compare x Clear Enable mask. */
+
+#define CCMR_TIxDirect_Set ((uint8_t)0x01)
+/*CCER1*/
+#define TIM1_CCER1_CC2NP ((uint8_t)0x80) /*!< Capture/Compare 2 Complementary output Polarity mask. */
+#define TIM1_CCER1_CC2NE ((uint8_t)0x40) /*!< Capture/Compare 2 Complementary output enable mask. */
+#define TIM1_CCER1_CC2P  ((uint8_t)0x20) /*!< Capture/Compare 2 output Polarity mask. */
+#define TIM1_CCER1_CC2E  ((uint8_t)0x10) /*!< Capture/Compare 2 output enable mask. */
+#define TIM1_CCER1_CC1NP ((uint8_t)0x08) /*!< Capture/Compare 1 Complementary output Polarity mask. */
+#define TIM1_CCER1_CC1NE ((uint8_t)0x04) /*!< Capture/Compare 1 Complementary output enable mask. */
+#define TIM1_CCER1_CC1P  ((uint8_t)0x02) /*!< Capture/Compare 1 output Polarity mask. */
+#define TIM1_CCER1_CC1E  ((uint8_t)0x01) /*!< Capture/Compare 1 output enable mask. */
+/*CCER2*/
+#define TIM1_CCER2_CC4P  ((uint8_t)0x20) /*!< Capture/Compare 4 Polarity mask. */
+#define TIM1_CCER2_CC4E  ((uint8_t)0x10) /*!< Capture/Compare 4 Enable mask. */
+#define TIM1_CCER2_CC3NP ((uint8_t)0x08) /*!< Capture/Compare 3 Complementary output Polarity mask. */
+#define TIM1_CCER2_CC3NE ((uint8_t)0x04) /*!< Capture/Compare 3 Complementary output enable mask. */
+#define TIM1_CCER2_CC3P  ((uint8_t)0x02) /*!< Capture/Compare 3 output Polarity mask. */
+#define TIM1_CCER2_CC3E  ((uint8_t)0x01) /*!< Capture/Compare 3 output enable mask. */
+/*CNTR*/
+#define TIM1_CNTRH_CNT   ((uint8_t)0xFF) /*!< Counter Value (MSB) mask. */
+#define TIM1_CNTRL_CNT   ((uint8_t)0xFF) /*!< Counter Value (LSB) mask. */
+/*PSCR*/
+#define TIM1_PSCH_PSC    ((uint8_t)0xFF) /*!< Prescaler Value (MSB) mask. */
+#define TIM1_PSCL_PSC    ((uint8_t)0xFF) /*!< Prescaler Value (LSB) mask. */
+/*ARR*/
+#define TIM1_ARRH_ARR    ((uint8_t)0xFF) /*!< Autoreload Value (MSB) mask. */
+#define TIM1_ARRL_ARR    ((uint8_t)0xFF) /*!< Autoreload Value (LSB) mask. */
+/*RCR*/
+#define TIM1_RCR_REP     ((uint8_t)0xFF) /*!< Repetition Counter Value mask. */
+/*CCR1*/
+#define TIM1_CCR1H_CCR1  ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (MSB) mask. */
+#define TIM1_CCR1L_CCR1  ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (LSB) mask. */
+/*CCR2*/
+#define TIM1_CCR2H_CCR2  ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (MSB) mask. */
+#define TIM1_CCR2L_CCR2  ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (LSB) mask. */
+/*CCR3*/
+#define TIM1_CCR3H_CCR3  ((uint8_t)0xFF) /*!< Capture/Compare 3 Value (MSB) mask. */
+#define TIM1_CCR3L_CCR3  ((uint8_t)0xFF) /*!< Capture/Compare 3 Value (LSB) mask. */
+/*CCR4*/
+#define TIM1_CCR4H_CCR4  ((uint8_t)0xFF) /*!< Capture/Compare 4 Value (MSB) mask. */
+#define TIM1_CCR4L_CCR4  ((uint8_t)0xFF) /*!< Capture/Compare 4 Value (LSB) mask. */
+/*BKR*/
+#define TIM1_BKR_MOE     ((uint8_t)0x80) /*!< Main Output Enable mask. */
+#define TIM1_BKR_AOE     ((uint8_t)0x40) /*!< Automatic Output Enable mask. */
+#define TIM1_BKR_BKP     ((uint8_t)0x20) /*!< Break Polarity mask. */
+#define TIM1_BKR_BKE     ((uint8_t)0x10) /*!< Break Enable mask. */
+#define TIM1_BKR_OSSR    ((uint8_t)0x08) /*!< Off-State Selection for Run mode mask. */
+#define TIM1_BKR_OSSI    ((uint8_t)0x04) /*!< Off-State Selection for Idle mode mask. */
+#define TIM1_BKR_LOCK    ((uint8_t)0x03) /*!< Lock Configuration mask. */
+/*DTR*/
+#define TIM1_DTR_DTG     ((uint8_t)0xFF) /*!< Dead-Time Generator set-up mask. */
+/*OISR*/
+#define TIM1_OISR_OIS3N  ((uint8_t)0x20) /*!< Output Idle state 3 (OC3N output) mask. */
+#define TIM1_OISR_OIS3   ((uint8_t)0x10) /*!< Output Idle state 3 (OC3 output) mask. */
+#define TIM1_OISR_OIS2N  ((uint8_t)0x08) /*!< Output Idle state 2 (OC2N output) mask. */
+#define TIM1_OISR_OIS2   ((uint8_t)0x04) /*!< Output Idle state 2 (OC2 output) mask. */
+#define TIM1_OISR_OIS1N  ((uint8_t)0x02) /*!< Output Idle state 1 (OC1N output) mask. */
+#define TIM1_OISR_OIS1   ((uint8_t)0x01) /*!< Output Idle state 1 (OC1 output) mask. */
+
+/*DCR1*/
+#define TIM1_DCR1_DBA    ((uint8_t)0x1F)    /*!< DMA Base Address mask. */
+
+/*DCR2*/
+#define TIM1_DCR2_DBL    ((uint8_t)0x1F)    /*!< DMA Burst Length mask. */
+
+/*DMAR*/
+#define TIM1_DMAR_VR     ((uint8_t)0xFF)    /*!< Virtual register mask. */
+
+
+/**
+  * @}
+  */
+/*----------------------------------------------------------------------------*/
+
+/**
+  * @brief 16 bit timer :TIM2, TIM3 & TIM5
+  */
+typedef struct TIM_struct
+{
+  __IO uint8_t CR1;    /*!< control register 1   */
+  __IO uint8_t CR2;    /*!< control register 2   */
+  __IO uint8_t SMCR;   /*!< Synchro mode control register */
+  __IO uint8_t ETR;    /*!< external trigger register */
+  __IO uint8_t DER;    /*!< DMA requests enable register */
+  __IO uint8_t IER;    /*!< interrupt enable register*/
+  __IO uint8_t SR1;    /*!< status register 1   */
+  __IO uint8_t SR2;    /*!< status register 2   */
+  __IO uint8_t EGR;    /*!< event generation register */
+  __IO uint8_t CCMR1;  /*!< CC mode register 1      */
+  __IO uint8_t CCMR2;  /*!< CC mode register 2      */
+  __IO uint8_t CCER1;  /*!< CC enable register 1     */
+  __IO uint8_t CNTRH;  /*!< counterregister  high  */
+  __IO uint8_t CNTRL;  /*!< counterregister  low   */
+  __IO uint8_t PSCR;   /*!< prescaler  register   */
+  __IO uint8_t ARRH;   /*!< auto-reload register high  */
+  __IO uint8_t ARRL;   /*!< auto-reload register low    */
+  __IO uint8_t CCR1H;  /*!< capture/compare register 1 high   */
+  __IO uint8_t CCR1L;  /*!< capture/compare register 1 low     */
+  __IO uint8_t CCR2H;  /*!< capture/compare register 2 high   */
+  __IO uint8_t CCR2L;  /*!< capture/compare register 2 low     */
+  __IO uint8_t BKR;    /*!< Break Register */
+  __IO uint8_t OISR;   /*!< Output idle register */
+}
+TIM_TypeDef;
+
+/** @addtogroup TIM2_TIM3_Registers_Reset_Value
+  * @{
+  */
+#define TIM_CR1_RESET_VALUE    ((uint8_t)0x00)
+#define TIM_CR2_RESET_VALUE    ((uint8_t)0x00)
+#define TIM_SMCR_RESET_VALUE   ((uint8_t)0x00)
+#define TIM_ETR_RESET_VALUE    ((uint8_t)0x00)
+#define TIM_DER_RESET_VALUE    ((uint8_t)0x00)
+#define TIM_IER_RESET_VALUE    ((uint8_t)0x00)
+#define TIM_SR1_RESET_VALUE    ((uint8_t)0x00)
+#define TIM_SR2_RESET_VALUE    ((uint8_t)0x00)
+#define TIM_EGR_RESET_VALUE    ((uint8_t)0x00)
+#define TIM_CCMR1_RESET_VALUE  ((uint8_t)0x00)
+#define TIM_CCMR2_RESET_VALUE  ((uint8_t)0x00)
+
+#define TIM_CCER1_RESET_VALUE  ((uint8_t)0x00)
+
+#define TIM_CNTRH_RESET_VALUE  ((uint8_t)0x00)
+#define TIM_CNTRL_RESET_VALUE  ((uint8_t)0x00)
+
+#define TIM_PSCR_RESET_VALUE   ((uint8_t)0x00)
+#define TIM_ARRH_RESET_VALUE   ((uint8_t)0xFF)
+#define TIM_ARRL_RESET_VALUE   ((uint8_t)0xFF)
+
+#define TIM_CCR1H_RESET_VALUE  ((uint8_t)0x00)
+#define TIM_CCR1L_RESET_VALUE  ((uint8_t)0x00)
+#define TIM_CCR2H_RESET_VALUE  ((uint8_t)0x00)
+#define TIM_CCR2L_RESET_VALUE  ((uint8_t)0x00)
+
+#define TIM_BKR_RESET_VALUE    ((uint8_t)0x00)
+#define TIM_OISR_RESET_VALUE   ((uint8_t)0x00)
+
+/**
+  * @}
+  */
+
+/** @addtogroup TIM2_TIM3_TIM5_Registers_Bits_Definition
+  * @{
+  */
+/* CR1*/
+#define TIM_CR1_ARPE     ((uint8_t)0x80) /*!< Auto-Reload Preload Enable Mask. */
+#define TIM_CR1_CMS      ((uint8_t)0x60) /*!< Center-aligned Mode Selection Mask. */
+#define TIM_CR1_DIR      ((uint8_t)0x10) /*!< Direction Mask. */
+#define TIM_CR1_OPM      ((uint8_t)0x08) /*!< One Pulse Mode Mask. */
+#define TIM_CR1_URS      ((uint8_t)0x04) /*!< Update Request Source Mask. */
+#define TIM_CR1_UDIS     ((uint8_t)0x02) /*!< Update DIsable Mask. */
+#define TIM_CR1_CEN      ((uint8_t)0x01) /*!< Counter Enable Mask. */
+
+/* CR2*/
+#define TIM_CR2_TI1S     ((uint8_t)0x80) /*!< TI1 selection  */
+#define TIM_CR2_MMS      ((uint8_t)0x70) /*!< MMS Selection Mask. */
+#define TIM_CR2_CCDS     ((uint8_t)0x08) /*!< Capture/Compare DMA Selection */
+
+
+/* SMCR*/
+#define TIM_SMCR_MSM     ((uint8_t)0x80) /*!< Master/Slave Mode Mask. */
+#define TIM_SMCR_TS      ((uint8_t)0x70) /*!< Trigger Selection Mask. */
+#define TIM_SMCR_SMS     ((uint8_t)0x07) /*!< Slave Mode Selection Mask. */
+
+
+/* ETR*/
+#define TIM_ETR_ETP      ((uint8_t)0x80) /*!< External Trigger Polarity Mask. */
+#define TIM_ETR_ECE      ((uint8_t)0x40)/*!< External Clock Mask. */
+#define TIM_ETR_ETPS     ((uint8_t)0x30) /*!< External Trigger Prescaler Mask. */
+#define TIM_ETR_ETF      ((uint8_t)0x0F) /*!< External Trigger Filter Mask. */
+
+/* DER*/
+#define TIM_DER_CC2DE    ((uint8_t)0x04) /*!< Capture/Compare 2 DMA request Enable mask.*/
+#define TIM_DER_CC1DE    ((uint8_t)0x02) /*!< Capture/Compare 1 DMA request Enable mask.*/
+#define TIM_DER_UDE      ((uint8_t)0x01) /*!< Update DMA request Enable  mask. */
+
+/* IER*/
+#define TIM_IER_BIE      ((uint8_t)0x80) /*!< Break Interrupt Enable Mask. */
+#define TIM_IER_TIE      ((uint8_t)0x40) /*!< Trigger Interrupt Enable Mask. */
+#define TIM_IER_CC2IE    ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Enable Mask. */
+#define TIM_IER_CC1IE    ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Enable Mask. */
+#define TIM_IER_UIE      ((uint8_t)0x01) /*!< Update Interrupt Enable Mask. */
+
+/* SR1*/
+#define TIM_SR1_BIF      ((uint8_t)0x80) /*!< Break Interrupt Flag Mask. */
+#define TIM_SR1_TIF      ((uint8_t)0x40) /*!< Trigger Interrupt Flag Mask. */
+#define TIM_SR1_CC2IF    ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Flag Mask. */
+#define TIM_SR1_CC1IF    ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Flag Mask. */
+#define TIM_SR1_UIF      ((uint8_t)0x01) /*!< Update Interrupt Flag Mask. */
+
+/* SR2*/
+#define TIM_SR2_CC2OF    ((uint8_t)0x04) /*!< Capture/Compare 2 Overcapture Flag Mask. */
+#define TIM_SR2_CC1OF    ((uint8_t)0x02) /*!< Capture/Compare 1 Overcapture Flag Mask. */
+
+/*EGR*/
+#define TIM_EGR_BG       ((uint8_t)0x80) /*!< Break Generation Mask. */
+#define TIM_EGR_TG       ((uint8_t)0x40) /*!< Trigger Generation Mask. */
+#define TIM_EGR_CC2G     ((uint8_t)0x04) /*!< Capture/Compare 2 Generation Mask. */
+#define TIM_EGR_CC1G     ((uint8_t)0x02) /*!< Capture/Compare 1 Generation Mask. */
+#define TIM_EGR_UG       ((uint8_t)0x01) /*!< Update Generation Mask. */
+
+/*CCMR*/
+#define TIM_CCMR_ICxF    ((uint8_t)0xF0) /*!< Input Capture x Filter Mask. */
+#define TIM_CCMR_ICxPSC  ((uint8_t)0x0C) /*!< Input Capture x Prescaler Mask. */
+#define TIM_CCMR_CCxS    ((uint8_t)0x03) /*!< Capture/Compare x Selection Mask. */
+#define TIM_CCMR_OCM     ((uint8_t)0x70) /*!< Output Compare x Mode Mask. */
+#define TIM_CCMR_OCxPE   ((uint8_t)0x08) /*!< Output Compare x Preload Enable Mask. */
+#define TIM_CCMR_OCxFE   ((uint8_t)0x04) /*!< Output Compare x Fast Enable Mask. */
+
+#define TIM_CCMR_TIxDirect_Set   ((uint8_t)0x01)
+
+/*CCER1*/
+#define TIM_CCER1_CC2P   ((uint8_t)0x20) /*!< Capture/Compare 2 output Polarity Mask. */
+#define TIM_CCER1_CC2E   ((uint8_t)0x10) /*!< Capture/Compare 2 output enable Mask. */
+#define TIM_CCER1_CC1P   ((uint8_t)0x02) /*!< Capture/Compare 1 output Polarity Mask. */
+#define TIM_CCER1_CC1E   ((uint8_t)0x01) /*!< Capture/Compare 1 output enable Mask. */
+
+/*CNTR*/
+#define TIM_CNTRH_CNT    ((uint8_t)0xFF) /*!< Counter Value (MSB) Mask. */
+#define TIM_CNTRL_CNT    ((uint8_t)0xFF) /*!< Counter Value (LSB) Mask. */
+
+/*PSCR*/
+#define TIM_PSCR_PSC     ((uint8_t)0x07) /*!< Prescaler Value  Mask. */
+
+/*ARR*/
+#define TIM_ARRH_ARR     ((uint8_t)0xFF) /*!< Autoreload Value (MSB) Mask. */
+#define TIM_ARRL_ARR     ((uint8_t)0xFF) /*!< Autoreload Value (LSB) Mask. */
+
+
+/*CCR1*/
+#define TIM_CCR1H_CCR1   ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (MSB) Mask. */
+#define TIM_CCR1L_CCR1   ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (LSB) Mask. */
+
+/*CCR2*/
+#define TIM_CCR2H_CCR2   ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (MSB) Mask. */
+#define TIM_CCR2L_CCR2   ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (LSB) Mask. */
+
+
+/*BKR*/
+#define TIM_BKR_MOE      ((uint8_t)0x80) /*!< Main Output Enable Mask. */
+#define TIM_BKR_AOE      ((uint8_t)0x40) /*!< Automatic Output Enable Mask. */
+#define TIM_BKR_BKP      ((uint8_t)0x20) /*!< Break Polarity Mask. */
+#define TIM_BKR_BKE      ((uint8_t)0x10) /*!< Break Enable Mask. */
+#define TIM_BKR_OSSI     ((uint8_t)0x04) /*!< Off-State Selection for Idle mode Mask. */
+#define TIM_BKR_LOCK     ((uint8_t)0x03) /*!<Lock Configuration Mask. */
+
+/*OISR*/
+#define TIM_OISR_OIS2    ((uint8_t)0x04) /*!< Output Idle state 2 (OC2 output) Mask. */
+#define TIM_OISR_OIS1    ((uint8_t)0x01) /*!< Output Idle state 1 (OC1 output) Mask. */
+/**
+  * @}
+  */
+
+
+/*----------------------------------------------------------------------------*/
+
+/**
+  * @brief 8-bit system or Low End Small Timer (TIM4)
+  */
+typedef struct TIM4_struct
+{
+  __IO uint8_t CR1;   /*!< control register 1 */
+  __IO uint8_t CR2;   /*!< control register 2 */
+  __IO uint8_t SMCR;  /*!< Synchro mode control register */
+  __IO uint8_t DER;   /*!< DMA requests enable register */
+  __IO uint8_t IER;   /*!< interrupt enable register  */
+  __IO uint8_t SR1;   /*!< status register 1    */
+  __IO uint8_t EGR;   /*!< event generation register */
+  __IO uint8_t CNTR;  /*!< counter register  */
+  __IO uint8_t PSCR;  /*!< prescaler register */
+  __IO uint8_t ARR;   /*!< auto-reload register */
+}
+TIM4_TypeDef;
+/** @addtogroup TIM4_Registers_Reset_Value
+  * @{
+  */
+#define TIM4_CR1_RESET_VALUE    ((uint8_t)0x00)
+#define TIM4_CR2_RESET_VALUE    ((uint8_t)0x00)
+#define TIM4_SMCR_RESET_VALUE   ((uint8_t)0x00)
+#define TIM4_DER_RESET_VALUE    ((uint8_t)0x00)
+#define TIM4_IER_RESET_VALUE    ((uint8_t)0x00)
+#define TIM4_SR1_RESET_VALUE    ((uint8_t)0x00)
+#define TIM4_EGR_RESET_VALUE    ((uint8_t)0x00)
+#define TIM4_CNTR_RESET_VALUE   ((uint8_t)0x00)
+#define TIM4_PSCR_RESET_VALUE   ((uint8_t)0x00)
+#define TIM4_ARR_RESET_VALUE    ((uint8_t)0xFF)
+
+/**
+* @}
+*/
+
+/** @addtogroup TIM4_Registers_Bits_Definition
+  * @{
+  */
+/* CR1*/
+#define TIM4_CR1_ARPE    ((uint8_t)0x80) /*!< Auto-Reload Preload Enable Mask. */
+#define TIM4_CR1_OPM     ((uint8_t)0x08) /*!< One Pulse Mode Mask. */
+#define TIM4_CR1_URS     ((uint8_t)0x04) /*!< Update Request Source Mask. */
+#define TIM4_CR1_UDIS    ((uint8_t)0x02) /*!< Update DIsable Mask. */
+#define TIM4_CR1_CEN     ((uint8_t)0x01) /*!< Counter Enable Mask. */
+
+/* CR2*/
+#define TIM4_CR2_MMS     ((uint8_t)0x70) /*!< MMS Selection Mask. */
+
+/* SMCR*/
+#define TIM4_SMCR_MSM    ((uint8_t)0x80) /*!< Master/Slave Mode Mask. */
+#define TIM4_SMCR_TS     ((uint8_t)0x70) /*!< Trigger Selection Mask. */
+#define TIM4_SMCR_SMS    ((uint8_t)0x07) /*!< Slave Mode Selection Mask. */
+
+/* DER*/
+#define TIM4_DER_UDE     ((uint8_t)0x01) /*!< Update DMA request Enable  mask. */
+
+/* IER*/
+#define TIM4_IER_TIE     ((uint8_t)0x40) /*!< Trigger Interrupt Enable Mask. */
+#define TIM4_IER_UIE     ((uint8_t)0x01) /*!< Update Interrupt Enable Mask. */
+
+/* SR1*/
+#define TIM4_SR1_UIF     ((uint8_t)0x01) /*!< Update Interrupt Flag Mask. */
+#define TIM4_SR1_TIF     ((uint8_t)0x40) /*!< Trigger Interrupt Flag Mask. */
+
+/* EGR*/
+#define TIM4_EGR_UG      ((uint8_t)0x01) /*!< Update Generation Mask. */
+#define TIM4_EGR_TG      ((uint8_t)0x40) /*!< Trigger Generation Mask. */
+
+/* CNTR*/
+#define TIM4_CNTR_CNT    ((uint8_t)0xFF) /*!<Counter Value (LSB) Mask. */
+
+/* PSCR*/
+#define TIM4_PSCR_PSC    ((uint8_t)0x0F) /*!<Prescaler Value  Mask. */
+
+/* ARR*/
+#define TIM4_ARR_ARR     ((uint8_t)0xFF) /*!<Autoreload Value Mask. */
+/**
+  * @}
+  */
+
+/*----------------------------------------------------------------------------*/
+
+/**
+  * @brief USART
+  */
+typedef struct USART_struct
+{
+  __IO uint8_t SR;   /*!<  USART status register  */
+  __IO uint8_t DR;   /*!<  USART data register     */
+  __IO uint8_t BRR1; /*!<  USART baud rate register   */
+  __IO uint8_t BRR2; /*!<  USART DIV mantissa[11:8] SCIDIV fraction */
+  __IO uint8_t CR1;  /*!<  USART control register 1     */
+  __IO uint8_t CR2;  /*!<  USART control register 2     */
+  __IO uint8_t CR3;  /*!<  USART control register 3      */
+  __IO uint8_t CR4;  /*!< USART control register 4      */
+  __IO uint8_t CR5;  /*!<  USART control register 5       */
+  __IO uint8_t GTR;  /*!<  USART guard time register     */
+  __IO uint8_t PSCR; /*!<  USART prescaler register     */
+}
+USART_TypeDef;
+
+
+/** @addtogroup USART_Registers_Reset_Value
+  * @{
+  */
+#define USART_SR_RESET_VALUE ((uint8_t)0xC0)
+#define USART_BRR1_RESET_VALUE ((uint8_t)0x00)
+#define USART_BRR2_RESET_VALUE ((uint8_t)0x00)
+#define USART_CR1_RESET_VALUE ((uint8_t)0x00)
+#define USART_CR2_RESET_VALUE ((uint8_t)0x00)
+#define USART_CR3_RESET_VALUE ((uint8_t)0x00)
+#define USART_CR4_RESET_VALUE ((uint8_t)0x00)
+
+/**
+  * @}
+  */
+
+/** @addtogroup USART_Registers_Bits_Definition
+  * @{
+  */
+#define USART_SR_TXE       ((uint8_t)0x80) /*!< Transmit Data Register Empty mask */
+#define USART_SR_TC        ((uint8_t)0x40) /*!< Transmission Complete mask */
+#define USART_SR_RXNE      ((uint8_t)0x20) /*!< Read Data Register Not Empty mask */
+#define USART_SR_IDLE      ((uint8_t)0x10) /*!< IDLE line detected mask */
+#define USART_SR_OR        ((uint8_t)0x08) /*!< OverRun error mask */
+#define USART_SR_NF        ((uint8_t)0x04) /*!< Noise Flag mask */
+#define USART_SR_FE        ((uint8_t)0x02) /*!< Framing Error mask */
+#define USART_SR_PE        ((uint8_t)0x01) /*!< Parity Error mask */
+
+#define USART_BRR1_DIVM    ((uint8_t)0xFF) /*!< LSB mantissa of USARTDIV [7:0] mask */
+
+#define USART_BRR2_DIVM    ((uint8_t)0xF0) /*!< MSB mantissa of USARTDIV [11:8] mask */
+#define USART_BRR2_DIVF    ((uint8_t)0x0F) /*!< Fraction bits of USARTDIV [3:0] mask */
+
+#define USART_CR1_R8       ((uint8_t)0x80) /*!< Receive Data bit 8 */
+#define USART_CR1_T8       ((uint8_t)0x40) /*!< Transmit data bit 8 */
+#define USART_CR1_USARTD   ((uint8_t)0x20) /*!< USART Disable (for low power consumption) */
+#define USART_CR1_M        ((uint8_t)0x10) /*!< Word length mask */
+#define USART_CR1_WAKE     ((uint8_t)0x08) /*!< Wake-up method mask */
+#define USART_CR1_PCEN     ((uint8_t)0x04) /*!< Parity Control Enable mask */
+#define USART_CR1_PS       ((uint8_t)0x02) /*!< USART Parity Selection */
+#define USART_CR1_PIEN     ((uint8_t)0x01) /*!< USART Parity Interrupt Enable mask */
+
+#define USART_CR2_TIEN     ((uint8_t)0x80) /*!< Transmitter Interrupt Enable mask */
+#define USART_CR2_TCIEN    ((uint8_t)0x40) /*!< TransmissionComplete Interrupt Enable mask */
+#define USART_CR2_RIEN     ((uint8_t)0x20) /*!< Receiver Interrupt Enable mask */
+#define USART_CR2_ILIEN    ((uint8_t)0x10) /*!< IDLE Line Interrupt Enable mask */
+#define USART_CR2_TEN      ((uint8_t)0x08) /*!< Transmitter Enable mask */
+#define USART_CR2_REN      ((uint8_t)0x04) /*!< Receiver Enable mask */
+#define USART_CR2_RWU      ((uint8_t)0x02) /*!< Receiver Wake-Up mask */
+#define USART_CR2_SBK      ((uint8_t)0x01) /*!< Send Break mask */
+
+#define USART_CR3_STOP     ((uint8_t)0x30) /*!< STOP bits [1:0] mask */
+#define USART_CR3_CLKEN    ((uint8_t)0x08) /*!< Clock Enable mask */
+#define USART_CR3_CPOL     ((uint8_t)0x04) /*!< Clock Polarity mask */
+#define USART_CR3_CPHA     ((uint8_t)0x02) /*!< Clock Phase mask */
+#define USART_CR3_LBCL     ((uint8_t)0x01) /*!< Last Bit Clock pulse mask */
+
+#define USART_CR4_ADD      ((uint8_t)0x0F) /*!< Address of the USART node mask */
+
+#define USART_CR5_DMAT     ((uint8_t)0x80) /*!< DMA Enable transmitter mask */
+#define USART_CR5_DMAR     ((uint8_t)0x40) /*!< DMA Enable receiver mask */
+#define USART_CR5_SCEN     ((uint8_t)0x20) /*!< Smart Card Enable mask */
+#define USART_CR5_NACK     ((uint8_t)0x10) /*!< Smart Card Nack Enable mask */
+#define USART_CR5_HDSEL    ((uint8_t)0x08) /*!< Half-Duplex Selection mask */
+#define USART_CR5_IRLP     ((uint8_t)0x04) /*!< Irda Low Power Selection mask */
+#define USART_CR5_IREN     ((uint8_t)0x02) /*!< Irda Enable mask */
+#define USART_CR5_EIE      ((uint8_t)0x01) /*!< Error Interrupt mask */
+/**
+  * @}
+  */
+/*----------------------------------------------------------------------------*/
+
+/**
+  * @brief Analog to Digital Converter (ADC) peripheral
+  */
+typedef struct ADC_struct
+{
+  __IO uint8_t   CR1;      /*!< Control register 1    */
+  __IO uint8_t   CR2;      /*!< Control register 2    */
+  __IO uint8_t   CR3;      /*!<  Control register 3    */
+  __IO uint8_t   SR;       /*!< Status register    */
+  __IO uint8_t   DRH;      /*!< Data register MSB    */
+  __IO uint8_t   DRL;      /*!< Data register LSB    */
+  __IO uint8_t   HTRH;     /*!< High voltage reference register MSB    */
+  __IO uint8_t   HTRL;     /*!< High voltage reference register LSB    */
+  __IO uint8_t   LTRH;     /*!< Low voltage reference register MSB    */
+  __IO uint8_t   LTRL;     /*!< Low voltage reference register LSB    */
+  __IO uint8_t   SQR[4];   /*!< Channel select scan registers    */
+  __IO uint8_t   TRIGR[4]; /*!< Trigger disable  registers  */
+}
+ADC_TypeDef;
+
+/** @addtogroup ADC_Registers_Reset_Value
+  * @{
+  */
+#define  ADC_CR1_RESET_VALUE      ((uint8_t) 0x00)
+#define  ADC_CR2_RESET_VALUE      ((uint8_t) 0x00)
+#define  ADC_CR3_RESET_VALUE      ((uint8_t) 0x1F)
+#define  ADC_SR_RESET_VALUE       ((uint8_t) 0x00)
+#define  ADC_DRH_RESET_VALUE      ((uint8_t) 0x00)
+#define  ADC_DRL_RESET_VALUE      ((uint8_t) 0x00)
+#define  ADC_HTRH_RESET_VALUE     ((uint8_t) 0x0F)
+#define  ADC_HTRL_RESET_VALUE     ((uint8_t) 0xFF)
+#define  ADC_LTRH_RESET_VALUE     ((uint8_t) 0x00)
+#define  ADC_LTRL_RESET_VALUE     ((uint8_t) 0x00)
+#define  ADC_SQR1_RESET_VALUE     ((uint8_t) 0x00)
+#define  ADC_SQR2_RESET_VALUE     ((uint8_t) 0x00)
+#define  ADC_SQR3_RESET_VALUE     ((uint8_t) 0x00)
+#define  ADC_SQR4_RESET_VALUE     ((uint8_t) 0x00)
+#define  ADC_TRIGR1_RESET_VALUE   ((uint8_t) 0x00)
+#define  ADC_TRIGR2_RESET_VALUE   ((uint8_t) 0x00)
+#define  ADC_TRIGR3_RESET_VALUE   ((uint8_t) 0x00)
+#define  ADC_TRIGR4_RESET_VALUE   ((uint8_t) 0x00)
+
+
+/**
+* @}
+*/
+
+/** @addtogroup ADC_Registers_Bits_Definition
+  * @{
+  */
+#define  ADC_CR1_ADON           ((uint8_t)0x01)
+#define  ADC_CR1_START          ((uint8_t)0x02)
+#define  ADC_CR1_CONT           ((uint8_t)0x04)
+#define  ADC_CR1_EOCIE          ((uint8_t)0x08)
+#define  ADC_CR1_AWDIE          ((uint8_t)0x10)
+#define  ADC_CR1_RES            ((uint8_t)0x60)
+#define  ADC_CR1_OVERIE         ((uint8_t)0x80)
+
+
+#define  ADC_CR2_SMPT1          ((uint8_t)0x07)
+#define  ADC_CR2_EXTSEL         ((uint8_t)0x18)
+#define  ADC_CR2_TRIGEDGE       ((uint8_t)0x60)
+#define  ADC_CR2_PRESC          ((uint8_t)0x80)
+
+#define  ADC_CR3_CHSEL          ((uint8_t)0x1F)
+#define  ADC_CR3_SMPT2          ((uint8_t)0xE0)
+
+#define  ADC_SR_EOC             ((uint8_t)0x01)
+#define  ADC_SR_AWD             ((uint8_t)0x02)
+#define  ADC_SR_OVER            ((uint8_t)0x04)
+
+#define  ADC_DRH_CONVDATA       ((uint8_t)0x0F)
+#define  ADC_DRL_CONVDATA       ((uint8_t)0xFF)
+
+#define  ADC_HTRH_HT            ((uint8_t)0x0F)
+#define  ADC_HTRL_HT            ((uint8_t)0xFF)
+
+#define  ADC_LTRH_LT            ((uint8_t)0x0F)
+#define  ADC_LTRL_LT            ((uint8_t)0xFF)
+
+#define  ADC_SQR1_CHSELS        ((uint8_t)0x3F)
+#define  ADC_SQR1_DMAOFF        ((uint8_t)0x80)
+#define  ADC_SQR2_CHSELS        ((uint8_t)0xFF)
+#define  ADC_SQR3_CHSELS        ((uint8_t)0xFF)
+#define  ADC_SQR4_CHSELS        ((uint8_t)0xFF)
+
+#define  ADC_TRIGR1_TRIG        ((uint8_t)0x0F)
+#define  ADC_TRIGR1_VREFINTON   ((uint8_t)0x10)
+#define  ADC_TRIGR1_TSON        ((uint8_t)0x20)
+
+#define  ADC_TRIGR2_TRIG        ((uint8_t)0xFF)
+#define  ADC_TRIGR3_TRIG        ((uint8_t)0xFF)
+#define  ADC_TRIGR4_TRIG        ((uint8_t)0xFF)
+
+/**
+  * @}
+  */
+/*----------------------------------------------------------------------------*/
+/*----------------------------------------------------------------------------*/
+
+/**
+ * @brief Digital to Analog Converter (DAC) peripheral
+  */
+typedef struct DAC_struct
+{
+  __IO uint8_t  CH1CR1;   /*!< DAC control register 1  */
+  __IO uint8_t  CH1CR2;   /*!< DAC control register 2  */
+  __IO uint8_t  CH2CR1;   /*!< DAC channel 2 control register 1  */
+  __IO uint8_t  CH2CR2;   /*!< DAC channel 2 control register 2  */
+  __IO uint8_t  SWTRIGR; /*!< DAC software trigger register */
+  __IO uint8_t  SR;      /*!< DAC status register */
+
+  /*Channel 1 registers*/
+  __IO uint8_t  RESERVED0[2];
+  __IO uint8_t  CH1RDHRH; /*!< DAC Channel 1 right aligned data holding register MSB */
+  __IO uint8_t  CH1RDHRL; /*!< DAC Channel 1 right aligned data holding register LSB */
+  __IO uint8_t  RESERVED1[2];
+  __IO uint8_t  CH1LDHRH; /*!< DAC Channel 1 left aligned data holding register MSB */
+  __IO uint8_t  CH1LDHRL; /*!< DAC Channel 1 left aligned data holding register LSB */
+  __IO uint8_t  RESERVED2[2];
+  __IO uint8_t  CH1DHR8; /*!< DAC Channel 1 8-bit data holding register */
+
+  /*Channel 2 registers*/
+  __IO uint8_t  RESERVED3[3];
+  __IO uint8_t  CH2RDHRH; /*!< DAC Channel 2 right aligned data holding register MSB */
+  __IO uint8_t  CH2RDHRL; /*!< DAC Channel 2 right aligned data holding register LSB */
+  __IO uint8_t  RESERVED4[2];
+  __IO uint8_t  CH2LDHRH; /*!< DAC Channel 2 left aligned data holding register MSB */
+  __IO uint8_t  CH2LDHRL; /*!< DAC Channel 2 left aligned data holding register LSB */
+  __IO uint8_t  RESERVED5[2];
+  __IO uint8_t  CH2DHR8; /*!< DAC Channel 2 8-bit data holding register */
+
+
+  /* Dual mode registers */
+  __IO uint8_t  RESERVED6[3];
+  __IO uint8_t  DCH1RDHRH; /*!< DAC Dual mode Channel 1 right aligned data holding register MSB */
+  __IO uint8_t  DCH1RDHRL; /*!< DAC Dual mode Channel 1 right aligned data holding register LSB */
+  __IO uint8_t  DCH2RDHRH; /*!< DAC Dual mode Channel 2 right aligned data holding register MSB */
+  __IO uint8_t  DCH2RDHRL; /*!< DAC Dual mode Channel 2 right aligned data holding register LSB */
+  __IO uint8_t  DCH1LDHRH; /*!< DAC Dual mode Channel 1 left aligned data holding register MSB */
+  __IO uint8_t  DCH1LDHRL; /*!< DAC Dual mode Channel 1 left aligned data holding register LSB */
+  __IO uint8_t  DCH2LDHRH; /*!< DAC Dual mode Channel 2 left aligned data holding register MSB */
+  __IO uint8_t  DCH2LDHRL; /*!< DAC Dual mode Channel 2 left aligned data holding register LSB */
+  __IO uint8_t  DCH1DHR8; /*!< DAC Dual mode Channel 1 8-bit data holding register */
+  __IO uint8_t  DCH2DHR8; /*!< DAC Dual mode Channel 2 8-bit data holding register */
+
+  /* DOR registers*/
+  __IO uint8_t  RESERVED7[2];
+  __IO uint8_t  CH1DORH; /*!< DAC Channel 1 data output register MSB */
+  __IO uint8_t  CH1DORL; /*!< DAC Channel 1 data output register LSB */
+  __IO uint8_t  RESERVED8[2];
+  __IO uint8_t  CH2DORH; /*!< DAC Channel 2 data output register MSB */
+  __IO uint8_t  CH2DORL; /*!< DAC Channel 2 data output register LSB */
+}
+DAC_TypeDef;
+
+/** @addtogroup DAC_Registers_Reset_Value
+  * @{
+  */
+#define DAC_CR1_RESET_VALUE       ((uint8_t)0x00)
+#define DAC_CR2_RESET_VALUE       ((uint8_t)0x00)
+#define DAC_SWTRIGR_RESET_VALUE   ((uint8_t)0x00)
+#define DAC_SR_RESET_VALUE        ((uint8_t)0x00)
+#define DAC_RDHRH_RESET_VALUE     ((uint8_t)0x00)
+#define DAC_RDHRL_RESET_VALUE     ((uint8_t)0x00)
+#define DAC_LDHRH_RESET_VALUE     ((uint8_t)0x00)
+#define DAC_LDHRL_RESET_VALUE     ((uint8_t)0x00)
+#define DAC_DHR8_RESET_VALUE      ((uint8_t)0x00)
+#define DAC_DORH_RESET_VALUE      ((uint8_t)0x00)
+#define DAC_DORL_RESET_VALUE      ((uint8_t)0x00)
+/**
+  * @}
+  */
+
+/** @addtogroup DAC_Registers_Bits_Definition
+  * @{
+  */
+
+/* CR1*/
+#define DAC_CR1_TSEL          ((uint8_t)0x38) /*!<  DAC channel trigger selection. */
+#define DAC_CR1_TEN           ((uint8_t)0x04) /*!<  DAC channel trigger enable. */
+#define DAC_CR1_BOFF          ((uint8_t)0x02) /*!<  DAC channel output buffer disable. */
+#define DAC_CR1_EN            ((uint8_t)0x01) /*!<  DAC channel enable. */
+#define DAC_CR1_WAVEN         ((uint8_t)0xC0) /*!<  DAC channel wave generation enable. */
+
+/* CR2*/
+#define DAC_CR2_DMAUDRIE      ((uint8_t)0x20) /*!<  DAC channel DMA underrun interrupt enable. */
+#define DAC_CR2_DMAEN         ((uint8_t)0x10) /*!<  DAC DMA enable. */
+#define DAC_CR2_MAMPx         ((uint8_t)0x0F) /*!<  DAC Dchannel wave generation config. */
+
+/* SWTRIGR*/
+#define DAC_SWTRIGR_SWTRIG1   ((uint8_t)0x01) /*!<  DAC channel 1 software trigger. */
+#define DAC_SWTRIGR_SWTRIG2   ((uint8_t)0x02) /*!<  DAC channel 2 software trigger. */
+
+/* SR*/
+#define DAC_SR_DMAUDR1        ((uint8_t)0x01) /*!<  DAC channel 1 DMA underrun flag. */
+#define DAC_SR_DMAUDR2        ((uint8_t)0x02) /*!<  DAC channel 2 DMA underrun flag. */
+
+/* RDHRH*/
+#define DAC_RDHRH_RDHRH       ((uint8_t)0x0F) /*!<  DAC right aligned data holding register most significant bits. */
+
+/* RDHRL*/
+#define DAC_RDHRL_RDHRL       ((uint8_t)0xFF) /*!<  DAC right aligned data holding register least significant bits. */
+
+/* LDHRL*/
+#define DAC_LDHRH_LDHRH       ((uint8_t)0xFF) /*!<  DAC left aligned data holding register most significant bits. */
+
+/* LDHRL*/
+#define DAC_LDHRL_LDHRL       ((uint8_t)0xF0) /*!<  DAC left aligned data holding register least significant bits. */
+
+/* DHR8*/
+#define DAC_DHR8_8DHR         ((uint8_t)0xFF) /*!< DAC 8bit data holding bits */
+
+/* DORH*/
+#define DAC_DORH_DORH         ((uint8_t)0x0F) /*!< DAC data output register most significant bit */
+
+/* DORL*/
+#define DAC_DORL_DORL         ((uint8_t)0xFF) /*!< DAC data output register least significant bit */
+
+/**
+  * @}
+  */
+
+/*----------------------------------------------------------------------------*/
+
+/**
+  * @brief  Direct-Memory Access (DMA)
+  */
+typedef struct DMA_struct
+{
+  __IO uint8_t  GCSR;     /*!<  Global configuration and status register  */
+  __IO uint8_t  GIR1;     /*!<  Global interrupt register 1  */
+}
+DMA_TypeDef;
+/**
+  * @}
+  */
+typedef struct DMA_Channel_struct
+{
+  __IO uint8_t  CCR;       /*!<  CHx Control register  */
+  __IO uint8_t  CSPR;      /*!<  CHx Status & Priority register  */
+  __IO uint8_t  CNBTR;     /*!<  CHx Number of Bytes to Tranfer register  */
+  __IO uint8_t  CPARH;     /*!<  Peripheral Address High register  */
+  __IO uint8_t  CPARL;     /*!<  Peripheral Address Low register  */
+  __IO uint8_t  CM0EAR;    /*!<  Memory 0 Extended Address register  (for channel3)*/
+  __IO uint8_t  CM0ARH;    /*!<  Memory 0 Address High register  */
+  __IO uint8_t  CM0ARL;    /*!<  Memory 0 Address Low register  */
+}
+DMA_Channel_TypeDef;
+/**
+  * @}
+  */
+
+/** @addtogroup DMA_Registers_Reset_Value
+  * @{
+  */
+#define DMA_GCSR_RESET_VALUE       ((uint8_t)0xFC)
+#define DMA_GIR1_RESET_VALUE       ((uint8_t)0x00)
+/**
+  * @}
+  */
+
+/** @addtogroup DMA_Channels_Registers_Reset_Value
+  * @{
+  */
+#define DMA_CCR_RESET_VALUE          ((uint8_t)0x00)
+#define DMA_CSPR_RESET_VALUE         ((uint8_t)0x00)
+#define DMA_CNBTR_RESET_VALUE        ((uint8_t)0x00)
+#define DMA_CPARH_RESET_VALUE        ((uint8_t)0x52)
+#define DMA_C3PARH_RESET_VALUE       ((uint8_t)0x40)
+#define DMA_CPARL_RESET_VALUE        ((uint8_t)0x00)
+#define DMA_C3M0EAR_RESET_VALUE      ((uint8_t)0x00)
+#define DMA_CM0ARH_RESET_VALUE       ((uint8_t)0x00)
+#define DMA_CM0ARL_RESET_VALUE       ((uint8_t)0x00)
+/** @addtogroup DMA_Registers_Bits_Definition
+  * @{
+  */
+
+/*  Bit definition for DMA_GCSR register  */
+
+#define  DMA_GCSR_GE        ((uint8_t)0x01)            /*!<Global Enable */
+#define  DMA_GCSR_GB        ((uint8_t)0x02)            /*!<Global Busy */
+#define  DMA_GCSR_TO        ((uint8_t)0xFC)            /*!<Time Out */
+
+/*  Bit definition for DMA_GIR1 register  */
+#define  DMA_GIR1_IFC0      ((uint8_t)0x01)            /*!< Interrupt Flag Channel 0 */
+#define  DMA_GIR1_IFC1      ((uint8_t)0x02)            /*!< Interrupt Flag Channel 1 */
+#define  DMA_GIR1_IFC2      ((uint8_t)0x04)            /*!< Interrupt Flag Channel 2 */
+#define  DMA_GIR1_IFC3      ((uint8_t)0x08)            /*!< Interrupt Flag Channel 3 */
+
+
+/*  Bit definition for DMA_CCR registers  */
+#define  DMA_CCR_CE         ((uint8_t)0x01)            /*!<Channel enable*/
+#define  DMA_CCR_TCIE       ((uint8_t)0x02)            /*!<Transfer complete interrupt enable */
+#define  DMA_CCR_HTIE       ((uint8_t)0x04)            /*!<Half Transfer interrupt enable */
+#define  DMA_CCR_DTD        ((uint8_t)0x08)            /*!<Data transfer direction */
+#define  DMA_CCR_ARM        ((uint8_t)0x10)            /*!<Autorelaod mode Circular buffer mode */
+#define  DMA_CCR_IDM        ((uint8_t)0x20)            /*!<Inc/Dec mode */
+#define  DMA_CCR_MEM        ((uint8_t)0x40)            /*!<Memory Transfer Enable */
+
+
+/*  Bit definition for DMA_CSPR registers  */
+#define  DMA_CSPR_TCIF      ((uint8_t)0x02)            /*!<Transaction Complete Interrupt Flag*/
+#define  DMA_CSPR_HTIF      ((uint8_t)0x04)            /*!<Half Transaction Interrupt Flag*/
+#define  DMA_CSPR_16BM      ((uint8_t)0x08)            /*!<16 bit mode*/
+#define  DMA_CSPR_PL        ((uint8_t)0x30)            /*!<Channel priority level*/
+#define  DMA_CSPR_PEND      ((uint8_t)0x40)            /*!<Channel pending*/
+#define  DMA_CSPR_BUSY      ((uint8_t)0x80)            /*!<Channel Busy */
+
+
+/*  Bit definition for DMA_CNBTR register */
+#define  DMA_CNBTR_NDT      ((uint8_t)0xFF)            /*!<Number of data to Transfer */
+
+
+/*  Bit definition for DMA_CPARH register  */
+#define  DMA_CPARH_PA       ((uint8_t)0xFF)        /*!<Peripheral MSB Address Pointer */
+/*  Bit definition for DMA_CPARL register  */
+#define  DMA_CPARL_PA       ((uint8_t)0xFF)        /*!<Peripheral LSB Address Pointer */
+
+
+/*  Bit definition for DMA_CMAR registers  */
+#define  DMA_CM0EAR_MA      ((uint8_t)0x01)        /* Memory Extended Address Pointer only for channel 3 in Memory to memory transfer*/
+#define  DMA_CM0ARH_MA      ((uint8_t)0xFF)        /*!<Memory MSB Address Pointer*/
+#define  DMA_CM0ARL_MA      ((uint8_t)0xFF)        /*!<Memory LSB Address Pointer */
+
+
+/**
+  * @}
+  */
+/*----------------------------------------------------------------------------*/
+
+/**
+  * @brief Window Watchdog (WWDG)
+  */
+typedef struct WWDG_struct
+{
+  __IO uint8_t CR; /*!< Control Register */
+  __IO uint8_t WR; /*!< Window Register */
+}
+WWDG_TypeDef;
+
+/** @addtogroup WWDG_Registers_Reset_Value
+  * @{
+  */
+
+#define WWDG_CR_RESET_VALUE ((uint8_t)0x7F)
+#define WWDG_WR_RESET_VALUE ((uint8_t)0x7F)
+
+/**
+* @}
+*/
+
+/** @addtogroup WWDG_Registers_Bits_Definition
+  * @{
+  */
+
+#define WWDG_CR_WDGA ((uint8_t)0x80) /*!< WDGA bit mask */
+#define WWDG_CR_T6   ((uint8_t)0x40) /*!< T6 bit mask */
+#define WWDG_CR_T    ((uint8_t)0x7F) /*!< T bits mask */
+
+#define WWDG_WR_MSB  ((uint8_t)0x80) /*!< MSB bit mask */
+#define WWDG_WR_W    ((uint8_t)0x7F) /*!< W bits mask */
+
+
+/**
+  * @}
+  */
+
+/*----------------------------------------------------------------------------*/
+/**
+  * @brief LCD Controller (LCD)
+  */
+typedef struct LCD_struct
+{
+  __IO uint8_t CR1;      /*!< LCD control register 1 */
+  __IO uint8_t CR2;      /*!< LCD control register 2 */
+  __IO uint8_t CR3;      /*!< LCD control register 3 */
+  __IO uint8_t FRQ;      /*!< LCD frequency register */
+  __IO uint8_t PM[6];    /*!< LCD portmask registers*/
+  uint8_t RESERVED1[2];  /*!< Reserved */
+  __IO uint8_t RAM[22];  /*!< LCD RAM registers*/
+  uint8_t RESERVED2[13]; /*!< Reserved */
+  __IO uint8_t CR4;      /*!< LCD control register 4 */
+}
+LCD_TypeDef;
+/** @addtogroup LCD_Registers_Reset_Value
+  * @{
+  */
+#define LCD_CR1_RESET_VALUE    ((uint8_t)0x00) /*!< Control Register 1 reset value */
+#define LCD_CR2_RESET_VALUE    ((uint8_t)0x00) /*!< Control Register 2 reset value */
+#define LCD_CR3_RESET_VALUE    ((uint8_t)0x00) /*!< Control Register 3 reset value */
+#define LCD_FRQ_RESET_VALUE    ((uint8_t)0x00) /*!< Register Frequency reset value */
+#define LCD_PM_RESET_VALUE     ((uint8_t)0x00) /*!< Port mask Register reset value */
+#define LCD_RAM_RESET_VALUE    ((uint8_t)0x00) /*!< RAM Register reset value       */
+#define LCD_CR4_RESET_VALUE    ((uint8_t)0x00) /*!< Control Register 4 reset value */
+
+
+/**
+* @}
+*/
+
+/** @addtogroup LCD_Registers_Bits_Definition
+  * @{
+  */
+#define LCD_CR1_BLINK    ((uint8_t)0xC0) /*!< Blink bits mask           */
+#define LCD_CR1_BLINKF   ((uint8_t)0x38) /*!< Blink frequency bits mask */
+#define LCD_CR1_DUTY     ((uint8_t)0x06) /*!< Duty bits mask            */
+#define LCD_CR1_B2       ((uint8_t)0x01) /*!< Bias selector bit mask    */
+
+
+#define LCD_CR2_PON      ((uint8_t)0xE0) /*!< Pulse on duration bits mask */
+#define LCD_CR2_HD       ((uint8_t)0x10) /*!< High drive enable bit mask  */
+#define LCD_CR2_CC       ((uint8_t)0x0E) /*!< Contrast control bits mask  */
+#define LCD_CR2_VSEL     ((uint8_t)0x01) /*!< Voltage source bit mask     */
+
+#define LCD_CR3_LCDEN    ((uint8_t)0x40) /*!< Enable bit mask           */
+#define LCD_CR3_SOFIE    ((uint8_t)0x20) /*!< Start of frame interrupt enable mask */
+#define LCD_CR3_SOF      ((uint8_t)0x10) /*!< Start of frame bit mask              */
+#define LCD_CR3_SOFC     ((uint8_t)0x08) /*!< Clear start of frame bit mask        */
+#define LCD_CR3_DEAD     ((uint8_t)0x07) /*!< DEAD time bits mask                  */
+
+#define LCD_FRQ_DIV      ((uint8_t)0x0F) /*!< Divider bits mask */
+#define LCD_FRQ_PS       ((uint8_t)0xF0) /*!< 16 bits prescaler bits mask */
+
+#define LCD_CR4_MAPCOM   ((uint8_t)0x08) /*!< Select the mapping scheme for the COM[7:4] */
+#define LCD_CR4_PAGECOM  ((uint8_t)0x04) /*!< Select the LCD RAM page sector */
+#define LCD_CR4_DUTY8    ((uint8_t)0x02) /*!< Enable the 1/8 duty */
+#define LCD_CR4_B4       ((uint8_t)0x01) /*!< Enable the 1/4 bias */
+
+
+/**
+  * @}
+  */
+
+/*----------------------------------------------------------------------------*/
+/* This peripheral is avilable in STM8L16x devices only*/
+/**
+  * @brief AES tiny (AES)
+  */
+typedef struct AES_struct
+{
+  __IO uint8_t CR;      /*!< AES control register     */
+  __IO uint8_t SR;      /*!< AES status register      */
+  __IO uint8_t DINR;    /*!< AES Data input register  */
+  __IO uint8_t DOUTR;   /*!< AES Data output register */
+}
+AES_TypeDef;
+
+/** @addtogroup AES_Registers_Reset_Value
+  * @{
+  */
+#define AES_CR_RESET_VALUE    ((uint8_t)0x00) /*!< Control Register reset value     */
+#define AES_SR_RESET_VALUE    ((uint8_t)0x00) /*!< Status Register reset value      */
+#define AES_DINR_RESET_VALUE  ((uint8_t)0x00) /*!< Data input register reset value  */
+#define AES_DOUTR_RESET_VALUE ((uint8_t)0x00) /*!< Data output register reset value */
+/**
+* @}
+*/
+
+/** @addtogroup AES_Registers_Bits_Definition
+  * @{
+  */
+#define AES_CR_DMAEN  ((uint8_t)0x80) /*!< DMA Enable bit mask */
+#define AES_CR_ERRIE  ((uint8_t)0x40) /*!< Error Interrupt Enable bit mask */
+#define AES_CR_CCIE   ((uint8_t)0x20) /*!< Computation Complete Interrupt Enable bit mask */
+#define AES_CR_ERRC   ((uint8_t)0x10) /*!< Error Clear bit mask  */
+#define AES_CR_CCFC   ((uint8_t)0x08) /*!< Computation Complete Flag Clear bit mask */
+#define AES_CR_MODE   ((uint8_t)0x06) /*!< AES Modes of Operation bits mask */
+#define AES_CR_EN     ((uint8_t)0x01) /*!< AES Enable bit mask */
+
+#define AES_SR_WRERR  ((uint8_t)0x04) /*!< Write Error Flag bit mask */
+#define AES_SR_RDERR  ((uint8_t)0x02) /*!< Read Error Flag bit mask */
+#define AES_SR_CCF    ((uint8_t)0x01) /*!< Computation Complete Flag bit mask */
+
+#define AES_DINR      ((uint8_t)0xFF) /*!< Data Input bits mask */
+#define AES_DOUTR     ((uint8_t)0xFF) /*!< Data Output bits mask */
+
+/**
+  * @}
+  */
+/******************************************************************************/
+/*                          Peripherals Base Address                          */
+/******************************************************************************/
+#define OPT_BASE                    (uint16_t)0x4800
+#define GPIOA_BASE                  (uint16_t)0x5000
+#define GPIOB_BASE                  (uint16_t)0x5005
+#define GPIOC_BASE                  (uint16_t)0x500A
+#define GPIOD_BASE                  (uint16_t)0x500F
+#define GPIOE_BASE                  (uint16_t)0x5014
+#define GPIOF_BASE                  (uint16_t)0x5019
+#define GPIOG_BASE                  (uint16_t)0x501E
+#define GPIOH_BASE                  (uint16_t)0x5023
+#define GPIOI_BASE                  (uint16_t)0x5028
+#define FLASH_BASE                  (uint16_t)0x5050
+#define DMA1_BASE                   (uint16_t)0x5070
+#define DMA1_Channel0_BASE          (uint16_t)0x5075
+#define DMA1_Channel1_BASE          (uint16_t)0x507F
+#define DMA1_Channel2_BASE          (uint16_t)0x5089
+#define DMA1_Channel3_BASE          (uint16_t)0x5093
+#define SYSCFG_BASE                 (uint16_t)0x509D
+#define EXTI_BASE                   (uint16_t)0x50A0
+#define WFE_BASE                    (uint16_t)0x50A6
+#define RST_BASE                    (uint16_t)0x50B0
+#define PWR_BASE                    (uint16_t)0x50B2
+#define CLK_BASE                    (uint16_t)0x50C0
+#define WWDG_BASE                   (uint16_t)0x50D3
+#define IWDG_BASE                   (uint16_t)0x50E0
+#define BEEP_BASE                   (uint16_t)0x50F0
+#define RTC_BASE                    (uint16_t)0x5140
+#define CSSLSE_BASE                 (uint16_t)0x5190
+#define SPI1_BASE                   (uint16_t)0x5200
+#define SPI2_BASE                   (uint16_t)0x53C0
+#define I2C1_BASE                   (uint16_t)0x5210
+#define USART1_BASE                 (uint16_t)0x5230
+#define USART2_BASE                 (uint16_t)0x53E0
+#define USART3_BASE                 (uint16_t)0x53F0
+#define TIM2_BASE                   (uint16_t)0x5250
+#define TIM3_BASE                   (uint16_t)0x5280
+#define TIM1_BASE                   (uint16_t)0x52B0
+#define TIM4_BASE                   (uint16_t)0x52E0
+#define IRTIM_BASE                  (uint16_t)0x52FF
+#define TIM5_BASE                   (uint16_t)0x5300
+#define ADC1_BASE                   (uint16_t)0x5340
+#define DAC_BASE                    (uint16_t)0x5380
+#define AES_BASE                    (uint16_t)0x53D0
+#define LCD_BASE                    (uint16_t)0x5400
+#define RI_BASE                     (uint16_t)0x5430
+#define COMP_BASE                   (uint16_t)0x5440
+#define CFG_BASE                    (uint16_t)0x7F60
+#define ITC_BASE                    (uint16_t)0x7F70
+#define DM_BASE                     (uint16_t)0x7F90
+
+/******************************************************************************/
+/*                          Peripherals declarations                          */
+/******************************************************************************/
+
+
+#define SYSCFG                      ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define GPIOA                       ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB                       ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC                       ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD                       ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE                       ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF                       ((GPIO_TypeDef *) GPIOF_BASE)
+#define GPIOG                       ((GPIO_TypeDef *) GPIOG_BASE)
+#define GPIOH                       ((GPIO_TypeDef *) GPIOH_BASE)
+#define GPIOI                       ((GPIO_TypeDef *) GPIOI_BASE)
+#define RTC                         ((RTC_TypeDef *) RTC_BASE)
+#define FLASH                       ((FLASH_TypeDef *) FLASH_BASE)
+#define EXTI                        ((EXTI_TypeDef *) EXTI_BASE)
+#define RST                         ((RST_TypeDef *) RST_BASE)
+#define PWR                         ((PWR_TypeDef *) PWR_BASE)
+#define CLK                         ((CLK_TypeDef *) CLK_BASE)
+#define CSSLSE                      ((CSSLSE_TypeDef *) CSSLSE_BASE)
+#define WWDG                        ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG                        ((IWDG_TypeDef *) IWDG_BASE)
+#define WFE                         ((WFE_TypeDef *) WFE_BASE)
+#define BEEP                        ((BEEP_TypeDef *) BEEP_BASE)
+#define SPI1                        ((SPI_TypeDef *) SPI1_BASE)
+#define SPI2                        ((SPI_TypeDef *) SPI2_BASE)
+#define I2C1                        ((I2C_TypeDef *) I2C1_BASE)
+#define USART1                      ((USART_TypeDef *) USART1_BASE)
+#define USART2                      ((USART_TypeDef *) USART2_BASE)
+#define USART3                      ((USART_TypeDef *) USART3_BASE)
+#define LCD                         ((LCD_TypeDef *) LCD_BASE)
+#define TIM1                        ((TIM1_TypeDef *) TIM1_BASE)
+#define TIM2                        ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3                        ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4                        ((TIM4_TypeDef *) TIM4_BASE)
+#define TIM5                        ((TIM_TypeDef *) TIM5_BASE)
+#define IRTIM                       ((IRTIM_TypeDef *) IRTIM_BASE)
+#define ITC                         ((ITC_TypeDef *) ITC_BASE)
+#define DAC                         ((DAC_TypeDef *) DAC_BASE)
+#define DMA1                        ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Channel0               ((DMA_Channel_TypeDef *) DMA1_Channel0_BASE)
+#define DMA1_Channel1               ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2               ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3               ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DM                          ((DM_TypeDef *) DM_BASE)
+#define RI                          ((RI_TypeDef *) RI_BASE)
+#define COMP                        ((COMP_TypeDef *) COMP_BASE)
+#define AES                         ((AES_TypeDef *) AES_BASE)
+#define ADC1                        ((ADC_TypeDef *) ADC1_BASE)
+#define CFG                         ((CFG_TypeDef *) CFG_BASE)
+#define OPT                         ((OPT_TypeDef *) OPT_BASE)
+
+#ifdef USE_STDPERIPH_DRIVER 
+ #include "stm8l15x_conf.h"
+#endif
+
+/* Exported macro --------------------------------------------------------------*/
+
+/*============================== Interrupts ====================================*/
+#ifdef _RAISONANCE_
+ #include <intrist7.h>
+ #define enableInterrupts()  _rim_()  /*!<enable interrupts */
+ #define disableInterrupts() _sim_()  /*!<disable interrupts */
+ #define rim()               _rim_()  /*!<enable interrupts */
+ #define sim()               _sim_()  /*!<disable interrupts */
+ #define nop()               _nop_()  /*!<No Operation */
+ #define trap()              _trap_() /*!<Trap (soft IT) */
+ #define wfi()               _wfi_()  /*!<Wait For Interrupt */
+ #define wfe()               _wfe_()  /*!<Wait For Interrupt */
+ #define halt()              _halt_() /*!<Halt */
+#elif defined(_COSMIC_)
+ #define enableInterrupts() {_asm("rim\n");} /*!<enable interrupts */
+ #define disableInterrupts() {_asm("sim\n");} /*!<disable interrupts */
+ #define rim() {_asm("rim\n");} /*!<enable interrupts */
+ #define sim() {_asm("sim\n");} /*!<disable interrupts */
+ #define nop() {_asm("nop\n");} /*!<No Operation */
+ #define trap() {_asm("trap\n");} /*!<Trap (soft IT) */
+ #define wfi() {_asm("wfi\n");} /*!<Wait For Interrupt */
+ #define wfe() {_asm("wfe\n");} /*!<Wait for event */
+ #define halt() {_asm("halt\n");} /*!<Halt */
+#else /*_IAR*/
+ #include <intrinsics.h>
+ #define enableInterrupts()    __enable_interrupt()   /* enable interrupts */
+ #define disableInterrupts()   __disable_interrupt()  /* disable interrupts */
+ #define rim()                 __enable_interrupt()   /* enable interrupts */
+ #define sim()                 __disable_interrupt()  /* disable interrupts */
+ #define nop()                 __no_operation()       /* No Operation */
+ #define trap()                __trap()               /* Trap (soft IT) */
+ #define wfi()                 __wait_for_interrupt() /* Wait For Interrupt */
+ #define wfe()                 __wait_for_event();    /* Wait for event */
+ #define halt()                __halt()               /* Halt */
+#endif /* _RAISONANCE_ */
+
+/*============================== Interrupt vector Handling ========================*/
+
+#ifdef _COSMIC_
+ #define INTERRUPT_HANDLER(a,b) @far @interrupt void a(void)
+ #define INTERRUPT_HANDLER_TRAP(a) void @far @interrupt a(void)
+#endif /* _COSMIC_ */
+
+#ifdef _RAISONANCE_
+ #define INTERRUPT_HANDLER(a,b) void a(void) interrupt b
+ #define INTERRUPT_HANDLER_TRAP(a) void a(void) trap
+#endif /* _RAISONANCE_ */
+
+#ifdef _IAR_
+ #define STRINGVECTOR(x) #x
+ #define VECTOR_ID(x) STRINGVECTOR( vector = (x) )
+ #define INTERRUPT_HANDLER( a, b )  \
+ _Pragma( VECTOR_ID( (b)+2 ) )        \
+ __interrupt void (a)( void )
+ #define INTERRUPT_HANDLER_TRAP(a) \
+ _Pragma( VECTOR_ID( 1 ) ) \
+ __interrupt void (a) (void)  
+#endif /* _IAR_ */
+
+/*============================== Interrupt Handler declaration ========================*/
+#ifdef _COSMIC_
+ #define INTERRUPT @far @interrupt
+#elif defined(_IAR_)
+ #define INTERRUPT __interrupt
+#endif /* _COSMIC_ */
+ 
+/*============================== Handling bits ====================================*/
+/*-----------------------------------------------------------------------------
+Method : I
+Description : Handle the bit from the character variables.
+Comments :    The different parameters of commands are
+              - VAR : Name of the character variable where the bit is located.
+              - Place : Bit position in the variable (7 6 5 4 3 2 1 0)
+              - Value : Can be 0 (reset bit) or not 0 (set bit)
+              The "MskBit" command allows to select some bits in a source
+              variables and copy it in a destination var (return the value).
+              The "ValBit" command returns the value of a bit in a char
+              variable: the bit is reseted if it returns 0 else the bit is set.
+              This method generates not an optimised code yet.
+-----------------------------------------------------------------------------*/
+#define SetBit(VAR,Place)         ( (VAR) |= (uint8_t)((uint8_t)1<<(uint8_t)(Place)) )
+#define ClrBit(VAR,Place)         ( (VAR) &= (uint8_t)((uint8_t)((uint8_t)1<<(uint8_t)(Place))^(uint8_t)255) )
+
+#define ChgBit(VAR,Place)         ( (VAR) ^= (uint8_t)((uint8_t)1<<(uint8_t)(Place)) )
+#define AffBit(VAR,Place,Value)   ((Value) ? \
+                                   ((VAR) |= ((uint8_t)1<<(Place))) : \
+                                   ((VAR) &= (((uint8_t)1<<(Place))^(uint8_t)255)))
+#define MskBit(Dest,Msk,Src)      ( (Dest) = ((Msk) & (Src)) | ((~(Msk)) & (Dest)) )
+
+#define ValBit(VAR,Place)         ((uint8_t)(VAR) & (uint8_t)((uint8_t)1<<(uint8_t)(Place)))
+
+#define BYTE_0(n)                 ((uint8_t)((n) & (uint8_t)0xFF))        /*!< Returns the low byte of the 32-bit value */
+#define BYTE_1(n)                 ((uint8_t)(BYTE_0((n) >> (uint8_t)8)))  /*!< Returns the second byte of the 32-bit value */
+#define BYTE_2(n)                 ((uint8_t)(BYTE_0((n) >> (uint8_t)16))) /*!< Returns the third byte of the 32-bit value */
+#define BYTE_3(n)                 ((uint8_t)(BYTE_0((n) >> (uint8_t)24))) /*!< Returns the high byte of the 32-bit value */
+
+/*============================== Assert Macros ====================================*/
+#define IS_STATE_VALUE(STATE) \
+  (((STATE) == SET) || \
+   ((STATE) == RESET))
+
+/*-----------------------------------------------------------------------------
+Method : II
+Description : Handle directly the bit.
+Comments :    The idea is to handle directly with the bit name. For that, it is
+              necessary to have RAM area descriptions (example: HW register...)
+              and the following command line for each area.
+              This method generates the most optimized code.
+-----------------------------------------------------------------------------*/
+
+#define AREA 0x00     /* The area of bits begins at address 0x10. */
+
+#define BitClr(BIT)  ( *((unsigned char *) (AREA+(BIT)/8)) &= (~(1<<(7-(BIT)%8))) )
+#define BitSet(BIT)  ( *((unsigned char *) (AREA+(BIT)/8)) |= (1<<(7-(BIT)%8)) )
+#define BitVal(BIT)  ( *((unsigned char *) (AREA+(BIT)/8)) & (1<<(7-(BIT)%8)) )
+
+
+#endif /* __STM8L15x_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_adc.h b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_adc.h
new file mode 100755
index 0000000..c633c1a
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_adc.h
@@ -0,0 +1,383 @@
+/**
+  ******************************************************************************
+  * @file    stm8l15x_adc.h
+  * @author  MCD Application Team
+  * @version V1.6.0
+  * @date    28-June-2013
+  * @brief   This file contains all the functions prototypes for the ADC 
+  *          firmware library.
+  ******************************************************************************
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ****************************************************************************** 
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM8L15x_ADC_H
+#define __STM8L15x_ADC_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm8l15x.h"
+
+/** @addtogroup STM8L15x_StdPeriph_Driver
+  * @{
+  */
+  
+/** @addtogroup ADC
+  * @{
+  */ 
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup ADC_Exported_Types
+  * @{
+  */
+
+
+/** @defgroup ADC_Channels 
+  * @{
+  */
+typedef enum
+{
+  ADC_Channel_0           = ((uint16_t)0x0301), /*!< Channel 00 */
+  ADC_Channel_1           = ((uint16_t)0x0302), /*!< Channel 01 */
+  ADC_Channel_2           = ((uint16_t)0x0304), /*!< Channel 02 */
+  ADC_Channel_3           = ((uint16_t)0x0308), /*!< Channel 03 */
+  ADC_Channel_4           = ((uint16_t)0x0310), /*!< Channel 04 */
+  ADC_Channel_5           = ((uint16_t)0x0320), /*!< Channel 05 */
+  ADC_Channel_6           = ((uint16_t)0x0340), /*!< Channel 06 */
+  ADC_Channel_7           = ((uint16_t)0x0380), /*!< Channel 07 */
+
+  ADC_Channel_8           = ((uint16_t)0x0201), /*!< Channel 08 */
+  ADC_Channel_9           = ((uint16_t)0x0202), /*!< Channel 09 */
+  ADC_Channel_10          = ((uint16_t)0x0204), /*!< Channel 10 */
+  ADC_Channel_11          = ((uint16_t)0x0208), /*!< Channel 11 */
+  ADC_Channel_12          = ((uint16_t)0x0210), /*!< Channel 12 */
+  ADC_Channel_13          = ((uint16_t)0x0220), /*!< Channel 13 */
+  ADC_Channel_14          = ((uint16_t)0x0240), /*!< Channel 14 */
+  ADC_Channel_15          = ((uint16_t)0x0280), /*!< Channel 15 */
+
+  ADC_Channel_16          = ((uint16_t)0x0101), /*!< Channel 16 */
+  ADC_Channel_17          = ((uint16_t)0x0102), /*!< Channel 17 */
+  ADC_Channel_18          = ((uint16_t)0x0104), /*!< Channel 18 */
+  ADC_Channel_19          = ((uint16_t)0x0108), /*!< Channel 19 */
+  ADC_Channel_20          = ((uint16_t)0x0110), /*!< Channel 20 */
+  ADC_Channel_21          = ((uint16_t)0x0120), /*!< Channel 21 */
+  ADC_Channel_22          = ((uint16_t)0x0140), /*!< Channel 22 */
+  ADC_Channel_23          = ((uint16_t)0x0180), /*!< Channel 23 */
+
+  ADC_Channel_24          = ((uint16_t)0x0001), /*!< Channel 24 */
+  ADC_Channel_25          = ((uint16_t)0x0002), /*!< Channel 25 */
+  ADC_Channel_26          = ((uint16_t)0x0004), /*!< Channel 26 */
+  ADC_Channel_27          = ((uint16_t)0x0008), /*!< Channel 27 */
+
+  ADC_Channel_Vrefint     = ((uint16_t)0x0010), /*!< Vrefint Channel  */
+  ADC_Channel_TempSensor  = ((uint16_t)0x0020), /*!< Temperature sensor Channel  */
+
+  /* combination*/
+  ADC_Channel_00To07      = ((uint16_t)0x03FF), /*!<select from channel00 to channel07 */
+  ADC_Channel_08To15      = ((uint16_t)0x02FF), /*!<select from channel08 to channel15 */
+  ADC_Channel_16To23      = ((uint16_t)0x01FF), /*!<select from channel16 to channel23 */
+  ADC_Channel_24To27      = ((uint16_t)0x00FF)  /*!<select from channel24 to channel27 */
+
+}ADC_Channel_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup ADC_Conversion_Mode
+  * @{
+  */
+typedef enum
+{
+  ADC_ConversionMode_Single     = ((uint8_t)0x00), /*!< Single Conversion Mode */
+  ADC_ConversionMode_Continuous = ((uint8_t)0x04)  /*!< Continuous Conversion Mode */
+}ADC_ConversionMode_TypeDef;
+
+#define IS_ADC_CONVERSION_MODE(MODE) (((MODE) == ADC_ConversionMode_Single) || \
+                                      ((MODE) == ADC_ConversionMode_Continuous))
+/**
+  * @}
+  */
+  
+/** @defgroup ADC_Resolution
+  * @{
+  */
+typedef enum
+{
+  ADC_Resolution_12Bit = ((uint8_t)0x00), /*!< 12 bit resolution */
+  ADC_Resolution_10Bit = ((uint8_t)0x20), /*!< 10 bit resolution */
+  ADC_Resolution_8Bit  = ((uint8_t)0x40), /*!<  8 bit resolution */
+  ADC_Resolution_6Bit  = ((uint8_t)0x60)  /*!<  6 bit resolution */
+}ADC_Resolution_TypeDef;
+
+#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12Bit) || \
+                                       ((RESOLUTION) == ADC_Resolution_10Bit) || \
+                                       ((RESOLUTION) == ADC_Resolution_8Bit) || \
+                                       ((RESOLUTION) == ADC_Resolution_6Bit))
+/**
+  * @}
+  */
+  
+/** @defgroup ADC_Clock_Prescaler
+  * @{
+  */
+typedef enum
+{
+  ADC_Prescaler_1 = ((uint8_t)0x00), /*!< ADC Clock frequency is divided by 1 */
+  ADC_Prescaler_2 = ((uint8_t)0x80)  /*!< ADC Clock frequency is divided by 2 */
+}ADC_Prescaler_TypeDef;
+
+#define IS_ADC_PRESCALER(PRESCALER) (((PRESCALER) == ADC_Prescaler_1) || \
+                                     ((PRESCALER) == ADC_Prescaler_2))
+/**
+  * @}
+  */
+  
+/** @defgroup ADC_External_Trigger_Sensitivity
+  * @{
+  */
+typedef enum
+{
+  ADC_ExtTRGSensitivity_Rising  = ((uint8_t)0x20), /*!< External Trigger Sensitivity is Rising Edge */
+  ADC_ExtTRGSensitivity_Falling = ((uint8_t)0x40), /*!< External Trigger Sensitivity is Falling Edge */
+  ADC_ExtTRGSensitivity_All     = ((uint8_t)0x60)  /*!< External Trigger Sensitivity is Falling and Rising Edge */
+}ADC_ExtTRGSensitivity_TypeDef;
+
+#define IS_ADC_EXT_TRG_SENSITIVITY(SENSITIVITY) (((SENSITIVITY) == ADC_ExtTRGSensitivity_Rising) || \
+                                                 ((SENSITIVITY) == ADC_ExtTRGSensitivity_Falling) || \
+                                                 ((SENSITIVITY) == ADC_ExtTRGSensitivity_All))
+/**
+  * @}
+  */
+  
+/** @defgroup ADC_External_Event_Source_Selection
+  * @{
+  */
+typedef enum
+{
+  ADC_ExtEventSelection_None     = ((uint8_t)0x00), /*!< Conversion starts only by software start */
+  ADC_ExtEventSelection_Trigger1 = ((uint8_t)0x08), /*!< Trigger 1  Enables conversion */
+  ADC_ExtEventSelection_Trigger2 = ((uint8_t)0x10), /*!< Trigger 2 Enables conversion */
+  ADC_ExtEventSelection_Trigger3 = ((uint8_t)0x18)  /*!< Trigger 3 Enables conversion */
+}ADC_ExtEventSelection_TypeDef;
+
+#define IS_ADC_EXT_EVENT_SELECTION(SELECTION) (((SELECTION) == ADC_ExtEventSelection_None) || \
+                                               ((SELECTION) == ADC_ExtEventSelection_Trigger1) || \
+                                               ((SELECTION) == ADC_ExtEventSelection_Trigger2) || \
+                                               ((SELECTION) == ADC_ExtEventSelection_Trigger3))
+/**
+  * @}
+  */
+  
+/** @defgroup ADC_Group_Channel_Definition
+  * @{
+  */
+typedef enum
+{
+  ADC_Group_SlowChannels = ((uint8_t)0x00), /*!<Slow Channels group(Channel 0 to 23) */
+  ADC_Group_FastChannels = ((uint8_t)0x01)  /*!<Fast Channels group Channel 24 to 27, 
+                                                Channel Vrefint, Channel TempSensor)*/
+}ADC_Group_TypeDef;
+
+#define IS_ADC_GROUP(GROUP) (((GROUP) == ADC_Group_SlowChannels) || \
+                             ((GROUP) == ADC_Group_FastChannels))
+/**
+  * @}
+  */
+  
+/** @defgroup ADC_Sampling_Time
+  * @{
+  */
+typedef enum
+{
+  ADC_SamplingTime_4Cycles   = ((uint8_t)0x00), /*!< Sampling Time Cycles is 4 */
+  ADC_SamplingTime_9Cycles   = ((uint8_t)0x01), /*!< Sampling Time Cycles is 9 */
+  ADC_SamplingTime_16Cycles  = ((uint8_t)0x02), /*!< Sampling Time Cycles is 16 */
+  ADC_SamplingTime_24Cycles  = ((uint8_t)0x03), /*!< Sampling Time Cycles is 24 */
+  ADC_SamplingTime_48Cycles  = ((uint8_t)0x04), /*!< Sampling Time Cycles is 48 */
+  ADC_SamplingTime_96Cycles  = ((uint8_t)0x05), /*!< Sampling Time Cycles is 96 */
+  ADC_SamplingTime_192Cycles = ((uint8_t)0x06), /*!< Sampling Time Cycles is 192 */
+  ADC_SamplingTime_384Cycles = ((uint8_t)0x07)  /*!< Sampling Time Cycles is 384 */
+}ADC_SamplingTime_TypeDef;
+
+#define IS_ADC_SAMPLING_TIME_CYCLES(TIME) (((TIME) == ADC_SamplingTime_4Cycles) || \
+                                           ((TIME) == ADC_SamplingTime_9Cycles) || \
+                                           ((TIME) == ADC_SamplingTime_16Cycles) || \
+                                           ((TIME) == ADC_SamplingTime_24Cycles) || \
+                                           ((TIME) == ADC_SamplingTime_48Cycles) || \
+                                           ((TIME) == ADC_SamplingTime_96Cycles) || \
+                                           ((TIME) == ADC_SamplingTime_192Cycles) || \
+                                           ((TIME) == ADC_SamplingTime_384Cycles))
+/**
+  * @}
+  */
+  
+/** @defgroup  ADC_Analog_WatchDog_Channel_selection
+  * @{
+  */
+typedef enum
+{
+  ADC_AnalogWatchdogSelection_Channel0  = ((uint8_t)0x00), /*!< AWD affected to Channel 0 */
+  ADC_AnalogWatchdogSelection_Channel1  = ((uint8_t)0x01), /*!< AWD affected to Channel 1 */
+  ADC_AnalogWatchdogSelection_Channel2  = ((uint8_t)0x02), /*!< AWD affected to Channel 2 */
+  ADC_AnalogWatchdogSelection_Channel3  = ((uint8_t)0x03), /*!< AWD affected to Channel 3 */
+  ADC_AnalogWatchdogSelection_Channel4  = ((uint8_t)0x04), /*!< AWD affected to Channel 4 */
+  ADC_AnalogWatchdogSelection_Channel5  = ((uint8_t)0x05), /*!< AWD affected to Channel 5 */
+  ADC_AnalogWatchdogSelection_Channel6  = ((uint8_t)0x06), /*!< AWD affected to Channel 6 */
+  ADC_AnalogWatchdogSelection_Channel7  = ((uint8_t)0x07), /*!< AWD affected to Channel 7 */
+  ADC_AnalogWatchdogSelection_Channel8  = ((uint8_t)0x08), /*!< AWD affected to Channel 8 */
+  ADC_AnalogWatchdogSelection_Channel9  = ((uint8_t)0x09), /*!< AWD affected to Channel 9 */
+  ADC_AnalogWatchdogSelection_Channel10 = ((uint8_t)0x0A), /*!< AWD affected to Channel 10 */
+  ADC_AnalogWatchdogSelection_Channel11 = ((uint8_t)0x0B), /*!< AWD affected to Channel 11 */
+  ADC_AnalogWatchdogSelection_Channel12 = ((uint8_t)0x0C), /*!< AWD affected to Channel 12 */
+  ADC_AnalogWatchdogSelection_Channel13 = ((uint8_t)0x0D), /*!< AWD affected to Channel 13 */
+  ADC_AnalogWatchdogSelection_Channel14 = ((uint8_t)0x0E), /*!< AWD affected to Channel 14 */
+  ADC_AnalogWatchdogSelection_Channel15 = ((uint8_t)0x0F), /*!< AWD affected to Channel 15 */
+  ADC_AnalogWatchdogSelection_Channel16 = ((uint8_t)0x10), /*!< AWD affected to Channel 16 */
+  ADC_AnalogWatchdogSelection_Channel17 = ((uint8_t)0x11), /*!< AWD affected to Channel 17 */
+  ADC_AnalogWatchdogSelection_Channel18 = ((uint8_t)0x12), /*!< AWD affected to Channel 18 */
+  ADC_AnalogWatchdogSelection_Channel19 = ((uint8_t)0x13), /*!< AWD affected to Channel 19 */
+  ADC_AnalogWatchdogSelection_Channel20 = ((uint8_t)0x14), /*!< AWD affected to Channel 20 */
+  ADC_AnalogWatchdogSelection_Channel21 = ((uint8_t)0x15), /*!< AWD affected to Channel 21 */
+  ADC_AnalogWatchdogSelection_Channel22 = ((uint8_t)0x16), /*!< AWD affected to Channel 22 */
+  ADC_AnalogWatchdogSelection_Channel23 = ((uint8_t)0x17), /*!< AWD affected to Channel 23 */
+
+  ADC_AnalogWatchdogSelection_Channel24  = ((uint8_t)0x18), /*!< AWD affected to Channel 24 */
+  ADC_AnalogWatchdogSelection_Channel25  = ((uint8_t)0x19), /*!< AWD affected to Channel 25 */
+  ADC_AnalogWatchdogSelection_Channel26  = ((uint8_t)0x1A), /*!< AWD affected to Channel 26 */
+  ADC_AnalogWatchdogSelection_Channel27  = ((uint8_t)0x1B), /*!< AWD affected to Channel 27 */
+
+  ADC_AnalogWatchdogSelection_Vrefint    = ((uint8_t)0x1C), /*!< AWD affected to Internal Vref Channel  */
+  ADC_AnalogWatchdogSelection_TempSensor = ((uint8_t)0x1D)  /*!< AWD affected to Temperature Sensor Channel */
+}ADC_AnalogWatchdogSelection_TypeDef;
+
+#define IS_ADC_ANALOGWATCHDOG_SELECTION(CHANNEL) (((CHANNEL) <= 0x1D))
+/**
+  * @}
+  */
+  
+/** @defgroup  ADC_Interrupts
+  * @{
+  */
+typedef enum
+{
+  ADC_IT_EOC  = ((uint8_t)0x08), /*!< End of Conversion  Interrupt  */
+  ADC_IT_AWD  = ((uint8_t)0x10), /*!< Analog WatchDog  Interrupt  */
+  ADC_IT_OVER = ((uint8_t)0x80)  /*!< Over Run Interrupt  */
+}ADC_IT_TypeDef;
+
+#define IS_ADC_IT(IT) ((((IT) & (uint8_t)0x67) == 0x00) && ((IT) != 0x00))
+#define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \
+                           ((IT) == ADC_IT_OVER))
+/**
+  * @}
+  */
+  
+/** @defgroup  ADC_Flags
+  * @{
+  */
+typedef enum
+{
+  ADC_FLAG_EOC  = ((uint8_t)0x01), /*!< End of Conversion  flag  */
+  ADC_FLAG_AWD  = ((uint8_t)0x02), /*!< Analog WatchDog  flag  */
+  ADC_FLAG_OVER = ((uint8_t)0x04)  /*!< Over Run flag  */
+}ADC_FLAG_TypeDef;
+
+#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xF8) == 0x00) && ((FLAG) != 0x00))
+#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_EOC) || ((FLAG) == ADC_FLAG_AWD) || \
+                               ((FLAG) == ADC_FLAG_OVER))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Exported constants --------------------------------------------------------*/  
+/* Exported Macros -----------------------------------------------------------*/
+/** @defgroup ADC_Exported_Macros
+  * @{
+  */
+#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+  
+/*  Function used to set the ADC configuration to the default reset state *****/
+void ADC_DeInit(ADC_TypeDef* ADCx);
+
+/* Initialization and Configuration functions *********************************/ 
+void ADC_Init(ADC_TypeDef* ADCx,
+              ADC_ConversionMode_TypeDef ADC_ConversionMode,
+              ADC_Resolution_TypeDef ADC_Resolution,
+              ADC_Prescaler_TypeDef ADC_Prescaler);
+void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_SoftwareStartConv(ADC_TypeDef* ADCx);
+void ADC_ExternalTrigConfig(ADC_TypeDef* ADCx,
+                            ADC_ExtEventSelection_TypeDef ADC_ExtEventSelection,
+                            ADC_ExtTRGSensitivity_TypeDef ADC_ExtTRGSensitivity);
+                            
+/* Analog Watchdog configuration functions ************************************/
+void ADC_AnalogWatchdogChannelSelect(ADC_TypeDef* ADCx,
+                                     ADC_AnalogWatchdogSelection_TypeDef ADC_AnalogWatchdogSelection);
+void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,
+                                        uint16_t LowThreshold);
+void ADC_AnalogWatchdogConfig(ADC_TypeDef* ADCx,
+                              ADC_AnalogWatchdogSelection_TypeDef ADC_AnalogWatchdogSelection,
+                              uint16_t HighThreshold,
+                              uint16_t LowThreshold);
+
+/* Temperature Sensor & Vrefint (Voltage Reference internal) management functions */
+void ADC_TempSensorCmd(FunctionalState NewState);
+void ADC_VrefintCmd(FunctionalState NewState);
+
+/* Channels Configuration functions *******************************************/                              
+void ADC_ChannelCmd(ADC_TypeDef* ADCx, ADC_Channel_TypeDef ADC_Channels,
+                    FunctionalState NewState);
+
+void ADC_SamplingTimeConfig(ADC_TypeDef* ADCx, ADC_Group_TypeDef ADC_GroupChannels,
+                            ADC_SamplingTime_TypeDef ADC_SamplingTime);
+void ADC_SchmittTriggerConfig(ADC_TypeDef* ADCx, ADC_Channel_TypeDef ADC_Channels,
+                              FunctionalState NewState);
+uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);
+
+
+
+/* Channels DMA Configuration function ****************************************/
+void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+
+/* Interrupts and flags management functions **********************************/
+void ADC_ITConfig(ADC_TypeDef* ADCx, 
+                  ADC_IT_TypeDef ADC_IT, 
+                  FunctionalState NewState);
+FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, ADC_FLAG_TypeDef ADC_FLAG);
+void ADC_ClearFlag(ADC_TypeDef* ADCx, ADC_FLAG_TypeDef ADC_FLAG);
+ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, ADC_IT_TypeDef ADC_IT);
+void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, ADC_IT_TypeDef ADC_IT);
+
+#endif /*__STM8L15x_ADC_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_aes.h b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_aes.h
new file mode 100755
index 0000000..a5a78e9
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_aes.h
@@ -0,0 +1,155 @@
+/**
+  ********************************************************************************
+  * @file    stm8l15x_aes.h
+  * @author  MCD Application Team
+  * @version V1.6.0
+  * @date    28-June-2013
+  * @brief   This file contains all the functions prototypes for the AES firmware
+  *          library.
+  ******************************************************************************
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ****************************************************************************** 
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM8L15x_AES_H
+#define __STM8L15x_AES_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm8l15x.h"
+
+/** @addtogroup STM8L15x_StdPeriph_Driver
+  * @{
+  */
+  
+/** @addtogroup AES
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup AES_Exported_Types
+  * @{
+  */
+
+/** @defgroup AES_Operation_Mode
+  * @{
+  */
+typedef enum
+{
+  AES_Operation_Encryp            = (uint8_t)0x00, /*!< AES in Encryption mode */
+  AES_Operation_KeyDeriv          = (uint8_t)0x02, /*!< AES in Key Derivation mode */
+  AES_Operation_Decryp            = (uint8_t)0x04, /*!< AES in Decryption mode */
+  AES_Operation_KeyDerivAndDecryp = (uint8_t)0x06  /*!< AES in Key Derivation and Decryption mode */
+} AES_Operation_TypeDef;
+
+#define IS_AES_MODE(Operation) (((Operation) == AES_Operation_Encryp) || \
+                                ((Operation) == AES_Operation_KeyDeriv) || \
+                                ((Operation) == AES_Operation_Decryp)   || \
+                                ((Operation) == AES_Operation_KeyDerivAndDecryp))
+/**
+  * @}
+  */
+  
+/** @defgroup AES_Flags
+  * @{
+  */
+typedef enum
+{
+  AES_FLAG_CCF      = (uint8_t)0x01,  /*!< Computation Complete Flag */
+  AES_FLAG_RDERR    = (uint8_t)0x02,  /*!< Read Error Flag           */
+  AES_FLAG_WRERR    = (uint8_t)0x04   /*!< Write Error Flag          */
+}AES_FLAG_TypeDef;
+
+#define IS_AES_FLAG(Flag)  (((Flag) == AES_FLAG_CCF) || \
+                            ((Flag) == AES_FLAG_RDERR)  || \
+                            ((Flag) == AES_FLAG_WRERR))
+   
+/**
+  * @}
+  */
+  
+/** @defgroup AES_Interrupts
+  * @{
+  */
+typedef enum
+{
+  AES_IT_CCIE   = (uint16_t)0x20, /*!< Computation Complete interrupt enable */
+  AES_IT_ERRIE  = (uint16_t)0x40  /*!< Error interrupt enable                */
+}AES_IT_TypeDef;
+
+#define IS_AES_IT(IT) (((IT) == AES_IT_CCIE) || \
+                       ((IT) == AES_IT_ERRIE))
+   
+/**
+  * @}
+  */
+  
+/** @defgroup AES_DMA_Transfer_Direction
+  * @{
+  */
+typedef enum
+{
+  AES_DMATransfer_InOut = (uint8_t) 0x80 /*!< DMA requests enabled for input transfer phase
+                                              as well as for the output transfer phase */
+}
+AES_DMATransfer_TypeDef;
+
+#define IS_AES_DMATRANSFER(Transfer)   ((Transfer) == AES_DMATransfer_InOut)
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+  
+/* Exported constants --------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+/*  Function used to set the AES configuration to the default reset state *****/  
+void AES_DeInit(void);
+
+/* AES Configuration **********************************************************/
+void AES_OperationModeConfig(AES_Operation_TypeDef AES_Operation);
+void AES_Cmd(FunctionalState NewState);
+
+/* AES Read and Write operations **********************************************/
+void AES_WriteSubData(uint8_t Data);
+void AES_WriteSubKey(uint8_t Key);
+uint8_t AES_ReadSubData(void);
+uint8_t AES_ReadSubKey(void);
+
+/* DMA transfers management function ******************************************/
+void AES_DMAConfig(AES_DMATransfer_TypeDef AES_DMATransfer, FunctionalState NewState);
+
+/* Interrupts and flags management functions **********************************/
+void AES_ITConfig(AES_IT_TypeDef AES_IT, FunctionalState NewState);
+FlagStatus AES_GetFlagStatus(AES_FLAG_TypeDef AES_FLAG);
+void AES_ClearFlag(AES_FLAG_TypeDef AES_FLAG);
+ITStatus AES_GetITStatus(AES_IT_TypeDef AES_IT);
+void AES_ClearITPendingBit(AES_IT_TypeDef AES_IT);
+
+#endif /* __STM8L15x_AES_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_beep.h b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_beep.h
new file mode 100755
index 0000000..0e7c3f8
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_beep.h
@@ -0,0 +1,114 @@
+/**
+  ******************************************************************************
+  * @file    stm8l15x_beep.h
+  * @author  MCD Application Team
+  * @version V1.6.0
+  * @date    28-June-2013
+  * @brief   This file contains all the functions prototypes for the BEEP firmware
+  *          library.
+  ******************************************************************************
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ****************************************************************************** 
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM8L15x_BEEP_H
+#define __STM8L15x_BEEP_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm8l15x.h"
+
+/** @addtogroup STM8L15x_StdPeriph_Driver
+  * @{
+  */
+  
+/** @addtogroup BEEP
+  * @{
+  */ 
+  
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup BEEP_Exported_Types
+  * @{
+  */
+  
+/** @defgroup BEEP_Frequency
+  * @{
+  */
+typedef enum {
+  BEEP_Frequency_1KHz = (uint8_t)0x00,  /*!< Beep signal output frequency 1 KHz */
+  BEEP_Frequency_2KHz = (uint8_t)0x40,  /*!< Beep signal output frequency 2 KHz */
+  BEEP_Frequency_4KHz = (uint8_t)0x80   /*!< Beep signal output frequency 4 KHz */
+} BEEP_Frequency_TypeDef;
+
+#define IS_BEEP_FREQUENCY(FREQ) (((FREQ) == BEEP_Frequency_1KHz) || \
+                                 ((FREQ) == BEEP_Frequency_2KHz) || \
+                                 ((FREQ) == BEEP_Frequency_4KHz))
+ 
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+      
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup BEEP_Exported_Constants
+  * @{
+  */
+
+#define BEEP_CALIBRATION_DEFAULT ((uint8_t)0x01)  /*!< Default value when calibration is not done */
+#define LSI_FREQUENCY_MIN ((uint32_t)25000)       /*!< LSI minimum value in Hertz */
+#define LSI_FREQUENCY_MAX ((uint32_t)75000)       /*!< LSI maximum value in Hertz */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup BEEP_Exported_Macros
+  * @{
+  */
+#define IS_LSI_FREQUENCY(FREQ) (((FREQ) >= LSI_FREQUENCY_MIN) && ((FREQ) <= LSI_FREQUENCY_MAX))
+
+/**
+  * @}
+  */
+
+/* Exported functions ------------------------------------------------------- */
+
+/*  Function used to set the BEEP configuration to the default reset state *****/  
+void BEEP_DeInit(void);
+
+/* Initialization and Configuration functions *********************************/
+void BEEP_Init(BEEP_Frequency_TypeDef BEEP_Frequency);
+void BEEP_Cmd(FunctionalState NewState);
+
+/* Low Speed Internal Clock(LSI) Calibration functions functions **************/
+void BEEP_LSClockToTIMConnectCmd(FunctionalState NewState);
+void BEEP_LSICalibrationConfig(uint32_t LSIFreqHz);
+
+
+#endif /* __STM8L15x_BEEP_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_clk.h b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_clk.h
new file mode 100755
index 0000000..bbcf35d
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_clk.h
@@ -0,0 +1,441 @@
+/**
+  ******************************************************************************
+  * @file    stm8l15x_clk.h
+  * @author  MCD Application Team
+  * @version V1.6.0
+  * @date    28-June-2013
+  * @brief   This file contains all the functions prototypes for the CLK firmware
+  *          library.
+  ******************************************************************************
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ****************************************************************************** 
+  */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM8L15x_CLK_H
+#define __STM8L15x_CLK_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm8l15x.h"
+
+/** @addtogroup STM8L15x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup CLK
+  * @{
+  */ 
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup Exported_Types
+  * @{
+  */
+  
+/** @defgroup CLK_HSE_Configuration
+  * @{
+  */
+typedef enum {
+  CLK_HSE_OFF    = (uint8_t)0x00, /*!< HSE Diasble */
+  CLK_HSE_ON     = (uint8_t)0x01, /*!< HSE Enable */
+  CLK_HSE_Bypass = (uint8_t)0x11  /*!< HSE Bypass and enable */
+} CLK_HSE_TypeDef;
+
+#define IS_CLK_HSE(CONFIG) (((CONFIG) == CLK_HSE_ON) ||\
+                            ((CONFIG) == CLK_HSE_OFF)||\
+                            ((CONFIG) == CLK_HSE_Bypass))
+/**
+  * @}
+  */
+                              
+/** @defgroup CLK_LSE_Configuration
+  * @{
+  */
+typedef enum {
+  CLK_LSE_OFF    = (uint8_t)0x00, /*!< LSE Diasble */
+  CLK_LSE_ON     = (uint8_t)0x04, /*!< LSE Enable */
+  CLK_LSE_Bypass = (uint8_t)0x24  /*!< LSE Bypass and enable */
+} CLK_LSE_TypeDef;
+
+#define IS_CLK_LSE(CONFIG) (((CONFIG) == CLK_LSE_OFF) ||\
+                            ((CONFIG) == CLK_LSE_ON)  ||\
+                            ((CONFIG) == CLK_LSE_Bypass))
+/**
+  * @}
+  */
+
+/** @defgroup CLK_System_Clock_Sources
+  * @{
+  */
+typedef enum {
+  CLK_SYSCLKSource_HSI = (uint8_t)0x01, /*!< System Clock Source HSI */
+  CLK_SYSCLKSource_LSI = (uint8_t)0x02, /*!< System Clock Source LSI */
+  CLK_SYSCLKSource_HSE = (uint8_t)0x04, /*!< System Clock Source HSE */
+  CLK_SYSCLKSource_LSE = (uint8_t)0x08  /*!< System Clock Source LSE */
+} CLK_SYSCLKSource_TypeDef;
+
+#define IS_CLK_SOURCE(SOURCE) (((SOURCE) == CLK_SYSCLKSource_HSI) ||\
+                               ((SOURCE) == CLK_SYSCLKSource_LSI) ||\
+                               ((SOURCE) == CLK_SYSCLKSource_HSE) ||\
+                               ((SOURCE) == CLK_SYSCLKSource_LSE))
+/**
+  * @}
+  */
+
+/** @defgroup CLK_Clock_Output_Selection
+  * @{
+  */
+typedef enum {
+  CLK_CCOSource_Off = (uint8_t)0x00, /*!< Clock Output Off */
+  CLK_CCOSource_HSI = (uint8_t)0x02, /*!< HSI Clock Output  */
+  CLK_CCOSource_LSI = (uint8_t)0x04, /*!< LSI Clock Output */
+  CLK_CCOSource_HSE = (uint8_t)0x08, /*!< HSE Clock Output */
+  CLK_CCOSource_LSE = (uint8_t)0x10  /*!< LSE Clock Output */
+} CLK_CCOSource_TypeDef;
+
+#define IS_CLK_OUTPUT(OUTPUT)  (((OUTPUT) == CLK_CCOSource_Off)  ||\
+                                ((OUTPUT) == CLK_CCOSource_HSI)  ||\
+                                ((OUTPUT) == CLK_CCOSource_LSI)  ||\
+                                ((OUTPUT) == CLK_CCOSource_HSE)  ||\
+                                ((OUTPUT) == CLK_CCOSource_LSE))
+/**
+  * @}
+  */
+     
+/** @defgroup CLK_Clock_Output_Prescaler
+  * @{
+  */
+typedef enum {
+  CLK_CCODiv_1  = (uint8_t)0x00, /*!< Clock Output Div 1 */
+  CLK_CCODiv_2  = (uint8_t)0x20, /*!< Clock Output Div 2 */
+  CLK_CCODiv_4  = (uint8_t)0x40, /*!< Clock Output Div 4 */
+  CLK_CCODiv_8  = (uint8_t)0x60, /*!< Clock Output Div 8 */
+  CLK_CCODiv_16 = (uint8_t)0x80, /*!< Clock Output Div 16 */
+  CLK_CCODiv_32 = (uint8_t)0xA0, /*!< Clock Output Div 32 */
+  CLK_CCODiv_64 = (uint8_t)0xC0  /*!< Clock Output Div 64 */
+} CLK_CCODiv_TypeDef;
+
+#define IS_CLK_OUTPUT_DIVIDER(PRESCALER) (((PRESCALER) == CLK_CCODiv_1)  ||\
+                                          ((PRESCALER) == CLK_CCODiv_2)  ||\
+                                          ((PRESCALER) == CLK_CCODiv_4)  ||\
+                                          ((PRESCALER) == CLK_CCODiv_8)  ||\
+                                          ((PRESCALER) == CLK_CCODiv_16) ||\
+                                          ((PRESCALER) == CLK_CCODiv_32) ||\
+                                          ((PRESCALER) == CLK_CCODiv_64))
+/**
+  * @}
+  */
+  
+/** @defgroup CLK_Beep_Selection
+  * @{
+  */
+typedef enum {
+  CLK_BEEPCLKSource_Off = (uint8_t)0x00, /*!< Clock BEEP Off */
+  CLK_BEEPCLKSource_LSI = (uint8_t)0x02, /*!< Clock BEEP : LSI */
+  CLK_BEEPCLKSource_LSE = (uint8_t)0x04  /*!< Clock BEEP : LSE */
+} CLK_BEEPCLKSource_TypeDef;
+
+#define IS_CLK_CLOCK_BEEP(OUTPUT) (((OUTPUT) == CLK_BEEPCLKSource_Off)  ||\
+                                   ((OUTPUT) == CLK_BEEPCLKSource_LSI)  ||\
+                                   ((OUTPUT) == CLK_BEEPCLKSource_LSE))
+/**
+  * @}
+  */
+  
+/** @defgroup CLK_RTC_Selection
+  * @{
+  */
+typedef enum {
+  CLK_RTCCLKSource_Off = (uint8_t)0x00, /*!< Clock RTC Off */
+  CLK_RTCCLKSource_HSI = (uint8_t)0x02, /*!< Clock RTC : HSI */
+  CLK_RTCCLKSource_LSI = (uint8_t)0x04, /*!< Clock RTC : LSI */
+  CLK_RTCCLKSource_HSE = (uint8_t)0x08, /*!< Clock RTC : HSE */
+  CLK_RTCCLKSource_LSE = (uint8_t)0x10  /*!< Clock RTC : LSE */
+} CLK_RTCCLKSource_TypeDef;
+
+#define IS_CLK_CLOCK_RTC(OUTPUT) (((OUTPUT) == CLK_RTCCLKSource_Off)  ||\
+                                  ((OUTPUT) == CLK_RTCCLKSource_HSI)  ||\
+                                  ((OUTPUT) == CLK_RTCCLKSource_LSI)  ||\
+                                  ((OUTPUT) == CLK_RTCCLKSource_HSE)  ||\
+                                  ((OUTPUT) == CLK_RTCCLKSource_LSE))
+/**
+  * @}
+  */
+  
+/** @defgroup CLK_RTC_Prescaler
+  * @{
+  */
+typedef enum {
+  CLK_RTCCLKDiv_1  = (uint8_t)0x00, /*!< Clock RTC Div 1 */
+  CLK_RTCCLKDiv_2  = (uint8_t)0x20, /*!< Clock RTC Div 2  */
+  CLK_RTCCLKDiv_4  = (uint8_t)0x40, /*!< Clock RTC Div 4 */
+  CLK_RTCCLKDiv_8  = (uint8_t)0x60, /*!< Clock RTC Div 8 */
+  CLK_RTCCLKDiv_16 = (uint8_t)0x80, /*!< Clock RTC Div 16 */
+  CLK_RTCCLKDiv_32 = (uint8_t)0xA0, /*!< Clock RTC  Div 32 */
+  CLK_RTCCLKDiv_64 = (uint8_t)0xC0  /*!< Clock RTC  Div 64 */
+} CLK_RTCCLKDiv_TypeDef;
+
+#define IS_CLK_CLOCK_RTC_DIV(DIV) (((DIV) == CLK_RTCCLKDiv_1)  ||\
+                                   ((DIV) == CLK_RTCCLKDiv_2)  ||\
+                                   ((DIV) == CLK_RTCCLKDiv_4)  ||\
+                                   ((DIV) == CLK_RTCCLKDiv_8)  ||\
+                                   ((DIV) == CLK_RTCCLKDiv_16) ||\
+                                   ((DIV) == CLK_RTCCLKDiv_32) ||\
+                                   ((DIV) == CLK_RTCCLKDiv_64))
+/**
+  * @}
+  */
+  
+/** @defgroup CLK_Peripherals
+  * @{
+  */
+/* Elements values convention: 0xXY
+        X = choice between the peripheral registers
+        X = 0 : PCKENR1
+        X = 1 : PCKENR2
+        X = 2 : PCKENR3
+        Y = Peripheral position in the register
+  */        
+typedef enum {
+  CLK_Peripheral_TIM2    = (uint8_t)0x00, /*!< Peripheral Clock Enable 1, TIM2 */
+  CLK_Peripheral_TIM3    = (uint8_t)0x01, /*!< Peripheral Clock Enable 1, TIM3 */
+  CLK_Peripheral_TIM4    = (uint8_t)0x02, /*!< Peripheral Clock Enable 1, TIM4 */
+  CLK_Peripheral_I2C1    = (uint8_t)0x03, /*!< Peripheral Clock Enable 1, I2C1 */
+  CLK_Peripheral_SPI1    = (uint8_t)0x04, /*!< Peripheral Clock Enable 1, SPI1 */
+  CLK_Peripheral_USART1  = (uint8_t)0x05, /*!< Peripheral Clock Enable 1, USART1 */
+  CLK_Peripheral_BEEP    = (uint8_t)0x06, /*!< Peripheral Clock Enable 1, BEEP */
+  CLK_Peripheral_DAC     = (uint8_t)0x07, /*!< Peripheral Clock Enable 1, DAC */
+  CLK_Peripheral_ADC1    = (uint8_t)0x10, /*!< Peripheral Clock Enable 2, ADC1 */
+  CLK_Peripheral_TIM1    = (uint8_t)0x11, /*!< Peripheral Clock Enable 2, TIM1 */
+  CLK_Peripheral_RTC     = (uint8_t)0x12, /*!< Peripheral Clock Enable 2, RTC */
+  CLK_Peripheral_LCD     = (uint8_t)0x13, /*!< Peripheral Clock Enable 2, LCD */
+  CLK_Peripheral_DMA1    = (uint8_t)0x14, /*!< Peripheral Clock Enable 2, DMA1 */
+  CLK_Peripheral_COMP    = (uint8_t)0x15, /*!< Peripheral Clock Enable 2, COMP1 and COMP2 */
+  CLK_Peripheral_BOOTROM = (uint8_t)0x17,/*!< Peripheral Clock Enable 2, Boot ROM */
+  CLK_Peripheral_AES     = (uint8_t)0x20, /*!< Peripheral Clock Enable 3, AES */
+  CLK_Peripheral_TIM5    = (uint8_t)0x21, /*!< Peripheral Clock Enable 3, TIM5 */
+  CLK_Peripheral_SPI2    = (uint8_t)0x22, /*!< Peripheral Clock Enable 3, SPI2 */
+  CLK_Peripheral_USART2  = (uint8_t)0x23, /*!< Peripheral Clock Enable 3, USART2 */
+  CLK_Peripheral_USART3  = (uint8_t)0x24,  /*!< Peripheral Clock Enable 3, USART3 */
+  CLK_Peripheral_CSSLSE  = (uint8_t)0x25   /*!< Peripheral Clock Enable 3, CSS on LSE */
+} CLK_Peripheral_TypeDef;
+
+#define IS_CLK_PERIPHERAL(PERIPHERAL) (((PERIPHERAL) == CLK_Peripheral_DAC)     ||\
+                                       ((PERIPHERAL) == CLK_Peripheral_ADC1)    ||\
+                                       ((PERIPHERAL) == CLK_Peripheral_DMA1)    ||\
+                                       ((PERIPHERAL) == CLK_Peripheral_RTC)     ||\
+                                       ((PERIPHERAL) == CLK_Peripheral_LCD)     ||\
+                                       ((PERIPHERAL) == CLK_Peripheral_COMP)    ||\
+                                       ((PERIPHERAL) == CLK_Peripheral_TIM1)    ||\
+                                       ((PERIPHERAL) == CLK_Peripheral_USART1)  ||\
+                                       ((PERIPHERAL) == CLK_Peripheral_SPI1)    ||\
+                                       ((PERIPHERAL) == CLK_Peripheral_I2C1)    ||\
+                                       ((PERIPHERAL) == CLK_Peripheral_TIM4)    ||\
+                                       ((PERIPHERAL) == CLK_Peripheral_TIM3)    ||\
+                                       ((PERIPHERAL) == CLK_Peripheral_BEEP)    ||\
+                                       ((PERIPHERAL) == CLK_Peripheral_BOOTROM) ||\
+                                       ((PERIPHERAL) == CLK_Peripheral_AES)     ||\
+                                       ((PERIPHERAL) == CLK_Peripheral_TIM5)    ||\
+                                       ((PERIPHERAL) == CLK_Peripheral_SPI2)    ||\
+                                       ((PERIPHERAL) == CLK_Peripheral_USART2)  ||\
+                                       ((PERIPHERAL) == CLK_Peripheral_USART3)  ||\
+                                       ((PERIPHERAL) == CLK_Peripheral_CSSLSE)  ||\
+                                       ((PERIPHERAL) == CLK_Peripheral_TIM2))
+/**
+  * @}
+  */
+     
+/** @defgroup CLK_System_Clock_Divider
+  * @{
+  */
+typedef enum {
+  CLK_SYSCLKDiv_1   = (uint8_t)0x00, /*!< System Clock Divider: 1 */
+  CLK_SYSCLKDiv_2   = (uint8_t)0x01, /*!< System Clock Divider: 2 */
+  CLK_SYSCLKDiv_4   = (uint8_t)0x02, /*!< System Clock Divider: 4 */
+  CLK_SYSCLKDiv_8   = (uint8_t)0x03, /*!< System Clock Divider: 8 */
+  CLK_SYSCLKDiv_16  = (uint8_t)0x04, /*!< System Clock Divider: 16 */
+  CLK_SYSCLKDiv_32  = (uint8_t)0x05, /*!< System Clock Divider: 32 */
+  CLK_SYSCLKDiv_64  = (uint8_t)0x06, /*!< System Clock Divider: 64 */
+  CLK_SYSCLKDiv_128 = (uint8_t)0x07  /*!< System Clock Divider: 128 */
+} CLK_SYSCLKDiv_TypeDef;
+
+#define IS_CLK_SYSTEM_DIVIDER(DIV) (((DIV) == CLK_SYSCLKDiv_1) ||\
+                                    ((DIV) == CLK_SYSCLKDiv_2) ||\
+                                    ((DIV) == CLK_SYSCLKDiv_4) ||\
+                                    ((DIV) == CLK_SYSCLKDiv_8) ||\
+                                    ((DIV) == CLK_SYSCLKDiv_16) ||\
+                                    ((DIV) == CLK_SYSCLKDiv_32) ||\
+                                    ((DIV) == CLK_SYSCLKDiv_64) ||\
+                                    ((DIV) == CLK_SYSCLKDiv_128))
+/**
+  * @}
+  */
+        
+/** @defgroup CLK_Flags
+  * @{
+  */
+/* Elements values convention: 0xXY
+    X = choice between the register's flags
+       X = 0 : CLK_CRTCR
+       X = 1 : CLK_ICKCR
+       X = 2 : CLK_CCOR
+       X = 3 : CLK_ECKCR
+       X = 4 : CLK_SWCR
+       X = 5 : CLK_CSSR
+       X = 6 : CLK_CBEEPR
+       X = 7 : CLK_REGCSRR
+       X = 8 : CSSLSE_CSR
+  Y = flag position in the register
+*/
+typedef enum {
+  CLK_FLAG_RTCSWBSY    = (uint8_t)0x00, /*!< RTC clock busy in switch Flag */
+  CLK_FLAG_HSIRDY      = (uint8_t)0x11, /*!< High speed internal oscillator ready Flag */
+  CLK_FLAG_LSIRDY      = (uint8_t)0x13, /*!< Low speed internal oscillator ready Flag */
+  CLK_FLAG_CCOBSY      = (uint8_t)0x20, /*!< Configurable clock output busy */
+  CLK_FLAG_HSERDY      = (uint8_t)0x31, /*!< High speed external oscillator ready Flag */
+  CLK_FLAG_LSERDY      = (uint8_t)0x33, /*!< Low speed external oscillator ready Flag */
+  CLK_FLAG_SWBSY       = (uint8_t)0x40, /*!< Switch busy Flag */
+  CLK_FLAG_AUX         = (uint8_t)0x51, /*!< Auxiliary oscillator connected to master clock */
+  CLK_FLAG_CSSD        = (uint8_t)0x53, /*!< Clock security system detection Flag */
+  CLK_FLAG_BEEPSWBSY   = (uint8_t)0x60, /*!< BEEP clock busy in switch Flag*/
+  CLK_FLAG_EEREADY     = (uint8_t)0x77, /*!< Flash program memory and Data EEPROM ready Flag */
+  CLK_FLAG_EEBUSY      = (uint8_t)0x76, /*!< Flash program memory and Data EEPROM busy Flag */
+  CLK_FLAG_LSEPD       = (uint8_t)0x75, /*!< LSE power-down Flag */
+  CLK_FLAG_HSEPD       = (uint8_t)0x74, /*!< HSE power-down Flag */
+  CLK_FLAG_LSIPD       = (uint8_t)0x73, /*!< LSI power-down Flag */
+  CLK_FLAG_HSIPD       = (uint8_t)0x72, /*!< HSI power-down Flag */
+  CLK_FLAG_REGREADY    = (uint8_t)0x70,  /*!< REGREADY Flag */
+  CLK_FLAG_LSECSSF     = (uint8_t)0x83,  /*!< CSS on LSE detection Flag */
+  CLK_FLAG_RTCCLKSWF   = (uint8_t)0x84   /*!< RTCCLK switch completed flag on LSE failure */
+}CLK_FLAG_TypeDef;
+
+#define IS_CLK_FLAGS(FLAG) (((FLAG) == CLK_FLAG_LSIRDY) ||\
+                            ((FLAG) == CLK_FLAG_HSIRDY) ||\
+                            ((FLAG) == CLK_FLAG_HSERDY) ||\
+                            ((FLAG) == CLK_FLAG_SWBSY) ||\
+                            ((FLAG) == CLK_FLAG_CSSD) ||\
+                            ((FLAG) == CLK_FLAG_AUX) ||\
+                            ((FLAG) == CLK_FLAG_LSERDY) ||\
+                            ((FLAG) == CLK_FLAG_CCOBSY) ||\
+                            ((FLAG) == CLK_FLAG_RTCSWBSY) ||\
+                            ((FLAG) == CLK_FLAG_EEREADY) ||\
+                            ((FLAG) == CLK_FLAG_EEBUSY) ||\
+                            ((FLAG) == CLK_FLAG_LSEPD) ||\
+                            ((FLAG) == CLK_FLAG_LSIPD) ||\
+                            ((FLAG) == CLK_FLAG_HSEPD) ||\
+                            ((FLAG) == CLK_FLAG_HSIPD) ||\
+                            ((FLAG) == CLK_FLAG_REGREADY) ||\
+                            ((FLAG) == CLK_FLAG_BEEPSWBSY)||\
+                            ((FLAG) == CLK_FLAG_LSECSSF)||\
+                            ((FLAG) == CLK_FLAG_RTCCLKSWF))
+/**
+  * @}
+  */
+
+/** @defgroup CLK_Interrupts
+  * @{
+  */
+typedef enum {
+  CLK_IT_CSSD     = (uint8_t)0x0C,  /*!< Clock security system detection Flag */
+  CLK_IT_SWIF     = (uint8_t)0x1C,  /*!< Clock switch interrupt Flag */
+  CLK_IT_LSECSSF  = (uint8_t)0x2C   /*!< LSE Clock security system detection Interrupt */
+}CLK_IT_TypeDef;
+#define IS_CLK_IT(IT) (((IT) == CLK_IT_CSSD) ||\
+                       ((IT) == CLK_IT_SWIF) ||\
+                       ((IT) == CLK_IT_LSECSSF))
+                       
+#define IS_CLK_CLEAR_IT(IT) (((IT) == CLK_IT_SWIF)||\
+                             ((IT) == CLK_IT_LSECSSF))
+/**
+  * @}
+  */
+
+/** @defgroup CLK_Halt_Configuration
+  * @{
+  */
+typedef enum {
+  CLK_Halt_BEEPRunning = (uint8_t)0x40, /*!< BEEP clock Halt/Active-halt mode */
+  CLK_Halt_FastWakeup  = (uint8_t)0x20, /*!< Fast wakeup from Halt/Active-halt modes */
+  CLK_Halt_SlowWakeup  = (uint8_t)0x10  /*!< Slow Active-halt mode */
+}
+CLK_Halt_TypeDef;
+
+#define IS_CLK_HALT(HALT) (((HALT) == CLK_Halt_BEEPRunning) ||\
+                           ((HALT) == CLK_Halt_FastWakeup) ||\
+                           ((HALT) == CLK_Halt_SlowWakeup))
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+    
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/* Function used to set the CLK configuration to the default reset state ******/
+void CLK_DeInit(void);
+
+/* Internal/external clocks, CSS and CCO configuration functions **************/
+void CLK_HSICmd(FunctionalState NewState);
+void CLK_AdjustHSICalibrationValue(uint8_t CLK_HSICalibrationValue);
+void CLK_LSICmd(FunctionalState NewState);
+void CLK_HSEConfig(CLK_HSE_TypeDef CLK_HSE);
+void CLK_LSEConfig(CLK_LSE_TypeDef CLK_LSE);
+void CLK_ClockSecuritySystemEnable(void);
+void CLK_ClockSecuritySytemDeglitchCmd(FunctionalState NewState);
+void CLK_CCOConfig(CLK_CCOSource_TypeDef CLK_CCOSource, CLK_CCODiv_TypeDef CLK_CCODiv);
+
+/* System clocks configuration functions ******************/
+void CLK_SYSCLKSourceConfig(CLK_SYSCLKSource_TypeDef CLK_SYSCLKSource);
+CLK_SYSCLKSource_TypeDef CLK_GetSYSCLKSource(void);
+uint32_t CLK_GetClockFreq(void);
+void CLK_SYSCLKDivConfig(CLK_SYSCLKDiv_TypeDef CLK_SYSCLKDiv);
+void CLK_SYSCLKSourceSwitchCmd(FunctionalState NewState);
+
+/* Peripheral clocks configuration functions **********************************/
+void CLK_RTCClockConfig(CLK_RTCCLKSource_TypeDef CLK_RTCCLKSource, CLK_RTCCLKDiv_TypeDef CLK_RTCCLKDiv);
+void CLK_BEEPClockConfig(CLK_BEEPCLKSource_TypeDef CLK_BEEPCLKSource);
+void CLK_PeripheralClockConfig(CLK_Peripheral_TypeDef CLK_Peripheral, FunctionalState NewState);
+
+/* CSS on LSE configuration functions *****************************************/
+void CLK_LSEClockSecuritySystemEnable(void);
+void CLK_RTCCLKSwitchOnLSEFailureEnable(void);
+
+/* Low power clock configuration functions ************************************/
+void CLK_HaltConfig(CLK_Halt_TypeDef CLK_Halt, FunctionalState NewState);
+void CLK_MainRegulatorCmd(FunctionalState NewState);
+
+/* Interrupts and flags management functions **********************************/
+void CLK_ITConfig(CLK_IT_TypeDef CLK_IT, FunctionalState NewState);
+FlagStatus CLK_GetFlagStatus(CLK_FLAG_TypeDef CLK_FLAG);
+void CLK_ClearFlag(void);
+ITStatus CLK_GetITStatus(CLK_IT_TypeDef CLK_IT);
+void CLK_ClearITPendingBit(CLK_IT_TypeDef CLK_IT);
+
+
+#endif /* __STM8L15x_CLK_H */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_comp.h b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_comp.h
new file mode 100755
index 0000000..cd442f2
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_comp.h
@@ -0,0 +1,239 @@
+/**
+  ******************************************************************************
+  * @file    stm8l15x_comp.h
+  * @author  MCD Application Team
+  * @version V1.6.0
+  * @date    28-June-2013
+  * @brief   This file contains all the functions prototypes for the COMP firmware
+  *          library.
+  ******************************************************************************
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ****************************************************************************** 
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM8L15x_COMP_H
+#define __STM8L15x_COMP_H
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm8l15x.h"
+
+/** @addtogroup STM8L15x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup COMP
+  * @{
+  */ 
+  
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup COMP_Exported_Types
+  * @{
+  */
+
+/** @defgroup COMP_Selection
+  * @{
+  */
+typedef enum
+{
+  COMP_Selection_COMP1 = ((uint8_t)0x01), /*!< Selection of Comparator 1. */
+  COMP_Selection_COMP2 = ((uint8_t)0x02)  /*!< Selection of Comparator 2. */
+}COMP_Selection_TypeDef;
+
+#define IS_COMP_ALL_PERIPH(PERIPH) (((PERIPH) == COMP_Selection_COMP1) || \
+                                    ((PERIPH) == COMP_Selection_COMP2))
+/**
+  * @}
+  */
+  
+/** @defgroup COMP_Edge
+  * @{
+  */
+typedef enum
+{
+  COMP_Edge_Falling         = ((uint8_t)0x01), /*!< Falling edge selection. */
+  COMP_Edge_Rising          = ((uint8_t)0x02), /*!< Rising edge selection. */
+  COMP_Edge_Rising_Falling  = ((uint8_t)0x03)  /*!< Rising and Falling edge selection. */
+}COMP_Edge_TypeDef;
+
+#define IS_COMP_EDGE(EDGE) (((EDGE) == COMP_Edge_Falling) || \
+                            ((EDGE) == COMP_Edge_Rising)  || \
+                            ((EDGE) == COMP_Edge_Rising_Falling))
+/**
+  * @}
+  */
+  
+/** @defgroup COMP_Inverting_Input_Selection
+  * @{
+  */
+typedef enum
+{
+  COMP_InvertingInput_IO         = ((uint8_t)0x08), /*!< Input/Output on comparator inverting input enable.*/
+  COMP_InvertingInput_VREFINT    = ((uint8_t)0x10), /*!< VREFINT on comparator inverting input enable.     */
+  COMP_InvertingInput_3_4VREFINT = ((uint8_t)0x18), /*!< 3/4 VREFINT on comparator inverting input enable. */
+  COMP_InvertingInput_1_2VREFINT = ((uint8_t)0x20), /*!< 1/2 VREFINT on comparator inverting input enable. */
+  COMP_InvertingInput_1_4VREFINT = ((uint8_t)0x28), /*!< 1/4 VREFINT on comparator inverting input enable. */
+  COMP_InvertingInput_DAC1       = ((uint8_t)0x30),  /*!< DAC1 output on comparator inverting input enable.  */
+  COMP_InvertingInput_DAC2       = ((uint8_t)0x38)  /*!< DAC2 output on comparator inverting input enable.  */
+}COMP_InvertingInput_Typedef;
+
+#define IS_COMP_INVERTING_INPUT(INPUT) (((INPUT) == COMP_InvertingInput_IO) || \
+                                        ((INPUT) == COMP_InvertingInput_VREFINT) || \
+                                        ((INPUT) == COMP_InvertingInput_3_4VREFINT) || \
+                                        ((INPUT) == COMP_InvertingInput_1_2VREFINT) || \
+                                        ((INPUT) == COMP_InvertingInput_1_4VREFINT) || \
+                                        ((INPUT) == COMP_InvertingInput_DAC1) || \
+                                        ((INPUT) == COMP_InvertingInput_DAC2))
+/**
+  * @}
+  */
+  
+/** @defgroup COMP2_Output_Selection
+  * @{
+  */
+typedef enum
+{
+  COMP_OutputSelect_TIM2IC2       = ((uint8_t)0x00), /*!< COMP2 output connected to TIM2 Input Capture 2 */
+  COMP_OutputSelect_TIM3IC2       = ((uint8_t)0x40), /*!< COMP2 output connected to TIM3 Input Capture 2 */
+  COMP_OutputSelect_TIM1BRK       = ((uint8_t)0x80), /*!< COMP2 output connected to TIM1 Break Input     */
+  COMP_OutputSelect_TIM1OCREFCLR  = ((uint8_t)0xC0)  /*!< COMP2 output connected to TIM1 OCREF Clear     */
+}COMP_OutputSelect_Typedef;
+
+#define IS_COMP_OUTPUT(OUTPUT) (((OUTPUT) == COMP_OutputSelect_TIM2IC2) || \
+                                ((OUTPUT) == COMP_OutputSelect_TIM3IC2) || \
+                                ((OUTPUT) == COMP_OutputSelect_TIM1BRK) || \
+                                ((OUTPUT) == COMP_OutputSelect_TIM1OCREFCLR))
+/**
+  * @}
+  */
+  
+/** @defgroup COMP_Speed
+  * @{
+  */
+typedef enum
+{
+  COMP_Speed_Slow  = ((uint8_t)0x00), /*!< Comparator speed: slow */
+  COMP_Speed_Fast  = ((uint8_t)0x04)  /*!< Comparator speed: fast */
+}COMP_Speed_TypeDef;
+
+#define IS_COMP_SPEED(SPEED) (((SPEED) == COMP_Speed_Slow) || \
+                              ((SPEED) == COMP_Speed_Fast))
+/**
+  * @}
+  */
+  
+/** @defgroup COMP_Trigger_Group
+  * @{
+  */
+typedef enum
+{
+  COMP_TriggerGroup_InvertingInput     = ((uint8_t)0x01), /*!< Trigger on comparator 2 inverting input */
+  COMP_TriggerGroup_NonInvertingInput  = ((uint8_t)0x02), /*!< Trigger on comparator 2 non inverting input */
+  COMP_TriggerGroup_VREFINTOutput      = ((uint8_t)0x03), /*!< Trigger on VREFINT output */
+  COMP_TriggerGroup_DACOutput          = ((uint8_t)0x04)  /*!< Trigger on DAC output */
+}COMP_TriggerGroup_TypeDef;
+
+#define IS_COMP_TRIGGERGROUP(TRIGGERGROUP) (((TRIGGERGROUP) == COMP_TriggerGroup_NonInvertingInput) || \
+                                            ((TRIGGERGROUP) == COMP_TriggerGroup_InvertingInput) || \
+                                            ((TRIGGERGROUP) == COMP_TriggerGroup_VREFINTOutput) || \
+                                            ((TRIGGERGROUP) == COMP_TriggerGroup_DACOutput)
+/**
+  * @}
+  */
+  
+/** @defgroup COMP_Trigger_Pin
+  * @{
+  */
+typedef enum
+{
+  COMP_TriggerPin_0 = ((uint8_t)0x01), /*!< PE5 for the non inverting input Trigger Group
+                                                PC3 for the inverting input Trigger Group
+                                                PB6 for the DAC output Trigger Group
+                                                PC2 for the VREFINT output Trigger Group
+                                              */
+  COMP_TriggerPin_1 = ((uint8_t)0x02), /*!< PD0 for the non inverting input Trigger Group
+                                                PC4 for the inverting input Trigger Group
+                                                PB5 for the DAC output Trigger Group
+                                                PD7 for the VREFINT output Trigger Group
+                                              */
+  COMP_TriggerPin_2 = ((uint8_t)0x04)  /*!< PD1 for the non inverting input Trigger Group
+                                            PC7 for the inverting input Trigger Group
+                                            PB4 for the DAC output Trigger Group
+                                            PD6 for the VREFINT output Trigger Group */
+}COMP_TriggerPin_TypeDef;
+
+#define IS_COMP_TRIGGERPIN(TRIGGERPIN)  ((((uint8_t)(TRIGGERPIN) & (uint8_t)0xF8) == (uint8_t) 0x00) && \
+                                         ((TRIGGERPIN) != (uint8_t)0x00))
+/**
+  * @}
+  */
+  
+/** @defgroup COMP_Output_Level
+  * @{
+  */
+typedef enum
+{
+  COMP_OutputLevel_Low   = ((uint8_t)0x00), /*!< Comparator output level is low */
+  COMP_OutputLevel_High  = ((uint8_t)0x01)  /*!< Comparator output level is high */
+}COMP_OutputLevel_TypeDef;
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/* Function used to set the CLK configuration to the default reset state ******/
+void COMP_DeInit(void);
+/* Initialization and Configuration functions ****************************/
+void COMP_Init(COMP_InvertingInput_Typedef COMP_InvertingInput, COMP_OutputSelect_Typedef COMP_OutputSelect,
+               COMP_Speed_TypeDef COMP_Speed);
+void COMP_VrefintToCOMP1Connect(FunctionalState NewState);
+void COMP_EdgeConfig(COMP_Selection_TypeDef COMP_Selection, COMP_Edge_TypeDef COMP_Edge);
+COMP_OutputLevel_TypeDef COMP_GetOutputLevel(COMP_Selection_TypeDef COMP_Selection);
+/* Window mode control function ***********************************************/
+void COMP_WindowCmd(FunctionalState NewState);
+/* Internal Reference Voltage (VREFINT) output function ***********************/
+void COMP_VrefintOutputCmd(FunctionalState NewState);
+/* Comparator channels trigger configuration functions ************************/
+void COMP_SchmittTriggerCmd(FunctionalState NewState);
+void COMP_TriggerConfig(COMP_TriggerGroup_TypeDef COMP_TriggerGroup,
+                        COMP_TriggerPin_TypeDef COMP_TriggerPin,
+                        FunctionalState NewState);
+/* Interrupts and flags management functions **********************************/
+void COMP_ITConfig(COMP_Selection_TypeDef COMP_Selection, FunctionalState NewState);
+FlagStatus COMP_GetFlagStatus(COMP_Selection_TypeDef COMP_Selection);
+void COMP_ClearFlag(COMP_Selection_TypeDef COMP_Selection);
+ITStatus COMP_GetITStatus(COMP_Selection_TypeDef COMP_Selection);
+void COMP_ClearITPendingBit(COMP_Selection_TypeDef COMP_Selection);
+
+/**
+  * @}
+  */
+
+#endif /* __STM8L15x_COMP_H */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_dac.h b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_dac.h
new file mode 100755
index 0000000..26b54c5
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_dac.h
@@ -0,0 +1,290 @@
+/**
+  ******************************************************************************
+  * @file    stm8l15x_dac.h
+  * @author  MCD Application Team
+  * @version V1.6.0
+  * @date    28-June-2013
+  * @brief   This file contains all the functions prototypes for the DAC firmware
+  *          library.
+  ******************************************************************************
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ****************************************************************************** 
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM8L15x_DAC_H
+#define __STM8L15x_DAC_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm8l15x.h"
+
+/** @addtogroup STM8L15x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup DAC
+  * @{
+  */
+  
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup DAC_Exported_types
+  * @{
+  */
+  
+/** @defgroup DAC_trigger_selection 
+  * @{
+  */
+typedef enum
+{
+  DAC_Trigger_None     = ((uint8_t)0x30), /*!< DAC trigger None  */
+  DAC_Trigger_T4_TRGO  = ((uint8_t)0x00), /*!< DAC trigger TIM4 TRGO  */
+  DAC_Trigger_T5_TRGO  = ((uint8_t)0x08), /*!< DAC trigger TIM5 TRGO  */
+  DAC_Trigger_Ext      = ((uint8_t)0x10), /*!< DAC trigger External Trigger (PE4) */
+  DAC_Trigger_Software = ((uint8_t)0x38)  /*!< DAC trigger software  */
+}DAC_Trigger_TypeDef;
+
+#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \
+                                 ((TRIGGER) == DAC_Trigger_T4_TRGO) || \
+                                 ((TRIGGER) == DAC_Trigger_T5_TRGO) || \
+                                 ((TRIGGER) == DAC_Trigger_Ext) || \
+                                 ((TRIGGER) == DAC_Trigger_Software))
+/**
+  * @}
+  */
+
+/** @defgroup DAC_data_alignment 
+  * @{
+  */
+typedef enum
+{
+  DAC_Align_12b_R = ((uint8_t)0x00), /*!< DAC alignment  Right 12bit */
+  DAC_Align_12b_L = ((uint8_t)0x04), /*!< DAC alignment  Left 12bit */
+  DAC_Align_8b_R  = ((uint8_t)0x08)  /*!< DAC alignment  Right 8bit */
+}DAC_Align_TypeDef;
+
+#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \
+                             ((ALIGN) == DAC_Align_12b_L) || \
+                             ((ALIGN) == DAC_Align_8b_R))
+/**
+  * @}
+  */
+  
+/** @defgroup DAC_Channel_selection 
+  * @{
+  */
+typedef enum
+{
+  DAC_Channel_1 = ((uint8_t)0x00), /*!< DAC Channel 1 selection  */
+  DAC_Channel_2 = ((uint8_t)0x01)  /*!< DAC Channel 2 selection  */
+}DAC_Channel_TypeDef;
+
+#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \
+                                 ((CHANNEL) == DAC_Channel_2))
+                                 
+/**
+  * @}
+  */
+  
+/** @defgroup DAC_wave_generation 
+  * @{
+  */
+
+typedef enum
+{
+  DAC_Wave_Noise    = ((uint8_t)0x40), /*!< Noise Wave Generation  */
+  DAC_Wave_Triangle = ((uint8_t)0x80)  /*!< Triangle Wave Generation */
+}DAC_Wave_TypeDef;
+
+#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \
+                           ((WAVE) == DAC_Wave_Triangle))
+/**
+  * @}
+  */
+  
+/** @defgroup DAC_output_buffer 
+  * @{
+  */
+typedef enum
+{
+  DAC_OutputBuffer_Enable  = ((uint8_t)0x00), /*!< DAC output buffer Enabled  */
+  DAC_OutputBuffer_Disable = ((uint8_t)0x02)  /*!< DAC output buffer Disabled  */
+}DAC_OutputBuffer_TypeDef;
+
+#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \
+                                           ((STATE) == DAC_OutputBuffer_Disable))
+/**
+  * @}
+  */
+  
+/** @defgroup DAC_interrupts_definition 
+  * @{
+  */
+typedef enum
+{
+  DAC_IT_DMAUDR = ((uint8_t)0x20) /*!< DMA Underrun Interrupt */
+}DAC_IT_TypeDef;
+
+#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR))
+/**
+  * @}
+  */
+  
+/** @defgroup DAC_flags_definition 
+  * @{
+  */ 
+typedef enum
+{
+  DAC_FLAG_DMAUDR = ((uint8_t)0x01) /*!< DMA Underrun flag  */
+}DAC_FLAG_TypeDef;
+
+#define IS_DAC_GET_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR))
+#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR))
+
+/**
+  * @}
+  */
+  
+/** @defgroup DAC_lfsrunmask
+  * @{
+  */
+  
+typedef enum
+{
+  DAC_LFSRUnmask_Bit0       =  ((uint8_t)0x00), /*!<  Noise LFSR Unmask 1 LSB */
+  DAC_LFSRUnmask_Bits1_0    =  ((uint8_t)0x01), /*!<  Noise LFSR Unmask 2 LSB */
+  DAC_LFSRUnmask_Bits2_0    =  ((uint8_t)0x02), /*!<  Noise LFSR Unmask 3 LSB */
+  DAC_LFSRUnmask_Bits3_0    =  ((uint8_t)0x03), /*!<  Noise LFSR Unmask 4 LSB */
+  DAC_LFSRUnmask_Bits4_0    =  ((uint8_t)0x04), /*!<  Noise LFSR Unmask 5 LSB */
+  DAC_LFSRUnmask_Bits5_0    =  ((uint8_t)0x05), /*!<  Noise LFSR Unmask 6 LSB */
+  DAC_LFSRUnmask_Bits6_0    =  ((uint8_t)0x06), /*!<  Noise LFSR Unmask 7 LSB */
+  DAC_LFSRUnmask_Bits7_0    =  ((uint8_t)0x07), /*!<  Noise LFSR Unmask 8 LSB */
+  DAC_LFSRUnmask_Bits8_0    =  ((uint8_t)0x08), /*!<  Noise LFSR Unmask 9 LSB */
+  DAC_LFSRUnmask_Bits9_0    =  ((uint8_t)0x09), /*!<  Noise LFSR Unmask 10 LSB */
+  DAC_LFSRUnmask_Bits10_0   =  ((uint8_t)0x0A), /*!<  Noise LFSR Unmask 11 LSB */
+  DAC_LFSRUnmask_Bits11_0   =  ((uint8_t)0x0B)  /*!<  Noise LFSR Unmask 12 LSB */
+}DAC_LFSRUnmask_TypeDef;
+
+#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) ((VALUE) <= 0x0F)
+/**
+  * @}
+  */
+  
+/** @defgroup DAC_triangleamplitude
+  * @{
+  */
+typedef enum
+{
+  DAC_TriangleAmplitude_1     =  ((uint8_t)0x00), /*!<  Triangle Amplitude = Vref.(1/4096)*/
+  DAC_TriangleAmplitude_3     =  ((uint8_t)0x01), /*!<  Triangle Amplitude = Vref.(3/4096)*/
+  DAC_TriangleAmplitude_7     =  ((uint8_t)0x02), /*!<  Triangle Amplitude = Vref.(7/4096)*/
+  DAC_TriangleAmplitude_15    =  ((uint8_t)0x03), /*!<  Triangle Amplitude = Vref.(15/4096)*/
+  DAC_TriangleAmplitude_31    =  ((uint8_t)0x04), /*!<  Triangle Amplitude = Vref.(31/4096)*/
+  DAC_TriangleAmplitude_63    =  ((uint8_t)0x05), /*!<  Triangle Amplitude = Vref.(63/4096)*/
+  DAC_TriangleAmplitude_127   =  ((uint8_t)0x06), /*!<  Triangle Amplitude = Vref.(127/4096)*/
+  DAC_TriangleAmplitude_255   =  ((uint8_t)0x07), /*!<  Triangle Amplitude = Vref.(255/4096)*/
+  DAC_TriangleAmplitude_511   =  ((uint8_t)0x08), /*!<  Triangle Amplitude = Vref.(511/4096)*/
+  DAC_TriangleAmplitude_1023  =  ((uint8_t)0x09), /*!<  Triangle Amplitude = Vref.(1023/4096)*/
+  DAC_TriangleAmplitude_2047  =  ((uint8_t)0x0A), /*!<  Triangle Amplitude = Vref.(2047/4096)*/
+  DAC_TriangleAmplitude_4095  =  ((uint8_t)0x0B)  /*!<  Triangle Amplitude = Vref.(4095/4096)*/
+}DAC_TriangleAmplitude_TypeDef;
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup DAC_Exported_Constants
+  * @{
+  */
+
+/** @defgroup DAC_data 
+  * @{
+  */
+#define IS_DAC_DATA_08R(DATA) ((DATA) <= 0x00FF) 
+
+/**
+  * @}
+  */
+/** @defgroup DAC_Registers_Offset 
+  * @{
+  */  
+#define CR1_Offset         ((uint8_t)0x00)
+#define CR2_Offset         ((uint8_t)0x01)
+#define DCH1RDHRH_Offset   ((uint8_t)0x20)
+#define CH1RDHRH_Offset    ((uint8_t)0x08)
+#define CH2RDHRH_Offset    ((uint8_t)0x14)
+/**
+  * @}
+  */
+
+/** @defgroup DAC_legacy 
+  * @{
+  */
+#define DAC_TriangleWaveAmplitude  DAC_SetTriangleWaveAmplitude
+#define DAC_NoiseWaveLFSR  DAC_SetNoiseWaveLFSR 
+
+/**
+  * @}
+  */
+     
+/**
+  * @}
+  */ 
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */ 
+
+/*  Function used to set the DAC configuration to the default reset state *****/  
+void DAC_DeInit(void);
+
+/*  DAC channels configuration: trigger, output buffer, data format functions */
+void DAC_Init(DAC_Channel_TypeDef DAC_Channel,
+              DAC_Trigger_TypeDef DAC_Trigger,
+              DAC_OutputBuffer_TypeDef DAC_OutputBuffer);
+void DAC_Cmd(DAC_Channel_TypeDef DAC_Channel, FunctionalState NewState);
+void DAC_SoftwareTriggerCmd(DAC_Channel_TypeDef DAC_Channel, FunctionalState NewState);
+void DAC_DualSoftwareTriggerCmd(FunctionalState NewState);
+void DAC_WaveGenerationCmd(DAC_Channel_TypeDef DAC_Channel, DAC_Wave_TypeDef DAC_Wave, FunctionalState NewState);
+void DAC_SetNoiseWaveLFSR(DAC_Channel_TypeDef DAC_Channel, DAC_LFSRUnmask_TypeDef DAC_LFSRUnmask);
+void DAC_SetTriangleWaveAmplitude(DAC_Channel_TypeDef DAC_Channel, DAC_TriangleAmplitude_TypeDef DAC_TriangleAmplitude);
+void DAC_SetChannel1Data(DAC_Align_TypeDef DAC_Align, uint16_t DAC_Data);
+void DAC_SetChannel2Data(DAC_Align_TypeDef DAC_Align, uint16_t DAC_Data);
+void DAC_SetDualChannelData(DAC_Align_TypeDef DAC_Align, uint16_t DAC_Data2, uint16_t DAC_Data1);
+uint16_t DAC_GetDataOutputValue(DAC_Channel_TypeDef DAC_Channel);
+
+/* DMA management function ***************************************************/                            
+void DAC_DMACmd(DAC_Channel_TypeDef DAC_Channel, FunctionalState NewState);
+
+/* Interrupts and flags management functions **********************************/
+void DAC_ITConfig(DAC_Channel_TypeDef DAC_Channel, DAC_IT_TypeDef DAC_IT, FunctionalState NewState);
+FlagStatus DAC_GetFlagStatus(DAC_Channel_TypeDef DAC_Channel, DAC_FLAG_TypeDef DAC_FLAG);
+void DAC_ClearFlag(DAC_Channel_TypeDef DAC_Channel, DAC_FLAG_TypeDef DAC_FLAG);
+ITStatus DAC_GetITStatus(DAC_Channel_TypeDef DAC_Channel, DAC_IT_TypeDef DAC_IT);
+void DAC_ClearITPendingBit(DAC_Channel_TypeDef DAC_Channel, DAC_IT_TypeDef DAC_IT);
+
+#endif /*__STM8L15x_DAC_H */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_dma.h b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_dma.h
new file mode 100755
index 0000000..779152d
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_dma.h
@@ -0,0 +1,338 @@
+/**
+  ******************************************************************************
+  * @file    stm8l15x_dma.h
+  * @author  MCD Application Team
+  * @version V1.6.0
+  * @date    28-June-2013
+  * @brief   This file contains all the functions prototypes for the DMA 
+  *          firmware library.
+  ******************************************************************************
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ****************************************************************************** 
+  */
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM8L15x_DMA_H
+ #define __STM8L15x_DMA_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm8l15x.h"
+
+/** @addtogroup STM8L15x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup DMA
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @addtogroup DMA_Exported_Types
+  * @{
+  */
+
+/** @defgroup DMA_Data_Transfer_Direction
+  * @{
+  */
+typedef enum
+{
+  DMA_DIR_PeripheralToMemory  = ((uint8_t)0x00), /*!< Data transfer direction is Peripheral To Memory   */
+  DMA_DIR_MemoryToPeripheral  = ((uint8_t)0x08), /*!< Data transfer direction is Memory To Peripheral */
+  DMA_DIR_Memory0ToMemory1    = ((uint8_t)0x40)  /*!< Data transfer direction is Memory0 To Memory 1 */
+}DMA_DIR_TypeDef;
+
+#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_MemoryToPeripheral) || \
+                         ((DIR) == DMA_DIR_PeripheralToMemory) || \
+                         ((DIR) == DMA_DIR_Memory0ToMemory1 ))
+/**
+  * @}
+  */
+  
+/** @defgroup DMA_Mode
+  * @{
+  */
+typedef enum
+{
+  DMA_Mode_Normal = ((uint8_t)0x00),  /*!< DMA normal buffer mode*/
+  DMA_Mode_Circular = ((uint8_t)0x10) /*!< DMA circular buffer mode */
+}DMA_Mode_TypeDef;
+
+#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || \
+                           ((MODE) == DMA_Mode_Normal))
+/**
+  * @}
+  */
+  
+/** @defgroup DMA_Incremented_Mode
+  * @{
+  */
+typedef enum
+{
+  DMA_MemoryIncMode_Dec = ((uint8_t)0x00), /*!< DMA memory incremented mode is decremental */
+  DMA_MemoryIncMode_Inc = ((uint8_t)0x20)  /*!< DMA memory incremented mode is incremental */
+}DMA_MemoryIncMode_TypeDef;
+
+#define IS_DMA_MEMORY_INC_MODE(MODE) (((MODE) == DMA_MemoryIncMode_Inc) || \
+                                      ((MODE) == DMA_MemoryIncMode_Dec))
+/**
+  * @}
+  */
+  
+/** @defgroup DMA_Priority
+  * @{
+  */
+typedef enum
+{
+  DMA_Priority_Low      = ((uint8_t)0x00), /*!< Software Priority is Low */
+  DMA_Priority_Medium   = ((uint8_t)0x10), /*!< Software Priority is Medium */
+  DMA_Priority_High     = ((uint8_t)0x20), /*!< Software Priority is High */
+  DMA_Priority_VeryHigh = ((uint8_t)0x30)  /*!< Software Priority is Very High*/
+}DMA_Priority_TypeDef;
+
+#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \
+                                   ((PRIORITY) == DMA_Priority_High) || \
+                                   ((PRIORITY) == DMA_Priority_Medium) || \
+                                   ((PRIORITY) == DMA_Priority_Low))
+/**
+  * @}
+  */
+  
+/** @defgroup DMA_Memory_Data_Size
+  * @{
+  */
+typedef enum
+{
+  DMA_MemoryDataSize_Byte     = ((uint8_t)0x00),/*!< Memory Data Size is 1 Byte */
+  DMA_MemoryDataSize_HalfWord = ((uint8_t)0x08) /*!< Memory Data Size is 2 Bytes */
+}DMA_MemoryDataSize_TypeDef;
+
+#define IS_DMA_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \
+                                ((SIZE) == DMA_MemoryDataSize_HalfWord))
+/**
+  * @}
+  */
+  
+/** @defgroup DMA_Flags
+  * @{
+  */
+typedef enum
+{
+  DMA1_FLAG_GB    = ((uint16_t)0x0002), /*!< Global Busy Flag */
+
+  DMA1_FLAG_IFC0  = ((uint16_t)0x1001), /*!< Global Interrupt Flag Channel 0 */
+  DMA1_FLAG_IFC1  = ((uint16_t)0x1002), /*!< Global Interrupt Flag Channel 1 */
+  DMA1_FLAG_IFC2  = ((uint16_t)0x1004), /*!< Global Interrupt Flag Channel 2 */
+  DMA1_FLAG_IFC3  = ((uint16_t)0x1008), /*!< Global Interrupt Flag Channel 3 */
+
+  DMA1_FLAG_TC0   = ((uint16_t)0x0102), /*!< Transaction Complete Interrupt Flag Channel 0 */
+  DMA1_FLAG_TC1   = ((uint16_t)0x0202), /*!< Transaction Complete Interrupt Flag Channel 1 */
+  DMA1_FLAG_TC2   = ((uint16_t)0x0402), /*!< Transaction Complete Interrupt Flag Channel 2 */
+  DMA1_FLAG_TC3   = ((uint16_t)0x0802), /*!< Transaction Complete Interrupt Flag Channel 3 */
+
+  DMA1_FLAG_HT0   = ((uint16_t)0x0104), /*!< Half Transaction Interrupt Flag Channel 0 */
+  DMA1_FLAG_HT1   = ((uint16_t)0x0204), /*!< Half Transaction Interrupt Flag Channel 1 */
+  DMA1_FLAG_HT2   = ((uint16_t)0x0404), /*!< Half Transaction Interrupt Flag Channel 2 */
+  DMA1_FLAG_HT3   = ((uint16_t)0x0804), /*!< Half Transaction Interrupt Flag Channel 3 */
+
+  DMA1_FLAG_PEND0 = ((uint16_t)0x0140), /*!< DMA Request pending on Channel 0 */
+  DMA1_FLAG_PEND1 = ((uint16_t)0x0240), /*!< DMA Request pending on Channel 1 */
+  DMA1_FLAG_PEND2 = ((uint16_t)0x0440), /*!< DMA Request pending on Channel 2 */
+  DMA1_FLAG_PEND3 = ((uint16_t)0x0840), /*!< DMA Request pending on Channel 3 */
+
+  DMA1_FLAG_BUSY0 = ((uint16_t)0x0180), /*!< No DMA transfer on going in Channel 0 */
+  DMA1_FLAG_BUSY1 = ((uint16_t)0x0280), /*!< No DMA transfer on going in Channel 1 */
+  DMA1_FLAG_BUSY2 = ((uint16_t)0x0480), /*!< No DMA transfer on going in Channel 2 */
+  DMA1_FLAG_BUSY3 = ((uint16_t)0x0880)  /*!< No DMA transfer on going in Channel 3 */
+}DMA_FLAG_TypeDef;
+
+#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GB) || \
+                               ((FLAG) == DMA1_FLAG_IFC0) || \
+                               ((FLAG) == DMA1_FLAG_IFC1) || \
+                               ((FLAG) == DMA1_FLAG_IFC2) || \
+                               ((FLAG) == DMA1_FLAG_IFC3) || \
+                               ((FLAG) == DMA1_FLAG_TC0) || \
+                               ((FLAG) == DMA1_FLAG_TC1) || \
+                               ((FLAG) == DMA1_FLAG_TC2) || \
+                               ((FLAG) == DMA1_FLAG_TC3) || \
+                               ((FLAG) == DMA1_FLAG_HT0) || \
+                               ((FLAG) == DMA1_FLAG_HT1) || \
+                               ((FLAG) == DMA1_FLAG_HT2) || \
+                               ((FLAG) == DMA1_FLAG_HT3) || \
+                               ((FLAG) == DMA1_FLAG_PEND0) || \
+                               ((FLAG) == DMA1_FLAG_PEND1) || \
+                               ((FLAG) == DMA1_FLAG_PEND2) || \
+                               ((FLAG) == DMA1_FLAG_PEND3) || \
+                               ((FLAG) == DMA1_FLAG_BUSY0) || \
+                               ((FLAG) == DMA1_FLAG_BUSY1) || \
+                               ((FLAG) == DMA1_FLAG_BUSY2) || \
+                               ((FLAG) == DMA1_FLAG_BUSY3))
+
+#define IS_DMA_CLEAR_FLAG(FLAG) (((FLAG) == DMA1_FLAG_TC0) || \
+                                 ((FLAG) == DMA1_FLAG_TC1) || \
+                                 ((FLAG) == DMA1_FLAG_TC2) || \
+                                 ((FLAG) == DMA1_FLAG_TC3) || \
+                                 ((FLAG) == DMA1_FLAG_HT0) || \
+                                 ((FLAG) == DMA1_FLAG_HT1) || \
+                                 ((FLAG) == DMA1_FLAG_HT2) || \
+                                 ((FLAG) == DMA1_FLAG_HT3) || \
+                                 ((FLAG) == (DMA1_FLAG_TC0 |DMA1_FLAG_HT0)) || \
+                                 ((FLAG) == (DMA1_FLAG_TC1 |DMA1_FLAG_HT1)) || \
+                                 ((FLAG) == (DMA1_FLAG_TC2 |DMA1_FLAG_HT2)) || \
+                                 ((FLAG) == (DMA1_FLAG_TC3 |DMA1_FLAG_HT3)))
+/**
+  * @}
+  */
+  
+/** @defgroup DMA_One_Channel_Interrupts
+  * @{
+  */
+typedef enum
+{
+  DMA_ITx_TC = ((uint8_t)0x02),/*!< Transaction Complete Interrupt  */
+  DMA_ITx_HT = ((uint8_t)0x04) /*!< Half Transaction Interrupt*/
+}DMA_ITx_TypeDef;
+
+#define IS_DMA_CONFIG_ITX(IT) ((((IT) & 0xF9) == 0x00) && ((IT) != 0x00))
+/**
+  * @}
+  */
+  
+/** @defgroup DMA_Interrupts 
+  * @{
+  */
+typedef enum
+{
+  /* Transaction Complete Interrupts*/
+  DMA1_IT_TC0 = ((uint8_t)0x12), /*!< Transaction Complete Interrupt Channel 0 */
+  DMA1_IT_TC1 = ((uint8_t)0x22), /*!< Transaction Complete Interrupt Channel 1 */
+  DMA1_IT_TC2 = ((uint8_t)0x42), /*!< Transaction Complete Interrupt Channel 2 */
+  DMA1_IT_TC3 = ((uint8_t)0x82), /*!< Transaction Complete Interrupt Channel 3 */
+  /* Half Transaction Interrupts */
+  DMA1_IT_HT0 = ((uint8_t)0x14), /*!< Half Transaction Interrupt Channel 0 */
+  DMA1_IT_HT1 = ((uint8_t)0x24), /*!< Half Transaction Interrupt Channel 1 */
+  DMA1_IT_HT2 = ((uint8_t)0x44), /*!< Half Transaction Interrupt Channel 2 */
+  DMA1_IT_HT3 = ((uint8_t)0x84)  /*!< Half Transaction Interrupt Channel 3 */
+}DMA_IT_TypeDef;
+
+#define IS_DMA_CLEAR_IT(IT) (((IT) == DMA1_IT_TC0) || \
+                             ((IT) == DMA1_IT_TC1) || \
+                             ((IT) == DMA1_IT_TC2) || \
+                             ((IT) == DMA1_IT_TC3) || \
+                             ((IT) == DMA1_IT_HT0) || \
+                             ((IT) == DMA1_IT_HT1) || \
+                             ((IT) == DMA1_IT_HT2) || \
+                             ((IT) == DMA1_IT_HT3) || \
+                             ((IT) == (DMA1_IT_TC0|DMA1_IT_HT0)) || \
+                             ((IT) == (DMA1_IT_TC1|DMA1_IT_HT1)) || \
+                             ((IT) == (DMA1_IT_TC2|DMA1_IT_HT2)) || \
+                             ((IT) == (DMA1_IT_TC3|DMA1_IT_HT3)))
+
+#define IS_DMA_GET_IT(IT)(((IT) == DMA1_IT_TC0) || \
+                          ((IT) == DMA1_IT_TC1) || \
+                          ((IT) == DMA1_IT_TC2) || \
+                          ((IT) == DMA1_IT_TC3) || \
+                          ((IT) == DMA1_IT_HT0) || \
+                          ((IT) == DMA1_IT_HT1) || \
+                          ((IT) == DMA1_IT_HT2) || \
+                          ((IT) == DMA1_IT_HT3))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Exported constants --------------------------------------------------------*/    
+/* Exported macro ------------------------------------------------------------*/
+/** @addtogroup DMA_Exported_Macros
+  * @{
+  */
+
+/** @defgroup DMA_Channels
+  * @{
+  */
+#define IS_DMA_CHANNEL(PERIPH) (((*(uint16_t*)&(PERIPH)) == DMA1_Channel0_BASE)  || \
+                                ((*(uint16_t*)&(PERIPH)) == DMA1_Channel1_BASE)  || \
+                                ((*(uint16_t*)&(PERIPH)) == DMA1_Channel2_BASE)  || \
+                                ((*(uint16_t*)&(PERIPH)) == DMA1_Channel3_BASE))
+/**
+  * @}
+  */
+
+
+/** @defgroup DMA_Buffer_Size
+  * @{
+  */
+#define IS_DMA_BUFFER_SIZE(SIZE) ((SIZE) > (uint8_t)0x0)
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Timeout
+  * @{
+  */
+#define IS_DMA_TIMEOUT(TIME) ((TIME) < (uint8_t)0x40)
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+
+/* Exported functions ------------------------------------------------------- */ 
+  
+/*  Functions used to set the DMA configuration to the default reset state ****/ 
+void DMA_GlobalDeInit(void);
+void DMA_DeInit(DMA_Channel_TypeDef* DMA_Channelx);
+
+/* Initialization and Configuration functions *********************************/
+void DMA_Init(DMA_Channel_TypeDef* DMA_Channelx,
+              uint32_t DMA_Memory0BaseAddr,
+              uint16_t DMA_PeripheralMemory1BaseAddr,
+              uint8_t DMA_BufferSize,
+              DMA_DIR_TypeDef DMA_DIR,
+              DMA_Mode_TypeDef DMA_Mode,
+              DMA_MemoryIncMode_TypeDef DMA_MemoryIncMode,
+              DMA_Priority_TypeDef DMA_Priority,
+              DMA_MemoryDataSize_TypeDef DMA_MemoryDataSize );
+void DMA_GlobalCmd(FunctionalState NewState);
+void DMA_Cmd(DMA_Channel_TypeDef* DMA_Channelx, FunctionalState NewState);
+void DMA_SetTimeOut(uint8_t DMA_TimeOut);
+
+/* Data Counter functions *****************************************************/
+void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMA_Channelx, uint8_t DataNumber);
+uint8_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMA_Channelx);
+
+/* Interrupts and flags management functions **********************************/
+void DMA_ITConfig(DMA_Channel_TypeDef* DMA_Channelx, DMA_ITx_TypeDef DMA_ITx, FunctionalState NewState);
+FlagStatus DMA_GetFlagStatus(DMA_FLAG_TypeDef DMA_FLAG);
+void DMA_ClearFlag(DMA_FLAG_TypeDef DMA_FLAG);
+ITStatus DMA_GetITStatus(DMA_IT_TypeDef DMA_IT);
+void DMA_ClearITPendingBit(DMA_IT_TypeDef DMA_IT);
+
+#endif /*__STM8L15x_DMA_H */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_exti.h b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_exti.h
new file mode 100755
index 0000000..8cfbf12
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_exti.h
@@ -0,0 +1,285 @@
+/**
+  ******************************************************************************
+  * @file    stm8l15x_exti.h
+  * @author  MCD Application Team
+  * @version V1.6.0
+  * @date    28-June-2013
+  * @brief   This file contains all the functions prototypes for the EXTI firmware
+  *          library.
+  ******************************************************************************
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ****************************************************************************** 
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM8L15x_EXTI_H
+#define __STM8L15x_EXTI_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm8l15x.h"
+
+/** @addtogroup STM8L15x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup EXTI
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @addtogroup EXTI_Exported_Types
+  * @{
+  */
+
+/** @defgroup EXTI_Trigger
+  * @{
+  */
+typedef enum
+{
+  EXTI_Trigger_Falling_Low    = (uint8_t)0x00, /*!< Interrupt on Falling edge and Low level */
+  EXTI_Trigger_Rising         = (uint8_t)0x01, /*!< Interrupt on Rising edge only */
+  EXTI_Trigger_Falling        = (uint8_t)0x02, /*!< Interrupt on Falling edge only */
+  EXTI_Trigger_Rising_Falling = (uint8_t)0x03  /*!< Interrupt on Rising and Falling edges */
+} EXTI_Trigger_TypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_Half_Port
+  *
+  * @brief EXTI halfPort possible values
+  * Values are coded as following:
+  * - Bit 7: 0 => the half port is in EXTI_CONF1 register
+  *          1 => the half port is in EXTI_CONF2 register
+  * - Bits[6:0] => the half port selection mask
+  * @{
+  */
+typedef enum
+{
+  EXTI_HalfPort_B_LSB  = (uint8_t)0x01, /*!< Interrupt selector PB(3:0) */
+  EXTI_HalfPort_B_MSB  = (uint8_t)0x02, /*!< Interrupt selector PB(7:4) */
+  EXTI_HalfPort_D_LSB  = (uint8_t)0x04, /*!< Interrupt selector PD(3:0) */
+  EXTI_HalfPort_D_MSB  = (uint8_t)0x08, /*!< Interrupt selector PD(7:4) */
+  EXTI_HalfPort_E_LSB  = (uint8_t)0x10, /*!< Interrupt selector PE(3:0) */
+  EXTI_HalfPort_E_MSB  = (uint8_t)0x20, /*!< Interrupt selector PE(7:4) */
+  EXTI_HalfPort_F_LSB  = (uint8_t)0x40, /*!< Interrupt selector PF(3:0) */
+  EXTI_HalfPort_F_MSB  = (uint8_t)0x81, /*!< Interrupt selector PF(7:4) */
+  EXTI_HalfPort_G_LSB  = (uint8_t)0x82, /*!< Interrupt selector PG(3:0) */
+  EXTI_HalfPort_G_MSB  = (uint8_t)0x84, /*!< Interrupt selector PG(7:4) */
+  EXTI_HalfPort_H_LSB  = (uint8_t)0x88, /*!< Interrupt selector PH(3:0) */
+  EXTI_HalfPort_H_MSB  = (uint8_t)0x90  /*!< Interrupt selector PH(7:4) */
+} EXTI_HalfPort_TypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_Port
+  *
+  * @brief EXTI Port possible values
+  * Values are coded in 0xXY format where
+  * X: the register index
+  *   X = 0: EXTI_CR3
+  *   X = 1: EXTI_CR4
+  * Y: the number of shift to be performed
+  * @{
+  */
+typedef enum
+{
+  EXTI_Port_B = (uint8_t)0x00, /*!< GPIO Port B */
+  EXTI_Port_D = (uint8_t)0x02, /*!< GPIO Port D */
+  EXTI_Port_E = (uint8_t)0x04, /*!< GPIO Port E */
+  EXTI_Port_F = (uint8_t)0x06, /*!< GPIO Port F */
+  EXTI_Port_G = (uint8_t)0x10, /*!< GPIO Port G */
+  EXTI_Port_H = (uint8_t)0x12  /*!< GPIO Port H */
+} EXTI_Port_TypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_Pin
+  *
+  * @brief EXTI PinNum possible values
+  * Values are coded in 0xXY format where
+  * X: the register index
+  *   X = 0: EXTI_CR1
+  *   X = 1: EXTI_CR2
+  * Y: the number of shift to be performed
+  * @{
+  */
+typedef enum
+{
+  EXTI_Pin_0 = (uint8_t)0x00, /*!< GPIO Pin 0 */
+  EXTI_Pin_1 = (uint8_t)0x02, /*!< GPIO Pin 1 */
+  EXTI_Pin_2 = (uint8_t)0x04, /*!< GPIO Pin 2 */
+  EXTI_Pin_3 = (uint8_t)0x06, /*!< GPIO Pin 3 */
+  EXTI_Pin_4 = (uint8_t)0x10, /*!< GPIO Pin 4 */
+  EXTI_Pin_5 = (uint8_t)0x12, /*!< GPIO Pin 5 */
+  EXTI_Pin_6 = (uint8_t)0x14, /*!< GPIO Pin 6 */
+  EXTI_Pin_7 = (uint8_t)0x16  /*!< GPIO Pin 7 */
+} EXTI_Pin_TypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_Interrupts
+  *
+  * @brief EXTI IT pending bit possible values
+  * Values are coded in 0xXY format where
+  * X: the register index
+  *    X = 00:  EXTI_SR1
+  *    X = 01:  EXTI_SR2
+  * Y: the IT pending bit mask
+  * @{
+  */
+typedef enum
+{
+  EXTI_IT_Pin0    = (uint16_t)0x0001, /*!< GPIO Pin pos 0 */
+  EXTI_IT_Pin1    = (uint16_t)0x0002, /*!< GPIO Pin pos 1 */
+  EXTI_IT_Pin2    = (uint16_t)0x0004, /*!< GPIO Pin pos 2 */
+  EXTI_IT_Pin3    = (uint16_t)0x0008, /*!< GPIO Pin pos 3 */
+  EXTI_IT_Pin4    = (uint16_t)0x0010, /*!< GPIO Pin pos 4 */
+  EXTI_IT_Pin5    = (uint16_t)0x0020, /*!< GPIO Pin pos 5 */
+  EXTI_IT_Pin6    = (uint16_t)0x0040, /*!< GPIO Pin pos 6 */
+  EXTI_IT_Pin7    = (uint16_t)0x0080, /*!< GPIO Pin pos 7 */
+  EXTI_IT_PortB   = (uint16_t)0x0101, /*!< GPIO Port B    */
+  EXTI_IT_PortD   = (uint16_t)0x0102, /*!< GPIO Port D    */
+  EXTI_IT_PortE   = (uint16_t)0x0104, /*!< GPIO Port E    */
+  EXTI_IT_PortF   = (uint16_t)0x0108, /*!< GPIO Port F    */
+  EXTI_IT_PortG   = (uint16_t)0x0110, /*!< GPIO Port G    */
+  EXTI_IT_PortH   = (uint16_t)0x0120  /*!< GPIO Port H    */
+} EXTI_IT_TypeDef;
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
+
+/** @addtogroup EXTI_Exported_Macros
+  * @{
+  */
+
+/**
+  * @brief Macro used by the assert function to check the different functions parameters.
+  */
+
+/**
+  * @brief Macro used by the assert function in order to check the different values
+  *  of EXTI Sensitivity
+  */
+#define IS_EXTI_TRIGGER(TRIGGER) \
+  (((TRIGGER) == EXTI_Trigger_Falling_Low)  || \
+   ((TRIGGER) == EXTI_Trigger_Rising) || \
+   ((TRIGGER) == EXTI_Trigger_Falling) || \
+   ((TRIGGER) == EXTI_Trigger_Rising_Falling))
+
+/**
+  * @brief Macro used by the assert function in order to check the different
+  *   half ports values for configuration.
+  */
+#define IS_EXTI_HALFPORT(HALFPORT) \
+  (((HALFPORT) == EXTI_HalfPort_B_LSB) ||\
+   ((HALFPORT) == EXTI_HalfPort_B_MSB) ||\
+   ((HALFPORT) == EXTI_HalfPort_D_LSB) ||\
+   ((HALFPORT) == EXTI_HalfPort_D_MSB) ||\
+   ((HALFPORT) == EXTI_HalfPort_E_LSB) ||\
+   ((HALFPORT) == EXTI_HalfPort_E_MSB) ||\
+   ((HALFPORT) == EXTI_HalfPort_F_LSB) ||\
+   ((HALFPORT) == EXTI_HalfPort_F_MSB) ||\
+   ((HALFPORT) == EXTI_HalfPort_G_LSB) ||\
+   ((HALFPORT) == EXTI_HalfPort_G_MSB) ||\
+   ((HALFPORT) == EXTI_HalfPort_H_LSB) ||\
+   ((HALFPORT) == EXTI_HalfPort_H_MSB))
+
+/**
+  * @brief Macro used by the assert function in order to check the different Port Number values
+  */
+#define IS_EXTI_PORT(PORT) (((PORT) == EXTI_Port_B) ||\
+                            ((PORT) == EXTI_Port_D) ||\
+                            ((PORT) == EXTI_Port_E) ||\
+                            ((PORT) == EXTI_Port_F) ||\
+                            ((PORT) == EXTI_Port_G) ||\
+                            ((PORT) == EXTI_Port_H))
+
+/**
+  * @brief Macro used by the assert function in order to check the different Pin numbers values
+  */
+#define IS_EXTI_PINNUM(PINNUM) \
+  (((PINNUM) == EXTI_Pin_0) ||\
+   ((PINNUM) == EXTI_Pin_1) ||\
+   ((PINNUM) == EXTI_Pin_2) ||\
+   ((PINNUM) == EXTI_Pin_3) ||\
+   ((PINNUM) == EXTI_Pin_4) ||\
+   ((PINNUM) == EXTI_Pin_5) ||\
+   ((PINNUM) == EXTI_Pin_6) ||\
+   ((PINNUM) == EXTI_Pin_7))
+
+/**
+  * @brief Macro used by the assert function in order to check the different flags values
+  */
+#define IS_EXTI_ITPENDINGBIT(ITPENDINGBIT) \
+  (((ITPENDINGBIT) == EXTI_IT_Pin0) ||\
+   ((ITPENDINGBIT) == EXTI_IT_Pin1) ||\
+   ((ITPENDINGBIT) == EXTI_IT_Pin2) ||\
+   ((ITPENDINGBIT) == EXTI_IT_Pin3) ||\
+   ((ITPENDINGBIT) == EXTI_IT_Pin4) ||\
+   ((ITPENDINGBIT) == EXTI_IT_Pin5) ||\
+   ((ITPENDINGBIT) == EXTI_IT_Pin6) ||\
+   ((ITPENDINGBIT) == EXTI_IT_Pin7) ||\
+   ((ITPENDINGBIT) == EXTI_IT_PortB) ||\
+   ((ITPENDINGBIT) == EXTI_IT_PortD) ||\
+   ((ITPENDINGBIT) == EXTI_IT_PortE) ||\
+   ((ITPENDINGBIT) == EXTI_IT_PortF) ||\
+   ((ITPENDINGBIT) == EXTI_IT_PortG) ||\
+   ((ITPENDINGBIT) == EXTI_IT_PortH))
+/**
+  * @}
+  */
+
+/* Exported functions ------------------------------------------------------- */
+/* EXTI configuration *********************************************************/
+void EXTI_DeInit(void);
+void EXTI_SetPinSensitivity(EXTI_Pin_TypeDef EXTI_Pin, EXTI_Trigger_TypeDef EXTI_Trigger);
+void EXTI_SelectPort(EXTI_Port_TypeDef EXTI_Port);
+void EXTI_SetHalfPortSelection(EXTI_HalfPort_TypeDef EXTI_HalfPort, FunctionalState NewState);
+void EXTI_SetPortSensitivity(EXTI_Port_TypeDef EXTI_Port, EXTI_Trigger_TypeDef EXTI_Trigger);
+EXTI_Trigger_TypeDef EXTI_GetPinSensitivity(EXTI_Pin_TypeDef EXTI_Pin);
+EXTI_Trigger_TypeDef EXTI_GetPortSensitivity(EXTI_Port_TypeDef EXTI_Port);
+
+/* EXTI Interrupt status management *******************************************/
+ITStatus EXTI_GetITStatus(EXTI_IT_TypeDef EXTI_IT);
+void EXTI_ClearITPendingBit(EXTI_IT_TypeDef EXTI_IT);
+
+#endif /* __STM8L15x_EXTI_H */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_flash.h b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_flash.h
new file mode 100755
index 0000000..129cdfb
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_flash.h
@@ -0,0 +1,356 @@
+/**
+  ******************************************************************************
+  * @file    stm8l15x_flash.h
+  * @author  MCD Application Team
+  * @version V1.6.0
+  * @date    28-June-2013
+  * @brief   This file contains all the functions prototypes for the FLASH firmware
+  *          library.
+  ******************************************************************************
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ****************************************************************************** 
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM8L15x_FLASH_H__
+#define __STM8L15x_FLASH_H__
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm8l15x.h"
+
+/** @addtogroup STM8L15x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup FLASH
+  * @{
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @addtogroup FLASH_Exported_Constants
+  * @{
+  */
+#define FLASH_PROGRAM_START_PHYSICAL_ADDRESS       ((uint32_t)0x00008000) /*!< Flash: start address */  
+#define FLASH_DATA_EEPROM_START_PHYSICAL_ADDRESS   ((uint32_t)0x00001000) /*!< Data Eeprom: start address */
+
+/* STM8L15x High density devices */
+#if defined (STM8L15X_HD) || defined (STM8L05X_HD_VL) 
+ #define FLASH_PROGRAM_END_PHYSICAL_ADDRESS         ((uint32_t)0x00017FFF) /*!< Flash: end address */
+ #define FLASH_DATA_EEPROM_END_PHYSICAL_ADDRESS     ((uint32_t)0x000017FF) /*!< Data Eeprom: end address */
+ #define FLASH_PROGRAM_BLOCKS_NUMBER                ((uint16_t)0x200)      /*!< Flash memory: total number of Block */
+ #define FLASH_DATA_EEPROM_BLOCKS_NUMBER            ((uint8_t)0x10)        /*!< Data EEprom: total number of Block */
+ #define FLASH_BLOCK_SIZE                           ((uint8_t)0x80)        /*!< Number of bytes in a Block 
+                                                                              (common for Program and Data EEprom memories) */
+ 
+/* STM8L15x Medium density and Medium density plus devices */ 
+#elif defined (STM8L15X_MD) || defined (STM8L15X_MDP) || defined (STM8AL31_L_MD) || defined (STM8L05X_MD_VL)
+ #define FLASH_PROGRAM_END_PHYSICAL_ADDRESS         ((uint32_t)0x0000FFFF) /*!< Flash: end address */
+ #define FLASH_DATA_EEPROM_END_PHYSICAL_ADDRESS     ((uint32_t)0x000013FF) /*!< Data Eeprom: end address */
+ #define FLASH_PROGRAM_BLOCKS_NUMBER                ((uint16_t)0x100)      /*!< Flash memory: total number of Block */
+ #define FLASH_DATA_EEPROM_BLOCKS_NUMBER            ((uint8_t)0x8)         /*!< Data EEprom: total number of Block */
+ #define FLASH_BLOCK_SIZE                           ((uint8_t)0x80)        /*!< Number of bytes in a Block 
+                                                                              (common for Program and Data EEprom memories) */
+
+/* STM8L15x Low density devices */ 
+#elif defined (STM8L15X_LD) || defined (STM8L05X_LD_VL)
+ #define FLASH_PROGRAM_END_PHYSICAL_ADDRESS         ((uint32_t)0x00009FFF) /*!< Flash: end address */
+ #define FLASH_DATA_EEPROM_END_PHYSICAL_ADDRESS     ((uint32_t)0x000010FF) /*!< Data Eeprom: end address */
+ #define FLASH_PROGRAM_BLOCKS_NUMBER                ((uint16_t)0x80)       /*!< Flash memory: total number of Block */
+ #define FLASH_DATA_EEPROM_BLOCKS_NUMBER            ((uint8_t)0x4)         /*!< Data EEprom: total number of Block */
+ #define FLASH_BLOCK_SIZE                           ((uint8_t)0x40)        /*!< Number of bytes in a Block 
+                                                                              (common for Program and Data EEprom memories) */
+#endif /* STM8L15X_HD or STM8L05X_HD_VL*/
+
+/*Common defines for all STM8L15x devices */
+#define FLASH_OPTION_BYTES_START_PHYSICAL_ADDRESS  ((uint32_t)0x00004800) /*!< Option bytes: start address */
+#define FLASH_OPTION_BYTES_END_PHYSICAL_ADDRESS    ((uint32_t)0x0000480A) /*!< Option bytes: end address */
+#define FLASH_RASS_KEY1                            ((uint8_t)0x56)        /*!< First RASS key */
+#define FLASH_RASS_KEY2                            ((uint8_t)0xAE)        /*!< Second RASS key */
+#define FLASH_READOUTPROTECTION_KEY                ((uint8_t)0xAA)        /*!< Read out protection key */
+
+/**
+  * @}
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @addtogroup FLASH_Exported_Types
+  * @{
+  */
+
+/** @defgroup FLASH_Memory_Type
+  * @{
+  */
+  typedef enum
+  {
+    FLASH_MemType_Program      = (uint8_t)0xFD, /*!< Program memory */
+    FLASH_MemType_Data         = (uint8_t)0xF7  /*!< Data EEPROM memory */
+  } FLASH_MemType_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup FLASH_Programming_Mode
+  * @{
+  */
+typedef enum
+{
+  FLASH_ProgramMode_Standard = (uint8_t)0x00, /*!< Standard programming mode */
+  FLASH_ProgramMode_Fast     = (uint8_t)0x10  /*!< Fast programming mode */
+} FLASH_ProgramMode_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup FLASH_Programming_Time
+  * @{
+  */
+typedef enum
+{
+  FLASH_ProgramTime_Standard = (uint8_t)0x00, /*!< Standard programming time fixed at 1/2 tprog */
+  FLASH_ProgramTime_TProg    = (uint8_t)0x01  /*!< Programming time fixed at tprog */
+} FLASH_ProgramTime_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup FLASH_Power_Mode
+  * @{
+  */
+typedef enum
+{
+  FLASH_Power_IDDQ = (uint8_t)0x00,  /*!< Flash program and data EEPROM in IDDQ */
+  FLASH_Power_On    = (uint8_t)0x01  /*!< Flash program and data EEPROM not in IDDQ */
+} FLASH_Power_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup FLASH_Status
+  * @{
+  */
+typedef enum
+{
+  FLASH_Status_Write_Protection_Error = (uint8_t)0x01, /*!< Write attempted to protected Block */
+  FLASH_Status_TimeOut                = (uint8_t)0x02, /*!< Time out error */
+  FLASH_Status_Successful_Operation   = (uint8_t)0x04  /*!< End of operation flag */
+} FLASH_Status_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup FLASH_Power_Status
+  * @{
+  */
+typedef enum
+{
+  FLASH_PowerStatus_IDDQDuringWaitMode          = (uint8_t)0x04, /*!< Flash program and data EEPROM
+                                                                            in IDDQ during Wait mode*/
+  FLASH_PowerStatus_IDDQDuringRunMode           = (uint8_t)0x08, /*!< Flash program and data EEPROM
+                                                                            in IDDQ mode during Run mode*/
+  FLASH_PowerStatus_IDDQDuringWaitAndRunModes   = (uint8_t)0x0C,  /*!<Flash program and data EEPROM
+                                                                            in IDDQ during Wait and run modes*/
+  FLASH_PowerStatus_On                          = (uint8_t)0x00  /*!< Flash program and data EEPROM
+                                                                                    is powered on during Wait and Run modes */
+} FLASH_PowerStatus_TypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Flags
+  * @{
+  */
+typedef enum {
+  FLASH_FLAG_HVOFF     = (uint8_t)0x40,     /*!< End of high voltage flag */
+  FLASH_FLAG_DUL       = (uint8_t)0x08,     /*!< Data EEPROM unlocked flag */
+  FLASH_FLAG_EOP       = (uint8_t)0x04,     /*!< End of programming (write or erase operation) flag */
+  FLASH_FLAG_PUL       = (uint8_t)0x02,     /*!< Flash Program memory unlocked flag */
+  FLASH_FLAG_WR_PG_DIS = (uint8_t)0x01      /*!< Write attempted to protected page flag */
+} FLASH_FLAG_TypeDef;
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+
+/** @addtogroup FLASH_Exported_Macros
+  * @{
+  */
+
+/**
+  * @brief Macro used by the assert function in order to check the different
+  *   sensitivity values for the flash Address
+  */
+
+#define IS_FLASH_PROGRAM_ADDRESS(Address) (((Address) >= FLASH_PROGRAM_START_PHYSICAL_ADDRESS) && \
+    ((Address) <= FLASH_PROGRAM_END_PHYSICAL_ADDRESS))
+
+
+/**
+  * @brief Macro used by the assert function in order to check the different
+  *   sensitivity values for the data Eeprom Address
+  */
+
+#define IS_FLASH_DATA_EEPROM_ADDRESS(Address) (((Address) >= FLASH_DATA_EEPROM_START_PHYSICAL_ADDRESS) && \
+    ((Address) <= FLASH_DATA_EEPROM_END_PHYSICAL_ADDRESS))
+
+/**
+  * @brief Macro used by the assert function in order to check the different
+  *  sensitivity values for the data eeprom and flash program Address
+  */
+#define IS_FLASH_ADDRESS(Address)((((Address) >= FLASH_PROGRAM_START_PHYSICAL_ADDRESS) && ((Address) <= FLASH_PROGRAM_END_PHYSICAL_ADDRESS)) || \
+                                  (((Address) >= FLASH_DATA_EEPROM_START_PHYSICAL_ADDRESS) && ((Address) <= FLASH_DATA_EEPROM_END_PHYSICAL_ADDRESS)))
+
+/**
+  * @brief Macro used by the assert function in order to check the different
+  *   sensitivity values for the option bytes Address
+  */
+#define IS_OPTION_BYTE_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_OPTION_BYTES_START_PHYSICAL_ADDRESS) && \
+    ((ADDRESS) <= FLASH_OPTION_BYTES_END_PHYSICAL_ADDRESS))
+
+/**
+  * @brief Macro used by the assert function in order to check the different
+  *   sensitivity values for the flash Block number
+  */
+#define IS_FLASH_PROGRAM_BLOCK_NUMBER(BlockNum) ((BlockNum) < FLASH_PROGRAM_BLOCKS_NUMBER)
+
+/**
+  * @brief Macro used by the assert function in order to check the different
+  *   sensitivity values for the data eeprom Block number
+  */
+#define IS_FLASH_DATA_EEPROM_BLOCK_NUMBER(BlockNum) ((BlockNum) < FLASH_DATA_EEPROM_BLOCKS_NUMBER)
+
+/**
+  * @brief Macro used by the assert function in order to check the different
+  *   sensitivity values for the flash memory type
+  */
+#define IS_FLASH_MEMORY_TYPE(MemType) (((MemType) == FLASH_MemType_Program) || \
+                                       ((MemType) == FLASH_MemType_Data))
+
+/**
+  * @brief Macro used by the assert function in order to check the different
+  *   sensitivity values for the flash program block mode
+  */
+#define IS_FLASH_PROGRAM_MODE(Mode) (((Mode) == FLASH_ProgramMode_Standard) || \
+                                     ((Mode) == FLASH_ProgramMode_Fast))
+
+/**
+  * @brief Macro used by the assert function in order to check the program time mode
+  */
+#define IS_FLASH_PROGRAM_TIME(Time) (((Time) == FLASH_ProgramTime_Standard) || \
+                                     ((Time) == FLASH_ProgramTime_TProg))
+
+/**
+  * @brief Macro used by the assert function in order to check the power mode
+  */
+#define IS_FLASH_POWER(Power) (((Power) == FLASH_Power_IDDQ) || \
+                               ((Power) == FLASH_Power_On))
+
+/**
+  * @brief Macro used by the assert function in order to check the power status during wait and run modes
+  */
+#define IS_FLASH_POWERSTATUS(PowerStatus) (((PowerStatus) == FLASH_PowerStatus_IDDQDuringWaitMode) || \
+    ((PowerStatus) == FLASH_PowerStatus_IDDQDuringRunMode ) || \
+    ((PowerStatus) == FLASH_PowerStatus_IDDQDuringWaitAndRunModes) || \
+    ((PowerStatus) == FLASH_Power_On))
+
+/**
+  * @brief Macro used by the assert function in order to check the different flags values
+  */
+#define IS_FLASH_FLAGS(FLAG) (((FLAG) == FLASH_FLAG_HVOFF) || \
+                              ((FLAG) == FLASH_FLAG_DUL) || \
+                              ((FLAG) == FLASH_FLAG_EOP) || \
+                              ((FLAG) == FLASH_FLAG_PUL) || \
+                              ((FLAG) == FLASH_FLAG_WR_PG_DIS))
+
+/**
+  * @}
+  */
+
+/* Exported functions ------------------------------------------------------- */
+/* FLASH program and Data EEPROM memories interface configuration functions ***/
+FLASH_ProgramTime_TypeDef FLASH_GetProgrammingTime(void);
+void FLASH_SetProgrammingTime(FLASH_ProgramTime_TypeDef FLASH_ProgTime);
+void FLASH_PowerWaitModeConfig(FLASH_Power_TypeDef FLASH_Power);
+
+/* FLASH program and Data EEPROM memories Programming functions ***************/
+void FLASH_DeInit(void);
+void FLASH_Unlock(FLASH_MemType_TypeDef FLASH_MemType);
+void FLASH_Lock(FLASH_MemType_TypeDef FLASH_MemType);
+void FLASH_ProgramByte(uint32_t Address, uint8_t Data);
+void FLASH_EraseByte(uint32_t Address);
+void FLASH_ProgramWord(uint32_t Address, uint32_t Data);
+uint8_t FLASH_ReadByte(uint32_t Address);
+
+/* Option Bytes Programming functions *****************************************/
+uint16_t FLASH_GetBootSize(void);
+uint16_t FLASH_GetCodeSize(void);
+FunctionalState FLASH_GetReadOutProtectionStatus(void);
+void FLASH_ProgramOptionByte(uint16_t Address, uint8_t Data);
+void FLASH_EraseOptionByte(uint16_t Address);
+
+/* Interrupts and flags management functions **********************************/
+void FLASH_ITConfig(FunctionalState NewState);
+FlagStatus FLASH_GetFlagStatus(FLASH_FLAG_TypeDef FLASH_FLAG);
+
+/* Functions to be executed from RAM ******************************************/
+
+/**
+@code
+ All the functions declared below must be executed from RAM exclusively, except 
+ for the FLASH_WaitForLastOperation function which can be executed from Flash.
+ 
+ Steps of the execution from RAM differs from one toolchain to another.
+ for more details refer to stm8l15x_flash.c file.
+ 
+ To enable execution from RAM you can either uncomment the following define 
+ in the stm8s.h file or define it in your toolchain compiler preprocessor
+ - #define RAM_EXECUTION  (1) 
+
+@endcode
+*/
+
+IN_RAM(void FLASH_PowerRunModeConfig(FLASH_Power_TypeDef FLASH_Power));
+IN_RAM(FLASH_PowerStatus_TypeDef FLASH_GetPowerStatus(void));
+
+IN_RAM(void FLASH_ProgramBlock(uint16_t BlockNum, FLASH_MemType_TypeDef FLASH_MemType,
+                        FLASH_ProgramMode_TypeDef FLASH_ProgMode, uint8_t *Buffer));
+IN_RAM(void FLASH_EraseBlock(uint16_t BlockNum, FLASH_MemType_TypeDef FLASH_MemType));
+
+IN_RAM(FLASH_Status_TypeDef FLASH_WaitForLastOperation(FLASH_MemType_TypeDef FLASH_MemType));
+
+#endif /*__STM8L15x_FLASH_H__*/
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_gpio.h b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_gpio.h
new file mode 100755
index 0000000..6e9fbb5
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_gpio.h
@@ -0,0 +1,176 @@
+/**
+  ******************************************************************************
+  * @file    stm8l15x_gpio.h
+  * @author  MCD Application Team
+  * @version V1.6.0
+  * @date    28-June-2013
+  * @brief   This file contains all the functions prototypes for the GPIO firmware
+  *          library.
+  ******************************************************************************
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ****************************************************************************** 
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM8L15x_GPIO_H
+#define __STM8L15x_GPIO_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm8l15x.h"
+
+/** @addtogroup STM8L15x_StdPeriph_Driver
+  * @{
+  */
+  
+/** @addtogroup I2C
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @addtogroup GPIO_Exported_Types
+  * @{
+  */
+
+/**
+  * @defgroup GPIO_Modes
+  *
+  * @brief
+  *     
+  * Bits definitions:
+  * - Bit 7: 0 = INPUT mode
+  *          1 = OUTPUT mode
+  *          1 = PULL-UP (input) or PUSH-PULL (output)
+  * - Bit 5: 0 = No external interrupt (input) or No slope control (output)
+  *          1 = External interrupt (input) or Slow control enabled (output)
+  * - Bit 4: 0 = Low level (output)
+  *          1 = High level (output push-pull) or HI-Z (output open-drain)
+  * @{
+  */
+typedef enum
+{
+  GPIO_Mode_In_FL_No_IT      = (uint8_t)0x00,   /*!< Input floating, no external interrupt */
+  GPIO_Mode_In_PU_No_IT      = (uint8_t)0x40,   /*!< Input pull-up, no external interrupt */
+  GPIO_Mode_In_FL_IT         = (uint8_t)0x20,   /*!< Input floating, external interrupt */
+  GPIO_Mode_In_PU_IT         = (uint8_t)0x60,   /*!< Input pull-up, external interrupt */
+  GPIO_Mode_Out_OD_Low_Fast  = (uint8_t)0xA0,   /*!< Output open-drain, low level, 10MHz */
+  GPIO_Mode_Out_PP_Low_Fast  = (uint8_t)0xE0,   /*!< Output push-pull, low level, 10MHz */
+  GPIO_Mode_Out_OD_Low_Slow  = (uint8_t)0x80,   /*!< Output open-drain, low level, 2MHz */
+  GPIO_Mode_Out_PP_Low_Slow  = (uint8_t)0xC0,   /*!< Output push-pull, low level, 2MHz */
+  GPIO_Mode_Out_OD_HiZ_Fast  = (uint8_t)0xB0,   /*!< Output open-drain, high-impedance level, 10MHz */
+  GPIO_Mode_Out_PP_High_Fast = (uint8_t)0xF0,   /*!< Output push-pull, high level, 10MHz */
+  GPIO_Mode_Out_OD_HiZ_Slow  = (uint8_t)0x90,   /*!< Output open-drain, high-impedance level, 2MHz */
+  GPIO_Mode_Out_PP_High_Slow = (uint8_t)0xD0    /*!< Output push-pull, high level, 2MHz */
+}GPIO_Mode_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup GPIO_Pin
+  * @{
+  */
+
+typedef enum
+{
+  GPIO_Pin_0    = ((uint8_t)0x01),   /*!< Pin 0 selected */
+  GPIO_Pin_1    = ((uint8_t)0x02),   /*!< Pin 1 selected */
+  GPIO_Pin_2    = ((uint8_t)0x04),   /*!< Pin 2 selected */
+  GPIO_Pin_3    = ((uint8_t)0x08),   /*!< Pin 3 selected */
+  GPIO_Pin_4    = ((uint8_t)0x10),   /*!< Pin 4 selected */
+  GPIO_Pin_5    = ((uint8_t)0x20),   /*!< Pin 5 selected */
+  GPIO_Pin_6    = ((uint8_t)0x40),   /*!< Pin 6 selected */
+  GPIO_Pin_7    = ((uint8_t)0x80),   /*!< Pin 7 selected */
+  GPIO_Pin_LNib = ((uint8_t)0x0F),   /*!< Low nibble pins selected */
+  GPIO_Pin_HNib = ((uint8_t)0xF0),   /*!< High nibble pins selected */
+  GPIO_Pin_All  = ((uint8_t)0xFF)    /*!< All pins selected */
+}GPIO_Pin_TypeDef;
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+  
+/* Exported constants --------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
+
+/** @addtogroup GPIO_Exported_Macros
+  * @{
+  */
+
+/**
+  * @brief Macro used by the assert function to check the different functions parameters.
+  */
+
+/**
+  * @brief Macro used by the assert function in order to check the different
+  * values of GPIOMode_TypeDef.
+  */
+#define IS_GPIO_MODE(MODE) \
+  (((MODE) == GPIO_Mode_In_FL_No_IT)       || \
+   ((MODE) == GPIO_Mode_In_PU_No_IT)       || \
+   ((MODE) == GPIO_Mode_In_FL_IT)          || \
+   ((MODE) == GPIO_Mode_In_PU_IT)          || \
+   ((MODE) == GPIO_Mode_Out_OD_Low_Fast)   || \
+   ((MODE) == GPIO_Mode_Out_PP_Low_Fast)   || \
+   ((MODE) == GPIO_Mode_Out_OD_Low_Slow)   || \
+   ((MODE) == GPIO_Mode_Out_PP_Low_Slow)   || \
+   ((MODE) == GPIO_Mode_Out_OD_HiZ_Fast)   || \
+   ((MODE) == GPIO_Mode_Out_PP_High_Fast)  || \
+   ((MODE) == GPIO_Mode_Out_OD_HiZ_Slow)   || \
+   ((MODE) == GPIO_Mode_Out_PP_High_Slow))
+
+/**
+  * @brief Macro used by the assert function in order to check the different
+  * values of GPIO_Pins.
+  */
+#define IS_GPIO_PIN(PIN) ((PIN) != (uint8_t)0x00)
+
+/**
+  * @}
+  */
+
+
+/* Exported functions ------------------------------------------------------- */
+/* Initialization and Configuration *******************************************/
+void GPIO_DeInit(GPIO_TypeDef* GPIOx);
+void GPIO_Init(GPIO_TypeDef* GPIOx, uint8_t GPIO_Pin, GPIO_Mode_TypeDef GPIO_Mode);
+void GPIO_ExternalPullUpConfig(GPIO_TypeDef* GPIOx, uint8_t GPIO_Pin, FunctionalState NewState);
+
+/* GPIO Read and Write ********************************************************/
+void GPIO_Write(GPIO_TypeDef* GPIOx, uint8_t GPIO_PortVal);
+void GPIO_WriteBit(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef GPIO_Pin, BitAction GPIO_BitVal);
+void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint8_t GPIO_Pin);
+void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint8_t GPIO_Pin);
+void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint8_t GPIO_Pin);
+uint8_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
+uint8_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
+BitStatus GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef GPIO_Pin);
+BitStatus GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef GPIO_Pin);
+
+#endif /* __STM8L15x_GPIO_H */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_i2c.h b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_i2c.h
new file mode 100755
index 0000000..8dee6b0
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_i2c.h
@@ -0,0 +1,806 @@
+/**
+  ******************************************************************************
+  * @file    stm8l15x_i2c.h
+  * @author  MCD Application Team
+  * @version V1.6.0
+  * @date    28-June-2013
+  * @brief   This file contains all the functions prototypes for the I2C firmware 
+  *          library.
+  ******************************************************************************
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ****************************************************************************** 
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM8L15x_I2C_H
+#define __STM8L15x_I2C_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm8l15x.h"
+
+/** @addtogroup STM8L15x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup I2C
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup I2C_Exported_Types
+ * @{
+ */
+/** @defgroup I2C_mode
+  * @{
+  */
+typedef enum
+{
+  I2C_Mode_I2C           = (uint8_t)0x00,   /*!< I2C mode */
+  I2C_Mode_SMBusDevice   = (uint8_t)0x02,   /*!< SMBus Device mode */
+  I2C_Mode_SMBusHost     = (uint8_t)0x0A    /*!< SMBus Host mode */
+} I2C_Mode_TypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_duty_cycle_in_fast_mode
+  * @{
+  */
+typedef enum
+{
+  I2C_DutyCycle_2    = (uint8_t)0x00,  /*!< Fast mode Tlow/THigh = 2 */
+  I2C_DutyCycle_16_9 = (uint8_t)0x40   /*!< Fast mode Tlow/Thigh = 16/9 */
+} I2C_DutyCycle_TypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_acknowledgement
+  * @{
+  */
+typedef enum
+{
+  I2C_Ack_Disable = (uint8_t)0x00,  /*!< No acknowledge */
+  I2C_Ack_Enable  = (uint8_t)0x04   /*!< Acknowledge Enabled */
+} I2C_Ack_TypeDef;
+/**
+  * @}
+  */
+
+/** @defgroup  I2C_Position_Acknowledgement
+  * @{
+  */
+typedef enum
+{
+  I2C_AckPosition_Current = (uint8_t)0x00,   /*!< Acknowledge on the current byte */
+  I2C_AckPosition_Next    = (uint8_t)0x08    /*!< Acknowledge on the next byte */
+} I2C_AckPosition_TypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_acknowledged_address
+  * @{
+  */
+typedef enum
+{
+  I2C_AcknowledgedAddress_7bit  = (uint8_t)0x00,  /*!< 7-bit slave address (10-bit address not acknowledged) */
+  I2C_AcknowledgedAddress_10bit = (uint8_t)0x80   /*!< 10-bit slave address (7-bit address not acknowledged) */
+} I2C_AcknowledgedAddress_TypeDef;
+/**
+  * @}
+  */
+
+/** @defgroup I2C_transfer_direction
+  * @{
+  */
+  
+/**
+  * Warning: the values correspond to the ADD0 bit position in the OARL register
+  */
+typedef enum
+{
+  I2C_Direction_Transmitter = (uint8_t)0x00,  /*!< Transmission direction */
+  I2C_Direction_Receiver    = (uint8_t)0x01   /*!< Reception direction */
+} I2C_Direction_TypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_SMBus_alert_pin_level
+  * @{
+  */
+typedef enum
+{
+  I2C_SMBusAlert_High = (uint8_t)0x00,  /*!< SMBAlert pin high */
+  I2C_SMBusAlert_Low  =  (uint8_t)0x01   /*!< SMBAlert pin Low */
+} I2C_SMBusAlert_TypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_PEC_position
+  * @{
+  */
+typedef enum
+{
+  I2C_PECPosition_Current = (uint8_t)0x00,  /*!< Current byte in shift register is PEC */
+  I2C_PECPosition_Next    = (uint8_t)0x08   /*!< Next  byte in shift register is PEC */
+} I2C_PECPosition_TypeDef;
+/**
+  * @}
+  */
+
+/** @defgroup I2C_flags_definition
+  * @{
+  */
+/**
+  * @brief Elements values convention: 0xXXYY
+  *  X = SRx registers index
+  *      X = 1 : SR1
+  *      X = 2 : SR2
+  *      X = 3 : SR3
+  *  Y = Flag mask in the register
+  */
+
+typedef enum
+{
+  /* SR1 register flags */
+  I2C_FLAG_TXE        = (uint16_t)0x0180,  /*!< Transmit Data Register Empty flag */
+  I2C_FLAG_RXNE       = (uint16_t)0x0140,  /*!< Read Data Register Not Empty flag */
+  I2C_FLAG_STOPF      = (uint16_t)0x0110,  /*!< Stop detected flag */
+  I2C_FLAG_ADD10      = (uint16_t)0x0108,  /*!< 10-bit Header sent flag */
+  I2C_FLAG_BTF        = (uint16_t)0x0104,  /*!< Data Byte Transfer Finished flag */
+  I2C_FLAG_ADDR       = (uint16_t)0x0102,  /*!< Address Sent/Matched (master/slave) flag */
+  I2C_FLAG_SB         = (uint16_t)0x0101,  /*!< Start bit sent flag */
+
+  /* SR2 register flags */
+  I2C_FLAG_SMBALERT   = (uint16_t)0x0280,  /*!< SMBUS Alert flag */
+  I2C_FLAG_TIMEOUT     = (uint16_t)0x0240,  /*!< Time out flag */
+  I2C_FLAG_WUFH       = (uint16_t)0x0220,  /*!< Wake Up From Halt flag */
+  I2C_FLAG_PECERR     = (uint16_t)0x0210,  /*!< PEC error flag */
+  I2C_FLAG_OVR        = (uint16_t)0x0208,  /*!< Overrun/Underrun flag */
+  I2C_FLAG_AF         = (uint16_t)0x0204,  /*!< Acknowledge Failure flag */
+  I2C_FLAG_ARLO       = (uint16_t)0x0202,  /*!< Arbitration Loss flag */
+  I2C_FLAG_BERR       = (uint16_t)0x0201,  /*!< Misplaced Start or Stop condition */
+
+  /* SR3 register flags */
+  I2C_FLAG_DUALF    = (uint16_t)0x0380,  /*!< DUAL Flag */
+  I2C_FLAG_SMBHOST    = (uint16_t)0x0340,  /*!< SMBUS host Flag */
+  I2C_FLAG_SMBDEFAULT = (uint16_t)0x0320,  /*!< SMBUS default flag */
+  I2C_FLAG_GENCALL    = (uint16_t)0x0310,  /*!< General Call header received Flag */
+  I2C_FLAG_TRA        = (uint16_t)0x0304,  /*!< Transmitter Receiver flag */
+  I2C_FLAG_BUSY       = (uint16_t)0x0302,  /*!< Bus Busy flag */
+  I2C_FLAG_MSL        = (uint16_t)0x0301   /*!< Master Slave flag */
+} I2C_FLAG_TypeDef;
+
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_interrupts_definition
+  * @{
+  */
+
+/**
+  * @brief I2C Pending bits
+  * Elements values convention: 0xXYZZ
+  *  X = SRx registers index
+  *      X = 0 : ITR
+  *      X = 1 : SR1
+  *      X = 2 : SR2
+  *  Y = Position of the corresponding Interrupt
+  *  ZZ = flag mask in the dedicated register(X register)
+  */
+
+typedef enum
+{
+  I2C_IT_ERR             = (uint16_t)0x0001,   /*!< Error Interruption */
+  I2C_IT_EVT             = (uint16_t)0x0002,   /*!< Event Interruption */
+  I2C_IT_BUF             = (uint16_t)0x0004,   /*!< Buffer Interruption */
+  /* SR1 register*/
+  I2C_IT_TXE             = (uint16_t)0x1680,   /*!< Transmit Data Register Empty  */
+  I2C_IT_RXNE            = (uint16_t)0x1640,   /*!< Read Data Register Not Empty  */
+  I2C_IT_STOPF           = (uint16_t)0x1210,   /*!< Stop detected  */
+  I2C_IT_ADD10           = (uint16_t)0x1208,   /*!< 10-bit Header sent */
+  I2C_IT_BTF             = (uint16_t)0x1204,   /*!< Data Byte Transfer Finished  */
+  I2C_IT_ADDR            = (uint16_t)0x1202,   /*!< Address Sent/Matched (master/slave)  */
+  I2C_IT_SB              = (uint16_t)0x1201,   /*!< Start bit sent  */
+
+  /* SR2 register*/
+  I2C_IT_SMBALERT        = (uint16_t)0x2180,   /*!< SMBUS alert  */
+  I2C_IT_TIMEOUT         = (uint16_t)0x2140,   /*!< Time out  */
+  I2C_IT_WUFH            = (uint16_t)0x2220,   /*!< PEC error  */
+  I2C_IT_PECERR          = (uint16_t)0x2110,   /*!< Wake Up From Halt  */
+  I2C_IT_OVR             = (uint16_t)0x2108,   /*!< Overrun/Underrun  */
+  I2C_IT_AF              = (uint16_t)0x2104,   /*!< Acknowledge Failure  */
+  I2C_IT_ARLO            = (uint16_t)0x2102,   /*!< Arbitration Loss  */
+  I2C_IT_BERR            = (uint16_t)0x2101    /*!< Misplaced Start or Stop condition */
+} I2C_IT_TypeDef;
+/**
+  * @}
+  */
+  
+/** @defgroup I2C_Events
+  * @{
+  */
+
+/**
+  * @brief I2C possible events
+  * Values convention: 0xXXYY
+  * XX = Event SR3 corresponding value
+  * YY = Event SR1 corresponding value
+  * @note if Event = EV3_2 the rule above does not apply
+  * YY = Event SR2 corresponding value
+  */
+
+typedef enum
+{
+  /**
+ ===============================================================================
+               I2C Master Events (Events grouped in order of communication)                   
+ ===============================================================================  
+ */
+/**
+  * @brief  Communication start
+  *
+  * After sending the START condition (I2C_GenerateSTART() function) the master
+  * has to wait for this event. It means that the Start condition has been correctly
+  * released on the I2C bus (the bus is free, no other devices is communicating).
+  *
+  */
+  /* --EV5 */
+  I2C_EVENT_MASTER_MODE_SELECT               = (uint16_t)0x0301,  /*!< BUSY, MSL and SB flag */
+
+/**
+  * @brief  Address Acknowledge
+  *
+  * After checking on EV5 (start condition correctly released on the bus), the
+  * master sends the address of the slave(s) with which it will communicate
+  * (I2C_Send7bitAddress() function, it also determines the direction of the communication:
+  * Master transmitter or Receiver).
+  * Then the master has to wait that a slave acknowledges his address.
+  * If an acknowledge is sent on the bus, one of the following events will
+  * be set:
+  *
+  *  1) In case of Master Receiver (7-bit addressing):
+  *  the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED event is set.
+  *
+  *  2) In case of Master Transmitter (7-bit addressing):
+  *  the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED is set
+  *
+  *  3) In case of 10-Bit addressing mode, the master (just after generating the START
+  *  and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData()
+  *  function).
+  *  Then master should wait on EV9. It means that the 10-bit addressing
+  *  header has been correctly sent on the bus.
+  *  Then master should send the second part of the 10-bit address (LSB) using
+  *  the function I2C_Send7bitAddress(). Then master should wait for event EV6.
+  *
+  */
+  /* --EV6 */
+  I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED = (uint16_t)0x0782,  /*!< BUSY, MSL, ADDR, TXE and TRA flags */
+  I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED    = (uint16_t)0x0302,  /*!< BUSY, MSL and ADDR flags */
+  /* --EV9 */
+  I2C_EVENT_MASTER_MODE_ADDRESS10            = (uint16_t)0x0308,  /*!< BUSY, MSL and ADD10 flags */
+
+/**
+  * @brief Communication events
+  *
+  * If a communication is established (START condition generated and slave address
+  * acknowledged) then the master has to check on one of the following events for
+  * communication procedures:
+  *
+  * 1) Master Receiver mode: The master has to wait on the event EV7 then to read
+  *    the data received from the slave (I2C_ReceiveData() function).
+  *
+  * 2) Master Transmitter mode: The master has to send data (I2C_SendData()
+  *    function) then to wait on event EV8 or EV8_2.
+  *    These two events are similar:
+  *     - EV8 means that the data has been written in the data register and is
+  *       being shifted out.
+  *     - EV8_2 means that the data has been physically shifted out and output
+  *       on the bus.
+  *     In most cases, using EV8 is sufficient for the application.
+  *     Using EV8_2 leads to a slower communication but ensure more reliable test.
+  *     EV8_2 is also more suitable than EV8 for testing on the last data transmission
+  *     (before Stop condition generation).
+  *
+  *  @note In case the user software does not guarantee that this event EV7 is
+  *  managed before the current byte end of transfer, then user may check on EV7
+  *  and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)).
+  *  In this case the communication may be slower.
+  *
+  */
+  /* Master RECEIVER mode -----------------------------*/
+  /* --EV7 */
+  I2C_EVENT_MASTER_BYTE_RECEIVED             = (uint16_t)0x0340,  /*!< BUSY, MSL and RXNE flags */
+
+  /* Master TRANSMITTER mode --------------------------*/
+  /* --EV8 */
+  I2C_EVENT_MASTER_BYTE_TRANSMITTING         = (uint16_t)0x0780,  /*!< TRA, BUSY, MSL, TXE flags */
+  /* --EV8_2 */
+
+  I2C_EVENT_MASTER_BYTE_TRANSMITTED          = (uint16_t)0x0784,  /*!< EV8_2: TRA, BUSY, MSL, TXE and BTF flags */
+
+/**
+ ===============================================================================
+               I2C Slave Events (Events grouped in order of communication)                  
+ ===============================================================================  
+ */
+ 
+/**
+  * @brief  Communication start events
+  *
+  * Wait on one of these events at the start of the communication. It means that
+  * the I2C peripheral detected a Start condition on the bus (generated by master
+  * device) followed by the peripheral address.
+  * The peripheral generates an ACK condition on the bus (if the acknowledge
+  * feature is enabled through function I2C_AcknowledgeConfig()) and the events
+  * listed above are set :
+  *
+  * 1) In normal case (only one address managed by the slave), when the address
+  *   sent by the master matches the own address of the peripheral (configured by
+  *   I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set
+  *   (where XXX could be TRANSMITTER or RECEIVER).
+  *
+  * 2) In case the address sent by the master matches the second address of the 
+  *   peripheral (configured by the function I2C_OwnAddress2Config() and enabled 
+  *   by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED 
+  *   (where XXX could be TRANSMITTER or RECEIVER) are set.
+  *  
+  * 3) In case the address sent by the master is General Call (address 0x00) and 
+  *   if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) 
+  *   the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED.  
+  * 
+  */
+
+  /* --EV1  (all the events below are variants of EV1) */
+  /* 1) Case of One Single Address managed by the slave */
+  I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED    = (uint16_t)0x0202,  /*!< BUSY and ADDR flags */
+  I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED = (uint16_t)0x0682,  /*!< TRA, BUSY, TXE and ADDR flags */
+
+  /* 2) Case of Dual address managed by the slave */
+  I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED    = (uint16_t)0x8200,  /*! DUALF and BUSY flags */
+  I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED = (uint16_t)0x8680,  /*! DUALF, TRA, BUSY and TXE flags */
+
+  /* 3) Case of General Call enabled for the slave */
+  I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED  = (uint16_t)0x1200,  /*!< EV2: GENCALL and BUSY flags */
+
+  /**
+    * @brief  Communication events
+    *
+    * Wait on one of these events when EV1 has already been checked :
+    *
+    * - Slave RECEIVER mode:
+    *     - EV2: When the application is expecting a data byte to be received.
+    *     - EV4: When the application is expecting the end of the communication:
+    *       master sends a stop condition and data transmission is stopped.
+    *
+    * - Slave Transmitter mode:
+    *    - EV3: When a byte has been transmitted by the slave and the application
+    *      is expecting the end of the byte transmission.
+    *      The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and I2C_EVENT_SLAVE_BYTE_TRANSMITTING
+    *      are similar. The second one can optionally be used when the user software
+    *      doesn't guarantee the EV3 is managed before the current byte end of transfer.
+    *    - EV3_2: When the master sends a NACK in order to tell slave that data transmission
+    *      shall end (before sending the STOP condition).
+    *      In this case slave has to stop sending data bytes and expect a Stop
+    *      condition on the bus.
+    *
+    *  @note In case the  user software does not guarantee that the event EV2 is
+    *  managed before the current byte end of transfer, then user may check on EV2
+    *  and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)).
+    *  In this case the communication may be slower.
+    *
+    */
+  /* Slave RECEIVER mode --------------------------*/
+  /* --EV2 */
+  I2C_EVENT_SLAVE_BYTE_RECEIVED              = (uint16_t)0x0240,  /*!< BUSY and RXNE flags */
+  /* --EV4  */
+  I2C_EVENT_SLAVE_STOP_DETECTED              = (uint16_t)0x0010,  /*!< STOPF flag */
+
+  /* Slave TRANSMITTER mode -----------------------*/
+  /* --EV3 */
+  I2C_EVENT_SLAVE_BYTE_TRANSMITTED           = (uint16_t)0x0684,  /*!< TRA, BUSY, TXE and BTF flags */
+  I2C_EVENT_SLAVE_BYTE_TRANSMITTING          = (uint16_t)0x0680,  /*!< TRA, BUSY and TXE flags */
+  /* --EV3_2 */
+  I2C_EVENT_SLAVE_ACK_FAILURE                = (uint16_t)0x0004  /*!< AF flag */
+} I2C_Event_TypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup  I2C_Registers
+  * @{
+  */
+typedef enum
+{
+  I2C_Register_CR1    = (uint8_t)0x00,   /*!< Control register 1 */
+  I2C_Register_CR2    = (uint8_t)0x01,   /*!< Control register 2 */
+  I2C_Register_FREQR  = (uint8_t)0x02,   /*!< Frequency register */
+  I2C_Register_OARL   = (uint8_t)0x03,   /*!< Own address register LSB */
+  I2C_Register_OARH   = (uint8_t)0x04,   /*!< Own address register MSB */
+  I2C_Register_DR     = (uint8_t)0x06,   /*!< Data register */
+  I2C_Register_SR1    = (uint8_t)0x07,   /*!< Status register 1 */
+  I2C_Register_SR2    = (uint8_t)0x08,   /*!< Status register 2 */
+  I2C_Register_SR3    = (uint8_t)0x09,   /*!< Status register 3 */
+  I2C_Register_ITR    = (uint8_t)0x0A,   /*!< Interrupt and DMA register */
+  I2C_Register_CCRL   = (uint8_t)0x0B,   /*!< Clock control register low */
+  I2C_Register_CCRH   = (uint8_t)0x0C,   /*!< Clock control register high */
+  I2C_Register_TRISER = (uint8_t)0x0D,   /*!< TRISE register */
+  I2C_Register_PECR   = (uint8_t)0x0E    /*!< PEC register */
+} I2C_Register_TypeDef;
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup I2C_Exported_Constants
+  * @{
+  */
+#define I2C_MAX_STANDARD_FREQ ((uint32_t)100000)
+#define I2C_MAX_FAST_FREQ     ((uint32_t)400000)
+
+/**
+  *@}
+  */
+
+/* Exported macro -----------------------------------------------------------*/
+/** @defgroup I2C_Exported_Macros
+  * @{
+  */
+
+/**
+  * @brief Macro used by the assert function to check the different functions parameters.
+  */
+
+/**
+  * @brief  Macro used by the assert function to check the different I2C modes.
+  */
+#define IS_I2C_MODE(MODE)(((MODE) == I2C_Mode_I2C) || \
+                          ((MODE) == I2C_Mode_SMBusDevice) || \
+                          ((MODE) == I2C_Mode_SMBusHost))
+
+/**
+  * @brief  Macro used by the assert function to check the different I2C duty cycles.
+  */
+#define IS_I2C_DUTY_CYCLE(CYCLE)(((CYCLE) == I2C_DutyCycle_2) || \
+                                 ((CYCLE) == I2C_DutyCycle_16_9))
+
+/**
+  * @brief  Macro used by the assert function to check the different acknowledgement configuration
+  */
+#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Disable) || \
+                                 ((STATE) == I2C_Ack_Enable))
+/**
+  * @brief  Macro used by the assert function to check the different acknowledgement position
+  */
+#define IS_I2C_ACK_POSITION(POSITION) (((POSITION) == I2C_AckPosition_Next) || \
+                                       ((POSITION) == I2C_AckPosition_Current))
+
+/**
+  * @brief  Macro used by the assert function to check the different I2C PEC positions.
+  */
+#define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Current) || \
+                                       ((POSITION) == I2C_PECPosition_Next))
+
+/**
+  * @brief  Macro used by the assert function to check the different I2C addressing modes.
+  */
+#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDMODE) (((ADDMODE) == I2C_AcknowledgedAddress_7bit) || \
+    ((ADDMODE) == I2C_AcknowledgedAddress_10bit))
+
+/**
+  * @brief  Macro used by the assert function to check the different I2C SMBus Alert pin configuration.
+  */
+#define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_High) || \
+                                   ((ALERT) == I2C_SMBusAlert_Low))
+
+/**
+  * @brief  Macro used by the assert function to check the different I2C communication direction.
+  */
+#define IS_I2C_DIRECTION(DIR)(((DIR) == I2C_Direction_Transmitter) || \
+                              ((DIR) == I2C_Direction_Receiver ))
+
+/**
+  * @brief  Macro used by the assert function to check the different I2C flags.
+  */
+#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_TXE)        || \
+                               ((FLAG) == I2C_FLAG_RXNE)       || \
+                               ((FLAG) == I2C_FLAG_STOPF)      || \
+                               ((FLAG) == I2C_FLAG_ADD10)      || \
+                               ((FLAG) == I2C_FLAG_BTF)        || \
+                               ((FLAG) == I2C_FLAG_ADDR)       || \
+                               ((FLAG) == I2C_FLAG_SB)         || \
+                               ((FLAG) == I2C_FLAG_SMBALERT)   || \
+                               ((FLAG) == I2C_FLAG_TIMEOUT)    || \
+                               ((FLAG) == I2C_FLAG_WUFH)       || \
+                               ((FLAG) == I2C_FLAG_PECERR)     || \
+                               ((FLAG) == I2C_FLAG_OVR)        || \
+                               ((FLAG) == I2C_FLAG_AF)         || \
+                               ((FLAG) == I2C_FLAG_ARLO)       || \
+                               ((FLAG) == I2C_FLAG_BERR)       || \
+                               ((FLAG) == I2C_FLAG_DUALF)      || \
+                               ((FLAG) == I2C_FLAG_SMBHOST)    || \
+                               ((FLAG) == I2C_FLAG_SMBDEFAULT) || \
+                               ((FLAG) == I2C_FLAG_GENCALL)    || \
+                               ((FLAG) == I2C_FLAG_TRA)        || \
+                               ((FLAG) == I2C_FLAG_BUSY)       || \
+                               ((FLAG) == I2C_FLAG_MSL))
+
+/**
+  * @brief  Macro used by the assert function to check the I2C flags to clear.
+  */
+#define IS_I2C_CLEAR_FLAG(FLAG) ((((uint16_t)(FLAG) & (uint16_t)0xFD00) == 0x00) && ((uint16_t)(FLAG) != 0x00))
+
+/**
+  * @brief Macro used by the assert_param function in order to check the different
+  *  sensitivity values for the Interrupts
+  */
+#define IS_I2C_CONFIG_IT(IT) ((((uint16_t)(IT) & (uint16_t)0xFFF8) == 0x00) && ((uint16_t)(IT) != 0x00))
+
+/**
+  * @brief  Macro used by the assert function to check the different I2C possible
+  *   pending bits to clear by writing 0.
+  */
+#define IS_I2C_CLEAR_IT(IT) ((((uint16_t)(IT) & (uint16_t)0xDC00) == 0x00) && ((uint16_t)(IT) != 0x00))
+
+/**
+  * @brief  Macro used by the assert function to check the different I2C possible pending bits.
+  */
+#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_OVR)      ||\
+                           ((IT) == I2C_IT_AF)       ||\
+                           ((IT) == I2C_IT_ARLO)     ||\
+                           ((IT) == I2C_IT_BERR)     ||\
+                           ((IT) == I2C_IT_TXE)      ||\
+                           ((IT) == I2C_IT_RXNE)     ||\
+                           ((IT) == I2C_IT_STOPF)    ||\
+                           ((IT) == I2C_IT_ADD10)    ||\
+                           ((IT) == I2C_IT_BTF)      ||\
+                           ((IT) == I2C_IT_ADDR)     ||\
+                           ((IT) == I2C_IT_PECERR)   ||\
+                           ((IT) == I2C_IT_TIMEOUT)  ||\
+                           ((IT) == I2C_IT_SMBALERT) ||\
+                           ((IT) == I2C_IT_WUFH)     ||\
+                           ((IT) == I2C_IT_SB))
+/**
+  * @brief  Macro used by the assert function to check the different I2C possible events.
+  */
+#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \
+                             ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \
+                             ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \
+                             ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \
+                             ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \
+                             ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \
+                             ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | (uint16_t)I2C_FLAG_DUALF)) || \
+                             ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | (uint16_t)I2C_FLAG_GENCALL)) || \
+                             ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \
+                             ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | (uint16_t)I2C_FLAG_DUALF)) || \
+                             ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | (uint16_t)I2C_FLAG_GENCALL)) || \
+                             ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE) || \
+                             ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \
+                             ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \
+                             ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \
+                             ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \
+                             ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \
+                             ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \
+                             ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \
+                             ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10))
+/**
+  * @brief  Macro used by the assert function to check the different I2C registers.
+  */
+#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \
+                                   ((REGISTER) == I2C_Register_CR2) || \
+                                   ((REGISTER) == I2C_Register_FREQR) || \
+                                   ((REGISTER) == I2C_Register_OARL) || \
+                                   ((REGISTER) == I2C_Register_OARH) || \
+                                   ((REGISTER) == I2C_Register_DR) || \
+                                   ((REGISTER) == I2C_Register_SR1) || \
+                                   ((REGISTER) == I2C_Register_SR2) || \
+                                   ((REGISTER) == I2C_Register_SR3) || \
+                                   ((REGISTER) == I2C_Register_ITR) || \
+                                   ((REGISTER) == I2C_Register_CCRL) || \
+                                   ((REGISTER) == I2C_Register_CCRH) || \
+                                   ((REGISTER) == I2C_Register_TRISER) || \
+                                   ((REGISTER) == I2C_Register_PECR))
+/**
+  * @brief  Macro used by the assert function to check the different I2C possible own address.
+  */
+#define IS_I2C_OWN_ADDRESS(ADDRESS) ((ADDRESS) <= (uint16_t)0x03FF)
+
+/**
+  * @brief  Macro used by the assert function to check the different I2C address
+  * The address must be even
+  */
+#define IS_I2C_ADDRESS(ADD) (((ADD) & (uint8_t)0x01) == (uint8_t)0x00)
+
+/**
+  * @brief  Macro used by the assert function to check that I2C Output clock frequency must be between 1Hz and 400kHz.
+  */
+#define IS_I2C_OUTPUT_CLOCK_FREQ(FREQ) (((FREQ) >= (uint8_t)1) && ((FREQ) <= I2C_MAX_FAST_FREQ))
+
+/**
+  * @}
+  */
+
+/* Exported functions ------------------------------------------------------- */
+
+/*  Function used to set the I2C configuration to the default reset state *****/
+void I2C_DeInit(I2C_TypeDef* I2Cx);
+
+/* Initialization and Configuration functions *********************************/
+void I2C_Init(I2C_TypeDef* I2Cx, uint32_t OutputClockFrequency, uint16_t OwnAddress,
+              I2C_Mode_TypeDef I2C_Mode, I2C_DutyCycle_TypeDef I2C_DutyCycle,
+              I2C_Ack_TypeDef I2C_Ack, I2C_AcknowledgedAddress_TypeDef I2C_AcknowledgedAddress);
+void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address);
+void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_AckPositionConfig(I2C_TypeDef* I2Cx, I2C_AckPosition_TypeDef I2C_AckPosition);
+void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, I2C_DutyCycle_TypeDef I2C_DutyCycle);
+void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, I2C_SMBusAlert_TypeDef I2C_SMBusAlert);
+void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, I2C_Direction_TypeDef I2C_Direction);
+
+/* Data transfers functions ***************************************************/ 
+void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);
+uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);
+
+/* PEC management functions ***************************************************/ 
+void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, I2C_PECPosition_TypeDef I2C_PECPosition);
+uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);
+void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
+
+/* DMA transfers management functions *****************************************/
+void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+
+/* Interrupts, events and flags management functions **************************/
+
+void I2C_ITConfig(I2C_TypeDef* I2Cx, I2C_IT_TypeDef I2C_IT, FunctionalState NewState);
+uint8_t I2C_ReadRegister(I2C_TypeDef* I2Cx, I2C_Register_TypeDef I2C_Register);
+
+/**
+ * @brief
+ *  
+@verbatim 
+================================================================================
+                       I2C State Monitoring Functions
+================================================================================
+ This I2C driver provides three different ways for I2C state monitoring
+  depending on the application requirements and constraints:
+
+
+ 1) Basic state monitoring:
+    Using I2C_CheckEvent() function:
+    It compares the status registers (SR1, SR2 and SR3) content to a given event
+    (can be the combination of one or more flags).
+    It returns SUCCESS if the current status includes the given flags
+    and returns ERROR if one or more flags are missing in the current status.
+    - When to use:
+      - This function is suitable for most applications as well as for startup
+      activity since the events are fully described in the product reference manual
+      (RM0031).
+      - It is also suitable for users who need to define their own events.
+    - Limitations:
+      - If an error occurs (ie. error flags are set besides to the monitored flags),
+        the I2C_CheckEvent() function may return SUCCESS despite the communication
+        hold or corrupted real state.
+        In this case, it is advised to use error interrupts to monitor the error
+        events and handle them in the interrupt IRQ handler.
+
+        @note
+        For error management, it is advised to use the following functions:
+          - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).
+          - I2Cx_IRQHandler() which is called when the I2C interrupts occur.
+            Where x is the peripheral instance (I2C1,...)
+          - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into the
+           I2Cx_IRQHandler() function in order to determine which error occurred.
+          - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd()
+            and/or I2C_GenerateStop() in order to clear the error flag and
+            source and return to correct communication status.
+
+
+  2) Advanced state monitoring:
+     Using the function I2C_GetLastEvent() which returns the image of both SR1
+     & SR3 status registers in a single word (uint16_t) (Status Register 3 value
+     is shifted left by 8 bits and concatenated to Status Register 1).
+     - When to use:
+       - This function is suitable for the same applications above but it allows to
+         overcome the limitations of I2C_GetFlagStatus() function (see below).
+         The returned value could be compared to events already defined in the
+         library (stm8l15x_i2c.h) or to custom values defined by user.
+       - This function is suitable when multiple flags are monitored at the same time.
+       - At the opposite of I2C_CheckEvent() function, this function allows user to
+         choose when an event is accepted (when all events flags are set and no
+         other flags are set or just when the needed flags are set like
+         I2C_CheckEvent() function).
+     - Limitations:
+       - User may need to define his own events.
+       - Same remark concerning the error management is applicable for this
+         function if user decides to check only regular communication flags (and
+         ignores error flags).
+
+
+ 3) Flag-based state monitoring:
+     Using the function I2C_GetFlagStatus() which simply returns the status of
+     one single flag (ie. I2C_FLAG_RXNE ...).
+     - When to use:
+        - This function could be used for specific applications or in debug phase.
+        - It is suitable when only one flag checking is needed (most I2C events
+          are monitored through multiple flags).
+     - Limitations:
+        - When calling this function, the Status register is accessed. Some flags are
+          cleared when the status register is accessed. So checking the status
+          of one Flag, may clear other ones.
+        - Function may need to be called twice or more in order to monitor one
+          single event.
+          
+          
+@endverbatim
+ *            
+ */
+
+/**
+ ===============================================================================
+                          1. Basic state monitoring                    
+ ===============================================================================
+*/  
+ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, I2C_Event_TypeDef I2C_Event);
+/**
+ ===============================================================================
+                          2. Advanced state monitoring                   
+ ===============================================================================  
+ */
+I2C_Event_TypeDef I2C_GetLastEvent(I2C_TypeDef* I2Cx);
+/**
+ ===============================================================================
+                          3. Flag-based state monitoring                   
+ ===============================================================================  
+ */
+FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, I2C_FLAG_TypeDef I2C_FLAG);
+
+void I2C_ClearFlag(I2C_TypeDef* I2Cx, I2C_FLAG_TypeDef I2C_FLAG);
+ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, I2C_IT_TypeDef I2C_IT);
+void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, I2C_IT_TypeDef I2C_IT);
+
+#endif /* __STM8L15x_I2C_H */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_irtim.h b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_irtim.h
new file mode 100755
index 0000000..8d0a00e
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_irtim.h
@@ -0,0 +1,65 @@
+/**
+  ******************************************************************************
+  * @file    stm8l15x_irtim.h
+  * @author  MCD Application Team
+  * @version V1.6.0
+  * @date    28-June-2013
+  * @brief   This file contains all the functions prototypes for the IRTIM firmware
+  *          library.
+  ******************************************************************************
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ****************************************************************************** 
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM8L15x_IRTIM_H
+#define __STM8L15x_IRTIM_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm8l15x.h"
+
+/** @addtogroup STM8L15x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup IRTIM
+ * @{
+ */
+ 
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/* IRTIM configuration ********************************************************/
+void IRTIM_DeInit(void);
+void IRTIM_Cmd(FunctionalState NewState);
+void IRTIM_HighSinkODCmd(FunctionalState NewState);
+
+/* IRITM status management ****************************************************/
+FunctionalState IRTIM_GetStatus(void);
+FunctionalState IRTIM_GetHighSinkODStatus(void);
+
+/**
+  * @}
+  */
+
+#endif /* __STM8L15x_IRTIM_H */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_itc.h b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_itc.h
new file mode 100755
index 0000000..0f566f0
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_itc.h
@@ -0,0 +1,269 @@
+/**
+  ******************************************************************************
+  * @file    stm8l15x_itc.h
+  * @author  MCD Application Team
+  * @version V1.6.0
+  * @date    28-June-2013
+  * @brief   This file contains all the functions prototypes for the ITC firmware
+  *          library.
+  ******************************************************************************
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ****************************************************************************** 
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM8L15x_ITC_H__
+#define __STM8L15x_ITC_H__
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm8l15x.h"
+
+/** @addtogroup STM8L15x_StdPeriph_Driver
+  * @{
+  */
+  
+/** @addtogroup ITC
+  * @{
+  */ 
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup ITC_Exported_Types
+  * @{
+  */
+
+/** @defgroup ITC_Interrupt_Lines_selection
+  * @{
+  */
+typedef enum {
+  FLASH_IRQn                               = (uint8_t)1,   /*!< Flash interrupt  */
+  DMA1_CHANNEL0_1_IRQn                     = (uint8_t)2,   /*!< DMA Channels 0/1 */
+  DMA1_CHANNEL2_3_IRQn                     = (uint8_t)3,   /*!< DMA Channels 2/3 */
+  EXTIE_F_PVD_IRQn                         = (uint8_t)5,   /*!< GPIOE/F and PVD interrupt */
+  EXTI0_IRQn                               = (uint8_t)8,   /*!< PIN0 interrupt   */
+  EXTI1_IRQn                               = (uint8_t)9,   /*!< PIN1 interrupt   */
+  EXTI2_IRQn                               = (uint8_t)10,  /*!< PIN2 interrupt   */
+  EXTI3_IRQn                               = (uint8_t)11,  /*!< PIN3 interrupt   */
+  EXTI4_IRQn                               = (uint8_t)12,  /*!< PIN4 interrupt   */
+  EXTI5_IRQn                               = (uint8_t)13,  /*!< PIN5 interrupt   */
+  EXTI6_IRQn                               = (uint8_t)14,  /*!< PIN6 interrupt   */
+  EXTI7_IRQn                               = (uint8_t)15,  /*!< PIN7 interrupt   */
+  ADC1_COMP_IRQn                           = (uint8_t)18,  /*!< ADC1/Comparator interrupt */
+  TIM4_UPD_OVF_TRG_IRQn                    = (uint8_t)25,  /*!< TIM4 Update/Overflow/Trigger interrupt */
+  SPI1_IRQn                                = (uint8_t)26,  /*!< SPI1 interrupt */
+#if defined (STM8L15X_MD) || defined (STM8L05X_MD_VL) || defined (STM8AL31_L_MD)
+  RTC_IRQn                                 = (uint8_t)4,   /*!< RTC interrupt    */
+  EXTIB_IRQn                               = (uint8_t)6,   /*!< GPIOB interrupt  */
+  EXTID_IRQn                               = (uint8_t)7,   /*!< GPIOD interrupt  */
+  LCD_IRQn                                 = (uint8_t)16,  /*!< LCD Driver interrupt    */
+	SWITCH_CSS_BREAK_DAC_IRQn                = (uint8_t)17,  /*!< Clock switch/CSS interrupt/TIM1 Break /DAC  interrupt */
+  TIM2_UPD_OVF_TRG_BRK_IRQn                = (uint8_t)19,  /*!< TIM2 Update/Overflow/Trigger/Break interrupt*/
+  TIM2_CC_IRQn                             = (uint8_t)20,  /*!< TIM2 input captute/output compare interrupt  */
+  TIM3_UPD_OVF_TRG_BRK_IRQn                = (uint8_t)21,  /*!< TIM3 Update/Overflow/Trigger/Break interrupt */
+  TIM3_CC_IRQn                             = (uint8_t)22,  /*!< TIM3 capture/compare interrupt  */
+	TIM1_UPD_OVF_TRG_IRQn                    = (uint8_t)23,  /*!< TIM1 TIM1 Update/Overflow/Trigger interrupt */
+  TIM1_CC_IRQn                             = (uint8_t)24,  /*!< TIM1 capture/compare interrupt  */
+  USART1_TX_IRQn                           = (uint8_t)27,  /*!< USART1 TX interrupt */
+  USART1_RX_IRQn                           = (uint8_t)28,  /*!< USART1 RX interrupt */
+  I2C1_IRQn                                = (uint8_t)29   /*!< I2C1 interrupt */
+#elif defined (STM8L15X_LD) || defined (STM8L05X_LD_VL)
+  RTC_CSSLSE_IRQn                          = (uint8_t)4,   /*!< RTC / CSSLSE interrupt    */
+  EXTIB_IRQn                               = (uint8_t)6,   /*!< GPIOB interrupt  */
+  EXTID_IRQn                               = (uint8_t)7,   /*!< GPIOD interrupt  */
+	SWITCH_CSS_IRQn                          = (uint8_t)17,  /*!< Clock switch/CSS interrupt/TIM1 Break /DAC  interrupt */
+  TIM2_UPD_OVF_TRG_BRK_IRQn                = (uint8_t)19,  /*!< TIM2 Update/Overflow/Trigger/Break interrupt*/
+  TIM2_CC_IRQn                             = (uint8_t)20,  /*!< TIM2 input captute/output compare interrupt  */
+  TIM3_UPD_OVF_TRG_BRK_IRQn                = (uint8_t)21,  /*!< TIM3 Update/Overflow/Trigger/Break interrupt */
+  TIM3_CC_IRQn                             = (uint8_t)22,  /*!< TIM3 capture/compare interrupt  */
+  USART1_TX_IRQn                           = (uint8_t)27,  /*!< USART1 TX interrupt */
+  USART1_RX_IRQn                           = (uint8_t)28,  /*!< USART1 RX interrupt */
+  I2C1_IRQn                                = (uint8_t)29   /*!< I2C1 interrupt */
+#elif defined (STM8L15X_HD) || defined (STM8L15X_MDP) || defined (STM8L05X_HD_VL)
+  RTC_CSSLSE_IRQn                          = (uint8_t)4,   /*!< RTC / CSSLSE interrupt    */
+  EXTIB_G_IRQn                             = (uint8_t)6,   /*!< GPIOB / G interrupt  */
+  EXTID_H_IRQn                             = (uint8_t)7,   /*!< GPIOD / H interrupt  */
+  LCD_AES_IRQn                             = (uint8_t)16,  /*!< LCD / AES interrupt    */
+	SWITCH_CSS_BREAK_DAC_IRQn                = (uint8_t)17,  /*!< Clock switch/CSS interrupt/TIM1 Break /DAC  interrupt */
+  TIM2_UPD_OVF_TRG_BRK_USART2_TX_IRQn      = (uint8_t)19,  /*!< TIM2 Update/Overflow/Trigger/Break /USART2 TX interrupt*/
+  TIM2_CC_USART2_RX_IRQn                   = (uint8_t)20,  /*!< TIM2 capture/compare / USART2 RX interrupt  */
+  TIM3_UPD_OVF_TRG_BRK_USART3_TX_IRQn      = (uint8_t)21,  /*!< TIM3 Update/Overflow/Trigger/Break / USART3 TX interrupt */
+  TIM3_CC_USART3_RX_IRQn                   = (uint8_t)22,  /*!< TIM3 capture/compare / USART3 RX interrupt  */
+	TIM1_UPD_OVF_TRG_IRQn                    = (uint8_t)23,  /*!< TIM1 TIM1 Update/Overflow/Trigger interrupt */
+  TIM1_CC_IRQn                             = (uint8_t)24,  /*!< TIM1 capture/compare interrupt  */
+  USART1_TX_TIM5_UPD_OVF_TRG_BRK_IRQn      = (uint8_t)27,  /*!< USART1 TX / TIM5 Update/Overflow/Trigger/Break interrupt */
+  USART1_RX_TIM5_CC_IRQn                   = (uint8_t)28,  /*!< USART1 RX / TIM5 capture/compare interrupt */
+  I2C1_SPI2_IRQn                           = (uint8_t)29   /*!< I2C1 / SPI2 interrupt */
+#endif  /* STM8L15X_MD */
+}IRQn_TypeDef;
+
+#if defined (STM8L15X_MD) || defined (STM8L05X_MD_VL) || defined (STM8AL31_L_MD)
+ #define IS_ITC_IRQ(Irq) (((Irq) == FLASH_IRQn) || \
+                         ((Irq) == DMA1_CHANNEL0_1_IRQn) || \
+                         ((Irq) == DMA1_CHANNEL2_3_IRQn) || \
+                         ((Irq) == RTC_IRQn) || \
+                         ((Irq) == EXTIE_F_PVD_IRQn) || \
+                         ((Irq) == EXTIB_IRQn) || \
+                         ((Irq) == EXTID_IRQn) || \
+                         ((Irq) == EXTI0_IRQn) || \
+                         ((Irq) == EXTI1_IRQn) || \
+                         ((Irq) == EXTI2_IRQn) || \
+                         ((Irq) == EXTI3_IRQn) || \
+                         ((Irq) == EXTI4_IRQn) || \
+                         ((Irq) == EXTI5_IRQn) || \
+                         ((Irq) == EXTI6_IRQn) || \
+                         ((Irq) == EXTI7_IRQn) || \
+                         ((Irq) == LCD_IRQn) || \
+                         ((Irq) == SWITCH_CSS_BREAK_DAC_IRQn) || \
+                         ((Irq) == ADC1_COMP_IRQn) || \
+                         ((Irq) == TIM2_UPD_OVF_TRG_BRK_IRQn) || \
+                         ((Irq) == TIM2_CC_IRQn) || \
+                         ((Irq) == TIM3_UPD_OVF_TRG_BRK_IRQn) || \
+                         ((Irq) == TIM3_CC_IRQn) || \
+                         ((Irq) == TIM1_UPD_OVF_TRG_IRQn) || \
+                         ((Irq) == TIM1_CC_IRQn) || \
+                         ((Irq) == TIM4_UPD_OVF_TRG_IRQn) || \
+                         ((Irq) == SPI1_IRQn) || \
+                         ((Irq) == USART1_TX_IRQn) || \
+                         ((Irq) == USART1_RX_IRQn) || \
+                         ((Irq) == I2C1_IRQn))
+#elif defined (STM8L15X_LD) || defined (STM8L05X_LD_VL)
+ #define IS_ITC_IRQ(Irq) (((Irq) == FLASH_IRQn) || \
+                         ((Irq) == DMA1_CHANNEL0_1_IRQn) || \
+                         ((Irq) == DMA1_CHANNEL2_3_IRQn) || \
+                         ((Irq) == RTC_CSSLSE_IRQn) || \
+                         ((Irq) == EXTIE_F_PVD_IRQn) || \
+                         ((Irq) == EXTIB_IRQn) || \
+                         ((Irq) == EXTID_IRQn) || \
+                         ((Irq) == EXTI0_IRQn) || \
+                         ((Irq) == EXTI1_IRQn) || \
+                         ((Irq) == EXTI2_IRQn) || \
+                         ((Irq) == EXTI3_IRQn) || \
+                         ((Irq) == EXTI4_IRQn) || \
+                         ((Irq) == EXTI5_IRQn) || \
+                         ((Irq) == EXTI6_IRQn) || \
+                         ((Irq) == EXTI7_IRQn) || \
+                         ((Irq) == SWITCH_CSS_IRQn) || \
+                         ((Irq) == ADC1_COMP_IRQn) || \
+                         ((Irq) == TIM2_UPD_OVF_TRG_BRK_IRQn) || \
+                         ((Irq) == TIM2_CC_IRQn) || \
+                         ((Irq) == TIM3_UPD_OVF_TRG_BRK_IRQn) || \
+                         ((Irq) == TIM3_CC_IRQn) || \
+                         ((Irq) == TIM4_UPD_OVF_TRG_IRQn) || \
+                         ((Irq) == SPI1_IRQn) || \
+                         ((Irq) == USART1_TX_IRQn) || \
+                         ((Irq) == USART1_RX_IRQn) || \
+                         ((Irq) == I2C1_IRQn))												 
+#elif defined (STM8L15X_HD) || defined (STM8L15X_MDP) || defined (STM8L05X_HD_VL)
+ #define IS_ITC_IRQ(Irq) (((Irq) == FLASH_IRQn) || \
+                         ((Irq) == DMA1_CHANNEL0_1_IRQn) || \
+                         ((Irq) == DMA1_CHANNEL2_3_IRQn) || \
+                         ((Irq) == RTC_CSSLSE_IRQn) || \
+                         ((Irq) == EXTIE_F_PVD_IRQn) || \
+                         ((Irq) == EXTIB_G_IRQn) || \
+                         ((Irq) == EXTID_H_IRQn) || \
+                         ((Irq) == EXTI0_IRQn) || \
+                         ((Irq) == EXTI1_IRQn) || \
+                         ((Irq) == EXTI2_IRQn) || \
+                         ((Irq) == EXTI3_IRQn) || \
+                         ((Irq) == EXTI4_IRQn) || \
+                         ((Irq) == EXTI5_IRQn) || \
+                         ((Irq) == EXTI6_IRQn) || \
+                         ((Irq) == EXTI7_IRQn) || \
+                         ((Irq) == LCD_AES_IRQn) || \
+                         ((Irq) == SWITCH_CSS_BREAK_DAC_IRQn) || \
+                         ((Irq) == ADC1_COMP_IRQn) || \
+                         ((Irq) == TIM2_UPD_OVF_TRG_BRK_USART2_TX_IRQn) || \
+                         ((Irq) == TIM2_CC_USART2_RX_IRQn) || \
+                         ((Irq) == TIM3_UPD_OVF_TRG_BRK_USART3_TX_IRQn) || \
+                         ((Irq) == TIM3_CC_USART3_RX_IRQn) || \
+                         ((Irq) == TIM1_UPD_OVF_TRG_IRQn) || \
+                         ((Irq) == TIM1_CC_IRQn) || \
+                         ((Irq) == TIM4_UPD_OVF_TRG_IRQn) || \
+                         ((Irq) == SPI1_IRQn) || \
+                         ((Irq) == USART1_TX_TIM5_UPD_OVF_TRG_BRK_IRQn) || \
+                         ((Irq) == USART1_RX_TIM5_CC_IRQn) || \
+                         ((Irq) == I2C1_SPI2_IRQn))
+#endif /* STM8L15X_MD */
+
+/**
+  * @}
+  */
+  
+/** @defgroup ITC_Priority_Level_selection
+  * @{
+  */
+typedef enum {
+  ITC_PriorityLevel_0 = (uint8_t)0x02, /*!< Software priority level 0 (cannot be written) */
+  ITC_PriorityLevel_1 = (uint8_t)0x01, /*!< Software priority level 1 */
+  ITC_PriorityLevel_2 = (uint8_t)0x00, /*!< Software priority level 2 */
+  ITC_PriorityLevel_3 = (uint8_t)0x03  /*!< Software priority level 3 */
+} ITC_PriorityLevel_TypeDef;
+
+#define IS_ITC_PRIORITY(PriorityValue) \
+  (((PriorityValue) == ITC_PriorityLevel_0) || \
+   ((PriorityValue) == ITC_PriorityLevel_1) || \
+   ((PriorityValue) == ITC_PriorityLevel_2) || \
+   ((PriorityValue) == ITC_PriorityLevel_3))
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup ITC_Exported_Constants
+  * @{
+  */
+
+#define CPU_SOFT_INT_DISABLED ((uint8_t)0x28) /*!< Mask for I1 and I0 bits in CPU_CC register */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+
+/** @defgroup ITC_Exported_Constants
+  * @{
+  */
+#define IS_ITC_INTERRUPTS_DISABLED (ITC_GetSoftIntStatus() == CPU_SOFT_INT_DISABLED)
+
+/**
+  * @}
+  */
+
+/* Exported functions ------------------------------------------------------- */
+/* Function used to set the ITC configuration to the default reset state ******/ 
+void ITC_DeInit(void);
+
+/* ITC configuration and management functions ******/ 
+uint8_t ITC_GetCPUCC(void);
+uint8_t ITC_GetSoftIntStatus(void);
+void ITC_SetSoftwarePriority(IRQn_TypeDef IRQn, ITC_PriorityLevel_TypeDef ITC_PriorityLevel);
+ITC_PriorityLevel_TypeDef ITC_GetSoftwarePriority(IRQn_TypeDef IRQn);
+
+#endif /* __STM8L15x_ITC_H__ */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_iwdg.h b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_iwdg.h
new file mode 100755
index 0000000..4872caf
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_iwdg.h
@@ -0,0 +1,137 @@
+/*******************************************************************************
+  * @file    stm8l15x_iwdg.h
+  * @author  MCD Application Team
+  * @version V1.6.0
+  * @date    28-June-2013
+  * @brief   This file contains all the functions prototypes for the IWDG 
+  *          firmware library.
+  ******************************************************************************
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ****************************************************************************** 
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM8L15x_IWDG_H
+#define __STM8L15x_IWDG_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm8l15x.h"
+
+/** @addtogroup STM8L15x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup IWDG
+  * @{
+  */
+  
+/* Exported variables ------------------------------------------------------- */
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup IWDG_Exported_Constants
+  * @{
+  */
+
+/** @defgroup IWDG_KeyRefresh
+  * @{
+  */
+#define IWDG_KEY_REFRESH    ((uint8_t)0xAA)  /*!< This value written in the Key 
+                                                  register prevent the watchdog reset */
+/**
+ * @}
+ */
+ 
+/** @defgroup IWDG_KeyEnable
+  * @{
+  */
+#define IWDG_KEY_ENABLE     ((uint8_t)0xCC)  /*!< This value written in the Key
+                                                  register start the watchdog counting down*/
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup IWDG_Exported_Types
+  * @{
+  */
+
+/** @defgroup IWDG_WriteAccess
+  * @{
+  */
+typedef enum
+{
+  IWDG_WriteAccess_Enable  = (uint8_t)0x55, 
+  IWDG_WriteAccess_Disable = (uint8_t)0x00
+} IWDG_WriteAccess_TypeDef;
+#define IS_IWDG_WRITE_ACCESS_MODE(MODE) (((MODE) == IWDG_WriteAccess_Enable) || \
+                                         ((MODE) == IWDG_WriteAccess_Disable))
+/**
+ * @}
+ */
+ 
+/** @defgroup IWDG_prescaler 
+  * @{
+  */
+typedef enum
+{
+  IWDG_Prescaler_4   = (uint8_t)0x00, /*!< Used to set prescaler register to 4 */
+  IWDG_Prescaler_8   = (uint8_t)0x01, /*!< Used to set prescaler register to 8 */
+  IWDG_Prescaler_16  = (uint8_t)0x02, /*!< Used to set prescaler register to 16 */
+  IWDG_Prescaler_32  = (uint8_t)0x03, /*!< Used to set prescaler register to 32 */
+  IWDG_Prescaler_64  = (uint8_t)0x04, /*!< Used to set prescaler register to 64 */
+  IWDG_Prescaler_128 = (uint8_t)0x05, /*!< Used to set prescaler register to 128 */
+  IWDG_Prescaler_256 = (uint8_t)0x06  /*!< Used to set prescaler register to 256 */
+} IWDG_Prescaler_TypeDef;
+#define IS_IWDG_PRESCALER_VALUE(VALUE) (((VALUE) == IWDG_Prescaler_4)   || \
+                                        ((VALUE) == IWDG_Prescaler_8)   || \
+                                        ((VALUE) == IWDG_Prescaler_16)  || \
+                                        ((VALUE) == IWDG_Prescaler_32)  || \
+                                        ((VALUE) == IWDG_Prescaler_64)  || \
+                                        ((VALUE) == IWDG_Prescaler_128) || \
+                                        ((VALUE) == IWDG_Prescaler_256))
+/**
+ * @}
+ */        
+                                 
+/**
+  * @}
+  */
+
+/* Exported functions ------------------------------------------------------- */
+/* Prescaler and Counter configuration functions ******************************/
+void IWDG_WriteAccessCmd(IWDG_WriteAccess_TypeDef IWDG_WriteAccess);
+void IWDG_SetPrescaler(IWDG_Prescaler_TypeDef IWDG_Prescaler);
+void IWDG_SetReload(uint8_t IWDG_Reload);
+void IWDG_ReloadCounter(void);
+
+/* IWDG activation function ***************************************************/
+void IWDG_Enable(void);
+
+#endif /* __STM8L15x_IWDG_H */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_lcd.h b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_lcd.h
new file mode 100755
index 0000000..90101f6
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_lcd.h
@@ -0,0 +1,470 @@
+/**
+  ******************************************************************************
+  * @file    stm8l15x_lcd.h
+  * @author  MCD Application Team
+  * @version V1.6.0
+  * @date    28-June-2013
+  * @brief   This file contains all the functions prototypes for the LCD firmware
+  *          library.
+  ******************************************************************************
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ****************************************************************************** 
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM8L15x_LCD_H
+#define __STM8L15x_LCD_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm8l15x.h"
+
+/** @addtogroup STM8L15x_StdPeriph_Driver
+  * @{
+  */
+  
+/** @addtogroup LCD
+  * @{
+  */ 
+  
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup LCD_Exported_Types
+  * @{
+  */
+
+/** @defgroup LCD_Duty
+  * @brief element values correspond to the bits position
+  * @{
+  */
+
+typedef enum {
+  LCD_Duty_Static = (uint8_t)0x00, /*!< Static duty */
+  LCD_Duty_1_2    = (uint8_t)0x02, /*!< 1/2 duty    */
+  LCD_Duty_1_3    = (uint8_t)0x04, /*!< 1/3 duty    */
+  LCD_Duty_1_4    = (uint8_t)0x06, /*!< 1/4 duty    */
+  LCD_Duty_1_8    = (uint8_t)0x20  /*!< 1/8 duty    */
+} LCD_Duty_TypeDef;
+
+#define IS_LCD_DUTY(DUTY) (((DUTY) == LCD_Duty_Static) || ((DUTY) == LCD_Duty_1_2) || \
+                           ((DUTY) == LCD_Duty_1_3) || ((DUTY) == LCD_Duty_1_4) || \
+                           ((DUTY) == LCD_Duty_1_8))
+/**
+  * @}
+  */
+  
+/** @defgroup LCD_Bias
+  * @brief element values correspond to the bits position
+  * @{
+  */
+typedef enum {
+  LCD_Bias_1_4  = (uint8_t)0x10,  /*!< 1/4 bias  */
+  LCD_Bias_1_3  = (uint8_t)0x00,  /*!< 1/3 bias  */
+  LCD_Bias_1_2  = (uint8_t)0x01   /*!< 1/2 bias  */
+} LCD_Bias_TypeDef;
+
+#define IS_LCD_BIAS(BIAS) (((BIAS) == LCD_Bias_1_4) || \
+                           ((BIAS) == LCD_Bias_1_3) || \
+                           ((BIAS) == LCD_Bias_1_2))
+
+/**
+  * @}
+  */
+                           
+/** @defgroup LCD_Clock_Prescaler
+  * @brief element values correspond to the bits position
+  * @{
+  */
+typedef enum {
+  LCD_Prescaler_1     = (uint8_t)0x00, /*!< CLKprescaler = ClKinput       */
+  LCD_Prescaler_2     = (uint8_t)0x10, /*!< CLKprescaler = ClKinput/2     */
+  LCD_Prescaler_4     = (uint8_t)0x20, /*!< CLKprescaler = ClKinput/4     */
+  LCD_Prescaler_8     = (uint8_t)0x30, /*!< CLKprescaler = ClKinput/8     */
+  LCD_Prescaler_16    = (uint8_t)0x40, /*!< CLKprescaler = ClKinput/16    */
+  LCD_Prescaler_32    = (uint8_t)0x50, /*!< CLKprescaler = ClKinput/32    */
+  LCD_Prescaler_64    = (uint8_t)0x60, /*!< CLKprescaler = ClKinput/64    */
+  LCD_Prescaler_128   = (uint8_t)0x70, /*!< CLKprescaler = ClKinput/128   */
+  LCD_Prescaler_256   = (uint8_t)0x80, /*!< CLKprescaler = ClKinput/256   */
+  LCD_Prescaler_512   = (uint8_t)0x90, /*!< CLKprescaler = ClKinput/512   */
+  LCD_Prescaler_1024  = (uint8_t)0xA0, /*!< CLKprescaler = ClKinput/1024  */
+  LCD_Prescaler_2048  = (uint8_t)0xB0, /*!< CLKprescaler = ClKinput/2048  */
+  LCD_Prescaler_4096  = (uint8_t)0xC0, /*!< CLKprescaler = ClKinput/4096  */
+  LCD_Prescaler_8192  = (uint8_t)0xD0, /*!< CLKprescaler = ClKinput/8192  */
+  LCD_Prescaler_16384 = (uint8_t)0xE0, /*!< CLKprescaler = ClKinput/16384 */
+  LCD_Prescaler_32768 = (uint8_t)0xF0  /*!< CLKprescaler = ClKinput/32768 */
+} LCD_Prescaler_TypeDef;
+
+#define IS_LCD_CLOCK_PRESCALER(PRESCALER) (((PRESCALER) == LCD_Prescaler_1) || \
+                                           ((PRESCALER) == LCD_Prescaler_2) || \
+                                           ((PRESCALER) == LCD_Prescaler_4) || \
+                                           ((PRESCALER) == LCD_Prescaler_8) || \
+                                           ((PRESCALER) == LCD_Prescaler_16) || \
+                                           ((PRESCALER) == LCD_Prescaler_32) || \
+                                           ((PRESCALER) == LCD_Prescaler_64) || \
+                                           ((PRESCALER) == LCD_Prescaler_128) || \
+                                           ((PRESCALER) == LCD_Prescaler_256) || \
+                                           ((PRESCALER) == LCD_Prescaler_512) || \
+                                           ((PRESCALER) == LCD_Prescaler_1024) || \
+                                           ((PRESCALER) == LCD_Prescaler_2048) || \
+                                           ((PRESCALER) == LCD_Prescaler_4096) || \
+                                           ((PRESCALER) == LCD_Prescaler_8192) || \
+                                           ((PRESCALER) == LCD_Prescaler_16384) || \
+                                           ((PRESCALER) == LCD_Prescaler_32768))
+    
+/**
+  * @}
+  */
+  
+/** @defgroup LCD_Clock_Divider
+  * @brief element values correspond to the bits position
+  * @{
+  */
+typedef enum {
+  LCD_Divider_16 = (uint8_t)0x00, /*!< LCD frequency = CLKprescaler/16 */
+  LCD_Divider_17 = (uint8_t)0x01, /*!< LCD frequency = CLKprescaler/17 */
+  LCD_Divider_18 = (uint8_t)0x02, /*!< LCD frequency = CLKprescaler/18 */
+  LCD_Divider_19 = (uint8_t)0x03, /*!< LCD frequency = CLKprescaler/19 */
+  LCD_Divider_20 = (uint8_t)0x04, /*!< LCD frequency = CLKprescaler/20 */
+  LCD_Divider_21 = (uint8_t)0x05, /*!< LCD frequency = CLKprescaler/21 */
+  LCD_Divider_22 = (uint8_t)0x06, /*!< LCD frequency = CLKprescaler/22 */
+  LCD_Divider_23 = (uint8_t)0x07, /*!< LCD frequency = CLKprescaler/23 */
+  LCD_Divider_24 = (uint8_t)0x08, /*!< LCD frequency = CLKprescaler/24 */
+  LCD_Divider_25 = (uint8_t)0x09, /*!< LCD frequency = CLKprescaler/25 */
+  LCD_Divider_26 = (uint8_t)0x0A, /*!< LCD frequency = CLKprescaler/26 */
+  LCD_Divider_27 = (uint8_t)0x0B, /*!< LCD frequency = CLKprescaler/27 */
+  LCD_Divider_28 = (uint8_t)0x0C, /*!< LCD frequency = CLKprescaler/28 */
+  LCD_Divider_29 = (uint8_t)0x0D, /*!< LCD frequency = CLKprescaler/29 */
+  LCD_Divider_30 = (uint8_t)0x0E, /*!< LCD frequency = CLKprescaler/30 */
+  LCD_Divider_31 = (uint8_t)0x0F  /*!< LCD frequency = CLKprescaler/31 */
+} LCD_Divider_TypeDef;
+
+#define IS_LCD_CLOCK_DIVIDER(DIVIDER) (((DIVIDER) == LCD_Divider_16) || \
+                                       ((DIVIDER) == LCD_Divider_17) || \
+                                       ((DIVIDER) == LCD_Divider_18) || \
+                                       ((DIVIDER) == LCD_Divider_19) || \
+                                       ((DIVIDER) == LCD_Divider_20) || \
+                                       ((DIVIDER) == LCD_Divider_21) || \
+                                       ((DIVIDER) == LCD_Divider_22) || \
+                                       ((DIVIDER) == LCD_Divider_23) || \
+                                       ((DIVIDER) == LCD_Divider_24) || \
+                                       ((DIVIDER) == LCD_Divider_25) || \
+                                       ((DIVIDER) == LCD_Divider_26) || \
+                                       ((DIVIDER) == LCD_Divider_27) || \
+                                       ((DIVIDER) == LCD_Divider_28) || \
+                                       ((DIVIDER) == LCD_Divider_29) || \
+                                       ((DIVIDER) == LCD_Divider_30) || \
+                                       ((DIVIDER) == LCD_Divider_31))
+                                       
+/**
+  * @}
+  */
+  
+/** @defgroup LCD_Contrast
+  * @brief element values correspond to the bits position
+  * @{
+  */
+typedef enum {
+  LCD_Contrast_Level_0 = (uint8_t)0x00, /*!< Medium Density / High Density Maximum Voltage = 2.60V / 2.60V */
+  LCD_Contrast_Level_1 = (uint8_t)0x02, /*!< Medium Density / High Density Maximum Voltage = 2.70V / 2.73V */
+  LCD_Contrast_Level_2 = (uint8_t)0x04, /*!< Medium Density / High Density Maximum Voltage = 2.80V / 2.86V */
+  LCD_Contrast_Level_3 = (uint8_t)0x06, /*!< Medium Density / High Density Maximum Voltage = 2.90V / 2.99V */
+  LCD_Contrast_Level_4 = (uint8_t)0x08, /*!< Medium Density / High Density Maximum Voltage = 3.00V / 3.12V */
+  LCD_Contrast_Level_5 = (uint8_t)0x0A, /*!< Medium Density / High Density Maximum Voltage = 3.10V / 3.25V */
+  LCD_Contrast_Level_6 = (uint8_t)0x0C, /*!< Medium Density / High Density Maximum Voltage = 3.20V / 3.38V */
+  LCD_Contrast_Level_7 = (uint8_t)0x0E  /*!< Medium Density / High Density Maximum Voltage = 3.30V / 3.51V */
+} LCD_Contrast_TypeDef;
+
+#define IS_LCD_CONTRAST(CONTRAST) (((CONTRAST) == LCD_Contrast_Level_0) || \
+                                   ((CONTRAST) == LCD_Contrast_Level_1) || \
+                                   ((CONTRAST) == LCD_Contrast_Level_2) || \
+                                   ((CONTRAST) == LCD_Contrast_Level_3) || \
+                                   ((CONTRAST) == LCD_Contrast_Level_4) || \
+                                   ((CONTRAST) == LCD_Contrast_Level_5) || \
+                                   ((CONTRAST) == LCD_Contrast_Level_6) || \
+                                   ((CONTRAST) == LCD_Contrast_Level_7))
+                                   
+/**
+  * @}
+  */
+
+/** @defgroup LCD_Voltage_Source
+  * @brief element values correspond to the bits position
+  * @{
+  */
+typedef enum {
+  LCD_VoltageSource_Internal = (uint8_t)0x00, /*!< Internal voltage source for the LCD */
+  LCD_VoltageSource_External = (uint8_t)0x01  /*!< External voltage source for the LCD */
+} LCD_VoltageSource_TypeDef;
+
+#define IS_LCD_VOLTAGE_SOURCE(SOURCE) (((SOURCE) == LCD_VoltageSource_Internal) || \
+                                       ((SOURCE) == LCD_VoltageSource_External))
+                                       
+/**
+  * @}
+  */
+
+/** @defgroup LCD_Pulse_On_Duration
+  * @brief element values correspond to the bits position
+  * @{
+  */
+typedef enum {
+  LCD_PulseOnDuration_0 = (uint8_t)0x00, /*!< Pulse on duration = 0/CLKprescaler  */
+  LCD_PulseOnDuration_1 = (uint8_t)0x20, /*!< Pulse on duration = 1/CLKprescaler  */
+  LCD_PulseOnDuration_2 = (uint8_t)0x40, /*!< Pulse on duration = 2/CLKprescaler  */
+  LCD_PulseOnDuration_3 = (uint8_t)0x60, /*!< Pulse on duration = 3/CLKprescaler  */
+  LCD_PulseOnDuration_4 = (uint8_t)0x80, /*!< Pulse on duration = 4/CLKprescaler  */
+  LCD_PulseOnDuration_5 = (uint8_t)0xA0, /*!< Pulse on duration = 5/CLKprescaler  */
+  LCD_PulseOnDuration_6 = (uint8_t)0xC0, /*!< Pulse on duration = 6/CLKprescaler  */
+  LCD_PulseOnDuration_7 = (uint8_t)0xE0  /*!< Pulse on duration = 7/CLKprescaler  */
+} LCD_PulseOnDuration_TypeDef;
+
+#define IS_LCD_PULSE_DURATION(DURATION) (((DURATION) == LCD_PulseOnDuration_0) || \
+    ((DURATION) == LCD_PulseOnDuration_1) || \
+    ((DURATION) == LCD_PulseOnDuration_2) || \
+    ((DURATION) == LCD_PulseOnDuration_3) || \
+    ((DURATION) == LCD_PulseOnDuration_4) || \
+    ((DURATION) == LCD_PulseOnDuration_5) || \
+    ((DURATION) == LCD_PulseOnDuration_6) || \
+    ((DURATION) == LCD_PulseOnDuration_7))
+    
+/**
+  * @}
+  */
+  
+/** @defgroup LCD_Dead_Time
+  * @brief element values correspond to the bits position
+  * @{
+  */
+typedef enum {
+  LCD_DeadTime_0 = (uint8_t)0x00, /*!< No dead Time  */
+  LCD_DeadTime_1 = (uint8_t)0x01, /*!< One Phase between different couple of Frame   */
+  LCD_DeadTime_2 = (uint8_t)0x02, /*!< Two Phase between different couple of Frame   */
+  LCD_DeadTime_3 = (uint8_t)0x03, /*!< Tree Phase between different couple of Frame  */
+  LCD_DeadTime_4 = (uint8_t)0x04, /*!< Four Phase between different couple of Frame  */
+  LCD_DeadTime_5 = (uint8_t)0x05, /*!< Five Phase between different couple of Frame  */
+  LCD_DeadTime_6 = (uint8_t)0x06, /*!< Six Phase between different couple of Frame   */
+  LCD_DeadTime_7 = (uint8_t)0x07  /*!< Seven Phase between different couple of Frame */
+} LCD_DeadTime_TypeDef;
+
+#define IS_LCD_DEAD_TIME(TIME) (((TIME) == LCD_DeadTime_0) || \
+                                ((TIME) == LCD_DeadTime_1) || \
+                                ((TIME) == LCD_DeadTime_2) || \
+                                ((TIME) == LCD_DeadTime_3) || \
+                                ((TIME) == LCD_DeadTime_4) || \
+                                ((TIME) == LCD_DeadTime_5) || \
+                                ((TIME) == LCD_DeadTime_6) || \
+                                ((TIME) == LCD_DeadTime_7))
+                                
+/**
+  * @}
+  */
+  
+/** @defgroup LCD_BlinkMode 
+  * @{
+  */
+typedef enum {
+  LCD_BlinkMode_Off           = (uint8_t)0x00, /*!< Blink inactive            */
+  LCD_BlinkMode_SEG0_COM0     = (uint8_t)0x40, /*!< SEG0 on COM0 blink        */
+  LCD_BlinkMode_SEG0_AllCOM   = (uint8_t)0x80, /*!< SEG0 on All COM blink     */
+  LCD_BlinkMode_AllSEG_AllCOM = (uint8_t)0xC0  /*!< All SEG on All COm Blink  */
+} LCD_BlinkMode_TypeDef;
+
+#define IS_LCD_BLINK_MODE(BLINK) (((BLINK) == LCD_BlinkMode_Off) || \
+                                  ((BLINK) == LCD_BlinkMode_SEG0_COM0) || \
+                                  ((BLINK) == LCD_BlinkMode_SEG0_AllCOM) || \
+                                  ((BLINK) == LCD_BlinkMode_AllSEG_AllCOM))
+                                  
+/**
+  * @}
+  */
+  
+/** @defgroup LCD_Blink_Frequency
+  * @brief element values correspond to the bits position
+  * @{
+  */
+typedef enum {
+  LCD_BlinkFrequency_Div8    = (uint8_t)0x00, /*!< The Blink frequency = fLcd/8    */
+  LCD_BlinkFrequency_Div16   = (uint8_t)0x08, /*!< The Blink frequency = fLcd/16   */
+  LCD_BlinkFrequency_Div32   = (uint8_t)0x10, /*!< The Blink frequency = fLcd/32   */
+  LCD_BlinkFrequency_Div64   = (uint8_t)0x18, /*!< The Blink frequency = fLcd/64   */
+  LCD_BlinkFrequency_Div128  = (uint8_t)0x20, /*!< The Blink frequency = fLcd/128  */
+  LCD_BlinkFrequency_Div256  = (uint8_t)0x28, /*!< The Blink frequency = fLcd/256  */
+  LCD_BlinkFrequency_Div512  = (uint8_t)0x30, /*!< The Blink frequency = fLcd/512  */
+  LCD_BlinkFrequency_Div1024 = (uint8_t)0x38  /*!< The Blink frequency = fLcd/1024 */
+} LCD_BlinkFrequency_TypeDef;
+
+#define IS_LCD_BLINK_FREQUENCY(BLINKF) (((BLINKF) == LCD_BlinkFrequency_Div8) || \
+                                        ((BLINKF) == LCD_BlinkFrequency_Div16) || \
+                                        ((BLINKF) == LCD_BlinkFrequency_Div32) || \
+                                        ((BLINKF) == LCD_BlinkFrequency_Div64) || \
+                                        ((BLINKF) == LCD_BlinkFrequency_Div128) || \
+                                        ((BLINKF) == LCD_BlinkFrequency_Div256) || \
+                                        ((BLINKF) == LCD_BlinkFrequency_Div512) || \
+                                        ((BLINKF) == LCD_BlinkFrequency_Div1024))
+/**
+  * @}
+  */
+  
+/** @defgroup LCD_RAMRegister 
+  * @{
+  */
+typedef enum {
+  LCD_RAMRegister_0   = (uint8_t)0x00,  /*!< RAM Register 0  */
+  LCD_RAMRegister_1   = (uint8_t)0x01,  /*!< RAM Register 1  */
+  LCD_RAMRegister_2   = (uint8_t)0x02,  /*!< RAM Register 2  */
+  LCD_RAMRegister_3   = (uint8_t)0x03,  /*!< RAM Register 3  */
+  LCD_RAMRegister_4   = (uint8_t)0x04,  /*!< RAM Register 4  */
+  LCD_RAMRegister_5   = (uint8_t)0x05,  /*!< RAM Register 5  */
+  LCD_RAMRegister_6   = (uint8_t)0x06,  /*!< RAM Register 6  */
+  LCD_RAMRegister_7   = (uint8_t)0x07,  /*!< RAM Register 7  */
+  LCD_RAMRegister_8   = (uint8_t)0x08,  /*!< RAM Register 8  */
+  LCD_RAMRegister_9   = (uint8_t)0x09,  /*!< RAM Register 9  */
+  LCD_RAMRegister_10  = (uint8_t)0x0A,  /*!< RAM Register 10 */
+  LCD_RAMRegister_11  = (uint8_t)0x0B,  /*!< RAM Register 11 */
+  LCD_RAMRegister_12  = (uint8_t)0x0C,  /*!< RAM Register 12 */
+  LCD_RAMRegister_13  = (uint8_t)0x0D,  /*!< RAM Register 13 */
+  LCD_RAMRegister_14  = (uint8_t)0x0E,  /*!< RAM Register 14 */
+  LCD_RAMRegister_15  = (uint8_t)0x0F,  /*!< RAM Register 15 */
+  LCD_RAMRegister_16  = (uint8_t)0x10,  /*!< RAM Register 16 */
+  LCD_RAMRegister_17  = (uint8_t)0x11,  /*!< RAM Register 17 */
+  LCD_RAMRegister_18  = (uint8_t)0x12,  /*!< RAM Register 18 */
+  LCD_RAMRegister_19  = (uint8_t)0x13,  /*!< RAM Register 19 */
+  LCD_RAMRegister_20  = (uint8_t)0x14,  /*!< RAM Register 20 */
+  LCD_RAMRegister_21  = (uint8_t)0x15   /*!< RAM Register 21 */
+} LCD_RAMRegister_TypeDef;
+
+#define IS_LCD_RAM_REGISTER(REGISTER) (((REGISTER) == LCD_RAMRegister_0) || \
+                                       ((REGISTER) == LCD_RAMRegister_1) || \
+                                       ((REGISTER) == LCD_RAMRegister_2) || \
+                                       ((REGISTER) == LCD_RAMRegister_3) || \
+                                       ((REGISTER) == LCD_RAMRegister_4) || \
+                                       ((REGISTER) == LCD_RAMRegister_5) || \
+                                       ((REGISTER) == LCD_RAMRegister_6) || \
+                                       ((REGISTER) == LCD_RAMRegister_7) || \
+                                       ((REGISTER) == LCD_RAMRegister_8) || \
+                                       ((REGISTER) == LCD_RAMRegister_9) || \
+                                       ((REGISTER) == LCD_RAMRegister_10) || \
+                                       ((REGISTER) == LCD_RAMRegister_11) || \
+                                       ((REGISTER) == LCD_RAMRegister_12) || \
+                                       ((REGISTER) == LCD_RAMRegister_13) || \
+                                       ((REGISTER) == LCD_RAMRegister_14) || \
+                                       ((REGISTER) == LCD_RAMRegister_15) || \
+                                       ((REGISTER) == LCD_RAMRegister_16) || \
+                                       ((REGISTER) == LCD_RAMRegister_17) || \
+                                       ((REGISTER) == LCD_RAMRegister_18) || \
+                                       ((REGISTER) == LCD_RAMRegister_19) || \
+                                       ((REGISTER) == LCD_RAMRegister_20) || \
+                                       ((REGISTER) == LCD_RAMRegister_21))
+                                       
+/**
+  * @}
+  */
+  
+/** @defgroup LCD_Port_Mask_Register
+  * @{
+  */
+typedef enum {
+  LCD_PortMaskRegister_0 = (uint8_t)0x00,  /*!< PortMask Register 0  */
+  LCD_PortMaskRegister_1 = (uint8_t)0x01,  /*!< PortMask Register 1  */
+  LCD_PortMaskRegister_2 = (uint8_t)0x02,  /*!< PortMask Register 2  */
+  LCD_PortMaskRegister_3 = (uint8_t)0x03,  /*!< PortMask Register 3  */
+  LCD_PortMaskRegister_4 = (uint8_t)0x04,  /*!< PortMask Register 4  */
+  LCD_PortMaskRegister_5 = (uint8_t)0x05   /*!< PortMask Register 5  */
+} LCD_PortMaskRegister_TypeDef;
+
+#define IS_LCD_PORT_MASK(MASK) (((MASK) == LCD_PortMaskRegister_0) || \
+                                ((MASK) == LCD_PortMaskRegister_1) || \
+                                ((MASK) == LCD_PortMaskRegister_2) || \
+                                ((MASK) == LCD_PortMaskRegister_3) || \
+                                ((MASK) == LCD_PortMaskRegister_4) || \
+                                ((MASK) == LCD_PortMaskRegister_5))
+                                
+/**
+  * @}
+  */
+  
+/** @defgroup LCD_Page_Selection
+  * @{
+  */
+typedef enum {
+  LCD_PageSelection_FirstPage  = (uint8_t)0x00,  /*!< The LCD RAM is selected as the first page  */
+  LCD_PageSelection_SecondPage = (uint8_t)0x04   /*!< The LCD RAM is selected as the second page */
+} LCD_PageSelection_TypeDef;
+
+#define IS_LCD_PAGE_SELECT(PAGE) (((PAGE) == LCD_PageSelection_FirstPage) || \
+                                  ((PAGE) == LCD_PageSelection_SecondPage))
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+
+/* Private define ------------------------------------------------------------*/
+/* LCD Legacy defines */
+/** @defgroup LCD_Private_Define
+  * @ brief LCD Legacy defines
+  * @{
+  */
+#define LCD_Contrast_2V6   ((uint8_t)LCD_Contrast_Level_0)
+#define LCD_Contrast_2V7   ((uint8_t)LCD_Contrast_Level_1)
+#define LCD_Contrast_2V8   ((uint8_t)LCD_Contrast_Level_2)
+#define LCD_Contrast_2V9   ((uint8_t)LCD_Contrast_Level_3)
+#define LCD_Contrast_3V0   ((uint8_t)LCD_Contrast_Level_4)
+#define LCD_Contrast_3V1   ((uint8_t)LCD_Contrast_Level_5)
+#define LCD_Contrast_3V2   ((uint8_t)LCD_Contrast_Level_6)
+#define LCD_Contrast_3V3   ((uint8_t)LCD_Contrast_Level_7) 
+/**
+  * @}
+  */
+/* Private macros ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/*  Function used to set the LCD configuration to the default reset state *****/
+void LCD_DeInit(void);
+
+/* Initialization and Configuration functions *********************************/
+void LCD_Init(LCD_Prescaler_TypeDef LCD_Prescaler, LCD_Divider_TypeDef LCD_Divider,
+              LCD_Duty_TypeDef LCD_Duty, LCD_Bias_TypeDef LCD_Bias, LCD_VoltageSource_TypeDef LCD_VoltageSource);
+void LCD_PortMaskConfig(LCD_PortMaskRegister_TypeDef LCD_PortMaskRegister, uint8_t LCD_Mask);
+void LCD_Cmd(FunctionalState NewState);
+void LCD_HighDriveCmd(FunctionalState NewState);
+void LCD_PulseOnDurationConfig(LCD_PulseOnDuration_TypeDef LCD_PulseOnDuration);
+void LCD_DeadTimeConfig(LCD_DeadTime_TypeDef LCD_DeadTime);
+void LCD_BlinkConfig(LCD_BlinkMode_TypeDef LCD_BlinkMode, LCD_BlinkFrequency_TypeDef LCD_BlinkFrequency);
+void LCD_ContrastConfig(LCD_Contrast_TypeDef LCD_Contrast);
+
+/* LCD RAM memory write functions *********************************************/
+void LCD_WriteRAM(LCD_RAMRegister_TypeDef LCD_RAMRegister, uint8_t LCD_Data);
+void LCD_PageSelect(LCD_PageSelection_TypeDef LCD_PageSelection);
+
+/* Interrupts and flags management functions **********************************/
+void LCD_ITConfig(FunctionalState NewState);
+FlagStatus LCD_GetFlagStatus(void);
+void LCD_ClearFlag(void);
+ITStatus LCD_GetITStatus(void);
+void LCD_ClearITPendingBit(void);
+
+#endif /* __STM8L15x_LCD_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_pwr.h b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_pwr.h
new file mode 100755
index 0000000..04b8bb3
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_pwr.h
@@ -0,0 +1,128 @@
+/**
+  ******************************************************************************
+  * @file    stm8l15x_pwr.h
+  * @author  MCD Application Team
+  * @version V1.6.0
+  * @date    28-June-2013
+  * @brief   This file contains all the functions prototypes for the PWR firmware
+  *          library.
+  ******************************************************************************
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ****************************************************************************** 
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM8L15x_PWR_H
+#define __STM8L15x_PWR_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm8l15x.h"
+
+/** @addtogroup STM8L15x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup PWR
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup PWR_Exported_Types
+  * @{
+  */
+
+/** @defgroup PVD_detection_level 
+  * @{
+  */
+
+typedef enum {
+  PWR_PVDLevel_1V85  = (uint8_t)0x00, /*!< PVD threshold = 1.85 V */
+  PWR_PVDLevel_2V05  = (uint8_t)0x02, /*!< PVD threshold = 2.05 V */
+  PWR_PVDLevel_2V26  = (uint8_t)0x04, /*!< PVD threshold = 2.26 V */
+  PWR_PVDLevel_2V45  = (uint8_t)0x06, /*!< PVD threshold = 2.45 V */
+  PWR_PVDLevel_2V65  = (uint8_t)0x08, /*!< PVD threshold = 2.65 V */
+  PWR_PVDLevel_2V85  = (uint8_t)0x0A, /*!< PVD threshold = 2.85 V */
+  PWR_PVDLevel_3V05  = (uint8_t)0x0C, /*!< PVD threshold = 3.05 V */
+  PWR_PVDLevel_PVDIn = (uint8_t)0x0E  /*!< PVD threshold = PVD_IN input pin */
+} PWR_PVDLevel_TypeDef;
+
+#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_1V85) || \
+                                 ((LEVEL) == PWR_PVDLevel_2V05) || \
+                                 ((LEVEL) == PWR_PVDLevel_2V26) || \
+                                 ((LEVEL) == PWR_PVDLevel_2V45) || \
+                                 ((LEVEL) == PWR_PVDLevel_2V65) || \
+                                 ((LEVEL) == PWR_PVDLevel_2V85) || \
+                                 ((LEVEL) == PWR_PVDLevel_3V05) || \
+                                 ((LEVEL) == PWR_PVDLevel_PVDIn))
+/**
+  * @}
+  */
+  
+/** @defgroup PWR_Flag 
+  * @{
+  */
+  
+typedef enum {
+  PWR_FLAG_PVDOF    = (uint8_t)0x40,/*!< PVD output flag */
+  PWR_FLAG_PVDIF    = (uint8_t)0x20, /*!< PVD Interrupt flag */
+  PWR_FLAG_VREFINTF = (uint8_t)0x01  /*!< Internal reference voltage status flag */
+} PWR_FLAG_TypeDef;
+
+#define IS_PWR_FLAG(FLAG)   (((FLAG) == PWR_FLAG_PVDOF) || \
+                             ((FLAG) == PWR_FLAG_PVDIF) || \
+                             ((FLAG) == PWR_FLAG_VREFINTF))
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+  
+/* Exported constants --------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/* Function used to set the PWR configuration to the default reset state ******/ 
+void PWR_DeInit(void);
+
+/* PVD configuration functions ************************************************/ 
+void PWR_PVDLevelConfig(PWR_PVDLevel_TypeDef PWR_PVDLevel);
+void PWR_PVDCmd(FunctionalState NewState);
+
+/* Ultra Low Power mode configuration functions *******************************/ 
+void PWR_FastWakeUpCmd(FunctionalState NewState);
+void PWR_UltraLowPowerCmd(FunctionalState NewState);
+
+/* Interrupts and flags management functions **********************************/
+void PWR_PVDITConfig(FunctionalState NewState);
+ITStatus PWR_PVDGetITStatus(void);
+FlagStatus PWR_GetFlagStatus(PWR_FLAG_TypeDef PWR_FLAG);
+void PWR_PVDClearFlag(void);
+void PWR_PVDClearITPendingBit(void);
+
+#endif /* __STM8L15x_PWR_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_rst.h b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_rst.h
new file mode 100755
index 0000000..8d3b0be
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_rst.h
@@ -0,0 +1,88 @@
+/**
+  ******************************************************************************
+  * @file    stm8l15x_rst.h
+  * @author  MCD Application Team
+  * @version V1.6.0
+  * @date    28-June-2013
+  * @brief   This file contains all the functions prototypes for the RST firmware
+  *          library.
+  ******************************************************************************
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ****************************************************************************** 
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM8L15x_RST_H
+#define __STM8L15x_RST_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm8l15x.h"
+
+/** @addtogroup STM8L15x_StdPeriph_Driver
+  * @{
+  */
+  
+/** @addtogroup RST
+  * @{
+  */ 
+  
+/* Exported variables ------------------------------------------------------- */
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup RST_Exported_Types
+  * @{
+  */
+
+/** @defgroup RST_Flags 
+  * @{
+  */
+typedef enum {
+  RST_FLAG_PORF   = (uint8_t)0x01, /*!< POR reset flag */
+  RST_FLAG_SWIMF  = (uint8_t)0x08, /*!< SWIM reset flag */
+  RST_FLAG_ILLOPF = (uint8_t)0x04, /*!< Illegal opcode reset flag */
+  RST_FLAG_IWDGF  = (uint8_t)0x02, /*!< Independent watchdog reset flag */
+  RST_FLAG_WWDGF  = (uint8_t)0x10, /*!< Window watchdog reset flag */
+  RST_FLAG_BORF   = (uint8_t)0x20  /*!< BOR reset flag */
+} RST_FLAG_TypeDef;
+
+#define IS_RST_FLAG(FLAG)  (((FLAG) == RST_FLAG_PORF) || ((FLAG) == RST_FLAG_BORF) || \
+                            ((FLAG) == RST_FLAG_IWDGF) || ((FLAG) == RST_FLAG_ILLOPF) || \
+                            ((FLAG) == RST_FLAG_WWDGF) || ((FLAG) == RST_FLAG_SWIMF))
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+/* Exported constants --------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+/* Flag management functions **************************************************/
+FlagStatus RST_GetFlagStatus(RST_FLAG_TypeDef RST_Flag);
+void RST_ClearFlag(RST_FLAG_TypeDef RST_Flag);
+
+/* NRST Pin configuration function ********************************************/
+void RST_GPOutputEnable(void);
+
+#endif /* __STM8L15x_RST_H */
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_rtc.h b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_rtc.h
new file mode 100755
index 0000000..eea8f9f
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_rtc.h
@@ -0,0 +1,953 @@
+/**
+  ******************************************************************************
+  * @file    stm8l15x_rtc.h
+  * @author  MCD Application Team
+  * @version V1.6.0
+  * @date    28-June-2013
+  * @brief   This file contains all the functions prototypes for the RTC 
+  *          firmware library.
+  ******************************************************************************
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ****************************************************************************** 
+  */
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM8L15x_RTC_H
+#define __STM8L15x_RTC_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm8l15x.h"
+
+/** @addtogroup STM8L15x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup RTC
+  * @{
+  */ 
+  
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup RTC_Exported_Types
+  * @{
+  */
+
+/** @defgroup RTC_Weekdays
+  * @{
+  */ 
+typedef enum
+{
+  RTC_Weekday_Monday      =  ((uint8_t)0x01), /*!< WeekDay is Monday */
+  RTC_Weekday_Tuesday     =  ((uint8_t)0x02), /*!< WeekDay is Tuesday */
+  RTC_Weekday_Wednesday   =  ((uint8_t)0x03), /*!< WeekDay is Wednesday */
+  RTC_Weekday_Thursday    =  ((uint8_t)0x04), /*!< WeekDay is Thursday */
+  RTC_Weekday_Friday      =  ((uint8_t)0x05), /*!< WeekDay is Friday */
+  RTC_Weekday_Saturday    =  ((uint8_t)0x06), /*!< WeekDay is Saturday */
+  RTC_Weekday_Sunday      =  ((uint8_t)0x07)  /*!< WeekDay is Sunday */
+}
+RTC_Weekday_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup RTC_Months
+  * @{
+  */ 
+typedef enum
+{
+  RTC_Month_January   =  ((uint8_t)0x01), /*!< Month is January */
+  RTC_Month_February  =  ((uint8_t)0x02), /*!< Month is February */
+  RTC_Month_March     =  ((uint8_t)0x03), /*!< Month is March */
+  RTC_Month_April     =  ((uint8_t)0x04), /*!< Month is April */
+  RTC_Month_May       =  ((uint8_t)0x05), /*!< Month is May */
+  RTC_Month_June      =  ((uint8_t)0x06), /*!< Month is June */
+  RTC_Month_July      =  ((uint8_t)0x07), /*!< Month is July */
+  RTC_Month_August    =  ((uint8_t)0x08), /*!< Month is August */
+  RTC_Month_September =  ((uint8_t)0x09), /*!< Month is September */
+  RTC_Month_October   =  ((uint8_t)0x10), /*!< Month is October */
+  RTC_Month_November  =  ((uint8_t)0x11), /*!< Month is November */
+  RTC_Month_December  =  ((uint8_t)0x12)  /*!< Month is December */
+}
+RTC_Month_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup RTC_Hour_Format
+  * @{
+  */ 
+typedef enum
+{
+  RTC_HourFormat_24  = ((uint8_t)0x00), /*!< Hour Format is 24H */
+  RTC_HourFormat_12  = ((uint8_t)0x40)  /*!< Hour Format is 12H (using AM/PM) */
+}
+RTC_HourFormat_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup RTC_Time
+  * @{
+  */ 
+typedef enum
+{
+  RTC_H12_AM     = ((uint8_t)0x00), /*!< AM/PM notation is AM or 24 hour format */
+  RTC_H12_PM     = ((uint8_t)0x40)  /*!< AM/PM notation is PM  */
+}
+RTC_H12_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup RTC_Alarm_WeekDay_Selection
+  * @{
+  */ 
+typedef enum
+{
+  RTC_AlarmDateWeekDaySel_Date     = ((uint8_t)0x00), /*!< Date/WeekDay selection is Date */
+  RTC_AlarmDateWeekDaySel_WeekDay  = ((uint8_t)0x40)  /*!< Date/WeekDay selection is WeekDay */
+}
+RTC_AlarmDateWeekDaySel_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup RTC_Alarm_Mask
+  * @{
+  */ 
+typedef enum
+{
+  RTC_AlarmMask_None         =  ((uint8_t)0x00), /*!< Alarm Masks disabled */
+  RTC_AlarmMask_Seconds      =  ((uint8_t)0x80), /*!< Alarm Seconds Mask */
+  RTC_AlarmMask_Minutes      =  ((uint8_t)0x40), /*!< Alarm Minutes Mask */
+  RTC_AlarmMask_Hours        =  ((uint8_t)0x20), /*!< Alarm Hours Mask */
+  RTC_AlarmMask_DateWeekDay  =  ((uint8_t)0x10), /*!< Alarm Date/WeekDay Mask */
+  RTC_AlarmMask_All          =  ((uint8_t)0xF0)  /*!< Alarm All Mask are enabled */
+}
+RTC_AlarmMask_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup RTC_Sub_Second_Alarm_Mask
+  * @{
+  */ 
+typedef enum
+{
+  RTC_AlarmSubSecondMask_All      =  ((uint8_t)0x00), /*!< All Alarm SS fields are masked. There is no comparison on sub seconds for Alarm */
+  RTC_AlarmSubSecondMask_None     =  ((uint8_t)0x0F), /*!< SS[14:0] are compared and must match to activate alarm. */
+  RTC_AlarmSubSecondMask_SS14_1   =  ((uint8_t)0x01), /*!< SS[14:1] are not used in Alarm comparison. Only SS[0] is compared. */
+  RTC_AlarmSubSecondMask_SS14_2   =  ((uint8_t)0x02), /*!< SS[14:2] are not used in Alarm comparison. Only SS[1:0] are compared */
+  RTC_AlarmSubSecondMask_SS14_3   =  ((uint8_t)0x03), /*!< SS[14:3] are not used in Alarm comparison. Only SS[1:0] are compared */
+  RTC_AlarmSubSecondMask_SS14_4   =  ((uint8_t)0x04), /*!< SS[14:4] are not used in Alarm comparison. Only SS[1:0] are compared */
+  RTC_AlarmSubSecondMask_SS14_5   =  ((uint8_t)0x05), /*!< SS[14:5] are not used in Alarm comparison. Only SS[1:0] are compared */
+  RTC_AlarmSubSecondMask_SS14_6   =  ((uint8_t)0x06), /*!< SS[14:6] are not used in Alarm comparison. Only SS[1:0] are compared */
+  RTC_AlarmSubSecondMask_SS14_7   =  ((uint8_t)0x07), /*!< SS[14:7] are not used in Alarm comparison. Only SS[1:0] are compared */
+  RTC_AlarmSubSecondMask_SS14_8   =  ((uint8_t)0x08), /*!< SS[14:8] are not used in Alarm comparison. Only SS[1:0] are compared */
+  RTC_AlarmSubSecondMask_SS14_9   =  ((uint8_t)0x09), /*!< SS[14:9] are not used in Alarm comparison. Only SS[1:0] are compared */
+  RTC_AlarmSubSecondMask_SS14_10  =  ((uint8_t)0x0A), /*!< SS[14:10] are not used in Alarm comparison. Only SS[1:0] are compared */
+  RTC_AlarmSubSecondMask_SS14_11  =  ((uint8_t)0x0B), /*!< SS[14:11] are not used in Alarm comparison. Only SS[1:0] are compared */
+  RTC_AlarmSubSecondMask_SS14_12  =  ((uint8_t)0x0C), /*!< SS[14:12] are not used in Alarm comparison. Only SS[1:0] are compared */
+  RTC_AlarmSubSecondMask_SS14_13  =  ((uint8_t)0x0D), /*!< SS[14:13] are not used in Alarm comparison. Only SS[1:0] are compared */
+  RTC_AlarmSubSecondMask_SS14     =  ((uint8_t)0x0E) /*!< SS[14] is not used in Alarm comparison. Only SS[13:0] are compared */
+}
+RTC_AlarmSubSecondMask_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup RTC_Wakeup_Clock
+  * @{
+  */ 
+typedef enum
+{
+  RTC_WakeUpClock_RTCCLK_Div16    = ((uint8_t)0x00), /*!< (RTC clock) div 16*/
+  RTC_WakeUpClock_RTCCLK_Div8     = ((uint8_t)0x01), /*!< (RTC clock) div 8*/
+  RTC_WakeUpClock_RTCCLK_Div4     = ((uint8_t)0x02), /*!< (RTC clock) div 4*/
+  RTC_WakeUpClock_RTCCLK_Div2     = ((uint8_t)0x03), /*!< (RTC clock) div 2*/
+  RTC_WakeUpClock_CK_SPRE_16bits  = ((uint8_t)0x04), /*!< CK SPRE with a counter from 0x0000 to 0xFFFF */
+  RTC_WakeUpClock_CK_SPRE_17bits  = ((uint8_t)0x06)  /*!< CK SPRE with a counter from 0x10000 to 0x1FFFF */
+}
+RTC_WakeUpClock_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup RTC_Output_Selection
+  * @{
+  */ 
+typedef enum
+{
+  RTC_Output_Disable = ((uint8_t)0x00), /*!< RTC Alternate function Output is disabled  */
+  RTC_Output_Alarm   = ((uint8_t)0x20), /*!< RTC Alternate function Output is the Alarm A event*/
+  RTC_Output_WakeUp  = ((uint8_t)0x60)  /*!< RTC Alternate function Output is the WakeUp event */
+}
+RTC_Output_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup RTC_Output_Polarity
+  * @{
+  */ 
+typedef enum
+{
+  RTC_OutputPolarity_High  = ((uint8_t)0x00), /*!< RTC Alternate function Output Polarity is High  */
+  RTC_OutputPolarity_Low   = ((uint8_t)0x10)  /*!< RTC Alternate function Output Polarity is Low  */
+}
+RTC_OutputPolarity_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup RTC_Calibration_Output
+  * @{
+  */ 
+typedef enum
+{
+  RTC_CalibOutput_512Hz  = ((uint8_t)0x00), /*!< RTC Calibration Output is 512Hz */
+  RTC_CalibOutput_1Hz    = ((uint8_t)0x80)  /*!< RTC Calibration Output is 1Hz */
+}
+RTC_CalibOutput_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup RTC_DayLight_Saving
+  * @{
+  */ 
+typedef enum
+{
+  RTC_DayLightSaving_SUB1H  = ((uint8_t)0x02), /*!< Substract 1 hour to the current Time (Winter Time Adjustment) */
+  RTC_DayLightSaving_ADD1H  = ((uint8_t)0x01)  /*!< Add 1 hour to the current Time (Summer Time Adjustment) */
+}
+RTC_DayLightSaving_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup RTC_Store_Operation
+  * @{
+  */ 
+typedef enum
+{
+  RTC_StoreOperation_Set   = ((uint8_t)0x04), /*!< Store Operation Set */
+  RTC_StoreOperation_Reset = ((uint8_t)0x00)  /*!< Store Operation Reset */
+}
+RTC_StoreOperation_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup RTC_Input_Parameter_Format
+  * @{
+  */ 
+typedef enum
+{
+  RTC_Format_BIN  = ((uint8_t)0x00), /*!< Binary Format is used  */
+  RTC_Format_BCD  = ((uint8_t)0x01)  /*!< BCD Format is used  */
+}
+RTC_Format_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup RTC_Flags
+  * @{
+  */ 
+typedef enum
+{
+  RTC_FLAG_TAMP3F  = ((uint16_t)0x0080), /*!< TAMPER3 detection  Flag. If set, tamper detection event is detected on tamper input 3 */
+  RTC_FLAG_TAMP2F  = ((uint16_t)0x0040), /*!< TAMPER2 detection  Flag. If set, tamper detection event is detected on tamper input 2 */
+  RTC_FLAG_TAMP1F  = ((uint16_t)0x0020), /*!< TAMPER1 detection  Flag. If set, tamper detection event is detected on tamper input 1 */
+
+  RTC_FLAG_WUTF    = ((uint16_t)0x0004), /*!< Wake up Timer Flag. If set, the Wake Up down counter reaches 0 */
+  RTC_FLAG_ALRAF   = ((uint16_t)0x0001), /*!< Alarm A Flag. If set, the Time/Date registers matches Alarm A registers */
+
+  RTC_FLAG_INITF   = ((uint16_t)0x4000), /*!< Initialisation Flag. If set,Calender registers has been initialized  */
+  RTC_FLAG_RSF     = ((uint16_t)0x2000), /*!< Registers Synchronization Flag. If set,Calender registers synchronized  */
+  RTC_FLAG_INITS   = ((uint16_t)0x1000), /*!< Initialisation Status Flag. If set,Calender  update is allowed  */
+
+  RTC_FLAG_SHPF    = ((uint16_t)0x0800), /*!< Shift operation pending Flag. This flag is set by hardware as soon as a shift operation is
+                                              initiated by a write to the RTC_SHIFTRL. It is cleared by hardware as soon as the corresponding
+                                              shift operation has completed.  */
+
+  RTC_FLAG_WUTWF   = ((uint16_t)0x0400), /*!< Wake up Timer write Flag. If set, Wake up Timer update is allowed */
+  RTC_FLAG_RECALPF = ((uint16_t)0x0200), /*!<   Recalibration pending Flag, The status flag RECALPF is automatically set to ‘1’ when software
+                                                writes to the register RTC_CALRL, indicating that the RTC_CALRx registers are blocked.
+                                                When the new calibration settings are taken into account, this Flag returns by hardware to ‘0’. */
+  RTC_FLAG_ALRAWF  = ((uint16_t)0x0100)  /*!< Alarm  A write Flag. If set, Alarm A update is allowed   */
+}
+RTC_Flag_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup RTC_Interrupts
+  * @{
+  */ 
+typedef enum
+{
+  RTC_IT_WUT  = ((uint16_t)0x0040),  /*!< Wake up Timer Interrupt */
+  RTC_IT_ALRA = ((uint16_t)0x0010),  /*!< Alarm A Interrupt */
+  RTC_IT_TAMP = ((uint16_t)0x0F01)   /*!< Tamper Interrupt */
+}
+RTC_IT_TypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Tamper_Level
+  * @{
+  */ 
+typedef enum
+{
+  RTC_TamperLevel_Low    = ((uint8_t)0x00), /*!< Tamper staying low triggers a tamper detection event. */
+  RTC_TamperLevel_High   = ((uint8_t)0x54)  /*!< Tamper staying high triggers a tamper detection event. */
+}
+RTC_TamperLevel_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup RTC_Tamper_State
+  * @{
+  */ 
+typedef enum
+{
+  RTC_TamperState_Disable  = ((uint8_t)0x00), /*!< Tamper State is Disable */
+  RTC_TamperState_Enable   = ((uint8_t)0x01)  /*!< Tamper State is Enable  */
+}
+RTC_TamperState_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup RTC_Tamper_definition
+  * @{
+  */ 
+typedef enum
+{
+  RTC_Tamper_1 = ((uint8_t)0x02),  /*!< Tamper 1 selection */
+  RTC_Tamper_2 = ((uint8_t)0x08),  /*!< Tamper 2 selection */
+  RTC_Tamper_3 = ((uint8_t)0x20)   /*!< Tamper 3 selection */
+}
+RTC_Tamper_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup RTC_Tamper_Precharge_Duration
+  * @{
+  */ 
+typedef enum
+{
+  RTC_TamperPrechargeDuration_None    = ((uint8_t)0x80),  /*!< Tamper pins are not precharged before sampling */
+  RTC_TamperPrechargeDuration_1RTCCLK = ((uint8_t)0x00),  /*!< Tamper pins are precharged before sampling during 1 RTCCLK cycle  */
+  RTC_TamperPrechargeDuration_2RTCCLK = ((uint8_t)0x20),  /*!< Tamper pins are precharged before sampling during 2 RTCCLK cycles */
+  RTC_TamperPrechargeDuration_4RTCCLK = ((uint8_t)0x40),  /*!< Tamper pins are precharged before sampling during 4 RTCCLK cycles */
+  RTC_TamperPrechargeDuration_8RTCCLK = ((uint8_t)0x60)   /*!< Tamper pins are precharged before sampling during 8 RTCCLK cycles */
+}
+RTC_TamperPrechargeDuration_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup RTC_Tamper_Filter
+  * @{
+  */ 
+typedef enum
+{
+  RTC_TamperFilter_1Sample    = ((uint8_t)0x00), /*!< Tamper is activated after 1 sample at the active level */
+  RTC_TamperFilter_2Sample    = ((uint8_t)0x08), /*!< Tamper is activated after 2 consecutive samples at the active level. */
+  RTC_TamperFilter_4Sample    = ((uint8_t)0x10), /*!< Tamper is activated after 4 consecutive samples at the active level. */
+  RTC_TamperFilter_8Sample    = ((uint8_t)0x18)  /*!< Tamper is activated after 8 consecutive samples at the active level. */
+}
+RTC_TamperFilter_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup RTC_Tamper_Sampling_Frequency
+  * @{
+  */ 
+typedef enum
+{
+  RTC_TamperSamplingFreq_RTCCLK_Div32768  = ((uint8_t)0x00), /*!< Tamper inputs are sampled with a frequency =  RTCCLK / 32768 */
+  RTC_TamperSamplingFreq_RTCCLK_Div16384  = ((uint8_t)0x01), /*!< Tamper inputs are sampled with a frequency =  RTCCLK / 16384 */
+  RTC_TamperSamplingFreq_RTCCLK_Div8192   = ((uint8_t)0x02), /*!< Tamper inputs are sampled with a frequency =  RTCCLK / 8192  */
+  RTC_TamperSamplingFreq_RTCCLK_Div4096   = ((uint8_t)0x03), /*!< Tamper inputs are sampled with a frequency =  RTCCLK / 4096  */
+  RTC_TamperSamplingFreq_RTCCLK_Div2048   = ((uint8_t)0x04), /*!< Tamper inputs are sampled with a frequency =  RTCCLK / 2048  */
+  RTC_TamperSamplingFreq_RTCCLK_Div1024   = ((uint8_t)0x05), /*!< Tamper inputs are sampled with a frequency =  RTCCLK / 1024  */
+  RTC_TamperSamplingFreq_RTCCLK_Div512    = ((uint8_t)0x06), /*!< Tamper inputs are sampled with a frequency =  RTCCLK / 512   */
+  RTC_TamperSamplingFreq_RTCCLK_Div256    = ((uint8_t)0x07)  /*!< Tamper inputs are sampled with a frequency =  RTCCLK / 256   */
+}
+RTC_TamperSamplingFreq_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup RTC_Shift_Add_1s
+  * @{
+  */ 
+typedef enum
+{
+  RTC_ShiftAdd1S_Set    = ((uint8_t)0x80), /*!< Add 1 Second */
+  RTC_ShiftAdd1S_Reset  = ((uint8_t)0x00)  /*!< Do not Add 1 Second */
+}
+RTC_ShiftAdd1S_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup RTC_Smooth_Calibration_Period
+  * @{
+  */ 
+typedef enum
+{
+  RTC_SmoothCalibPeriod_32sec  = ((uint8_t)0x00), /*!<  if RTCCLK = 32768 Hz, Smooth calibration period is 32s,  else 2exp20 RTCCLK seconds */
+  RTC_SmoothCalibPeriod_16sec  = ((uint8_t)0x20), /*!<  if RTCCLK = 32768 Hz, Smooth calibration period is 16s, else 2exp19 RTCCLK seconds */
+  RTC_SmoothCalibPeriod_8sec   = ((uint8_t)0x40)  /*!<  if RTCCLK = 32768 Hz, Smooth calibration period is 8s, else 2exp18 RTCCLK seconds */
+}
+RTC_SmoothCalibPeriod_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup RTC_Smooth_Calibration_Pulses
+  * @{
+  */ 
+typedef enum
+{
+  RTC_SmoothCalibPlusPulses_Set    = ((uint8_t)0x80), /*!<  The number of RTCCLK pulses added during a X -second window =  Y  - CALM[8:0].  
+                                                             with Y = 512, 256, 128 when X = 32, 16, 8 */
+  RTC_SmoothCalibPlusPulses_Reset  = ((uint8_t)0x00)  /*!<  The number of RTCCLK pulses substituted during a 32-second window =  CALM[8:0]. */
+
+}
+RTC_SmoothCalibPlusPulses_TypeDef;
+
+/**
+  * @}
+  */
+
+/**
+  * @brief RTC Init structure definition
+  */
+
+typedef struct
+{
+
+  RTC_HourFormat_TypeDef RTC_HourFormat; /*!< RTC Hour Format */
+
+  uint8_t RTC_AsynchPrediv;   /*!< RTC Asynchronous Predivider.
+                                   This parameter can be any value from 
+                                   0x00 to 0x7F.*/
+
+  uint16_t RTC_SynchPrediv;   /*!< RTC Synchronous Predivider.
+                                   This parameter can be any value from 
+                                   0x0000 to 0x7FFF.*/
+}
+RTC_InitTypeDef;
+
+
+/**
+  * @brief RTC Time structure definition
+  */
+typedef struct
+{
+  uint8_t RTC_Hours;       /*!< RTC Hours.
+                            If Binary format is selected :
+                               - If RTC_Hour format is RTC_Hour format_12, 
+                                 this parameter can be any value from 1 to 12.
+                               - If RTC_Hour format is RTC_Hour format_24, 
+                                 this parameter can be any value from 0 to 23.
+                            If BCD format is selected :
+                               - If RTC_Hour format is RTC_Hour format_12, 
+                                 this parameter can be any BCD value from 
+                                 0x01 to 0x12.
+                               - If RTC_Hour format is RTC_Hour format_24, 
+                                 this parameter can be any BCD value  from 
+                                 0x00 to 0x23.*/
+  uint8_t RTC_Minutes;     /*!< RTC Minutes.
+                             If Binary format is selected, this parameter can
+                                be any value from 0 to 59.
+                             If BCD format is selected, this parameter can
+                                be any BCD value from 0x00 to 0x59.*/
+  uint8_t RTC_Seconds;     /*!< RTC Seconds.
+                             If Binary format is selected, this parameter can
+                                be any value from 0 to 59.
+                             If BCD format is selected, this parameter can
+                                be any BCD value from 0x00 to 0x59.*/
+  RTC_H12_TypeDef RTC_H12;  /*!< RTC 12-hour clock period (AM/PM) */
+}
+RTC_TimeTypeDef;
+
+/**
+  * @brief RTC Date structure definition
+  */
+typedef struct
+{
+  RTC_Weekday_TypeDef  RTC_WeekDay; /*!< The RTC Calender Weekday. */
+
+  RTC_Month_TypeDef RTC_Month;      /*!< The RTC Calender Month. */
+
+  uint8_t RTC_Date;                 /*!< The RTC Calender Date.
+                                      If Binary format is selected, this 
+                                         parameter can be any value from 1 to 31.
+                                      If BCD format is selected, this parameter
+                                         can be any BCD value from 0x01 to 0x31.*/
+
+  uint8_t RTC_Year;                 /*!< The RTC Calender Date.
+                                      If Binary format is selected, this parameter
+                                         can be any value from 0 to 99.
+                                      If BCD format is selected, this parameter
+                                         can be any BCD value from 0x00 to 0x99.*/
+}
+RTC_DateTypeDef;
+
+/**
+  * @brief RTC Alarm structure definition
+  */
+typedef struct
+{
+  RTC_TimeTypeDef RTC_AlarmTime;                           /*!< RTC Alarm Time */
+
+  uint8_t RTC_AlarmMask;                                   /*!< The RTC Alarm Fields Masks. */
+
+  RTC_AlarmDateWeekDaySel_TypeDef RTC_AlarmDateWeekDaySel; /*!< The RTC Alarm Date/WeekDay selection. */
+
+  uint8_t RTC_AlarmDateWeekDay;                            /*!< The RTC Alarm Date/WeekDay value.
+                                                               - If RTC Alarm Date/WeekDay selection is Date
+                                                                and if If Binary format is selected, this
+                                                                parameter can be any value from 1 to 31.
+                                                               - If RTC Alarm Date/WeekDay selection is WeekDay,
+                                                                 this parameter can be one of the
+                                                                 @ref RTC_Weekday_TypeDef enumeration.*/
+}
+RTC_AlarmTypeDef;
+  /**
+  * @}
+  */
+/* Exported constants --------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup RTC_Exported_Macros
+* @{
+*/
+
+/**
+  * @brief Macro used by the assert_param function in order to check the used 
+  *        Calender Hour format
+  */
+
+#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HourFormat_12) || \
+                                    ((FORMAT) == RTC_HourFormat_24))
+
+/**
+  * @brief Macro used by the assert_param function in order to check the used 
+  *        Asynchronous Predivider
+  */
+#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7F)
+
+/**
+  * @brief Macro used by the assert_param function in order to check the used 
+  *        Synchronous Predivider
+  */
+#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FFF)
+
+/**
+  * @brief Macro used by the assert_param function in order to check the used 
+  *        Calender Hours value (format 12h)
+  */
+#define IS_RTC_HOUR12_MAX(HOUR) ((HOUR) <= (uint8_t)12)
+#define IS_RTC_HOUR12_MIN(HOUR) ((HOUR) > (uint8_t)0)
+
+/**
+  * @brief Macro used by the assert_param function in order to check the used 
+  *        Calender Hours value (format 24h)
+  */
+#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23)
+
+/**
+  * @brief Macro used by the assert_param function in order to check the used 
+  *        Calender minutes value
+  */
+#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59)
+
+/**
+  * @brief Macro used by the assert_param function in order to check the used 
+  *        Calender seconds value
+  */
+#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59)
+
+/**
+  * @brief Macro used by the assert_param function in order to check the used 
+  *        Calender H12 mode
+  */
+#define IS_RTC_H12(PM) (((PM) == (RTC_H12_AM)) || ((PM) == (RTC_H12_PM)))
+
+
+/**
+  * @brief Macro used by the assert_param function in order to check the used 
+  *        Calender Year value
+  */
+#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99)
+
+/**
+  * @brief Macro used by the assert_param function in order to check the used 
+  *        Calender month value
+  */
+#define IS_RTC_MONTH_MAX(MONTH) ((MONTH) <= (uint8_t)12)
+#define IS_RTC_MONTH_MIN(MONTH) ((MONTH) >= (uint8_t)1)
+
+/**
+  * @brief Macro used by the assert_param function in order to check the used 
+  *        Calender Date value
+  */
+#define IS_RTC_DATE_MAX(DATE) ((DATE) <= (uint8_t)31)
+#define IS_RTC_DATE_MIN(DATE) ((DATE) >= (uint8_t)1)
+
+/**
+  * @brief Macro used by the assert_param function in order to check the used 
+  *        Calender Week day value
+  */
+#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) ==   RTC_Weekday_Monday)    || \
+                                 ((WEEKDAY) ==   RTC_Weekday_Tuesday)   || \
+                                 ((WEEKDAY) ==   RTC_Weekday_Wednesday) || \
+                                 ((WEEKDAY) ==   RTC_Weekday_Thursday)  || \
+                                 ((WEEKDAY) ==   RTC_Weekday_Friday)    || \
+                                 ((WEEKDAY) ==   RTC_Weekday_Saturday)  || \
+                                 ((WEEKDAY) ==   RTC_Weekday_Sunday))
+
+/**
+  * @brief Macro used by the assert_param function in order to check the used 
+  *        Alarm Date/week day  selection
+  */
+#define IS_RTC_ALARM_DATEWEEKDAY_SEL(SEL) (((SEL) == RTC_AlarmDateWeekDaySel_Date) || \
+                                           ((SEL) == RTC_AlarmDateWeekDaySel_WeekDay))
+
+/**
+  * @brief Macro used by the assert_param function in order to check the used 
+  *        Alarm Mask
+  */
+#define IS_RTC_ALARM_MASK(MASK) (((MASK) & 0x0F) == (uint8_t)(RESET))
+
+/**
+  * @brief Macro used by the assert_param function in order to check the used 
+  *        wakeup clock source
+  */
+#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WakeUpClock_RTCCLK_Div16) || \
+                                    ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div8)  || \
+                                    ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div4)  || \
+                                    ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div2)  || \
+                                    ((CLOCK) == RTC_WakeUpClock_CK_SPRE_16bits) || \
+                                    ((CLOCK) == RTC_WakeUpClock_CK_SPRE_17bits))
+
+/**
+  * @brief Macro used by the assert_param function in order to check the used 
+  *        Output selection
+  */
+#define IS_RTC_OUTPUT_SEL(SEL) (((SEL) == RTC_Output_Disable) || \
+                                ((SEL) == RTC_Output_Alarm) || \
+                                ((SEL) == RTC_Output_WakeUp))
+/**
+  * @brief Macro used by the assert_param function in order to check the used 
+  *        Output polarity
+  */
+#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OutputPolarity_High) || \
+                                ((POL) == RTC_OutputPolarity_Low))
+
+/**
+  * @brief Macro used by the assert_param function in order to check the used 
+  *        Daylight saving mode
+  */
+#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) ==  RTC_DayLightSaving_SUB1H) || \
+                                      ((SAVE) == RTC_DayLightSaving_ADD1H))
+
+/**
+  * @brief Macro used by the assert_param function in order to check the used 
+  *        Store Operation status
+  */
+#define IS_RTC_STORE_OPERATION(OP) (((OP) ==  RTC_StoreOperation_Set) || \
+                                    ((OP) == RTC_StoreOperation_Reset))
+
+
+/**
+  * @brief Macro used by the assert_param function in order to check the used 
+  *        format (bin/bcd) for data user insert
+  */
+#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_Format_BIN) || \
+                               ((FORMAT) == RTC_Format_BCD))
+
+/**
+  * @brief Macro used by the assert_param function in order to check the used 
+  *        Flag to get
+  */
+#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_WUTF)  || \
+                               ((FLAG) == RTC_FLAG_ALRAF) || \
+                               ((FLAG) == RTC_FLAG_INITF) || \
+                               ((FLAG) == RTC_FLAG_RSF)   || \
+                               ((FLAG) == RTC_FLAG_INITS) || \
+                               ((FLAG) == RTC_FLAG_WUTWF) || \
+                               ((FLAG) == RTC_FLAG_TAMP3F)|| \
+                               ((FLAG) == RTC_FLAG_TAMP2F)|| \
+                               ((FLAG) == RTC_FLAG_TAMP1F)|| \
+                               ((FLAG) == RTC_FLAG_SHPF)  || \
+                               ((FLAG) == RTC_FLAG_RECALPF) || \
+                               ((FLAG) == RTC_FLAG_ALRAWF))
+
+/* RTC_FLAG_ALRAWF is for Medium Density only but supported by High Density 
+   Devices*/
+
+/**
+  * @brief Macro used by the assert_param function in order to check the used 
+  *        Flag to clear
+  */
+#define RTC_FLAG_CLRBLE (RTC_FLAG_RSF | RTC_FLAG_ALRAF | RTC_FLAG_WUTF| RTC_FLAG_TAMP1F|RTC_FLAG_TAMP2F|RTC_FLAG_TAMP3F)
+#define IS_RTC_CLEAR_FLAG(FLAG) (((FLAG) != RESET) && ((uint16_t)((FLAG) & (uint16_t)(~(RTC_FLAG_CLRBLE))) == RESET))
+
+/**
+  * @brief Macro used by the assert_param function in order to check the used 
+  *       Interrupt to configure
+  */
+#define IS_RTC_CONFIG_IT(IT) (((uint16_t)(IT) != (uint8_t)RESET) && ((uint16_t)((uint16_t)(IT) & (uint16_t)(~(uint16_t)(RTC_IT_WUT|RTC_IT_ALRA|RTC_IT_TAMP))) == (uint8_t)RESET))
+
+/**
+  * @brief Macro used by the assert_param function in order to check the used 
+  *        Interrupt to get
+  */
+#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_WUT) || \
+                           ((IT) == RTC_IT_ALRA)|| \
+                           ((IT) == RTC_IT_TAMP) )
+
+/**
+  * @brief Macro used by the assert_param function in order to check the used 
+  *        Interrupt to clear
+  */
+#define IS_RTC_CLEAR_IT(IT)  (((IT) != RESET) && ((uint16_t)((IT) & (uint16_t)(~(uint16_t)(RTC_IT_WUT|RTC_IT_ALRA|RTC_IT_TAMP))) == RESET))
+
+/**
+  * @brief Macro used by the assert_param function in order to check the used 
+  *        Tamper Levels
+  */
+#define IS_RTC_TAMPER_LEVEL(LEVEL) (((LEVEL) == RTC_TamperLevel_Low) || \
+                                    ((LEVEL) == RTC_TamperLevel_High))
+
+/**
+  * @brief Macro used by the assert_param function in order to check the used 
+  *       Tamper
+  */
+#define NOT_CORRECT_TAMPER  (uint8_t)~(uint8_t)( RTC_Tamper_1 | \
+                                                 RTC_Tamper_2 | \
+                                                 RTC_Tamper_3)
+#define IS_RTC_TAMPER(TAMPER) (((uint8_t)((TAMPER) & NOT_CORRECT_TAMPER) == RESET) && ((TAMPER) != RESET))
+
+/**
+  * @brief Macro used by the assert_param function in order to check the used 
+  *        Tampers Filter
+  */
+#define IS_RTC_TAMPER_FILTER(SEL) (((SEL) == RTC_TamperFilter_1Sample) || \
+                                   ((SEL) == RTC_TamperFilter_2Sample) || \
+                                   ((SEL) == RTC_TamperFilter_4Sample) || \
+                                   ((SEL) == RTC_TamperFilter_8Sample))
+
+/**
+  * @brief Macro used by the assert_param function in order to check the used 
+  *        Tampers Sampling Frequencies
+  */
+#define IS_RTC_TAMPER_SAMPLING_FREQ(SEL) ((SEL) <= RTC_TamperSamplingFreq_RTCCLK_Div256)
+
+
+/**
+  * @brief Macro used by the assert_param function in order to check the used 
+  *        Tampers Pins precharge duration
+  */
+#define IS_RTC_TAMPER_PINS_PRECHAR_DURATION(SEL) (((SEL) == RTC_TamperPrechargeDuration_None) || \
+                                                  ((SEL) == RTC_TamperPrechargeDuration_1RTCCLK) || \
+                                                  ((SEL) == RTC_TamperPrechargeDuration_2RTCCLK) || \
+                                                  ((SEL) == RTC_TamperPrechargeDuration_4RTCCLK) || \
+                                                  ((SEL) == RTC_TamperPrechargeDuration_8RTCCLK))
+
+/**
+  * @brief Macro used by the assert_param function in order to check the used 
+  *        Smooth calibration period
+  */
+#define  IS_RTC_SMOOTH_CALIB_PERIOD(SEL) (((SEL) == RTC_SmoothCalibPeriod_32sec) || \
+                                          ((SEL) == RTC_SmoothCalibPeriod_16sec) || \
+                                          ((SEL) == RTC_SmoothCalibPeriod_8sec))
+    
+/**
+  * @brief Macro used by the assert_param function in order to check the used 
+  *        Smooth calibration Plus pulses
+  */
+#define  IS_RTC_SMOOTH_CALIB_PLUS(SEL) (((SEL) == RTC_SmoothCalibPlusPulses_Set) || \
+                                        ((SEL) == RTC_SmoothCalibPlusPulses_Reset))
+/**
+  * @brief Macro used by the assert_param function in order to check the used  
+  *        Smooth calibration Minus  pulses
+  */
+#define  IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x01FF)
+
+/**
+  * @brief Macro used by the assert_param function in order to check the used 
+  *        Output Selection
+  */
+#define  IS_RTC_OUTPUT_SELECT(SEL) (((SEL) == RTC_Output_Disable) || \
+                                    ((SEL) == RTC_Output_Alarm) || \
+                                    ((SEL) == RTC_Output_WakeUp))
+
+/**
+  * @brief Macro used by the assert_param function in order to check the 
+  *        used calibration Output Selection
+  */
+#define  IS_RTC_CALOUTPUT_SELECT(SEL) (((SEL) == RTC_CalibOutput_512Hz) || \
+                                       ((SEL) == RTC_CalibOutput_1Hz))
+                                       
+/**
+  * @brief Macro used by the assert_param function in order to check the used 
+  *        Alarm sub second value
+  */
+#define IS_RTC_ALARM_SS_VALUE(SS) ((SS) <= 0x7FFF)
+
+/**
+  * @brief Macro used by the assert_param function in order to check the used 
+  *        Alarm sub second mask
+  */
+#define IS_RTC_ALARM_SS_MASK(MASK) ((MASK) <= 0x0F)
+
+/**
+  * @brief Macro used by the assert_param function in order to check the used 
+  *        fraction of seconds to sub
+  */
+#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x7FFF)
+
+/**
+  * @brief Macro used by the assert_param function in order to check the 
+  *        parameter of 1 second to add
+  */
+#define IS_RTC_SHIFT_ADD1S(VAL) (((VAL) == RTC_ShiftAdd1S_Set) || \
+                                 ((VAL) == RTC_ShiftAdd1S_Reset))
+                                 
+/**
+  * @}
+  */
+/* Exported functions ------------------------------------------------------- */
+
+/*  Function used to set the RTC configuration to the default reset state *****/ 
+ErrorStatus RTC_DeInit(void);
+
+/* Initialization and Configuration functions *********************************/ 
+ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct);
+void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct);
+void RTC_WriteProtectionCmd(FunctionalState NewState);
+ErrorStatus RTC_EnterInitMode(void);
+void RTC_ExitInitMode(void);
+ErrorStatus RTC_WaitForSynchro(void);
+void RTC_RatioCmd(FunctionalState NewState);
+void RTC_BypassShadowCmd(FunctionalState NewState);
+
+/* Time and Date configuration functions **************************************/ 
+ErrorStatus RTC_SetTime(RTC_Format_TypeDef RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct);
+void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct);
+void RTC_GetTime(RTC_Format_TypeDef RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct);
+uint16_t RTC_GetSubSecond(void);
+ErrorStatus RTC_SetDate(RTC_Format_TypeDef RTC_Format, RTC_DateTypeDef* RTC_DateStruct);
+void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct);
+void RTC_GetDate(RTC_Format_TypeDef RTC_Format, RTC_DateTypeDef* RTC_DateStruct);
+
+/* Alarm configuration functions  *********************************************/ 
+void RTC_SetAlarm(RTC_Format_TypeDef RTC_Format,  RTC_AlarmTypeDef* RTC_AlarmStruct);
+void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct);
+void RTC_GetAlarm(RTC_Format_TypeDef RTC_Format,  RTC_AlarmTypeDef* RTC_AlarmStruct);
+ErrorStatus RTC_AlarmCmd(FunctionalState NewState);
+ErrorStatus RTC_AlarmSubSecondConfig(uint16_t RTC_AlarmSubSecondValue,
+                                     RTC_AlarmSubSecondMask_TypeDef RTC_AlarmSubSecondMask);
+
+/* WakeUp Timer configuration functions ***************************************/ 
+void RTC_WakeUpClockConfig(RTC_WakeUpClock_TypeDef RTC_WakeUpClock);
+void RTC_SetWakeUpCounter(uint16_t RTC_WakeupCounter);
+uint16_t RTC_GetWakeUpCounter(void);
+ErrorStatus RTC_WakeUpCmd(FunctionalState NewState);
+
+/* Daylight Saving configuration functions ************************************/ 
+void RTC_DayLightSavingConfig(RTC_DayLightSaving_TypeDef RTC_DayLightSaving,
+                              RTC_StoreOperation_TypeDef RTC_StoreOperation);
+RTC_StoreOperation_TypeDef  RTC_GetStoreOperation(void);
+
+/* Output pin Configuration function ******************************************/ 
+void RTC_OutputConfig(RTC_Output_TypeDef RTC_Output,
+                      RTC_OutputPolarity_TypeDef RTC_OutputPolarity);
+
+/* Shift control  synchronisation function ************************************/ 
+ErrorStatus RTC_SynchroShiftConfig(RTC_ShiftAdd1S_TypeDef RTC_ShiftAdd1S,
+                                   uint16_t RTC_ShiftSubFS);
+
+/* Smooth Calibration functions  **********************************************/
+ErrorStatus RTC_SmoothCalibConfig(RTC_SmoothCalibPeriod_TypeDef RTC_SmoothCalibPeriod,
+                                  RTC_SmoothCalibPlusPulses_TypeDef RTC_SmoothCalibPlusPulses,
+                                  uint16_t RTC_SmouthCalibMinusPulsesValue);
+
+/* Calibration configuration functions ****************************************/ 
+void RTC_CalibOutputConfig(RTC_CalibOutput_TypeDef RTC_CalibOutput);
+void RTC_CalibOutputCmd(FunctionalState NewState);
+
+/* Tampers configuration functions ********************************************/ 
+void RTC_TamperLevelConfig(RTC_Tamper_TypeDef RTC_Tamper,
+                           RTC_TamperLevel_TypeDef RTC_TamperLevel);
+void RTC_TamperFilterConfig(RTC_TamperFilter_TypeDef RTC_TamperFilter);
+void RTC_TamperSamplingFreqConfig(RTC_TamperSamplingFreq_TypeDef RTC_TamperSamplingFreq);
+void RTC_TamperPinsPrechargeDuration(RTC_TamperPrechargeDuration_TypeDef RTC_TamperPrechargeDuration);
+void RTC_TamperCmd(RTC_Tamper_TypeDef RTC_Tamper,
+                   FunctionalState NewState);
+
+/* Interrupts and flags management functions **********************************/ 
+void RTC_ITConfig(RTC_IT_TypeDef RTC_IT, FunctionalState NewState);
+FlagStatus RTC_GetFlagStatus(RTC_Flag_TypeDef RTC_FLAG);
+void RTC_ClearFlag(RTC_Flag_TypeDef RTC_FLAG);
+ITStatus RTC_GetITStatus(RTC_IT_TypeDef RTC_IT);
+void RTC_ClearITPendingBit(RTC_IT_TypeDef RTC_IT);
+
+#endif /*__STM8L15x_RTC_H */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_spi.h b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_spi.h
new file mode 100755
index 0000000..26a8312
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_spi.h
@@ -0,0 +1,401 @@
+/**
+  ******************************************************************************
+  * @file    stm8l15x_spi.h
+  * @author  MCD Application Team
+  * @version V1.6.0
+  * @date    28-June-2013
+  * @brief   This file contains all the functions prototypes for the SPI firmware
+  *          library.
+  ******************************************************************************
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ****************************************************************************** 
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM8L15x_SPI_H
+#define __STM8L15x_SPI_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm8l15x.h"
+
+/** @addtogroup STM8L15x_StdPeriph_Driver
+  * @{
+  */
+  
+/** @addtogroup SPI
+  * @{
+  */
+  
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup SPI_Exported_Types
+  * @{
+  */
+
+/** @defgroup SPI_Direction_Mode
+  * @brief element values correspond to BDM, BDOE, RXONLY bits position
+  * @{
+  */
+typedef enum {
+  SPI_Direction_2Lines_FullDuplex = (uint8_t)0x00, /*!< 2-line uni-directional data mode enable */
+  SPI_Direction_2Lines_RxOnly     = (uint8_t)0x04, /*!< Receiver only in 2 line uni-directional data mode */
+  SPI_Direction_1Line_Rx          = (uint8_t)0x80, /*!< Receiver only in 1 line bi-directional data mode */
+  SPI_Direction_1Line_Tx          = (uint8_t)0xC0  /*!< Transmit only in 1 line bi-directional data mode */
+} SPI_DirectionMode_TypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_SlaveSelect_Management
+  * @brief element values correspond to LSBFIRST bit position
+  * @{
+  */  
+typedef enum
+{
+  SPI_NSS_Soft  = (uint8_t)0x02, /*!< Software slave management disabled */
+  SPI_NSS_Hard  = (uint8_t)0x00  /*!< Software slave management enabled */
+} SPI_NSS_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup SPI_Direction
+  * @{
+  */
+typedef enum 
+{
+  SPI_Direction_Rx = (uint8_t)0x00, /*!< Select Rx receive direction in bi-directional mode */
+  SPI_Direction_Tx = (uint8_t)0x01  /*!< Select Tx transmission direction in bi-directional mode */
+} SPI_Direction_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup SPI_Mode
+  * @{
+  */
+typedef enum
+{
+  SPI_Mode_Master = (uint8_t)0x04, /*!< SPI Master configuration */
+  SPI_Mode_Slave  = (uint8_t)0x00  /*!< SPI Slave configuration */
+} SPI_Mode_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup SPI_BaudRate_Prescaler
+  * @{
+  */
+typedef enum {
+  SPI_BaudRatePrescaler_2   = (uint8_t)0x00, /*!< SPI frequency = frequency(CPU)/2 */
+  SPI_BaudRatePrescaler_4   = (uint8_t)0x08, /*!< SPI frequency = frequency(CPU)/4 */
+  SPI_BaudRatePrescaler_8   = (uint8_t)0x10, /*!< SPI frequency = frequency(CPU)/8 */
+  SPI_BaudRatePrescaler_16  = (uint8_t)0x18, /*!< SPI frequency = frequency(CPU)/16 */
+  SPI_BaudRatePrescaler_32  = (uint8_t)0x20, /*!< SPI frequency = frequency(CPU)/32 */
+  SPI_BaudRatePrescaler_64  = (uint8_t)0x28, /*!< SPI frequency = frequency(CPU)/64 */
+  SPI_BaudRatePrescaler_128 = (uint8_t)0x30, /*!< SPI frequency = frequency(CPU)/128 */
+  SPI_BaudRatePrescaler_256 = (uint8_t)0x38  /*!< SPI frequency = frequency(CPU)/256 */
+} SPI_BaudRatePrescaler_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup SPI_Clock_Polarity
+  * @{
+  */
+typedef enum 
+{
+  SPI_CPOL_Low  = (uint8_t)0x00, /*!< Clock to 0 when idle */
+  SPI_CPOL_High = (uint8_t)0x02  /*!< Clock to 1 when idle */
+} SPI_CPOL_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup SPI_Clock_Phase
+  * @{
+  */
+typedef enum 
+{
+  SPI_CPHA_1Edge = (uint8_t)0x00, /*!< The first clock transition is the first data capture edge */
+  SPI_CPHA_2Edge = (uint8_t)0x01  /*!< The second clock transition is the first data capture edge */
+} SPI_CPHA_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup SPI_Frame_Format
+  * @{
+  */
+typedef enum 
+{
+  SPI_FirstBit_MSB = (uint8_t)0x00, /*!< MSB bit will be transmitted first */
+  SPI_FirstBit_LSB = (uint8_t)0x80  /*!< LSB bit will be transmitted first */
+} SPI_FirstBit_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup SPI_DMA_requests
+  * @{
+  */
+typedef enum {
+  SPI_DMAReq_RX = (uint8_t)0x01,    /*!< SPI DMA Rx transfer requests */
+  SPI_DMAReq_TX = (uint8_t)0x02     /*!< SPI DMA Tx transfer requests */
+} SPI_DMAReq_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup SPI_CRC
+  * @{
+  */
+typedef enum {
+  SPI_CRC_RX = (uint8_t)0x00, /*!< Select Tx CRC register */
+  SPI_CRC_TX = (uint8_t)0x01  /*!< Select Rx CRC register */
+} SPI_CRC_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup SPI_Flags
+  * @{
+  */
+typedef enum {
+  SPI_FLAG_BSY    = (uint8_t)0x80, /*!< Busy flag */
+  SPI_FLAG_OVR    = (uint8_t)0x40, /*!< Overrun flag */
+  SPI_FLAG_MODF   = (uint8_t)0x20, /*!< Mode fault */
+  SPI_FLAG_CRCERR = (uint8_t)0x10, /*!< CRC error flag */
+  SPI_FLAG_WKUP   = (uint8_t)0x08, /*!< Wake-up flag */
+  SPI_FLAG_TXE    = (uint8_t)0x02, /*!< Transmit buffer empty */
+  SPI_FLAG_RXNE   = (uint8_t)0x01  /*!< Receive buffer empty */
+} SPI_FLAG_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup SPI_Interrupts
+  * @brief SPI_IT possible values
+  * Elements values convention: 0xYX
+  *   X: Position of the corresponding Interrupt
+  *   Y: ITPENDINGBIT position
+  * @{
+  */
+typedef enum
+{
+  SPI_IT_WKUP   = (uint8_t)0x34, /*!< Wake-up interrupt*/
+  SPI_IT_OVR    = (uint8_t)0x65,  /*!< Overrun interrupt*/
+  SPI_IT_MODF   = (uint8_t)0x55, /*!< Mode fault interrupt*/
+  SPI_IT_CRCERR = (uint8_t)0x45, /*!< CRC error interrupt*/
+  SPI_IT_TXE    = (uint8_t)0x17, /*!< Transmit buffer empty interrupt*/
+  SPI_IT_RXNE   = (uint8_t)0x06, /*!< Receive buffer not empty interrupt*/
+  SPI_IT_ERR    = (uint8_t)0x05  /*!< Error interrupt*/
+} SPI_IT_TypeDef;
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
+
+/** @defgroup SPI_Exported_Macros
+  * @brief Macros used by the assert_param function to check the different functions parameters.
+  * @{
+  */
+
+/**
+  * @brief Macro used by the assert_param function in order to check the data direction mode values
+  */
+#define IS_SPI_DATA_DIRECTION(Mode) (((Mode) == SPI_Direction_2Lines_FullDuplex) || \
+                                     ((Mode) == SPI_Direction_2Lines_RxOnly) || \
+                                     ((Mode) == SPI_Direction_1Line_Rx) || \
+                                     ((Mode) == SPI_Direction_1Line_Tx))
+
+/**
+  * @brief Macro used by the assert_param function in order to check the mode half duplex data direction values
+  */
+#define IS_SPI_DIRECTION(Direction) (((Direction) == SPI_Direction_Rx) || \
+                                     ((Direction) == SPI_Direction_Tx))
+
+/**
+  * @brief Macro used by the assert_param function in order to check the NSS management values
+  */
+#define IS_SPI_SLAVEMANAGEMENT(NSS) (((NSS) == SPI_NSS_Soft) || \
+                                     ((NSS) == SPI_NSS_Hard))
+
+
+/**
+  * @brief Macro used by the assert_param function in order to check the different
+  *  sensitivity values for the CRC polynomial
+  */
+#define IS_SPI_CRC_POLYNOMIAL(Polynomial) ((Polynomial) > (uint8_t)0x00)
+
+/**
+  * @brief Macro used by the assert_param function in order to check the SPI Mode values
+  */
+#define IS_SPI_MODE(Mode) (((Mode) == SPI_Mode_Master) || \
+                           ((Mode) == SPI_Mode_Slave))
+
+/**
+  * @brief Macro used by the assert_param function in order to check the baudrate values
+  */
+#define IS_SPI_BAUDRATE_PRESCALER(Prescaler) (((Prescaler) == SPI_BaudRatePrescaler_2) || \
+                                              ((Prescaler) == SPI_BaudRatePrescaler_4) || \
+                                              ((Prescaler) == SPI_BaudRatePrescaler_8) || \
+                                              ((Prescaler) == SPI_BaudRatePrescaler_16) || \
+                                              ((Prescaler) == SPI_BaudRatePrescaler_32) || \
+                                              ((Prescaler) == SPI_BaudRatePrescaler_64) || \
+                                              ((Prescaler) == SPI_BaudRatePrescaler_128) || \
+                                              ((Prescaler) == SPI_BaudRatePrescaler_256))
+
+/**
+  * @brief Macro used by the assert_param function in order to check the polarity values
+  */
+#define IS_SPI_POLARITY(ClkPol) (((ClkPol) == SPI_CPOL_Low) || \
+                                 ((ClkPol) == SPI_CPOL_High))
+
+/**
+  * @brief Macro used by the assert_param function in order to check the phase values
+  */
+#define IS_SPI_PHASE(ClkPha) (((ClkPha) == SPI_CPHA_1Edge) || \
+                              ((ClkPha) == SPI_CPHA_2Edge))
+
+/**
+  * @brief Macro used by the assert_param function in order to check the first bit
+  *   to be transmitted values
+  */
+#define IS_SPI_FIRSTBIT(Bit) (((Bit) == SPI_FirstBit_MSB) || \
+                              ((Bit) == SPI_FirstBit_LSB))
+
+/**
+  * @brief Macro used by the assert_param function in order to check the CRC Transmit/Receive
+  */
+#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_TX) || \
+                         ((CRC) == SPI_CRC_RX))
+
+/**
+  * @brief Macro used by the assert_param function in order to check the DMA transfer requests
+  */
+#define IS_SPI_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFC) == 0x00) && ((DMAREQ) != 0x00))
+
+/**
+  * @brief Macro used by the assert_param function in order to check the different flags values
+  */
+#define IS_SPI_FLAG(Flag) (((Flag) == SPI_FLAG_OVR) || \
+                           ((Flag) == SPI_FLAG_MODF) || \
+                           ((Flag) == SPI_FLAG_CRCERR) || \
+                           ((Flag) == SPI_FLAG_WKUP) || \
+                           ((Flag) == SPI_FLAG_TXE) || \
+                           ((Flag) == SPI_FLAG_RXNE) || \
+                           ((Flag) == SPI_FLAG_BSY))
+
+/**
+  * @brief Macro used by the assert_param function in order to check the different
+  *   sensitivity values for the flag that can be cleared by writing 0
+  */
+#define IS_SPI_CLEAR_FLAG(Flag) (((Flag) == SPI_FLAG_CRCERR) || \
+                                 ((Flag) == SPI_FLAG_WKUP))
+
+/**
+  * @brief Macro used by the assert_param function in order to check the different
+  *   sensitivity values for the Interrupts
+  */
+#define IS_SPI_CONFIG_IT(Interrupt) (((Interrupt) == SPI_IT_TXE)  || \
+                                     ((Interrupt) == SPI_IT_RXNE)  || \
+                                     ((Interrupt) == SPI_IT_ERR) || \
+                                     ((Interrupt) == SPI_IT_WKUP))
+
+/**
+  * @brief Macro used by the assert_param function in order to check the different
+  *   sensitivity values for the pending bit
+  */
+#define IS_SPI_GET_IT(ITPendingBit) (((ITPendingBit) == SPI_IT_OVR)  || \
+                                     ((ITPendingBit) == SPI_IT_MODF) || \
+                                     ((ITPendingBit) == SPI_IT_CRCERR) || \
+                                     ((ITPendingBit) == SPI_IT_WKUP) || \
+                                     ((ITPendingBit) == SPI_IT_TXE)  || \
+                                     ((ITPendingBit) == SPI_IT_RXNE))
+
+/**
+  * @brief Macro used by the assert_param function in order to check the different
+  *   sensitivity values for the pending bit that can be cleared by writing 0
+  */
+#define IS_SPI_CLEAR_IT(ITPendingBit) (((ITPendingBit) == SPI_IT_CRCERR) || \
+                                       ((ITPendingBit) == SPI_IT_WKUP))
+
+/**
+  * @}
+  */
+
+/* Exported functions ------------------------------------------------------- */
+/* Function used to set the SPI configuration to the default reset state *****/ 
+void SPI_DeInit(SPI_TypeDef* SPIx);
+/* Initialization and Configuration functions *********************************/
+void SPI_Init(SPI_TypeDef* SPIx, SPI_FirstBit_TypeDef SPI_FirstBit,
+              SPI_BaudRatePrescaler_TypeDef SPI_BaudRatePrescaler,
+              SPI_Mode_TypeDef SPI_Mode, SPI_CPOL_TypeDef SPI_CPOL,
+              SPI_CPHA_TypeDef SPI_CPHA, SPI_DirectionMode_TypeDef SPI_Data_Direction,
+              SPI_NSS_TypeDef SPI_Slave_Management, uint8_t CRCPolynomial);
+void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+void SPI_NSSInternalSoftwareCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, SPI_Direction_TypeDef SPI_Direction);
+
+/* Data transfers functions ***************************************************/
+void SPI_SendData(SPI_TypeDef* SPIx, uint8_t Data);
+uint8_t SPI_ReceiveData(SPI_TypeDef* SPIx);
+
+/* Hardware CRC Calculation functions *****************************************/
+void SPI_TransmitCRC(SPI_TypeDef* SPIx);
+void SPI_CalculateCRCCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+uint8_t SPI_GetCRC(SPI_TypeDef* SPIx, SPI_CRC_TypeDef SPI_CRC);
+void SPI_ResetCRC(SPI_TypeDef* SPIx);
+uint8_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);
+
+/* DMA transfer management functions *****************************************/
+void SPI_DMACmd(SPI_TypeDef* SPIx, SPI_DMAReq_TypeDef SPI_DMAReq, FunctionalState NewState);
+
+/* Interrupts and flags management functions **********************************/
+void SPI_ITConfig(SPI_TypeDef* SPIx, SPI_IT_TypeDef SPI_IT, FunctionalState NewState);
+FlagStatus SPI_GetFlagStatus(SPI_TypeDef* SPIx, SPI_FLAG_TypeDef SPI_FLAG);
+void SPI_ClearFlag(SPI_TypeDef* SPIx, SPI_FLAG_TypeDef SPI_FLAG);
+ITStatus SPI_GetITStatus(SPI_TypeDef* SPIx, SPI_IT_TypeDef SPI_IT);
+void SPI_ClearITPendingBit(SPI_TypeDef* SPIx, SPI_IT_TypeDef SPI_IT);
+
+#endif /* __STM8L15x_SPI_H */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_syscfg.h b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_syscfg.h
new file mode 100755
index 0000000..f85696d
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_syscfg.h
@@ -0,0 +1,421 @@
+/**
+  ******************************************************************************
+  * @file    stm8l15x_syscfg.h
+  * @author  MCD Application Team
+  * @version V1.6.0
+  * @date    28-June-2013
+  * @brief   This file contains all the functions prototypes for the SYSCFG firmware
+  *          library.
+  ******************************************************************************
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ****************************************************************************** 
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM8L15x_SYSCFG_H
+#define __STM8L15x_SYSCFG_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm8l15x.h"
+
+/** @addtogroup STM8L15x_StdPeriph_Driver
+  * @{
+  */
+  
+/** @addtogroup SYSCFG
+  * @{
+  */ 
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup SYSCFG_Exported_Types
+  * @{
+  */
+
+/** @defgroup RI_Input_Capture
+  * @{
+  */
+typedef enum
+{
+  RI_InputCapture_IC2 = ((uint8_t) 0x02), /*!< TIM1 Input Capture 2 is routed */
+  RI_InputCapture_IC3 = ((uint8_t) 0x03)  /*!< TIM1 Input Capture 3 is routed */
+}RI_InputCapture_TypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup RI_Input_Capture_Routing
+  * @{
+  */
+typedef enum
+{
+  RI_InputCaptureRouting_0  = ((uint8_t) 0x00), /*!< TIM1 IC2 is routed to PD4, IC3 to PD5 */
+  RI_InputCaptureRouting_1  = ((uint8_t) 0x01), /*!< TIM1 IC2 is routed to PF0, IC3 to PF1 */
+  RI_InputCaptureRouting_2  = ((uint8_t) 0x02), /*!< TIM1 IC2 is routed to PF2, IC3 to PF3 */
+  RI_InputCaptureRouting_3  = ((uint8_t) 0x03), /*!< TIM1 IC2 is routed to PE0, IC3 to PE1 */
+  RI_InputCaptureRouting_4  = ((uint8_t) 0x04), /*!< TIM1 IC2 is routed to PE2, IC3 to PE3 */
+  RI_InputCaptureRouting_5  = ((uint8_t) 0x05), /*!< TIM1 IC2 is routed to PE4, IC3 to PE5 */
+  RI_InputCaptureRouting_6  = ((uint8_t) 0x06), /*!< TIM1 IC2 is routed to PE6, IC3 to PE7 */
+  RI_InputCaptureRouting_7  = ((uint8_t) 0x07), /*!< TIM1 IC2 is routed to PD0, IC3 to PD1 */
+  RI_InputCaptureRouting_8  = ((uint8_t) 0x08), /*!< TIM1 IC2 is routed to PD2, IC3 to PD3 */
+  RI_InputCaptureRouting_9  = ((uint8_t) 0x09), /*!< TIM1 IC2 is routed to PD4, IC3 to PD5 */
+  RI_InputCaptureRouting_10 = ((uint8_t) 0x0A), /*!< TIM1 IC2 is routed to PD6, IC3 to PD7 */
+  RI_InputCaptureRouting_11 = ((uint8_t) 0x0B), /*!< TIM1 IC2 is routed to PC0, IC3 to PC1 */
+  RI_InputCaptureRouting_12 = ((uint8_t) 0x0C), /*!< TIM1 IC2 is routed to PC2, IC3 to PC3 */
+  RI_InputCaptureRouting_13 = ((uint8_t) 0x0D), /*!< TIM1 IC2 is routed to PC4, IC3 to PC5 */
+  RI_InputCaptureRouting_14 = ((uint8_t) 0x0E), /*!< TIM1 IC2 is routed to PC6, IC3 to PC7 */
+  RI_InputCaptureRouting_15 = ((uint8_t) 0x0F), /*!< TIM1 IC2 is routed to PB0, IC3 to PB1 */
+  RI_InputCaptureRouting_16 = ((uint8_t) 0x10), /*!< TIM1 IC2 is routed to PB2, IC3 to PB3 */
+  RI_InputCaptureRouting_17 = ((uint8_t) 0x11), /*!< TIM1 IC2 is routed to PB4, IC3 to PB5 */
+  RI_InputCaptureRouting_18 = ((uint8_t) 0x12), /*!< TIM1 IC2 is routed to PB6, IC3 to PB7 */
+  RI_InputCaptureRouting_19 = ((uint8_t) 0x13), /*!< TIM1 IC2 is routed to PA0, IC3 to PA2 */
+  RI_InputCaptureRouting_20 = ((uint8_t) 0x14), /*!< TIM1 IC2 is routed to PA3, IC3 to PA4 */
+  RI_InputCaptureRouting_21 = ((uint8_t) 0x15), /*!< TIM1 IC2 is routed to PA5, IC3 to PA6 */
+  RI_InputCaptureRouting_22 = ((uint8_t) 0x16)  /*!< TIM1 IC2 is routed to PA7, IC3 to PD5 */
+}RI_InputCaptureRouting_TypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup RI_Analog_Switch
+  * @{
+  */
+/**
+  * @brief Definition of the Analog Switch to be controlled.
+  * Values are coded in 0xXY format where
+  * X: the register index (1: RI_ASCR1, 2: RI_ASCR2)
+  * Y: the bit position which corresponds with the Analog Switch
+  */
+typedef enum
+{
+  RI_AnalogSwitch_0  = ((uint8_t) 0x10), /*!< Analog switch 0 */
+  RI_AnalogSwitch_1  = ((uint8_t) 0x11), /*!< Analog switch 1 */
+  RI_AnalogSwitch_2  = ((uint8_t) 0x12), /*!< Analog switch 2 */
+  RI_AnalogSwitch_3  = ((uint8_t) 0x13), /*!< Analog switch 3 */
+  RI_AnalogSwitch_4  = ((uint8_t) 0x14), /*!< Analog switch 4 */
+  RI_AnalogSwitch_5  = ((uint8_t) 0x15), /*!< Analog switch 5 */
+  RI_AnalogSwitch_6  = ((uint8_t) 0x16), /*!< Analog switch 6 */
+  RI_AnalogSwitch_7  = ((uint8_t) 0x17), /*!< Analog switch 7 */
+  RI_AnalogSwitch_8  = ((uint8_t) 0x20), /*!< Analog switch 8 */
+  RI_AnalogSwitch_9  = ((uint8_t) 0x21), /*!< Analog switch 9 */
+  RI_AnalogSwitch_10 = ((uint8_t) 0x22), /*!< Analog switch 10 */
+  RI_AnalogSwitch_11 = ((uint8_t) 0x23), /*!< Analog switch 11 */
+  RI_AnalogSwitch_14 = ((uint8_t) 0x26)  /*!< Analog switch 14 */
+}RI_AnalogSwitch_TypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup RI_IO_Switch
+  * @{
+  */
+/**
+  * @brief Definition of the I/O Switch to be controlled.
+  * Values are coded in 0xXY format where
+  * X: the register index (1: RI_IOSR1, 2: RI_IOSR2, 3: RI_IOSR3 or 4: RI_IOSR4)
+  * Y: the bit index of the Input Output Switch in RI_IOSRx register
+  */
+typedef enum
+{
+  RI_IOSwitch_1   = ((uint8_t) 0x10),  /*!< Input Output Switch switch 1  */
+  RI_IOSwitch_2   = ((uint8_t) 0x20),  /*!< Input Output Switch switch 2  */
+  RI_IOSwitch_3   = ((uint8_t) 0x30),  /*!< Input Output Switch switch 3  */
+  RI_IOSwitch_4   = ((uint8_t) 0x11),  /*!< Input Output Switch switch 4  */
+  RI_IOSwitch_5   = ((uint8_t) 0x21),  /*!< Input Output Switch switch 4  */
+  RI_IOSwitch_6   = ((uint8_t) 0x31),  /*!< Input Output Switch switch 6  */
+  RI_IOSwitch_7   = ((uint8_t) 0x12),  /*!< Input Output Switch switch 7  */
+  RI_IOSwitch_8   = ((uint8_t) 0x22),  /*!< Input Output Switch switch 8  */
+  RI_IOSwitch_9   = ((uint8_t) 0x32),  /*!< Input Output Switch switch 9  */
+  RI_IOSwitch_10  = ((uint8_t) 0x13),  /*!< Input Output Switch switch 10 */
+  RI_IOSwitch_11  = ((uint8_t) 0x23),  /*!< Input Output Switch switch 11 */
+  RI_IOSwitch_12  = ((uint8_t) 0x33),  /*!< Input Output Switch switch 12 */
+  RI_IOSwitch_13  = ((uint8_t) 0x14),  /*!< Input Output Switch switch 13 */
+  RI_IOSwitch_14  = ((uint8_t) 0x24),  /*!< Input Output Switch switch 14 */
+  RI_IOSwitch_15  = ((uint8_t) 0x34),  /*!< Input Output Switch switch 15 */
+  RI_IOSwitch_16  = ((uint8_t) 0x15),  /*!< Input Output Switch switch 16 */
+  RI_IOSwitch_17  = ((uint8_t) 0x25),  /*!< Input Output Switch switch 17 */
+  RI_IOSwitch_18  = ((uint8_t) 0x35),  /*!< Input Output Switch switch 18 */
+  RI_IOSwitch_19  = ((uint8_t) 0x16),  /*!< Input Output Switch switch 19 */
+  RI_IOSwitch_20  = ((uint8_t) 0x26),  /*!< Input Output Switch switch 20 */
+  RI_IOSwitch_21  = ((uint8_t) 0x36),  /*!< Input Output Switch switch 21 */
+  RI_IOSwitch_22  = ((uint8_t) 0x17),  /*!< Input Output Switch switch 22 */
+  RI_IOSwitch_23  = ((uint8_t) 0x27),  /*!< Input Output Switch switch 23 */
+  RI_IOSwitch_24  = ((uint8_t) 0x37),  /*!< Input Output Switch switch 24 */
+  RI_IOSwitch_26  = ((uint8_t) 0x41),  /*!< Input Output Switch switch 26 */
+  RI_IOSwitch_27  = ((uint8_t) 0x46),  /*!< Input Output Switch switch 27 */
+  RI_IOSwitch_28  = ((uint8_t) 0x47),  /*!< Input Output Switch switch 28 */
+  RI_IOSwitch_29  = ((uint8_t) 0x40)   /*!< Input Output Switch switch 29 */
+}RI_IOSwitch_TypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup RI_Resistor
+  * @{
+  */
+/**
+  * @brief Definition of the pull-up and pull-down resistors for COMP1 and ADC.
+  */
+typedef enum
+{
+  RI_Resistor_10KPU  = ((uint8_t) 0x01),
+  RI_Resistor_400KPU = ((uint8_t) 0x02),
+  RI_Resistor_10KPD  = ((uint8_t) 0x04),
+  RI_Resistor_400KPD = ((uint8_t) 0x08)
+}RI_Resistor_TypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup REMAP_Pin
+  * @{
+  */
+/**
+  * @brief Definition of the REMAP pins.
+  * Elements values convention: 0xXY
+  *  X = RMPCRx registers index
+  *      X = 0x01 : RMPCR1
+  *      X = 0x02 : RMPCR2
+  *      X = 0x03 : RMPCR3
+  *  Y = Mask for setting/resetting bits in RMPCRx register
+  */
+typedef enum
+{
+  /* RMPCR1 register bits */
+  REMAP_Pin_USART1TxRxPortA = ((uint16_t)0x011C), /*!< USART1 Tx- Rx (PC3- PC2) remapping to PA2- PA3 */
+  REMAP_Pin_USART1TxRxPortC = ((uint16_t)0x012C), /*!< USART1 Tx- Rx (PC3- PC2) remapping to PC5- PC6 */
+  REMAP_Pin_USART1Clk       = ((uint16_t)0x014B), /*!< USART1 CK (PC4) remapping to PA0 */
+  REMAP_Pin_SPI1Full        = ((uint16_t)0x0187), /*!< SPI1 MISO- MOSI- SCK- NSS(PB7- PB6- PB5- PB4)
+                                                       remapping to PA2- PA3- PC6- PC5 */
+  /* RMPCR2 register bits */
+  REMAP_Pin_ADC1ExtTRIG1    = ((uint16_t)0x0201), /*!< ADC1 External Trigger 1 (PA6) remapping to PD0 */
+  REMAP_Pin_TIM2TRIGPortA   = ((uint16_t)0x0202), /*!< TIM2 Trigger (PB3) remapping to PA4 */
+  REMAP_Pin_TIM3TRIGPortA   = ((uint16_t)0x0204), /*!< TIM3 Trigger (PD1) remapping to PA5 */
+  REMAP_Pin_TIM2TRIGLSE     = ((uint16_t)0x0208), /*!< TIM2 Trigger remapping to LSE */
+  REMAP_Pin_TIM3TRIGLSE     = ((uint16_t)0x0210), /*!< TIM3 Trigger remapping to LSE */
+  REMAP_Pin_SPI2Full        = ((uint16_t)0x0220), /*!< SPI2 MISO- MOSI- SCK- NSS(PG7- PG6- PG5- PG4)
+                                                       remapping to PI3- PI2- PI1- PI0 */
+  REMAP_Pin_TIM3TRIGPortG   = ((uint16_t)0x0240), /*!< TIM3 Trigger (PD1) remapping to PG3 */
+  REMAP_Pin_TIM23BKIN       = ((uint16_t)0x0280), /*!< TIM2 Break Input (PA4) remapping to PG0
+                                                           and TIM3 Break Input (PA5) remapping to PG1 */
+  /* RMPCR3 register bits */
+  REMAP_Pin_SPI1PortF       = ((uint16_t)0x0301), /*!< SPI1 MISO- MOSI- SCK- NSS(PB7- PB6- PB5- PB4)
+                                                       remapping to PF0- PF1- PF2- PF3   */
+  REMAP_Pin_USART3TxRxPortF = ((uint16_t)0x0302), /*!< USART3 Tx- Rx (PG1- PG0) remapping to PF0- PF1 */
+  REMAP_Pin_USART3Clk       = ((uint16_t)0x0304), /*!< USART3 CK (PG2) remapping to PF2 */
+  REMAP_Pin_TIM3Channel1    = ((uint16_t)0x0308), /*!< TIM3 Channel 1 (PB1) remapping to PI0 */
+  REMAP_Pin_TIM3Channel2    = ((uint16_t)0x0310), /*!< TIM3 Channel 2 (PD0) remapping to PI3 */
+  REMAP_Pin_CCO             = ((uint16_t)0x0320), /*!< CCO (PC4) remapping to PE2 */
+  REMAP_Pin_TIM2Channel1    = ((uint16_t)0x0340), /*!< TIM2 Channel 1 (PB0) remapping to PC5 */
+  REMAP_Pin_TIM2Channel2    = ((uint16_t)0x0380)  /*!< TIM2 Channel 2 (PB2) remapping to PC6 */
+}REMAP_Pin_TypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup REMAP_DMA_Channel
+  * @{
+  */
+typedef enum
+{
+  REMAP_DMA1Channel_ADC1ToChannel0  = ((uint8_t)0x00), /*!< ADC1 DMA1 req/ack mapped on DMA1 channel 0 */
+  REMAP_DMA1Channel_ADC1ToChannel1  = ((uint8_t)0x01), /*!< ADC1 DMA1 req/ack mapped on DMA1 channel 1 */
+  REMAP_DMA1Channel_ADC1ToChannel2  = ((uint8_t)0x02), /*!< ADC1 DMA1 req/ack mapped on DMA1 channel 2 */
+  REMAP_DMA1Channel_ADC1ToChannel3  = ((uint8_t)0x03), /*!< ADC1 DMA1 req/ack mapped on DMA1 channel 3 */
+  REMAP_DMA1Channel_TIM4ToChannel0  = ((uint8_t)0xF0), /*!< TIM4 DMA1 req/ack mapped on DMA1 channel 0 */
+  REMAP_DMA1Channel_TIM4ToChannel1  = ((uint8_t)0xF4), /*!< TIM4 DMA1 req/ack mapped on DMA1 channel 1 */
+  REMAP_DMA1Channel_TIM4ToChannel2  = ((uint8_t)0xF8), /*!< TIM4 DMA1 req/ack mapped on DMA1 channel 2 */
+  REMAP_DMA1Channel_TIM4ToChannel3  = ((uint8_t)0xFC)  /*!< TIM4 DMA1 req/ack mapped on DMA1 channel 3 */
+}REMAP_DMAChannel_TypeDef;
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Exported constants --------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup SYSCFG_Exported_Macros
+  * @{
+  */
+
+/**
+  * @brief Macro used by the assert function in order to check the different
+  * values of @ref RI_InputCaptureTypeDef enum.
+  */
+#define IS_RI_INPUTCAPTURE(RI_IC) (((RI_IC) == RI_InputCapture_IC2) || \
+                                   ((RI_IC) == RI_InputCapture_IC3))
+
+/**
+  * @brief Macro used by the assert function in order to check the different
+  * values of @ref RI_InputCaptureRoutingTypeDef enum.
+  */
+#define IS_RI_INPUTCAPTUREROUTING(RI_IC_ROUTING) (((RI_IC_ROUTING) == RI_InputCaptureRouting_0) || \
+    ((RI_IC_ROUTING) == RI_InputCaptureRouting_1) || \
+    ((RI_IC_ROUTING) == RI_InputCaptureRouting_2) || \
+    ((RI_IC_ROUTING) == RI_InputCaptureRouting_3) || \
+    ((RI_IC_ROUTING) == RI_InputCaptureRouting_4) || \
+    ((RI_IC_ROUTING) == RI_InputCaptureRouting_5) || \
+    ((RI_IC_ROUTING) == RI_InputCaptureRouting_6) || \
+    ((RI_IC_ROUTING) == RI_InputCaptureRouting_7) || \
+    ((RI_IC_ROUTING) == RI_InputCaptureRouting_8) || \
+    ((RI_IC_ROUTING) == RI_InputCaptureRouting_9) || \
+    ((RI_IC_ROUTING) == RI_InputCaptureRouting_10) || \
+    ((RI_IC_ROUTING) == RI_InputCaptureRouting_11) || \
+    ((RI_IC_ROUTING) == RI_InputCaptureRouting_12) || \
+    ((RI_IC_ROUTING) == RI_InputCaptureRouting_13) || \
+    ((RI_IC_ROUTING) == RI_InputCaptureRouting_14) || \
+    ((RI_IC_ROUTING) == RI_InputCaptureRouting_15) || \
+    ((RI_IC_ROUTING) == RI_InputCaptureRouting_16) || \
+    ((RI_IC_ROUTING) == RI_InputCaptureRouting_17) || \
+    ((RI_IC_ROUTING) == RI_InputCaptureRouting_18) || \
+    ((RI_IC_ROUTING) == RI_InputCaptureRouting_19) || \
+    ((RI_IC_ROUTING) == RI_InputCaptureRouting_20) || \
+    ((RI_IC_ROUTING) == RI_InputCaptureRouting_21) || \
+    ((RI_IC_ROUTING) == RI_InputCaptureRouting_22))
+
+/**
+  * @brief Macro used by the assert function in order to check the different
+  * values of @ref RI_AnalogSwitch_TypeDef enum.
+  */
+#define IS_RI_ANALOGSWITCH(RI_ANALOGSWITCH) (((RI_ANALOGSWITCH) == RI_AnalogSwitch_0) || \
+    ((RI_ANALOGSWITCH) == RI_AnalogSwitch_1) || \
+    ((RI_ANALOGSWITCH) == RI_AnalogSwitch_2) || \
+    ((RI_ANALOGSWITCH) == RI_AnalogSwitch_3) || \
+    ((RI_ANALOGSWITCH) == RI_AnalogSwitch_4) || \
+    ((RI_ANALOGSWITCH) == RI_AnalogSwitch_5) || \
+    ((RI_ANALOGSWITCH) == RI_AnalogSwitch_6) || \
+    ((RI_ANALOGSWITCH) == RI_AnalogSwitch_7) || \
+    ((RI_ANALOGSWITCH) == RI_AnalogSwitch_8) || \
+    ((RI_ANALOGSWITCH) == RI_AnalogSwitch_9) || \
+    ((RI_ANALOGSWITCH) == RI_AnalogSwitch_10)|| \
+    ((RI_ANALOGSWITCH) == RI_AnalogSwitch_11)|| \
+    ((RI_ANALOGSWITCH) == RI_AnalogSwitch_14))
+
+/**
+  * @brief Macro used by the assert function in order to check the different
+  * values of @ref RI_IOSwitch_TypeDef enum.
+  */
+#define IS_RI_IOSWITCH(RI_IOSWITCH) (((RI_IOSWITCH) == RI_IOSwitch_1) || \
+                                     ((RI_IOSWITCH) == RI_IOSwitch_2) || \
+                                     ((RI_IOSWITCH) == RI_IOSwitch_3) || \
+                                     ((RI_IOSWITCH) == RI_IOSwitch_4) || \
+                                     ((RI_IOSWITCH) == RI_IOSwitch_5) || \
+                                     ((RI_IOSWITCH) == RI_IOSwitch_6) || \
+                                     ((RI_IOSWITCH) == RI_IOSwitch_7) || \
+                                     ((RI_IOSWITCH) == RI_IOSwitch_8) || \
+                                     ((RI_IOSWITCH) == RI_IOSwitch_9) || \
+                                     ((RI_IOSWITCH) == RI_IOSwitch_10) || \
+                                     ((RI_IOSWITCH) == RI_IOSwitch_11) || \
+                                     ((RI_IOSWITCH) == RI_IOSwitch_12) || \
+                                     ((RI_IOSWITCH) == RI_IOSwitch_13) || \
+                                     ((RI_IOSWITCH) == RI_IOSwitch_14) || \
+                                     ((RI_IOSWITCH) == RI_IOSwitch_15) || \
+                                     ((RI_IOSWITCH) == RI_IOSwitch_16) || \
+                                     ((RI_IOSWITCH) == RI_IOSwitch_17) || \
+                                     ((RI_IOSWITCH) == RI_IOSwitch_18) || \
+                                     ((RI_IOSWITCH) == RI_IOSwitch_19) || \
+                                     ((RI_IOSWITCH) == RI_IOSwitch_20) || \
+                                     ((RI_IOSWITCH) == RI_IOSwitch_21) || \
+                                     ((RI_IOSWITCH) == RI_IOSwitch_22) || \
+                                     ((RI_IOSWITCH) == RI_IOSwitch_23) || \
+                                     ((RI_IOSWITCH) == RI_IOSwitch_24) || \
+                                     ((RI_IOSWITCH) == RI_IOSwitch_26) || \
+                                     ((RI_IOSWITCH) == RI_IOSwitch_27) || \
+                                     ((RI_IOSWITCH) == RI_IOSwitch_28) || \
+                                     ((RI_IOSWITCH) == RI_IOSwitch_29))
+
+/**
+  * @brief Macro used by the assert function in order to check the different
+  * values of @ref RI_ResistorTypeDef enum.
+  */
+#define IS_RI_RESISTOR(RI_RESISTOR) (((RI_RESISTOR) ==  RI_Resistor_10KPU)  || \
+                                     ((RI_RESISTOR) ==  RI_Resistor_400KPU) || \
+                                     ((RI_RESISTOR) ==  RI_Resistor_10KPD)  || \
+                                     ((RI_RESISTOR) ==  RI_Resistor_400KPD))
+/**
+  * @brief Macro used by the assert function in order to check the different
+  * values of @ref REMAP_Pin_TypeDef enum.
+  */
+#define IS_REMAP_PIN(PIN) (((PIN) == REMAP_Pin_USART1TxRxPortA) || \
+                           ((PIN) == REMAP_Pin_USART1TxRxPortC) || \
+                           ((PIN) == REMAP_Pin_USART1Clk) || \
+                           ((PIN) == REMAP_Pin_SPI1Full) || \
+                           ((PIN) == REMAP_Pin_ADC1ExtTRIG1) || \
+                           ((PIN) == REMAP_Pin_TIM2TRIGPortA) || \
+                           ((PIN) == REMAP_Pin_TIM3TRIGPortA) || \
+                           ((PIN) == REMAP_Pin_TIM2TRIGLSE) || \
+                           ((PIN) == REMAP_Pin_TIM3TRIGLSE) || \
+                           ((PIN) == REMAP_Pin_SPI2Full) || \
+                           ((PIN) == REMAP_Pin_TIM3TRIGPortG) || \
+                           ((PIN) == REMAP_Pin_TIM23BKIN) || \
+                           ((PIN) == REMAP_Pin_SPI1PortF) || \
+                           ((PIN) == REMAP_Pin_USART3TxRxPortF) || \
+                           ((PIN) == REMAP_Pin_USART3Clk) || \
+                           ((PIN) == REMAP_Pin_TIM3Channel1) || \
+                           ((PIN) == REMAP_Pin_TIM3Channel2) || \
+                           ((PIN) == REMAP_Pin_CCO) || \
+                           ((PIN) == REMAP_Pin_TIM2Channel1) || \
+                           ((PIN) == REMAP_Pin_TIM2Channel2))
+
+
+/**
+  * @brief Macro used by the assert function in order to check the different
+  * values of the @ref REMAP_DMAChannel_TypeDef enum.
+  */
+#define IS_REMAP_DMACHANNEL(MAP) (((MAP) == REMAP_DMA1Channel_ADC1ToChannel0) || \
+                                  ((MAP) == REMAP_DMA1Channel_ADC1ToChannel1) || \
+                                  ((MAP) == REMAP_DMA1Channel_ADC1ToChannel2) || \
+                                  ((MAP) == REMAP_DMA1Channel_ADC1ToChannel3) || \
+                                  ((MAP) == REMAP_DMA1Channel_TIM4ToChannel0) || \
+                                  ((MAP) == REMAP_DMA1Channel_TIM4ToChannel1) || \
+                                  ((MAP) == REMAP_DMA1Channel_TIM4ToChannel2) || \
+                                  ((MAP) == REMAP_DMA1Channel_TIM4ToChannel3))
+/**
+  * @}
+  */
+  
+/* Exported functions ------------------------------------------------------- */
+/* Routing Interface (RI) configuration ***************************************/
+void SYSCFG_RIDeInit(void);
+void SYSCFG_RITIMInputCaptureConfig(RI_InputCapture_TypeDef RI_InputCapture,
+                                    RI_InputCaptureRouting_TypeDef RI_InputCaptureRouting);
+void SYSCFG_RIAnalogSwitchConfig(RI_AnalogSwitch_TypeDef RI_AnalogSwitch,
+                                 FunctionalState NewState);
+void SYSCFG_RIIOSwitchConfig(RI_IOSwitch_TypeDef RI_IOSwitch, FunctionalState NewState);
+void SYSCFG_RIResistorConfig(RI_Resistor_TypeDef RI_Resistor, FunctionalState NewState);
+
+/* SYSCFG configuration *******************************************************/
+void SYSCFG_REMAPDeInit(void);
+void SYSCFG_REMAPPinConfig(REMAP_Pin_TypeDef REMAP_Pin, FunctionalState NewState);
+void SYSCFG_REMAPDMAChannelConfig(REMAP_DMAChannel_TypeDef REMAP_DMAChannel);
+
+#endif /* __STM8L15x_SYSCFG_H */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_tim1.h b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_tim1.h
new file mode 100755
index 0000000..06e47fc
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_tim1.h
@@ -0,0 +1,1041 @@
+/**
+  ******************************************************************************
+  * @file    stm8l15x_tim1.h
+  * @author  MCD Application Team
+  * @version V1.6.0
+  * @date    28-June-2013
+  * @brief   This file contains all the functions prototypes for the TIM1 firmware
+  *          library.
+  ******************************************************************************
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ****************************************************************************** 
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM8L15x_TIM1_H
+#define __STM8L15x_TIM1_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm8l15x.h"
+
+/** @addtogroup STM8L15x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup TIM1
+  * @{
+  */ 
+  
+/* Exported types ------------------------------------------------------------*/  
+/** @defgroup TIM1_Exported_Types
+  * @{
+  */
+
+/** @defgroup TIM1_Output_Compare_Mode
+  * @{
+  */
+typedef enum
+{
+  TIM1_OCMode_Timing     = ((uint8_t)0x00),
+  TIM1_OCMode_Active     = ((uint8_t)0x10),
+  TIM1_OCMode_Inactive   = ((uint8_t)0x20),
+  TIM1_OCMode_Toggle     = ((uint8_t)0x30),
+  TIM1_OCMode_PWM1       = ((uint8_t)0x60),
+  TIM1_OCMode_PWM2       = ((uint8_t)0x70)
+}TIM1_OCMode_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup TIM1_One_Pulse_Mode
+  * @{
+  */
+typedef enum
+{
+  TIM1_OPMode_Single                 = ((uint8_t)0x01),
+  TIM1_OPMode_Repetitive             = ((uint8_t)0x00)
+}TIM1_OPMode_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup TIM1_Channels
+  * @{
+  */
+typedef enum
+{
+  TIM1_Channel_1                     = ((uint8_t)0x00),
+  TIM1_Channel_2                     = ((uint8_t)0x01),
+  TIM1_Channel_3                     = ((uint8_t)0x02),
+  TIM1_Channel_4                     = ((uint8_t)0x03)
+}TIM1_Channel_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup TIM1_Counter_Mode
+  * @{
+  */
+typedef enum
+{
+  TIM1_CounterMode_Up                = ((uint8_t)0x00),
+  TIM1_CounterMode_Down              = ((uint8_t)0x10),
+  TIM1_CounterMode_CenterAligned1    = ((uint8_t)0x20),
+  TIM1_CounterMode_CenterAligned2    = ((uint8_t)0x40),
+  TIM1_CounterMode_CenterAligned3    = ((uint8_t)0x60)
+}TIM1_CounterMode_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup TIM1_Output_Compare_Polarity
+  * @{
+  */
+typedef enum
+{
+  TIM1_OCPolarity_High               = ((uint8_t)0x00),
+  TIM1_OCPolarity_Low                = ((uint8_t)0x22)
+}TIM1_OCPolarity_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup TIM1_Output_Compare_N_Polarity
+  * @{
+  */
+typedef enum
+{
+  TIM1_OCNPolarity_High              = ((uint8_t)0x00),
+  TIM1_OCNPolarity_Low               = ((uint8_t)0x88)
+}TIM1_OCNPolarity_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup TIM1_Output_State
+  * @{
+  */
+typedef enum
+{
+  TIM1_OutputState_Disable           = ((uint8_t)0x00),
+  TIM1_OutputState_Enable            = ((uint8_t)0x11)
+}TIM1_OutputState_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup TIM1_Output_N_State
+  * @{
+  */
+typedef enum
+{
+  TIM1_OutputNState_Disable = ((uint8_t)0x00),
+  TIM1_OutputNState_Enable  = ((uint8_t)0x44)
+} TIM1_OutputNState_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup TIM1_Break_State
+  * @{
+  */
+typedef enum
+{
+  TIM1_BreakState_Enable             = ((uint8_t)0x10),
+  TIM1_BreakState_Disable            = ((uint8_t)0x00)
+}TIM1_BreakState_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup TIM1_Break_Polarity
+  * @{
+  */
+typedef enum
+{
+  TIM1_BreakPolarity_Low             = ((uint8_t)0x00),
+  TIM1_BreakPolarity_High            = ((uint8_t)0x20)
+}TIM1_BreakPolarity_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup TIM1_Automatic_Output
+  * @{
+  */
+typedef enum
+{
+  TIM1_AutomaticOutput_Enable        = ((uint8_t)0x40),
+  TIM1_AutomaticOutput_Disable       = ((uint8_t)0x00)
+}TIM1_AutomaticOutput_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup TIM1_Lock_Level
+  * @{
+  */
+typedef enum
+{
+  TIM1_LockLevel_Off                 = ((uint8_t)0x00),
+  TIM1_LockLevel_1                   = ((uint8_t)0x01),
+  TIM1_LockLevel_2                   = ((uint8_t)0x02),
+  TIM1_LockLevel_3                   = ((uint8_t)0x03)
+}TIM1_LockLevel_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup TIM1_OSSI_State
+  * @{
+  */
+typedef enum
+{
+  TIM1_OSSIState_Enable              = ((uint8_t)0x04),
+  TIM1_OSSIState_Disable             = ((uint8_t)0x00)
+}TIM1_OSSIState_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup TIM1_Output_Compare_Idle_state
+  * @{
+  */
+typedef enum
+{
+  TIM1_OCIdleState_Set               = ((uint8_t)0x55),
+  TIM1_OCIdleState_Reset             = ((uint8_t)0x00)
+}TIM1_OCIdleState_TypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM1_Output_Compare_N_Idle_state
+  * @{
+  */
+typedef enum
+{
+  TIM1_OCNIdleState_Set             = ((uint8_t)0x2A),
+  TIM1_OCNIdleState_Reset           = ((uint8_t)0x00)
+}TIM1_OCNIdleState_TypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM1_Input_Capture_Polarity
+  * @{
+  */
+typedef enum
+{
+  TIM1_ICPolarity_Rising            = ((uint8_t)0x00),
+  TIM1_ICPolarity_Falling           = ((uint8_t)0x01)
+}TIM1_ICPolarity_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup TIM1_Input_Capture_Selection
+  * @{
+  */
+typedef enum
+{
+  TIM1_ICSelection_DirectTI          = ((uint8_t)0x01),
+  TIM1_ICSelection_IndirectTI        = ((uint8_t)0x02),
+  TIM1_ICSelection_TRGI              = ((uint8_t)0x03)
+}TIM1_ICSelection_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup TIM1_Input_Capture_Prescaler
+  * @{
+  */
+typedef enum
+{
+  TIM1_ICPSC_DIV1                    = ((uint8_t)0x00),
+  TIM1_ICPSC_DIV2                    = ((uint8_t)0x04),
+  TIM1_ICPSC_DIV4                    = ((uint8_t)0x08),
+  TIM1_ICPSC_DIV8                    = ((uint8_t)0x0C)
+}TIM1_ICPSC_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup TIM1_Output_Compare_Reference_Clear
+  * @{
+  */
+typedef enum
+{
+  TIM1_OCReferenceClear_ETRF       = ((uint8_t)0x08),
+  TIM1_OCReferenceClear_OCREFCLR   = ((uint8_t)0x00)
+}
+TIM1_OCReferenceClear_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup TIM1_Interrupts
+  * @{
+  */
+typedef enum
+{
+  TIM1_IT_Update                     = ((uint8_t)0x01),
+  TIM1_IT_CC1                        = ((uint8_t)0x02),
+  TIM1_IT_CC2                        = ((uint8_t)0x04),
+  TIM1_IT_CC3                        = ((uint8_t)0x08),
+  TIM1_IT_CC4                        = ((uint8_t)0x10),
+  TIM1_IT_COM                        = ((uint8_t)0x20),
+  TIM1_IT_Trigger                    = ((uint8_t)0x40),
+  TIM1_IT_Break                      = ((uint8_t)0x80)
+}TIM1_IT_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup TIM1_External_Trigger_Prescaler
+  * @{
+  */
+typedef enum
+{
+  TIM1_ExtTRGPSC_OFF                 = ((uint8_t)0x00),
+  TIM1_ExtTRGPSC_DIV2                = ((uint8_t)0x10),
+  TIM1_ExtTRGPSC_DIV4                = ((uint8_t)0x20),
+  TIM1_ExtTRGPSC_DIV8                = ((uint8_t)0x30)
+}TIM1_ExtTRGPSC_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup TIM1_Internal_Trigger_Selection
+  * @{
+  */
+typedef enum
+{
+  TIM1_TRGSelection_TIM4             = ((uint8_t)0x00),  /*!< TRIG Input source =  TIM TRIG Output  */
+  TIM1_TRGSelection_TIM5             = ((uint8_t)0x10),  /*!< TRIG Input source =  TIM TRIG Output  */
+  TIM1_TRGSelection_TIM3             = ((uint8_t)0x20),  /*!< TRIG Input source =  TIM TRIG Output  */
+  TIM1_TRGSelection_TIM2             = ((uint8_t)0x30),  /*!< TRIG Input source =  TIM TRIG Output  */
+  TIM1_TRGSelection_TI1F_ED          = ((uint8_t)0x40),
+  TIM1_TRGSelection_TI1FP1           = ((uint8_t)0x50),
+  TIM1_TRGSelection_TI2FP2           = ((uint8_t)0x60),
+  TIM1_TRGSelection_ETRF             = ((uint8_t)0x70)
+}TIM1_TRGSelection_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup TIM1_TI_External_Clock_Source
+  * @{
+  */
+typedef enum
+{
+  TIM1_TIxExternalCLK1Source_TI1ED   = ((uint8_t)0x40),
+  TIM1_TIxExternalCLK1Source_TI1     = ((uint8_t)0x50),
+  TIM1_TIxExternalCLK1Source_TI2     = ((uint8_t)0x60)
+}TIM1_TIxExternalCLK1Source_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup TIM1_External_Trigger_Polarity
+  * @{
+  */
+typedef enum
+{
+  TIM1_ExtTRGPolarity_Inverted       = ((uint8_t)0x80),
+  TIM1_ExtTRGPolarity_NonInverted    = ((uint8_t)0x00)
+}TIM1_ExtTRGPolarity_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup TIM1_Prescaler_Reload_Mode
+  * @{
+  */
+typedef enum
+{
+  TIM1_PSCReloadMode_Update          = ((uint8_t)0x00),
+  TIM1_PSCReloadMode_Immediate       = ((uint8_t)0x01)
+}TIM1_PSCReloadMode_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup TIM1_Encoder_Mode
+  * @{
+  */
+typedef enum
+{
+  TIM1_EncoderMode_TI1               = ((uint8_t)0x01),
+  TIM1_EncoderMode_TI2               = ((uint8_t)0x02),
+  TIM1_EncoderMode_TI12              = ((uint8_t)0x03)
+}TIM1_EncoderMode_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup TIM1_Event_Source
+  * @{
+  */
+typedef enum
+{
+  TIM1_EventSource_Update            = ((uint8_t)0x01),
+  TIM1_EventSource_CC1               = ((uint8_t)0x02),
+  TIM1_EventSource_CC2               = ((uint8_t)0x04),
+  TIM1_EventSource_CC3               = ((uint8_t)0x08),
+  TIM1_EventSource_CC4               = ((uint8_t)0x10),
+  TIM1_EventSource_COM               = ((uint8_t)0x20),
+  TIM1_EventSource_Trigger           = ((uint8_t)0x40),
+  TIM1_EventSource_Break             = ((uint8_t)0x80)
+}TIM1_EventSource_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup TIM1_Update_Source
+  * @{
+  */
+typedef enum
+{
+  TIM1_UpdateSource_Global           = ((uint8_t)0x00),
+  TIM1_UpdateSource_Regular          = ((uint8_t)0x01)
+}TIM1_UpdateSource_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup TIM1_Trigger_Output_Source
+  * @{
+  */
+typedef enum
+{
+  TIM1_TRGOSource_Reset              = ((uint8_t)0x00),
+  TIM1_TRGOSource_Enable             = ((uint8_t)0x10),
+  TIM1_TRGOSource_Update             = ((uint8_t)0x20),
+  TIM1_TRGOSource_OC1                = ((uint8_t)0x30),
+  TIM1_TRGOSource_OC1REF             = ((uint8_t)0x40),
+  TIM1_TRGOSource_OC2REF             = ((uint8_t)0x50),
+  TIM1_TRGOSource_OC3REF             = ((uint8_t)0x60),
+  TIM1_TRGOSource_OC4REF             = ((uint8_t)0x70)
+}TIM1_TRGOSource_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup TIM1_Slave_Mode
+  * @{
+  */
+typedef enum
+{
+  TIM1_SlaveMode_Reset               = ((uint8_t)0x04),
+  TIM1_SlaveMode_Gated               = ((uint8_t)0x05),
+  TIM1_SlaveMode_Trigger             = ((uint8_t)0x06),
+  TIM1_SlaveMode_External1           = ((uint8_t)0x07)
+}TIM1_SlaveMode_TypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM1_Flags
+  * @{
+  */
+typedef enum
+{
+  TIM1_FLAG_Update                   = ((uint16_t)0x0001),
+  TIM1_FLAG_CC1                      = ((uint16_t)0x0002),
+  TIM1_FLAG_CC2                      = ((uint16_t)0x0004),
+  TIM1_FLAG_CC3                      = ((uint16_t)0x0008),
+  TIM1_FLAG_CC4                      = ((uint16_t)0x0010),
+  TIM1_FLAG_COM                      = ((uint16_t)0x0020),
+  TIM1_FLAG_Trigger                  = ((uint16_t)0x0040),
+  TIM1_FLAG_Break                    = ((uint16_t)0x0080),
+  TIM1_FLAG_CC1OF                    = ((uint16_t)0x0200),
+  TIM1_FLAG_CC2OF                    = ((uint16_t)0x0400),
+  TIM1_FLAG_CC3OF                    = ((uint16_t)0x0800),
+  TIM1_FLAG_CC4OF                    = ((uint16_t)0x1000)
+}TIM1_FLAG_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup TIM1_Forced_Action
+  * @{
+  */
+typedef enum
+{
+  TIM1_ForcedAction_Active           = ((uint8_t)0x50),
+  TIM1_ForcedAction_Inactive         = ((uint8_t)0x40)
+}TIM1_ForcedAction_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup TIM1_DMA_Source_Requests
+  * @{
+  */
+typedef enum
+{
+  TIM1_DMASource_Update     = ((uint8_t)0x01),  /*!< TIM1 DMA Update Request*/
+  TIM1_DMASource_CC1        = ((uint8_t)0x02),  /*!< TIM1 DMA CC1 Request*/
+  TIM1_DMASource_CC2        = ((uint8_t)0x04),  /*!< TIM1 DMA CC2 Request*/
+  TIM1_DMASource_CC3        = ((uint8_t)0x08),  /*!< TIM1 DMA CC3 Request*/
+  TIM1_DMASource_CC4        = ((uint8_t)0x10),  /*!< TIM1 DMA CC4 Request*/
+  TIM1_DMASource_COM        = ((uint8_t)0x20)  /*!< TIM1 DMA COM Req */
+} TIM1_DMASource_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup TIM1_DMA_Base_Address
+  * @{
+  */
+typedef enum
+{
+  TIM1_DMABase_CR1      = ((uint8_t)0x00),
+  TIM1_DMABase_CR2      = ((uint8_t)0x01),
+  TIM1_DMABase_SMCR     = ((uint8_t)0x02),
+  TIM1_DMABase_ETR      = ((uint8_t)0x03),
+  TIM1_DMABase_DER      = ((uint8_t)0x04),
+  TIM1_DMABase_IER      = ((uint8_t)0x05),
+  TIM1_DMABase_SR1      = ((uint8_t)0x06),
+  TIM1_DMABase_SR2      = ((uint8_t)0x07),
+  TIM1_DMABase_EGR      = ((uint8_t)0x08),
+  TIM1_DMABase_CCMR1    = ((uint8_t)0x09),
+  TIM1_DMABase_CCMR2    = ((uint8_t)0x0A),
+  TIM1_DMABase_CCMR3    = ((uint8_t)0x0B),
+  TIM1_DMABase_CCMR4    = ((uint8_t)0x0C),
+  TIM1_DMABase_CCER1    = ((uint8_t)0x0D),
+  TIM1_DMABase_CCER2    = ((uint8_t)0x0E),
+  TIM1_DMABase_CNTH     = ((uint8_t)0x0F),
+  TIM1_DMABase_CNTL     = ((uint8_t)0x10),
+  TIM1_DMABase_PSCH     = ((uint8_t)0x11),
+  TIM1_DMABase_PSCL     = ((uint8_t)0x12),
+  TIM1_DMABase_ARRH     = ((uint8_t)0x13),
+  TIM1_DMABase_ARRL     = ((uint8_t)0x14),
+  TIM1_DMABase_RCR      = ((uint8_t)0x15),
+  TIM1_DMABase_CCR1H    = ((uint8_t)0x16),
+  TIM1_DMABase_CCR1L    = ((uint8_t)0x17),
+  TIM1_DMABase_CCR2H    = ((uint8_t)0x18),
+  TIM1_DMABase_CCR2L    = ((uint8_t)0x19),
+  TIM1_DMABase_CCR3H    = ((uint8_t)0x1A),
+  TIM1_DMABase_CCR3L    = ((uint8_t)0x1B),
+  TIM1_DMABase_CCR4H    = ((uint8_t)0x1C),
+  TIM1_DMABase_CCR4L    = ((uint8_t)0x1D),
+  TIM1_DMABase_BKR      = ((uint8_t)0x1E),
+  TIM1_DMABase_DTR      = ((uint8_t)0x1F)
+
+} TIM1_DMABase_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup TIM1_DMA_Burst_Length
+  * @{
+  */
+typedef enum
+{
+  TIM1_DMABurstLength_1Byte      = ((uint8_t)0x00),
+  TIM1_DMABurstLength_2Byte      = ((uint8_t)0x01),
+  TIM1_DMABurstLength_3Byte      = ((uint8_t)0x02),
+  TIM1_DMABurstLength_4Byte      = ((uint8_t)0x03),
+  TIM1_DMABurstLength_5Byte      = ((uint8_t)0x04),
+  TIM1_DMABurstLength_6Byte      = ((uint8_t)0x05),
+  TIM1_DMABurstLength_7Byte      = ((uint8_t)0x06),
+  TIM1_DMABurstLength_8Byte      = ((uint8_t)0x07),
+  TIM1_DMABurstLength_9Byte      = ((uint8_t)0x08),
+  TIM1_DMABurstLength_10Byte     = ((uint8_t)0x09),
+  TIM1_DMABurstLength_11Byte     = ((uint8_t)0x0A),
+  TIM1_DMABurstLength_12Byte     = ((uint8_t)0x0B),
+  TIM1_DMABurstLength_13Byte     = ((uint8_t)0x0C),
+  TIM1_DMABurstLength_14Byte     = ((uint8_t)0x0D),
+  TIM1_DMABurstLength_15Byte     = ((uint8_t)0x0E),
+  TIM1_DMABurstLength_16Byte     = ((uint8_t)0x0F),
+  TIM1_DMABurstLength_17Byte     = ((uint8_t)0x10),
+  TIM1_DMABurstLength_18Byte     = ((uint8_t)0x11),
+  TIM1_DMABurstLength_19Byte     = ((uint8_t)0x12),
+  TIM1_DMABurstLength_20Byte     = ((uint8_t)0x13),
+  TIM1_DMABurstLength_21Byte     = ((uint8_t)0x14),
+  TIM1_DMABurstLength_22Byte     = ((uint8_t)0x15),
+  TIM1_DMABurstLength_23Byte     = ((uint8_t)0x16),
+  TIM1_DMABurstLength_24Byte     = ((uint8_t)0x17),
+  TIM1_DMABurstLength_25Byte     = ((uint8_t)0x18),
+  TIM1_DMABurstLength_26Byte     = ((uint8_t)0x19),
+  TIM1_DMABurstLength_27Byte     = ((uint8_t)0x1A),
+  TIM1_DMABurstLength_28Byte     = ((uint8_t)0x1B),
+  TIM1_DMABurstLength_29Byte     = ((uint8_t)0x1C),
+  TIM1_DMABurstLength_30Byte     = ((uint8_t)0x1D),
+  TIM1_DMABurstLength_31Byte     = ((uint8_t)0x1E),
+  TIM1_DMABurstLength_32Byte     = ((uint8_t)0x1F)
+
+} TIM1_DMABurstLength_TypeDef;
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup TIM1_Exported_Macros
+  * @{
+  */
+#define IS_TIM1_OC_MODE(MODE) (((MODE) ==  TIM1_OCMode_Timing) || \
+                               ((MODE) == TIM1_OCMode_Active) || \
+                               ((MODE) == TIM1_OCMode_Inactive) || \
+                               ((MODE) == TIM1_OCMode_Toggle)|| \
+                               ((MODE) == TIM1_OCMode_PWM1) || \
+                               ((MODE) == TIM1_OCMode_PWM2))
+
+#define IS_TIM1_OCM(MODE)(((MODE) ==  TIM1_OCMode_Timing) || \
+                          ((MODE) == TIM1_OCMode_Active) || \
+                          ((MODE) == TIM1_OCMode_Inactive) || \
+                          ((MODE) == TIM1_OCMode_Toggle)|| \
+                          ((MODE) == TIM1_OCMode_PWM1) || \
+                          ((MODE) == TIM1_OCMode_PWM2) || \
+                          ((MODE) == (uint8_t)TIM1_ForcedAction_Active) || \
+                          ((MODE) == (uint8_t)TIM1_ForcedAction_Inactive))
+
+#define IS_TIM1_OPM_MODE(MODE) (((MODE) == TIM1_OPMode_Single) || \
+                                ((MODE) == TIM1_OPMode_Repetitive))
+
+#define IS_TIM1_CHANNEL(CHANNEL) (((CHANNEL) == TIM1_Channel_1) || \
+                                  ((CHANNEL) == TIM1_Channel_2) || \
+                                  ((CHANNEL) == TIM1_Channel_3) || \
+                                  ((CHANNEL) == TIM1_Channel_4))
+
+#define IS_TIM1_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM1_Channel_1) || \
+                                       ((CHANNEL) == TIM1_Channel_2))
+
+#define IS_TIM1_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM1_Channel_1) || \
+    ((CHANNEL) == TIM1_Channel_2) || \
+    ((CHANNEL) == TIM1_Channel_3))
+
+#define IS_TIM1_COUNTER_MODE(MODE) (((MODE) == TIM1_CounterMode_Up) || \
+                                    ((MODE) == TIM1_CounterMode_Down) || \
+                                    ((MODE) == TIM1_CounterMode_CenterAligned1) || \
+                                    ((MODE) == TIM1_CounterMode_CenterAligned2) || \
+                                    ((MODE) == TIM1_CounterMode_CenterAligned3))
+
+#define IS_TIM1_OC_POLARITY(POLARITY) (((POLARITY) == TIM1_OCPolarity_High) || \
+                                       ((POLARITY) == TIM1_OCPolarity_Low))
+
+#define IS_TIM1_OCN_POLARITY(POLARITY) (((POLARITY) == TIM1_OCNPolarity_High) || \
+                                        ((POLARITY) == TIM1_OCNPolarity_Low))
+
+#define IS_TIM1_OUTPUT_STATE(STATE) (((STATE) == TIM1_OutputState_Disable) || \
+                                     ((STATE) == TIM1_OutputState_Enable))
+
+#define IS_TIM1_OUTPUTN_STATE(STATE) (((STATE) == TIM1_OutputNState_Disable) ||\
+                                      ((STATE) == TIM1_OutputNState_Enable))
+
+#define IS_TIM1_BREAK_STATE(STATE) (((STATE) == TIM1_BreakState_Enable) || \
+                                    ((STATE) == TIM1_BreakState_Disable))
+
+#define IS_TIM1_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM1_BreakPolarity_Low) || \
+    ((POLARITY) == TIM1_BreakPolarity_High))
+
+#define IS_TIM1_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM1_AutomaticOutput_Enable) || \
+    ((STATE) == TIM1_AutomaticOutput_Disable))
+
+#define IS_TIM1_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM1_LockLevel_Off) || \
+                                   ((LEVEL) == TIM1_LockLevel_1) || \
+                                   ((LEVEL) == TIM1_LockLevel_2) || \
+                                   ((LEVEL) == TIM1_LockLevel_3))
+
+#define IS_TIM1_OSSI_STATE(STATE) (((STATE) == TIM1_OSSIState_Enable) || \
+                                   ((STATE) == TIM1_OSSIState_Disable))
+
+#define IS_TIM1_OCIDLE_STATE(STATE) (((STATE) == TIM1_OCIdleState_Set) || \
+                                     ((STATE) == TIM1_OCIdleState_Reset))
+
+#define IS_TIM1_OCNIDLE_STATE(STATE) (((STATE) == TIM1_OCNIdleState_Set) || \
+                                      ((STATE) == TIM1_OCNIdleState_Reset))
+
+#define IS_TIM1_IC_POLARITY(POLARITY) (((POLARITY) == TIM1_ICPolarity_Rising) || \
+                                       ((POLARITY) == TIM1_ICPolarity_Falling))
+
+#define IS_TIM1_IC_SELECTION(SELECTION) (((SELECTION) == TIM1_ICSelection_DirectTI) || \
+    ((SELECTION) == TIM1_ICSelection_IndirectTI) || \
+    ((SELECTION) == TIM1_ICSelection_TRGI))
+
+#define IS_TIM1_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM1_ICPSC_DIV1) || \
+    ((PRESCALER) == TIM1_ICPSC_DIV2) || \
+    ((PRESCALER) == TIM1_ICPSC_DIV4) || \
+    ((PRESCALER) == TIM1_ICPSC_DIV8))
+
+#define IS_TIM1_OCREFERENCECECLEAR_SOURCE(SOURCE) (((SOURCE) == TIM1_OCReferenceClear_ETRF) || \
+    ((SOURCE) == TIM1_OCReferenceClear_OCREFCLR))
+
+#define IS_TIM1_IT(IT) ((IT) != 0x00)
+
+#define IS_TIM1_GET_IT(IT) (((IT) == TIM1_IT_Update) || \
+                            ((IT) == TIM1_IT_CC1) || \
+                            ((IT) == TIM1_IT_CC2) || \
+                            ((IT) == TIM1_IT_CC3) || \
+                            ((IT) == TIM1_IT_CC4) || \
+                            ((IT) == TIM1_IT_COM) || \
+                            ((IT) == TIM1_IT_Trigger) || \
+                            ((IT) == TIM1_IT_Break))
+
+#define IS_TIM1_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM1_ExtTRGPSC_OFF) || \
+    ((PRESCALER) == TIM1_ExtTRGPSC_DIV2) || \
+    ((PRESCALER) == TIM1_ExtTRGPSC_DIV4) || \
+    ((PRESCALER) == TIM1_ExtTRGPSC_DIV8))
+
+#define IS_TIM1_TRIGGER_SELECTION(SELECTION) \
+  (((SELECTION) == TIM1_TRGSelection_TIM2) || \
+   ((SELECTION) == TIM1_TRGSelection_TIM3) || \
+   ((SELECTION) == TIM1_TRGSelection_TIM4) || \
+   ((SELECTION) == TIM1_TRGSelection_TIM5) || \
+   ((SELECTION) == TIM1_TRGSelection_TI1F_ED) || \
+   ((SELECTION) == TIM1_TRGSelection_TI1FP1) || \
+   ((SELECTION) == TIM1_TRGSelection_TI2FP2) || \
+   ((SELECTION) == TIM1_TRGSelection_ETRF))
+
+
+#define IS_TIM1_TIX_TRIGGER_SELECTION(SELECTION) \
+  (((SELECTION) == TIM1_TRGSelection_TI1F_ED) || \
+   ((SELECTION) == TIM1_TRGSelection_TI1FP1) || \
+   ((SELECTION) == TIM1_TRGSelection_TI2FP2))
+
+#define IS_TIM1_TIXCLK_SOURCE(SOURCE)  (((SOURCE) == TIM1_TIxExternalCLK1Source_TI1ED) || \
+                                        ((SOURCE) == TIM1_TIxExternalCLK1Source_TI2) || \
+                                        ((SOURCE) == TIM1_TIxExternalCLK1Source_TI1))
+
+#define IS_TIM1_EXT_POLARITY(POLARITY) (((POLARITY) == TIM1_ExtTRGPolarity_Inverted) || \
+                                        ((POLARITY) == TIM1_ExtTRGPolarity_NonInverted))
+
+#define IS_TIM1_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM1_PSCReloadMode_Update) || \
+    ((RELOAD) == TIM1_PSCReloadMode_Immediate))
+
+#define IS_TIM1_ENCODER_MODE(MODE) (((MODE) == TIM1_EncoderMode_TI1) || \
+                                    ((MODE) == TIM1_EncoderMode_TI2) || \
+                                    ((MODE) == TIM1_EncoderMode_TI12))
+
+#define IS_TIM1_EVENT_SOURCE(SOURCE) ((SOURCE) != 0x00)
+
+#define IS_TIM1_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM1_TRGOSource_Reset) || \
+                                     ((SOURCE) == TIM1_TRGOSource_Enable) || \
+                                     ((SOURCE) == TIM1_TRGOSource_Update) || \
+                                     ((SOURCE) == TIM1_TRGOSource_OC1)  || \
+                                     ((SOURCE) == TIM1_TRGOSource_OC1REF) || \
+                                     ((SOURCE) == TIM1_TRGOSource_OC2REF) || \
+                                     ((SOURCE) == TIM1_TRGOSource_OC3REF) || \
+                                     ((SOURCE) == TIM1_TRGOSource_OC4REF))
+
+
+#define IS_TIM1_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM1_UpdateSource_Global) || \
+                                       ((SOURCE) == TIM1_UpdateSource_Regular))
+
+#define IS_TIM1_GET_FLAG(FLAG) (((FLAG) == TIM1_FLAG_Update) || \
+                                ((FLAG) == TIM1_FLAG_CC1)    || \
+                                ((FLAG) == TIM1_FLAG_CC2)    || \
+                                ((FLAG) == TIM1_FLAG_CC3)    || \
+                                ((FLAG) == TIM1_FLAG_CC4)    || \
+                                ((FLAG) == TIM1_FLAG_COM)    || \
+                                ((FLAG) == TIM1_FLAG_Trigger)|| \
+                                ((FLAG) == TIM1_FLAG_Break)  || \
+                                ((FLAG) == TIM1_FLAG_CC1OF)  || \
+                                ((FLAG) == TIM1_FLAG_CC2OF)  || \
+                                ((FLAG) == TIM1_FLAG_CC3OF)  || \
+                                ((FLAG) == TIM1_FLAG_CC4OF))
+
+
+#define IS_TIM1_SLAVE_MODE(MODE) (((MODE) == TIM1_SlaveMode_Reset) || \
+                                  ((MODE) == TIM1_SlaveMode_Gated) || \
+                                  ((MODE) == TIM1_SlaveMode_Trigger) || \
+                                  ((MODE) == TIM1_SlaveMode_External1))
+
+#define IS_TIM1_CLEAR_FLAG(FLAG) ((((uint16_t)(FLAG) & (uint16_t)0xE100) == 0x0000) && ((FLAG) != 0x0000))
+
+#define IS_TIM1_FORCED_ACTION(ACTION) (((ACTION) == TIM1_ForcedAction_Active) || \
+                                       ((ACTION) == TIM1_ForcedAction_Inactive))
+
+#define IS_TIM1_DMA_SOURCE(SOURCE) \
+  (((SOURCE) == TIM1_DMASource_Update) || \
+   ((SOURCE) == TIM1_DMASource_CC1) || \
+   ((SOURCE) == TIM1_DMASource_CC2) || \
+   ((SOURCE) == TIM1_DMASource_CC3) || \
+   ((SOURCE) == TIM1_DMASource_CC4) || \
+   ((SOURCE) == TIM1_DMASource_COM))
+
+#define IS_TIM1_DMABase(SOURCE) \
+  (((SOURCE) == TIM1_DMABase_CR1)  || \
+   ((SOURCE) == TIM1_DMABase_CR2)  || \
+   ((SOURCE) == TIM1_DMABase_SMCR) || \
+   ((SOURCE) == TIM1_DMABase_ETR) || \
+   ((SOURCE) == TIM1_DMABase_DER) || \
+   ((SOURCE) == TIM1_DMABase_IER) || \
+   ((SOURCE) == TIM1_DMABase_SR1) || \
+   ((SOURCE) == TIM1_DMABase_SR2) || \
+   ((SOURCE) == TIM1_DMABase_EGR) || \
+   ((SOURCE) == TIM1_DMABase_CCMR1) || \
+   ((SOURCE) == TIM1_DMABase_CCMR2  ) || \
+   ((SOURCE) == TIM1_DMABase_CCMR3) || \
+   ((SOURCE) == TIM1_DMABase_CCMR4) || \
+   ((SOURCE) == TIM1_DMABase_CCER1) || \
+   ((SOURCE) == TIM1_DMABase_CCER2) || \
+   ((SOURCE) == TIM1_DMABase_CNTH) || \
+   ((SOURCE) == TIM1_DMABase_CNTL) || \
+   ((SOURCE) == TIM1_DMABase_PSCH) || \
+   ((SOURCE) == TIM1_DMABase_PSCL) || \
+   ((SOURCE) == TIM1_DMABase_ARRH) || \
+   ((SOURCE) == TIM1_DMABase_ARRL) || \
+   ((SOURCE) == TIM1_DMABase_RCR)  || \
+   ((SOURCE) == TIM1_DMABase_CCR1H) || \
+   ((SOURCE) == TIM1_DMABase_CCR1L) || \
+   ((SOURCE) == TIM1_DMABase_CCR2H  ) || \
+   ((SOURCE) == TIM1_DMABase_CCR2L) || \
+   ((SOURCE) == TIM1_DMABase_CCR3H) || \
+   ((SOURCE) == TIM1_DMABase_CCR3L) || \
+   ((SOURCE) == TIM1_DMABase_CCR4H) || \
+   ((SOURCE) == TIM1_DMABase_CCR4L) || \
+   ((SOURCE) == TIM1_DMABase_BKR) || \
+   ((SOURCE) == TIM1_DMABase_DTR))
+
+#define IS_TIM1_DMABurstLength(SOURCE) \
+  (((SOURCE)  == TIM1_DMABurstLength_1Byte)  || \
+   ((SOURCE) == TIM1_DMABurstLength_2Byte)  || \
+   ((SOURCE) == TIM1_DMABurstLength_3Byte) || \
+   ((SOURCE) == TIM1_DMABurstLength_4Byte) || \
+   ((SOURCE) == TIM1_DMABurstLength_5Byte) || \
+   ((SOURCE) == TIM1_DMABurstLength_6Byte) || \
+   ((SOURCE) == TIM1_DMABurstLength_7Byte) || \
+   ((SOURCE) == TIM1_DMABurstLength_8Byte) || \
+   ((SOURCE) == TIM1_DMABurstLength_9Byte) || \
+   ((SOURCE) == TIM1_DMABurstLength_10Byte) || \
+   ((SOURCE) == TIM1_DMABurstLength_11Byte  ) || \
+   ((SOURCE) == TIM1_DMABurstLength_12Byte) || \
+   ((SOURCE) == TIM1_DMABurstLength_13Byte) || \
+   ((SOURCE) == TIM1_DMABurstLength_14Byte) || \
+   ((SOURCE) == TIM1_DMABurstLength_15Byte) || \
+   ((SOURCE) == TIM1_DMABurstLength_16Byte) || \
+   ((SOURCE) == TIM1_DMABurstLength_17Byte) || \
+   ((SOURCE) == TIM1_DMABurstLength_18Byte) || \
+   ((SOURCE) == TIM1_DMABurstLength_19Byte) || \
+   ((SOURCE) == TIM1_DMABurstLength_20Byte) || \
+   ((SOURCE) == TIM1_DMABurstLength_21Byte) || \
+   ((SOURCE) == TIM1_DMABurstLength_22Byte) || \
+   ((SOURCE) == TIM1_DMABurstLength_23Byte) || \
+   ((SOURCE) == TIM1_DMABurstLength_24Byte) || \
+   ((SOURCE) == TIM1_DMABurstLength_25Byte) || \
+   ((SOURCE) == TIM1_DMABurstLength_26Byte) || \
+   ((SOURCE) == TIM1_DMABurstLength_27Byte) || \
+   ((SOURCE) == TIM1_DMABurstLength_28Byte) || \
+   ((SOURCE) == TIM1_DMABurstLength_29Byte) || \
+   ((SOURCE) == TIM1_DMABurstLength_30Byte) || \
+   ((SOURCE) == TIM1_DMABurstLength_31Byte) || \
+   ((SOURCE) == TIM1_DMABurstLength_32Byte))
+
+/** TIM1 External Trigger Filer Value */
+#define IS_TIM1_EXT_TRG_FILTER(FILTER) ((FILTER) <= 0x0F)
+
+/** TIM1 Input Capture Filer Value */
+#define IS_TIM1_IC_FILTER(ICFILTER) ((ICFILTER) <= 0x0F)
+/**
+  * @}
+  */
+
+/* Exported Functions -----------------------------------------------------------*/
+
+/* TimeBase management ********************************************************/
+void TIM1_DeInit(void);
+void TIM1_TimeBaseInit(uint16_t TIM1_Prescaler,
+                       TIM1_CounterMode_TypeDef TIM1_CounterMode,
+                       uint16_t TIM1_Period,
+                       uint8_t TIM1_RepetitionCounter);
+void TIM1_PrescalerConfig(uint16_t Prescaler,
+                          TIM1_PSCReloadMode_TypeDef TIM1_PSCReloadMode);
+void TIM1_CounterModeConfig(TIM1_CounterMode_TypeDef TIM1_CounterMode);
+void TIM1_SetCounter(uint16_t Counter);
+void TIM1_SetAutoreload(uint16_t Autoreload);
+uint16_t TIM1_GetCounter(void);
+uint16_t TIM1_GetPrescaler(void);
+void TIM1_UpdateDisableConfig(FunctionalState NewState);
+void TIM1_UpdateRequestConfig(TIM1_UpdateSource_TypeDef TIM1_UpdateSource);
+void TIM1_ARRPreloadConfig(FunctionalState NewState);
+void TIM1_SelectOnePulseMode(TIM1_OPMode_TypeDef TIM1_OPMode);
+void TIM1_Cmd(FunctionalState NewState);
+
+/* Output Compare management **************************************************/
+void TIM1_OC1Init(TIM1_OCMode_TypeDef TIM1_OCMode,
+                  TIM1_OutputState_TypeDef TIM1_OutputState,
+                  TIM1_OutputNState_TypeDef TIM1_OutputNState,
+                  uint16_t TIM1_Pulse,
+                  TIM1_OCPolarity_TypeDef TIM1_OCPolarity,
+                  TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity,
+                  TIM1_OCIdleState_TypeDef TIM1_OCIdleState,
+                  TIM1_OCNIdleState_TypeDef TIM1_OCNIdleState);
+void TIM1_OC2Init(TIM1_OCMode_TypeDef TIM1_OCMode,
+                  TIM1_OutputState_TypeDef TIM1_OutputState,
+                  TIM1_OutputNState_TypeDef TIM1_OutputNState,
+                  uint16_t TIM1_Pulse,
+                  TIM1_OCPolarity_TypeDef TIM1_OCPolarity,
+                  TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity,
+                  TIM1_OCIdleState_TypeDef TIM1_OCIdleState,
+                  TIM1_OCNIdleState_TypeDef TIM1_OCNIdleState);
+void TIM1_OC3Init(TIM1_OCMode_TypeDef TIM1_OCMode,
+                  TIM1_OutputState_TypeDef TIM1_OutputState,
+                  TIM1_OutputNState_TypeDef TIM1_OutputNState,
+                  uint16_t TIM1_Pulse,
+                  TIM1_OCPolarity_TypeDef TIM1_OCPolarity,
+                  TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity,
+                  TIM1_OCIdleState_TypeDef TIM1_OCIdleState,
+                  TIM1_OCNIdleState_TypeDef TIM1_OCNIdleState);
+void TIM1_BDTRConfig(TIM1_OSSIState_TypeDef TIM1_OSSIState,
+                     TIM1_LockLevel_TypeDef TIM1_LockLevel,
+                     uint8_t TIM1_DeadTime,
+                     TIM1_BreakState_TypeDef TIM1_Break,
+                     TIM1_BreakPolarity_TypeDef TIM1_BreakPolarity,
+                     TIM1_AutomaticOutput_TypeDef TIM1_AutomaticOutput);
+void TIM1_CtrlPWMOutputs(FunctionalState NewState);
+void TIM1_SelectOCxM(TIM1_Channel_TypeDef TIM1_Channel, TIM1_OCMode_TypeDef TIM1_OCMode);
+void TIM1_SetCompare1(uint16_t Compare1);
+void TIM1_SetCompare2(uint16_t Compare2);
+void TIM1_SetCompare3(uint16_t Compare3);
+void TIM1_SetCompare4(uint16_t Compare4);
+void TIM1_CCPreloadControl(FunctionalState NewState);
+void TIM1_ForcedOC1Config(TIM1_ForcedAction_TypeDef TIM1_ForcedAction);
+void TIM1_ForcedOC2Config(TIM1_ForcedAction_TypeDef TIM1_ForcedAction);
+void TIM1_ForcedOC3Config(TIM1_ForcedAction_TypeDef TIM1_ForcedAction);
+void TIM1_OC1PreloadConfig(FunctionalState NewState);
+void TIM1_OC2PreloadConfig(FunctionalState NewState);
+void TIM1_OC3PreloadConfig(FunctionalState NewState);
+void TIM1_OC4PreloadConfig(FunctionalState NewState);
+void TIM1_OC1FastConfig(FunctionalState NewState);
+void TIM1_OC2FastConfig(FunctionalState NewState);
+void TIM1_OC3FastConfig(FunctionalState NewState);
+void TIM1_ClearOC1Ref(FunctionalState NewState);
+void TIM1_ClearOC2Ref(FunctionalState NewState);
+void TIM1_ClearOC3Ref(FunctionalState NewState);
+void TIM1_ClearOC4Ref(FunctionalState NewState);
+void TIM1_OC1PolarityConfig(TIM1_OCPolarity_TypeDef TIM1_OCPolarity);
+void TIM1_OC1NPolarityConfig(TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity);
+void TIM1_OC2PolarityConfig(TIM1_OCPolarity_TypeDef TIM1_OCPolarity);
+void TIM1_OC2NPolarityConfig(TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity);
+void TIM1_OC3PolarityConfig(TIM1_OCPolarity_TypeDef TIM1_OCPolarity);
+void TIM1_OC3NPolarityConfig(TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity);
+void TIM1_SelectOCREFClear(TIM1_OCReferenceClear_TypeDef TIM1_OCReferenceClear);
+void TIM1_SelectCOM(FunctionalState NewState);
+void TIM1_CCxCmd(TIM1_Channel_TypeDef TIM1_Channel, FunctionalState NewState);
+void TIM1_CCxNCmd(TIM1_Channel_TypeDef TIM1_Channel, FunctionalState NewState);
+
+/* Input Capture management ***************************************************/
+void TIM1_ICInit(TIM1_Channel_TypeDef TIM1_Channel,
+                 TIM1_ICPolarity_TypeDef TIM1_ICPolarity,
+                 TIM1_ICSelection_TypeDef TIM1_ICSelection,
+                 TIM1_ICPSC_TypeDef TIM1_ICPrescaler,
+                 uint8_t TIM1_ICFilter);
+void TIM1_PWMIConfig(TIM1_Channel_TypeDef TIM1_Channel,
+                     TIM1_ICPolarity_TypeDef TIM1_ICPolarity,
+                     TIM1_ICSelection_TypeDef TIM1_ICSelection,
+                     TIM1_ICPSC_TypeDef TIM1_ICPrescaler,
+                     uint8_t TIM1_ICFilter);
+uint16_t TIM1_GetCapture1(void);
+uint16_t TIM1_GetCapture2(void);
+uint16_t TIM1_GetCapture3(void);
+uint16_t TIM1_GetCapture4(void);
+void TIM1_SetIC1Prescaler(TIM1_ICPSC_TypeDef TIM1_IC1Prescaler);
+void TIM1_SetIC2Prescaler(TIM1_ICPSC_TypeDef TIM1_IC2Prescaler);
+void TIM1_SetIC3Prescaler(TIM1_ICPSC_TypeDef TIM1_IC3Prescaler);
+void TIM1_SetIC4Prescaler(TIM1_ICPSC_TypeDef TIM1_IC4Prescaler);
+
+/* Interrupts, DMA and flags management ***************************************/
+void TIM1_ITConfig(TIM1_IT_TypeDef TIM1_IT, FunctionalState NewState);
+void TIM1_GenerateEvent(TIM1_EventSource_TypeDef TIM1_EventSource);
+FlagStatus TIM1_GetFlagStatus(TIM1_FLAG_TypeDef TIM1_FLAG);
+void TIM1_ClearFlag(TIM1_FLAG_TypeDef TIM1_FLAG);
+ITStatus TIM1_GetITStatus(TIM1_IT_TypeDef TIM1_IT);
+void TIM1_ClearITPendingBit(TIM1_IT_TypeDef TIM1_IT);
+void TIM1_DMAConfig(TIM1_DMABase_TypeDef TIM1_DMABase,
+                    TIM1_DMABurstLength_TypeDef TIM1_DMABurstLength);
+void TIM1_DMACmd(TIM1_DMASource_TypeDef TIM1_DMASource, FunctionalState NewState);
+void TIM1_SelectCCDMA(FunctionalState NewState);
+
+/* Clocks management **********************************************************/
+void TIM1_InternalClockConfig(void);
+void TIM1_TIxExternalClockConfig(TIM1_TIxExternalCLK1Source_TypeDef TIM1_TIxExternalCLKSource,
+                                 TIM1_ICPolarity_TypeDef TIM1_ICPolarity,
+                                 uint8_t ICFilter);
+void TIM1_ETRClockMode1Config(TIM1_ExtTRGPSC_TypeDef TIM1_ExtTRGPrescaler,
+                              TIM1_ExtTRGPolarity_TypeDef TIM1_ExtTRGPolarity,
+                              uint8_t ExtTRGFilter);
+void TIM1_ETRClockMode2Config(TIM1_ExtTRGPSC_TypeDef TIM1_ExtTRGPrescaler,
+                              TIM1_ExtTRGPolarity_TypeDef TIM1_ExtTRGPolarity,
+                              uint8_t ExtTRGFilter);
+                              
+/* Synchronization management *************************************************/
+void TIM1_SelectInputTrigger(TIM1_TRGSelection_TypeDef TIM1_InputTriggerSource);
+void TIM1_SelectOutputTrigger(TIM1_TRGOSource_TypeDef TIM1_TRGOSource);
+void TIM1_SelectSlaveMode(TIM1_SlaveMode_TypeDef TIM1_SlaveMode);
+void TIM1_SelectMasterSlaveMode(FunctionalState NewState);
+void TIM1_ETRConfig(TIM1_ExtTRGPSC_TypeDef TIM1_ExtTRGPrescaler,
+                    TIM1_ExtTRGPolarity_TypeDef TIM1_ExtTRGPolarity,
+                    uint8_t ExtTRGFilter);
+
+/* Specific interface management **********************************************/
+void TIM1_EncoderInterfaceConfig(TIM1_EncoderMode_TypeDef TIM1_EncoderMode,
+                                 TIM1_ICPolarity_TypeDef TIM1_IC1Polarity,
+                                 TIM1_ICPolarity_TypeDef TIM1_IC2Polarity);
+void TIM1_SelectHallSensor(FunctionalState NewState);
+
+#endif /* __STM8L15x_TIM1_H */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_tim2.h b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_tim2.h
new file mode 100755
index 0000000..ef4b46b
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_tim2.h
@@ -0,0 +1,902 @@
+/**
+  ******************************************************************************
+  * @file    stm8l15x_tim2.h
+  * @author  MCD Application Team
+  * @version V1.6.0
+  * @date    28-June-2013
+  * @brief   This file contains all the functions prototypes for the TIM2 firmware
+  *          library.
+  ******************************************************************************
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ****************************************************************************** 
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM8L15x_TIM2_H
+#define __STM8L15x_TIM2_H
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm8l15x.h"
+
+/** @addtogroup STM8L15x_StdPeriph_Driver
+  * @{
+  */
+  
+/** @addtogroup TIM2
+  * @{
+  */
+   
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup TIM2_Exported_Types
+  * @{
+  */
+
+/** @defgroup TIM2_Forced_Action
+  * @{
+  */
+typedef enum
+{
+  TIM2_ForcedAction_Active   = ((uint8_t)0x50),   /*!< Output Reference is forced low */
+  TIM2_ForcedAction_Inactive = ((uint8_t)0x40)    /*!< Output Reference is forced high */
+}
+TIM2_ForcedAction_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup TIM2_Prescaler
+  * @{
+  */
+typedef enum
+{
+  TIM2_Prescaler_1     = ((uint8_t)0x00),   /*!< Time base Prescaler = 1 (No effect)*/
+  TIM2_Prescaler_2     = ((uint8_t)0x01),   /*!< Time base Prescaler = 2 */
+  TIM2_Prescaler_4     = ((uint8_t)0x02),   /*!< Time base Prescaler = 4 */
+  TIM2_Prescaler_8     = ((uint8_t)0x03),   /*!< Time base Prescaler = 8 */
+  TIM2_Prescaler_16    = ((uint8_t)0x04),   /*!< Time base Prescaler = 16 */
+  TIM2_Prescaler_32    = ((uint8_t)0x05),   /*!< Time base Prescaler = 32 */
+  TIM2_Prescaler_64    = ((uint8_t)0x06),   /*!< Time base Prescaler = 64 */
+  TIM2_Prescaler_128   = ((uint8_t)0x07)    /*!< Time base Prescaler = 128 */
+}TIM2_Prescaler_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup TIM2_OCMode
+  * @{
+  */
+typedef enum
+{
+  TIM2_OCMode_Timing    = ((uint8_t)0x00),   /*!< Timing (Frozen) Mode*/
+  TIM2_OCMode_Active    = ((uint8_t)0x10),   /*!< Active Mode*/
+  TIM2_OCMode_Inactive  = ((uint8_t)0x20),   /*!< Inactive Mode*/
+  TIM2_OCMode_Toggle    = ((uint8_t)0x30),   /*!< Toggle Mode*/
+  TIM2_OCMode_PWM1      = ((uint8_t)0x60),   /*!< PWM Mode 1*/
+  TIM2_OCMode_PWM2      = ((uint8_t)0x70)    /*!< PWM Mode 2*/
+}TIM2_OCMode_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup TIM2_OnePulseMode
+  * @{
+  */
+typedef enum
+{
+  TIM2_OPMode_Single      = ((uint8_t)0x01), /*!< Single one Pulse mode (OPM Active) */
+  TIM2_OPMode_Repetitive  = ((uint8_t)0x00)  /*!< Repetitive Pulse mode (OPM inactive) */
+}TIM2_OPMode_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup TIM2_Channel
+  * @{
+  */
+typedef enum
+{
+  TIM2_Channel_1  = ((uint8_t)0x00),  /*!< Channel 1*/
+  TIM2_Channel_2  = ((uint8_t)0x01)   /*!< Channel 2*/
+}TIM2_Channel_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup TIM2_CounterMode
+  * @{
+  */
+typedef enum
+{
+  TIM2_CounterMode_Up               = ((uint8_t)0x00),   /*!< Counter Up Mode */
+  TIM2_CounterMode_Down             = ((uint8_t)0x10),   /*!< Counter Down Mode */
+  TIM2_CounterMode_CenterAligned1   = ((uint8_t)0x20),   /*!< Counter Central aligned Mode 1 */
+  TIM2_CounterMode_CenterAligned2   = ((uint8_t)0x40),   /*!< Counter Central aligned Mode 2 */
+  TIM2_CounterMode_CenterAligned3   = ((uint8_t)0x60)    /*!< Counter Central aligned Mode 3 */
+}TIM2_CounterMode_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup TIM2_Output_Compare_Polarity
+  * @{
+  */
+typedef enum
+{
+  TIM2_OCPolarity_High   = ((uint8_t)0x00),   /*!< Output compare polarity  = High */
+  TIM2_OCPolarity_Low    = ((uint8_t)0x01)    /*!< Output compare polarity  = Low */
+}TIM2_OCPolarity_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup TIM2_Output_State
+  * @{
+  */
+typedef enum
+{
+  TIM2_OutputState_Disable   = ((uint8_t)0x00),   /*!< Output compare State disabled (channel output disabled) */
+  TIM2_OutputState_Enable    = ((uint8_t)0x01)    /*!< Output compare State enabled (channel output enabled) */
+}TIM2_OutputState_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup TIM2_Break_State
+  * @{
+  */
+typedef enum
+{
+  TIM2_BreakState_Disable  = ((uint8_t)0x00),   /*!< Break State disabled (break option disabled) */
+  TIM2_BreakState_Enable   = ((uint8_t)0x10)    /*!< Break State enabled (break option enabled) */
+
+}TIM2_BreakState_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup TIM2_Break_Polarity
+  * @{
+  */
+typedef enum
+{
+  TIM2_BreakPolarity_High  = ((uint8_t)0x20),  /*!< if Break, channel polarity = High */
+  TIM2_BreakPolarity_Low   = ((uint8_t)0x00)   /*!< if Break, channel polarity = Low */
+
+}TIM2_BreakPolarity_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup TIM2_Automatic_Output
+  * @{
+  */  
+typedef enum
+{
+  TIM2_AutomaticOutput_Enable    = ((uint8_t)0x40),   /*!< Automatic Output option enabled */
+  TIM2_AutomaticOutput_Disable   = ((uint8_t)0x00)    /*!< Automatic Output option disabled */
+}TIM2_AutomaticOutput_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup TIM2_Lock_Level
+  * @{
+  */
+typedef enum
+{
+  TIM2_LockLevel_Off  = ((uint8_t)0x00),   /*!< Lock option disabled */
+  TIM2_LockLevel_1    = ((uint8_t)0x01),   /*!< Select Lock Level 1  */
+  TIM2_LockLevel_2    = ((uint8_t)0x02),   /*!< Select Lock Level 2  */
+  TIM2_LockLevel_3    = ((uint8_t)0x03)    /*!< Select Lock Level 3  */
+}TIM2_LockLevel_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup TIM2_OSSI_State
+  * @{
+  */
+typedef enum
+{
+  TIM2_OSSIState_Enable    = ((uint8_t)0x04),   /*!< Off-State Selection for Idle mode enabled  */
+  TIM2_OSSIState_Disable   = ((uint8_t)0x00)    /*!< Off-State Selection for Idle mode disabled  */
+}TIM2_OSSIState_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup TIM2_Output_Compare_Idle_state
+  * @{
+  */
+typedef enum
+{
+  TIM2_OCIdleState_Reset  = ((uint8_t)0x00),   /*!< Output Compare Idle state  = Reset */
+  TIM2_OCIdleState_Set    = ((uint8_t)0x01)    /*!< Output Compare Idle state  = Set */
+}TIM2_OCIdleState_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup TIM2_Input_Capture_Polarity
+  * @{
+  */
+typedef enum
+{
+  TIM2_ICPolarity_Rising   = ((uint8_t)0x00),   /*!< Input Capture on Rising Edge*/
+  TIM2_ICPolarity_Falling  = ((uint8_t)0x01)    /*!< Input Capture on Falling Edge*/
+}TIM2_ICPolarity_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup TIM2_Input_Capture_Selection
+  * @{
+  */
+typedef enum
+{
+  TIM2_ICSelection_DirectTI    = ((uint8_t)0x01),   /*!< Input Capture mapped on the direct input*/
+  TIM2_ICSelection_IndirectTI  = ((uint8_t)0x02),   /*!< Input Capture mapped on the indirect input*/
+  TIM2_ICSelection_TRGI        = ((uint8_t)0x03)    /*!< Input Capture mapped on the Trigger Input*/
+}TIM2_ICSelection_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup TIM2_Input_Capture_Prescaler
+  * @{
+  */
+typedef enum
+{
+  TIM2_ICPSC_DIV1  = ((uint8_t)0x00),  /*!< Input Capture Prescaler = 1 (one capture every 1 event) */
+  TIM2_ICPSC_DIV2  = ((uint8_t)0x04),  /*!< Input Capture Prescaler = 2 (one capture every 2 events) */
+  TIM2_ICPSC_DIV4  = ((uint8_t)0x08),  /*!< Input Capture Prescaler = 4 (one capture every 4 events) */
+  TIM2_ICPSC_DIV8  = ((uint8_t)0x0C)   /*!< Input Capture Prescaler = 8 (one capture every 8 events) */
+}TIM2_ICPSC_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup TIM2_Interrupts
+  * @{
+  */
+typedef enum
+{
+  TIM2_IT_Update   = ((uint8_t)0x01),   /*!< Update Interrupt*/
+  TIM2_IT_CC1      = ((uint8_t)0x02),   /*!< Capture Compare Channel1 Interrupt*/
+  TIM2_IT_CC2      = ((uint8_t)0x04),   /*!< Capture Compare Channel2 Interrupt*/
+  TIM2_IT_Trigger  = ((uint8_t)0x40),   /*!< Trigger  Interrupt*/
+  TIM2_IT_Break    = ((uint8_t)0x80)    /*!< Break Interrupt*/
+}TIM2_IT_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup TIM2_External_Trigger_Prescaler
+  * @{
+  */
+typedef enum
+{
+  TIM2_ExtTRGPSC_OFF   = ((uint8_t)0x00),   /*!< No External Trigger prescaler  */
+  TIM2_ExtTRGPSC_DIV2  = ((uint8_t)0x10),   /*!< External Trigger prescaler = 2 (ETRP frequency divided by 2) */
+  TIM2_ExtTRGPSC_DIV4  = ((uint8_t)0x20),   /*!< External Trigger prescaler = 4 (ETRP frequency divided by 4) */
+  TIM2_ExtTRGPSC_DIV8  = ((uint8_t)0x30)    /*!< External Trigger prescaler = 8 (ETRP frequency divided by 8) */
+}TIM2_ExtTRGPSC_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup TIM2_Internal_Trigger_Selection
+  * @{
+  */
+typedef enum
+{
+  TIM2_TRGSelection_TIM4     = ((uint8_t)0x00),  /*!< TRIG Input source =  TIM TRIG Output  */
+  TIM2_TRGSelection_TIM1     = ((uint8_t)0x10),  /*!< TRIG Input source =  TIM TRIG Output  */
+  TIM2_TRGSelection_TIM3     = ((uint8_t)0x20),  /*!< TRIG Input source =  TIM TRIG Output  */
+  TIM2_TRGSelection_TIM5     = ((uint8_t)0x30),  /*!< TRIG Input source =  TIM TRIG Output  */
+  TIM2_TRGSelection_TI1F_ED  = ((uint8_t)0x40),  /*!< TRIG Input source = TI1F_ED (TI1 Edge Detector)  */
+  TIM2_TRGSelection_TI1FP1   = ((uint8_t)0x50),  /*!< TRIG Input source = TI1FP1 (Filtred Timer Input 1) */
+  TIM2_TRGSelection_TI2FP2   = ((uint8_t)0x60),  /*!< TRIG Input source = TI2FP2 (Filtred Timer Input 2)  */
+  TIM2_TRGSelection_ETRF     = ((uint8_t)0x70)   /*!< TRIG Input source =  ETRF (External Trigger Input ) */
+}TIM2_TRGSelection_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup TIM2_TI_External_Clock_Source
+  * @{
+  */
+typedef enum
+{
+  TIM2_TIxExternalCLK1Source_TI1ED  = ((uint8_t)0x40),   /*!< External Clock mode 1 source = TI1ED */
+  TIM2_TIxExternalCLK1Source_TI1    = ((uint8_t)0x50),   /*!< External Clock mode 1 source = TI1 */
+  TIM2_TIxExternalCLK1Source_TI2    = ((uint8_t)0x60)    /*!< External Clock mode 1 source = TI2 */
+}TIM2_TIxExternalCLK1Source_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup TIM2_External_Trigger_Polarity
+  * @{
+  */
+typedef enum
+{
+  TIM2_ExtTRGPolarity_Inverted     = ((uint8_t)0x80),   /*!< External Trigger Polarity = inverted */
+  TIM2_ExtTRGPolarity_NonInverted  = ((uint8_t)0x00)    /*!< External Trigger Polarity = non inverted */
+}TIM2_ExtTRGPolarity_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup TIM2_Prescaler_Reload_Mode
+  * @{
+  */
+typedef enum
+{
+  TIM2_PSCReloadMode_Update      = ((uint8_t)0x00),   /*!< Prescaler value is reloaded at every update*/
+  TIM2_PSCReloadMode_Immediate   = ((uint8_t)0x01)    /*!< Prescaler value is reloaded immediatly*/
+}TIM2_PSCReloadMode_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup TIM2_Encoder_Mode
+  * @{
+  */
+typedef enum
+{
+  TIM2_EncoderMode_TI1     = ((uint8_t)0x01),   /*!< Encoder mode 1*/
+  TIM2_EncoderMode_TI2     = ((uint8_t)0x02),   /*!< Encoder mode 2*/
+  TIM2_EncoderMode_TI12    = ((uint8_t)0x03)    /*!< Encoder mode 3*/
+}TIM2_EncoderMode_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup TIM2_Event_Source
+  * @{
+  */
+typedef enum
+{
+  TIM2_EventSource_Update   = ((uint8_t)0x01),   /*!< Update Event*/
+  TIM2_EventSource_CC1      = ((uint8_t)0x02),   /*!< Capture Compare Channel1  Event*/
+  TIM2_EventSource_CC2      = ((uint8_t)0x04),   /*!< Capture Compare Channel2 Event*/
+  TIM2_EventSource_Trigger  = ((uint8_t)0x40),   /*!< Trigger Event*/
+  TIM2_EventSource_Break    = ((uint8_t)0x80)    /*!< Break Event*/
+}TIM2_EventSource_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup TIM2_Update_Source
+  * @{
+  */
+typedef enum
+{
+  TIM2_UpdateSource_Global   = ((uint8_t)0x00),   /*!< Global Update request source */
+  TIM2_UpdateSource_Regular  = ((uint8_t)0x01)    /*!< Regular Update request source */
+}TIM2_UpdateSource_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup TIM2_Trigger_Output_Source
+  * @{
+  */
+typedef enum
+{
+  TIM2_TRGOSource_Reset    = ((uint8_t)0x00),   /*!< Trigger Output source = Reset*/
+  TIM2_TRGOSource_Enable   = ((uint8_t)0x10),   /*!< Trigger Output source = TIM2 is enabled*/
+  TIM2_TRGOSource_Update   = ((uint8_t)0x20),   /*!< Trigger Output source = Update event*/
+  TIM2_TRGOSource_OC1      = ((uint8_t)0x30),   /*!< Trigger Output source = output compare channel1  */
+  TIM2_TRGOSource_OC1REF   = ((uint8_t)0x40),   /*!< Trigger Output source = output compare channel 1 reference */
+  TIM2_TRGOSource_OC2REF   = ((uint8_t)0x50)    /*!< Trigger Output source = output compare channel 2 reference */
+}TIM2_TRGOSource_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup TIM2_Slave_Mode
+  * @{
+  */
+typedef enum
+{
+  TIM2_SlaveMode_Reset      = ((uint8_t)0x04),  /*!< Slave Mode Selection  = Reset*/
+  TIM2_SlaveMode_Gated      = ((uint8_t)0x05),  /*!< Slave Mode Selection  = Gated*/
+  TIM2_SlaveMode_Trigger    = ((uint8_t)0x06),  /*!< Slave Mode Selection  = Trigger*/
+  TIM2_SlaveMode_External1  = ((uint8_t)0x07)   /*!< Slave Mode Selection  = External 1*/
+}TIM2_SlaveMode_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup TIM2_Flags
+  * @{
+  */
+typedef enum
+{
+  TIM2_FLAG_Update   = ((uint16_t)0x0001),  /*!< Update Flag */
+  TIM2_FLAG_CC1      = ((uint16_t)0x0002),  /*!< Capture compare 1 Flag */
+  TIM2_FLAG_CC2      = ((uint16_t)0x0004),  /*!< Capture compare 2 Flag */
+  TIM2_FLAG_Trigger  = ((uint16_t)0x0040),  /*!< Trigger Flag */
+  TIM2_FLAG_Break    = ((uint16_t)0x0080),  /*!< Break Flag */
+  TIM2_FLAG_CC1OF    = ((uint16_t)0x0200),  /*!< Capture compare 1 over capture Flag */
+  TIM2_FLAG_CC2OF    = ((uint16_t)0x0400)   /*!< Capture compare 2 over capture Flag */
+}TIM2_FLAG_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup TIM2_DMA_Source_Requests
+  * @{
+  */
+typedef enum
+{
+  TIM2_DMASource_Update   = ((uint8_t)0x01),  /*!< TIM2 DMA Update Request*/
+  TIM2_DMASource_CC1      = ((uint8_t)0x02),  /*!< TIM2 DMA CC1 Request*/
+  TIM2_DMASource_CC2      = ((uint8_t)0x04)   /*!< TIM2 DMA CC2 Request*/
+}TIM2_DMASource_TypeDef;
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
+
+/** @defgroup TIM2_Exported_Macros
+  * @{
+  */
+
+/**
+  * @brief Macro used by the assert function to check the different functions parameters.
+  */
+
+/**
+  * @brief Macro TIM2 Forced Action
+  */
+#define IS_TIM2_FORCED_ACTION(ACTION) \
+  (((ACTION) == TIM2_ForcedAction_Active) || \
+   ((ACTION) == TIM2_ForcedAction_Inactive))
+
+/**
+  * @brief Macro TIM2 Prescaler
+  */
+#define IS_TIM2_PRESCALER(PRESCALER) \
+  (((PRESCALER) == TIM2_Prescaler_1)  || \
+   ((PRESCALER) == TIM2_Prescaler_2)  || \
+   ((PRESCALER) == TIM2_Prescaler_4)  || \
+   ((PRESCALER) == TIM2_Prescaler_8)  || \
+   ((PRESCALER) == TIM2_Prescaler_16) || \
+   ((PRESCALER) == TIM2_Prescaler_32) || \
+   ((PRESCALER) == TIM2_Prescaler_64) || \
+   ((PRESCALER) == TIM2_Prescaler_128))
+
+/**
+  * @brief Macro TIM2 Output Compare and PWM modes
+  */
+#define IS_TIM2_OC_MODE(MODE) \
+  (((MODE) ==  TIM2_OCMode_Timing)  || \
+   ((MODE) == TIM2_OCMode_Active)   || \
+   ((MODE) == TIM2_OCMode_Inactive) || \
+   ((MODE) == TIM2_OCMode_Toggle)   || \
+   ((MODE) == TIM2_OCMode_PWM1)     || \
+   ((MODE) == TIM2_OCMode_PWM2))
+
+#define IS_TIM2_OCM(MODE) \
+  (((MODE) ==  TIM2_OCMode_Timing)  || \
+   ((MODE) == TIM2_OCMode_Active)   || \
+   ((MODE) == TIM2_OCMode_Inactive) || \
+   ((MODE) == TIM2_OCMode_Toggle)   || \
+   ((MODE) == TIM2_OCMode_PWM1)     || \
+   ((MODE) == TIM2_OCMode_PWM2)     || \
+   ((MODE) == (uint8_t)TIM2_ForcedAction_Active) || \
+   ((MODE) == (uint8_t)TIM2_ForcedAction_Inactive))
+/**
+  * @brief Macro TIM2 One Pulse Mode
+  */
+#define IS_TIM2_OPM_MODE(MODE) \
+  (((MODE) == TIM2_OPMode_Single) || \
+   ((MODE) == TIM2_OPMode_Repetitive))
+
+/**
+  * @brief Macro TIM2 Channel
+  */
+#define IS_TIM2_CHANNEL(CHANNEL) \
+  (((CHANNEL) == TIM2_Channel_1) || \
+   ((CHANNEL) == TIM2_Channel_2) )
+
+/**
+  * @brief Macro TIM2 Counter Mode
+  */
+#define IS_TIM2_COUNTER_MODE(MODE) \
+  (((MODE) == TIM2_CounterMode_Up)   || \
+   ((MODE) == TIM2_CounterMode_Down) || \
+   ((MODE) == TIM2_CounterMode_CenterAligned1) || \
+   ((MODE) == TIM2_CounterMode_CenterAligned2) || \
+   ((MODE) == TIM2_CounterMode_CenterAligned3))
+
+/**
+  * @brief Macro TIM2 Output Compare Polarity
+  */
+#define IS_TIM2_OC_POLARITY(POLARITY) \
+  (((POLARITY) == TIM2_OCPolarity_High) || \
+   ((POLARITY) == TIM2_OCPolarity_Low))
+
+/**
+  * @brief Macro TIM2 Output Compare states
+  */
+#define IS_TIM2_OUTPUT_STATE(STATE) \
+  (((STATE) == TIM2_OutputState_Disable) || \
+   ((STATE) == TIM2_OutputState_Enable))
+
+/**
+ * @brief Macro Break Input enable/disable
+ */
+#define IS_TIM2_BREAK_STATE(STATE) \
+  (((STATE) == TIM2_BreakState_Enable) || \
+   ((STATE) == TIM2_BreakState_Disable))
+
+/**
+  * @brief Macro Break Polarity
+  */
+#define IS_TIM2_BREAK_POLARITY(POLARITY) \
+  (((POLARITY) == TIM2_BreakPolarity_Low) || \
+   ((POLARITY) == TIM2_BreakPolarity_High))
+
+/**
+  * @brief Macro TIM2 AOE Bit Set/Reset
+  */
+#define IS_TIM2_AUTOMATIC_OUTPUT_STATE(STATE) \
+  (((STATE) == TIM2_AutomaticOutput_Enable) || \
+   ((STATE) == TIM2_AutomaticOutput_Disable))
+
+/**
+  * @brief Macro Lock levels
+  */
+#define IS_TIM2_LOCK_LEVEL(LEVEL) \
+  (((LEVEL) == TIM2_LockLevel_Off) || \
+   ((LEVEL) == TIM2_LockLevel_1)   || \
+   ((LEVEL) == TIM2_LockLevel_2)   || \
+   ((LEVEL) == TIM2_LockLevel_3))
+
+/**
+  * @brief Macro OSSI: Off-State Selection for Idle mode states
+  */
+#define IS_TIM2_OSSI_STATE(STATE) \
+  (((STATE) == TIM2_OSSIState_Enable) || \
+   ((STATE) == TIM2_OSSIState_Disable))
+
+/**
+  * @brief Macro TIM2 OC IDLE STATE
+  */
+#define IS_TIM2_OCIDLE_STATE(STATE) \
+  (((STATE) == TIM2_OCIdleState_Set) || \
+   ((STATE) == TIM2_OCIdleState_Reset))
+
+/**
+  * @brief Macro TIM2 IC POLARITY
+  */
+
+#define IS_TIM2_IC_POLARITY(POLARITY) \
+  (((POLARITY) == TIM2_ICPolarity_Rising) || \
+   ((POLARITY) == TIM2_ICPolarity_Falling))
+
+/**
+  * @brief Macro TIM2 IC SELECTION
+  */
+#define IS_TIM2_IC_SELECTION(SELECTION) \
+  (((SELECTION) == TIM2_ICSelection_DirectTI)   || \
+   ((SELECTION) == TIM2_ICSelection_IndirectTI) || \
+   ((SELECTION) == TIM2_ICSelection_TRGI))
+
+/**
+  * @brief Macro TIM2 IC PRESCALER
+  */
+#define IS_TIM2_IC_PRESCALER(PRESCALER) \
+  (((PRESCALER) == TIM2_ICPSC_DIV1) || \
+   ((PRESCALER) == TIM2_ICPSC_DIV2) || \
+   ((PRESCALER) == TIM2_ICPSC_DIV4) || \
+   ((PRESCALER) == TIM2_ICPSC_DIV8))
+
+/**
+  * @brief Macro TIM2 Input Capture Filter Value
+  */
+#define IS_TIM2_IC_FILTER(ICFILTER) \
+  ((ICFILTER) <= 0x0F)
+
+/**
+  * @brief Macro TIM2 Interrupts
+  */
+#define IS_TIM2_IT(IT) \
+  ((IT) != 0x00)
+
+#define IS_TIM2_GET_IT(IT) \
+  (((IT) == TIM2_IT_Update)  || \
+   ((IT) == TIM2_IT_CC1)     || \
+   ((IT) == TIM2_IT_CC2)     || \
+   ((IT) == TIM2_IT_Trigger) || \
+   ((IT) == TIM2_IT_Break))
+
+/**
+  * @brief Macro TIM2 external trigger prescaler
+  */
+#define IS_TIM2_EXT_PRESCALER(PRESCALER) \
+  (((PRESCALER) == TIM2_ExtTRGPSC_OFF)  || \
+   ((PRESCALER) == TIM2_ExtTRGPSC_DIV2) || \
+   ((PRESCALER) == TIM2_ExtTRGPSC_DIV4) || \
+   ((PRESCALER) == TIM2_ExtTRGPSC_DIV8))
+/**
+  * @brief Macro TIM2  Trigger Selection
+  */
+#define IS_TIM2_TRIGGER_SELECTION(SELECTION) \
+  (((SELECTION) == TIM2_TRGSelection_TIM4) || \
+   ((SELECTION) == TIM2_TRGSelection_TIM1) || \
+   ((SELECTION) == TIM2_TRGSelection_TIM3) || \
+   ((SELECTION) == TIM2_TRGSelection_TIM5) || \
+   ((SELECTION) == TIM2_TRGSelection_TI1F_ED) || \
+   ((SELECTION) == TIM2_TRGSelection_TI1FP1)  || \
+   ((SELECTION) == TIM2_TRGSelection_TI2FP2)  || \
+   ((SELECTION) == TIM2_TRGSelection_ETRF))
+
+
+#define IS_TIM2_TIX_TRIGGER_SELECTION(SELECTION) \
+  (((SELECTION) == TIM2_TRGSelection_TI1F_ED) || \
+   ((SELECTION) == TIM2_TRGSelection_TI1FP1)  || \
+   ((SELECTION) == TIM2_TRGSelection_TI2FP2))
+
+/**
+  * @brief Macro TIM2  TIx external Clock Selection
+  */
+#define IS_TIM2_TIXCLK_SOURCE(SOURCE)  \
+  (((SOURCE) == TIM2_TIxExternalCLK1Source_TI1ED) || \
+   ((SOURCE) == TIM2_TIxExternalCLK1Source_TI2)   || \
+   ((SOURCE) == TIM2_TIxExternalCLK1Source_TI1))
+
+/**
+  * @brief Macro TIM2  Trigger Polarity
+  */
+#define IS_TIM2_EXT_POLARITY(POLARITY) \
+  (((POLARITY) == TIM2_ExtTRGPolarity_Inverted) || \
+   ((POLARITY) == TIM2_ExtTRGPolarity_NonInverted))
+
+/**
+  * @brief Macro TIM2 External Trigger Filter
+  */
+#define IS_TIM2_EXT_FILTER(EXTFILTER) \
+  ((EXTFILTER) <= 0x0F)
+
+/**
+  * @brief Macro TIM2 Prescaler Reload
+  */
+#define IS_TIM2_PRESCALER_RELOAD(RELOAD) \
+  (((RELOAD) == TIM2_PSCReloadMode_Update) || \
+   ((RELOAD) == TIM2_PSCReloadMode_Immediate))
+
+/**
+  * @brief Macro TIM2 encoder mode
+  */
+#define IS_TIM2_ENCODER_MODE(MODE) \
+  (((MODE) == TIM2_EncoderMode_TI1) || \
+   ((MODE) == TIM2_EncoderMode_TI2) || \
+   ((MODE) == TIM2_EncoderMode_TI12))
+
+/**
+  * @brief Macro TIM2 event source
+  */
+#define IS_TIM2_EVENT_SOURCE(SOURCE) \
+  ((((SOURCE) & (uint8_t)0x18) == 0x00) && \
+   ((SOURCE) != 0x00))
+
+/**
+  * @brief Macro TIM2 update source
+  */
+#define IS_TIM2_UPDATE_SOURCE(SOURCE) \
+  (((SOURCE) == TIM2_UpdateSource_Global) || \
+   ((SOURCE) == TIM2_UpdateSource_Regular))
+
+/**
+  * @brief Macro TIM2 TRGO source
+  */
+#define IS_TIM2_TRGO_SOURCE(SOURCE) \
+  (((SOURCE) == TIM2_TRGOSource_Reset)  || \
+   ((SOURCE) == TIM2_TRGOSource_Enable) || \
+   ((SOURCE) == TIM2_TRGOSource_Update) || \
+   ((SOURCE) == TIM2_TRGOSource_OC1)    || \
+   ((SOURCE) == TIM2_TRGOSource_OC1REF) || \
+   ((SOURCE) == TIM2_TRGOSource_OC2REF))
+/**
+  * @brief Macro TIM2 Slave mode
+  */
+#define IS_TIM2_SLAVE_MODE(MODE) \
+  (((MODE) == TIM2_SlaveMode_Reset)   || \
+   ((MODE) == TIM2_SlaveMode_Gated)   || \
+   ((MODE) == TIM2_SlaveMode_Trigger) || \
+   ((MODE) == TIM2_SlaveMode_External1))
+/**
+  * @brief Macro TIM2 Flags
+  */
+#define IS_TIM2_GET_FLAG(FLAG) \
+  (((FLAG) == TIM2_FLAG_Update)  || \
+   ((FLAG) == TIM2_FLAG_CC1)     || \
+   ((FLAG) == TIM2_FLAG_CC2)     || \
+   ((FLAG) == TIM2_FLAG_Trigger) || \
+   ((FLAG) == TIM2_FLAG_Break)   || \
+   ((FLAG) == TIM2_FLAG_CC1OF)   || \
+   ((FLAG) == TIM2_FLAG_CC2OF))
+
+#define IS_TIM2_CLEAR_FLAG(FLAG) \
+  ((((FLAG) & (uint16_t)0xE100) == 0x0000) && ((FLAG) != 0x0000))
+
+/**
+  * @brief Macro TIM2 DMA sources
+  */
+
+#define IS_TIM2_DMA_SOURCE(SOURCE) \
+  (((SOURCE) == TIM2_DMASource_Update) || \
+   ((SOURCE) == TIM2_DMASource_CC1) || \
+   ((SOURCE) == TIM2_DMASource_CC2))
+
+/**
+  * @}
+  */
+
+/* Exported functions ------------------------------------------------------- */
+/* TimeBase management ********************************************************/
+void TIM2_DeInit(void);
+void TIM2_TimeBaseInit(TIM2_Prescaler_TypeDef TIM2_Prescaler,
+                       TIM2_CounterMode_TypeDef TIM2_CounterMode, uint16_t TIM2_Period);
+void TIM2_PrescalerConfig(TIM2_Prescaler_TypeDef Prescaler,
+                          TIM2_PSCReloadMode_TypeDef TIM2_PSCReloadMode);
+void TIM2_CounterModeConfig(TIM2_CounterMode_TypeDef TIM2_CounterMode);
+void TIM2_SetCounter(uint16_t Counter);
+void TIM2_SetAutoreload(uint16_t Autoreload);
+uint16_t TIM2_GetCounter(void);
+TIM2_Prescaler_TypeDef TIM2_GetPrescaler(void);
+void TIM2_UpdateDisableConfig(FunctionalState NewState);
+void TIM2_UpdateRequestConfig(TIM2_UpdateSource_TypeDef TIM2_UpdateSource);
+void TIM2_ARRPreloadConfig(FunctionalState NewState);
+void TIM2_SelectOnePulseMode(TIM2_OPMode_TypeDef TIM2_OPMode);
+void TIM2_Cmd(FunctionalState NewState);
+
+/* Output Compare management **************************************************/
+void TIM2_OC1Init(TIM2_OCMode_TypeDef TIM2_OCMode,
+                  TIM2_OutputState_TypeDef TIM2_OutputState,
+                  uint16_t TIM2_Pulse,
+                  TIM2_OCPolarity_TypeDef TIM2_OCPolarity,
+                  TIM2_OCIdleState_TypeDef TIM2_OCIdleState);
+void TIM2_OC2Init(TIM2_OCMode_TypeDef TIM2_OCMode,
+                  TIM2_OutputState_TypeDef TIM2_OutputState,
+                  uint16_t TIM2_Pulse,
+                  TIM2_OCPolarity_TypeDef TIM2_OCPolarity,
+                  TIM2_OCIdleState_TypeDef TIM2_OCIdleState);
+void TIM2_BKRConfig(TIM2_OSSIState_TypeDef TIM2_OSSIState,
+                    TIM2_LockLevel_TypeDef TIM2_LockLevel,
+                    TIM2_BreakState_TypeDef TIM2_BreakState,
+                    TIM2_BreakPolarity_TypeDef TIM2_BreakPolarity,
+                    TIM2_AutomaticOutput_TypeDef TIM2_AutomaticOutput);
+void TIM2_CtrlPWMOutputs(FunctionalState NewState);
+void TIM2_SelectOCxM(TIM2_Channel_TypeDef TIM2_Channel, TIM2_OCMode_TypeDef TIM2_OCMode);
+void TIM2_SetCompare1(uint16_t Compare);
+void TIM2_SetCompare2(uint16_t Compare);
+void TIM2_ForcedOC1Config(TIM2_ForcedAction_TypeDef TIM2_ForcedAction);
+void TIM2_ForcedOC2Config(TIM2_ForcedAction_TypeDef TIM2_ForcedAction);
+void TIM2_OC1PreloadConfig(FunctionalState NewState);
+void TIM2_OC2PreloadConfig(FunctionalState NewState);
+void TIM2_OC1FastConfig(FunctionalState NewState);
+void TIM2_OC2FastConfig(FunctionalState NewState);
+void TIM2_OC1PolarityConfig(TIM2_OCPolarity_TypeDef TIM2_OCPolarity);
+void TIM2_OC2PolarityConfig(TIM2_OCPolarity_TypeDef TIM2_OCPolarity);
+void TIM2_CCxCmd(TIM2_Channel_TypeDef TIM2_Channel, FunctionalState NewState);
+
+/* Input Capture management ***************************************************/
+void TIM2_ICInit(TIM2_Channel_TypeDef TIM2_Channel,
+                 TIM2_ICPolarity_TypeDef TIM2_ICPolarity,
+                 TIM2_ICSelection_TypeDef TIM2_ICSelection,
+                 TIM2_ICPSC_TypeDef TIM2_ICPrescaler,
+                 uint8_t TIM2_ICFilter);
+void TIM2_PWMIConfig(TIM2_Channel_TypeDef TIM2_Channel,
+                     TIM2_ICPolarity_TypeDef TIM2_ICPolarity,
+                     TIM2_ICSelection_TypeDef TIM2_ICSelection,
+                     TIM2_ICPSC_TypeDef TIM2_ICPrescaler,
+                     uint8_t TIM2_ICFilter);
+uint16_t TIM2_GetCapture1(void);
+uint16_t TIM2_GetCapture2(void);
+void TIM2_SetIC1Prescaler(TIM2_ICPSC_TypeDef TIM2_IC1Prescaler);
+void TIM2_SetIC2Prescaler(TIM2_ICPSC_TypeDef TIM2_IC2Prescaler);
+
+/* Interrupts, DMA and flags management ***************************************/
+void TIM2_ITConfig(TIM2_IT_TypeDef TIM2_IT, FunctionalState NewState);
+void TIM2_GenerateEvent(TIM2_EventSource_TypeDef TIM2_EventSource);
+FlagStatus TIM2_GetFlagStatus(TIM2_FLAG_TypeDef TIM2_FLAG);
+void TIM2_ClearFlag(TIM2_FLAG_TypeDef TIM2_FLAG);
+ITStatus TIM2_GetITStatus(TIM2_IT_TypeDef TIM2_IT);
+void TIM2_ClearITPendingBit(TIM2_IT_TypeDef TIM2_IT);
+void TIM2_DMACmd(TIM2_DMASource_TypeDef TIM2_DMASource, FunctionalState NewState);
+void TIM2_SelectCCDMA(FunctionalState NewState);
+
+/* Clocks management **********************************************************/
+void TIM2_InternalClockConfig(void);
+void TIM2_TIxExternalClockConfig(TIM2_TIxExternalCLK1Source_TypeDef TIM2_TIxExternalCLKSource,
+                                 TIM2_ICPolarity_TypeDef TIM2_ICPolarity,
+                                 uint8_t ICFilter);
+void TIM2_ETRClockMode1Config(TIM2_ExtTRGPSC_TypeDef TIM2_ExtTRGPrescaler,
+                              TIM2_ExtTRGPolarity_TypeDef TIM2_ExtTRGPolarity,
+                              uint8_t ExtTRGFilter);
+void TIM2_ETRClockMode2Config(TIM2_ExtTRGPSC_TypeDef TIM2_ExtTRGPrescaler,
+                              TIM2_ExtTRGPolarity_TypeDef TIM2_ExtTRGPolarity,
+                              uint8_t ExtTRGFilter);
+
+/* Synchronization management *************************************************/
+void TIM2_SelectInputTrigger(TIM2_TRGSelection_TypeDef TIM2_InputTriggerSource);
+void TIM2_SelectOutputTrigger(TIM2_TRGOSource_TypeDef TIM2_TRGOSource);
+void TIM2_SelectSlaveMode(TIM2_SlaveMode_TypeDef TIM2_SlaveMode);
+void TIM2_SelectMasterSlaveMode(FunctionalState NewState);
+void TIM2_ETRConfig(TIM2_ExtTRGPSC_TypeDef TIM2_ExtTRGPrescaler,
+                    TIM2_ExtTRGPolarity_TypeDef TIM2_ExtTRGPolarity,
+                    uint8_t ExtTRGFilter);
+
+/* Specific interface management **********************************************/
+void TIM2_EncoderInterfaceConfig(TIM2_EncoderMode_TypeDef TIM2_EncoderMode,
+                                 TIM2_ICPolarity_TypeDef TIM2_IC1Polarity,
+                                 TIM2_ICPolarity_TypeDef TIM2_IC2Polarity);
+void TIM2_SelectHallSensor(FunctionalState NewState);
+
+#endif /* __STM8L15x_TIM2_H */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_tim3.h b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_tim3.h
new file mode 100755
index 0000000..9c07d2b
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_tim3.h
@@ -0,0 +1,906 @@
+/**
+  ******************************************************************************
+  * @file    stm8l15x_tim3.h
+  * @author  MCD Application Team
+  * @version V1.6.0
+  * @date    28-June-2013
+  * @brief   This file contains all the functions prototypes for the TIM3 firmware
+  *          library.
+  ******************************************************************************
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ****************************************************************************** 
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM8L15x_TIM3_H
+#define __STM8L15x_TIM3_H
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm8l15x.h"
+
+/** @defgroup STM8L15x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup TIM3
+  * @{
+  */ 
+  
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup TIM3_Exported_Types
+  * @{
+  */
+
+/** @defgroup TIM3_Forced_Action
+  * @{
+  */
+typedef enum
+{
+  TIM3_ForcedAction_Active    = ((uint8_t)0x50), /*!< Output Reference is forced low */
+  TIM3_ForcedAction_Inactive  = ((uint8_t)0x40)  /*!< Output Reference is forced high */
+}
+TIM3_ForcedAction_TypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM3_Prescaler
+  * @{
+  */
+typedef enum
+{
+  TIM3_Prescaler_1     = ((uint8_t)0x00), /*!< Time base Prescaler = 1 (No effect)*/
+  TIM3_Prescaler_2     = ((uint8_t)0x01), /*!< Time base Prescaler = 2 */
+  TIM3_Prescaler_4     = ((uint8_t)0x02), /*!< Time base Prescaler = 4 */
+  TIM3_Prescaler_8     = ((uint8_t)0x03), /*!< Time base Prescaler = 8 */
+  TIM3_Prescaler_16    = ((uint8_t)0x04), /*!< Time base Prescaler = 16 */
+  TIM3_Prescaler_32    = ((uint8_t)0x05), /*!< Time base Prescaler = 32 */
+  TIM3_Prescaler_64    = ((uint8_t)0x06), /*!< Time base Prescaler = 64 */
+  TIM3_Prescaler_128   = ((uint8_t)0x07)  /*!< Time base Prescaler = 128 */
+}TIM3_Prescaler_TypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM3_OCMode
+  * @{
+  */
+typedef enum
+{
+  TIM3_OCMode_Timing    = ((uint8_t)0x00), /*!< Timing (Frozen) Mode*/
+  TIM3_OCMode_Active    = ((uint8_t)0x10), /*!< Active Mode*/
+  TIM3_OCMode_Inactive  = ((uint8_t)0x20), /*!< Inactive Mode*/
+  TIM3_OCMode_Toggle    = ((uint8_t)0x30), /*!< Toggle Mode*/
+  TIM3_OCMode_PWM1      = ((uint8_t)0x60), /*!< PWM Mode 1*/
+  TIM3_OCMode_PWM2      = ((uint8_t)0x70)  /*!< PWM Mode 2*/
+}TIM3_OCMode_TypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM3_OnePulseMode
+  * @{
+  */
+typedef enum
+{
+  TIM3_OPMode_Single      = ((uint8_t)0x01), /*!< Single one Pulse mode (OPM Active) */
+  TIM3_OPMode_Repetitive  = ((uint8_t)0x00)  /*!< Repetitive Pulse mode (OPM inactive) */
+}TIM3_OPMode_TypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM3_Channel
+  * @{
+  */
+typedef enum
+{
+  TIM3_Channel_1     = ((uint8_t)0x00),  /*!< Channel 1*/
+  TIM3_Channel_2     = ((uint8_t)0x01)   /*!< Channel 2*/
+}TIM3_Channel_TypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM3_CounterMode
+  * @{
+  */
+typedef enum
+{
+  TIM3_CounterMode_Up              = ((uint8_t)0x00), /*!< Counter Up Mode */
+  TIM3_CounterMode_Down            = ((uint8_t)0x10), /*!< Counter Down Mode */
+  TIM3_CounterMode_CenterAligned1  = ((uint8_t)0x20), /*!< Counter Central aligned Mode 1 */
+  TIM3_CounterMode_CenterAligned2  = ((uint8_t)0x40), /*!< Counter Central aligned Mode 2 */
+  TIM3_CounterMode_CenterAligned3  = ((uint8_t)0x60)  /*!< Counter Central aligned Mode 3 */
+}TIM3_CounterMode_TypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM3_Output_Compare_Polarity
+  * @{
+  */
+typedef enum
+{
+  TIM3_OCPolarity_High   = ((uint8_t)0x00), /*!< Output compare polarity  = High */
+  TIM3_OCPolarity_Low    = ((uint8_t)0x01)  /*!< Output compare polarity  = Low */
+}TIM3_OCPolarity_TypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM3_Output_State
+  * @{
+  */
+typedef enum
+{
+  TIM3_OutputState_Disable  = ((uint8_t)0x00), /*!< Output compare State disabled
+                                                          (channel output disabled) */
+  TIM3_OutputState_Enable   = ((uint8_t)0x01)  /*!< Output compare State enabled
+                                                   (channel output enabled) */
+}TIM3_OutputState_TypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM3_Break_State
+  * @{
+  */
+typedef enum
+{
+  TIM3_BreakState_Disable   = ((uint8_t)0x00), /*!< Break State disabled (break option disabled) */
+  TIM3_BreakState_Enable    = ((uint8_t)0x10)  /*!< Break State enabled (break option enabled) */
+}TIM3_BreakState_TypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM3_Break_Polarity
+  * @{
+  */
+typedef enum
+{
+  TIM3_BreakPolarity_High   = ((uint8_t)0x20),  /*!< if Break, channel polarity = High */
+  TIM3_BreakPolarity_Low    = ((uint8_t)0x00)   /*!< if Break, channel polarity = Low */
+}TIM3_BreakPolarity_TypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM3_Automatic_Output
+  * @{
+  */
+typedef enum
+{
+  TIM3_AutomaticOutput_Enable   = ((uint8_t)0x40), /*!< Automatic Output option enabled */
+  TIM3_AutomaticOutput_Disable  = ((uint8_t)0x00)  /*!< Automatic Output option disabled */
+}TIM3_AutomaticOutput_TypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM3_Lock_Level
+  * @{
+  */
+typedef enum
+{
+  TIM3_LockLevel_Off        = ((uint8_t)0x00), /*!< Lock option disabled */
+  TIM3_LockLevel_1          = ((uint8_t)0x01), /*!< Select Lock Level 1  */
+  TIM3_LockLevel_2          = ((uint8_t)0x02), /*!< Select Lock Level 2  */
+  TIM3_LockLevel_3          = ((uint8_t)0x03)  /*!< Select Lock Level 3  */
+}TIM3_LockLevel_TypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM3_OSSI_State
+  * @{
+  */
+typedef enum
+{
+  TIM3_OSSIState_Enable   = ((uint8_t)0x04), /*!< Off-State Selection for Idle mode enabled  */
+  TIM3_OSSIState_Disable  = ((uint8_t)0x00)  /*!< Off-State Selection for Idle mode disabled  */
+}TIM3_OSSIState_TypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM3_Output_Compare_Idle_state
+  * @{
+  */
+typedef enum
+{
+  TIM3_OCIdleState_Reset  = ((uint8_t)0x00), /*!< Output Compare Idle state  = Reset */
+  TIM3_OCIdleState_Set    = ((uint8_t)0x01)  /*!< Output Compare Idle state  = Set */
+}TIM3_OCIdleState_TypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM3_Input_Capture_Polarity
+  * @{
+  */
+typedef enum
+{
+  TIM3_ICPolarity_Rising  = ((uint8_t)0x00), /*!< Input Capture on Rising Edge*/
+  TIM3_ICPolarity_Falling  = ((uint8_t)0x01)  /*!< Input Capture on Falling Edge*/
+}TIM3_ICPolarity_TypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM3_Input_Capture_Selection
+  * @{
+  */
+typedef enum
+{
+  TIM3_ICSelection_DirectTI    = ((uint8_t)0x01), /*!< Input Capture mapped on the direct input*/
+  TIM3_ICSelection_IndirectTI  = ((uint8_t)0x02), /*!< Input Capture mapped on the indirect input*/
+  TIM3_ICSelection_TRGI        = ((uint8_t)0x03)  /*!< Input Capture mapped on the Trigger Input*/
+}TIM3_ICSelection_TypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM3_Input_Capture_Prescaler
+  * @{
+  */
+typedef enum
+{
+  TIM3_ICPSC_DIV1  = ((uint8_t)0x00),  /*!< Input Capture Prescaler = 1 (one capture every 1 event) */
+  TIM3_ICPSC_DIV2  = ((uint8_t)0x04),  /*!< Input Capture Prescaler = 2 (one capture every 2 events) */
+  TIM3_ICPSC_DIV4  = ((uint8_t)0x08),  /*!< Input Capture Prescaler = 4 (one capture every 4 events) */
+  TIM3_ICPSC_DIV8  = ((uint8_t)0x0C)   /*!< Input Capture Prescaler = 8 (one capture every 8 events) */
+}TIM3_ICPSC_TypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM3_Interrupts
+  * @{
+  */
+typedef enum
+{
+  TIM3_IT_Update   = ((uint8_t)0x01), /*!< Update Interrupt*/
+  TIM3_IT_CC1      = ((uint8_t)0x02), /*!< Capture Compare Channel1 Interrupt*/
+  TIM3_IT_CC2      = ((uint8_t)0x04), /*!< Capture Compare Channel2 Interrupt*/
+  TIM3_IT_Trigger  = ((uint8_t)0x40), /*!< Trigger  Interrupt*/
+  TIM3_IT_Break    = ((uint8_t)0x80)  /*!< Break Interrupt*/
+}TIM3_IT_TypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM3_External_Trigger_Prescaler
+  * @{
+  */
+typedef enum
+{
+  TIM3_ExtTRGPSC_OFF   = ((uint8_t)0x00), /*!< No External Trigger prescaler  */
+  TIM3_ExtTRGPSC_DIV2  = ((uint8_t)0x10), /*!< External Trigger prescaler = 2 (ETRP frequency divided by 2) */
+  TIM3_ExtTRGPSC_DIV4  = ((uint8_t)0x20), /*!< External Trigger prescaler = 4 (ETRP frequency divided by 4) */
+  TIM3_ExtTRGPSC_DIV8  = ((uint8_t)0x30)  /*!< External Trigger prescaler = 8 (ETRP frequency divided by 8) */
+}TIM3_ExtTRGPSC_TypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM3_Internal_Trigger_Selection
+  * @{
+  */
+typedef enum
+{
+  TIM3_TRGSelection_TIM4     = ((uint8_t)0x00), /*!< TRIG Input source =  TIM TRIG Output  */
+  TIM3_TRGSelection_TIM1     = ((uint8_t)0x10), /*!< TRIG Input source =  TIM TRIG Output  */
+  TIM3_TRGSelection_TIM5     = ((uint8_t)0x20), /*!< TRIG Input source =  TIM TRIG Output  */
+  TIM3_TRGSelection_TIM2     = ((uint8_t)0x30), /*!< TRIG Input source =  TIM TRIG Output  */
+  TIM3_TRGSelection_TI1F_ED  = ((uint8_t)0x40), /*!< TRIG Input source = TI1F_ED (TI1 Edge Detector)  */
+  TIM3_TRGSelection_TI1FP1   = ((uint8_t)0x50), /*!< TRIG Input source = TI1FP1  (Filtred Timer Input 1) */
+  TIM3_TRGSelection_TI2FP2   = ((uint8_t)0x60), /*!< TRIG Input source = TI2FP2 (Filtred Timer Input 2)  */
+  TIM3_TRGSelection_ETRF     = ((uint8_t)0x70)  /*!< TRIG Input source =  ETRF (External Trigger Input ) */
+}TIM3_TRGSelection_TypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM3_TI_External_Clock_Source
+  * @{
+  */
+typedef enum
+{
+  TIM3_TIxExternalCLK1Source_TI1ED  = ((uint8_t)0x40),  /*!< External Clock mode 1 source = TI1ED */
+  TIM3_TIxExternalCLK1Source_TI1    = ((uint8_t)0x50),  /*!< External Clock mode 1 source = TI1 */
+  TIM3_TIxExternalCLK1Source_TI2    = ((uint8_t)0x60)   /*!< External Clock mode 1 source = TI2 */
+}TIM3_TIxExternalCLK1Source_TypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM3_External_Trigger_Polarity
+  * @{
+  */
+typedef enum
+{
+  TIM3_ExtTRGPolarity_Inverted     = ((uint8_t)0x80), /*!< External Trigger Polarity = inverted */
+  TIM3_ExtTRGPolarity_NonInverted  = ((uint8_t)0x00)  /*!< External Trigger Polarity = non inverted */
+}TIM3_ExtTRGPolarity_TypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM3_Prescaler_Reload_Mode
+  * @{
+  */
+typedef enum
+{
+  TIM3_PSCReloadMode_Update     = ((uint8_t)0x00), /*!< Prescaler value is reloaded at every update*/
+  TIM3_PSCReloadMode_Immediate  = ((uint8_t)0x01)  /*!< Prescaler value is reloaded immediatly*/
+}TIM3_PSCReloadMode_TypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM3_Encoder_Mode
+  * @{
+  */
+typedef enum
+{
+  TIM3_EncoderMode_TI1    = ((uint8_t)0x01), /*!< Encoder mode 1*/
+  TIM3_EncoderMode_TI2    = ((uint8_t)0x02), /*!< Encoder mode 2*/
+  TIM3_EncoderMode_TI12   = ((uint8_t)0x03)  /*!< Encoder mode 3*/
+}TIM3_EncoderMode_TypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM3_Event_Source
+  * @{
+  */
+typedef enum
+{
+  TIM3_EventSource_Update   = ((uint8_t)0x01), /*!< Update Event*/
+  TIM3_EventSource_CC1      = ((uint8_t)0x02), /*!< Capture Compare Channel1  Event*/
+  TIM3_EventSource_CC2      = ((uint8_t)0x04), /*!< Capture Compare Channel2 Event*/
+  TIM3_EventSource_Trigger  = ((uint8_t)0x40), /*!< Trigger Event*/
+  TIM3_EventSource_Break    = ((uint8_t)0x80)  /*!< Break Event*/
+}TIM3_EventSource_TypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM3_Update_Source
+  * @{
+  */
+typedef enum
+{
+  TIM3_UpdateSource_Global  = ((uint8_t)0x00), /*!< Global Update request source */
+  TIM3_UpdateSource_Regular = ((uint8_t)0x01)  /*!< Regular Update request source */
+}TIM3_UpdateSource_TypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM3_Trigger_Output_Source
+  * @{
+  */
+typedef enum
+{
+  TIM3_TRGOSource_Reset   = ((uint8_t)0x00), /*!< Trigger Output source = Reset*/
+  TIM3_TRGOSource_Enable  = ((uint8_t)0x10), /*!< Trigger Output source = TIM3 is enabled*/
+  TIM3_TRGOSource_Update  = ((uint8_t)0x20), /*!< Trigger Output source = Update event*/
+  TIM3_TRGOSource_OC1     = ((uint8_t)0x30), /*!< Trigger Output source = output compare channel1  */
+  TIM3_TRGOSource_OC1REF  = ((uint8_t)0x40), /*!< Trigger Output source = output compare channel 1 reference */
+  TIM3_TRGOSource_OC2REF  = ((uint8_t)0x50)  /*!< Trigger Output source = output compare channel 2 reference */
+}TIM3_TRGOSource_TypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM3_Slave_Mode
+  * @{
+  */
+typedef enum
+{
+  TIM3_SlaveMode_Reset      = ((uint8_t)0x04), /*!< Slave Mode Selection  = Reset*/
+  TIM3_SlaveMode_Gated      = ((uint8_t)0x05), /*!< Slave Mode Selection  = Gated*/
+  TIM3_SlaveMode_Trigger    = ((uint8_t)0x06), /*!< Slave Mode Selection  = Trigger*/
+  TIM3_SlaveMode_External1  = ((uint8_t)0x07)  /*!< Slave Mode Selection  = External 1*/
+}TIM3_SlaveMode_TypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM3_Flags
+  * @{
+  */
+typedef enum
+{
+  TIM3_FLAG_Update   = ((uint16_t)0x0001), /*!< Update Flag */
+  TIM3_FLAG_CC1      = ((uint16_t)0x0002), /*!< Capture compare 1 Flag */
+  TIM3_FLAG_CC2      = ((uint16_t)0x0004), /*!< Capture compare 2 Flag */
+  TIM3_FLAG_Trigger  = ((uint16_t)0x0040), /*!< Trigger Flag */
+  TIM3_FLAG_Break    = ((uint16_t)0x0080), /*!< Break Flag */
+  TIM3_FLAG_CC1OF    = ((uint16_t)0x0200), /*!< Capture compare 1 over capture Flag */
+  TIM3_FLAG_CC2OF    = ((uint16_t)0x0400)  /*!< Capture compare 2 over capture Flag */
+}TIM3_FLAG_TypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM3_DMA_Source_Requests
+  * @{
+  */
+typedef enum
+{
+  TIM3_DMASource_Update   = ((uint8_t)0x01),  /*!< TIM3 DMA Update Request*/
+  TIM3_DMASource_CC1      = ((uint8_t)0x02),
+  TIM3_DMASource_CC2      = ((uint8_t)0x04)
+}TIM3_DMASource_TypeDef;
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
+
+/** @defgroup TIM3_Exported_Macros
+  * @{
+  */
+
+/**
+  * @brief Macro used by the assert function to check the different functions parameters.
+  */
+
+/**
+  * @brief Macro TIM3 Forced Action
+  */
+#define IS_TIM3_FORCED_ACTION(ACTION) \
+  (((ACTION) == TIM3_ForcedAction_Active) || \
+   ((ACTION) == TIM3_ForcedAction_Inactive))
+
+/**
+  * @brief Macro TIM3 Prescaler
+  */
+#define IS_TIM3_PRESCALER(PRESCALER) \
+  (((PRESCALER) == TIM3_Prescaler_1)  || \
+   ((PRESCALER) == TIM3_Prescaler_2)  || \
+   ((PRESCALER) == TIM3_Prescaler_4)  || \
+   ((PRESCALER) == TIM3_Prescaler_8)  || \
+   ((PRESCALER) == TIM3_Prescaler_16) || \
+   ((PRESCALER) == TIM3_Prescaler_32) || \
+   ((PRESCALER) == TIM3_Prescaler_64) || \
+   ((PRESCALER) == TIM3_Prescaler_128))
+
+/**
+  * @brief Macro TIM3 Output Compare and PWM modes
+  */
+#define IS_TIM3_OC_MODE(MODE) \
+  (((MODE) ==  TIM3_OCMode_Timing)  || \
+   ((MODE) == TIM3_OCMode_Active)   || \
+   ((MODE) == TIM3_OCMode_Inactive) || \
+   ((MODE) == TIM3_OCMode_Toggle)   || \
+   ((MODE) == TIM3_OCMode_PWM1)     || \
+   ((MODE) == TIM3_OCMode_PWM2))
+
+#define IS_TIM3_OCM(MODE)   \
+  (((MODE) ==  TIM3_OCMode_Timing)  || \
+   ((MODE) == TIM3_OCMode_Active)   || \
+   ((MODE) == TIM3_OCMode_Inactive) || \
+   ((MODE) == TIM3_OCMode_Toggle)   || \
+   ((MODE) == TIM3_OCMode_PWM1)     || \
+   ((MODE) == TIM3_OCMode_PWM2)     || \
+   ((MODE) == (uint8_t)TIM3_ForcedAction_Active) || \
+   ((MODE) == (uint8_t)TIM3_ForcedAction_Inactive))
+/**
+  * @brief Macro TIM3 One Pulse Mode
+  */
+#define IS_TIM3_OPM_MODE(MODE) \
+  (((MODE) == TIM3_OPMode_Single) || \
+   ((MODE) == TIM3_OPMode_Repetitive))
+
+/**
+  * @brief Macro TIM3 Channel
+  */
+#define IS_TIM3_CHANNEL(CHANNEL) \
+  (((CHANNEL) == TIM3_Channel_1) || \
+   ((CHANNEL) == TIM3_Channel_2) )
+
+/**
+  * @brief Macro TIM3 Counter Mode
+  */
+#define IS_TIM3_COUNTER_MODE(MODE) \
+  (((MODE) == TIM3_CounterMode_Up)   || \
+   ((MODE) == TIM3_CounterMode_Down) || \
+   ((MODE) == TIM3_CounterMode_CenterAligned1) || \
+   ((MODE) == TIM3_CounterMode_CenterAligned2) || \
+   ((MODE) == TIM3_CounterMode_CenterAligned3))
+
+/**
+  * @brief Macro TIM3 Output Compare Polarity
+  */
+#define IS_TIM3_OC_POLARITY(POLARITY) \
+  (((POLARITY) == TIM3_OCPolarity_High) || \
+   ((POLARITY) == TIM3_OCPolarity_Low))
+
+/**
+  * @brief Macro TIM3 Output Compare states
+  */
+#define IS_TIM3_OUTPUT_STATE(STATE) \
+  (((STATE) == TIM3_OutputState_Disable) || \
+   ((STATE) == TIM3_OutputState_Enable))
+
+
+/**
+  * @brief Macro Break Input enable/disable
+  */
+#define IS_TIM3_BREAK_STATE(STATE) \
+  (((STATE) == TIM3_BreakState_Enable) || \
+   ((STATE) == TIM3_BreakState_Disable))
+
+/**
+  * @brief Macro Break Polarity
+  */
+#define IS_TIM3_BREAK_POLARITY(POLARITY) \
+  (((POLARITY) == TIM3_BreakPolarity_Low) || \
+   ((POLARITY) == TIM3_BreakPolarity_High))
+
+/**
+  * @brief Macro TIM3 AOE Bit Set/Reset
+  */
+#define IS_TIM3_AUTOMATIC_OUTPUT_STATE(STATE) \
+  (((STATE) == TIM3_AutomaticOutput_Enable) || \
+   ((STATE) == TIM3_AutomaticOutput_Disable))
+
+/**
+  * @brief Macro Lock levels
+  */
+#define IS_TIM3_LOCK_LEVEL(LEVEL) \
+  (((LEVEL) == TIM3_LockLevel_Off) || \
+   ((LEVEL) == TIM3_LockLevel_1)   || \
+   ((LEVEL) == TIM3_LockLevel_2)   || \
+   ((LEVEL) == TIM3_LockLevel_3))
+
+/**
+  * @brief Macro OSSI: Off-State Selection for Idle mode states
+  */
+#define IS_TIM3_OSSI_STATE(STATE) \
+  (((STATE) == TIM3_OSSIState_Enable) || \
+   ((STATE) == TIM3_OSSIState_Disable))
+
+/**
+  * @brief Macro TIM3 OC IDLE STATE
+  */
+#define IS_TIM3_OCIDLE_STATE(STATE) \
+  (((STATE) == TIM3_OCIdleState_Set) || \
+   ((STATE) == TIM3_OCIdleState_Reset))
+
+/**
+  * @brief Macro TIM3 IC POLARITY
+  */
+
+#define IS_TIM3_IC_POLARITY(POLARITY) \
+  (((POLARITY) == TIM3_ICPolarity_Rising) || \
+   ((POLARITY) == TIM3_ICPolarity_Falling))
+
+/**
+  * @brief Macro TIM3 IC SELECTION
+  */
+#define IS_TIM3_IC_SELECTION(SELECTION) \
+  (((SELECTION) == TIM3_ICSelection_DirectTI)   || \
+   ((SELECTION) == TIM3_ICSelection_IndirectTI) || \
+   ((SELECTION) == TIM3_ICSelection_TRGI))
+
+
+/**
+  * @brief Macro TIM3 IC PRESCALER
+  */
+#define IS_TIM3_IC_PRESCALER(PRESCALER) \
+  (((PRESCALER) == TIM3_ICPSC_DIV1) || \
+   ((PRESCALER) == TIM3_ICPSC_DIV2) || \
+   ((PRESCALER) == TIM3_ICPSC_DIV4) || \
+   ((PRESCALER) == TIM3_ICPSC_DIV8))
+
+/**
+  * @brief Macro TIM3 Input Capture Filter Value
+  */
+#define IS_TIM3_IC_FILTER(ICFILTER) \
+  ((ICFILTER) <= 0x0F)
+
+/**
+  * @brief Macro TIM3 Interrupts
+  */
+#define IS_TIM3_IT(IT) \
+  ((IT) != 0x00)
+
+#define IS_TIM3_GET_IT(IT) \
+  (((IT) == TIM3_IT_Update)  || \
+   ((IT) == TIM3_IT_CC1)     || \
+   ((IT) == TIM3_IT_CC2)     || \
+   ((IT) == TIM3_IT_Trigger) || \
+   ((IT) == TIM3_IT_Break))
+
+/**
+  * @brief Macro TIM3 external trigger prescaler
+  */
+#define IS_TIM3_EXT_PRESCALER(PRESCALER) \
+  (((PRESCALER) == TIM3_ExtTRGPSC_OFF)  || \
+   ((PRESCALER) == TIM3_ExtTRGPSC_DIV2) || \
+   ((PRESCALER) == TIM3_ExtTRGPSC_DIV4) || \
+   ((PRESCALER) == TIM3_ExtTRGPSC_DIV8))
+
+/**
+  * @brief Macro TIM3  Trigger Selection
+  */
+#define IS_TIM3_TRIGGER_SELECTION(SELECTION) \
+  (((SELECTION) == TIM3_TRGSelection_TI1F_ED) || \
+   ((SELECTION) == TIM3_TRGSelection_TI1FP1)  || \
+   ((SELECTION) == TIM3_TRGSelection_TI2FP2)  || \
+   ((SELECTION) == TIM3_TRGSelection_TIM4) || \
+   ((SELECTION) == TIM3_TRGSelection_TIM1) || \
+   ((SELECTION) == TIM3_TRGSelection_TIM5) || \
+   ((SELECTION) == TIM3_TRGSelection_TIM2) || \
+   ((SELECTION) == TIM3_TRGSelection_ETRF))
+
+
+#define IS_TIM3_TIX_TRIGGER_SELECTION(SELECTION) \
+  (((SELECTION) == TIM3_TRGSelection_TI1F_ED) || \
+   ((SELECTION) == TIM3_TRGSelection_TI1FP1)  || \
+   ((SELECTION) == TIM3_TRGSelection_TI2FP2))
+
+/**
+  * @brief Macro TIM3  TIx external Clock Selection
+  */
+#define IS_TIM3_TIXCLK_SOURCE(SOURCE)  \
+  (((SOURCE) == TIM3_TIxExternalCLK1Source_TI1ED) || \
+   ((SOURCE) == TIM3_TIxExternalCLK1Source_TI2)   || \
+   ((SOURCE) == TIM3_TIxExternalCLK1Source_TI1))
+
+/**
+  * @brief Macro TIM3  Trigger Polarity
+  */
+#define IS_TIM3_EXT_POLARITY(POLARITY) \
+  (((POLARITY) == TIM3_ExtTRGPolarity_Inverted) || \
+   ((POLARITY) == TIM3_ExtTRGPolarity_NonInverted))
+
+/**
+  * @brief Macro TIM3 External Trigger Filter
+  */
+#define IS_TIM3_EXT_FILTER(EXTFILTER) \
+  ((EXTFILTER) <= 0x0F)
+
+/**
+  * @brief Macro TIM3 Prescaler Reload
+  */
+#define IS_TIM3_PRESCALER_RELOAD(RELOAD) \
+  (((RELOAD) == TIM3_PSCReloadMode_Update) || \
+   ((RELOAD) == TIM3_PSCReloadMode_Immediate))
+
+/**
+  * @brief Macro TIM3 encoder mode
+  */
+#define IS_TIM3_ENCODER_MODE(MODE) \
+  (((MODE) == TIM3_EncoderMode_TI1) || \
+   ((MODE) == TIM3_EncoderMode_TI2) || \
+   ((MODE) == TIM3_EncoderMode_TI12))
+
+/**
+  * @brief Macro TIM3 event source
+  */
+#define IS_TIM3_EVENT_SOURCE(SOURCE) \
+  ((((SOURCE) & (uint8_t)0x18) == 0x00) && ((SOURCE) != 0x00))
+
+/**
+  * @brief Macro TIM3 update source
+  */
+#define IS_TIM3_UPDATE_SOURCE(SOURCE) \
+  (((SOURCE) == TIM3_UpdateSource_Global) || \
+   ((SOURCE) == TIM3_UpdateSource_Regular))
+
+/**
+  * @brief Macro TIM3 TRGO source
+  */
+#define IS_TIM3_TRGO_SOURCE(SOURCE) \
+  (((SOURCE) == TIM3_TRGOSource_Reset)  || \
+   ((SOURCE) == TIM3_TRGOSource_Enable) || \
+   ((SOURCE) == TIM3_TRGOSource_Update) || \
+   ((SOURCE) == TIM3_TRGOSource_OC1)    || \
+   ((SOURCE) == TIM3_TRGOSource_OC1REF) || \
+   ((SOURCE) == TIM3_TRGOSource_OC2REF))
+/**
+  * @brief Macro TIM3 Slave mode
+  */
+#define IS_TIM3_SLAVE_MODE(MODE) \
+  (((MODE) == TIM3_SlaveMode_Reset)   || \
+   ((MODE) == TIM3_SlaveMode_Gated)   || \
+   ((MODE) == TIM3_SlaveMode_Trigger) || \
+   ((MODE) == TIM3_SlaveMode_External1))
+/**
+  * @brief Macro TIM3 Flags
+  */
+#define IS_TIM3_GET_FLAG(FLAG) \
+  (((FLAG) == TIM3_FLAG_Update)  || \
+   ((FLAG) == TIM3_FLAG_CC1)     || \
+   ((FLAG) == TIM3_FLAG_CC2)     || \
+   ((FLAG) == TIM3_FLAG_Trigger) || \
+   ((FLAG) == TIM3_FLAG_Break)   || \
+   ((FLAG) == TIM3_FLAG_CC1OF)   || \
+   ((FLAG) == TIM3_FLAG_CC2OF))
+
+#define IS_TIM3_CLEAR_FLAG(FLAG) \
+  ((((FLAG) & (uint16_t)0xE100) == 0x0000) && ((FLAG) != 0x0000))
+
+/**
+  * @brief Macro TIM3 DMA sources
+  */
+
+#define IS_TIM3_DMA_SOURCE(SOURCE) \
+  (((SOURCE) == TIM3_DMASource_Update) || \
+   ((SOURCE) == TIM3_DMASource_CC1) || \
+   ((SOURCE) == TIM3_DMASource_CC2))
+
+/**
+  * @}
+  */
+
+/* Exported functions ------------------------------------------------------- */
+/* TimeBase management ********************************************************/
+void TIM3_DeInit(void);
+void TIM3_TimeBaseInit(TIM3_Prescaler_TypeDef TIM3_Prescaler,
+                       TIM3_CounterMode_TypeDef TIM3_CounterMode,
+                       uint16_t TIM3_Period);
+void TIM3_PrescalerConfig(TIM3_Prescaler_TypeDef Prescaler,
+                          TIM3_PSCReloadMode_TypeDef TIM3_PSCReloadMode);
+void TIM3_CounterModeConfig(TIM3_CounterMode_TypeDef TIM3_CounterMode);
+void TIM3_SetCounter(uint16_t Counter);
+void TIM3_SetAutoreload(uint16_t Autoreload);
+uint16_t TIM3_GetCounter(void);
+TIM3_Prescaler_TypeDef TIM3_GetPrescaler(void);
+void TIM3_UpdateDisableConfig(FunctionalState NewState);
+void TIM3_UpdateRequestConfig(TIM3_UpdateSource_TypeDef TIM3_UpdateSource);
+void TIM3_ARRPreloadConfig(FunctionalState NewState);
+void TIM3_SelectOnePulseMode(TIM3_OPMode_TypeDef TIM3_OPMode);
+void TIM3_Cmd(FunctionalState NewState);
+
+/* Output Compare management **************************************************/
+void TIM3_OC1Init(TIM3_OCMode_TypeDef TIM3_OCMode,
+                  TIM3_OutputState_TypeDef TIM3_OutputState,
+                  uint16_t TIM3_Pulse,
+                  TIM3_OCPolarity_TypeDef TIM3_OCPolarity,
+                  TIM3_OCIdleState_TypeDef TIM3_OCIdleState);
+void TIM3_OC2Init(TIM3_OCMode_TypeDef TIM3_OCMode,
+                  TIM3_OutputState_TypeDef TIM3_OutputState,
+                  uint16_t TIM3_Pulse,
+                  TIM3_OCPolarity_TypeDef TIM3_OCPolarity,
+                  TIM3_OCIdleState_TypeDef TIM3_OCIdleState);
+void TIM3_BKRConfig(TIM3_OSSIState_TypeDef TIM3_OSSIState,
+                    TIM3_LockLevel_TypeDef TIM3_LockLevel,
+                    TIM3_BreakState_TypeDef TIM3_BreakState,
+                    TIM3_BreakPolarity_TypeDef TIM3_BreakPolarity,
+                    TIM3_AutomaticOutput_TypeDef TIM3_AutomaticOutput);
+void TIM3_CtrlPWMOutputs(FunctionalState NewState);
+void TIM3_SelectOCxM(TIM3_Channel_TypeDef TIM3_Channel,
+                     TIM3_OCMode_TypeDef TIM3_OCMode);
+void TIM3_SetCompare1(uint16_t Compare);
+void TIM3_SetCompare2(uint16_t Compare);
+void TIM3_ForcedOC1Config(TIM3_ForcedAction_TypeDef TIM3_ForcedAction);
+void TIM3_ForcedOC2Config(TIM3_ForcedAction_TypeDef TIM3_ForcedAction);
+void TIM3_OC1PreloadConfig(FunctionalState NewState);
+void TIM3_OC2PreloadConfig(FunctionalState NewState);
+void TIM3_OC1FastConfig(FunctionalState NewState);
+void TIM3_OC2FastConfig(FunctionalState NewState);
+void TIM3_OC1PolarityConfig(TIM3_OCPolarity_TypeDef TIM3_OCPolarity);
+void TIM3_OC2PolarityConfig(TIM3_OCPolarity_TypeDef TIM3_OCPolarity);
+void TIM3_CCxCmd(TIM3_Channel_TypeDef TIM3_Channel, FunctionalState NewState);
+
+/* Input Capture management ***************************************************/
+void TIM3_ICInit(TIM3_Channel_TypeDef TIM3_Channel,
+                 TIM3_ICPolarity_TypeDef TIM3_ICPolarity,
+                 TIM3_ICSelection_TypeDef TIM3_ICSelection,
+                 TIM3_ICPSC_TypeDef TIM3_ICPrescaler,
+                 uint8_t TIM3_ICFilter);
+void TIM3_PWMIConfig(TIM3_Channel_TypeDef TIM3_Channel,
+                     TIM3_ICPolarity_TypeDef TIM3_ICPolarity,
+                     TIM3_ICSelection_TypeDef TIM3_ICSelection,
+                     TIM3_ICPSC_TypeDef TIM3_ICPrescaler,
+                     uint8_t TIM3_ICFilter);
+uint16_t TIM3_GetCapture1(void);
+uint16_t TIM3_GetCapture2(void);
+void TIM3_SetIC1Prescaler(TIM3_ICPSC_TypeDef TIM3_IC1Prescaler);
+void TIM3_SetIC2Prescaler(TIM3_ICPSC_TypeDef TIM3_IC2Prescaler);
+
+/* Interrupts, DMA and flags management ***************************************/
+void TIM3_ITConfig(TIM3_IT_TypeDef TIM3_IT, FunctionalState NewState);
+void TIM3_GenerateEvent(TIM3_EventSource_TypeDef TIM3_EventSource);
+FlagStatus TIM3_GetFlagStatus(TIM3_FLAG_TypeDef TIM3_FLAG);
+void TIM3_ClearFlag(TIM3_FLAG_TypeDef TIM3_FLAG);
+ITStatus TIM3_GetITStatus(TIM3_IT_TypeDef TIM3_IT);
+void TIM3_ClearITPendingBit(TIM3_IT_TypeDef TIM3_IT);
+void TIM3_DMACmd(TIM3_DMASource_TypeDef TIM3_DMASource, FunctionalState NewState);
+void TIM3_SelectCCDMA(FunctionalState NewState);
+
+/* Clocks management **********************************************************/
+void TIM3_InternalClockConfig(void);
+void TIM3_TIxExternalClockConfig(TIM3_TIxExternalCLK1Source_TypeDef TIM3_TIxExternalCLKSource,
+                                 TIM3_ICPolarity_TypeDef TIM3_ICPolarity,
+                                 uint8_t ICFilter);
+void TIM3_ETRClockMode1Config(TIM3_ExtTRGPSC_TypeDef TIM3_ExtTRGPrescaler,
+                              TIM3_ExtTRGPolarity_TypeDef TIM3_ExtTRGPolarity,
+                              uint8_t ExtTRGFilter);
+void TIM3_ETRClockMode2Config(TIM3_ExtTRGPSC_TypeDef TIM3_ExtTRGPrescaler,
+                              TIM3_ExtTRGPolarity_TypeDef TIM3_ExtTRGPolarity,
+                              uint8_t ExtTRGFilter);
+
+/* Synchronization management *************************************************/
+void TIM3_SelectInputTrigger(TIM3_TRGSelection_TypeDef TIM3_InputTriggerSource);
+void TIM3_SelectOutputTrigger(TIM3_TRGOSource_TypeDef TIM3_TRGOSource);
+void TIM3_SelectSlaveMode(TIM3_SlaveMode_TypeDef TIM3_SlaveMode);
+void TIM3_SelectMasterSlaveMode(FunctionalState NewState);
+void TIM3_ETRConfig(TIM3_ExtTRGPSC_TypeDef TIM3_ExtTRGPrescaler,
+                    TIM3_ExtTRGPolarity_TypeDef TIM3_ExtTRGPolarity,
+                    uint8_t ExtTRGFilter);
+
+/* Specific interface management **********************************************/
+void TIM3_EncoderInterfaceConfig(TIM3_EncoderMode_TypeDef TIM3_EncoderMode,
+                                 TIM3_ICPolarity_TypeDef TIM3_IC1Polarity,
+                                 TIM3_ICPolarity_TypeDef TIM3_IC2Polarity);
+void TIM3_SelectHallSensor(FunctionalState NewState);
+
+#endif /* __STM8L15x_TIM3_H */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_tim4.h b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_tim4.h
new file mode 100755
index 0000000..71f3e5b
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_tim4.h
@@ -0,0 +1,371 @@
+/**
+  ******************************************************************************
+  * @file    stm8l15x_tim4.h
+  * @author  MCD Application Team
+  * @version V1.6.0
+  * @date    28-June-2013
+  * @brief   This file contains all the functions prototypes for the TIM4 firmware
+  *          library.
+  ******************************************************************************
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ****************************************************************************** 
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM8L15x_TIM4_H
+#define __STM8L15x_TIM4_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm8l15x.h"
+
+/** @addtogroup STM8L15x_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup TIM4
+  * @{
+  */ 
+  
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup TIM4_Exported_Types
+  * @{
+  */
+
+
+/** @defgroup TIM4_Prescaler
+  * @{
+  */
+typedef enum
+{
+  TIM4_Prescaler_1      = ((uint8_t)0x00),   /*!< Time base Prescaler = 1 (No effect)*/
+  TIM4_Prescaler_2      = ((uint8_t)0x01),  /*!< Time base Prescaler = 2 */
+  TIM4_Prescaler_4      = ((uint8_t)0x02),  /*!< Time base Prescaler = 4 */
+  TIM4_Prescaler_8      = ((uint8_t)0x03),  /*!< Time base Prescaler = 8 */
+  TIM4_Prescaler_16     = ((uint8_t)0x04),  /*!< Time base Prescaler = 16 */
+  TIM4_Prescaler_32     = ((uint8_t)0x05),  /*!< Time base Prescaler = 32 */
+  TIM4_Prescaler_64     = ((uint8_t)0x06),  /*!< Time base Prescaler = 64 */
+  TIM4_Prescaler_128    = ((uint8_t)0x07),  /*!< Time base Prescaler = 128 */
+  TIM4_Prescaler_256    = ((uint8_t)0x08),  /*!< Time base Prescaler = 256 */
+  TIM4_Prescaler_512    = ((uint8_t)0x09),  /*!< Time base Prescaler = 512 */
+  TIM4_Prescaler_1024   = ((uint8_t)0x0A),  /*!< Time base Prescaler = 1024 */
+  TIM4_Prescaler_2048   = ((uint8_t)0x0B),  /*!< Time base Prescaler = 2048 */
+  TIM4_Prescaler_4096   = ((uint8_t)0x0C),  /*!< Time base Prescaler = 4096 */
+  TIM4_Prescaler_8192   = ((uint8_t)0x0D),  /*!< Time base Prescaler = 8196 */
+  TIM4_Prescaler_16384  = ((uint8_t)0x0E),  /*!< Time base Prescaler = 16384 */
+  TIM4_Prescaler_32768  = ((uint8_t)0x0F)   /*!< Time base Prescaler = 32768 */
+}TIM4_Prescaler_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup TIM4_One_Pulse_Mode
+  * @{
+  */
+typedef enum
+{
+  TIM4_OPMode_Single      = ((uint8_t) 0x01),  /*!< Single one Pulse mode (OPM Active) */
+  TIM4_OPMode_Repetitive  = ((uint8_t) 0x00)   /*!< Repetitive Pulse mode (OPM inactive) */
+}TIM4_OPMode_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup TIM4_Reload_Mode_Prescaler
+  * @{
+  */
+typedef enum
+{
+  TIM4_PSCReloadMode_Update      = ((uint8_t)0x00), /*!< Prescaler value is reloaded at every update */
+  TIM4_PSCReloadMode_Immediate  = ((uint8_t)0x01)  /*!< Prescaler value is reloaded immediatly */
+}TIM4_PSCReloadMode_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup TIM4_Update_Source
+  * @{
+  */
+typedef enum
+{
+  TIM4_UpdateSource_Global  = ((uint8_t)0x00),  /*!< Global Update request source */
+  TIM4_UpdateSource_Regular  = ((uint8_t)0x01)   /*!< Regular Update request source */
+}TIM4_UpdateSource_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup TIM4_Event_Source
+  * @{
+  */
+typedef enum
+{
+  TIM4_EventSource_Update    = ((uint8_t)0x01),  /*!< Update Event */
+  TIM4_EventSource_Trigger  = ((uint8_t)0x40)   /*!< Trigger Event */
+}TIM4_EventSource_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup TIM4_Trigger_Output_Source
+  * @{
+  */
+typedef enum
+{
+  TIM4_TRGOSource_Reset   = ((uint8_t)0x00),  /*!< Trigger Output source = Reset */
+  TIM4_TRGOSource_Enable  = ((uint8_t)0x10),  /*!< Trigger Output source = TIM4 is enabled */
+  TIM4_TRGOSource_Update  = ((uint8_t)0x20)   /*!< Trigger Output source = Update event */
+}TIM4_TRGOSource_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup TIM4_Salve_Mode
+  * @{
+  */
+typedef enum
+{
+  TIM4_SlaveMode_Disable    = ((uint8_t)0x00),   /*!< Disable slave mode to clock the prescaler
+                                                      directly with the internal clock */
+  TIM4_SlaveMode_Reset      = ((uint8_t)0x04),   /*!< Slave Mode Selection  = Reset*/
+  TIM4_SlaveMode_Gated      = ((uint8_t)0x05),   /*!< Slave Mode Selection  = Gated*/
+  TIM4_SlaveMode_Trigger    = ((uint8_t)0x06),  /*!< Slave Mode Selection  = Trigger*/
+  TIM4_SlaveMode_External1  = ((uint8_t)0x07)    /*!< Slave Mode Selection  = External 1*/
+}TIM4_SlaveMode_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup TIM4_Flags
+  * @{
+  */
+typedef enum
+{
+  TIM4_FLAG_Update  = ((uint8_t)0x01),  /*!< Update Flag */
+  TIM4_FLAG_Trigger  = ((uint8_t)0x40)    /*!< Trigger Flag */
+}TIM4_FLAG_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup TIM4_Interrupts
+  * @{
+  */
+typedef enum
+{
+  TIM4_IT_Update  = ((uint8_t)0x01),  /*!< Update Interrupt*/
+  TIM4_IT_Trigger  = ((uint8_t)0x40)   /*!< Trigger  Interrupt*/
+}TIM4_IT_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup TIM4_Internal_Trigger_Selection
+  * @{
+  */
+typedef enum
+{
+  TIM4_TRGSelection_TIM5  = ((uint8_t)0x00), /*!< TRIG Input source =  TIM5 TRIG Output */
+  TIM4_TRGSelection_TIM1  = ((uint8_t)0x10), /*!< TRIG Input source =  TIM1 TRIG Output */
+  TIM4_TRGSelection_TIM3  = ((uint8_t)0x20), /*!< TRIG Input source =  TIM3 TRIG Output */
+  TIM4_TRGSelection_TIM2  = ((uint8_t)0x30)  /*!< TRIG Input source =  TIM2 TRIG Output */
+}TIM4_TRGSelection_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup TIM4_DMA_source_requests
+  * @{
+  */
+typedef enum
+{
+  TIM4_DMASource_Update    = ((uint8_t)0x01)  /*!< TIM4 DMA Update Request*/
+}TIM4_DMASource_TypeDef;
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/* Exported constants --------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
+
+/** @defgroup TIM4_Exported_Macros
+  * @{
+  */
+
+/**
+  * @brief Macro used by the assert function to check the different functions parameters.
+  */
+
+/**
+  * @brief Macro TIM4 Prescaler
+  */
+#define IS_TIM4_Prescaler(PRESCALER)  \
+  (((PRESCALER) == TIM4_Prescaler_1)    || \
+   ((PRESCALER) == TIM4_Prescaler_2)    || \
+   ((PRESCALER) == TIM4_Prescaler_4)    || \
+   ((PRESCALER) == TIM4_Prescaler_8)    || \
+   ((PRESCALER) == TIM4_Prescaler_16)   || \
+   ((PRESCALER) == TIM4_Prescaler_32)   || \
+   ((PRESCALER) == TIM4_Prescaler_64)   || \
+   ((PRESCALER) == TIM4_Prescaler_128)  || \
+   ((PRESCALER) == TIM4_Prescaler_256)  || \
+   ((PRESCALER) == TIM4_Prescaler_512)  || \
+   ((PRESCALER) == TIM4_Prescaler_1024) || \
+   ((PRESCALER) == TIM4_Prescaler_2048) || \
+   ((PRESCALER) == TIM4_Prescaler_4096) || \
+   ((PRESCALER) == TIM4_Prescaler_8192) || \
+   ((PRESCALER) == TIM4_Prescaler_16384)|| \
+   ((PRESCALER) == TIM4_Prescaler_32768))
+/**
+  * @brief Macro TIM4 One Pulse Mode
+  */
+#define IS_TIM4_OPM_MODE(MODE)  \
+  (((MODE) == TIM4_OPMode_Single) || \
+   ((MODE) == TIM4_OPMode_Repetitive))
+
+/**
+  * @brief Macro TIM4 Prescaler reload
+  */
+#define IS_TIM4_Prescaler_RELOAD(RELOAD) \
+  (((RELOAD) == TIM4_PSCReloadMode_Update) || \
+   ((RELOAD) == TIM4_PSCReloadMode_Immediate))
+/**
+  * @brief Macro TIM4 Update source
+  */
+#define IS_TIM4_UPDATE_SOURCE(SOURCE) \
+  (((SOURCE) == TIM4_UpdateSource_Global) || \
+   ((SOURCE) == TIM4_UpdateSource_Regular))
+/**
+  * @brief Macro TIM4 Event source
+  */
+#define IS_TIM4_EVENT_SOURCE(SOURCE) \
+  ((((SOURCE) & (uint8_t)0xBE) == 0x00) && \
+   ((SOURCE) != 0x00))
+
+/**
+  * @brief Macro TIM4 TRGO source
+  */
+#define IS_TIM4_TRGO_SOURCE(SOURCE) \
+  (((SOURCE) == TIM4_TRGOSource_Reset) || \
+   ((SOURCE) == TIM4_TRGOSource_Enable)|| \
+   ((SOURCE) == TIM4_TRGOSource_Update))
+/**
+  * @brief Macro TIM4 Slave mode
+  */
+#define IS_TIM4_SLAVE_MODE(MODE) \
+  (((MODE) == TIM4_SlaveMode_Disable) || \
+   ((MODE) == TIM4_SlaveMode_Reset)   || \
+   ((MODE) == TIM4_SlaveMode_Gated)   || \
+   ((MODE) == TIM4_SlaveMode_Trigger) || \
+   ((MODE) == TIM4_SlaveMode_External1))
+/**
+  * @brief Macro TIM4 Flags
+  */
+#define IS_TIM4_GET_FLAG(FLAG) \
+  (((FLAG) == TIM4_FLAG_Update) || \
+   ((FLAG) == TIM4_FLAG_Trigger))
+
+#define IS_TIM4_CLEAR_FLAG(FLAG) \
+  ((((FLAG) & (uint8_t)0xBE) == 0x00) && ((FLAG) != 0x00))
+/**
+  * @brief Macro TIM4 interrupts
+  */
+#define IS_TIM4_IT(IT) \
+  (((IT) != 0x00) && \
+   (((uint8_t)(IT) & (uint8_t)(~(uint8_t)(0x41)))== 0x00))
+
+#define IS_TIM4_GET_IT(IT) \
+  (((IT) == TIM4_IT_Update) || \
+   ((IT) == TIM4_IT_Trigger))
+/**
+  * @brief Macro TIM4 Trigger selection
+  */
+#define IS_TIM4_TRIGGER_SELECTION(SELECTION) \
+  (((SELECTION) == TIM4_TRGSelection_TIM5) || \
+   ((SELECTION) == TIM4_TRGSelection_TIM1) || \
+   ((SELECTION) == TIM4_TRGSelection_TIM3) || \
+   ((SELECTION) == TIM4_TRGSelection_TIM2))
+
+/**
+  * @brief Macro TIM4 DMA sources
+  */
+
+#define IS_TIM4_DMA_SOURCE(SOURCE) (((SOURCE) == TIM4_DMASource_Update))
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/* TimeBase management ********************************************************/
+void TIM4_DeInit(void);
+void TIM4_TimeBaseInit(TIM4_Prescaler_TypeDef TIM4_Prescaler,
+                       uint8_t TIM4_Period);
+void TIM4_PrescalerConfig(TIM4_Prescaler_TypeDef Prescaler,
+                          TIM4_PSCReloadMode_TypeDef TIM4_PSCReloadMode);
+void TIM4_SetCounter(uint8_t Counter);
+void TIM4_SetAutoreload(uint8_t Autoreload);
+uint8_t TIM4_GetCounter(void);
+TIM4_Prescaler_TypeDef TIM4_GetPrescaler(void);
+void TIM4_UpdateDisableConfig(FunctionalState NewState);
+void TIM4_UpdateRequestConfig(TIM4_UpdateSource_TypeDef TIM4_UpdateSource);
+void TIM4_ARRPreloadConfig(FunctionalState NewState);
+void TIM4_SelectOnePulseMode(TIM4_OPMode_TypeDef TIM4_OPMode);
+void TIM4_Cmd(FunctionalState NewState);
+
+/* Interrupts, DMA and flags management ***************************************/
+void TIM4_ITConfig(TIM4_IT_TypeDef TIM4_IT, FunctionalState NewState);
+void TIM4_GenerateEvent(TIM4_EventSource_TypeDef TIM4_EventSource);
+FlagStatus TIM4_GetFlagStatus(TIM4_FLAG_TypeDef TIM4_FLAG);
+void TIM4_ClearFlag(TIM4_FLAG_TypeDef TIM4_FLAG);
+ITStatus TIM4_GetITStatus(TIM4_IT_TypeDef TIM4_IT);
+void TIM4_ClearITPendingBit(TIM4_IT_TypeDef TIM4_IT);
+void TIM4_DMACmd(TIM4_DMASource_TypeDef TIM4_DMASource, FunctionalState NewState);
+
+/* Clocks management **********************************************************/
+void TIM4_InternalClockConfig(void);
+
+/* Synchronization management *************************************************/
+void TIM4_SelectInputTrigger(TIM4_TRGSelection_TypeDef TIM4_InputTriggerSource);
+void TIM4_SelectOutputTrigger(TIM4_TRGOSource_TypeDef TIM4_TRGOSource);
+void TIM4_SelectSlaveMode(TIM4_SlaveMode_TypeDef TIM4_SlaveMode);
+void TIM4_SelectMasterSlaveMode(FunctionalState NewState);
+
+#endif /* __STM8L15x_TIM4_H */
+
+/**
+ * @}
+ */
+
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_tim5.h b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_tim5.h
new file mode 100755
index 0000000..cecae93
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_tim5.h
@@ -0,0 +1,768 @@
+/**
+  ******************************************************************************
+  * @file    stm8l15x_tim5.h
+  * @author  MCD Application Team
+  * @version V1.6.0
+  * @date    28-June-2013
+  * @brief   This file contains all the functions prototypes for the TIM5 firmware
+  *          library.
+  ******************************************************************************
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ****************************************************************************** 
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM8L15x_TIM5_H
+#define __STM8L15x_TIM5_H
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm8l15x.h"
+
+/** @addtogroup STM8L15x_StdPeriph_Driver
+  * @{
+  */
+  
+/** @addtogroup TIM5
+  * @{
+  */ 
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup TIM5_Exported_Types
+  * @{
+  */
+
+/** @defgroup TIM5_Forced_Action
+  * @{
+  */
+typedef enum
+{
+  TIM5_ForcedAction_Active   = ((uint8_t)0x50),   /*!< Output Reference is forced low */
+  TIM5_ForcedAction_Inactive = ((uint8_t)0x40)    /*!< Output Reference is forced high */
+}
+TIM5_ForcedAction_TypeDef;
+
+#define IS_TIM5_FORCED_ACTION(ACTION) (((ACTION) == TIM5_ForcedAction_Active) || \
+                                       ((ACTION) == TIM5_ForcedAction_Inactive))
+/**
+  * @}
+  */
+  
+/** @defgroup TIM5_Prescaler
+  * @{
+  */
+typedef enum
+{
+  TIM5_Prescaler_1     = ((uint8_t)0x00),   /*!< Time base Prescaler = 1 (No effect)*/
+  TIM5_Prescaler_2     = ((uint8_t)0x01),   /*!< Time base Prescaler = 2 */
+  TIM5_Prescaler_4     = ((uint8_t)0x02),   /*!< Time base Prescaler = 4 */
+  TIM5_Prescaler_8     = ((uint8_t)0x03),   /*!< Time base Prescaler = 8 */
+  TIM5_Prescaler_16    = ((uint8_t)0x04),   /*!< Time base Prescaler = 16 */
+  TIM5_Prescaler_32    = ((uint8_t)0x05),   /*!< Time base Prescaler = 32 */
+  TIM5_Prescaler_64    = ((uint8_t)0x06),   /*!< Time base Prescaler = 64 */
+  TIM5_Prescaler_128   = ((uint8_t)0x07)    /*!< Time base Prescaler = 128 */
+}TIM5_Prescaler_TypeDef;
+
+#define IS_TIM5_PRESCALER(PRESCALER) (((PRESCALER) == TIM5_Prescaler_1)  || \
+                                      ((PRESCALER) == TIM5_Prescaler_2)  || \
+                                      ((PRESCALER) == TIM5_Prescaler_4)  || \
+                                      ((PRESCALER) == TIM5_Prescaler_8)  || \
+                                      ((PRESCALER) == TIM5_Prescaler_16) || \
+                                      ((PRESCALER) == TIM5_Prescaler_32) || \
+                                      ((PRESCALER) == TIM5_Prescaler_64) || \
+                                      ((PRESCALER) == TIM5_Prescaler_128))
+/**
+  * @}
+  */
+  
+/** @defgroup TIM5_OCMode
+  * @{
+  */
+typedef enum
+{
+  TIM5_OCMode_Timing    = ((uint8_t)0x00),   /*!< Timing (Frozen) Mode*/
+  TIM5_OCMode_Active    = ((uint8_t)0x10),   /*!< Active Mode*/
+  TIM5_OCMode_Inactive  = ((uint8_t)0x20),   /*!< Inactive Mode*/
+  TIM5_OCMode_Toggle    = ((uint8_t)0x30),   /*!< Toggle Mode*/
+  TIM5_OCMode_PWM1      = ((uint8_t)0x60),   /*!< PWM Mode 1*/
+  TIM5_OCMode_PWM2      = ((uint8_t)0x70)    /*!< PWM Mode 2*/
+}TIM5_OCMode_TypeDef;
+
+#define IS_TIM5_OC_MODE(MODE) (((MODE) ==  TIM5_OCMode_Timing)  || \
+                               ((MODE) == TIM5_OCMode_Active)   || \
+                               ((MODE) == TIM5_OCMode_Inactive) || \
+                               ((MODE) == TIM5_OCMode_Toggle)   || \
+                               ((MODE) == TIM5_OCMode_PWM1)     || \
+                               ((MODE) == TIM5_OCMode_PWM2))
+
+#define IS_TIM5_OCM(MODE) (((MODE) ==  TIM5_OCMode_Timing)  || \
+                           ((MODE) == TIM5_OCMode_Active)   || \
+                           ((MODE) == TIM5_OCMode_Inactive) || \
+                           ((MODE) == TIM5_OCMode_Toggle)   || \
+                           ((MODE) == TIM5_OCMode_PWM1)     || \
+                           ((MODE) == TIM5_OCMode_PWM2)     || \
+                           ((MODE) == (uint8_t)TIM5_ForcedAction_Active) || \
+                           ((MODE) == (uint8_t)TIM5_ForcedAction_Inactive))
+/**
+  * @}
+  */
+  
+/** @defgroup TIM5_OnePulseMode
+  * @{
+  */
+typedef enum
+{
+  TIM5_OPMode_Single      = ((uint8_t)0x01), /*!< Single one Pulse mode (OPM Active) */
+  TIM5_OPMode_Repetitive  = ((uint8_t)0x00)  /*!< Repetitive Pulse mode (OPM inactive) */
+}TIM5_OPMode_TypeDef;
+
+#define IS_TIM5_OPM_MODE(MODE) (((MODE) == TIM5_OPMode_Single) || \
+                                ((MODE) == TIM5_OPMode_Repetitive))
+/**
+  * @}
+  */
+  
+/** @defgroup TIM5_Channel
+  * @{
+  */
+typedef enum
+{
+  TIM5_Channel_1  = ((uint8_t)0x00),  /*!< Channel 1*/
+  TIM5_Channel_2  = ((uint8_t)0x01)   /*!< Channel 2*/
+}TIM5_Channel_TypeDef;
+
+#define IS_TIM5_CHANNEL(CHANNEL) (((CHANNEL) == TIM5_Channel_1) || \
+                                  ((CHANNEL) == TIM5_Channel_2) )
+/**
+  * @}
+  */
+  
+/** @defgroup TIM5_CounterMode
+  * @{
+  */
+typedef enum
+{
+  TIM5_CounterMode_Up               = ((uint8_t)0x00),   /*!< Counter Up Mode */
+  TIM5_CounterMode_Down             = ((uint8_t)0x10),   /*!< Counter Down Mode */
+  TIM5_CounterMode_CenterAligned1   = ((uint8_t)0x20),   /*!< Counter Central aligned Mode 1 */
+  TIM5_CounterMode_CenterAligned2   = ((uint8_t)0x40),   /*!< Counter Central aligned Mode 2 */
+  TIM5_CounterMode_CenterAligned3   = ((uint8_t)0x60)    /*!< Counter Central aligned Mode 3 */
+}TIM5_CounterMode_TypeDef;
+
+#define IS_TIM5_COUNTER_MODE(MODE) (((MODE) == TIM5_CounterMode_Up)   || \
+                                    ((MODE) == TIM5_CounterMode_Down) || \
+                                    ((MODE) == TIM5_CounterMode_CenterAligned1) || \
+                                    ((MODE) == TIM5_CounterMode_CenterAligned2) || \
+                                    ((MODE) == TIM5_CounterMode_CenterAligned3))
+/**
+  * @}
+  */
+  
+/** @defgroup TIM5_Output_Compare_Polarity
+  * @{
+  */
+typedef enum
+{
+  TIM5_OCPolarity_High   = ((uint8_t)0x00),   /*!< Output compare polarity  = High */
+  TIM5_OCPolarity_Low    = ((uint8_t)0x01)    /*!< Output compare polarity  = Low */
+}TIM5_OCPolarity_TypeDef;
+
+#define IS_TIM5_OC_POLARITY(POLARITY) (((POLARITY) == TIM5_OCPolarity_High) || \
+                                       ((POLARITY) == TIM5_OCPolarity_Low))
+/**
+  * @}
+  */
+  
+/** @defgroup TIM5_Output_State
+  * @{
+  */
+typedef enum
+{
+  TIM5_OutputState_Disable   = ((uint8_t)0x00),   /*!< Output compare State disabled (channel output disabled) */
+  TIM5_OutputState_Enable    = ((uint8_t)0x01)    /*!< Output compare State enabled (channel output enabled) */
+}TIM5_OutputState_TypeDef;
+
+#define IS_TIM5_OUTPUT_STATE(STATE) (((STATE) == TIM5_OutputState_Disable) || \
+                                     ((STATE) == TIM5_OutputState_Enable))
+
+/**
+  * @}
+  */
+  
+/** @defgroup TIM5_Break_State
+  * @{
+  */
+typedef enum
+{
+  TIM5_BreakState_Disable  = ((uint8_t)0x00),   /*!< Break State disabled (break option disabled) */
+  TIM5_BreakState_Enable   = ((uint8_t)0x10)    /*!< Break State enabled (break option enabled) */
+}TIM5_BreakState_TypeDef;
+
+#define IS_TIM5_BREAK_STATE(STATE) (((STATE) == TIM5_BreakState_Enable) || \
+                                    ((STATE) == TIM5_BreakState_Disable))
+/**
+  * @}
+  */
+  
+/** @defgroup TIM5_Break_Polarity
+  * @{
+  */
+typedef enum
+{
+  TIM5_BreakPolarity_High  = ((uint8_t)0x20),  /*!< if Break, channel polarity = High */
+  TIM5_BreakPolarity_Low   = ((uint8_t)0x00)   /*!< if Break, channel polarity = Low */
+}TIM5_BreakPolarity_TypeDef;
+
+#define IS_TIM5_BREAK_POLARITY(POLARITY) \
+  (((POLARITY) == TIM5_BreakPolarity_Low) || \
+   ((POLARITY) == TIM5_BreakPolarity_High))
+/**
+  * @}
+  */
+
+/** @defgroup TIM5_Automatic_Output
+  * @{
+  */
+typedef enum
+{
+  TIM5_AutomaticOutput_Enable    = ((uint8_t)0x40),   /*!< Automatic Output option enabled */
+  TIM5_AutomaticOutput_Disable   = ((uint8_t)0x00)    /*!< Automatic Output option disabled */
+}TIM5_AutomaticOutput_TypeDef;
+
+#define IS_TIM5_AUTOMATIC_OUTPUT_STATE(STATE) \
+  (((STATE) == TIM5_AutomaticOutput_Enable) || \
+   ((STATE) == TIM5_AutomaticOutput_Disable))
+/**
+  * @}
+  */
+  
+/** @defgroup TIM5_Lock_Level
+  * @{
+  */
+typedef enum
+{
+  TIM5_LockLevel_Off  = ((uint8_t)0x00),   /*!< Lock option disabled */
+  TIM5_LockLevel_1    = ((uint8_t)0x01),   /*!< Select Lock Level 1  */
+  TIM5_LockLevel_2    = ((uint8_t)0x02),   /*!< Select Lock Level 2  */
+  TIM5_LockLevel_3    = ((uint8_t)0x03)    /*!< Select Lock Level 3  */
+}TIM5_LockLevel_TypeDef;
+
+#define IS_TIM5_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM5_LockLevel_Off) || \
+                                   ((LEVEL) == TIM5_LockLevel_1)   || \
+                                   ((LEVEL) == TIM5_LockLevel_2)   || \
+                                   ((LEVEL) == TIM5_LockLevel_3))
+/**
+  * @}
+  */
+  
+/** @defgroup TIM5_OSSI_State
+  * @{
+  */
+typedef enum
+{
+  TIM5_OSSIState_Enable    = ((uint8_t)0x04),   /*!< Off-State Selection for Idle mode enabled  */
+  TIM5_OSSIState_Disable   = ((uint8_t)0x00)    /*!< Off-State Selection for Idle mode disabled  */
+}TIM5_OSSIState_TypeDef;
+
+#define IS_TIM5_OSSI_STATE(STATE) \
+  (((STATE) == TIM5_OSSIState_Enable) || \
+   ((STATE) == TIM5_OSSIState_Disable))
+/**
+  * @}
+  */
+  
+/** @defgroup TIM5_Output_Compare_Idle_state
+  * @{
+  */
+typedef enum
+{
+  TIM5_OCIdleState_Reset  = ((uint8_t)0x00),   /*!< Output Compare Idle state  = Reset */
+  TIM5_OCIdleState_Set    = ((uint8_t)0x01)    /*!< Output Compare Idle state  = Set */
+}TIM5_OCIdleState_TypeDef;
+
+#define IS_TIM5_OCIDLE_STATE(STATE) \
+  (((STATE) == TIM5_OCIdleState_Set) || \
+   ((STATE) == TIM5_OCIdleState_Reset))
+/**
+  * @}
+  */
+  
+/** @defgroup TIM5_Input_Capture_Polarity
+  * @{
+  */
+typedef enum
+{
+  TIM5_ICPolarity_Rising   = ((uint8_t)0x00),   /*!< Input Capture on Rising Edge*/
+  TIM5_ICPolarity_Falling  = ((uint8_t)0x01)    /*!< Input Capture on Falling Edge*/
+}TIM5_ICPolarity_TypeDef;
+
+#define IS_TIM5_IC_POLARITY(POLARITY) \
+  (((POLARITY) == TIM5_ICPolarity_Rising) || \
+   ((POLARITY) == TIM5_ICPolarity_Falling))
+/**
+  * @}
+  */
+  
+/** @defgroup TIM5_Input_Capture_Selection
+  * @{
+  */
+typedef enum
+{
+  TIM5_ICSelection_DirectTI    = ((uint8_t)0x01),   /*!< Input Capture mapped on the direct input*/
+  TIM5_ICSelection_IndirectTI  = ((uint8_t)0x02),   /*!< Input Capture mapped on the indirect input*/
+  TIM5_ICSelection_TRGI        = ((uint8_t)0x03)    /*!< Input Capture mapped on the Trigger Input*/
+}TIM5_ICSelection_TypeDef;
+
+#define IS_TIM5_IC_SELECTION(SELECTION) \
+  (((SELECTION) == TIM5_ICSelection_DirectTI)   || \
+   ((SELECTION) == TIM5_ICSelection_IndirectTI) || \
+   ((SELECTION) == TIM5_ICSelection_TRGI))
+/**
+  * @}
+  */
+  
+/** @defgroup TIM5_Input_Capture_Prescaler
+  * @{
+  */
+typedef enum
+{
+  TIM5_ICPSC_DIV1  = ((uint8_t)0x00),  /*!< Input Capture Prescaler = 1 (one capture every 1 event) */
+  TIM5_ICPSC_DIV2  = ((uint8_t)0x04),  /*!< Input Capture Prescaler = 2 (one capture every 2 events) */
+  TIM5_ICPSC_DIV4  = ((uint8_t)0x08),  /*!< Input Capture Prescaler = 4 (one capture every 4 events) */
+  TIM5_ICPSC_DIV8  = ((uint8_t)0x0C)   /*!< Input Capture Prescaler = 8 (one capture every 8 events) */
+}TIM5_ICPSC_TypeDef;
+
+#define IS_TIM5_IC_PRESCALER(PRESCALER) \
+  (((PRESCALER) == TIM5_ICPSC_DIV1) || \
+   ((PRESCALER) == TIM5_ICPSC_DIV2) || \
+   ((PRESCALER) == TIM5_ICPSC_DIV4) || \
+   ((PRESCALER) == TIM5_ICPSC_DIV8))
+/**
+  * @}
+  */
+  
+/** @defgroup TIM5_Interrupts
+  * @{
+  */
+typedef enum
+{
+  TIM5_IT_Update   = ((uint8_t)0x01),   /*!< Update Interrupt*/
+  TIM5_IT_CC1      = ((uint8_t)0x02),   /*!< Capture Compare Channel1 Interrupt*/
+  TIM5_IT_CC2      = ((uint8_t)0x04),   /*!< Capture Compare Channel2 Interrupt*/
+  TIM5_IT_Trigger  = ((uint8_t)0x40),   /*!< Trigger  Interrupt*/
+  TIM5_IT_Break    = ((uint8_t)0x80)    /*!< Break Interrupt*/
+}TIM5_IT_TypeDef;
+
+#define IS_TIM5_IT(IT) \
+  ((IT) != 0x00)
+
+#define IS_TIM5_GET_IT(IT) \
+  (((IT) == TIM5_IT_Update)  || \
+   ((IT) == TIM5_IT_CC1)     || \
+   ((IT) == TIM5_IT_CC2)     || \
+   ((IT) == TIM5_IT_Trigger) || \
+   ((IT) == TIM5_IT_Break))
+/**
+  * @}
+  */
+  
+/** @defgroup TIM5_External_Trigger_Prescaler
+  * @{
+  */
+typedef enum
+{
+  TIM5_ExtTRGPSC_OFF   = ((uint8_t)0x00),   /*!< No External Trigger prescaler  */
+  TIM5_ExtTRGPSC_DIV2  = ((uint8_t)0x10),   /*!< External Trigger prescaler = 2 (ETRP frequency divided by 2) */
+  TIM5_ExtTRGPSC_DIV4  = ((uint8_t)0x20),   /*!< External Trigger prescaler = 4 (ETRP frequency divided by 4) */
+  TIM5_ExtTRGPSC_DIV8  = ((uint8_t)0x30)    /*!< External Trigger prescaler = 8 (ETRP frequency divided by 8) */
+}TIM5_ExtTRGPSC_TypeDef;
+
+#define IS_TIM5_EXT_PRESCALER(PRESCALER) \
+  (((PRESCALER) == TIM5_ExtTRGPSC_OFF)  || \
+   ((PRESCALER) == TIM5_ExtTRGPSC_DIV2) || \
+   ((PRESCALER) == TIM5_ExtTRGPSC_DIV4) || \
+   ((PRESCALER) == TIM5_ExtTRGPSC_DIV8))
+/**
+  * @}
+  */
+  
+/** @defgroup TIM5_Internal_Trigger_Selection
+  * @{
+  */
+typedef enum
+{
+  TIM5_TRGSelection_TIM4     = ((uint8_t)0x00),  /*!< TRIG Input source =  TIM TRIG Output  */
+  TIM5_TRGSelection_TIM1     = ((uint8_t)0x10),  /*!< TRIG Input source =  TIM TRIG Output  */
+  TIM5_TRGSelection_TIM3     = ((uint8_t)0x20),  /*!< TRIG Input source =  TIM TRIG Output  */
+  TIM5_TRGSelection_TIM2     = ((uint8_t)0x30),  /*!< TRIG Input source =  TIM TRIG Output  */
+  TIM5_TRGSelection_TI1F_ED  = ((uint8_t)0x40),  /*!< TRIG Input source = TI1F_ED (TI1 Edge Detector)  */
+  TIM5_TRGSelection_TI1FP1   = ((uint8_t)0x50),  /*!< TRIG Input source = TI1FP1 (Filtred Timer Input 1) */
+  TIM5_TRGSelection_TI2FP2   = ((uint8_t)0x60),  /*!< TRIG Input source = TI2FP2 (Filtred Timer Input 2)  */
+  TIM5_TRGSelection_ETRF     = ((uint8_t)0x70)   /*!< TRIG Input source =  ETRF (External Trigger Input ) */
+}TIM5_TRGSelection_TypeDef;
+
+#define IS_TIM5_TRIGGER_SELECTION(SELECTION) \
+  (((SELECTION) == TIM5_TRGSelection_TIM4) || \
+   ((SELECTION) == TIM5_TRGSelection_TIM1) || \
+   ((SELECTION) == TIM5_TRGSelection_TIM3) || \
+   ((SELECTION) == TIM5_TRGSelection_TIM2) || \
+   ((SELECTION) == TIM5_TRGSelection_TI1F_ED) || \
+   ((SELECTION) == TIM5_TRGSelection_TI1FP1)  || \
+   ((SELECTION) == TIM5_TRGSelection_TI2FP2)  || \
+   ((SELECTION) == TIM5_TRGSelection_ETRF))
+
+
+#define IS_TIM5_TIX_TRIGGER_SELECTION(SELECTION) \
+  (((SELECTION) == TIM5_TRGSelection_TI1F_ED) || \
+   ((SELECTION) == TIM5_TRGSelection_TI1FP1)  || \
+   ((SELECTION) == TIM5_TRGSelection_TI2FP2))
+/**
+  * @}
+  */
+  
+/** @defgroup TIM5_TI_External_Clock_Source
+  * @{
+  */
+typedef enum
+{
+  TIM5_TIxExternalCLK1Source_TI1ED  = ((uint8_t)0x40),   /*!< External Clock mode 1 source = TI1ED */
+  TIM5_TIxExternalCLK1Source_TI1    = ((uint8_t)0x50),   /*!< External Clock mode 1 source = TI1 */
+  TIM5_TIxExternalCLK1Source_TI2    = ((uint8_t)0x60)    /*!< External Clock mode 1 source = TI2 */
+}TIM5_TIxExternalCLK1Source_TypeDef;
+
+#define IS_TIM5_TIXCLK_SOURCE(SOURCE)  \
+  (((SOURCE) == TIM5_TIxExternalCLK1Source_TI1ED) || \
+   ((SOURCE) == TIM5_TIxExternalCLK1Source_TI2)   || \
+   ((SOURCE) == TIM5_TIxExternalCLK1Source_TI1))
+
+/**
+  * @}
+  */
+  
+/** @defgroup TIM5_External_Trigger_Polarity
+  * @{
+  */
+typedef enum
+{
+  TIM5_ExtTRGPolarity_Inverted     = ((uint8_t)0x80),   /*!< External Trigger Polarity = inverted */
+  TIM5_ExtTRGPolarity_NonInverted  = ((uint8_t)0x00)    /*!< External Trigger Polarity = non inverted */
+}TIM5_ExtTRGPolarity_TypeDef;
+
+#define IS_TIM5_EXT_POLARITY(POLARITY) \
+  (((POLARITY) == TIM5_ExtTRGPolarity_Inverted) || \
+   ((POLARITY) == TIM5_ExtTRGPolarity_NonInverted))
+/**
+  * @}
+  */
+  
+/** @defgroup TIM5_Prescaler_Reload_Mode
+  * @{
+  */
+typedef enum
+{
+  TIM5_PSCReloadMode_Update      = ((uint8_t)0x00),   /*!< Prescaler value is reloaded at every update*/
+  TIM5_PSCReloadMode_Immediate   = ((uint8_t)0x01)    /*!< Prescaler value is reloaded immediatly*/
+}TIM5_PSCReloadMode_TypeDef;
+
+#define IS_TIM5_PRESCALER_RELOAD(RELOAD) \
+  (((RELOAD) == TIM5_PSCReloadMode_Update) || \
+   ((RELOAD) == TIM5_PSCReloadMode_Immediate))
+/**
+  * @}
+  */
+  
+/** @defgroup TIM5_Encoder_Mode
+  * @{
+  */
+typedef enum
+{
+  TIM5_EncoderMode_TI1     = ((uint8_t)0x01),   /*!< Encoder mode 1*/
+  TIM5_EncoderMode_TI2     = ((uint8_t)0x02),   /*!< Encoder mode 2*/
+  TIM5_EncoderMode_TI12    = ((uint8_t)0x03)    /*!< Encoder mode 3*/
+}TIM5_EncoderMode_TypeDef;
+
+#define IS_TIM5_ENCODER_MODE(MODE) \
+  (((MODE) == TIM5_EncoderMode_TI1) || \
+   ((MODE) == TIM5_EncoderMode_TI2) || \
+   ((MODE) == TIM5_EncoderMode_TI12))
+/**
+  * @}
+  */
+  
+/** @defgroup TIM5_Event_Source
+  * @{
+  */
+typedef enum
+{
+  TIM5_EventSource_Update   = ((uint8_t)0x01),   /*!< Update Event*/
+  TIM5_EventSource_CC1      = ((uint8_t)0x02),   /*!< Capture Compare Channel1  Event*/
+  TIM5_EventSource_CC2      = ((uint8_t)0x04),   /*!< Capture Compare Channel2 Event*/
+  TIM5_EventSource_Trigger  = ((uint8_t)0x40),   /*!< Trigger Event*/
+  TIM5_EventSource_Break    = ((uint8_t)0x80)    /*!< Break Event*/
+}TIM5_EventSource_TypeDef;
+
+#define IS_TIM5_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint8_t)0x18) == 0x00) && \
+                                      ((SOURCE) != 0x00))
+/**
+  * @}
+  */
+  
+/** @defgroup TIM5_Update_Source
+  * @{
+  */
+typedef enum
+{
+  TIM5_UpdateSource_Global   = ((uint8_t)0x00),   /*!< Global Update request source */
+  TIM5_UpdateSource_Regular  = ((uint8_t)0x01)    /*!< Regular Update request source */
+}TIM5_UpdateSource_TypeDef;
+
+#define IS_TIM5_UPDATE_SOURCE(SOURCE) \
+  (((SOURCE) == TIM5_UpdateSource_Global) || \
+   ((SOURCE) == TIM5_UpdateSource_Regular))
+
+/**
+  * @}
+  */
+  
+/** @defgroup TIM5_Trigger_Output_Source
+  * @{
+  */
+typedef enum
+{
+  TIM5_TRGOSource_Reset    = ((uint8_t)0x00),   /*!< Trigger Output source = Reset*/
+  TIM5_TRGOSource_Enable   = ((uint8_t)0x10),   /*!< Trigger Output source = TIM5 is enabled*/
+  TIM5_TRGOSource_Update   = ((uint8_t)0x20),   /*!< Trigger Output source = Update event*/
+  TIM5_TRGOSource_OC1      = ((uint8_t)0x30),   /*!< Trigger Output source = output compare channel1  */
+  TIM5_TRGOSource_OC1REF   = ((uint8_t)0x40),   /*!< Trigger Output source = output compare channel 1 reference */
+  TIM5_TRGOSource_OC2REF   = ((uint8_t)0x50)    /*!< Trigger Output source = output compare channel 2 reference */
+}TIM5_TRGOSource_TypeDef;
+
+#define IS_TIM5_TRGO_SOURCE(SOURCE) \
+  (((SOURCE) == TIM5_TRGOSource_Reset)  || \
+   ((SOURCE) == TIM5_TRGOSource_Enable) || \
+   ((SOURCE) == TIM5_TRGOSource_Update) || \
+   ((SOURCE) == TIM5_TRGOSource_OC1)    || \
+   ((SOURCE) == TIM5_TRGOSource_OC1REF) || \
+   ((SOURCE) == TIM5_TRGOSource_OC2REF))
+/**
+  * @}
+  */
+  
+/** @defgroup TIM5_Slave_Mode
+  * @{
+  */
+typedef enum
+{
+  TIM5_SlaveMode_Reset      = ((uint8_t)0x04),  /*!< Slave Mode Selection  = Reset*/
+  TIM5_SlaveMode_Gated      = ((uint8_t)0x05),  /*!< Slave Mode Selection  = Gated*/
+  TIM5_SlaveMode_Trigger    = ((uint8_t)0x06),  /*!< Slave Mode Selection  = Trigger*/
+  TIM5_SlaveMode_External1  = ((uint8_t)0x07)   /*!< Slave Mode Selection  = External 1*/
+}TIM5_SlaveMode_TypeDef;
+
+#define IS_TIM5_SLAVE_MODE(MODE) \
+  (((MODE) == TIM5_SlaveMode_Reset)   || \
+   ((MODE) == TIM5_SlaveMode_Gated)   || \
+   ((MODE) == TIM5_SlaveMode_Trigger) || \
+   ((MODE) == TIM5_SlaveMode_External1))
+/**
+  * @}
+  */
+  
+/** @defgroup TIM5_Flags
+  * @{
+  */
+typedef enum
+{
+  TIM5_FLAG_Update   = ((uint16_t)0x0001),  /*!< Update Flag */
+  TIM5_FLAG_CC1      = ((uint16_t)0x0002),  /*!< Capture compare 1 Flag */
+  TIM5_FLAG_CC2      = ((uint16_t)0x0004),  /*!< Capture compare 2 Flag */
+  TIM5_FLAG_Trigger  = ((uint16_t)0x0040),  /*!< Trigger Flag */
+  TIM5_FLAG_Break    = ((uint16_t)0x0080),  /*!< Break Flag */
+  TIM5_FLAG_CC1OF    = ((uint16_t)0x0200),  /*!< Capture compare 1 over capture Flag */
+  TIM5_FLAG_CC2OF    = ((uint16_t)0x0400)   /*!< Capture compare 2 over capture Flag */
+}TIM5_FLAG_TypeDef;
+
+#define IS_TIM5_GET_FLAG(FLAG) \
+  (((FLAG) == TIM5_FLAG_Update)  || \
+   ((FLAG) == TIM5_FLAG_CC1)     || \
+   ((FLAG) == TIM5_FLAG_CC2)     || \
+   ((FLAG) == TIM5_FLAG_Trigger) || \
+   ((FLAG) == TIM5_FLAG_Break)   || \
+   ((FLAG) == TIM5_FLAG_CC1OF)   || \
+   ((FLAG) == TIM5_FLAG_CC2OF))
+
+#define IS_TIM5_CLEAR_FLAG(FLAG) \
+  ((((FLAG) & (uint16_t)0xE100) == 0x0000) && ((FLAG) != 0x0000))
+/**
+  * @}
+  */
+  
+/** @defgroup TIM5_DMA_Source_Requests
+  * @{
+  */
+typedef enum
+{
+  TIM5_DMASource_Update   = ((uint8_t)0x01),  /*!< TIM5 DMA Update Request*/
+  TIM5_DMASource_CC1      = ((uint8_t)0x02),  /*!< TIM5 DMA CC1 Request*/
+  TIM5_DMASource_CC2      = ((uint8_t)0x04)   /*!< TIM5 DMA CC2 Request*/
+}TIM5_DMASource_TypeDef;
+
+#define IS_TIM5_DMA_SOURCE(SOURCE) \
+  (((SOURCE) == TIM5_DMASource_Update) || \
+   ((SOURCE) == TIM5_DMASource_CC1) || \
+   ((SOURCE) == TIM5_DMASource_CC2))
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
+
+/** @defgroup TIM5_Exported_Macros
+  * @{
+  */
+
+/**
+  * @brief Macro TIM5 Input Capture Filter Value
+  */
+#define IS_TIM5_IC_FILTER(ICFILTER) ((ICFILTER) <= 0x0F)
+
+/**
+  * @brief Macro TIM5 External Trigger Filter
+  */
+#define IS_TIM5_EXT_FILTER(EXTFILTER) \
+  ((EXTFILTER) <= 0x0F)
+
+/**
+  * @}
+  */
+
+/* Exported functions ------------------------------------------------------- */
+
+/* TimeBase management ********************************************************/
+void TIM5_DeInit(void);
+void TIM5_TimeBaseInit(TIM5_Prescaler_TypeDef TIM5_Prescaler,
+                       TIM5_CounterMode_TypeDef TIM5_CounterMode, uint16_t TIM5_Period);
+void TIM5_PrescalerConfig(TIM5_Prescaler_TypeDef Prescaler,
+                          TIM5_PSCReloadMode_TypeDef TIM5_PSCReloadMode);
+void TIM5_CounterModeConfig(TIM5_CounterMode_TypeDef TIM5_CounterMode);
+void TIM5_SetCounter(uint16_t Counter);
+void TIM5_SetAutoreload(uint16_t Autoreload);
+uint16_t TIM5_GetCounter(void);
+TIM5_Prescaler_TypeDef TIM5_GetPrescaler(void);
+void TIM5_UpdateDisableConfig(FunctionalState NewState);
+void TIM5_UpdateRequestConfig(TIM5_UpdateSource_TypeDef TIM5_UpdateSource);
+void TIM5_ARRPreloadConfig(FunctionalState NewState);
+void TIM5_SelectOnePulseMode(TIM5_OPMode_TypeDef TIM5_OPMode);
+void TIM5_Cmd(FunctionalState NewState);
+
+/* Output Compare management **************************************************/
+void TIM5_OC1Init(TIM5_OCMode_TypeDef TIM5_OCMode,
+                  TIM5_OutputState_TypeDef TIM5_OutputState,
+                  uint16_t TIM5_Pulse,
+                  TIM5_OCPolarity_TypeDef TIM5_OCPolarity,
+                  TIM5_OCIdleState_TypeDef TIM5_OCIdleState);
+void TIM5_OC2Init(TIM5_OCMode_TypeDef TIM5_OCMode,
+                  TIM5_OutputState_TypeDef TIM5_OutputState,
+                  uint16_t TIM5_Pulse,
+                  TIM5_OCPolarity_TypeDef TIM5_OCPolarity,
+                  TIM5_OCIdleState_TypeDef TIM5_OCIdleState);
+void TIM5_BKRConfig(TIM5_OSSIState_TypeDef TIM5_OSSIState,
+                    TIM5_LockLevel_TypeDef TIM5_LockLevel,
+                    TIM5_BreakState_TypeDef TIM5_BreakState,
+                    TIM5_BreakPolarity_TypeDef TIM5_BreakPolarity,
+                    TIM5_AutomaticOutput_TypeDef TIM5_AutomaticOutput);
+void TIM5_CtrlPWMOutputs(FunctionalState NewState);
+void TIM5_SelectOCxM(TIM5_Channel_TypeDef TIM5_Channel, TIM5_OCMode_TypeDef TIM5_OCMode);
+void TIM5_SetCompare1(uint16_t Compare);
+void TIM5_SetCompare2(uint16_t Compare);
+void TIM5_ForcedOC1Config(TIM5_ForcedAction_TypeDef TIM5_ForcedAction);
+void TIM5_ForcedOC2Config(TIM5_ForcedAction_TypeDef TIM5_ForcedAction);
+void TIM5_OC1PreloadConfig(FunctionalState NewState);
+void TIM5_OC2PreloadConfig(FunctionalState NewState);
+void TIM5_OC1FastConfig(FunctionalState NewState);
+void TIM5_OC2FastConfig(FunctionalState NewState);
+void TIM5_OC1PolarityConfig(TIM5_OCPolarity_TypeDef TIM5_OCPolarity);
+void TIM5_OC2PolarityConfig(TIM5_OCPolarity_TypeDef TIM5_OCPolarity);
+void TIM5_CCxCmd(TIM5_Channel_TypeDef TIM5_Channel, FunctionalState NewState);
+
+/* Input Capture management ***************************************************/
+void TIM5_ICInit(TIM5_Channel_TypeDef TIM5_Channel,
+                 TIM5_ICPolarity_TypeDef TIM5_ICPolarity,
+                 TIM5_ICSelection_TypeDef TIM5_ICSelection,
+                 TIM5_ICPSC_TypeDef TIM5_ICPrescaler,
+                 uint8_t TIM5_ICFilter);
+void TIM5_PWMIConfig(TIM5_Channel_TypeDef TIM5_Channel,
+                     TIM5_ICPolarity_TypeDef TIM5_ICPolarity,
+                     TIM5_ICSelection_TypeDef TIM5_ICSelection,
+                     TIM5_ICPSC_TypeDef TIM5_ICPrescaler,
+                     uint8_t TIM5_ICFilter);
+uint16_t TIM5_GetCapture1(void);
+uint16_t TIM5_GetCapture2(void);
+void TIM5_SetIC1Prescaler(TIM5_ICPSC_TypeDef TIM5_IC1Prescaler);
+void TIM5_SetIC2Prescaler(TIM5_ICPSC_TypeDef TIM5_IC2Prescaler);
+
+/* Interrupts, DMA and flags management ***************************************/
+void TIM5_ITConfig(TIM5_IT_TypeDef TIM5_IT, FunctionalState NewState);
+void TIM5_GenerateEvent(TIM5_EventSource_TypeDef TIM5_EventSource);
+FlagStatus TIM5_GetFlagStatus(TIM5_FLAG_TypeDef TIM5_FLAG);
+void TIM5_ClearFlag(TIM5_FLAG_TypeDef TIM5_FLAG);
+ITStatus TIM5_GetITStatus(TIM5_IT_TypeDef TIM5_IT);
+void TIM5_ClearITPendingBit(TIM5_IT_TypeDef TIM5_IT);
+void TIM5_DMACmd(TIM5_DMASource_TypeDef TIM5_DMASource, FunctionalState NewState);
+void TIM5_SelectCCDMA(FunctionalState NewState);
+
+/* Clocks management **********************************************************/
+void TIM5_InternalClockConfig(void);
+void TIM5_TIxExternalClockConfig(TIM5_TIxExternalCLK1Source_TypeDef TIM5_TIxExternalCLKSource,
+                                 TIM5_ICPolarity_TypeDef TIM5_ICPolarity,
+                                 uint8_t ICFilter);
+void TIM5_ETRClockMode1Config(TIM5_ExtTRGPSC_TypeDef TIM5_ExtTRGPrescaler,
+                              TIM5_ExtTRGPolarity_TypeDef TIM5_ExtTRGPolarity,
+                              uint8_t ExtTRGFilter);
+void TIM5_ETRClockMode2Config(TIM5_ExtTRGPSC_TypeDef TIM5_ExtTRGPrescaler,
+                              TIM5_ExtTRGPolarity_TypeDef TIM5_ExtTRGPolarity,
+                              uint8_t ExtTRGFilter);
+
+/* Synchronization management *************************************************/
+void TIM5_SelectInputTrigger(TIM5_TRGSelection_TypeDef TIM5_InputTriggerSource);
+void TIM5_SelectOutputTrigger(TIM5_TRGOSource_TypeDef TIM5_TRGOSource);
+void TIM5_SelectSlaveMode(TIM5_SlaveMode_TypeDef TIM5_SlaveMode);
+void TIM5_SelectMasterSlaveMode(FunctionalState NewState);
+void TIM5_ETRConfig(TIM5_ExtTRGPSC_TypeDef TIM5_ExtTRGPrescaler,
+                    TIM5_ExtTRGPolarity_TypeDef TIM5_ExtTRGPolarity,
+                    uint8_t ExtTRGFilter);
+
+/* Specific interface management **********************************************/
+void TIM5_EncoderInterfaceConfig(TIM5_EncoderMode_TypeDef TIM5_EncoderMode,
+                                 TIM5_ICPolarity_TypeDef TIM5_IC1Polarity,
+                                 TIM5_ICPolarity_TypeDef TIM5_IC2Polarity);
+void TIM5_SelectHallSensor(FunctionalState NewState);
+
+#endif /* __STM8L15x_TIM5_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_usart.h b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_usart.h
new file mode 100755
index 0000000..0751c91
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_usart.h
@@ -0,0 +1,390 @@
+/**
+  ********************************************************************************
+  * @file    stm8l15x_usart.h
+  * @author  MCD Application Team
+  * @version V1.6.0
+  * @date    28-June-2013
+  * @brief   This file contains all the functions prototypes for the USART firmware
+  *          library.
+  ******************************************************************************
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ****************************************************************************** 
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM8L15x_USART_H
+#define __STM8L15x_USART_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm8l15x.h"
+#include "stm8l15x_clk.h"
+
+/** @addtogroup STM8L15x_StdPeriph_Driver
+  * @{
+  */
+/** @addtogroup USART
+  * @{
+  */ 
+  
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup USART_Exported_Types
+  * @{
+  */
+
+/** @defgroup USART_Flags
+  * @{
+  */
+typedef enum 
+{ 
+ USART_FLAG_TXE   = (uint16_t)0x0080, /*!< Transmit Data Register Empty flag */
+ USART_FLAG_TC    = (uint16_t)0x0040, /*!< Transmission Complete flag */
+ USART_FLAG_RXNE  = (uint16_t)0x0020, /*!< Read Data Register Not Empty flag */
+ USART_FLAG_IDLE  = (uint16_t)0x0010, /*!< Idle line detected flag */
+ USART_FLAG_OR    = (uint16_t)0x0008, /*!< OverRun error flag */
+ USART_FLAG_NF    = (uint16_t)0x0004, /*!< Noise error flag */
+ USART_FLAG_FE    = (uint16_t)0x0002, /*!< Framing Error flag */
+ USART_FLAG_PE    = (uint16_t)0x0001, /*!< Parity Error flag */
+ USART_FLAG_SBK   = (uint16_t)0x0101  /*!< Send Break characters Flag */
+} USART_FLAG_TypeDef;
+
+#define IS_USART_FLAG(Flag) \
+  (((Flag) == USART_FLAG_TXE) || \
+   ((Flag) == USART_FLAG_TC)  || \
+   ((Flag) == USART_FLAG_RXNE) || \
+   ((Flag) == USART_FLAG_IDLE) || \
+   ((Flag) == USART_FLAG_OR) || \
+   ((Flag) == USART_FLAG_NF) || \
+   ((Flag) == USART_FLAG_FE) || \
+   ((Flag) == USART_FLAG_PE) || \
+   ((Flag) == USART_FLAG_SBK))
+   
+#define IS_USART_CLEAR_FLAG(Flag) (((Flag) == USART_FLAG_TC))
+   
+/**
+  * @}
+  */
+
+/** @defgroup USART_Interrupts
+  * @{
+  */
+    
+/**
+  * @brief USART Interrupt definition
+  * USART_IT possible values
+  * Elements values convention: 0x0ZYX
+  *   X: Position of the corresponding Interrupt
+  *   Y: Flag position
+  *   Z: Register index
+  */
+typedef enum 
+{ 
+  USART_IT_TXE        = (uint16_t)0x0277, /*!< Transmit interrupt */
+  USART_IT_TC         = (uint16_t)0x0266, /*!< Transmission Complete interrupt */
+  USART_IT_RXNE       = (uint16_t)0x0255, /*!< Receive interrupt */
+  USART_IT_IDLE       = (uint16_t)0x0244, /*!< IDLE line interrupt */
+  USART_IT_OR         = (uint16_t)0x0235, /*!< Overrun Error interrupt */
+  USART_IT_PE         = (uint16_t)0x0100, /*!< Parity Error interrupt */
+  USART_IT_ERR        = (uint16_t)0x0500, /*!< Error interrupt */
+  USART_IT_NF         = (uint16_t)0x0102, /*!< Noise Error interrupt */
+  USART_IT_FE         = (uint16_t)0x0101  /*!< Frame Error interrupt */
+} USART_IT_TypeDef;
+
+#define IS_USART_CONFIG_IT(Interrupt) \
+  (((Interrupt) == USART_IT_PE) || \
+   ((Interrupt) == USART_IT_TXE) || \
+   ((Interrupt) == USART_IT_TC) || \
+   ((Interrupt) == USART_IT_RXNE) || \
+   ((Interrupt) == USART_IT_OR) || \
+   ((Interrupt) == USART_IT_ERR) || \
+   ((Interrupt) == USART_IT_IDLE))
+
+#define IS_USART_GET_IT(ITPendingBit) \
+  (((ITPendingBit) == USART_IT_TXE)  || \
+   ((ITPendingBit) == USART_IT_TC)   || \
+   ((ITPendingBit) == USART_IT_RXNE) || \
+   ((ITPendingBit) == USART_IT_IDLE) || \
+   ((ITPendingBit) == USART_IT_OR)  || \
+   ((ITPendingBit) == USART_IT_PE))
+
+#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE))
+/**
+  * @}
+  */
+  
+/** @defgroup USART_Wakeup_Modes
+  * @{
+  */
+typedef enum
+{
+  USART_WakeUp_IdleLine       = (uint8_t)0x00, /*!< 0x01 Idle Line wake up */
+  USART_WakeUp_AddressMark    = (uint8_t)0x08  /*!< 0x02 Address Mark wake up */
+} USART_WakeUp_TypeDef;
+
+#define IS_USART_WAKEUP(WakeUpMode)(((WakeUpMode) == USART_WakeUp_IdleLine) || \
+                                    ((WakeUpMode) == USART_WakeUp_AddressMark))
+/**
+  * @}
+  */
+  
+/** @defgroup USART_Stop_Bits
+  * @{
+  */
+typedef enum
+{
+  USART_StopBits_1   = (uint8_t)0x00, /*!< One stop bit is transmitted at the end of frame*/
+  USART_StopBits_2   = (uint8_t)0x20, /*!< Two stop bits are transmitted at the end of frame*/
+  USART_StopBits_1_5 = (uint8_t)0x30  /*!< One and half stop bits*/
+} USART_StopBits_TypeDef;
+
+#define IS_USART_STOPBITS(StopBit)(((StopBit) == USART_StopBits_1) || \
+                                   ((StopBit) == USART_StopBits_1_5) || \
+                                   ((StopBit) == USART_StopBits_2))
+/**
+  * @}
+  */
+  
+/** @defgroup USART_Parity
+  * @{
+  */
+typedef enum
+{
+  USART_Parity_No    = (uint8_t)0x00,      /*!< No Parity*/
+  USART_Parity_Even  = (uint8_t)0x04,      /*!< Even Parity*/
+  USART_Parity_Odd   = (uint8_t)0x06       /*!< Odd Parity*/
+} USART_Parity_TypeDef;
+
+#define IS_USART_PARITY(Parity)(((Parity) == USART_Parity_No)   || \
+                                ((Parity) == USART_Parity_Even) || \
+                                ((Parity) == USART_Parity_Odd ))
+/**
+  * @}
+  */
+  
+/** @defgroup USART_Lin_Break_Detection_Length 
+  * @{
+  */
+typedef enum
+{
+  USART_LINBreakDetectionLength_10BITS = (uint8_t)0x00, /*!< 10 bits Lin Break detection */
+  USART_LINBreakDetectionLength_11BITS = (uint8_t)0x01  /*!< 11 bits Lin Break detection */
+} USART_LINBreakDetectionLength_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @defgroup USART_Word_Length 
+  * @{
+  */
+typedef enum
+{
+  USART_WordLength_8b = (uint8_t)0x00,  /*!< 8 bits Data */
+  USART_WordLength_9b = (uint8_t)0x10   /*!< 9 bits Data */
+} USART_WordLength_TypeDef;
+
+#define IS_USART_WORDLENGTH(WordLength) (((WordLength) == USART_WordLength_8b) || \
+                                         ((WordLength) == USART_WordLength_9b))
+   
+/**
+  * @}
+  */
+  
+/** @defgroup USART_Mode 
+  * @{
+  */
+typedef enum
+{
+  USART_Mode_Rx    = (uint8_t)0x04,  /*!< Receive Enable */
+  USART_Mode_Tx    = (uint8_t)0x08   /*!< Transmit Enable */
+} USART_Mode_TypeDef;
+
+#define IS_USART_MODE(MODE) ((((MODE) & (uint8_t)0xF3) == 0x00) && ((MODE) != (uint16_t)0x00))
+/**
+  * @}
+  */
+  
+/** @defgroup USART_DMA_Requests 
+  * @{
+  */
+typedef enum
+{
+  USART_DMAReq_TX    = (uint8_t)0x80,  /*!< Receive DMA request Enable */
+  USART_DMAReq_RX    = (uint8_t)0x40   /*!< Transmit DMA request Enable */
+} USART_DMAReq_TypeDef;
+
+#define IS_USART_DMAREQ(DMAReq) ((((DMAReq) & (uint8_t)0x3F) == 0x00) && ((DMAReq) != (uint8_t)0x00))
+/**
+  * @}
+  */
+  
+/** @defgroup USART_IrDA_Mode 
+  * @{
+  */
+typedef enum
+{
+  USART_IrDAMode_Normal    = (uint8_t)0x00, /*!< IrDA Normal Mode   */
+  USART_IrDAMode_LowPower  = (uint8_t)0x01  /*!< IrDA Low Power Mode */
+} USART_IrDAMode_TypeDef;
+
+#define IS_USART_IRDAMODE(IrDAMode) (((IrDAMode) == USART_IrDAMode_LowPower) || \
+                                     ((IrDAMode) == USART_IrDAMode_Normal))
+/**
+  * @}
+  */
+  
+/** @defgroup USART_Clock 
+  * @{
+  */
+typedef enum
+{
+  USART_Clock_Disable    = (uint8_t)0x00,  /*!< CK pin disabled */
+  USART_Clock_Enable     = (uint8_t)0x08   /*!< CK pin enabled */
+} USART_Clock_TypeDef;
+
+#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) ||((CLOCK) == USART_Clock_Enable))
+/**
+  * @}
+  */
+  
+/** @defgroup USART_Clock_Polarity 
+  * @{
+  */
+typedef enum
+{
+  USART_CPOL_Low      = (uint8_t)0x00,  /*!< CK to 0 when idle */
+  USART_CPOL_High     = (uint8_t)0x04   /*!< CK to 1 when idle.*/
+} USART_CPOL_TypeDef;
+
+#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))
+/**
+  * @}
+  */
+  
+/** @defgroup USART_Clock_Phase 
+  * @{
+  */
+typedef enum
+{
+  USART_CPHA_1Edge     = (uint8_t)0x00,  /*!< The first clock transition is the first data capture edge*/
+  USART_CPHA_2Edge     = (uint8_t)0x02   /*!< The second clock transition is the first data capture edge*/
+} USART_CPHA_TypeDef;
+
+#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge))
+/**
+  * @}
+  */
+  
+/** @defgroup USART_LastBit 
+  * @{
+  */
+typedef enum
+{
+  USART_LastBit_Disable  = (uint8_t)0x00,  /*!< The clock pulse of the last data bit is not output to the SCLK pin.*/
+  USART_LastBit_Enable   = (uint8_t)0x01   /*!< The clock pulse of the last data bit is output to the SCLK pin.*/
+} USART_LastBit_TypeDef;
+
+#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \
+                                   ((LASTBIT) == USART_LastBit_Enable))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/* Exported constants --------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroupUSART_Exported_Macros
+  * @{
+  */
+/* BaudRate value should be < 625000 bps */
+#define IS_USART_BAUDRATE(NUM) ((NUM) <= (uint32_t)625000)
+
+#define USART_ADDRESS_MAX ((uint8_t)16)
+#define IS_USART_ADDRESS(address) ((address) < USART_ADDRESS_MAX)
+
+#define USART_DATA_9BITS_MAX ((uint16_t)0x1FF)
+#define IS_USART_DATA_9BITS(DATA) ((DATA) < USART_DATA_9BITS_MAX)
+
+/**
+  * @}
+  */
+
+/* Exported functions ------------------------------------------------------- */
+	
+/*  Function used to set the USART configuration to the default reset state ***/ 
+void USART_DeInit(USART_TypeDef* USARTx);
+
+/* Initialization and Configuration functions *********************************/
+void USART_Init(USART_TypeDef* USARTx, uint32_t BaudRate, USART_WordLength_TypeDef
+                USART_WordLength, USART_StopBits_TypeDef USART_StopBits,
+                USART_Parity_TypeDef USART_Parity, USART_Mode_TypeDef USART_Mode);
+void USART_ClockInit(USART_TypeDef* USARTx, USART_Clock_TypeDef USART_Clock,
+                     USART_CPOL_TypeDef USART_CPOL, USART_CPHA_TypeDef USART_CPHA,
+                     USART_LastBit_TypeDef USART_LastBit);
+void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler);
+void USART_SendBreak(USART_TypeDef* USARTx);
+
+/* Data transfers functions ***************************************************/ 
+void USART_SendData8(USART_TypeDef* USARTx, uint8_t Data);
+void USART_SendData9(USART_TypeDef* USARTx, uint16_t Data);
+uint8_t USART_ReceiveData8(USART_TypeDef* USARTx);
+uint16_t USART_ReceiveData9(USART_TypeDef* USARTx);
+
+/* Multi-Processor Communication functions ************************************/
+void USART_WakeUpConfig(USART_TypeDef* USARTx, USART_WakeUp_TypeDef USART_WakeUp);
+void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address);
+
+/* Half-duplex mode function **************************************************/
+void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+
+/* Smartcard mode functions ***************************************************/
+void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime);
+
+/* IrDA mode functions ********************************************************/
+void USART_IrDAConfig(USART_TypeDef* USARTx, USART_IrDAMode_TypeDef USART_IrDAMode);
+void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState);
+
+/* DMA transfers management functions *****************************************/
+void USART_DMACmd(USART_TypeDef* USARTx, USART_DMAReq_TypeDef USART_DMAReq,
+                  FunctionalState NewState);
+
+/* Interrupts and flags management functions **********************************/
+void USART_ITConfig(USART_TypeDef* USARTx, USART_IT_TypeDef USART_IT,
+                    FunctionalState NewState);
+FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, USART_FLAG_TypeDef USART_FLAG);
+void USART_ClearFlag(USART_TypeDef* USARTx, USART_FLAG_TypeDef USART_FLAG);
+ITStatus USART_GetITStatus(USART_TypeDef* USARTx, USART_IT_TypeDef USART_IT);
+void USART_ClearITPendingBit(USART_TypeDef* USARTx, USART_IT_TypeDef USART_IT);
+
+
+
+#endif /* __STM8L15x_USART_H */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_wfe.h b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_wfe.h
new file mode 100755
index 0000000..687a1c7
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_wfe.h
@@ -0,0 +1,151 @@
+/**
+  ******************************************************************************
+  * @file    stm8l15x_wfe.h
+  * @author  MCD Application Team
+  * @version V1.6.0
+  * @date    28-June-2013
+  * @brief   This file contains all the functions prototypes for the WFE firmware
+  *          library.
+  ******************************************************************************
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ****************************************************************************** 
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM8L15x_WFE_H
+#define __STM8L15x_WFE_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm8l15x.h"
+
+/** @addtogroup STM8L15x_StdPeriph_Driver
+  * @{
+  */
+  
+/** @addtogroup WFE
+  * @{
+  */ 
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup WFE_Exported_Types
+  * @{
+  */
+/** @defgroup WFE_Sources
+  * @brief Signal Sources to generate wake_up events
+@verbatim    
+  Elements values convention: 0xXXYY
+    X = SRx registers index
+        XX = 01 : CR1
+        XX = 02 : CR2
+        XX = 03 : CR3
+        XX = 04 : CR4
+    YY = flag mask in the dedicated register(XX register)
+@endverbatim
+  * @{
+  */
+typedef enum {
+  WFE_Source_TIM2_EV0     = (uint16_t)0x0101, /*!< TIM2 Update/Trigger and Break interrupt */
+  WFE_Source_TIM2_EV1     = (uint16_t)0x0102, /*!< TIM2 Capture/Compare interrupt          */
+  WFE_Source_TIM1_EV0     = (uint16_t)0x0104, /*!< TIM1 Update/Trigger and Break interrupt */
+  WFE_Source_TIM1_EV1     = (uint16_t)0x0108, /*!< TIM1 Capture/Compare interrupt          */
+  WFE_Source_EXTI_EV0     = (uint16_t)0x0110, /*!< I/O port interrupt from Pins 0          */
+  WFE_Source_EXTI_EV1     = (uint16_t)0x0120, /*!< I/O port interrupt from Pins 1          */
+  WFE_Source_EXTI_EV2     = (uint16_t)0x0140, /*!< I/O port interrupt from Pins 2          */
+  WFE_Source_EXTI_EV3     = (uint16_t)0x0180, /*!< I/O port interrupt from Pins 3          */
+  WFE_Source_EXTI_EV4     = (uint16_t)0x0201, /*!< I/O port interrupt from Pins 4          */
+  WFE_Source_EXTI_EV5     = (uint16_t)0x0202, /*!< I/O port interrupt from Pins 5          */
+  WFE_Source_EXTI_EV6     = (uint16_t)0x0204, /*!< I/O port interrupt from Pins 6          */
+  WFE_Source_EXTI_EV7     = (uint16_t)0x0208, /*!< I/O port interrupt from Pins 7          */
+  WFE_Source_EXTI_EVB_G   = (uint16_t)0x0210, /*!< I/O port interrupt from port B and G    */
+  WFE_Source_EXTI_EVD_H   = (uint16_t)0x0220, /*!< I/O port interrupt from Port D and H    */
+  WFE_Source_EXTI_EVE_F   = (uint16_t)0x0240, /*!< I/O port interrupt from Port E and F    */
+  WFE_Source_ADC1_COMP_EV = (uint16_t)0x0280, /*!< ADC1, COMP1 and COMP2 interrupts        */
+  WFE_Source_TIM3_EV0     = (uint16_t)0x0301, /*!< TIM3 Update/Trigger and Break interrupt */
+  WFE_Source_TIM3_EV1     = (uint16_t)0x0302, /*!< TIM3 Capture/Compare interrupt          */
+  WFE_Source_TIM4_EV      = (uint16_t)0x0304, /*!< TIM4 Update and Trigger interrupt       */
+  WFE_Source_SPI1_EV      = (uint16_t)0x0308, /*!< SPI1 Rx and Tx interrupt                */
+  WFE_Source_I2C1_EV      = (uint16_t)0x0310, /*!< I2C1 Rx and Tx interrupt                */
+  WFE_Source_USART1_EV    = (uint16_t)0x0320, /*!< USART1 Rx and Tx interrupt              */
+  WFE_Source_DMA1CH01_EV  = (uint16_t)0x0340, /*!< DMA1 channel 0 and  1 interrupt         */
+  WFE_Source_DMA1CH23_EV  = (uint16_t)0x0380,  /*!< DMA1 channel 2 and  3  interrupt        */
+  WFE_Source_RTC_CSS_EV   = (uint16_t)0x0401,  /*!< RTC or CSS on LSE event */
+  WFE_Source_SPI2_EV      = (uint16_t)0x0402,  /*!< SPI2 Rx and Tx interrupt */
+  WFE_Source_USART2_EV    = (uint16_t)0x0404,  /*!< USART2 Rx and Tx interrupt */
+  WFE_Source_USART3_EV    = (uint16_t)0x0408,  /*!< USART3 Rx and Tx interrupt */
+  WFE_Source_TIM5_EV0     = (uint16_t)0x0410,  /*!< TIM5 Update/Trigger and Break interrupt */
+  WFE_Source_TIM5_EV1     = (uint16_t)0x0420,  /*!< TIM5 Capture/Compare interrupt */
+  WFE_Source_AES_EV       = (uint16_t)0x0440   /*!< AES interrupt */
+} WFE_Source_TypeDef;
+
+#define IS_WFE_SOURCE(Source) (((Source) == WFE_Source_TIM2_EV0) || \
+                               ((Source) == WFE_Source_TIM2_EV1) || \
+                               ((Source) == WFE_Source_TIM1_EV0) || \
+                               ((Source) == WFE_Source_TIM1_EV1) || \
+                               ((Source) == WFE_Source_EXTI_EV0) || \
+                               ((Source) == WFE_Source_EXTI_EV1) || \
+                               ((Source) == WFE_Source_EXTI_EV2) || \
+                               ((Source) == WFE_Source_EXTI_EV3) || \
+                               ((Source) == WFE_Source_EXTI_EV4) || \
+                               ((Source) == WFE_Source_EXTI_EV5) || \
+                               ((Source) == WFE_Source_EXTI_EV6) || \
+                               ((Source) == WFE_Source_EXTI_EV7) || \
+                               ((Source) == WFE_Source_EXTI_EVB_G) || \
+                               ((Source) == WFE_Source_EXTI_EVD_H) || \
+                               ((Source) == WFE_Source_EXTI_EVE_F) || \
+                               ((Source) == WFE_Source_ADC1_COMP_EV) || \
+                               ((Source) == WFE_Source_TIM3_EV0) || \
+                               ((Source) == WFE_Source_TIM3_EV1) || \
+                               ((Source) == WFE_Source_TIM4_EV) || \
+                               ((Source) == WFE_Source_SPI1_EV) || \
+                               ((Source) == WFE_Source_I2C1_EV) || \
+                               ((Source) == WFE_Source_USART1_EV) || \
+                               ((Source) == WFE_Source_DMA1CH01_EV) || \
+                               ((Source) == WFE_Source_AES_EV) || \
+                               ((Source) == WFE_Source_TIM5_EV1) || \
+                               ((Source) == WFE_Source_TIM5_EV0) || \
+                               ((Source) == WFE_Source_USART3_EV) || \
+                               ((Source) == WFE_Source_USART2_EV) || \
+                               ((Source) == WFE_Source_SPI2_EV) || \
+                               ((Source) == WFE_Source_RTC_CSS_EV) || \
+                               ((Source) == WFE_Source_DMA1CH23_EV))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Exported constants --------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+/* Function used to set the WFE configuration to the default reset state ******/ 
+void WFE_DeInit(void);
+
+/* WFE Source configuration and management functions **************************/ 
+void WFE_WakeUpSourceEventCmd(WFE_Source_TypeDef WFE_Source, FunctionalState NewState);
+FunctionalState WFE_GetWakeUpSourceEventStatus(WFE_Source_TypeDef WFE_Source);
+
+#endif /* __STM8L15x_WFE_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_wwdg.h b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_wwdg.h
new file mode 100755
index 0000000..f963bcc
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/inc/stm8l15x_wwdg.h
@@ -0,0 +1,93 @@
+/**
+  ******************************************************************************
+  * @file    stm8l15x_wwdg.h
+  * @author  MCD Application Team
+  * @version V1.6.0
+  * @date    28-June-2013
+  * @brief   This file contains all the functions prototypes for the WWDG firmware
+  *          library.
+  ******************************************************************************
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ****************************************************************************** 
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM8L15x_WWDG_H
+#define __STM8L15x_WWDG_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm8l15x.h"
+
+/** @addtogroup STM8L15x_StdPeriph_Driver
+  * @{
+  */
+  
+/** @addtogroup WWDG
+  * @{
+  */ 
+  
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup  WWDG_Exported_Macros
+  * @{
+  */
+
+/** @defgroup WWDG_WindowLimitValue 
+  * @{
+  */ 
+#define IS_WWDG_WINDOW_LIMIT_VALUE(WindowLimitValue) ((WindowLimitValue) <= 0x7F)
+
+/**
+  * @}
+  */
+
+/** @defgroup WWDG_CounterValue 
+  * @{
+  */
+#define IS_WWDG_COUNTER_VALUE(CounterValue) ((CounterValue) <= 0x7F)
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+
+/* Exported functions ------------------------------------------------------- */
+/* Refresh window and Counter configuration functions *************************/
+void WWDG_Init(uint8_t Counter, uint8_t WindowValue);
+void WWDG_SetWindowValue(uint8_t WindowValue);
+void WWDG_SetCounter(uint8_t Counter);
+
+/* WWDG activation function ***************************************************/
+void WWDG_Enable(uint8_t Counter);
+
+/* WWDG counter and software reset management **********************************/
+uint8_t WWDG_GetCounter(void);
+void WWDG_SWReset(void);
+
+
+#endif /* __STM8L15x_WWDG_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
\ No newline at end of file
diff --git a/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_adc.c b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_adc.c
new file mode 100755
index 0000000..ec0348d
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_adc.c
@@ -0,0 +1,985 @@
+/**
+  ******************************************************************************
+  * @file    stm8l15x_adc.c
+  * @author  MCD Application Team
+  * @version V1.6.0
+  * @date    28-June-2013
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Analog to Digital Convertor (ADC) peripheral:           
+  *           - Initialization and Configuration
+  *           - Power saving
+  *           - Analog Watchdog configuration              
+  *           - Temperature Sensor & Vrefint (Voltage Reference internal) management 
+  *           - Regular Channels Configuration
+  *           - Regular Channels DMA Configuration
+  *           - Injected channels Configuration      
+  *           - Interrupts and flags management       
+  *         
+  *  @verbatim
+  *                               
+  *          ===================================================================      
+  *                                   How to use this driver
+  *          ===================================================================      
+  *          1. Enable The ADC controller clock using CLK_PeripheralClockConfig() 
+  *            function : CLK_PeripheralClockConfig(CLK_Peripheral_ADC1, ENABLE).
+  *
+  *            2. Configure the ADC Prescaler, conversion resolution and data 
+  *              alignment using the ADC_Init() function.
+  * 
+  *            3. Activate the ADC peripheral using ADC_Cmd() function.  
+  *
+  *          Regular channels group configuration
+  *          ====================================    
+  *            - To configure the ADC regular channels group features, use 
+  *              ADC_Init() and ADC_RegularChannelConfig() functions.
+  *            - To activate the continuous mode, use the ADC_continuousModeCmd()
+  *              function.
+  *            - To configure and activate the Discontinuous mode, use the 
+  *              ADC_DiscModeChannelCountConfig() and ADC_DiscModeCmd() functions.        
+  *            - To read the ADC converted values, use the ADC_GetConversionValue()
+  *              function.
+  *
+  *          DMA for Regular channels group features configuration
+  *          ====================================================== 
+  *           - To enable the DMA mode for regular channels group, use the 
+  *             ADC_DMACmd() function.
+  *           - To enable the generation of DMA requests continuously at the end
+  *             of the last DMA transfer, use the ADC_DMARequestAfterLastTransferCmd() 
+  *             function.    
+             
+  *          Injected channels group configuration
+  *          =====================================    
+  *            - To configure the ADC Injected channels group features, use 
+  *              ADC_InjectedChannelConfig() and  ADC_InjectedSequencerLengthConfig()
+  *              functions.
+  *            - To activate the continuous mode, use the ADC_continuousModeCmd()
+  *              function.
+  *            - To activate the Injected Discontinuous mode, use the 
+  *              ADC_InjectedDiscModeCmd() function.  
+  *            - To activate the AutoInjected mode, use the ADC_AutoInjectedConvCmd() 
+  *              function.        
+  *            - To read the ADC converted values, use the ADC_GetInjectedConversionValue() 
+  *              function.
+  *              
+  *  @endverbatim
+  *         
+  ******************************************************************************
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ****************************************************************************** 
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm8l15x_adc.h"
+
+/** @addtogroup STM8L15x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup ADC 
+  * @brief ADC driver modules
+  * @{
+  */ 
+  
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup ADC_Private_Functions
+  * @{
+  */ 
+    
+    
+/** @defgroup ADC_Group1 Initialization and Configuration functions
+ *  @brief   Initialization and Configuration functions 
+ *
+@verbatim    
+ ===============================================================================
+                      Initialization and Configuration functions
+ ===============================================================================  
+  This section provides functions allowing to:
+   - Enable or disable the ADC peripheral,
+   - Initialize and configure the ADC Prescaler, ADC Conversion Resolution 
+     (12bit..6bit), ADC Continuous Conversion Mode (Continuous or Single 
+     conversion),
+   - Configure External trigger Sensitivity and source,
+   - Start ADC conversion, by software trigger.
+
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Deinitializes the ADC peripheral registers to their default reset 
+  *         values.
+  * @param  ADCx where x can be 1 to select the specified ADC peripheral.
+  * @retval None
+  */
+void ADC_DeInit(ADC_TypeDef* ADCx)
+{
+  /*  Set the Configuration registers to their reset values */
+  ADCx->CR1 =  ADC_CR1_RESET_VALUE;
+  ADCx->CR2 =  ADC_CR2_RESET_VALUE;
+  ADCx->CR3 =  ADC_CR3_RESET_VALUE;
+
+  /*  Set the status registers to their reset values */
+  ADCx->SR =  (uint8_t)~ADC_SR_RESET_VALUE;
+
+  /*  Set the High threshold registers to their reset values */
+  ADCx->HTRH =  ADC_HTRH_RESET_VALUE;
+  ADCx->HTRL =  ADC_HTRL_RESET_VALUE;
+
+  /*  Set the low threshold registers to their reset values */
+  ADCx->LTRH =  ADC_LTRH_RESET_VALUE;
+  ADCx->LTRL =  ADC_LTRL_RESET_VALUE;
+
+  /*  Set the channels sequence registers to their reset values */
+  ADCx->SQR[0] =  ADC_SQR1_RESET_VALUE;
+  ADCx->SQR[1] =  ADC_SQR2_RESET_VALUE;
+  ADCx->SQR[2] =  ADC_SQR3_RESET_VALUE;
+  ADCx->SQR[3] =  ADC_SQR4_RESET_VALUE;
+
+  /*  Set the channels Trigger registers to their reset values */
+  ADCx->TRIGR[0] =  ADC_TRIGR1_RESET_VALUE;
+  ADCx->TRIGR[1] =  ADC_TRIGR2_RESET_VALUE;
+  ADCx->TRIGR[2] =  ADC_TRIGR3_RESET_VALUE;
+  ADCx->TRIGR[3] =  ADC_TRIGR4_RESET_VALUE;
+}
+
+/**
+  * @brief  Initializes the specified ADC peripheral according to the specified 
+  *         parameters.
+  * @param  ADCx where x can be 1 to select the specified ADC peripheral.
+  * @param  ADC_ConversionMode : specifies the ADC conversion mode,
+  *          This parameter can be one of the following values:
+  *            @arg ADC_ConversionMode_Single: Single Conversion Mode
+  *            @arg ADC_ConversionMode_Continuous: Continuous Conversion Mode
+  * @param  ADC_Resolution : specifies the ADC Data resolution,
+  *          This parameter can be one of the following values:
+  *            @arg ADC_Resolution_12Bit: 12 bit resolution
+  *            @arg ADC_Resolution_10Bit: 10 bit resolution
+  *            @arg ADC_Resolution_8Bit: 8 bit resolution
+  *            @arg ADC_Resolution_6Bit: 6 bit resolution      
+  * @param  ADC_Prescaler : specifies the ADC Prescaler,
+  *          This parameter can be one of the following values:
+  *            @arg ADC_Prescaler_1: ADC Clock frequency is divided by 1
+  *            @arg ADC_Prescaler_2: ADC Clock frequency is divided by 2
+  * @retval None
+  */
+void ADC_Init(ADC_TypeDef* ADCx,
+              ADC_ConversionMode_TypeDef ADC_ConversionMode,
+              ADC_Resolution_TypeDef ADC_Resolution,
+              ADC_Prescaler_TypeDef ADC_Prescaler)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_CONVERSION_MODE(ADC_ConversionMode));
+  assert_param(IS_ADC_RESOLUTION(ADC_Resolution));
+  assert_param(IS_ADC_PRESCALER(ADC_Prescaler));
+
+  /*clear CR1 register */
+  ADCx->CR1 &= (uint8_t)~(ADC_CR1_CONT | ADC_CR1_RES);
+
+  /* set the resolution and the conversion mode */
+  ADCx->CR1 |= (uint8_t)((uint8_t)ADC_ConversionMode | (uint8_t)ADC_Resolution);
+
+  /*clear CR2 register */
+  ADCx->CR2 &= (uint8_t)~(ADC_CR2_PRESC);
+
+  /* set the Prescaler */
+  ADCx->CR2 |= (uint8_t) ADC_Prescaler;
+}
+
+/**
+  * @brief  Enables or disables the selected ADC peripheral.
+  * @param  ADCx where x can be 1 to select the specified ADC peripheral.
+  * @param  NewState : new state of the specified ADC peripheral.
+    *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_Cmd(ADC_TypeDef* ADCx,
+             FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Set the ADON bit to wake up the specified ADC from power down mode */
+    ADCx->CR1 |= ADC_CR1_ADON;
+  }
+  else
+  {
+    /* Disable the selected ADC peripheral */
+    ADCx->CR1 &= (uint8_t)~ADC_CR1_ADON;
+  }
+}
+
+/**
+  * @brief  Starts ADC conversion, by software trigger.
+  * @param  ADCx where x can be 1 to select the specified ADC peripheral.
+  * @retval None
+  */
+void ADC_SoftwareStartConv(ADC_TypeDef* ADCx)
+{
+  /*  Start the ADC software conversion */
+  ADCx->CR1 |= ADC_CR1_START;
+}
+
+/**
+  * @brief  Configures the ADC conversion through external trigger.
+  * @param  ADCx where x can be 1 to select the specified ADC peripheral.
+  * @param  ADC_ExtEventSelection : Specifies the external trigger.
+  *          This parameter can be one of the following values:
+  *            @arg ADC_ExtEventSelection_None: Conversion starts only by software start
+  *            @arg ADC_ExtEventSelection_Trigger1: Trigger 1  Enables conversion
+  *            @arg ADC_ExtEventSelection_Trigger2: Trigger 2  Enables conversion
+  *            @arg ADC_ExtEventSelection_Trigger3: Trigger 3  Enables conversion      
+  * @param  ADC_ExtTRGSensitivity : Specifies the external trigger sensitivity.
+  *          This parameter can be one of the following values:
+  *            @arg ADC_ExtTRGSensitivity_Rising: External Trigger Sensitivity is Rising Edge
+  *            @arg ADC_ExtTRGSensitivity_Falling: External Trigger Sensitivity is Falling Edge
+  *            @arg ADC_ExtTRGSensitivity_All: External Trigger Sensitivity is Falling and Rising Edge
+  * @retval None
+  */
+void ADC_ExternalTrigConfig(ADC_TypeDef* ADCx,
+                            ADC_ExtEventSelection_TypeDef ADC_ExtEventSelection,
+                            ADC_ExtTRGSensitivity_TypeDef ADC_ExtTRGSensitivity)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_EXT_EVENT_SELECTION(ADC_ExtEventSelection));
+  assert_param(IS_ADC_EXT_TRG_SENSITIVITY(ADC_ExtTRGSensitivity));
+
+  /*clear old configuration of CR2 register */
+  ADCx->CR2 &= (uint8_t)~(ADC_CR2_TRIGEDGE | ADC_CR2_EXTSEL);
+
+  /* set the External Trigger Edge Sensitivity  and the external event 
+     selection */
+  ADCx->CR2 |= (uint8_t)( (uint8_t)ADC_ExtTRGSensitivity | \
+                          (uint8_t)ADC_ExtEventSelection);
+}
+
+ /**
+  * @}
+  */
+
+/** @defgroup ADC_Group2 Analog Watchdog configuration functions
+ *  @brief   Analog Watchdog configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+                    Analog Watchdog configuration functions
+ ===============================================================================  
+
+  This section provides functions allowing to configure the Analog Watchdog
+  (AWD) feature in the ADC.
+  
+  A typical configuration Analog Watchdog is done following these steps :
+   1. the ADC guarded channel is selected using the 
+      ADC_AnalogWatchdogChannelSelect() function.
+   2. The Analog watchdog lower and higher threshold are configured using the  
+      ADC_AnalogWatchdogThresholdsConfig() function.
+   
+   Note : Both AWD selection and thresholds can be configured with one unique 
+          function ADC_AnalogWatchdogConfig(), which is kept for firmware 
+          compatibility reason.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Configures the channel to be checked by the Analog watchdog.
+  * @param  ADCx where x can be 1 to select the specified ADC peripheral.
+  * @param  ADC_AnalogWatchdogSelection : Specifies the channel to be checked 
+  *         by the Analog watchdog.
+  *          This parameter can be one of the following values:
+  *            @arg ADC_AnalogWatchdogSelection_Channel0: AWD affected to Channel 0
+  *            @arg ADC_AnalogWatchdogSelection_Channel1: AWD affected to Channel 1
+  *            @arg ADC_AnalogWatchdogSelection_Channel2: AWD affected to Channel 2
+  *            @arg ADC_AnalogWatchdogSelection_Channel3: AWD affected to Channel 3
+  *            @arg ADC_AnalogWatchdogSelection_Channel4: AWD affected to Channel 4
+  *            @arg ADC_AnalogWatchdogSelection_Channel5: AWD affected to Channel 5
+  *            @arg ADC_AnalogWatchdogSelection_Channel6: AWD affected to Channel 6
+  *            @arg ADC_AnalogWatchdogSelection_Channel7: AWD affected to Channel 7
+  *            @arg ADC_AnalogWatchdogSelection_Channel8: AWD affected to Channel 8
+  *            @arg ADC_AnalogWatchdogSelection_Channel9: AWD affected to Channel 9
+  *            @arg ADC_AnalogWatchdogSelection_Channel10: AWD affected to Channel 10
+  *            @arg ADC_AnalogWatchdogSelection_Channel11: AWD affected to Channel 11
+  *            @arg ADC_AnalogWatchdogSelection_Channel12: AWD affected to Channel 12
+  *            @arg ADC_AnalogWatchdogSelection_Channel13: AWD affected to Channel 13
+  *            @arg ADC_AnalogWatchdogSelection_Channel14: AWD affected to Channel 14
+  *            @arg ADC_AnalogWatchdogSelection_Channel15: AWD affected to Channel 15
+  *            @arg ADC_AnalogWatchdogSelection_Channel16: AWD affected to Channel 16
+  *            @arg ADC_AnalogWatchdogSelection_Channel17: AWD affected to Channel 17
+  *            @arg ADC_AnalogWatchdogSelection_Channel18: AWD affected to Channel 18
+  *            @arg ADC_AnalogWatchdogSelection_Channel19: AWD affected to Channel 19
+  *            @arg ADC_AnalogWatchdogSelection_Channel20: AWD affected to Channel 20
+  *            @arg ADC_AnalogWatchdogSelection_Channel21: AWD affected to Channel 21
+  *            @arg ADC_AnalogWatchdogSelection_Channel22: AWD affected to Channel 22
+  *            @arg ADC_AnalogWatchdogSelection_Channel23: AWD affected to Channel 23
+  *         @ref ADC_AnalogWatchdogSelection_TypeDef enumeration.
+  * @retval None
+  */
+void ADC_AnalogWatchdogChannelSelect(ADC_TypeDef* ADCx,
+                                     ADC_AnalogWatchdogSelection_TypeDef ADC_AnalogWatchdogSelection)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ANALOGWATCHDOG_SELECTION(ADC_AnalogWatchdogSelection));
+
+  /* Reset the CHSEL bits */
+  ADCx->CR3 &= ((uint8_t)~ADC_CR3_CHSEL);
+
+  /* Select the channel to be checked by the Analog watchdog */
+  ADCx->CR3 |= (uint8_t)ADC_AnalogWatchdogSelection;
+}
+
+/**
+  * @brief  Configures the high and low thresholds of the Analog watchdog.
+  * @param  ADCx where x can be 1 to select the specified ADC peripheral.
+  * @param  HighThreshold: Analog watchdog High threshold value.
+    *       This parameter must be a 12bit value.
+  * @param  LowThreshold: Analog watchdog Low threshold value.
+    *       This parameter must be a 12bit value.
+  * @retval None
+  */
+void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, uint16_t LowThreshold)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_THRESHOLD(HighThreshold));
+  assert_param(IS_ADC_THRESHOLD(LowThreshold));
+
+  /* Set the ADC high threshold */
+  ADCx->HTRH = (uint8_t)(HighThreshold >> 8);
+  ADCx->HTRL = (uint8_t)(HighThreshold);
+
+  /* Set the ADC low threshold */
+  ADCx->LTRH = (uint8_t)(LowThreshold >> 8);
+  ADCx->LTRL = (uint8_t)(LowThreshold);
+}
+
+/**
+  * @brief  Configures the Analog watchdog.
+  * @param  ADCx where x can be 1 to select the specified ADC peripheral.
+  * @param  ADC_AnalogWatchdogSelection : Specifies the channel to be checked 
+  *         by the Analog watchdog.
+  *          This parameter can be one of the following values:
+  *            @arg ADC_AnalogWatchdogSelection_Channel0: AWD affected to Channel 0
+  *            @arg ADC_AnalogWatchdogSelection_Channel1: AWD affected to Channel 1
+  *            @arg ADC_AnalogWatchdogSelection_Channel2: AWD affected to Channel 2
+  *            @arg ADC_AnalogWatchdogSelection_Channel3: AWD affected to Channel 3
+  *            @arg ADC_AnalogWatchdogSelection_Channel4: AWD affected to Channel 4
+  *            @arg ADC_AnalogWatchdogSelection_Channel5: AWD affected to Channel 5
+  *            @arg ADC_AnalogWatchdogSelection_Channel6: AWD affected to Channel 6
+  *            @arg ADC_AnalogWatchdogSelection_Channel7: AWD affected to Channel 7
+  *            @arg ADC_AnalogWatchdogSelection_Channel8: AWD affected to Channel 8
+  *            @arg ADC_AnalogWatchdogSelection_Channel9: AWD affected to Channel 9
+  *            @arg ADC_AnalogWatchdogSelection_Channel10: AWD affected to Channel 10
+  *            @arg ADC_AnalogWatchdogSelection_Channel11: AWD affected to Channel 11
+  *            @arg ADC_AnalogWatchdogSelection_Channel12: AWD affected to Channel 12
+  *            @arg ADC_AnalogWatchdogSelection_Channel13: AWD affected to Channel 13
+  *            @arg ADC_AnalogWatchdogSelection_Channel14: AWD affected to Channel 14
+  *            @arg ADC_AnalogWatchdogSelection_Channel15: AWD affected to Channel 15
+  *            @arg ADC_AnalogWatchdogSelection_Channel16: AWD affected to Channel 16
+  *            @arg ADC_AnalogWatchdogSelection_Channel17: AWD affected to Channel 17
+  *            @arg ADC_AnalogWatchdogSelection_Channel18: AWD affected to Channel 18
+  *            @arg ADC_AnalogWatchdogSelection_Channel19: AWD affected to Channel 19
+  *            @arg ADC_AnalogWatchdogSelection_Channel20: AWD affected to Channel 20
+  *            @arg ADC_AnalogWatchdogSelection_Channel21: AWD affected to Channel 21
+  *            @arg ADC_AnalogWatchdogSelection_Channel22: AWD affected to Channel 22
+  *            @arg ADC_AnalogWatchdogSelection_Channel23: AWD affected to Channel 23  
+  * @param  HighThreshold: Analog watchdog High threshold value.
+    *       This parameter must be a 12bit value.
+  * @param  LowThreshold: Analog watchdog Low threshold value.
+    *       This parameter must be a 12bit value.
+  * @retval None
+  */
+void ADC_AnalogWatchdogConfig(ADC_TypeDef* ADCx,
+                              ADC_AnalogWatchdogSelection_TypeDef ADC_AnalogWatchdogSelection,
+                              uint16_t HighThreshold,
+                              uint16_t LowThreshold)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ANALOGWATCHDOG_SELECTION(ADC_AnalogWatchdogSelection));
+  assert_param(IS_ADC_THRESHOLD(HighThreshold));
+  assert_param(IS_ADC_THRESHOLD(LowThreshold));
+
+  /*Reset the CHSEL bits */
+  ADCx->CR3 &= ((uint8_t)~ADC_CR3_CHSEL);
+
+  /* Select the channel to be checked by the Analog watchdog.*/
+  ADCx->CR3 |= (uint8_t)ADC_AnalogWatchdogSelection;
+
+  /* Set the ADC high threshold */
+  ADCx->HTRH = (uint8_t)(HighThreshold >> 8);
+  ADCx->HTRL = (uint8_t)(HighThreshold);
+
+  /* Set the ADC low threshold */
+  ADCx->LTRH = (uint8_t)(LowThreshold >> 8);
+  ADCx->LTRL = (uint8_t)LowThreshold;
+}
+
+ /**
+  * @}
+  */
+
+/** @defgroup ADC_Group3 Temperature Sensor & Vrefint (Voltage Reference 
+ *            internal) management functions
+ *  @brief   Temperature Sensor & Vrefint (Voltage Reference internal) 
+ *            management functions 
+ *
+@verbatim   
+ ===============================================================================
+  Temperature Sensor & Vrefint (Voltage Reference internal) management functions
+ ===============================================================================  
+
+  This section provides functions allowing to enable/ disable the internal 
+  connections between the ADC and the Temperature Sensor and the Vrefint source.
+     
+  A typical configuration to get the Temperature sensor or/and Vrefint channels 
+  voltages is done following these steps :
+   1. Enable the internal connection of Temperature sensor or/and Vrefint sources 
+      with the ADC channels: 
+      - for the Temperature sensor using ADC_TempSensorCmd() function.
+      - for the Internal Voltage reference using ADC_VrefintCmd() function. 
+   2. Enable the ADC_Channel_TempSensor and/or ADC_Channel_Vrefint channels 
+      using ADC_ChannelCmd()function. 
+   3. Get the voltage values, using ADC_GetConversionValue().
+ 
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Enables or disables the Temperature sensor internal reference.
+  * @param  NewState : new state of the Temperature sensor internal reference.
+    *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_TempSensorCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /*Enable the Temperature sensor internal reference.*/
+    ADC1->TRIGR[0] |= (uint8_t)(ADC_TRIGR1_TSON);
+  }
+  else
+  {
+    /*Disable the Temperature sensor internal reference.*/
+    ADC1->TRIGR[0] &= (uint8_t)(~ADC_TRIGR1_TSON);
+  }
+}
+
+/**
+  * @brief  Enables or disables the Internal Voltage reference.
+  * @param  NewState : new state of the Internal Voltage reference.
+    *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_VrefintCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the Internal Voltage reference.*/
+    ADC1->TRIGR[0] |= (uint8_t)(ADC_TRIGR1_VREFINTON);
+  }
+  else
+  {
+    /* Disable the Internal Voltage reference.*/
+    ADC1->TRIGR[0] &= (uint8_t)(~ADC_TRIGR1_VREFINTON);
+  }
+}
+
+ /**
+  * @}
+  */
+/** @defgroup ADC_Group4 Channels Configuration functions
+ *  @brief   Channels Configuration functions
+ *
+@verbatim    
+ ===============================================================================
+                      Channels Configuration functions
+ ===============================================================================  
+  This section provides functions allowing to:
+   - Enable or disable the ADC channel using ADC_ChannelCmd() function,
+   - Configure the channels sampling times using ADC_SamplingTimeConfig() 
+     function.
+     Note: there are 2 sampling times configuration values : 
+            - 1st Group value : for channels 0..23  
+            - 2nd Group value : for channels 24..27 (depending on the MCU 
+              package density) and Temperature Sensor and Vrefint channels. 
+   - Configure the channels Schmitt Trigger for each channel using 
+     ADC_SchmittTriggerConfig() function.
+   - Get the current ADC conversion value.
+   
+ @endverbatim
+  * @{
+  */
+    
+/**
+  * @brief  Enables or disables the selected ADC channel(s).
+  * @param  ADCx where x can be 1 to select the specified ADC peripheral.
+  * @param  ADC_Channels: specifies the ADC channels to be initialized
+  *          This parameter can be one of the following values:
+  *            @arg ADC_Channel_0: Channel 0
+  *            @arg ADC_Channel_1: Channel 1
+  *            @arg ADC_Channel_2: Channel 2
+  *            @arg ADC_Channel_3: Channel 3
+  *            @arg ADC_Channel_4: Channel 4
+  *            @arg ADC_Channel_5: Channel 5
+  *            @arg ADC_Channel_6: Channel 6
+  *            @arg ADC_Channel_7: Channel 7
+  *            @arg ADC_Channel_8: Channel 8
+  *            @arg ADC_Channel_9: Channel 9
+  *            @arg ADC_Channel_10: Channel 10
+  *            @arg ADC_Channel_11: Channel 11
+  *            @arg ADC_Channel_12: Channel 12
+  *            @arg ADC_Channel_13: Channel 13
+  *            @arg ADC_Channel_14: Channel 14
+  *            @arg ADC_Channel_15: Channel 15
+  *            @arg ADC_Channel_16: Channel 16
+  *            @arg ADC_Channel_17: Channel 17
+  *            @arg ADC_Channel_18: Channel 18
+  *            @arg ADC_Channel_19: Channel 19
+  *            @arg ADC_Channel_20: Channel 20
+  *            @arg ADC_Channel_21: Channel 21
+  *            @arg ADC_Channel_22: Channel 22
+  *            @arg ADC_Channel_23: Channel 23
+  *            @arg ADC_Channel_24: Channel 24
+  *            @arg ADC_Channel_25: Channel 25
+  *            @arg ADC_Channel_26: Channel 26
+  *            @arg ADC_Channel_27: Channel 27
+  *            @arg ADC_Channel_Vrefint: Vrefint Channel
+  *            @arg ADC_Channel_TempSensor: Temperature sensor Channel
+  *            @arg ADC_Channel_00To07: select from channel00 to channel07
+  *            @arg ADC_Channel_08To15: select from channel08 to channel15
+  *            @arg ADC_Channel_16To23: select from channel16 to channel23
+  *            @arg ADC_Channel_24To27: select from channel24 to channel27
+  * @param  NewState : new state of the specified ADC channel(s).
+    *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_ChannelCmd(ADC_TypeDef* ADCx, ADC_Channel_TypeDef ADC_Channels, FunctionalState NewState)
+{
+  uint8_t regindex = 0;
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  regindex = (uint8_t)((uint16_t)ADC_Channels >> 8);
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ADC channel(s). */
+    ADCx->SQR[regindex] |= (uint8_t)(ADC_Channels);
+  }
+  else
+  {
+    /* Disable the selected ADC channel(s). */
+    ADCx->SQR[regindex] &= (uint8_t)(~(uint8_t)(ADC_Channels));
+  }
+}
+
+/**
+  * @brief  Configures the sampling time for the selected ADC channel group.
+  * @param  ADCx where x can be 1 to select the specified ADC peripheral.
+  * @param  ADC_GroupChannels : ADC channel group to configure.
+  *          This parameter can be one of the following values:
+  *            @arg ADC_Group_SlowChannels: Slow Channels group
+  *            @arg ADC_Group_FastChannels: Fast Channels group  
+  * @note   The channels of 1st ADC Group can be channels 0..23  
+  * @note   The channels of 2nd ADC Group can be channels 24..27 (depending on the MCU 
+  *         package density) and Temperature Sensor and Vrefint channels.  
+  * @param  ADC_SamplingTime : Specifies the sample time value
+  *          This parameter can be one of the following values:
+  *            @arg ADC_SamplingTime_4Cycles: Sampling Time Cycles is 4
+  *            @arg ADC_SamplingTime_9Cycles: Sampling Time Cycles is 9
+  *            @arg ADC_SamplingTime_16Cycles: Sampling Time Cycles is 16
+  *            @arg ADC_SamplingTime_24Cycles: Sampling Time Cycles is 24
+  *            @arg ADC_SamplingTime_48Cycles: Sampling Time Cycles is 48
+  *            @arg ADC_SamplingTime_96Cycles: Sampling Time Cycles is 96
+  *            @arg ADC_SamplingTime_192Cycles: Sampling Time Cycles is 192
+  *            @arg ADC_SamplingTime_384Cycles: Sampling Time Cycles is 384
+  * @retval None
+  */
+void ADC_SamplingTimeConfig(ADC_TypeDef* ADCx,
+                            ADC_Group_TypeDef ADC_GroupChannels,
+                            ADC_SamplingTime_TypeDef ADC_SamplingTime)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_GROUP(ADC_GroupChannels));
+  assert_param(IS_ADC_SAMPLING_TIME_CYCLES(ADC_SamplingTime));
+
+  if ( ADC_GroupChannels != ADC_Group_SlowChannels)
+  {
+    /* Configures the sampling time for the Fast ADC channel group. */
+    ADCx->CR3 &= (uint8_t)~ADC_CR3_SMPT2;
+    ADCx->CR3 |= (uint8_t)(ADC_SamplingTime << 5);
+  }
+  else
+  {
+    /* Configures the sampling time for the Slow ADC channel group. */
+    ADCx->CR2 &= (uint8_t)~ADC_CR2_SMPT1;
+    ADCx->CR2 |= (uint8_t)ADC_SamplingTime;
+  }
+}
+
+/**
+  * @brief  Configures the status of the Schmitt Trigger for the selected ADC 
+  *         channel(s).
+  * @param  ADCx where x can be 1 to select the specified ADC peripheral.
+  * @param  ADC_Channels: specifies the ADC channels to be initialized,
+  *          This parameter can be one of the following values:
+  *            @arg ADC_Channel_0: Channel 0
+  *            @arg ADC_Channel_1: Channel 1
+  *            @arg ADC_Channel_2: Channel 2
+  *            @arg ADC_Channel_3: Channel 3
+  *            @arg ADC_Channel_4: Channel 4
+  *            @arg ADC_Channel_5: Channel 5
+  *            @arg ADC_Channel_6: Channel 6
+  *            @arg ADC_Channel_7: Channel 7
+  *            @arg ADC_Channel_8: Channel 8
+  *            @arg ADC_Channel_9: Channel 9
+  *            @arg ADC_Channel_10: Channel 10
+  *            @arg ADC_Channel_11: Channel 11
+  *            @arg ADC_Channel_12: Channel 12
+  *            @arg ADC_Channel_13: Channel 13
+  *            @arg ADC_Channel_14: Channel 14
+  *            @arg ADC_Channel_15: Channel 15
+  *            @arg ADC_Channel_16: Channel 16
+  *            @arg ADC_Channel_17: Channel 17
+  *            @arg ADC_Channel_18: Channel 18
+  *            @arg ADC_Channel_19: Channel 19
+  *            @arg ADC_Channel_20: Channel 20
+  *            @arg ADC_Channel_21: Channel 21
+  *            @arg ADC_Channel_22: Channel 22
+  *            @arg ADC_Channel_23: Channel 23
+  *            @arg ADC_Channel_24: Channel 24
+  *            @arg ADC_Channel_25: Channel 25
+  *            @arg ADC_Channel_26: Channel 26
+  *            @arg ADC_Channel_27: Channel 27
+  *            @arg ADC_Channel_Vrefint: Vrefint Channel
+  *            @arg ADC_Channel_TempSensor: Temperature sensor Channel
+  *            @arg ADC_Channel_00To07: select from channel00 to channel07
+  *            @arg ADC_Channel_08To15: select from channel08 to channel15
+  *            @arg ADC_Channel_16To23: select from channel16 to channel23
+  *            @arg ADC_Channel_24To27: select from channel24 to channel27
+  * @param  NewState : new state of the Schmitt Trigger
+    *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_SchmittTriggerConfig(ADC_TypeDef* ADCx, ADC_Channel_TypeDef ADC_Channels,
+                              FunctionalState NewState)
+{
+  uint8_t regindex = 0;
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  regindex = (uint8_t)((uint16_t)ADC_Channels >> 8);
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the Schmitt Trigger for the selected ADC channel(s).*/
+    ADCx->TRIGR[regindex] &= (uint8_t)(~(uint8_t)ADC_Channels);
+  }
+  else
+  {
+    /* Disable the Schmitt Trigger for the selected ADC channel(s).*/
+    ADCx->TRIGR[regindex] |= (uint8_t)(ADC_Channels);
+  }
+}
+
+/**
+  * @brief  Returns the last ADC converted data.
+  * @param  ADCx where x can be 1 to select the specified ADC peripheral.
+  * @retval The Data conversion value.
+  */
+uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx)
+{
+  uint16_t tmpreg = 0;
+
+  /* Get last ADC converted data.*/
+  tmpreg = (uint16_t)(ADCx->DRH);
+  tmpreg = (uint16_t)((uint16_t)((uint16_t)tmpreg << 8) | ADCx->DRL);
+
+  /* Return the selected ADC conversion value */
+  return (uint16_t)(tmpreg) ;
+}
+
+ /**
+  * @}
+  */
+
+/** @defgroup ADC_Group5 ADC Channels DMA Configuration function
+ *  @brief   ADC Channels DMA Configuration function 
+ *
+@verbatim   
+ ===============================================================================
+                   ADC Channels DMA Configuration function
+ ===============================================================================  
+
+  This section provides a function allowing to configure the DMA for ADC 
+  channel.
+  Since converted channel values are stored into a unique data register, 
+  it is useful to use DMA for conversion of more than one channel. This 
+  avoids the loss of the data already stored in the ADC Data register. 
+  
+  When the DMA mode is enabled (using the ADC_DMACmd() function), after each
+  conversion of a channel, a DMA request is generated.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Enables or disables the specified ADC DMA request.
+  * @param  ADCx where x can be 1 to select the specified ADC peripheral.
+  * @param  NewState : new state of the specified ADC DMA transfer.
+    *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the specified ADC DMA request */
+    ADCx->SQR[0] &= (uint8_t)~ADC_SQR1_DMAOFF;
+  }
+  else
+  {
+    /* Disable the specified ADC DMA request */
+    ADCx->SQR[0] |= ADC_SQR1_DMAOFF;
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Group6 Interrupts and flags management functions
+ *  @brief   Interrupts and flags management functions
+ *
+@verbatim   
+ ===============================================================================
+                   Interrupts and flags management functions
+ ===============================================================================  
+
+  This section provides functions allowing to configure the ADC Interrupts and 
+  get the status and clear flags and Interrupts pending bits.
+  
+  The ADC provides 3 Interrupt sources and 3 Flags:
+  
+  Flags :
+  ---------- 
+     1. ADC_FLAG_OVR : Overrun detection when ADC channel converted data is lost
+
+     2. ADC_FLAG_EOC : End of conversion - to indicate the end of a regular 
+                  CHANNEL conversion or a GROUP conversions, depending of the 
+                  ADC Continuous Conversion Mode (Continuous or Single 
+                  conversion) and of the DMA usage.
+                  Note : if DMA is used, EOC occurs at the end of the sequence 
+                         conversion, else it occurs after each conversion
+     3. ADC_FLAG_AWD: to indicate if the converted voltage crosses the 
+                programmed Analog watchdog thresholds values.
+
+     
+  Interrupts :
+  ------------
+     1. ADC_IT_OVR : specifies the interrupt source for the Overrun detection event.
+     2. ADC_IT_EOC : specifies the interrupt source for the End of conversion event.
+     3. ADC_IT_AWD : specifies the interrupt source for the Analog watchdog event.
+
+@endverbatim
+  * @{
+  */ 
+
+/**
+  * @brief  Enables or disables the specified ADC interrupts.
+  * @param  ADCx where x can be 1 to select the specified ADC peripheral.
+  * @param  ADC_IT : specifies the ADC interrupt sources to be enabled or 
+  *         disabled. 
+  *          This parameter can be one of the following values:
+  *            @arg ADC_IT_EOC: End of Conversion Interrupt
+  *            @arg ADC_IT_AWD: Analog WatchDog Interrupt
+  *            @arg ADC_IT_OVER: Over Run Interrupt
+  * @param  NewState : new state of the specified ADC interrupts.
+    *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_ITConfig(ADC_TypeDef* ADCx, ADC_IT_TypeDef ADC_IT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  assert_param(IS_ADC_IT(ADC_IT));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ADC interrupts */
+    ADCx->CR1 |= (uint8_t) ADC_IT;
+  }
+  else
+  {
+    /* Disable the selected ADC interrupts */
+    ADCx->CR1 &= (uint8_t)(~ADC_IT);
+  }
+}
+
+/**
+  * @brief  Checks whether the specified ADC flag is set or not.
+  * @param  ADCx where x can be 1 to select the specified ADC peripheral.
+  * @param  ADC_FLAG: specifies the flag to check.
+  *          This parameter can be one of the following values:
+  *            @arg ADC_FLAG_EOC: End of Conversion flag
+  *            @arg ADC_FLAG_AWD: Analog WatchDog flag
+  *            @arg ADC_FLAG_OVER: Over Run flag    
+  * @retval The new state of ADC_FLAG (SET or RESET).
+  */
+FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, ADC_FLAG_TypeDef ADC_FLAG)
+{
+  FlagStatus flagstatus = RESET;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_GET_FLAG(ADC_FLAG));
+
+  /* Check the status of the specified ADC flag */
+  if ((ADCx->SR & ADC_FLAG) != (uint8_t)RESET)
+  {
+    /* ADC_FLAG is set */
+    flagstatus = SET;
+  }
+  else
+  {
+    /* ADC_FLAG is reset */
+    flagstatus = RESET;
+  }
+
+  /* Return the ADC_FLAG status */
+  return  flagstatus;
+}
+
+/**
+  * @brief  Clears the ADC's pending flags.
+  * @param  ADCx where x can be 1 to select the specified ADC peripheral.
+  * @param  ADC_FLAG: specifies the flag to clear.
+  *          This parameter can be one of the following values:
+  *            @arg ADC_FLAG_EOC: End of Conversion flag
+  *            @arg ADC_FLAG_AWD: Analog WatchDog flag
+  *            @arg ADC_FLAG_OVER: Over Run flag 
+  * @retval None
+  */
+void ADC_ClearFlag(ADC_TypeDef* ADCx,
+                   ADC_FLAG_TypeDef ADC_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG));
+
+  /* Clear the selected ADC flags */
+  ADCx->SR = (uint8_t)~ADC_FLAG;
+}
+
+/**
+  * @brief  Checks whether the specified ADC interrupt has occurred or not.
+  * @param  ADCx where x can be 1 to select the specified ADC peripheral.
+  * @param  ADC_IT: specifies the ADC interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg ADC_IT_EOC: End of Conversion Interrupt
+  *            @arg ADC_IT_AWD: Analog WatchDog Interrupt
+  *            @arg ADC_IT_OVER: Over Run Interrupt
+  * @retval Status of ADC_IT (SET or RESET).
+  */
+ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx,
+                         ADC_IT_TypeDef ADC_IT)
+{
+  ITStatus itstatus = RESET;
+  uint8_t itmask = 0, enablestatus = 0;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_GET_IT(ADC_IT));
+
+  /* Get the ADC IT index */
+  itmask = (uint8_t)(ADC_IT >> 3);
+  itmask =  (uint8_t)((uint8_t)((uint8_t)(itmask & (uint8_t)0x10) >> 2) | \
+                                (uint8_t)(itmask & (uint8_t)0x03));
+
+  /* Get the ADC_IT enable bit status */
+  enablestatus = (uint8_t)(ADCx->CR1 & (uint8_t)ADC_IT) ;
+
+  /* Check the status of the specified ADC interrupt */
+  if (((ADCx->SR & itmask) != (uint8_t)RESET) && enablestatus)
+  {
+    /* ADC_IT is set */
+    itstatus = SET;
+  }
+  else
+  {
+    /* ADC_IT is reset */
+    itstatus = RESET;
+  }
+
+  /* Return the ADC_IT status */
+  return  itstatus;
+}
+
+/**
+  * @brief  Clears the ADC’s interrupt pending bits.
+  * @param  ADCx where x can be 1 to select the specified ADC peripheral.
+  * @param  ADC_IT: specifies the ADC interrupt pending bit to clear.
+  *          This parameter can be one of the following values:
+  *            @arg ADC_IT_EOC: End of Conversion Interrupt
+  *            @arg ADC_IT_AWD: Analog WatchDog Interrupt
+  *            @arg ADC_IT_OVER: Over Run Interrupt
+  * @retval None
+  */
+void ADC_ClearITPendingBit(ADC_TypeDef* ADCx,
+                           ADC_IT_TypeDef ADC_IT)
+{
+  uint8_t itmask = 0;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_IT(ADC_IT));
+
+  /* Get the ADC IT index */
+  itmask = (uint8_t)(ADC_IT >> 3);
+  itmask =  (uint8_t)((uint8_t)(((uint8_t)(itmask & (uint8_t)0x10)) >> 2) | \
+                                 (uint8_t)(itmask & (uint8_t)0x03));
+
+  /* Clear the selected ADC interrupt pending bits */
+  ADCx->SR = (uint8_t)~itmask;
+}
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_aes.c b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_aes.c
new file mode 100755
index 0000000..3e4c945
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_aes.c
@@ -0,0 +1,485 @@
+/**
+  ******************************************************************************
+  * @file    stm8l15x_aes.c
+  * @author  MCD Application Team
+  * @version V1.6.0
+  * @date    28-June-2013
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Advanced Encryption Standard (AES) peripheral:           
+  *           - Configuration
+  *           - Read/Write operations
+  *           - DMA transfers management  
+  *           - Interrupts and flags management
+  *
+  *  @verbatim  
+  *          ===================================================================
+  *                                 How to use this driver
+  *          ===================================================================  
+  *          1- Enable AES clock to get write access to AES registers
+  *             using CLK_PeripheralClockConfig(CLK_Peripheral_AES, ENABLE);
+  *
+  *          2- Configure the AES operation mode using AES_OperationModeConfig()
+  *
+  *          3- If required, enable interrupt source using AES_ITConfig()
+  *
+  *          4- If required, when using the DMA mode 
+  *               - Configure the DMA using DMA_Init()
+  *               - Enable DMA requests using AES_DMAConfig()
+  *
+  *          5- Enable the AES peripheral using AES_Cmd()
+  *
+  *          6- Write data/key using AES_WriteSubData() / AES_WriteSubKey()
+  *            
+  *  @endverbatim   
+  ******************************************************************************
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ****************************************************************************** 
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm8l15x_aes.h"
+
+/** @addtogroup STM8L15x_StdPeriph_Driver
+  * @{
+  */
+  
+/** @defgroup AES 
+  * @brief AES driver modules
+  * @{
+  */ 
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup AES_Private_Functions
+  * @{
+  */ 
+
+/** @defgroup AES_Group1 Configuration
+ *  @brief   Configuration
+ *
+@verbatim   
+ ===============================================================================
+                           Configuration
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */  
+  
+/**
+  * @brief   Deinitializes the AES peripheral.
+  * @param   None.
+  * @retval  None
+  */
+void AES_DeInit(void)
+{
+  /* Set AES_CR to reset value 0x00, AES_SR is reset by setting ERRC and CCFC bits in CR */
+  AES->CR = AES_CR_ERRC | AES_CR_CCFC;
+  AES->DINR = AES_DINR_RESET_VALUE;       /* Set AES_DINR to reset value 0x00 */
+  AES->DOUTR = AES_DOUTR_RESET_VALUE;     /* Set AES_DOUTR to reset value 0x00 */
+}
+
+/**
+  * @brief   Configures the AES operation mode.
+  * @param   AES_Operation : the selected AES operation mode.
+  *          This parameter can be one of the following values:
+  *            @arg AES_Operation_Encryp: AES in Encryption mode
+  *            @arg AES_Operation_KeyDeriv: AES in Key Derivation mode
+  *            @arg AES_Operation_Decryp: AES in Decryption mode
+  *            @arg AES_Operation_KeyDerivAndDecryp: AES in Key Derivation and Decryption mode
+  * @note   The operation mode must be configured when AES peripheral is disabled.
+  * @retval  None
+  */
+void AES_OperationModeConfig(AES_Operation_TypeDef AES_Operation)
+{
+  /* Check the parameter */
+  assert_param(IS_AES_MODE(AES_Operation));
+
+  /* Reset the operation mode bits in CR register */
+  AES->CR &= (uint8_t) (~AES_CR_MODE);
+
+  /* Set the new operaton mode bits in CR register */
+  AES->CR |= (uint8_t) (AES_Operation);
+}
+
+/**
+  * @brief  Enable the AES peripheral.
+  * @param  NewState : The new state of the AES peripheral.
+    *         This parameter can be: ENABLE or DISABLE.
+  * @note   AES peripheral can be enabled once operation mode is configured using
+  *         AES_OperationModeConfig()  
+  * @retval None
+  */
+void AES_Cmd(FunctionalState NewState)
+{
+  /* Check the parameter */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    AES->CR |= (uint8_t) AES_CR_EN;   /**< AES Enable */
+  }
+  else
+  {
+    AES->CR &= (uint8_t)(~AES_CR_EN);  /**< AES Disable */
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup AES_Group2 AES Read and Write
+ *  @brief   AES Read and Write
+ *
+@verbatim   
+ ===============================================================================
+                        AES Read and Write operations
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Write data in DINR register to be processed by AES peripheral.
+  * @param  Data: The data to be processed.
+  * @note   When an unexpected write to DINR register is detected, WRERR flag is
+  *         set.
+  * @retval None
+  */
+void AES_WriteSubData(uint8_t Data)
+{
+  /* Write Data */
+  AES->DINR = Data;
+}
+
+/**
+  * @brief  Write key in DINR register.
+  * @param  Key: The key to be used for encryption/decryption.
+  * @note   When an unexpected write to DINR register is detected, WRERR flag is
+  *         set.
+  * @retval None
+  */
+void AES_WriteSubKey(uint8_t Key)
+{
+  /* Write key */
+  AES->DINR = Key;
+}
+
+/**
+  * @brief  Returns the data in DOUTR register processed by AES peripheral.
+  * @note   When an unexpected read of DOUTR register is detected, RDERR flag is
+  *         set
+  * @retval The processed data.
+  */
+uint8_t AES_ReadSubData(void)
+{
+  return AES->DOUTR;
+}
+
+/**
+  * @brief  Returns the DOUTR register content.
+  * @retval The derivation key.
+  * @note   When an unexpected read of DOUTR register is detected, RDERR flag is
+  *         set.  
+  */
+uint8_t AES_ReadSubKey(void)
+{
+  return AES->DOUTR;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup AES_Group3 DMA transfers management functions
+ *  @brief   DMA transfers management function
+ *
+@verbatim   
+ ===============================================================================
+                      DMA transfers management functions
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Configures the AES DMA interface.
+  * @param  AES_DMATransfer: Specifies the AES DMA transfer.
+  *          This parameter can be one of the following values:
+  *            @arg AES_DMATransfer_InOut: DMA requests enabled for input/Output transfer phase
+  * @param  NewState Indicates the new state of the AES DMA interface.
+    *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  * @note   CCF bit has no meaning when DMA requests are enabled (DMAEN = 1).
+  */
+void AES_DMAConfig(AES_DMATransfer_TypeDef AES_DMATransfer, FunctionalState NewState)
+{
+  /* Check the parameter */
+  assert_param(IS_AES_DMATRANSFER(AES_DMATransfer));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the DMA transfer */
+    AES->CR |= (uint8_t) AES_DMATransfer;
+  }
+  else
+  {
+    /* Disable the DMA transfer */
+    AES->CR &= (uint8_t)(~AES_DMATransfer);
+  }
+}
+
+
+/**
+  * @}
+  */
+
+/** @defgroup AES_Group4 Interrupts and flags management functions
+ *  @brief   Interrupts and flags management functions
+ *
+@verbatim   
+
+ ===============================================================================
+                   Interrupts and flags management functions
+ ===============================================================================
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the specified AES interrupt.
+  * @param  AES_IT: Specifies the AES interrupt source to enable/disable.
+  *          This parameter can be one of the following values:
+  *            @arg AES_IT_CCIE: Computation Complete interrupt enable
+  *            @arg AES_IT_ERRIE: Error interrupt enable
+  * @param  NewState : The new state of the AES peripheral.
+    *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void AES_ITConfig(AES_IT_TypeDef AES_IT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  assert_param(IS_AES_IT(AES_IT));
+
+  if (NewState != DISABLE)
+  {
+    AES->CR |= (uint8_t) AES_IT;    /**< AES_IT Enable */
+  }
+  else
+  {
+    AES->CR &= (uint8_t)(~AES_IT);  /**< AES_IT Disable */
+  }
+}
+
+/**
+  * @brief  Checks whether the specified AES flag is set or not.
+  * @param  AES_FLAG specifies the flag to check.
+  *          This parameter can be one of the following values:
+  *            @arg AES_FLAG_CCF: Computation Complete Flag
+  *            @arg AES_FLAG_RDERR: Read Error Flag
+  *            @arg AES_FLAG_WRERR: Write Error Flag 
+  * @retval FlagStatus (SET or RESET)
+  * @note   CCF bit has a meaning only when DMA requests are disabled (DMAEN bit = 0).
+  */
+FlagStatus AES_GetFlagStatus(AES_FLAG_TypeDef AES_FLAG)
+{
+  FlagStatus status = RESET;
+
+  /* Check parameters */
+  assert_param(IS_AES_FLAG(AES_FLAG));
+
+  if (AES_FLAG == AES_FLAG_CCF)
+  {
+    if ((AES->SR & (uint8_t)AES_FLAG_CCF) != (uint8_t)0x00)
+    {
+      /* Computation Complete Flag CCF is set */
+      status = (FlagStatus) SET;
+    }
+    else
+    {
+      /* Computation Complete Flag CCF is reset */
+      status = (FlagStatus) RESET;
+    }
+  }
+  else if (AES_FLAG == AES_FLAG_RDERR)
+  {
+    if ((AES->SR & (uint8_t)AES_FLAG_RDERR) != (uint8_t)0x00)
+    {
+      /* Read Error Flag RDERR is set */
+      status = (FlagStatus) SET;
+    }
+    else
+    {
+      /* Read Error Flag RDERR is reset */
+      status = (FlagStatus) RESET;
+    }
+  }
+  else
+  {
+    if ((AES->SR & (uint8_t)AES_FLAG_WRERR) != (uint8_t)0x00)
+    {
+      /* Write Error Flag WRERR is set */
+      status = (FlagStatus) SET;
+    }
+    else
+    {
+      /* Write Error Flag WRERR is reset */
+      status = (FlagStatus) RESET;
+    }
+  }
+  /* Return the AES_FLAG status */
+  return ((FlagStatus) status);
+}
+
+/**
+  * @brief  Clears the AES flags.
+  * @param  AES_FLAG: specifies the flag to clear.
+  *          This parameter can be one of the following values:
+  *            @arg AES_FLAG_CCF: Computation Complete Flag
+  *            @arg AES_FLAG_RDERR: Read Error Flag
+  *            @arg AES_FLAG_WRERR: Write Error Flag 
+  * @retval None
+  */
+void AES_ClearFlag(AES_FLAG_TypeDef AES_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_AES_FLAG(AES_FLAG));
+
+  /* Check if AES_FLAG is AES_FLAG_CCF */
+  if (AES_FLAG == AES_FLAG_CCF)
+  {
+    /* Clear CCF flag by setting CCFC bit */
+    AES->CR |= (uint8_t) AES_CR_CCFC;
+  }
+  else /* AES_FLAG is AES_FLAG_RDERR or AES_FLAG_WRERR */
+  {
+    /* Clear RDERR and WRERR flags by setting ERRC bit */
+    AES->CR |= (uint8_t) AES_CR_ERRC;
+  }
+}
+
+/**
+  * @brief  Checks whether the specified AES interrupt has occurred or not.
+  * @param  AES_IT: Specifies the AES interrupt pending bit to check.
+  *          This parameter can be one of the following values:
+  *            @arg AES_IT_CCIE: Computation Complete interrupt enable
+  *            @arg AES_IT_ERRIE: Error interrupt enable
+  * @retval ITStatus The new state of AES_IT (SET or RESET).
+  */
+ITStatus AES_GetITStatus(AES_IT_TypeDef AES_IT)
+{
+  ITStatus itstatus = RESET;
+  BitStatus cciebitstatus, ccfbitstatus = RESET;
+
+  /* Check parameters */
+  assert_param(IS_AES_IT(AES_IT));
+
+  cciebitstatus = (BitStatus) (AES->CR & AES_CR_CCIE);
+  ccfbitstatus =  (BitStatus) (AES->SR & AES_SR_CCF);
+
+  /* Check if AES_IT is AES_IT_CCIE */
+  if (AES_IT == AES_IT_CCIE)
+  {
+    /* Check the status of the specified AES interrupt */
+    if (((cciebitstatus) != RESET) && ((ccfbitstatus) != RESET))
+    {
+      /* Interrupt occurred */
+      itstatus = (ITStatus) SET;
+    }
+    else
+    {
+      /* Interrupt not occurred */
+      itstatus = (ITStatus) RESET;
+    }
+  }
+  else /* AES_IT is AES_IT_ERRIE */
+  {
+    /* Check the status of the specified AES interrupt */
+    if ((AES->CR & AES_CR_ERRIE) != RESET)
+    {
+      /* Check if WRERR or RDERR flags are set */
+      if ((AES->SR & (uint8_t)(AES_SR_WRERR | AES_SR_RDERR)) != RESET)
+      {
+        /* Interrupt occurred */
+        itstatus = (ITStatus) SET;
+      }
+      else
+      {
+        /* Interrupt not occurred */
+        itstatus = (ITStatus) RESET;
+      }
+    }
+    else
+    {
+      /* Interrupt not occurred */
+      itstatus = (ITStatus) RESET;
+    }
+  }
+
+  /* Return the AES_IT status */
+  return ((ITStatus)itstatus);
+}
+
+/**
+  * @brief  Clears the AES's interrupt pending bits.
+  * @param  AES_IT: specifies the interrupt pending bit to clear.
+  *          This parameter can be one of the following values:
+  *            @arg AES_IT_CCIE: Computation Complete interrupt enable
+  *            @arg AES_IT_ERRIE: Error interrupt enable
+  * @retval None
+  */
+void AES_ClearITPendingBit(AES_IT_TypeDef AES_IT)
+{
+  /* Check the parameters */
+  assert_param(IS_AES_IT(AES_IT));
+
+  /* Check if AES_IT is AES_IT_CCIE */
+  if (AES_IT == AES_IT_CCIE)
+  {
+    /* Clear CCF flag by setting CCFC bit */
+    AES->CR |= (uint8_t) AES_CR_CCFC;
+  }
+  else /* AES_IT is AES_IT_ERRIE */
+  {
+    /* Clear RDERR and WRERR flags by setting ERRC bit */
+    AES->CR |= (uint8_t) AES_CR_ERRC;
+  }
+}
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_beep.c b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_beep.c
new file mode 100755
index 0000000..155ebbe
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_beep.c
@@ -0,0 +1,244 @@
+/**
+  ******************************************************************************
+  * @file    stm8l15x_beep.c
+  * @author  MCD Application Team
+  * @version V1.6.0
+  * @date    28-June-2013
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the BEEPER (BEEP) peripheral:           
+  *           - Initialization and Configuration
+  *           - Low Speed Internal Clock(LSI) Calibration
+  *
+  *  @verbatim  
+  *          ===================================================================
+  *                                 How to use this driver
+  *          ===================================================================  
+  *          1- Make sure that the LS RC clock calibration is performed by the following 
+  *            steps:
+  *               - Connect internally the LS clock source to TIM2 channel 1 input
+  *                 capture for measurement using BEEP_LSClockToTIMConnectCmd() function
+  *               - Update the BEEP_CSR register by the measured LSI frequency 
+  *                  --> During this phase the BEEPER must be disabled to avoid 
+  *                      unwanted interrupts  
+  *
+  *          2- Configure the output beeper frequency using the BEEP_Init() function
+  *
+  *          3- Enable the beeper using the BEEP_Cmd() function
+  *
+  *  @endverbatim   
+  ******************************************************************************
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ****************************************************************************** 
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm8l15x_beep.h"
+
+/** @addtogroup STM8L15x_StdPeriph_Driver
+  * @{
+  */
+/** @defgroup BEEP 
+  * @brief BEEP driver modules
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup BEEP_Private_Functions
+  * @{
+  */
+
+/** @defgroup BEEP_Group1 Initialization and Configuration functions
+ *  @brief    Initialization and Configuration functions 
+ *
+@verbatim    
+ ===============================================================================
+                      Initialization and Configuration functions
+ ===============================================================================  
+  This section provides functions allowing to:
+   - Initialize and configure the Beeper frequency
+   - Enable and Disable the Beeper output
+   
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Deinitializes the BEEP peripheral registers to their default
+  *         reset values.
+  * @param  None
+  * @retval None
+  */
+void BEEP_DeInit(void)
+{
+  BEEP->CSR1 = BEEP_CSR1_RESET_VALUE;
+  BEEP->CSR2 = BEEP_CSR2_RESET_VALUE;
+}
+
+/**
+  * @brief  Initializes the BEEP function according to the specified parameters.
+  * @note   The LS RC calibration must be performed before calling this function.
+  * @param  BEEP_Frequency Frequency selection.
+  *         This parameter can be one of the values of @ref BEEP_Frequency_TypeDef.
+  * @retval None
+  */
+void BEEP_Init(BEEP_Frequency_TypeDef BEEP_Frequency)
+{
+
+  /* Check parameter */
+  assert_param(IS_BEEP_FREQUENCY(BEEP_Frequency));
+
+  /* Set a default calibration value if no calibration is done */
+  if ((BEEP->CSR2 & BEEP_CSR2_BEEPDIV) == BEEP_CSR2_BEEPDIV)
+  {
+    BEEP->CSR2 &= (uint8_t)(~BEEP_CSR2_BEEPDIV); /* Clear bits */
+    BEEP->CSR2 |= BEEP_CALIBRATION_DEFAULT;
+  }
+
+  /* Select the output frequency */
+  BEEP->CSR2 &= (uint8_t)(~BEEP_CSR2_BEEPSEL);
+  BEEP->CSR2 |= (uint8_t)(BEEP_Frequency);
+
+}
+
+/**
+  * @brief  Enable or disable the BEEP function.
+  * @note   Initialisation of BEEP and LS RC calibration must be done before.
+  * @param  NewState Indicates the new state of the BEEP function.
+  * @retval None
+  */
+void BEEP_Cmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the BEEP peripheral */
+    BEEP->CSR2 |= BEEP_CSR2_BEEPEN;
+  }
+  else
+  {
+    /* Disable the BEEP peripheral */
+    BEEP->CSR2 &= (uint8_t)(~BEEP_CSR2_BEEPEN);
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BEEP_Group2 Low Speed Internal Clock(LSI) Calibration functions
+ *  @brief    Low Speed Internal Clock(LSI) Calibration functions 
+ *
+@verbatim   
+ ===============================================================================
+              Low Speed Internal Clock(LSI) Calibration functions
+ ===============================================================================  
+
+  This section provides functions allowing to measure and calibrate the internal 
+  low speed clock source to ensure better BEEPER output frequency .
+  
+  A typical configuration for LSI calibration is done following these steps :
+   1. Disable the Beeper to avoid any unwanted interrupt using BEEP_Cmd() function 
+   2. Measure the LSI clock frequency by connecting it internally to TIM2 input capture  
+      using BEEP_LSClockToTIMConnectCmd() function.
+   3. Calibrate the beeper frequency with the measured LSI clock frequency using 
+      BEEP_LSICalibrationConfig() function.
+   
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Enable or disable the LS clock source connection to TIM for measurement.
+  * @param  NewState Indicates the new state of the LS clock to TIM connection
+  * @retval None
+  */
+void BEEP_LSClockToTIMConnectCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Connect LS clock to TIM for measurement */
+    BEEP->CSR1 |= BEEP_CSR1_MSR;
+  }
+  else
+  {
+    /* Disconnect LS clock to TIM */
+    BEEP->CSR1 &= (uint8_t)(~BEEP_CSR1_MSR);
+  }
+}
+/**
+  * @brief  Update CSR register with the measured LSI frequency.
+  * @note   BEEP must be disabled to avoid unwanted interrupts.
+  * @note   Prescaler calculation:
+  *         A is the integer part of LSIFreqkHz/4 and x the decimal part.
+  *         x <= A/(1+2A) is equivalent to A >= x(1+2A)
+  *         and also to 4A >= 4x(1+2A) [F1]
+  *         but we know that A + x = LSIFreqkHz/4 ==> 4x = LSIFreqkHz-4A
+  *         so [F1] can be written :
+  *         4A >= (LSIFreqkHz-4A)(1+2A)
+  * @param  LSIFreqHz Low Speed RC frequency measured by timer (in Hz).
+  * @retval None
+  */
+void BEEP_LSICalibrationConfig(uint32_t LSIFreqHz)
+{
+  uint16_t lsifreqkhz;
+  uint16_t A;
+
+  /* Check parameter */
+  assert_param(IS_LSI_FREQUENCY(LSIFreqHz));
+
+  lsifreqkhz = (uint16_t)(LSIFreqHz / 1000); /* Converts value in kHz */
+
+  /* Calculation of BEEPER calibration value */
+
+  BEEP->CSR2 &= (uint8_t)(~BEEP_CSR2_BEEPDIV); /* Clear bits */
+
+  A = (uint16_t)(lsifreqkhz >> 3U); /* Division by 8, keep integer part only */
+
+  if ((8U * A) >= ((lsifreqkhz - (8U * A)) * (1U + (2U * A))))
+  {
+    BEEP->CSR2 |= (uint8_t)(A - 2U);
+  }
+  else
+  {
+    BEEP->CSR2 |= (uint8_t)(A - 1U);
+  }
+}
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_clk.c b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_clk.c
new file mode 100755
index 0000000..732399d
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_clk.c
@@ -0,0 +1,1120 @@
+/**
+  ******************************************************************************
+  * @file    stm8l15x_clk.c
+  * @author  MCD Application Team
+  * @version V1.6.0
+  * @date    28-June-2013
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the clock controler (CLK) peripheral:
+  *           - Internal/external clocks, CSS and CCO configuration
+  *           - System clocks configuration
+  *           - Peripheral clocks configuration
+  *           - CSS on LSE configuration 
+  *           - Low power clock configuration  
+  *           - Interrupts and flags management
+  *
+  *  @verbatim
+  *               
+  *          ===================================================================
+  *                               CLK specific features
+  *          ===================================================================
+  *    
+  *          After reset the device is running from Internal High Speed oscillator
+  *          divided by 8 (HSI/8 = 2MHz) with all peripherals off.
+  *           - The clock for all peripherals is switched off, except for the BootROM 
+  *             clock used for bootloader, in which case, the software should be properly 
+  *             written to switch off that clock after the bootloader execution.     
+  *
+  *          Once the device starts from reset, the user application has to:
+  *           - Configure the clock source to be used to drive the System clock
+  *             (if the application needs higher frequency/performance)
+  *           - Configure the System clock frequency  
+  *           - Enable the clock for the peripheral(s) to be used
+  *           - Configure the clock source(s) for peripherals which clocks are not
+  *             derived from the System clock (RTC/LCD, BEEP)
+  *
+  *  @endverbatim
+  *    
+  ******************************************************************************
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ****************************************************************************** 
+  */
+
+/* Includes ------------------------------------------------------------------*/
+
+#include "stm8l15x_clk.h"
+
+/** @addtogroup STM8L15x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup CLK 
+  * @brief CLK driver modules
+  * @{
+  */ 
+/* Private typedef -----------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private Variables ---------------------------------------------------------*/
+/* Private Constant ---------------------------------------------------------*/
+CONST uint8_t SYSDivFactor[5] = {1, 2, 4, 8, 16}; /*!< Holds the different Master clock Divider factors */
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup CLK_Private_Functions
+  * @{
+  */ 
+
+/** @defgroup CLK_Group1 Internal and external clocks, CSS and CCO configuration functions
+ *  @brief   Internal and external clocks, CSS and CCO configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+      Internal/external clocks, CSS and CCO configuration functions
+ ===============================================================================  
+
+  This section provides functions allowing to configure the internal/external clocks,
+  CSS and CCO pins.
+  
+  1. HSI (high-speed internal), 16 MHz factory-trimmed RC used directly as System 
+     clock source.
+
+  2. LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC
+     and/or BEEP clock source.
+
+  3. HSE (high-speed external), 1 to 16 MHz crystal oscillator used directly as 
+     System clock source. Can be used also as RTC/LCD clock source.
+
+  4. LSE (low-speed external), 32 KHz oscillator used as RTC/LCD and/or BEEP clock source.
+
+  5. CSS (Clock security system), once enabled and if a HSE clock failure occurs 
+     (HSE used as System clock source), the System clock is automatically switched
+     to HSI and an interrupt is generated if enabled. 
+
+  6. CCO (configurable clock output), used to output HSI, LSE, HSE, HSI, LSI
+     clock (through a configurable prescaler) on PC4 pin.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the CLK peripheral registers to their default reset values.
+  * @param  None
+  * @retval None
+  */
+void CLK_DeInit(void)
+{
+  CLK->ICKCR = CLK_ICKCR_RESET_VALUE;
+  CLK->ECKCR = CLK_ECKCR_RESET_VALUE;
+  CLK->CRTCR = CLK_CRTCR_RESET_VALUE;
+  CLK->CBEEPR = CLK_CBEEPR_RESET_VALUE;
+  CLK->SWR  = CLK_SWR_RESET_VALUE;
+  CLK->SWCR = CLK_SWCR_RESET_VALUE;
+  CLK->CKDIVR = CLK_CKDIVR_RESET_VALUE;
+  CLK->PCKENR1 = CLK_PCKENR1_RESET_VALUE;
+  CLK->PCKENR2 = CLK_PCKENR2_RESET_VALUE;
+  CLK->PCKENR3 = CLK_PCKENR3_RESET_VALUE;
+  CLK->CSSR  = CLK_CSSR_RESET_VALUE;
+  CLK->CCOR = CLK_CCOR_RESET_VALUE;
+  CLK->HSITRIMR = CLK_HSITRIMR_RESET_VALUE;
+  CLK->HSICALR = CLK_HSICALR_RESET_VALUE;
+  CLK->HSIUNLCKR = CLK_HSIUNLCKR_RESET_VALUE;
+  CLK->REGCSR = CLK_REGCSR_RESET_VALUE;
+}
+
+/**
+  * @brief  Enables or disables the Internal High Speed oscillator (HSI).
+  * @note   The HSI is stopped by hardware when entering Halt and active Halt modes.
+  *         It is used (enabled by hardware) as system clock source after startup
+  *         from Reset, wakeup from Halt and active Halt mode when the FHWU bit is
+  *         set in the ICKCR register, or in case of HSE failure used as system clock
+  *         (if the Clock Security System CSS is enabled).             
+  * @note   HSI can not be stopped if it is used as active CCO source, as active 
+  *         RTC clock, if the safe oscillator (AUX) is enabled or as system clock source,
+  *         In this case, you have to select another source of the system clock 
+  *         then stop the HSI.
+  * @note   After enabling the HSI, the application software should wait on HSIRDY
+  *         flag to be set indicating that HSI clock is stable and can be used as
+  *         system clock source.  
+  * @param  NewState: new state of the HSI.
+    *         This parameter can be: ENABLE or DISABLE.
+  * @note   When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
+  *         clock cycles.  
+  * @retval None
+  */
+void CLK_HSICmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Set HSION bit */
+    CLK->ICKCR |= CLK_ICKCR_HSION;
+  }
+  else
+  {
+    /* Reset HSION bit */
+    CLK->ICKCR &= (uint8_t)(~CLK_ICKCR_HSION);
+  }
+}
+
+/**
+  * @brief  Adjusts the Internal High Speed oscillator (HSI) calibration value.
+  * @note   The calibration is used to compensate for the variations in voltage
+  *         and temperature that influence the frequency of the internal HSI RC.  
+  * @param  CLK_HSICalibrationValue : calibration trimming value.
+  *         This parameter must be a number between [(HSICALR regiter value) -12]
+  *         and [(HSICALR regiter value) + 8 ]  
+  * @note   Once HSITRIMR register configured, its value is used instead of the HSICALR
+  *         register values. 
+  * @retval None
+  */
+void CLK_AdjustHSICalibrationValue(uint8_t CLK_HSICalibrationValue)
+{
+  /* two consecutive write access to HSIUNLCKR register to unlock HSITRIMR */
+  CLK->HSIUNLCKR = 0xAC;
+  CLK->HSIUNLCKR = 0x35;
+
+  /* Store the new value */
+  CLK->HSITRIMR = (uint8_t)CLK_HSICalibrationValue;
+}
+
+/**
+  * @brief  Enables or disables the Internal Low Speed oscillator (LSI).
+  * @note   After enabling the LSI, the application software should wait on 
+  *         LSIRDY flag to be set indicating that LSI clock is stable and can
+  *         be used to clock the IWDG and/or the RTC.
+  * @note   LSI can not be disabled if used as system clock source, as active CCO 
+  *         source, as BEEP clock source while BEEPAHALT bit is set or, as RTC active 
+  *         clock source.     
+  * @param  NewState: new state of the LSI.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @note   When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
+  *         clock cycles. 
+  * @retval None
+  */
+void CLK_LSICmd(FunctionalState NewState)
+{
+
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Set LSION bit */
+    CLK->ICKCR |= CLK_ICKCR_LSION;
+  }
+  else
+  {
+    /* Reset LSION bit */
+    CLK->ICKCR &= (uint8_t)(~CLK_ICKCR_LSION);
+  }
+}
+
+/**
+  * @brief  Configures the External High Speed oscillator (HSE).
+  * @note   After enabling the HSE (CLK_HSE_ON or CLK_HSE_Bypass), the application
+  *         software should wait on HSERDY flag to be set indicating that HSE clock
+  *         is stable and can be used to clock the system.
+  * @note   HSE state can not be changed if it is used as system clock. In this case,
+  *         you have to select another source of the system clock then change 
+  *         the HSE state (ex. disable it).
+  * @note   The HSE is stopped by hardware when entering HALT and active HALT modes.  
+  * @param  CLK_HSE: specifies the new state of the HSE.
+  *         This parameter can be one of the following values:
+  *            @arg CLK_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
+  *                              6 HSE oscillator clock cycles.
+  *            @arg CLK_HSE_ON: turn ON the HSE oscillator
+  *            @arg CLK_HSE_Bypass: HSE oscillator bypassed with external clock
+  * @note   In case of Enabling HSE Bypass make sure that the HSE clock source is
+  *         not used by the RTC, output or involved in a switching operation.
+  * @retval None
+  */
+void CLK_HSEConfig(CLK_HSE_TypeDef CLK_HSE)
+{
+  /* Check the parameters */
+  assert_param(IS_CLK_HSE(CLK_HSE));
+
+  /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
+  /* Reset HSEON bit */
+  CLK->ECKCR &= (uint8_t)~CLK_ECKCR_HSEON;
+
+  /* Reset HSEBYP bit */
+  CLK->ECKCR &= (uint8_t)~CLK_ECKCR_HSEBYP;
+
+  /* Configure HSE */
+  CLK->ECKCR |= (uint8_t)CLK_HSE;
+}
+
+/**
+  * @brief  Configures the External Low Speed oscillator (LSE).
+  * @note   After enabling the LSE (CLK_LSE_ON or CLK_LSE_Bypass), the application
+  *         software should wait on LSERDY flag to be set indicating that LSE clock
+  *         is stable and can be used to clock the RTC.
+  * @param  CLK_LSE: specifies the new state of the LSE.
+  *         This parameter can be one of the following values:
+  *            @arg CLK_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
+  *                              6 LSE oscillator clock cycles.
+  *            @arg CLK_LSE_ON: turn ON the LSE oscillator
+  *            @arg CLK_LSE_Bypass: LSE oscillator bypassed with external clock
+  * @note   In case of Enabling LSE Bypass make sure that the LSE clock source is
+  *         not used by the RTC, output or involved in a switching operation.  
+  * @retval None
+  */
+void CLK_LSEConfig(CLK_LSE_TypeDef CLK_LSE)
+{
+  /* Check the parameters */
+  assert_param(IS_CLK_LSE(CLK_LSE));
+
+  /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/
+  /* Reset LSEON bit */
+  CLK->ECKCR &= (uint8_t)~CLK_ECKCR_LSEON;
+
+  /* Reset LSEBYP bit */
+  CLK->ECKCR &= (uint8_t)~CLK_ECKCR_LSEBYP;
+
+  /* Configure LSE */
+  CLK->ECKCR |= (uint8_t)CLK_LSE;
+
+}
+
+/**
+  * @brief  Enables the Clock Security System.
+  * @note   If a failure is detected on the HSE oscillator clock, this oscillator
+  *         is automatically disabled and an interrupt is generated to inform the
+  *         software about the failure allowing the MCU to perform rescue operations.
+  * @note   Once CSS is enabled it cannot be disabled until the next reset.  
+  * @param  None
+  * @retval None
+  */
+void CLK_ClockSecuritySystemEnable(void)
+{
+  /* Set CSSEN bit */
+  CLK->CSSR |= CLK_CSSR_CSSEN;
+}
+
+/**
+  * @brief  Enables the Clock Security System deglitcher system.
+  * @param  None
+  * @retval None
+  */
+void CLK_ClockSecuritySytemDeglitchCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Set CSSDGON bit */
+    CLK->CSSR |= CLK_CSSR_CSSDGON;
+  }
+  else
+  {
+    /* Reset CSSDGON  bit */
+    CLK->CSSR &= (uint8_t)(~CLK_CSSR_CSSDGON);
+  }
+}
+
+/**
+  * @brief  Selects the clock source to output on CCO pin(PC4).
+  * @note   PC4 should be configured output push-pull with the speed that matches 
+  *         maximum output speed of the desired clock.
+  * @param  CLK_CCOSource: specifies the clock source to output.
+  *          This parameter can be one of the following values:
+  *            @arg CLK_CCOSource_Off: No clock selected as CCO source
+  *            @arg CLK_CCOSource_HSI: HSI clock selected as CCO source
+  *            @arg CLK_CCOSource_LSI: LSI clock selected as CCO source
+  *            @arg CLK_CCOSource_LSE: LSE clock selected as CCO source
+  *            @arg CLK_CCOSource_HSE: HSE clock selected as CCO source
+  * @param  CLK_CCODiv: specifies the CCO prescaler.
+  *          This parameter can be one of the following values:
+  *            @arg CLK_CCODiv_1: no division applied to CCO clock
+  *            @arg CLK_CCODiv_2: division by 2 applied to CCO clock
+  *            @arg CLK_CCODiv_4: division by 4 applied to CCO clock
+  *            @arg CLK_CCODiv_8: division by 8 applied to CCO clock
+  *            @arg CLK_CCODiv_16: division by 16 applied to CCO clock
+  *            @arg CLK_CCODiv_32: division by 32 applied to CCO clock
+  *            @arg CLK_CCODiv_64: division by 64 applied to CCO clock
+  * @retval None
+  */
+void CLK_CCOConfig(CLK_CCOSource_TypeDef CLK_CCOSource, CLK_CCODiv_TypeDef CLK_CCODiv)
+{
+  /* check teh parameters */
+  assert_param(IS_CLK_OUTPUT(CLK_CCOSource));
+  assert_param(IS_CLK_OUTPUT_DIVIDER(CLK_CCODiv));
+
+  /* Selects the source provided on cco_ck output and its divider*/
+  CLK->CCOR = (uint8_t)((uint8_t)CLK_CCOSource | (uint8_t)CLK_CCODiv);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CLK_Group2 System clock configuration functions
+ *  @brief   System clock configuration functions
+ *
+@verbatim   
+ ===============================================================================
+                    System clock configuration functions
+ ===============================================================================  
+
+  This section provides functions allowing to configure the System clock.
+  
+  1. Several clock sources can be used to drive the System clock (SYSCLK): HSI,
+     HSE, LSI and LSE.
+     You can use "CLK_GetClocksFreq()" function to retrieve the frequencies of these clocks.  
+
+@note All the peripheral clocks are derived from the System clock (SYSCLK) except:
+       - BEEP: the Beeper clock can be derived either from a LSE or LSI clock sources. 
+          You have to use CLK_BEEPClockConfig() function to configure this clock. 
+       - RTC: the RTC clock can be derived either from the LSI, LSE, HSI or HSE clock
+          divided by 1 to 64. You have to use CLK_RTCClockConfig() functions to 
+          configure this clock.
+       - LCD : LCD clock is the RTC Clock divided by 2. 
+       - IWDG clock which is always the LSI clock.
+       
+  2. The maximum frequency of the SYSCLK is 16 MHz.
+
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Configures the system clock (SYSCLK).
+  * @note   The HSI is used (enabled by hardware) as system clock source after
+  *         startup from Reset, wake-up from Halt and active Halt modes, or in case
+  *         of failure of the HSE used as system clock (if the Clock Security System CSS is enabled).
+  * @note   A switch from one clock source to another occurs only if the target
+  *         clock source is ready (clock stable after startup delay or PLL locked). 
+  *         You can use CLK_GetSYSCLKSource() function to know which clock is
+  *         currently used as system clock source. 
+  * @param  CLK_SYSCLKSource: specifies the clock source used as system clock.
+  *          This parameter can be one of the following values:
+  *            @arg CLK_SYSCLKSource_HSI: HSI selected as system clock source
+  *            @arg CLK_SYSCLKSource_HSE: HSE selected as system clock source
+  *            @arg CLK_SYSCLKSource_LSI: LSI selected as system clock source
+  *            @arg CLK_SYSCLKSource_LSE: LSE selected as system clock source
+  * @retval None
+  */
+void CLK_SYSCLKSourceConfig(CLK_SYSCLKSource_TypeDef CLK_SYSCLKSource)
+{
+  /* check teh parameters */
+  assert_param(IS_CLK_SOURCE(CLK_SYSCLKSource));
+
+  /* Selection of the target clock source */
+  CLK->SWR = (uint8_t)CLK_SYSCLKSource;
+}
+
+/**
+  * @brief  Returns the clock source used as system clock.
+  * @param  None
+  * @retval Clock used as System clock (SYSCLK) source.
+  *         The returned value can be one of the following:
+  *         - CLK_SYSCLKSource_HSI: HSI used as system clock
+  *         - CLK_SYSCLKSource_LSI: LSI used as system clock
+  *         - CLK_SYSCLKSource_HSE: HSE used as system clock
+  *         - CLK_SYSCLKSource_LSE: LSE used as system clock
+  */
+CLK_SYSCLKSource_TypeDef CLK_GetSYSCLKSource(void)
+{
+  return ((CLK_SYSCLKSource_TypeDef)(CLK->SCSR));
+}
+
+/**
+  * @brief  Returns the frequencies of different the SYSCLK
+  * 
+  * @note   The system frequency computed by this function is not the real 
+  *         frequency in the chip. It is calculated based on the predefined 
+  *         constant and the selected clock source:
+  * @note     If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
+  * @note     If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
+  * @note     If SYSCLK source is LSE, function returns values based on LSE_VALUE(***) 
+  * @note     If SYSCLK source is LSI, function returns values based on LSI_VALUE(****)
+  * @note     (*) HSI_VALUE is a constant defined in stm8l15x.h file (default value
+  *               16 MHz) but the real value may vary depending on the variations
+  *               in voltage and temperature.
+  * @note     (**) HSE_VALUE is a constant defined in stm8l15x.h file (default value
+  *                16 MHz), user has to ensure that HSE_VALUE is same as the real
+  *                frequency of the crystal used. Otherwise, this function may
+  *                have wrong result.
+  * @note     (***) LSI_VALUE is a constant defined in stm8l15x.h file (default value
+  *               38 KHz) but the real value may vary depending on the variations
+  *               in voltage and temperature.
+  * @note     (****) LSE_VALUE is a constant defined in stm8l15x.h file (default value
+  *                32,768 KHz), user has to ensure that LSE_VALUE is same as the real
+  *                frequency of the crystal used. Otherwise, this function may
+  *                have wrong result.
+  *
+  * @note   The result of this function could be not correct when using fractional
+  *         value for HSE crystal.
+  *   
+  * @param  None
+  *
+  * @note   This function can be used by the user application to compute the 
+  *         baudrate for the communication peripherals or configure other parameters.
+  * @note   Each time SYSCLK clock changes, this function must be called to update
+  *         the returned value. Otherwise, any configuration based on this 
+  *         function will be incorrect.
+  *
+  * @retval System Clock frequency value
+  */
+uint32_t CLK_GetClockFreq(void)
+{
+  uint32_t clockfrequency = 0;
+  uint32_t sourcefrequency = 0;
+  CLK_SYSCLKSource_TypeDef clocksource = CLK_SYSCLKSource_HSI;
+  uint8_t tmp = 0, presc = 0;
+
+  /* Get SYSCLK source. */
+  clocksource = (CLK_SYSCLKSource_TypeDef)CLK->SCSR;
+
+  if ( clocksource == CLK_SYSCLKSource_HSI)
+  {
+    sourcefrequency = HSI_VALUE;
+  }
+  else if ( clocksource == CLK_SYSCLKSource_LSI)
+  {
+    sourcefrequency = LSI_VALUE;
+  }
+  else if ( clocksource == CLK_SYSCLKSource_HSE)
+  {
+    sourcefrequency = HSE_VALUE;
+  }
+  else
+  {
+    clockfrequency = LSE_VALUE;
+  }
+
+  /* Get System clock divider factor*/
+  tmp = (uint8_t)(CLK->CKDIVR & CLK_CKDIVR_CKM);
+  presc = SYSDivFactor[tmp];
+
+  /* Get System clock clcok frequency */
+  clockfrequency = sourcefrequency / presc;
+
+  return((uint32_t)clockfrequency);
+}
+
+/**
+  * @brief  Configures the System clock (SYSCLK) dividers.
+  * @param  CLK_SYSCLKDiv : Specifies the system clock divider to apply.
+  *          This parameter can be one of the following values:
+  *            @arg CLK_SYSCLKDiv_1 
+  *            @arg CLK_SYSCLKDiv_2
+  *            @arg CLK_SYSCLKDiv_4
+  *            @arg CLK_SYSCLKDiv_8
+  *            @arg CLK_SYSCLKDiv_16
+  *            @arg CLK_SYSCLKDiv_64
+  *            @arg CLK_SYSCLKDiv_128
+  * @retval None
+  */
+void CLK_SYSCLKDivConfig(CLK_SYSCLKDiv_TypeDef CLK_SYSCLKDiv)
+{
+  /* check the parameters */
+  assert_param(IS_CLK_SYSTEM_DIVIDER(CLK_SYSCLKDiv));
+
+  CLK->CKDIVR = (uint8_t)(CLK_SYSCLKDiv);
+}
+
+/**
+  * @brief  Enables or disables the clock switch execution.
+  * @param  NewState : new state of clock switch, value accepted ENABLE, DISABLE.
+  * @retval None
+  */
+void CLK_SYSCLKSourceSwitchCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Set SWEN bit */
+    CLK->SWCR |= CLK_SWCR_SWEN;
+  }
+  else
+  {
+    /* Reset SWEN  bit */
+    CLK->SWCR &= (uint8_t)(~CLK_SWCR_SWEN);
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CLK_Group3 Peripheral clocks configuration functions
+ *  @brief   Peripheral clocks configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+                   Peripheral clocks configuration functions
+ ===============================================================================  
+
+  This section provides functions allowing to configure the Peripheral clocks. 
+  
+  1. The RTC clock which is derived from the LSI, LSE, HSI or HSE clock divided by 1 to 64.
+     
+  2. The BEEP clock which is derived from the LSI or LSE clocks.
+
+  3. After restart from Reset or wakeup from HALT, all peripherals are off
+     Before to start using a peripheral you have to enable its interface clock. 
+     You can do this using CLK_AHBPeriphClockCmd()
+     , CLK_APB2PeriphClockCmd() and CLK_APB1PeriphClockCmd() functions.
+     
+  4. To reset the peripherals configuration (to the default state after device reset)
+     you can use CLK_PeripheralClockConfig() function.  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures the RTC clock (RTCCLK).
+  * @param  CLK_RTCCLKSource: specifies the RTC clock source.
+  *          This parameter can be one of the following values:
+  *            @arg CLK_RTCCLKSource_Off: RTC clock Off  
+  *            @arg CLK_RTCCLKSource_LSE: LSE selected as RTC clock
+  *            @arg CLK_RTCCLKSource_LSI: LSI selected as RTC clock
+  *            @arg CLK_RTCCLKSource_HSE: HSE selected as RTC clock
+  *            @arg CLK_RTCCLKSource_HSI: HSI selected as RTC clock  
+  *  
+  * @param  CLK_RTCCLKDiv: specifies the RTC clock source divider.
+  *          This parameter can be one of the following values:
+  *            @arg CLK_RTCCLKDiv_1: Clock RTC Div 1  
+  *            @arg CLK_RTCCLKDiv_2: Clock RTC Div 2
+  *            @arg CLK_RTCCLKDiv_4: Clock RTC Div 4
+  *            @arg CLK_RTCCLKDiv_8: Clock RTC Div 8
+  *            @arg CLK_RTCCLKDiv_16: Clock RTC Div 16
+  *            @arg CLK_RTCCLKDiv_32: Clock RTC Div 32
+  *            @arg CLK_RTCCLKDiv_64: Clock RTC Div 64
+  *  
+  * @note   If the LSE or LSI is used as RTC clock source, the RTC continues to
+  *         work in HALT and Active HALT modes, and can be used as wakeup source.
+  *         However, when the HSE clock is used as RTC clock source.    
+  * @note   The maximum input clock frequency for RTC is 1MHz (when using HSE/HSI as
+  *         RTC clock source).
+  *  
+  * @retval None
+  */
+void CLK_RTCClockConfig(CLK_RTCCLKSource_TypeDef CLK_RTCCLKSource, CLK_RTCCLKDiv_TypeDef CLK_RTCCLKDiv)
+{
+  /* check the parameters */
+  assert_param(IS_CLK_CLOCK_RTC(CLK_RTCCLKSource));
+  assert_param(IS_CLK_CLOCK_RTC_DIV(CLK_RTCCLKDiv));
+
+  /* Selects the source provided on to RTC and its divider*/
+  CLK->CRTCR = (uint8_t)((uint8_t)CLK_RTCCLKSource | (uint8_t)CLK_RTCCLKDiv);
+}
+
+/**
+  * @brief  Configures the BEEP clock (BEEPCLK).
+  * @param  CLK_BEEPCLKSource: specifies the BEEP clock source.
+  *          This parameter can be one of the following values:
+  *            @arg CLK_BEEPCLKSource_Off: BEEP clock Off  
+  *            @arg CLK_BEEPCLKSource_LSE: LSE selected as BEEP clock
+  *            @arg CLK_BEEPCLKSource_LSI: LSI selected as BEEP clock  
+  * @retval None
+  */
+void CLK_BEEPClockConfig(CLK_BEEPCLKSource_TypeDef CLK_BEEPCLKSource)
+{
+  /* check the parameters */
+  assert_param(IS_CLK_CLOCK_BEEP(CLK_BEEPCLKSource));
+
+  /* Selects the source provided to BEEP*/
+  CLK->CBEEPR = (uint8_t)(CLK_BEEPCLKSource);
+
+}
+
+/**
+* @brief  Enables or disables the specified peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it.   
+  * @param  CLK_Peripheral: specifies the peripheral to gate its clock.
+  *          This parameter can be any combination of the following values:
+  *            @arg CLK_Peripheral_TIM2:       TIM2 clock
+  *            @arg CLK_Peripheral_TIM3:       TIM3 clock 
+  *            @arg CLK_Peripheral_TIM4:       TIM4 clock
+  *            @arg CLK_Peripheral_I2C1:       I2C1 clock
+  *            @arg CLK_Peripheral_SPI1:       SPI1 clock
+  *            @arg CLK_Peripheral_USART1:     USART1 clock
+  *            @arg CLK_Peripheral_BEEP:       BEEP clock
+  *            @arg CLK_Peripheral_DAC:        DAC clock
+  *            @arg CLK_Peripheral_ADC1:       ADC1 clock
+  *            @arg CLK_Peripheral_TIM1:       TIM1 clock
+  *            @arg CLK_Peripheral_RTC:        RTC clock
+  *            @arg CLK_Peripheral_LCD:        LCD clock
+  *            @arg CLK_Peripheral_DMA1:       DMA1 clock
+  *            @arg CLK_Peripheral_COMP:       COMP clock
+  *            @arg CLK_Peripheral_BOOTROM:    BOOTROM clock
+  *            @arg CLK_Peripheral_AES:        AES clock
+  *            @arg CLK_Peripheral_TIM5:       TIM5 clock
+  *            @arg CLK_Peripheral_SPI2:       SPI2 clock
+  *            @arg CLK_Peripheral_USART2:     USART2 clock
+  *            @arg CLK_Peripheral_USART3:     USART3 clock
+  *            @arg CLK_Peripheral_CSSLSE:     CSS on LSE clock
+  * @param  NewState: new state of the specified peripheral clock.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void CLK_PeripheralClockConfig(CLK_Peripheral_TypeDef CLK_Peripheral, FunctionalState NewState)
+{
+  uint8_t reg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_CLK_PERIPHERAL(CLK_Peripheral));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* get flag register */
+  reg = (uint8_t)((uint8_t)CLK_Peripheral & (uint8_t)0xF0);
+
+  if ( reg == 0x00)
+  {
+    if (NewState != DISABLE)
+    {
+      /* Enable the peripheral Clock */
+      CLK->PCKENR1 |= (uint8_t)((uint8_t)1 << ((uint8_t)CLK_Peripheral & (uint8_t)0x0F));
+    }
+    else
+    {
+      /* Disable the peripheral Clock */
+      CLK->PCKENR1 &= (uint8_t)(~(uint8_t)(((uint8_t)1 << ((uint8_t)CLK_Peripheral & (uint8_t)0x0F))));
+    }
+  }
+  else if (reg == 0x10)
+  {
+    if (NewState != DISABLE)
+    {
+      /* Enable the peripheral Clock */
+      CLK->PCKENR2 |= (uint8_t)((uint8_t)1 << ((uint8_t)CLK_Peripheral & (uint8_t)0x0F));
+    }
+    else
+    {
+      /* Disable the peripheral Clock */
+      CLK->PCKENR2 &= (uint8_t)(~(uint8_t)(((uint8_t)1 << ((uint8_t)CLK_Peripheral & (uint8_t)0x0F))));
+    }
+  }
+  else
+  {
+    if (NewState != DISABLE)
+    {
+      /* Enable the peripheral Clock */
+      CLK->PCKENR3 |= (uint8_t)((uint8_t)1 << ((uint8_t)CLK_Peripheral & (uint8_t)0x0F));
+    }
+    else
+    {
+      /* Disable the peripheral Clock */
+      CLK->PCKENR3 &= (uint8_t)(~(uint8_t)(((uint8_t)1 << ((uint8_t)CLK_Peripheral & (uint8_t)0x0F))));
+    }
+  }
+}
+
+/**
+  * @}
+  */
+  
+/** @defgroup CLK_Group4 CSS on LSE configuration functions
+ *  @brief   CSS on LSE configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+                        CSS on LSE configuration functions
+ ===============================================================================  
+
+  This section provides functions allowing to configure the CSS on LSE capability. 
+  
+  1. The LSE crystal clock source failures can be monitored when used as RTC clock
+     by the mean of the LSI oscillator.
+     
+  2. The CSS on LSE is a feature implemented externally to RTC peripheral and though 
+     has no impact the clock controller registers.
+
+  3. To enable the CSS on LSE you can use CLK_LSEClockSecuritySystemEnable() function
+     
+  4. To configure the action to perform at RTC clock failure you can use 
+     CLK_RTCCLKSwitchOnLSEFailureEnable() function that allows to switch the RTC clock
+     from LSE to LSI.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables the clock CSS on LSE.
+  * @note   Once Enabled, only POR can Disable it.
+  * @param  None
+  * @retval None
+  */
+void CLK_LSEClockSecuritySystemEnable(void)
+{
+  /* Set CSSEN bit */
+  CSSLSE->CSR |= CSSLSE_CSR_CSSEN;
+}
+
+/**
+  * @brief  Enables RTC clock switch to LSI in case of LSE failure.
+  * @note   Once Enabled, only POR can Disable it.
+  * @param  None
+  * @retval None
+  */
+void CLK_RTCCLKSwitchOnLSEFailureEnable(void)
+{
+  /* Set SWITCHEN bit */
+  CSSLSE->CSR |= CSSLSE_CSR_SWITCHEN;
+}
+
+/**
+  * @}
+  */
+  
+/** @defgroup CLK_Group5 Low power clock configuration functions
+ *  @brief   Low power clock configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+                      Low power clock configuration functions
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures clock during halt and active halt modes.
+  * @param  CLK_Halt : Specifies the clock state and wake-up mode from halt way.
+  *         This parameter can be a value of @ref CLK_Halt_TypeDef.
+  * @param  NewState : Specifies the System clock (SYSCLK) state in active halt mode.
+  *         This parameter can be ENABLE or DISABLE.
+  * @retval None
+  */
+void CLK_HaltConfig(CLK_Halt_TypeDef CLK_Halt, FunctionalState NewState)
+{
+  /* check the parameters */
+  assert_param(IS_CLK_HALT(CLK_Halt));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    CLK->ICKCR |= (uint8_t)(CLK_Halt);
+  }
+  else
+  {
+    CLK->ICKCR &= (uint8_t)(~CLK_Halt);
+  }
+}
+
+/**
+  * @brief  Configures the main voltage regulator
+  * @param  NewState: specifies the MVR  state.
+  *         This parameter can be one of the following values:
+  *         - DISABLE: MVR disabled;
+  *         - ENABLE:  MVR enabled.
+  * @retval None
+  */
+void CLK_MainRegulatorCmd(FunctionalState NewState)
+{
+  /* check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Reset REGUOFF bit */
+    CLK->REGCSR &= (uint8_t)(~CLK_REGCSR_REGOFF);
+  }
+  else
+  {
+    /* Set REGUOFF bit */
+    CLK->REGCSR |= CLK_REGCSR_REGOFF;
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CLK_Group6 Interrupts and flags management functions
+ *  @brief   Interrupts and flags management functions 
+ *
+@verbatim   
+ ===============================================================================
+                   Interrupts and flags management functions
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+ /**
+  * @brief  Enables or disables the specified CLK interrupts.
+  * @param  CLK_IT: specifies the CLK interrupt sources to be enabled or disabled.
+  *          This parameter can be any combination of the following values:
+  *            @arg CLK_IT_CSSD: Clock security system detection interrupt
+  *            @arg CLK_IT_SWIF: Clock switch interrupt 
+  *            @arg CLK_IT_LSECSSF: LSE Clock security system detection interrupt
+  * @param  NewState: new state of the specified CLK interrupts.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void CLK_ITConfig(CLK_IT_TypeDef CLK_IT, FunctionalState NewState)
+{
+
+  /* check the parameters */
+  assert_param(IS_CLK_IT(CLK_IT));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    if (CLK_IT == CLK_IT_SWIF)
+    {
+      /* Enable the clock switch interrupt */
+      CLK->SWCR |= CLK_SWCR_SWIEN;
+    }
+    else if (CLK_IT == CLK_IT_LSECSSF)
+    {
+      /* Enable the CSS on LSE  interrupt */
+      CSSLSE->CSR |= CSSLSE_CSR_CSSIE;
+    }
+    else
+    {
+      /* Enable the clock security system detection interrupt */
+      CLK->CSSR |= CLK_CSSR_CSSDIE;
+    }
+  }
+  else  /*(NewState == DISABLE)*/
+  {
+    if (CLK_IT == CLK_IT_SWIF)
+		{
+      /* Disable the clock switch interrupt */
+      CLK->SWCR  &= (uint8_t)(~CLK_SWCR_SWIEN);
+    }
+    else if (CLK_IT == CLK_IT_LSECSSF)
+    {
+      /* Disable the CSS on LSE  interrupt */
+      CSSLSE->CSR &= (uint8_t)(~CSSLSE_CSR_CSSIE);
+    }
+    else
+    {
+      /* Disable the clock security system detection interrupt */
+      CLK->CSSR &= (uint8_t)(~CLK_CSSR_CSSDIE);
+    }
+  }
+}
+
+/**
+  * @brief  Checks whether the specified CLK flag is set or not.
+  * @param  CLK_FLAG: specifies the flag to check.
+  *          This parameter can be one of the following values:
+  *            @arg CLK_FLAG_LSIRDY: LSI oscillator clock ready
+  *            @arg CLK_FLAG_HSIRDY: HSI oscillator clock ready
+  *            @arg CLK_FLAG_HSERDY: HSE oscillator clock ready
+  *            @arg CLK_FLAG_SWBSY: Switch busy
+  *            @arg CLK_FLAG_CSSD: Clock security system detection
+  *            @arg CLK_FLAG_AUX: Auxiliary oscillator connected to master clock
+  *            @arg CLK_FLAG_LSERDY: LSE oscillator clock ready
+  *            @arg CLK_FLAG_CCOBSY: Configurable clock output busy
+  *            @arg CLK_FLAG_RTCSWBSY: RTC clock busy in switch
+  *            @arg CLK_FLAG_EEREADY: Flash program memory and Data EEPROM ready
+  *            @arg CLK_FLAG_EEBUSY: Flash program memory and Data EEPROM busy
+  *            @arg CLK_FLAG_LSEPD: LSE power-down
+  *            @arg CLK_FLAG_LSIPD: LSI power-down
+  *            @arg CLK_FLAG_HSEPD: HSE power-down
+  *            @arg CLK_FLAG_HSIPD: HSI power-down
+  *            @arg CLK_FLAG_REGREADY: REGREADY
+  *            @arg CLK_FLAG_BEEPSWBSY: BEEP clock busy in switch
+  *            @arg CLK_FLAG_LSECSSF: CSS on LSE detection
+  *            @arg CLK_FLAG_RTCCLKSWF: RTCCLK switch completed on LSE failure
+  * @retval The new state of CLK_FLAG (SET or RESET).
+  */
+FlagStatus CLK_GetFlagStatus(CLK_FLAG_TypeDef CLK_FLAG)
+{
+  uint8_t reg = 0;
+  uint8_t pos = 0;
+  FlagStatus bitstatus = RESET;
+
+  /* check the parameters */
+  assert_param(IS_CLK_FLAGS(CLK_FLAG));
+
+  /* get flag register */
+  reg = (uint8_t)((uint8_t)CLK_FLAG & (uint8_t)0xF0);
+
+  /* get flag position */
+  pos = (uint8_t)((uint8_t)CLK_FLAG & (uint8_t)0x0F);
+
+  if (reg == 0x00) /* The flag to check is in CRTC Rregister */
+  {
+    reg = CLK->CRTCR;
+  }
+  else if (reg == 0x10) /* The flag to check is in ICKCR register */
+  {
+    reg = CLK->ICKCR;
+  }
+  else if (reg == 0x20) /* The flag to check is in CCOR register */
+  {
+    reg = CLK->CCOR;
+  }
+  else if (reg == 0x30) /* The flag to check is in ECKCR register */
+  {
+    reg = CLK->ECKCR;
+  }
+  else if (reg == 0x40) /* The flag to check is in SWCR register */
+  {
+    reg = CLK->SWCR;
+  }
+  else if (reg == 0x50) /* The flag to check is in CSSR register */
+  {
+    reg = CLK->CSSR;
+  }
+  else if (reg == 0x70) /* The flag to check is in REGCSR register */
+  {
+    reg = CLK->REGCSR;
+  }
+  else if (reg == 0x80) /* The flag to check is in CSSLSE_CSRregister */
+  {
+    reg = CSSLSE->CSR;
+  }
+  else /* The flag to check is in CBEEPR register */
+  {
+    reg = CLK->CBEEPR;
+  }
+
+
+  if ((reg & (uint8_t)((uint8_t)1 << (uint8_t)pos)) != (uint8_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+
+  /* Return the flag status */
+  return((FlagStatus)bitstatus);
+}
+
+/**
+  * @brief  Clears the CSS LSE Flag.
+  * @param  None
+  * @retval None
+  */
+void CLK_ClearFlag(void)
+{
+
+  /* Clear the clock security system on LSE  detection Flag */
+  CSSLSE->CSR &= (uint8_t)(~CSSLSE_CSR_CSSF);
+}
+
+/**
+  * @brief  Checks whether the specified CLK interrupt has occurred or not.
+  * @param  CLK_IT: specifies the CLK interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg CLK_IT_SWIF: LSI ready interrupt
+  *            @arg CLK_IT_LSECSSF: LSE ready interrupt
+  *            @arg CLK_IT_CSSD: HSI ready interrupt
+  * @retval The new state of CLK_IT (SET or RESET).
+  */
+ITStatus CLK_GetITStatus(CLK_IT_TypeDef CLK_IT)
+{
+
+  ITStatus bitstatus = RESET;
+
+  /* check the parameters */
+  assert_param(IS_CLK_IT(CLK_IT));
+
+  if (CLK_IT == CLK_IT_SWIF)
+  {
+    /* Check the status of the clock switch interrupt */
+    if ((CLK->SWCR & (uint8_t)CLK_IT) == (uint8_t)0x0C)
+    {
+      bitstatus = SET;
+    }
+    else
+    {
+      bitstatus = RESET;
+    }
+  }
+  else if (CLK_IT == CLK_IT_LSECSSF)
+  {
+    /* Check the status of the clock security system on LSE interrupt */
+    if ((CSSLSE->CSR & (uint8_t)CLK_IT) == (uint8_t)0x0C)
+    {
+      bitstatus = SET;
+    }
+    else
+    {
+      bitstatus = RESET;
+    }
+  }
+  else /* CLK_IT == CLK_IT_CSSD */
+  {
+    /* Check the status of the security system detection interrupt */
+    if ((CLK->CSSR & (uint8_t)CLK_IT) == (uint8_t)0x0C)
+    {
+      bitstatus = SET;
+    }
+    else
+    {
+      bitstatus = RESET;
+    }
+  }
+
+  /* Return the CLK_IT status */
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the CLK's interrupt pending bits.
+  * @param  CLK_IT: specifies the interrupt pending bit to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg CLK_IT_SWIF: Clock switch interrupt
+  *            @arg CLK_IT_LSECSSF: LSE Clock security system detection interrupt
+  * @retval None
+  */
+void CLK_ClearITPendingBit(CLK_IT_TypeDef CLK_IT)
+{
+
+  /* check the parameters */
+  assert_param(IS_CLK_CLEAR_IT(CLK_IT));
+
+  if ((uint8_t)((uint8_t)CLK_IT & (uint8_t)0xF0) == (uint8_t)0x20)
+  {
+    /* Clear the status of the clock security system on LSE interrupt */
+    CSSLSE->CSR &= (uint8_t)(~CSSLSE_CSR_CSSF);
+  }
+  else
+  {
+    /* Clear the status of the clock switch interrupt */
+    CLK->SWCR &= (uint8_t)(~CLK_SWCR_SWIF);
+  }
+}
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+  
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_comp.c b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_comp.c
new file mode 100755
index 0000000..89356bd
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_comp.c
@@ -0,0 +1,725 @@
+/**
+  ******************************************************************************
+  * @file    stm8l15x_comp.c
+  * @author  MCD Application Team
+  * @version V1.6.0
+  * @date    28-June-2013
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the comparators (COMP1 and COMP2) peripheral: 
+  *           - Comparators configuration
+  *           - Window mode control
+  *           - Internal Reference Voltage (VREFINT) output
+  *           - Comparator channels trigger configuration
+  *           - Interrupts and flags management  
+  *           
+  *  @verbatim
+  *
+  *          ===================================================================
+  *                                 How to use this driver
+  *          ===================================================================
+  *          1- Enable comparators clock using CLK_PeripheralClockConfig(CLK_Peripheral_COMP, ENABLE);
+  *            
+  *          When using COMP1:
+  *          2- Connect internal reference voltage to COMP1 inverting input
+  *             using COMP_VrefintToCOMP1Connect()
+  *          3- Close the analog switch number 14 using SYSCFG_RIAnalogSwitchConfig()
+  *          4- Close the analog switch that corresponds to the pin to be used as 
+  *             non inverting input using SYSCFG_RIAnalogSwitchConfig()
+  *          5- Close the I/O switch of the pin to be used as non inverting input
+  *             using SYSCFG_RIIOSwitchConfig()
+  *          6- Configure the event detection using COMP_EdgeConfig()    
+  *
+  *          When using COMP2:
+  *          2- Select the COMP2 inverting input, configure the speed and COMP2
+  *             output redirection using COMP_Init()
+  *             If the inverting input is an external pin, close the I/O channel
+  *             switch using SYSCFG_RIIOSwitchConfig()
+  *          3- Close I/O Switch that corresponds to the selected pin as
+  *             comparator 2 non inverting input using SYSCFG_RIIOSwitchConfig()    
+  *          4- Configure the event detection using COMP_EdgeConfig()   
+  *
+  * @note
+  *          1- COMP1 comparator and ADC can't be used at the same time since
+  *             they share the same ADC switch matrix (analog switches).
+  *
+  *          2- When an I/O is used as comparator input, the corresponding GPIO 
+  *             registers should be configured in input floating.
+  *
+  *          3- Comparators outputs (CMP1OUT and CMP2OUT) are not mapped on
+  *             GPIO pin. They are only internal.
+  *             To get the comparator output level, use COMP_GetOutputLevel() function    
+  *  @endverbatim      
+  ******************************************************************************
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ****************************************************************************** 
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm8l15x_comp.h"
+
+/** @addtogroup STM8L15x_StdPeriph_Driver
+  * @{
+  */
+  
+/** @defgroup COMP 
+  * @brief COMP driver modules
+  * @{
+  */ 
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup COMP_Private_Functions
+  * @{
+  */
+
+/** @defgroup COMP_Group1 Initialization and Configuration functions
+ *  @brief   Initialization and Configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+                        Initialization and Configuration functions
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the COMPx peripheral registers to their default reset values.
+  * @param  None.
+  * @retval None.
+  */
+void COMP_DeInit(void)
+{
+  /* Set COMP->CSR1 to reset value 0x00 */
+  COMP->CSR1 = (uint8_t) COMP_CSR1_RESET_VALUE;
+
+  /* Set COMP->CSR2 to reset value 0x00 */
+  COMP->CSR2 = (uint8_t) COMP_CSR2_RESET_VALUE;
+
+  /* Set COMP->CSR3 to reset value 0xC0 */
+  COMP->CSR3 = (uint8_t) COMP_CSR3_RESET_VALUE;
+
+  /* Set COMP->CSR4 to reset value 0x00 */
+  COMP->CSR4 = (uint8_t) COMP_CSR4_RESET_VALUE;
+
+  /* Set COMP->CSR5 to reset value 0x00 */
+  COMP->CSR5 = (uint8_t) COMP_CSR5_RESET_VALUE;
+}
+
+/**
+  * @brief  Initializes the comparator inverting input, output and speed.
+  * @note   This function configures only COMP2.
+  * @param  COMP_InvertingInput : selects the comparator inverting input.
+  *          This parameter can be one of the following values:
+  *            @arg COMP_InvertingInput_IO: Input/Output on comparator inverting input enable
+  *            @arg COMP_InvertingInput_VREFINT: VREFINT on comparator inverting input enable
+  *            @arg COMP_InvertingInput_3_4VREFINT: 3/4 VREFINT on comparator inverting input enable
+  *            @arg COMP_InvertingInput_1_2VREFINT: 1/2 VREFINT on comparator inverting input enable
+  *            @arg COMP_InvertingInput_1_4VREFINT: 1/4 VREFINT on comparator inverting input enable
+  *            @arg COMP_InvertingInput_DAC1: DAC1 output on comparator inverting input enable
+  *            @arg COMP_InvertingInput_DAC2: DAC2 output on comparator inverting input enable
+  * @param  COMP_OutputSelect : selects the comparator output
+  *          This parameter can be one of the following values:
+  *            @arg COMP_OutputSelect_TIM2IC2: COMP2 output connected to TIM2 Input Capture 2
+  *            @arg COMP_OutputSelect_TIM3IC2: COMP2 output connected to TIM3 Input Capture 2
+  *            @arg COMP_OutputSelect_TIM1BRK: COMP2 output connected to TIM1 Break Input
+  *            @arg COMP_OutputSelect_TIM1OCREFCLR: COMP2 output connected to TIM1 OCREF Clear
+  * @param  COMP_Speed selects the comparator speed
+  *          This parameter can be one of the following values:
+  *            @arg COMP_Speed_Slow: Comparator speed: slow
+  *            @arg COMP_Speed_Fast: Comparator speed: fast
+  * @retval None.
+  */
+void COMP_Init(COMP_InvertingInput_Typedef COMP_InvertingInput,
+               COMP_OutputSelect_Typedef COMP_OutputSelect, COMP_Speed_TypeDef COMP_Speed)
+{
+  /* Check the parameters */
+  assert_param(IS_COMP_INVERTING_INPUT(COMP_InvertingInput));
+  assert_param(IS_COMP_OUTPUT(COMP_OutputSelect));
+  assert_param(IS_COMP_SPEED(COMP_Speed));
+
+  /* Reset the INSEL[2:0] bits in CSR3 register */
+  COMP->CSR3 &= (uint8_t) (~COMP_CSR3_INSEL);
+  /* Select the comparator inverting input */
+  COMP->CSR3 |= (uint8_t) COMP_InvertingInput;
+
+  /* Reset the OUTSEL[1:0] bits in CSR3 register */
+  COMP->CSR3 &= (uint8_t) (~COMP_CSR3_OUTSEL);
+  /* Redirect the comparator output */
+  COMP->CSR3 |= (uint8_t) COMP_OutputSelect;
+
+  /* Reset the comparator speed bit */
+  COMP->CSR2 &= (uint8_t) (~COMP_CSR2_SPEED);
+  /* Select the comparator speed */
+  COMP->CSR2 |= (uint8_t) COMP_Speed;
+}
+
+/**
+  * @brief  Enables or disables connection between VREFINT and COMP1 inverting input.
+  * @param  NewState new state of the VREFINT connection to COMP1 inverting input.
+  *         This parameter can be ENABLE or DISABLE.
+  * @retval None
+  */
+void COMP_VrefintToCOMP1Connect(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the comparator */
+    COMP->CSR3 |= COMP_CSR3_VREFEN;
+  }
+  else
+  {
+    /* Disable the comparator */
+    COMP->CSR3 &= (uint8_t)(~COMP_CSR3_VREFEN);
+  }
+}
+
+/**
+  * @brief  Configures the COMP edge detection.
+  * @param  COMP_Selection: selects the comparator.
+  *          This parameter can be one of the following values:
+  *            @arg COMP_Selection_COMP1: Selection of Comparator 1
+  *            @arg COMP_Selection_COMP2: Selection of Comparator 2
+  * @param  COMP_Edge: This parameter can be one of the following values:
+  *            @arg COMP_Edge_Falling: Falling edge selection
+  *            @arg COMP_Edge_Rising: Rising edge selection  
+  *            @arg COMP_Edge_Rising_Falling: Rising and Falling edge selection
+  * @retval None.
+  */
+void COMP_EdgeConfig(COMP_Selection_TypeDef COMP_Selection, COMP_Edge_TypeDef COMP_Edge)
+{
+  /* Check the parameters */
+  assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
+  assert_param(IS_COMP_EDGE(COMP_Edge));
+
+  /* Check if comparator 1 is selected */
+  if (COMP_Selection == COMP_Selection_COMP1)
+  {
+    /* Reset the comparator 1 edge control bits */
+    COMP->CSR1 &= (uint8_t) (~COMP_CSR1_CMP1);
+
+    /* Select the edge detection of comparator 1 output */
+    COMP->CSR1 |= (uint8_t) COMP_Edge;
+  }
+  /* The comparator 2 is selected */
+  else
+  {
+    /* Reset the comparator 2 edge control bits */
+    COMP->CSR2 &= (uint8_t) (~COMP_CSR2_CMP2);
+
+    /* Select the edge detection of comparator 2 output */
+    COMP->CSR2 |= (uint8_t) COMP_Edge;
+  }
+}
+
+/**
+  * @brief  Returns the output level of the comparator.
+  * @note   Comparators outputs aren't available on GPIO (outputs levels are 
+  *         only internal).
+  * @param  COMP_Selection: selects the comparator.
+  *          This parameter can be one of the following values:
+  *            @arg COMP_Selection_COMP1: Selection of Comparator 1
+  *            @arg COMP_Selection_COMP2: Selection of Comparator 2
+  * @retval Returns the comparator output level
+  *          This value can be one of the following:
+  *            - COMP_OutputLevel_Low: Comparator output level is low
+  *            - COMP_OutputLevel_High: Comparator output level is high
+  */
+COMP_OutputLevel_TypeDef COMP_GetOutputLevel(COMP_Selection_TypeDef COMP_Selection)
+{
+  uint8_t compout;
+
+  /* Check the parameters */
+  assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
+
+  /* Check if Comparator 1 is selected */
+  if (COMP_Selection == COMP_Selection_COMP1)
+  {
+    /* Check if comparator 1 output level is high */
+    if ((COMP->CSR1 & COMP_CSR1_CMP1OUT) != (uint8_t) RESET)
+    {
+      /* Get Comparator 1 output level */
+      compout = (COMP_OutputLevel_TypeDef) COMP_OutputLevel_High;
+    }
+    /* comparator 1 output level is low */
+    else
+    {
+      /* Get Comparator 1 output level */
+      compout = (COMP_OutputLevel_TypeDef) COMP_OutputLevel_Low;
+    }
+  }
+  /* Comparator 2 is selected */
+  else
+  {
+    /* Check if comparator 2 output level is high */
+    if ((COMP->CSR2 & COMP_CSR2_CMP2OUT) != (uint8_t) RESET)
+    {
+      /* Get Comparator output level */
+      compout = (COMP_OutputLevel_TypeDef) COMP_OutputLevel_High;
+    }
+    /* comparator 2 output level is low */
+    else
+    {
+      /* Get Comparator 2 output level */
+      compout = (COMP_OutputLevel_TypeDef) COMP_OutputLevel_Low;
+    }
+  }
+
+  /* Return the comparator output level */
+  return (COMP_OutputLevel_TypeDef)(compout);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup COMP_Group2 Window mode control function
+ *  @brief   Window mode control function 
+ *
+@verbatim   
+ ===============================================================================
+                              Window mode control function
+ ===============================================================================  
+
+  In window mode:
+      - COMP1 inverting input is fixed to VREFINT defining the first
+        threshold
+      - COMP2 inverting input is configurable (DAC_OUT1, VREFINT sub-multiples, ...)
+        defining the second threshold
+      - COMP1 and COMP2 non inverting inputs are connected together.
+         
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the window mode.
+  * @param  NewState new state of the window mode.
+  *         This parameter can be ENABLE or DISABLE.
+  * @retval None
+  */
+void COMP_WindowCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the window mode */
+    COMP->CSR3 |= (uint8_t) COMP_CSR3_WNDWE;
+  }
+  else
+  {
+    /* Disable the window mode */
+    COMP->CSR3 &= (uint8_t)(~COMP_CSR3_WNDWE);
+  }
+}
+/**
+  * @}
+  */
+  
+/** @defgroup COMP_Group3 Internal Reference Voltage output function
+ *  @brief   Internal Reference Voltage (VREFINT) output function 
+ *
+@verbatim   
+ ===============================================================================
+             Internal Reference Voltage (VREFINT) output function
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the output of the internal reference voltage.
+  * @param  NewState : new state of the Vrefint output.
+    *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void COMP_VrefintOutputCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the output of internal reference voltage */
+    COMP->CSR3 |= (uint8_t) COMP_CSR3_VREFOUTEN;
+  }
+  else
+  {
+    /* Disable the output of internal reference voltage */
+    COMP->CSR3 &= (uint8_t) (~COMP_CSR3_VREFOUTEN);
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup COMP_Group4 Comparator channels trigger configuration
+ *  @brief  Comparator channels trigger configuration
+ *
+@verbatim   
+ ===============================================================================
+                Comparator channels trigger configuration
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the schmitt trigger.
+  * @param  NewState : new state of the schmitt trigger.
+    *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void COMP_SchmittTriggerCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable Schmitt trigger on Input Output switches Channels */
+    COMP->CSR1 |= (uint8_t) COMP_CSR1_STE;
+  }
+  else
+  {
+    /* Enable Schmitt trigger on Input Output switches Channels */
+    COMP->CSR1 &= (uint8_t) (~COMP_CSR1_STE);
+  }
+}
+
+/**
+  * @brief  Enables or disables trigger on the specified input/output group.
+  * @param  COMP_TriggerGroup : specifies the input/output group
+  *          This parameter can be one of the following values:
+  *            @arg COMP_TriggerGroup_InvertingInput: Trigger on comparator 2 inverting input
+  *            @arg COMP_TriggerGroup_NonInvertingInput: Trigger on comparator 2 non inverting input
+  *            @arg COMP_TriggerGroup_VREFINTOutput: Trigger on VREFINT output
+  *            @arg COMP_TriggerGroup_DACOutput: Trigger on DAC output      
+  * @param  COMP_TriggerPin : specifies the pin(s) within the input/output group
+  *          This parameter can be one of the following values:
+  *            @arg COMP_TriggerPin_0: Trigger Pin 0
+  *            @arg COMP_TriggerPin_0: Trigger Pin 1
+  *            @arg COMP_TriggerPin_0: Trigger Pin 2    
+  * @param  NewState : enable or disable the trigger on the selected pin(s)
+    *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void COMP_TriggerConfig(COMP_TriggerGroup_TypeDef COMP_TriggerGroup,
+                        COMP_TriggerPin_TypeDef COMP_TriggerPin,
+                        FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_COMP_TRIGGERGROUP(COMP_TriggerGroup));
+  assert_param(IS_COMP_TRIGGERPIN(COMP_TriggerPin));
+
+  switch (COMP_TriggerGroup)
+  {
+    case COMP_TriggerGroup_InvertingInput:
+
+      if (NewState != DISABLE)
+      {
+        COMP->CSR4 &= (uint8_t) ~COMP_TriggerPin;
+      }
+      else
+      {
+        COMP->CSR4 |= (uint8_t) COMP_TriggerPin;
+      }
+      break;
+
+    case COMP_TriggerGroup_NonInvertingInput:
+      if (NewState != DISABLE)
+      {
+        COMP->CSR4 &= (uint8_t) ~((uint8_t)(COMP_TriggerPin << 3));
+      }
+      else
+      {
+        COMP->CSR4 |= (uint8_t) (COMP_TriggerPin << 3);
+      }
+      break;
+
+    case COMP_TriggerGroup_VREFINTOutput:
+      if (NewState != DISABLE)
+      {
+        COMP->CSR5 &= (uint8_t) ~COMP_TriggerPin;
+      }
+      else
+      {
+        COMP->CSR5 |= (uint8_t) COMP_TriggerPin;
+      }
+      break;
+
+    case COMP_TriggerGroup_DACOutput:
+      if (NewState != DISABLE)
+      {
+        COMP->CSR5 &= (uint8_t) ~((uint8_t)(COMP_TriggerPin << 3));
+      }
+      else
+      {
+        COMP->CSR5 |= (uint8_t) (COMP_TriggerPin << 3);
+      }
+      break;
+
+    default:
+      break;
+  }
+}
+
+/**
+  * @}
+  */
+  
+/** @defgroup COMP_Group5 Interrupts and flags management functions
+ *  @brief   Interrupts and flags management functions 
+ *
+@verbatim   
+ ===============================================================================
+                   Interrupts and flags management functions
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the interrupt generation when an event is detected.
+  * @param  COMP_Selection : selects the comparator
+  *          This parameter can be one of the following values:
+  *            @arg COMP_Selection_COMP1: Selection of Comparator 1
+  *            @arg COMP_Selection_COMP2: Selection of Comparator 2
+  * @param  NewState : new state of the COMPx interrupt.
+    *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void COMP_ITConfig(COMP_Selection_TypeDef COMP_Selection, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Check if Comparator 1 is selected */
+  if (COMP_Selection == COMP_Selection_COMP1)
+  {
+    if (NewState != DISABLE)
+    {
+      /* Enable the COMP1 Interrupt source */
+      COMP->CSR1 |= (uint8_t) COMP_CSR1_IE1;
+    }
+    else
+    {
+      /* Disable the COMP1 Interrupt source */
+      COMP->CSR1 &= (uint8_t)(~COMP_CSR1_IE1);
+    }
+  }
+  else /* Comparator 2 is selected */
+  {
+    if (NewState != DISABLE)
+    {
+      /* Enable the COMP2 Interrupt source */
+      COMP->CSR2 |= (uint8_t) COMP_CSR2_IE2;
+    }
+    else
+    {
+      /* Disable the COMP2 Interrupt source */
+      COMP->CSR2 &= (uint8_t)(~COMP_CSR2_IE2);
+    }
+  }
+}
+
+/**
+  * @brief  Checks whether the comparator flag is set or not.
+  * @param  COMP_Selection : selects the comparator
+  *          This parameter can be one of the following values:
+  *            @arg COMP_Selection_COMP1: Selection of Comparator 1
+  *            @arg COMP_Selection_COMP2: Selection of Comparator 2
+  * @retval The new state of COMPx event flag (SET or RESET).
+  */
+FlagStatus COMP_GetFlagStatus(COMP_Selection_TypeDef COMP_Selection)
+{
+  FlagStatus bitstatus = RESET;
+
+  /* Check the parameters */
+  assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
+
+  /* Check if COMP1 is selected */
+  if (COMP_Selection == COMP_Selection_COMP1)
+  {
+    if ((COMP->CSR1 & COMP_CSR1_EF1) != (uint8_t) RESET)
+    {
+      /* The comparator 1 event flag is set */
+      bitstatus = SET;
+    }
+    else
+    {
+      /* The comparator 1 event flag is reset */
+      bitstatus = RESET;
+    }
+  }
+  else   /* COMP2 is selected */
+  {
+    if ((COMP->CSR2 & COMP_CSR2_EF2) != (uint8_t) RESET)
+    {
+      /* The comparator 2 event flag is set */
+      bitstatus = SET;
+    }
+    else
+    {
+      /* The comparator 2 event flag is reset */
+      bitstatus = RESET;
+    }
+  }
+
+  /* return the comparator event flag status */
+  return (FlagStatus)(bitstatus);
+}
+
+/**
+  * @brief  Clears the comparator’s pending flag.
+  * @param  COMP_Selection : selects the comparator
+  *          This parameter can be one of the following values:
+  *            @arg COMP_Selection_COMP1: Selection of Comparator 1
+  *            @arg COMP_Selection_COMP2: Selection of Comparator 2
+  * @retval None.
+  */
+void COMP_ClearFlag(COMP_Selection_TypeDef COMP_Selection)
+{
+  /* Check the parameters */
+  assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
+
+  if (COMP_Selection == COMP_Selection_COMP1)
+  {
+    /* Clear the flag EF1 (rc_w0) clear this bit by writing 0. */
+    COMP->CSR1 &= (uint8_t) (~COMP_CSR1_EF1);
+  }
+  else
+  {
+    /* Clear the flag EF2 (rc_w0) clear this bit by writing 0. */
+    COMP->CSR2 &= (uint8_t) (~COMP_CSR2_EF2);
+  }
+}
+
+/**
+  * @brief  Checks whether the comparator interrupt has occurred or not.
+  * @param  COMP_Selection : selects the comparator
+  *          This parameter can be one of the following values:
+  *            @arg COMP_Selection_COMP1: Selection of Comparator 1
+  *            @arg COMP_Selection_COMP2: Selection of Comparator 2
+  * @retval ITStatus : The state of the COMPx event flag (SET or RESET).
+  */
+ITStatus COMP_GetITStatus(COMP_Selection_TypeDef COMP_Selection)
+{
+  ITStatus bitstatus = RESET;
+  uint8_t itstatus = 0x00, itenable = 0x00;
+
+  /* Check the parameters */
+  assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
+
+  if (COMP_Selection == COMP_Selection_COMP1)
+  {
+    /* Get the EF1 comparator event falg status */
+    itstatus = (uint8_t) (COMP->CSR1 & COMP_CSR1_EF1);
+
+    /* Get the IE1 interrupt enable bit status */
+    itenable = (uint8_t) (COMP->CSR1 & COMP_CSR1_IE1);
+
+    if ((itstatus != (uint8_t) RESET) && (itenable != (uint8_t) RESET))
+    {
+      /* the EF1 and IE1 are set */
+      bitstatus = SET;
+    }
+    else
+    {
+      /* the EF1 or IE1 is reset */
+      bitstatus = RESET;
+    }
+  }
+  else
+  {
+    /* Get the EF2 comparator event falg value */
+    itstatus = (uint8_t) (COMP->CSR2 & COMP_CSR2_EF2);
+
+    /* Get the IE2 interrupt enable bit value */
+    itenable = (uint8_t) (COMP->CSR2 & COMP_CSR2_IE2);
+
+    if ((itstatus != (uint8_t)RESET) && (itenable != (uint8_t)RESET))
+    {
+      /* The EF2 and IE2 are set */
+      bitstatus = SET;
+    }
+    else
+    {
+      /* The EF2 or IE2 is reset */
+      bitstatus = RESET;
+    }
+  }
+
+  /* Return the COMP interrupt status */
+  return (ITStatus) bitstatus;
+}
+
+/**
+  * @brief  Clears the interrupt pending bits of the comparator.
+  * @param  COMP_Selection : selects the comparator
+  *          This parameter can be one of the following values:
+  *            @arg COMP_Selection_COMP1: Selection of Comparator 1
+  *            @arg COMP_Selection_COMP2: Selection of Comparator 2
+  * @retval None
+  */
+void COMP_ClearITPendingBit(COMP_Selection_TypeDef COMP_Selection)
+{
+  /* Check the parameters */
+  assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
+
+  if (COMP_Selection == COMP_Selection_COMP1)
+  {
+    /* Clear the flag EF1 (rc_w0) clear this bit by writing 0. */
+    COMP->CSR1 &= (uint8_t) (~COMP_CSR1_EF1);
+  }
+  else
+  {
+    /* Clear the flag EF2 (rc_w0) clear this bit by writing 0. */
+    COMP->CSR2 &= (uint8_t) (~COMP_CSR2_EF2);
+  }
+}
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_dac.c b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_dac.c
new file mode 100755
index 0000000..bd8e1d9
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_dac.c
@@ -0,0 +1,836 @@
+/**
+  ******************************************************************************
+  * @file    stm8l15x_dac.c
+  * @author  MCD Application Team
+  * @version V1.6.0
+  * @date    28-June-2013
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Digital-to-Analog Converter (DAC) peripheral: 
+  *           - DAC channels configuration: trigger, output buffer, data format
+  *           - DMA management      
+  *           - Interrupts and flags management
+  *
+  *  @verbatim
+  *    
+  *          ===================================================================
+  *                             DAC Peripheral features
+  *          ===================================================================
+  *          The device integrates two 12-bit Digital Analog Converters that can 
+  *          be used independently or simultaneously (dual mode):
+  *            1- DAC channel1 with DAC_OUT1 (PF0) as output
+  *            1- DAC channel2 with DAC_OUT2 (PF1) as output
+  *
+  *          Digital to Analog conversion can be non-triggered using DAC_Trigger_None
+  *          and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register using 
+  *          DAC_SetChannel1Data()/DAC_SetChannel2Data.
+  *   
+  *         Digital to Analog conversion can be triggered by:
+  *             1- External event: PE4 using DAC_Trigger_Ext.
+  *                This pin (PE4) must be configured in input mode.
+  *
+  *             2- Timers TRGO: TIM4, TIM5 
+  *                (DAC_Trigger_T4_TRGO, DAC_Trigger_T5_TRGO)
+  *                The timer TRGO event should be selected using TIMx_SelectOutputTrigger()
+  *
+  *             3- Software using DAC_Trigger_Software
+  *
+  *          Each DAC channel integrates an output buffer that can be used to 
+  *          reduce the output impedance, and to drive external loads directly
+  *          without having to add an external operational amplifier.
+  *          
+  *          Refer to the device datasheet for more details about output impedance
+  *          value with and without output buffer.
+  *
+  *          Both DAC channels can be used to generate
+  *             1- Noise wave using DAC_Wave_Noise
+  *             2- Triangle wave using DAC_Wave_Triangle
+  *        
+  *
+  *          The DAC data format can be:
+  *             1- 8-bit right alignment using DAC_Align_8b_R
+  *             2- 12-bit left alignment using DAC_Align_12b_L
+  *             3- 12-bit right alignment using DAC_Align_12b_R
+  *
+  *          The analog output voltage on each DAC channel pin is determined
+  *          by the following equation: DAC_OUTx = VREF+ * DOR / 4095
+  *             with  DOR is the Data Output Register
+  *                   VEF+ is the input voltage reference (refer to the device datasheet)
+  *          e.g. To set DAC_OUT1 to 0.7V, use
+  *            DAC_SetChannel1Data(DAC_Align_12b_R, 868);
+  *          Assuming that VREF+ = 3.3, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V
+  *
+  *          A DMA1 request can be generated when an external trigger (but not
+  *          a software trigger) occurs if DMA1 requests are enabled using
+  *          DAC_DMACmd()
+  *          DMA1 requests are mapped as following:
+  *             1- DAC channel1 is mapped on DMA1 channel3 which must be already 
+  *                configured
+  *             2- DAC channel2 is mapped on DMA1 channel1 which must be already 
+  *                configured
+  *
+  *          ===================================================================      
+  *                              How to use this driver 
+  *          ===================================================================          
+  *            - DAC clock must be enabled to get write access to DAC registers using
+  *              CLK_PeripheralClockConfig(CLK_Peripheral_DAC, ENABLE)
+  *            - Configure DAC_OUTx (DAC_OUT1: PF0, DAC_OUT2: PF1) in analog mode.
+  *            - Configure the DAC channel using DAC_Init()
+  *            - Enable the DAC channel using DAC_Cmd()
+  * 
+  *  @endverbatim
+  *    
+  ******************************************************************************
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ****************************************************************************** 
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm8l15x_dac.h"
+
+/** @addtogroup STM8L15x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup DAC 
+  * @brief DAC driver modules
+  * @{
+  */ 
+  
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup DAC_Private_Functions
+  * @{
+  */ 
+
+/** @defgroup DAC_Group1 DAC channels configuration
+ *  @brief   DAC channels configuration: trigger, output buffer, data format 
+ *
+@verbatim   
+ ===============================================================================
+          DAC channels configuration: trigger, output buffer, data format
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the DAC peripheral registers to their default reset values.
+  * @param  None
+  * @retval None
+  */
+void DAC_DeInit(void)
+{
+  /*  Set Channel1  the Configuration registers to their reset values */
+  DAC->CH1CR1 = DAC_CR1_RESET_VALUE;
+  DAC->CH1CR2 = DAC_CR2_RESET_VALUE;
+
+  /*  Set Channel2  the Configuration registers to their reset values */
+  DAC->CH2CR1 = DAC_CR1_RESET_VALUE;
+  DAC->CH2CR2 = DAC_CR2_RESET_VALUE;
+
+  /*  Set the Software Trigger configuration registers to their reset values */
+  DAC->SWTRIGR = DAC_SWTRIGR_RESET_VALUE;
+
+  /*  Set the Status registers to their reset values */
+  DAC->SR = (uint8_t)~DAC_SR_RESET_VALUE;
+
+  /*  Set the Channel1 Data holding registers to their reset values */
+  DAC->CH1RDHRH = DAC_RDHRH_RESET_VALUE;
+  DAC->CH1RDHRL = DAC_RDHRL_RESET_VALUE;
+  DAC->CH1LDHRH = DAC_LDHRH_RESET_VALUE;
+  DAC->CH1LDHRL = DAC_LDHRL_RESET_VALUE;
+  DAC->CH1DHR8 = DAC_DHR8_RESET_VALUE;
+
+  /*  Set the Channel2 Data holding registers to their reset values */
+  DAC->CH2RDHRH = DAC_RDHRH_RESET_VALUE;
+  DAC->CH2RDHRL = DAC_RDHRL_RESET_VALUE;
+  DAC->CH2LDHRH = DAC_LDHRH_RESET_VALUE;
+  DAC->CH2LDHRL = DAC_LDHRL_RESET_VALUE;
+  DAC->CH2DHR8 = DAC_DHR8_RESET_VALUE;
+
+  /*  Set the Dual mode 12bit Right Data holding registers to their reset values */
+  DAC->DCH1RDHRH = DAC_RDHRH_RESET_VALUE;
+  DAC->DCH1RDHRL = DAC_RDHRL_RESET_VALUE;
+  DAC->DCH2RDHRH = DAC_RDHRH_RESET_VALUE;
+  DAC->DCH2RDHRL = DAC_RDHRL_RESET_VALUE;
+
+  /*  Set the Dual mode 12bit Left Data holding registers to their reset values */
+  DAC->DCH1LDHRH = DAC_LDHRH_RESET_VALUE;
+  DAC->DCH1LDHRL = DAC_LDHRL_RESET_VALUE;
+  DAC->DCH2LDHRH = DAC_LDHRH_RESET_VALUE;
+  DAC->DCH2LDHRL = DAC_LDHRL_RESET_VALUE;
+
+  /*  Set the Dual mode 8bit Data holding registers to their reset values */
+  DAC->DCH1DHR8 = DAC_DHR8_RESET_VALUE;
+  DAC->DCH2DHR8 = DAC_DHR8_RESET_VALUE;
+}
+
+/**
+  * @brief  Initializes the DAC according to the specified parameters.
+  * @param  DAC_Channel: the selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Channel_1: DAC Channel1 selected
+  *            @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  DAC_Trigger : the selected DAC trigger. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Trigger_None: DAC trigger None 
+  *            @arg DAC_Trigger_T4_TRGO: DAC trigger TIM4 TRGO
+  *            @arg DAC_Trigger_T5_TRGO: DAC trigger TIM5 TRGO
+  *            @arg DAC_Trigger_Ext: DAC trigger External Trigger (PE4)  
+  *            @arg DAC_Trigger_Software: DAC trigger software 
+  * @param  DAC_OutputBuffer : the status of DAC load Buffer
+  *          This parameter can be one of the following values:
+  *            @arg DAC_OutputBuffer_Enable: DAC output buffer Enabled
+  *            @arg DAC_OutputBuffer_Disable: DAC output buffer Disabled  
+  * @retval None
+  */
+void DAC_Init(DAC_Channel_TypeDef DAC_Channel,
+              DAC_Trigger_TypeDef DAC_Trigger,
+              DAC_OutputBuffer_TypeDef DAC_OutputBuffer)
+{
+  uint8_t tmpreg = 0;
+  uint16_t tmpreg2 = 0;
+
+  /* Check the DAC parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_DAC_TRIGGER(DAC_Trigger));
+  assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_OutputBuffer));
+
+  /* Get the DAC CHxCR1 value */
+  tmpreg2 =  (uint16_t)((uint8_t)((uint8_t)DAC_Channel << 1));
+  tmpreg = *(uint8_t*)((uint16_t)(DAC_BASE + CR1_Offset + tmpreg2));
+
+  /* Clear BOFFx, TENx, TSELx bits */
+  tmpreg &= (uint8_t)~(DAC_CR1_BOFF | DAC_CR1_TEN | DAC_CR1_TSEL );
+
+  /* Set BOFFx bit according to DAC_OutputBuffer value */
+  tmpreg |= (uint8_t)(DAC_OutputBuffer);
+
+
+  /* Configure for the selected DAC channel trigger*/
+  if (DAC_Trigger != DAC_Trigger_None)
+  {
+    /* Set TSELx and TEN  bits according to DAC_Trigger value */
+    tmpreg |= (uint8_t)(DAC_CR1_TEN | DAC_Trigger) ;
+  }
+
+  /* Write to DAC CHxCR1 */
+  *(uint8_t*)((uint16_t)(DAC_BASE + CR1_Offset + tmpreg2)) = (uint8_t)tmpreg;
+}
+
+/**
+  * @brief  Enables or disables the specified DAC channel.
+  * @param  DAC_Channel: the selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Channel_1: DAC Channel1 selected
+  *            @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  NewState: new state of the DAC channel. 
+  *      This parameter can be: ENABLE or DISABLE.
+  * @note When the DAC channel is enabled the trigger source can no more
+  *       be modified.
+  * @retval None
+  */
+void DAC_Cmd(DAC_Channel_TypeDef DAC_Channel, FunctionalState NewState)
+{
+  uint16_t cr1addr = 0;
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Find CHxCR1 register Address */
+  cr1addr = DAC_BASE + CR1_Offset + (uint8_t)((uint8_t)DAC_Channel << 1);
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected DAC channel */
+    (*(uint8_t*)(cr1addr)) |= DAC_CR1_EN;
+  }
+  else
+  {
+    /* Disable the selected DAC channel */
+    (*(uint8_t*)(cr1addr)) &= (uint8_t) ~(DAC_CR1_EN);
+  }
+}
+
+/**
+  * @brief  Enables or disables the selected DAC channel software trigger.
+  * @param  DAC_Channel: the selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Channel_1: DAC Channel1 selected
+  *            @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  NewState: new state of the selected DAC channel software trigger.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None.
+  */
+void DAC_SoftwareTriggerCmd(DAC_Channel_TypeDef DAC_Channel, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable software trigger for the selected DAC channel */
+    DAC->SWTRIGR |= (uint8_t)(DAC_SWTRIGR_SWTRIG1 << DAC_Channel);
+  }
+  else
+  {
+    /* Disable software trigger for the selected DAC channel */
+    DAC->SWTRIGR &= (uint8_t)~((uint8_t)(DAC_SWTRIGR_SWTRIG1 << DAC_Channel));
+  }
+}
+
+/**
+  * @brief  Enables or disables simultaneously the two DAC channels software
+  *         triggers.
+  * @param  NewState: new state of the DAC channels software triggers.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None.
+  */
+void DAC_DualSoftwareTriggerCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable software trigger for both DAC channels */
+    DAC->SWTRIGR |= (DAC_SWTRIGR_SWTRIG1 | DAC_SWTRIGR_SWTRIG2) ;
+  }
+  else
+  {
+    /* Disable software trigger for both DAC channels */
+    DAC->SWTRIGR &= (uint8_t)~(DAC_SWTRIGR_SWTRIG1 | DAC_SWTRIGR_SWTRIG2);
+  }
+}
+
+/**
+  * @brief  Enables or disables the selected DAC channel wave generation.
+  * @param  DAC_Channel: the selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Channel_1: DAC Channel1 selected
+  *            @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  DAC_Wave: Specifies the wave type to enable or disable.
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Wave_Noise: noise wave generation
+  *            @arg DAC_Wave_Triangle: triangle wave generation
+  * @param  NewState: new state of the selected DAC channel wave generation.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DAC_WaveGenerationCmd(DAC_Channel_TypeDef DAC_Channel,
+                           DAC_Wave_TypeDef DAC_Wave,
+                           FunctionalState NewState)
+{
+  uint8_t tmpreg = 0;
+
+  /* Check the DAC parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_DAC_WAVE(DAC_Wave));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Get the DAC CHxCR1 value & Clear WAVEN bits */
+  tmpreg = (uint8_t)((*(uint8_t*)(uint16_t)(DAC_BASE + CR1_Offset + (uint8_t)((uint8_t)DAC_Channel << 1))) & (uint8_t)~(DAC_CR1_WAVEN));
+
+  if (NewState != DISABLE)
+  {
+    tmpreg |= (uint8_t)(DAC_Wave);
+  }
+
+  /* Write to DAC CHxCR1 */
+  (*(uint8_t*) (uint16_t)(DAC_BASE + CR1_Offset +  (uint8_t)((uint8_t)DAC_Channel << 1))) = tmpreg;
+
+}
+
+/**
+  * @brief  Select DAC Noise Wave Generation LFSR according to the specified parameters.
+  * @param  DAC_Channel: the selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Channel_1: DAC Channel1 selected
+  *            @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  DAC_LFSRUnmask : the selected unmasked bit.
+  *          This parameter can be one of the following values:
+  *            @arg DAC_LFSRUnmask_Bit0: Noise LFSR Unmask 1 LSB
+  *            @arg DAC_LFSRUnmask_Bits1_0: Noise LFSR Unmask 2 LSB  
+  *            @arg DAC_LFSRUnmask_Bit2_0: Noise LFSR Unmask 3 LSB
+  *            @arg DAC_LFSRUnmask_Bit3_0: Noise LFSR Unmask 4 LSB
+  *            @arg DAC_LFSRUnmask_Bit4_0: Noise LFSR Unmask 5 LSB
+  *            @arg DAC_LFSRUnmask_Bit5_0: Noise LFSR Unmask 6 LSB
+  *            @arg DAC_LFSRUnmask_Bit6_0: Noise LFSR Unmask 7 LSB
+  *            @arg DAC_LFSRUnmask_Bit7_0: Noise LFSR Unmask 8 LSB
+  *            @arg DAC_LFSRUnmask_Bit8_0: Noise LFSR Unmask 9 LSB
+  *            @arg DAC_LFSRUnmask_Bit9_0: Noise LFSR Unmask 10 LSB
+  *            @arg DAC_LFSRUnmask_Bit10_0: Noise LFSR Unmask 11 LSB
+  *            @arg DAC_LFSRUnmask_Bit11_0: Noise LFSR Unmask 12 LSB                    
+  * @retval None
+  */
+void DAC_SetNoiseWaveLFSR(DAC_Channel_TypeDef DAC_Channel, DAC_LFSRUnmask_TypeDef DAC_LFSRUnmask)
+{
+  uint8_t tmpreg = 0;
+  uint16_t cr2addr = 0;
+
+  /* Check the DAC parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_LFSRUnmask));
+
+  /* Get the DAC CHxCR2 value  &  Clear MAMPx bits */
+  cr2addr = (uint16_t)(DAC_BASE + CR2_Offset + (uint8_t)((uint8_t)DAC_Channel << 1));
+  tmpreg = (uint8_t)((*(uint8_t*)(cr2addr)) & (uint8_t)~(DAC_CR2_MAMPx));
+
+  /* Write to DAC CHxCR2 */
+  (*(uint8_t*)(cr2addr)) = (uint8_t)( tmpreg | DAC_LFSRUnmask);
+}
+
+/**
+  * @brief  Select DAC Triangle Wave Generation Amplitude according to the specified parameters.
+  * @param  DAC_Channel: the selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Channel_1: DAC Channel1 selected
+  *            @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  DAC_TriangleAmplitude : the selected Amplitude
+  *          This parameter can be one of the following values:
+  *            @arg DAC_TriangleAmplitude_1: Triangle Amplitude = Vref.(1/4096)
+  *            @arg DAC_TriangleAmplitude_3: Triangle Amplitude = Vref.(3/4096)  
+  *            @arg DAC_TriangleAmplitude_7: Triangle Amplitude = Vref.(7/4096)
+  *            @arg DAC_TriangleAmplitude_15: Triangle Amplitude = Vref.(15/4096)
+  *            @arg DAC_TriangleAmplitude_31: Triangle Amplitude = Vref.(31/4096)
+  *            @arg DAC_TriangleAmplitude_63: Triangle Amplitude = Vref.(63/4096)
+  *            @arg DAC_TriangleAmplitude_127: Triangle Amplitude = Vref.(127/4096)
+  *            @arg DAC_TriangleAmplitude_255: Triangle Amplitude = Vref.(255/4096)
+  *            @arg DAC_TriangleAmplitude_511: Triangle Amplitude = Vref.(511/4096)
+  *            @arg DAC_TriangleAmplitude_1023: Triangle Amplitude = Vref.(1023/4096)
+  *            @arg DAC_TriangleAmplitude_2047: Triangle Amplitude = Vref.(2047/4096)
+  *            @arg DAC_TriangleAmplitude_4095: Triangle Amplitude = Vref.(4095/4096) 
+  * @retval None
+  */
+void DAC_SetTriangleWaveAmplitude(DAC_Channel_TypeDef DAC_Channel, DAC_TriangleAmplitude_TypeDef DAC_TriangleAmplitude)
+{
+  uint8_t tmpreg = 0;
+  uint16_t cr2addr = 0;
+
+  /* Check the DAC parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_TriangleAmplitude));
+
+
+  /* Get the DAC CHxCR2 value  &  Clear MAMPx bits */
+  cr2addr = (uint16_t)(DAC_BASE + CR2_Offset + (uint8_t)((uint8_t)DAC_Channel << 1));
+  tmpreg = (uint8_t)((*(uint8_t*)(cr2addr)) & (uint8_t)~(DAC_CR2_MAMPx));
+
+  /* Write to DAC CHxCR2 */
+  (*(uint8_t*)(cr2addr)) = (uint8_t)( tmpreg | DAC_TriangleAmplitude);
+}
+
+/**
+  * @brief  Set the specified data holding register value for DAC channel1.
+  * @param  DAC_Align: Specifies the data alignment for DAC channel1.
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Align_8b_R: 8bit right data alignment selected
+  *            @arg DAC_Align_12b_L: 12bit left data alignment selected
+  *            @arg DAC_Align_12b_R: 12bit right data alignment selected
+  * @param  Data : Data to be loaded in the selected data holding register.
+  * @retval None.
+  */
+void DAC_SetChannel1Data(DAC_Align_TypeDef DAC_Align, uint16_t DAC_Data)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_ALIGN(DAC_Align));
+
+  if (DAC_Align != DAC_Align_8b_R)
+  {
+    /* Set the DAC channel1 selected data holding register */
+    *(uint8_t*)((uint16_t)(DAC_BASE + CH1RDHRH_Offset + DAC_Align )) = (uint8_t)(((uint16_t)DAC_Data) >> 8);
+    *(uint8_t*)((uint16_t)(DAC_BASE + CH1RDHRH_Offset + 1 + DAC_Align )) = (uint8_t)DAC_Data;
+  }
+  else
+  {
+    /* Check the parameter */
+    assert_param(IS_DAC_DATA_08R(DAC_Data));
+
+    /* Set the DAC channel1 selected data holding register */
+    DAC->CH1DHR8 = (uint8_t)(DAC_Data);
+  }
+}
+
+/**
+  * @brief  Set the specified data holding register value for DAC channel2.
+  * @param  DAC_Align: Specifies the data alignment for DAC channel2.
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Align_8b_R: 8bit right data alignment selected
+  *            @arg DAC_Align_12b_L: 12bit left data alignment selected
+  *            @arg DAC_Align_12b_R: 12bit right data alignment selected
+  * @param  Data : Data to be loaded in the selected data holding register.
+  * @retval None.
+  */
+void DAC_SetChannel2Data(DAC_Align_TypeDef DAC_Align, uint16_t DAC_Data)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_ALIGN(DAC_Align));
+
+  if (DAC_Align != DAC_Align_8b_R)
+  {
+    /* Set the DAC channel2 selected data holding register */
+    *(uint8_t*)((uint16_t)(DAC_BASE + CH2RDHRH_Offset + DAC_Align )) = (uint8_t)(((uint16_t)DAC_Data) >> 8);
+    *(uint8_t*)((uint16_t)(DAC_BASE + CH2RDHRH_Offset + 1 + DAC_Align )) = (uint8_t)DAC_Data;
+  }
+  else
+  {
+    /* Check the parameter */
+    assert_param(IS_DAC_DATA_08R(DAC_Data));
+
+    /* Set the DAC channel2 selected data holding register */
+    DAC->CH2DHR8 = (uint8_t)(DAC_Data);
+  }
+}
+
+/**
+  * @brief  Set the specified data holding register value for dual channel DAC.
+  * @param  DAC_Align: Specifies the data alignment for dual channel DAC.
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Align_8b_R: 8bit right data alignment selected
+  *            @arg DAC_Align_12b_L: 12bit left data alignment selected
+  *            @arg DAC_Align_12b_R: 12bit right data alignment selected
+  * @param  Data2: Data for DAC Channel2 to be loaded in the selected data 
+  *         holding register.
+  * @param  Data1: Data for DAC Channel1 to be loaded in the selected data 
+  *         holding register.
+  * @note In dual mode, a unique register access is required to write in both
+  *       DAC channels at the same time.
+  * @retval None.
+  */
+void DAC_SetDualChannelData(DAC_Align_TypeDef DAC_Align, uint16_t DAC_Data2, uint16_t DAC_Data1)
+{
+  uint16_t dchxrdhrhaddr = 0;
+
+  /* Check the parameters */
+  assert_param(IS_DAC_ALIGN(DAC_Align));
+
+  if (DAC_Align != DAC_Align_8b_R)
+  {
+    /* Identify the DCHxRDHRH address*/
+    dchxrdhrhaddr = (uint16_t)(DAC_BASE + DCH1RDHRH_Offset + DAC_Align);
+
+    /* Set the DAC channels Dual data holding registers */
+    *(uint8_t*)(uint16_t)dchxrdhrhaddr = (uint8_t)(((uint16_t)DAC_Data1) >> 8);
+    *(uint8_t*)(uint16_t)(dchxrdhrhaddr + 1) = (uint8_t)DAC_Data1;
+    *(uint8_t*)(uint16_t)(dchxrdhrhaddr + 2) = (uint8_t)(((uint16_t)DAC_Data2) >> 8);
+    *(uint8_t*)(uint16_t)(dchxrdhrhaddr + 3) = (uint8_t)DAC_Data2;
+  }
+  else
+  {
+    /* Check the parameter */
+    assert_param(IS_DAC_DATA_08R(DAC_Data1 | DAC_Data2));
+
+    /* Set the DAC channels Dual data holding registers */
+    DAC->DCH1DHR8 = (uint8_t)(DAC_Data1);
+    DAC->DCH2DHR8 = (uint8_t)(DAC_Data2);
+  }
+}
+
+/**
+  * @brief  Returns the last data output value of the selected DAC channel.
+  * @param  DAC_Channel: the selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Channel_1: DAC Channel1 selected
+  *            @arg DAC_Channel_2: DAC Channel2 selected
+  * @retval The selected DAC channel data output value.
+  */
+uint16_t DAC_GetDataOutputValue(DAC_Channel_TypeDef DAC_Channel)
+{
+  uint16_t outputdata = 0;
+  uint16_t tmp = 0;
+
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+
+  if ( DAC_Channel ==  DAC_Channel_1)
+  {
+    /* Returns the DAC channel data output register value */
+    tmp = (uint16_t)((uint16_t)DAC->CH1DORH << 8);
+    outputdata = (uint16_t)(tmp | (DAC->CH1DORL));
+  }
+  else
+  {
+    /* Returns the DAC channel data output register value */
+    tmp = (uint16_t)((uint16_t)DAC->CH2DORH << 8);
+    outputdata = (uint16_t)(tmp | (DAC->CH2DORL));
+  }
+
+  /* return the selected DAC channel data output value.*/
+  return (uint16_t)outputdata;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Group2 DMA management functions
+ *  @brief   DMA management functions
+ *
+@verbatim   
+ ===============================================================================
+                          DMA management function
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Enables or disables the specified DAC channel DMA request.
+  *         When enabled DMA1 is generated when an external trigger occurs
+  * @param  DAC_Channel: the selected DAC channel.
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Channel_1: DAC Channel1 selected
+  *            @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  NewState: new state of the selected DAC channel DMA request.
+  *          This parameter can be: ENABLE or DISABLE.
+  *  The DAC channel1 (channel2) is mapped on DMA1 channel3 (channel1) which 
+  *  must be already configured. 
+  * @retval None
+  */
+void DAC_DMACmd(DAC_Channel_TypeDef DAC_Channel, FunctionalState NewState)
+{
+  uint16_t cr2addr = 0;
+
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Find CHxCR2 register Address */
+  cr2addr = DAC_BASE + CR2_Offset + (uint8_t)((uint8_t)DAC_Channel << 1);
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected DAC channel DMA request */
+    (*(uint8_t*)(cr2addr)) |= DAC_CR2_DMAEN;
+  }
+  else
+  {
+    /* Disable the selected DAC channel DMA request */
+    (*(uint8_t*)(cr2addr)) &= (uint8_t)~(DAC_CR2_DMAEN);
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Group3 Interrupts and flags management functions
+ *  @brief   Interrupts and flags management functions
+ *
+@verbatim   
+ ===============================================================================
+                   Interrupts and flags management functions
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+    
+/**
+  * @brief  Enables or disables the specified DAC interrupts.
+  * @param  DAC_Channel: the selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Channel_1: DAC Channel1 selected
+  *            @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  DAC_IT: specifies the DAC interrupt sources to be enabled or disabled. 
+  *   This parameter can be the following values:
+  *            @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
+  * @note The DMA underrun occurs when a second external trigger arrives before
+  *       the acknowledgement for the first external trigger is received (first request).
+  * @param  NewState: new state of the specified DAC interrupts.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DAC_ITConfig(DAC_Channel_TypeDef DAC_Channel, DAC_IT_TypeDef DAC_IT, FunctionalState NewState)
+{
+  uint16_t cr2addr = 0;
+
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  assert_param(IS_DAC_IT(DAC_IT));
+
+  /* Find CHxCR2 register Address */
+  cr2addr = DAC_BASE + CR2_Offset + (uint8_t)((uint8_t)DAC_Channel << 1);
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected DAC interrupts */
+    (*(uint8_t*)(cr2addr)) |=  (uint8_t)(DAC_IT);
+  }
+  else
+  {
+    /* Disable the selected DAC interrupts */
+    (*(uint8_t*)(cr2addr)) &= (uint8_t)(~(DAC_IT));
+  }
+}
+
+/**
+  * @brief  Checks whether the specified DAC flag is set or not.
+  * @param  DAC_Channel: thee selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Channel_1: DAC Channel1 selected
+  *            @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  DAC_FLAG: specifies the flag to check. 
+  *   This parameter can be only of the following value:
+  *            @arg DAC_FLAG_DMAUDR: DMA underrun flag
+  * @note The DMA underrun occurs when a second external trigger arrives before
+  *       the acknowledgement for the first external trigger is received (first request).
+  * @retval The new state of DAC_FLAG (SET or RESET).
+  */
+FlagStatus DAC_GetFlagStatus(DAC_Channel_TypeDef DAC_Channel, DAC_FLAG_TypeDef DAC_FLAG)
+{
+  FlagStatus flagstatus = RESET;
+  uint8_t flag = 0;
+
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_DAC_FLAG(DAC_FLAG));
+
+  flag = (uint8_t)(DAC_FLAG << DAC_Channel);
+
+  /* Check the status of the specified DAC flag */
+  if ((DAC->SR & flag ) != (uint8_t)RESET)
+  {
+    /* DAC FLAG is set */
+    flagstatus = SET;
+  }
+  else
+  {
+    /* DAC FLAG is reset */
+    flagstatus = RESET;
+  }
+
+  /* Return the DAC FLAG status */
+  return  flagstatus;
+}
+
+/**
+  * @brief  Clears the DAC channel's pending flags.
+  * @param  DAC_Channel: the selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Channel_1: DAC Channel1 selected
+  *            @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  DAC_FLAG: specifies the flag to clear. 
+  *   This parameter can be of the following value:
+  *            @arg DAC_FLAG_DMAUDR: DMA underrun flag                          
+  * @retval None
+  */
+void DAC_ClearFlag(DAC_Channel_TypeDef DAC_Channel, DAC_FLAG_TypeDef DAC_FLAG)
+{
+  uint8_t flag = 0;
+
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_DAC_FLAG(DAC_FLAG));
+
+  /* identify the selected flag*/
+  flag = (uint8_t)(DAC_FLAG << DAC_Channel);
+
+  /* Clear the selected DAC flag */
+  DAC->SR = (uint8_t)(~flag);
+}
+
+/**
+  * @brief  Checks whether the specified DAC interrupt has occurred or not.
+  * @param  DAC_Channel: the selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Channel_1: DAC Channel1 selected
+  *            @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  DAC_IT: specifies the DAC interrupt source to check. 
+  *   This parameter can be the following values:
+  *            @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
+  * @note The DMA underrun occurs when a second external trigger arrives before
+  *       the acknowledgement for the first external trigger is received (first request).
+  * @retval The new state of DAC_IT (SET or RESET).
+  */
+ITStatus DAC_GetITStatus(DAC_Channel_TypeDef DAC_Channel, DAC_IT_TypeDef DAC_IT)
+{
+  ITStatus itstatus = RESET;
+  uint8_t enablestatus = 0;
+  uint8_t flagstatus = 0;
+  uint8_t tempreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_DAC_IT(DAC_IT));
+
+  /* identify the status of the IT and its correspondent flag*/
+  tempreg = *(uint8_t*)(uint16_t)(DAC_BASE + CR2_Offset + (uint8_t)((uint8_t)DAC_Channel << 2));
+  enablestatus = (uint8_t)( tempreg & (uint8_t)((uint8_t)DAC_IT << DAC_Channel));
+  flagstatus = (uint8_t)(DAC->SR & (uint8_t)(DAC_IT >> ((uint8_t)0x05 - DAC_Channel)));
+
+  /* Check the status of the specified DAC interrupt */
+  if (((flagstatus) != (uint8_t)RESET) && enablestatus)
+  {
+    /* DAC IT is set */
+    itstatus = SET;
+  }
+  else
+  {
+    /* DAC IT is reset */
+    itstatus = RESET;
+  }
+
+  /* Return the DAC IT status */
+  return  itstatus;
+}
+
+/**
+  * @brief  Clears the DAC channel's interrupt pending bits.
+  * @param  DAC_Channel: the selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Channel_1: DAC Channel1 selected
+  *            @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  DAC_IT: specifies the DAC interrupt pending bit to clear.
+  *   This parameter can be the following values:
+  *            @arg DAC_IT_DMAUDR: DMA underrun interrupt mask                         
+  * @retval None
+  */
+void DAC_ClearITPendingBit(DAC_Channel_TypeDef DAC_Channel, DAC_IT_TypeDef DAC_IT)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_DAC_IT(DAC_IT));
+
+  /* Clear the selected DAC interrupt pending bits */
+  DAC->SR = (uint8_t)~(uint8_t)((uint8_t)DAC_IT >> (0x05 - DAC_Channel));
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_dma.c b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_dma.c
new file mode 100755
index 0000000..ac2c724
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_dma.c
@@ -0,0 +1,750 @@
+/**
+  ******************************************************************************
+  * @file    stm8l15x_dma.c
+  * @author  MCD Application Team
+  * @version V1.6.0
+  * @date    28-June-2013
+  * @brief   This file provides all the DMA firmware functions.
+ * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Direct Memory Access controller (DMA):           
+  *           - Initialization and Configuration
+  *           - Data Counter
+  *           - Interrupts and flags management
+  *           
+  *  @verbatim
+  *      
+  *          ===================================================================      
+  *                                 How to use this driver
+  *          =================================================================== 
+  *          1. Enable The DMA controller clock using CLK_PeripheralClockConfig() 
+  *            function: CLK_PeripheralClockConfig(CLK_Peripheral_DMA1, ENABLE).
+  *
+  *          2. Enable and configure the peripheral to be connected to the DMA 
+  *            channel (except for internal SRAM / FLASH memories: no 
+  *            initialization is necessary). 
+  *        
+  *          3. For a given Channel, program the Source and Destination 
+  *             addresses, the transfer Direction, the Buffer Size, the 
+  *             Peripheral and Memory Incrementation mode and Data Size, 
+  *             the Circular or Normal mode, the channel transfer Priority 
+  *             and the Memory-to-Memory transfer mode (for channel 3 only, 
+  *             if needed) using the DMA_Init() function.
+  *
+  *          4. Enable the the corresponding interrupt(s) using the function 
+  *             DMA_ITConfig() if you need to use DMA interrupts. 
+  *
+  *          5. Enable the DMA channel using the DMA_Cmd() function. 
+  *                
+  *          6. Activate the needed channel Request using PPP_DMACmd() function 
+  *            for any PPP peripheral except internal SRAM and FLASH (ie. TIM4, 
+  *             USART ...). The function allowing this operation is provided in 
+  *             each PPP peripheral driver (ie. TIM4_DMACmd for TIM4 peripheral).     
+  *
+  *          7. Optionally, you can configure the number of data to be 
+  *             transferred when the channel is disabled (ie. after each 
+  *             Transfer Complete event or when a Transfer Error occurs) using 
+  *             the function DMA_SetCurrDataCounter().
+  *             And you can get the number of remaining data to be transferred 
+  *             using the function DMA_GetCurrDataCounter() at run time (when 
+  *             the DMA channel is enabled and running).  
+  *                   
+  *          8. To control DMA events you can use one of the following 
+  *              two methods:
+  *               a- Check on DMA channel flags using the function 
+  *                  DMA_GetFlagStatus().  
+  *               b- Use DMA interrupts through the function DMA_ITConfig() 
+  *                   at initialization phase and DMA_GetITStatus() function 
+  *                   into interrupt routines in communication phase.  
+  *              After checking on a flag you should clear it using 
+  *              DMA_ClearFlag() function. And after checking on an interrupt 
+  *              event you should clear it using DMA_ClearITPendingBit() 
+  *              function.     
+  *                 
+  *  @endverbatim
+  *                                  
+  ******************************************************************************
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ****************************************************************************** 
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm8l15x_dma.h"
+
+/** @addtogroup STM8L15x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup DMA 
+  * @brief  DMA driver modules
+  * @{
+  */ 
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup DMA_Private_Functions
+  * @{
+  */ 
+
+/** @defgroup DMA_Group1 Initialization and Configuration functions
+ *  @brief   Initialization and Configuration functions
+ *
+@verbatim   
+ ===============================================================================
+                 Initialization and Configuration functions
+ ===============================================================================  
+
+  This subsection provides functions allowing to initialize the DMA channel 
+  source and destination addresses, incrementation and data sizes, transfer 
+  direction, buffer size, circular/normal mode selection, memory-to-memory mode 
+  selection and channel priority value.
+  
+  - The DMA_Init() function follows the DMA configuration procedures.
+  - All DMA channels can be enabled and disabled in the same time using 
+    DMA_GlobalCmd() function.
+  - The DMA has 4 channels, User can enable or disable channels using 
+    DMA_Cmd() function.
+  - The timeout duration (number of wait cycles starting from the latest 
+    request) is configured using DMA_SetTimeOut() function. The DMA then waits 
+    until this timeout has elapsed before requesting from the core a high 
+    priority access to the bus. 
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the DMA Global Status register to its default reset
+  *         values.
+  * @param  None
+  * @retval None
+  */
+void DMA_GlobalDeInit(void)
+{
+  /* Disable the  DMA    */
+  DMA1->GCSR &= (uint8_t)~(DMA_GCSR_GE);
+
+  /* Reset DMA Channelx control register */
+  DMA1->GCSR  = (uint8_t)DMA_GCSR_RESET_VALUE;
+}
+
+/**
+  * @brief  Deinitializes the DMA Channelx registers to their default reset 
+  *         values.
+  * @param  DMA_Channelx: selects the DMA Channelx where x can be 0 to 3
+  * @retval None
+  */
+void DMA_DeInit(DMA_Channel_TypeDef* DMA_Channelx)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA_CHANNEL(DMA_Channelx));
+
+  /* Disable the selected DMA Channelx */
+  DMA_Channelx->CCR &= (uint8_t)~(DMA_CCR_CE);
+
+  /* Reset DMA Channelx control register */
+  DMA_Channelx->CCR  = DMA_CCR_RESET_VALUE;
+
+  /* Reset DMA Channelx remaining bytes register */
+  DMA_Channelx->CNBTR = DMA_CNBTR_RESET_VALUE;
+
+  /* Reset DMA Channelx peripheral address register */
+  if (DMA_Channelx == DMA1_Channel3)
+  {
+    DMA_Channelx->CPARH  = DMA_C3PARH_RESET_VALUE;
+    DMA_Channelx->CM0EAR = DMA_C3M0EAR_RESET_VALUE;
+  }
+  else
+  {
+    DMA_Channelx->CPARH  = DMA_CPARH_RESET_VALUE;
+  }
+  DMA_Channelx->CPARL  = DMA_CPARL_RESET_VALUE;
+
+  /* Reset DMA Channelx memory address register */
+  DMA_Channelx->CM0ARH = DMA_CM0ARH_RESET_VALUE;
+  DMA_Channelx->CM0ARL = DMA_CM0ARL_RESET_VALUE;
+
+  /* Reset interrupt pending bits for DMA Channel */
+  DMA_Channelx->CSPR = DMA_CSPR_RESET_VALUE;
+}
+
+
+/**
+  * @brief  Initializes the DMA Channelx according to the specified parameters.
+  * @param  DMA_Channelx: selects the DMA Channelx where x can be 0 to 3
+  * @param  DMA_Memory0BaseAddr: Specifies  Memory 0 Base Address
+  * @param  DMA_PeripheralMemory1BaseAddr: Specifies DMA channelx Peripheral 
+  *         Base Address (if data is from/to  peripheral) or DMA channelx 
+  *         Memory1 Base Address (if data is from Memory0 to Memory1).
+  * @param  DMA_BufferSize: Specifies the size of the DMA channelx Buffer.
+  *         This parameter must be a value greater than 0.
+  * @param  DMA_DIR: Specifies the DMA Channelx transfer direction.
+  *          This parameter can be one of the following values:
+  *            @arg DMA_DIR_PeripheralToMemory: Data transfer direction is Peripheral To Memory
+  *            @arg DMA_DIR_MemoryToPeripheral: Data transfer direction is Memory To Peripheral
+  *            @arg DMA_DIR_Memory0ToMemory1: Data transfer direction is Memory0 To Memory 1    
+  * @param  DMA_Mode: Specifies the DMA channelx mode.
+  *          This parameter can be one of the following values:
+  *            @arg DMA_Mode_Normal: DMA normal buffer mode
+  *            @arg DMA_Mode_Circular: DMA circular buffer mode
+  * @param  DMA_MemoryIncMode: Specifies the DMA channelx memory Incremental/Decremental mode 
+  *          This parameter can be one of the following values:
+  *            @arg DMA_MemoryIncMode_Dec: DMA memory incremented mode is decremental
+  *            @arg DMA_MemoryIncMode_Inc: DMA memory incremented mode is incremental  
+  * @param  DMA_Priority: Specifies the DMA channelx priority.
+  *          This parameter can be one of the following values:
+  *            @arg DMA_Priority_Low: Software Priority is Low
+  *            @arg DMA_Priority_Medium: Software Priority is Medium
+  *            @arg DMA_Priority_High: Software Priority is High
+  *            @arg DMA_Priority_VeryHigh: Software Priority is Very High
+  * @param  DMA_MemoryDataSize: Specifies the DMA channelx transfer Data size
+  *          This parameter can be one of the following values:
+  *            @arg DMA_MemoryDataSize_Byte: Memory Data Size is 1 Byte
+  *            @arg DMA_MemoryDataSize_HalfWord: Memory Data Size is 2 Bytes  
+  * @retval None
+  */
+void DMA_Init(DMA_Channel_TypeDef* DMA_Channelx,
+              uint32_t DMA_Memory0BaseAddr,
+              uint16_t DMA_PeripheralMemory1BaseAddr,
+              uint8_t DMA_BufferSize,
+              DMA_DIR_TypeDef DMA_DIR,
+              DMA_Mode_TypeDef DMA_Mode,
+              DMA_MemoryIncMode_TypeDef DMA_MemoryIncMode,
+              DMA_Priority_TypeDef DMA_Priority,
+              DMA_MemoryDataSize_TypeDef DMA_MemoryDataSize )
+{
+  /* Check the parameters */
+  assert_param(IS_DMA_CHANNEL(DMA_Channelx));
+  assert_param(IS_DMA_DIR(DMA_DIR));
+  assert_param(IS_DMA_BUFFER_SIZE(DMA_BufferSize));
+  assert_param(IS_DMA_MODE(DMA_Mode));
+  assert_param(IS_DMA_MEMORY_INC_MODE(DMA_MemoryIncMode));
+  assert_param(IS_DMA_PRIORITY(DMA_Priority));
+
+  /*--------------------------- DMA Channelx CCR Configuration ---------------*/
+  /* Disable the selected DMA Channelx */
+  DMA_Channelx->CCR &= (uint8_t)~(DMA_CCR_CE);
+
+  /* Reset DMA Channelx control register */
+  DMA_Channelx->CCR  = DMA_CCR_RESET_VALUE;
+
+  /* Set DMA direction & Mode & Incremental Memory mode */
+  DMA_Channelx->CCR |= (uint8_t)((uint8_t)((uint8_t)DMA_DIR | \
+                                           (uint8_t)DMA_Mode) | \
+                                           (uint8_t)DMA_MemoryIncMode);
+
+  /*Clear old priority and memory data size  option */
+  DMA_Channelx->CSPR &= (uint8_t)(~(uint8_t)(DMA_CSPR_PL | DMA_CSPR_16BM));
+
+  /* Set old priority and memory data size  option */
+  DMA_Channelx->CSPR |= (uint8_t)((uint8_t)DMA_Priority | \
+                                  (uint8_t)DMA_MemoryDataSize);
+
+  /*--------------------------- DMA Channelx CNDTR Configuration -------------*/
+  /* Write to DMA Channelx CNDTR */
+  DMA_Channelx->CNBTR = (uint8_t)DMA_BufferSize;
+
+  /*--------------------------- DMA Channelx CPAR Configuration --------------*/
+  /* Write to DMA Channelx (0, 1 or 2)  Peripheral address  or  Write to 
+  DMA Channel 3 Memory 1 address  */
+  DMA_Channelx->CPARH = (uint8_t)(DMA_PeripheralMemory1BaseAddr >> (uint8_t)8);
+  DMA_Channelx->CPARL = (uint8_t)(DMA_PeripheralMemory1BaseAddr);
+
+  /*--------------------------- DMA Channelx CMAR Configuration --------------*/
+  /* Write to DMA Channelx Memory address */
+  if (DMA_Channelx == DMA1_Channel3)
+  {
+    DMA_Channelx->CM0EAR = (uint8_t)(DMA_Memory0BaseAddr >> (uint8_t)16);
+  }
+  DMA_Channelx->CM0ARH = (uint8_t)(DMA_Memory0BaseAddr >> (uint8_t)8);
+  DMA_Channelx->CM0ARL = (uint8_t)(DMA_Memory0BaseAddr);
+
+}
+
+/**
+  * @brief  Enables or disables All the DMA.
+  * @param  NewState: new state of the DMA. This parameter can be: ENABLE 
+  *                   or DISABLE.
+  * @retval None
+  */
+void DMA_GlobalCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the  DMA      */
+    DMA1->GCSR |= (uint8_t)DMA_GCSR_GE;
+  }
+  else
+  {
+    /* Disable the DMA */
+    DMA1->GCSR &= (uint8_t)(~DMA_GCSR_GE);
+  }
+}
+
+/**
+  * @brief  Enables or disables the specified DMA Channelx.
+  * @note   DMA_GlobalCmd function must be called first to enable or disable
+  *         the global DMA.
+  * @param  DMA_Channelx: selects the DMA Channelx where x can be 0 to 3
+  * @param  NewState: new state of the DMA Channelx.
+    *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DMA_Cmd(DMA_Channel_TypeDef* DMA_Channelx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA_CHANNEL(DMA_Channelx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected DMA Channelx */
+    DMA_Channelx->CCR |= DMA_CCR_CE;
+  }
+  else
+  {
+    /* Disable the selected DMA Channelx */
+    DMA_Channelx->CCR &= (uint8_t)(~DMA_CCR_CE);
+  }
+}
+
+/**
+  * @brief  Sets the Time out Value.
+  * @param  DMA_TimeOut: an integer from 0 to 63
+  * @note   If timeout duration >0 (number of wait cycles starting from the
+  *         latest request), the DMA waits until this timeout has elapsed before
+  *         requesting from the core a high priority access to the bus.
+  * @note   If timeout duration =0, there is no timeout and once a request is served,
+  *         the DMA immediately asks to the CPU a high priority access to the bus.
+  * @retval None
+  */
+void DMA_SetTimeOut(uint8_t DMA_TimeOut)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA_TIMEOUT(DMA_TimeOut));
+
+  /* set the time out, GB and GE must be = 0 */
+  DMA1->GCSR = 0;
+  DMA1->GCSR = (uint8_t)(DMA_TimeOut << (uint8_t)2);
+
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Group2 Data Counter functions
+ *  @brief   Data Counter functions 
+ *
+@verbatim   
+ ===============================================================================
+                           Data Counter functions
+ ===============================================================================  
+
+  This subsection provides functions allowing to configure and read the buffer 
+  size (number of data to be transferred). 
+
+  The DMA data counter can be written only when the DMA channel is disabled 
+  (ie. after transfer complete event).
+
+  The DMA_SetCurrDataCounter() function can be used to write the Channel data 
+  counter value.
+  
+
+  Note: It is advised to use this function rather than DMA_Init() (DMA_BufferSize 
+        parameter) in situations where only the Data buffer needs to be reloaded.
+
+  The DMA data counter can be read to indicate the number of remaining transfers 
+  for the relative DMA channel. This counter is decremented at the end of each 
+  data transfer and when the transfer is complete: 
+   - If Normal mode is selected: the counter is set to 0.
+   - If Circular mode is selected: the counter is reloaded with the initial value
+     (configured before enabling the DMA channel)
+   
+  The DMA_GetCurrDataCounter() function can be used to read the Channel current 
+  data counter value.
+     
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Set the number of data units to transfer for DMA Channelx.
+  * @param  DMA_Channelx: selects the DMA Channelx where x can be 0 to 3
+  * @param  DataNumber: The number of  data units to transfer, it can be any value
+  *         from 0 to 255
+  * @note   It is advised to use this function rather than DMA_Init() in situations
+  *         where only the Data buffer needs to be reloaded.  
+  * @retval None
+  */
+void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMA_Channelx, uint8_t DataNumber)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA_CHANNEL(DMA_Channelx));
+
+  /*Set the number of data units for DMA Channelx */
+  DMA_Channelx->CNBTR = DataNumber;
+}
+
+/**
+  * @brief  Returns the number of remaining data units in the current DMA Channelx transfer.
+  * @param  DMA_Channelx: selects the DMA Channelx where x can be 0 to 3
+  * @retval The number of remaining data units in the current DMA Channelx
+  */
+uint8_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMA_Channelx)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA_CHANNEL(DMA_Channelx));
+
+  /* Return the number of remaining data units for DMA Channelx */
+  return ((uint8_t)(DMA_Channelx->CNBTR));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Group3 Interrupts and flags management functions
+ *  @brief   Interrupts and flags management functions 
+ *
+@verbatim   
+ ===============================================================================
+                  Interrupts and flags management functions
+ ===============================================================================  
+
+  This subsection provides functions allowing to configure the DMA Interrupts 
+  sources and check or clear the flags or pending bits status.
+  The user should identify which mode will be used in his application to manage 
+  the DMA controller events: Polling mode or Interrupt mode. 
+    
+  Polling Mode
+  =============
+    Each DMA channel can be managed through 2 event Flags:
+    (x: DMA channel number )
+       1. DMA1_FLAG_TCx: to indicate that a Transfer Complete event occurred
+       2. DMA1_FLAG_HTx: to indicate that a Half-Transfer Complete event 
+                          occurred
+
+   In this Mode it is advised to use DMA_GetFlagStatus() and  DMA_ClearFlag() 
+   functions. 
+      
+
+  Interrupt Mode
+  ===============
+    Each DMA channel can be managed through 2 Interrupts:
+
+    Interrupt Source
+    ----------------
+       1. DMA_IT_TC: specifies the interrupt source for the Transfer Complete 
+                     event.  
+       2. DMA_IT_HT: specifies the interrupt source for the Half-transfer 
+                      Complete event.
+     
+  In this Mode it is advised to use DMA_ITConfig(), DMA_GetITStatus() and
+  DMA_ClearITPendingBit() functions.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the specified DMA Channelx interrupts.
+  * @param  DMA_Channelx: selects the DMA Channelx where x can be 0 to 3
+  * @param  DMA_ITx: specifies the DMA interrupts sources to be enabled or disabled. 
+  *          This parameter can be one of the following values:
+  *            @arg DMA_ITx_TC: Transaction Complete Interrupt
+  *            @arg DMA_ITx_HT: Half Transaction Interrupt  
+  * @param  NewState: new state of the specified DMA interrupts.
+    *       This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DMA_ITConfig(DMA_Channel_TypeDef* DMA_Channelx, 
+                  DMA_ITx_TypeDef DMA_ITx,
+                  FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA_CHANNEL(DMA_Channelx));
+  assert_param(IS_DMA_CONFIG_ITX(DMA_ITx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected DMA interrupts */
+    DMA_Channelx->CCR |= (uint8_t)(DMA_ITx);
+  }
+  else
+  {
+    /* Disable the selected DMA interrupts */
+    DMA_Channelx->CCR &= (uint8_t)~(DMA_ITx);
+  }
+}
+
+/**
+  * @brief  Checks whether the specified DMA Channelx flag is set or not.
+  * @param  DMA_FLAG: specifies the flag to check.
+  *          This parameter can be one of the following values:
+  *            @arg DMA1_FLAG_GB: Global Busy Flag
+  *            @arg DMA1_FLAG_IFC0: Global Interrupt Flag Channel 0
+  *            @arg DMA1_FLAG_IFC1: Global Interrupt Flag Channel 1
+  *            @arg DMA1_FLAG_IFC2: Global Interrupt Flag Channel 2
+  *            @arg DMA1_FLAG_IFC3: Global Interrupt Flag Channel 3
+  *            @arg DMA1_FLAG_TC0: Transaction Complete Interrupt Flag Channel 0
+  *            @arg DMA1_FLAG_TC1: Transaction Complete Interrupt Flag Channel 1
+  *            @arg DMA1_FLAG_TC2: Transaction Complete Interrupt Flag Channel 2
+  *            @arg DMA1_FLAG_TC2: Transaction Complete Interrupt Flag Channel 3
+  *            @arg DMA1_FLAG_HT0: Half Transaction Interrupt Flag Channel 0
+  *            @arg DMA1_FLAG_HT1: Half Transaction Interrupt Flag Channel 1
+  *            @arg DMA1_FLAG_HT2: Half Transaction Interrupt Flag Channel 2
+  *            @arg DMA1_FLAG_HT3: Half Transaction Interrupt Flag Channel 3
+  *            @arg DMA1_FLAG_PEND0: DMA Request pending on Channel 0
+  *            @arg DMA1_FLAG_PEND1: DMA Request pending on Channel 1
+  *            @arg DMA1_FLAG_PEND2: DMA Request pending on Channel 2
+  *            @arg DMA1_FLAG_PEND3: DMA Request pending on Channel 3
+  *            @arg DMA1_FLAG_BUSY0: No DMA transfer on going in Channel 0
+  *            @arg DMA1_FLAG_BUSY1: No DMA transfer on going in Channel 1 
+  *            @arg DMA1_FLAG_BUSY2: No DMA transfer on going in Channel 2 
+  *            @arg DMA1_FLAG_BUSY3: No DMA transfer on going in Channel 3                                        
+  * @retval  The status of DMA_FLAG (SET or RESET).
+  */
+FlagStatus DMA_GetFlagStatus(DMA_FLAG_TypeDef DMA_FLAG)
+{
+  FlagStatus flagstatus = RESET;
+  DMA_Channel_TypeDef* DMA_Channelx =  DMA1_Channel0;
+  uint8_t tmpgir1 = 0;
+  uint8_t tmpgcsr = 0;
+
+  /* Check the parameters */
+  assert_param(IS_DMA_GET_FLAG(DMA_FLAG));
+
+  /* Get flags registers values*/
+  tmpgcsr = DMA1->GCSR;
+  tmpgir1 = DMA1->GIR1;
+
+  if (((uint16_t)DMA_FLAG & (uint16_t)0x0F00) != (uint16_t)RESET)
+  {
+    /* find  the used DMA  channel */
+    if (((uint16_t)DMA_FLAG & 0x0100) != (uint16_t)RESET)
+    {
+      DMA_Channelx = DMA1_Channel0;
+    }
+    else if  (((uint16_t)DMA_FLAG & 0x0200) != (uint16_t)RESET)
+    {
+      DMA_Channelx = DMA1_Channel1;
+    }
+    else if  (((uint16_t)DMA_FLAG & 0x0400) != (uint16_t)RESET)
+    {
+      DMA_Channelx = DMA1_Channel2;
+    }
+    else
+    {
+      DMA_Channelx = DMA1_Channel3;
+    }
+
+    /*   Get the specified DMA Channelx flag status. */
+    flagstatus = (FlagStatus)((uint8_t)(DMA_Channelx->CSPR) & (uint8_t)DMA_FLAG);
+  }
+  else if (((uint16_t)DMA_FLAG & 0x1000) != (uint16_t)RESET)
+  {
+    /*   Get the specified DMA Channelx flag status. */
+    flagstatus = (FlagStatus)(tmpgir1 & (uint8_t)DMA_FLAG);
+  }
+  else /*if ((DMA_FLAG & DMA_FLAG_GB) != (uint16_t)RESET)*/
+  {
+    /*   Get the specified DMA Channelx flag status. */
+    flagstatus = (FlagStatus)(tmpgcsr & DMA_GCSR_GB);
+  }
+
+  /*  Return the specified DMA Channelx flag status. */
+  return (flagstatus);
+}
+
+/**
+  * @brief  Clears the DMA Channels selected flags.
+  * @param  DMA_FLAG: specifies the flag to clear.
+  *          This parameter can be one or a combination (for the same channel)of
+  *          the following values:
+  *            @arg DMA1_FLAG_TC0: Transaction Complete Interrupt Flag Channel 0
+  *            @arg DMA1_FLAG_TC1: Transaction Complete Interrupt Flag Channel 1
+  *            @arg DMA1_FLAG_TC2: Transaction Complete Interrupt Flag Channel 2
+  *            @arg DMA1_FLAG_TC2: Transaction Complete Interrupt Flag Channel 3
+  *            @arg DMA1_FLAG_HT0: Half Transaction Interrupt Flag Channel 0
+  *            @arg DMA1_FLAG_HT1: Half Transaction Interrupt Flag Channel 1
+  *            @arg DMA1_FLAG_HT2: Half Transaction Interrupt Flag Channel 2
+  *            @arg DMA1_FLAG_HT3: Half Transaction Interrupt Flag Channel 3
+  * @retval None
+  */
+void DMA_ClearFlag(DMA_FLAG_TypeDef DMA_FLAG)
+{
+  DMA_Channel_TypeDef* DMA_Channelx =  DMA1_Channel0;
+
+  /* Check the parameters */
+  assert_param(IS_DMA_CLEAR_FLAG(DMA_FLAG));
+
+  /* Identify  the used DMA  channel */
+  if (((uint16_t)DMA_FLAG & (uint16_t)0x0100) != (uint16_t)RESET)
+  {
+    DMA_Channelx = DMA1_Channel0;
+  }
+  else
+  {
+    if (((uint16_t)DMA_FLAG & (uint16_t)0x0200) != (uint16_t)RESET)
+    {
+      DMA_Channelx = DMA1_Channel1;
+    }
+    else
+    {
+      if (((uint16_t)DMA_FLAG & (uint16_t)0x0400) != (uint16_t)RESET)
+      {
+        DMA_Channelx = DMA1_Channel2;
+      }
+      else
+      {
+        DMA_Channelx = DMA1_Channel3;
+      }
+    }
+  }
+
+  /*Clears the DMA flags.*/
+  DMA_Channelx->CSPR &= (uint8_t)~(uint8_t)((uint8_t)DMA_FLAG & (uint8_t)0x06);
+}
+
+/**
+  * @brief  Checks whether the specified DMA Channelx interrupt has occurred or not.
+  * @param  DMA_IT: specifies the DMA interrupt source to check.
+  *          This parameter can be one or a combination of the following values:
+  *            @arg DMA1_IT_TC0: Transaction Complete Interrupt Channel 0
+  *            @arg DMA1_IT_TC1: Transaction Complete Interrupt Channel 1
+  *            @arg DMA1_IT_TC2: Transaction Complete Interrupt Channel 2
+  *            @arg DMA1_IT_TC3: Transaction Complete Interrupt Channel 3
+  *            @arg DMA1_IT_HT0: Half Transaction Interrupt Channel 0
+  *            @arg DMA1_IT_HT1: Half Transaction Interrupt Channel 1
+  *            @arg DMA1_IT_HT2: Half Transaction Interrupt Channel 2
+  *            @arg DMA1_IT_HT3: Half Transaction Interrupt Channel 3    
+  * @retval ITStatus: The status of DMA_IT (SET or RESET).
+  */
+ITStatus DMA_GetITStatus(DMA_IT_TypeDef DMA_IT)
+{
+  ITStatus itstatus = RESET;
+  uint8_t tmpreg = 0;
+  uint8_t tmp2 = 0;
+  DMA_Channel_TypeDef* DMA_Channelx =  DMA1_Channel0;
+
+  /* Check the parameters */
+  assert_param(IS_DMA_GET_IT(DMA_IT));
+
+  /* Identify  the used DMA  channel */
+  if ((DMA_IT & 0x10) != (uint8_t)RESET)
+  {
+    DMA_Channelx = DMA1_Channel0;
+  }
+  else
+  {
+    if  ((DMA_IT & 0x20) != (uint8_t)RESET)
+    {
+      DMA_Channelx = DMA1_Channel1;
+    }
+    else
+    {
+      if  ((DMA_IT & 0x40) != (uint8_t)RESET)
+      {
+        DMA_Channelx = DMA1_Channel2;
+      }
+      else
+      {
+        DMA_Channelx = DMA1_Channel3;
+      }
+    }
+  }
+  /*   Get the specified DMA Channelx interrupt status. */
+  tmpreg =  DMA_Channelx->CSPR ;
+  tmpreg &= DMA_Channelx->CCR ;
+  tmp2 = (uint8_t)(DMA_IT & (uint8_t)(DMA_CCR_TCIE | DMA_CCR_HTIE));
+  itstatus = (ITStatus)((uint8_t)tmpreg & (uint8_t)tmp2);
+
+  /*   Return the specified DMA Channelx interrupt status. */
+  return (itstatus);
+}
+
+/**
+  * @brief  Clears the DMA Channelx’s interrupt pending bits.
+  * @param  DMA_IT: specifies the DMA interrupt pending bit to clear.
+  *          This parameter can be one or a combination(for the same channel)of 
+  *          the following values:
+  *            @arg DMA1_IT_TC0: Transaction Complete Interrupt Channel 0
+  *            @arg DMA1_IT_TC1: Transaction Complete Interrupt Channel 1
+  *            @arg DMA1_IT_TC2: Transaction Complete Interrupt Channel 2
+  *            @arg DMA1_IT_TC3: Transaction Complete Interrupt Channel 3
+  *            @arg DMA1_IT_HT0: Half Transaction Interrupt Channel 0
+  *            @arg DMA1_IT_HT1: Half Transaction Interrupt Channel 1
+  *            @arg DMA1_IT_HT2: Half Transaction Interrupt Channel 2
+  *            @arg DMA1_IT_HT3: Half Transaction Interrupt Channel 3 
+  * @retval None
+  */
+void DMA_ClearITPendingBit(DMA_IT_TypeDef DMA_IT)
+{
+  DMA_Channel_TypeDef* DMA_Channelx =  DMA1_Channel0;
+
+  /* Check the parameters */
+  assert_param(IS_DMA_CLEAR_IT(DMA_IT));
+  /* Identify  the used DMA  channel */
+  if ((DMA_IT & 0x10) != (uint8_t)RESET)
+  {
+    DMA_Channelx = DMA1_Channel0;
+  }
+  else
+  {
+    if ((DMA_IT & 0x20) != (uint8_t)RESET)
+    {
+      DMA_Channelx = DMA1_Channel1;
+    }
+    else
+    {
+      if ((DMA_IT & 0x40) != (uint8_t)RESET)
+      {
+        DMA_Channelx = DMA1_Channel2;
+      }
+      else
+      {
+        DMA_Channelx = DMA1_Channel3;
+      }
+    }
+  }
+  /*Clears the DMA Channelx’s interrupt pending bits*/
+  DMA_Channelx->CSPR &= (uint8_t)~(uint8_t)(DMA_IT & (uint8_t)0x06);
+}
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+  
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_exti.c b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_exti.c
new file mode 100755
index 0000000..ebfc375
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_exti.c
@@ -0,0 +1,556 @@
+/**
+  ******************************************************************************
+  * @file    stm8l15x_exti.c
+  * @author  MCD Application Team
+  * @version V1.6.0
+  * @date    28-June-2013
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the EXTI peripheral:
+  *            - Interrupt sensitivity of GPIO ports/pins configuration
+  *            - Interrupt status management
+  *  @verbatim
+  *  
+  *          ===================================================================
+  *                                 How to use this driver
+  *          ===================================================================
+  *          This driver provides functions to configure and initialise the EXTI 
+  *          peripheral
+  *          These functions are split in 2 groups: 
+  *   
+  *          1. EXTI configuration: this group includes all needed functions 
+  *             to configure the EXTI GPIO ports and pins:
+  *                   - Set GPIO pins sensitivity
+  *                   - Select GPIO port, GPIO half port and set the GPIO port sensitivity
+  *                         
+  *          2. EXTI interrupt status management
+  *                   - Get the interrupt status: set/reset
+  *                   - Clear interrupt pending bits
+  *
+  *  @endverbatim
+  *   
+  ******************************************************************************
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ****************************************************************************** 
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm8l15x_exti.h"
+
+/** @addtogroup STM8L15x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup EXTI 
+  * @brief EXTI driver modules
+  * @{
+  */ 
+  
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup EXTI_Private_Functions
+  * @{
+  */
+
+/** @defgroup EXTI_Group1 Interrupt sensitivity of GPIO ports/pins configuration
+ *  @brief   Interrupt sensitivity of GPIO ports/pins configuration
+ *
+@verbatim   
+ ===============================================================================
+                         EXTI configuration functions
+ ===============================================================================  
+  
+       ===================================================================      
+                        EXTI Driver: how to configure EXTI
+       =================================================================== 
+       To use a GPIO pin as an interrupt source, follow theses steps:
+       
+         1. Configure the GPIO pin in input mode with interrupt enabled using
+            GPIO_Init()
+          
+         2. Configure the GPIO pin sensitivity (falling, rising...) using 
+            EXTI_SetPinSensitivity()
+          
+         3. Enable global interrupts using enableInterrupts()
+       
+         4. In the IRQ handler corresponding to the GPIO pin, clear the interrupt
+            pending bit using EXTI_ClearITPendingBit()
+
+       To use a GPIO port as an interrupt source, follows theses steps:  
+            
+         1. Configure the GPIO pins of the same port in input mode with interrupt
+            enabled using GPIO_Init()
+          
+         2. Configure the GPIO port sensitivity (falling, rising...) using 
+            EXTI_SetPortSensitivity()
+          
+         3. Select the GPIO port and the corresponding half port using  
+            EXTI_SelectPort() then EXTI_SetHalfPortSelection()
+        
+         4. Enable global interrupts using enableInterrupts()
+       
+         5. In the IRQ handler corresponding to the GPIO port, clear the interrupt
+            pending bit using EXTI_ClearITPendingBit()
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the EXTI registers to their default reset value.
+  * @param  None
+  * @retval None
+  */
+void EXTI_DeInit(void)
+{
+  EXTI->CR1 = EXTI_CR1_RESET_VALUE;
+  EXTI->CR2 = EXTI_CR2_RESET_VALUE;
+  EXTI->CR3 = EXTI_CR3_RESET_VALUE;
+  EXTI->CR4 = EXTI_CR4_RESET_VALUE;
+  EXTI->SR1 = 0xFF; /* Setting SR1 bits in order to clear flags */
+  EXTI->SR2 = 0xFF; /* Setting SR2 bits in order to clear flags */
+  EXTI->CONF1 = EXTI_CONF1_RESET_VALUE;
+  EXTI->CONF2 = EXTI_CONF2_RESET_VALUE;
+}
+
+/**
+  * @brief  Sets the external interrupt sensitivity of the selected pin.
+  * @note   Global interrupts must be disabled before calling this function.
+  * @note   The modification of external interrupt sensitivity is only possible
+  *         when he interrupts are disabled.
+  * @note   The normal behavior is to disable the interrupts before calling this
+  *         function, and re-enable them after.
+  * @param  EXTI_Pin : The pin to configure.
+  *          This parameter can be one of the following values:
+  *            @arg EXTI_Pin_0: GPIO Pin 0
+  *            @arg EXTI_Pin_1: GPIO Pin 1
+  *            @arg EXTI_Pin_2: GPIO Pin 2
+  *            @arg EXTI_Pin_3: GPIO Pin 3
+  *            @arg EXTI_Pin_4: GPIO Pin 4
+  *            @arg EXTI_Pin_5: GPIO Pin 5
+  *            @arg EXTI_Pin_6: GPIO Pin 6
+  *            @arg EXTI_Pin_7: GPIO Pin 7              
+  * @param  EXTI_Trigger : The external interrupt sensitivity value to set.
+  *          This parameter can be one of the following values:
+  *            @arg EXTI_Trigger_Falling_Low: Interrupt on Falling edge and Low level
+  *            @arg EXTI_Trigger_Rising: Interrupt on Rising edge only  
+  *            @arg EXTI_Trigger_Falling: Interrupt on Falling edge only 
+  *            @arg EXTI_Trigger_Rising_Falling: Interrupt on Rising and Falling edges       
+  * @retval None
+  */
+void EXTI_SetPinSensitivity(EXTI_Pin_TypeDef EXTI_Pin, EXTI_Trigger_TypeDef EXTI_Trigger)
+{
+
+  /* Check function parameters */
+  assert_param(IS_EXTI_PINNUM(EXTI_Pin));
+  assert_param(IS_EXTI_TRIGGER(EXTI_Trigger));
+
+  /* Clear port sensitivity bits */
+  switch (EXTI_Pin)
+  {
+    case EXTI_Pin_0:
+      EXTI->CR1 &=  (uint8_t)(~EXTI_CR1_P0IS);
+      EXTI->CR1 |= (uint8_t)((uint8_t)(EXTI_Trigger) << EXTI_Pin);
+      break;
+    case EXTI_Pin_1:
+      EXTI->CR1 &=  (uint8_t)(~EXTI_CR1_P1IS);
+      EXTI->CR1 |= (uint8_t)((uint8_t)(EXTI_Trigger) << EXTI_Pin);
+      break;
+    case EXTI_Pin_2:
+      EXTI->CR1 &=  (uint8_t)(~EXTI_CR1_P2IS);
+      EXTI->CR1 |= (uint8_t)((uint8_t)(EXTI_Trigger) << EXTI_Pin);
+      break;
+    case EXTI_Pin_3:
+      EXTI->CR1 &=  (uint8_t)(~EXTI_CR1_P3IS);
+      EXTI->CR1 |= (uint8_t)((uint8_t)(EXTI_Trigger) << EXTI_Pin);
+      break;
+    case EXTI_Pin_4:
+      EXTI->CR2 &=  (uint8_t)(~EXTI_CR2_P4IS);
+      EXTI->CR2 |= (uint8_t)((uint8_t)(EXTI_Trigger) << ((uint8_t)EXTI_Pin & (uint8_t)0xEF));
+      break;
+    case EXTI_Pin_5:
+      EXTI->CR2 &=  (uint8_t)(~EXTI_CR2_P5IS);
+      EXTI->CR2 |= (uint8_t)((uint8_t)(EXTI_Trigger) << ((uint8_t)EXTI_Pin & (uint8_t)0xEF));
+      break;
+    case EXTI_Pin_6:
+      EXTI->CR2 &=  (uint8_t)(~EXTI_CR2_P6IS);
+      EXTI->CR2 |= (uint8_t)((uint8_t)(EXTI_Trigger) << ((uint8_t)EXTI_Pin & (uint8_t)0xEF));
+      break;
+    case EXTI_Pin_7:
+      EXTI->CR2 &=  (uint8_t)(~EXTI_CR2_P7IS);
+      EXTI->CR2 |= (uint8_t)((uint8_t)(EXTI_Trigger) << ((uint8_t)EXTI_Pin & (uint8_t)0xEF));
+      break;
+    default:
+      break;
+  }
+}
+
+/**
+  * @brief  Selects the port interrupt selection.
+  * @param  EXTI_Port : The port number to access.
+  *          This parameter can be one of the following values:
+  *            @arg EXTI_Port_B: GPIO Port B
+  *            @arg EXTI_Port_D: GPIO Port D
+  *            @arg EXTI_Port_E: GPIO Port E
+  *            @arg EXTI_Port_F: GPIO Port F
+  *            @arg EXTI_Port_G: GPIO Port G
+  *            @arg EXTI_Port_H: GPIO Port H   
+  * @retval None
+  */
+void EXTI_SelectPort(EXTI_Port_TypeDef EXTI_Port)
+{
+  /* Check function parameter */
+  assert_param(IS_EXTI_PORT(EXTI_Port));
+
+  if (EXTI_Port == EXTI_Port_B)
+  {
+    /* Select Port B by resetting PGBS bit in CONF2 register */
+    EXTI->CONF2 &= (uint8_t) (~EXTI_CONF2_PGBS);
+  }
+  else if (EXTI_Port == EXTI_Port_D)
+  {
+    /* Select Port D by resetting PHDS bit in CONF2 register */
+    EXTI->CONF2 &= (uint8_t) (~EXTI_CONF2_PHDS);
+  }
+  else if (EXTI_Port == EXTI_Port_E)
+  {
+    /* Select Port E by resetting PFES bit in CONF1 register */
+    EXTI->CONF1 &= (uint8_t) (~EXTI_CONF1_PFES);
+  }
+  else if (EXTI_Port == EXTI_Port_F)
+  {
+    /* Select Port F by setting PFES bit in CONF1 register */
+    EXTI->CONF1 |= (uint8_t) (EXTI_CONF1_PFES);
+  }
+  else if (EXTI_Port == EXTI_Port_G)
+  {
+    /* Select Port G by setting PGBS bit in CONF2 register */
+    EXTI->CONF2 |= (uint8_t) (EXTI_CONF2_PGBS);
+  }
+  else /* EXTI_Port is EXTI_Port_H */
+  {
+    /* Select Port H by setting PHDS bit in CONF2 register */
+    EXTI->CONF2 |= (uint8_t) (EXTI_CONF2_PHDS);
+  }
+}
+
+/**
+  * @brief  Configures the half port interrupt selection.
+  * @note   This function should be called once the port sensitivity configured,
+  *         otherwise it will not have any effect on the port external interrupt.
+  * @note   This function should be called after EXTI_SelectPort() function which
+  *         selects the port to be used otherwise ports are selected by default
+  * @param  EXTI_HalfPort : The port part to access (MSB or LSB).
+  *          This parameter can be one of the following values:
+  *            @arg EXTI_HalfPort_B_LSB: Interrupt selector PB(3:0)
+  *            @arg EXTI_HalfPort_B_MSB: Interrupt selector PB(7:4)
+  *            @arg EXTI_HalfPort_D_LSB: Interrupt selector PD(3:0)
+  *            @arg EXTI_HalfPort_D_MSB: Interrupt selector PD(7:4)
+  *            @arg EXTI_HalfPort_E_LSB: Interrupt selector PE(3:0)
+  *            @arg EXTI_HalfPort_E_MSB: Interrupt selector PE(7:4)
+  *            @arg EXTI_HalfPort_F_LSB: Interrupt selector PF(3:0)
+  *            @arg EXTI_HalfPort_F_MSB: Interrupt selector PF(7:4)
+  *            @arg EXTI_HalfPort_G_LSB: Interrupt selector PG(3:0)
+  *            @arg EXTI_HalfPort_G_MSB: Interrupt selector PG(7:4)
+  *            @arg EXTI_HalfPort_H_LSB: Interrupt selector PH(3:0)
+  *            @arg EXTI_HalfPort_H_MSB: Interrupt selector PH(7:4)                      
+  * @param  NewState : The external interrupt new state.
+    *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void EXTI_SetHalfPortSelection(EXTI_HalfPort_TypeDef EXTI_HalfPort,
+                               FunctionalState NewState)
+{
+  /* Check function parameters */
+  assert_param(IS_EXTI_HALFPORT(EXTI_HalfPort));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if ((EXTI_HalfPort & 0x80) == 0x00)
+  {
+    if (NewState != DISABLE)
+    {
+      /* Enable port interrupt selector */
+      EXTI->CONF1 |= (uint8_t)EXTI_HalfPort;
+    }
+    else /*NewState == DISABLE */
+    {
+      /* Disable port interrupt selector */
+      EXTI->CONF1 &= (uint8_t)(~(uint8_t)EXTI_HalfPort);
+    }
+  }
+  else
+  {
+    if (NewState != DISABLE)
+    {
+      /* Enable port interrupt selector */
+      EXTI->CONF2 |= (uint8_t)(EXTI_HalfPort & (uint8_t)0x7F);
+    }
+    else /*NewState == DISABLE */
+    {
+      /* Disable port interrupt selector */
+      EXTI->CONF2 &= (uint8_t)(~(uint8_t) (EXTI_HalfPort & (uint8_t)0x7F));
+    }
+  }
+}
+
+/**
+  * @brief  Sets the external interrupt sensitivity of the selected port.
+  * @note   Global interrupts must be disabled before calling this function.
+  * @note   The modification of external interrupt sensitivity is only possible
+  *         when the interrupts are disabled.
+  * @note   The normal behavior is to disable the interrupts before calling this
+  *         function, and re-enable them after.
+  * @param  EXTI_Port : The port number to access.
+  *          This parameter can be one of the following values:
+  *            @arg EXTI_Port_B: GPIO Port B
+  *            @arg EXTI_Port_D: GPIO Port D
+  *            @arg EXTI_Port_E: GPIO Port E
+  *            @arg EXTI_Port_F: GPIO Port F
+  *            @arg EXTI_Port_G: GPIO Port G
+  *            @arg EXTI_Port_H: GPIO Port H  
+  * @param  EXTI_Trigger : The external interrupt sensitivity value to set.
+  *          This parameter can be one of the following values:
+  *            @arg EXTI_Trigger_Falling_Low: Interrupt on Falling edge and Low level
+  *            @arg EXTI_Trigger_Rising: Interrupt on Rising edge only  
+  *            @arg EXTI_Trigger_Falling: Interrupt on Falling edge only 
+  *            @arg EXTI_Trigger_Rising_Falling: Interrupt on Rising and Falling edges 
+  * @retval None
+  */
+void EXTI_SetPortSensitivity(EXTI_Port_TypeDef EXTI_Port,
+                             EXTI_Trigger_TypeDef EXTI_Trigger)
+{
+  /* Check function parameters */
+  assert_param(IS_EXTI_PORT(EXTI_Port));
+  assert_param(IS_EXTI_TRIGGER(EXTI_Trigger));
+
+  /* Ceck if selected port is in EXTI_CR3 register */
+  if ((EXTI_Port & 0xF0) == 0x00)
+  {
+    /* Reset the trigger bits corresponding to EXTI_Port */
+    EXTI->CR3 &= (uint8_t) (~(uint8_t)((uint8_t)0x03 << EXTI_Port));
+    /* Write EXTI port trigger */
+    EXTI->CR3 |= (uint8_t)((uint8_t)(EXTI_Trigger) << EXTI_Port);
+  }
+  else /* selected port is in EXTI_CR4 register */
+  {
+    /* Reset the trigger bits corresponding to EXTI_Port */
+    EXTI->CR4 &= (uint8_t) (~(uint8_t)((uint8_t)0x03 << (EXTI_Port & 0x0F)));
+    /* Write EXTI port trigger */
+    EXTI->CR4 |= (uint8_t)(EXTI_Trigger << (EXTI_Port & 0x0F));
+  }
+}
+
+/**
+  * @brief  Gets the external interrupt sensitivity of the selected pin.
+  * @param  EXTI_Pin : The pin number to access.
+  *          This parameter can be one of the following values:
+  *            @arg EXTI_Pin_0: GPIO Pin 0
+  *            @arg EXTI_Pin_1: GPIO Pin 1
+  *            @arg EXTI_Pin_2: GPIO Pin 2
+  *            @arg EXTI_Pin_3: GPIO Pin 3
+  *            @arg EXTI_Pin_4: GPIO Pin 4
+  *            @arg EXTI_Pin_5: GPIO Pin 5
+  *            @arg EXTI_Pin_6: GPIO Pin 6
+  *            @arg EXTI_Pin_7: GPIO Pin 7 
+  * @retval The external interrupt sensitivity of the selected port.
+  */
+EXTI_Trigger_TypeDef EXTI_GetPinSensitivity(EXTI_Pin_TypeDef EXTI_Pin)
+{
+  uint8_t value = 0;
+
+  /* Check function parameters */
+  assert_param(IS_EXTI_PINNUM(EXTI_Pin));
+
+  switch (EXTI_Pin)
+  {
+    case EXTI_Pin_0:
+      value = (uint8_t)(EXTI->CR1 & EXTI_CR1_P0IS);
+      break;
+    case EXTI_Pin_1:
+      value = (uint8_t)((uint8_t)(EXTI->CR1 & EXTI_CR1_P1IS) >> EXTI_Pin_1);
+      break;
+    case EXTI_Pin_2:
+      value = (uint8_t)((uint8_t)(EXTI->CR1 & EXTI_CR1_P2IS) >> EXTI_Pin_2);
+      break;
+    case EXTI_Pin_3:
+      value = (uint8_t)((uint8_t)(EXTI->CR1 & EXTI_CR1_P3IS) >> EXTI_Pin_3);
+      break;
+    case EXTI_Pin_4:
+      value = (uint8_t)(EXTI->CR2 & EXTI_CR2_P4IS);
+      break;
+    case EXTI_Pin_5:
+      value = (uint8_t)((uint8_t)(EXTI->CR2 & EXTI_CR2_P5IS) >> ((uint8_t)EXTI_Pin_5 & (uint8_t)0x0F));
+      break;
+    case EXTI_Pin_6:
+      value = (uint8_t)((uint8_t)(EXTI->CR2 & EXTI_CR2_P6IS) >> ((uint8_t)EXTI_Pin_6 & (uint8_t)0x0F));
+      break;
+    case EXTI_Pin_7:
+      value = (uint8_t)((uint8_t)(EXTI->CR2 & EXTI_CR2_P7IS) >> ((uint8_t)EXTI_Pin_7 & (uint8_t)0x0F));
+      break;
+    default:
+      break;
+  }
+  return((EXTI_Trigger_TypeDef)value);
+}
+
+/**
+  * @brief  Gets the external interrupt sensitivity of the selected port.
+  * @param  EXTI_Port : The port number to access.
+  *          This parameter can be one of the following values:
+  *            @arg EXTI_Port_B: GPIO Port B
+  *            @arg EXTI_Port_D: GPIO Port D
+  *            @arg EXTI_Port_E: GPIO Port E
+  *            @arg EXTI_Port_F: GPIO Port F
+  *            @arg EXTI_Port_G: GPIO Port G
+  *            @arg EXTI_Port_H: GPIO Port H  
+  * @retval The external interrupt sensitivity of the selected port.
+  */
+EXTI_Trigger_TypeDef EXTI_GetPortSensitivity(EXTI_Port_TypeDef EXTI_Port)
+{
+  uint8_t portsensitivity = 0;
+
+  /* Check function parameters */
+  assert_param(IS_EXTI_PORT(EXTI_Port));
+
+  /* Check if selected port is in EXTI_CR3 */
+  if ((EXTI_Port & 0xF0) == 0x00)
+  {
+    /* Get port sensitivity */
+    portsensitivity = (uint8_t)((uint8_t)0x03 & (uint8_t)(EXTI->CR3 >> EXTI_Port));
+  }
+  /* selected port is in EXTI_CR4 */
+  else
+  {
+    /* Get port sensitivity */
+    portsensitivity = (uint8_t)((uint8_t)0x03 & (uint8_t)(EXTI->CR4 >> (EXTI_Port & 0x0F)));
+  }
+
+  return((EXTI_Trigger_TypeDef)portsensitivity);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_Group2 EXTI Interrupt status management functions
+ *  @brief    EXTI Interrupt status management functions
+ *
+@verbatim   
+ ===============================================================================
+                   EXTI Interrupt status management functions
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Gets the external interrupt status.
+  * @param  EXTI_IT : Specifies the interrupt to read.
+  *          This parameter can be one of the following values:
+  *            @arg EXTI_IT_Pin0: GPIO Pin 0
+  *            @arg EXTI_IT_Pin1: GPIO Pin 1
+  *            @arg EXTI_IT_Pin2: GPIO Pin 2
+  *            @arg EXTI_IT_Pin3: GPIO Pin 3
+  *            @arg EXTI_IT_Pin4: GPIO Pin 4
+  *            @arg EXTI_IT_Pin5: GPIO Pin 5
+  *            @arg EXTI_IT_Pin6: GPIO Pin 6
+  *            @arg EXTI_IT_Pin7: GPIO Pin 7 
+  *            @arg EXTI_IT_PortB: GPIO Port B
+  *            @arg EXTI_IT_PortD: GPIO Port D
+  *            @arg EXTI_IT_PortE: GPIO Port E
+  *            @arg EXTI_IT_PortF: GPIO Port F
+  *            @arg EXTI_IT_PortG: GPIO Port G
+  *            @arg EXTI_IT_PortH: GPIO Port H           
+  * @retval The status of the specified interrupt.
+  *         This parameter can be a SET or RESET
+  */
+ITStatus EXTI_GetITStatus(EXTI_IT_TypeDef EXTI_IT)
+{
+  ITStatus status = RESET;
+  /* Check function parameters */
+  assert_param(IS_EXTI_ITPENDINGBIT(EXTI_IT));
+
+  if (((uint16_t)EXTI_IT & (uint16_t)0xFF00) == 0x0100)
+  {
+    status = (ITStatus)(EXTI->SR2 & (uint8_t)((uint16_t)EXTI_IT & (uint16_t)0x00FF));
+  }
+  else
+  {
+    status = (ITStatus)(EXTI->SR1 & ((uint8_t)((uint16_t)EXTI_IT & (uint16_t)0x00FF)));
+  }
+  return((ITStatus)status);
+}
+
+/**
+  * @brief  Clears the specified interrupt pending bit
+  * @param  EXTI_IT : Specifies the interrupt to clear
+  *          This parameter can be one of the following values:
+  *            @arg EXTI_IT_Pin0: GPIO Pin 0
+  *            @arg EXTI_IT_Pin1: GPIO Pin 1
+  *            @arg EXTI_IT_Pin2: GPIO Pin 2
+  *            @arg EXTI_IT_Pin3: GPIO Pin 3
+  *            @arg EXTI_IT_Pin4: GPIO Pin 4
+  *            @arg EXTI_IT_Pin5: GPIO Pin 5
+  *            @arg EXTI_IT_Pin6: GPIO Pin 6
+  *            @arg EXTI_IT_Pin7: GPIO Pin 7 
+  *            @arg EXTI_IT_PortB: GPIO Port B
+  *            @arg EXTI_IT_PortD: GPIO Port D
+  *            @arg EXTI_IT_PortE: GPIO Port E
+  *            @arg EXTI_IT_PortF: GPIO Port F
+  *            @arg EXTI_IT_PortG: GPIO Port G
+  *            @arg EXTI_IT_PortH: GPIO Port H  
+  * @retval None
+  */
+void EXTI_ClearITPendingBit(EXTI_IT_TypeDef EXTI_IT)
+{
+  uint16_t tempvalue = 0;
+
+  /* Check function parameters */
+  assert_param(IS_EXTI_ITPENDINGBIT(EXTI_IT));
+
+  tempvalue = ((uint16_t)EXTI_IT & (uint16_t)0xFF00);
+
+  if ( tempvalue == 0x0100)
+  {
+    EXTI->SR2 = (uint8_t)((uint16_t)EXTI_IT & (uint16_t)0x00FF);
+  }
+  else
+  {
+    EXTI->SR1 = (uint8_t) (EXTI_IT);
+  }
+}
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+  
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_flash.c b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_flash.c
new file mode 100755
index 0000000..69d3518
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_flash.c
@@ -0,0 +1,914 @@
+/**
+  ******************************************************************************
+  * @file    stm8l15x_flash.c
+  * @author  MCD Application Team
+  * @version V1.6.0
+  * @date    28-June-2013
+  * @brief   This file provides all the Flash firmware functions. These functions 
+  *          can be executed from Internal FLASH or Internal RAM memories.
+  *            - FLASH program and Data EEPROM memories interface configuration
+  *            - FLASH program and Data EEPROM memories Programming
+  *            - Option Bytes Programming
+  *            - Interrupts and flags management
+  *            - Functions to be executed from RAM
+  *               
+  *  @verbatim
+  *  
+  *          ===================================================================
+  *                                 How to use this driver
+  *          ===================================================================
+  *                           
+  *          This driver provides functions to configure and program the Flash 
+  *          memory of all STM8L15x devices
+  *          These functions are split in 4 groups
+  * 
+  *           1. FLASH program and Data EEPROM memories interface configuration 
+  *              functions: this group includes the management of the following 
+  *              features:
+  *                    - Set the fixed programming time
+  *                    - Configure the power state during WFI mode
+  *                    - Configure the power state during run, low power run and
+  *                      WFE modes (should be executed from internal RAM) 
+  *  
+  *           2. FLASH program and Data EEPROM memories Programming functions: 
+  *              this group includes all needed functions to erase and program 
+  *              the FLASH program or the Data EEPROM memory.
+  *                    - Lock and Unlock the Flash program interface.
+  *                    - Lock and Unlock the Data EEPROM interface.  
+  *                    - Erase function: Erase Byte, Erase Word and Erase Block 
+  *                      (should be executed from internal RAM). 
+  *                    - Program functions: Program Byte, Program Word, 
+  *                      Program Block (should be executed from internal RAM) 
+  *                      and Fast Program Block (should be executed from internal
+  *                      RAM).
+  *    
+  *           3. FLASH Option Bytes Programming functions: this group includes 
+  *              all needed functions to:
+  *                    - Program/erase the user option Bytes 
+  *                    - Get the Read Out Protection status (ROP option byte)
+  *                    - Get the User Boot Code size (UBC option byte)
+  *                    - Get the Protected Code size (PCODE option byte) 
+  *                    
+  *            Note: Option byte programming is very similar to data EEPROM byte
+  *                  programming.          
+  *  
+  *           4. FLASH Interrupts and flag management functions: this group 
+  *              includes all needed functions to:
+  *                    - Enable/Disable the flash interrupt sources
+  *                    - Get flags status
+  *                    - Wait for last flash operation(can be executed from 
+  *                      internal RAM)
+  *                        
+  *           5. Functions to be executed from RAM: this group includes the functions
+  *              that should be executed from RAM and provides description on how 
+  *              to handle this with the different supported toolchains
+  *   
+  *  The table below lists the functions that can be executed from RAM.
+  *  
+  *   +--------------------------------------------------------------------------------|
+  *   |   Functions prototypes      |    RAM execution            |     Comments       |
+  *   ---------------------------------------------------------------------------------|
+  *   |                             | Mandatory in case of block  | Can be executed    |
+  *   | FLASH_WaitForLastOperation  | Operation:                  | from Flash in case |
+  *   |                             | - Block programming         | of byte and word   |
+  *   |                             | - Block erase               | Operations         |
+  *   |--------------------------------------------------------------------------------|
+  *   | FLASH_PowerRunModeConfig    |       Exclusively           | useless from Flash |
+  *   |--------------------------------------------------------------------------------|
+  *   | FLASH_GetPowerStatus        |       Exclusively           | useless from Flash |
+  *   |--------------------------------------------------------------------------------|
+  *   | FLASH_ProgramBlock          |       Exclusively           | useless from Flash |
+  *   |--------------------------------------------------------------------------------|
+  *   | FLASH_EraseBlock            |       Exclusively           | useless from Flash |
+  *   |--------------------------------------------------------------------------------|
+  *  
+  *  To be able to execute functions from RAM several steps have to be followed.
+  *   These steps may differ from one toolchain to another.
+  *   A detailed description is available below within this driver.
+  *   You can also refer to the Flash_DataProgram example provided within the
+  *   STM8L15x_StdPeriph_Lib package.
+  * 
+  *  @endverbatim
+  *                      
+  ******************************************************************************
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ****************************************************************************** 
+  */
+/* Includes ------------------------------------------------------------------*/
+#include "stm8l15x_flash.h"
+
+/** @addtogroup STM8L15x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup FLASH 
+  * @brief FLASH driver modules
+  * @{
+  */
+  
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup FLASH_Private_Define
+  * @{
+  */ 
+#define FLASH_CLEAR_BYTE   ((uint8_t)0x00)
+#define FLASH_SET_BYTE     ((uint8_t)0xFF)
+#define OPERATION_TIMEOUT  ((uint16_t)0xFFFF)
+/**
+  * @}
+  */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+ 
+/** @defgroup FLASH_Private_Functions
+  * @{
+  */ 
+
+/** @defgroup FLASH_Group1 FLASH program and Data EEPROM memories Interface 
+  *                        configuration functions
+  *  @brief   FLASH Interface configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+      FLASH program and Data EEPROM memories interface configuration functions
+ ===============================================================================  
+
+   The FLASH program and Data EEPROM memories interface configuration functions,
+    includes the following functions:
+		
+   - FLASH_ProgramTime_TypeDef FLASH_GetProgrammingTime(void);
+   - void FLASH_SetProgrammingTime(FLASH_ProgramTime_TypeDef FLASH_ProgTime);
+	 - void FLASH_PowerWaitModeConfig(FLASH_Power_TypeDef FLASH_Power);
+
+   These functions don't need the unlock sequence.
+
+@endverbatim
+  * @{
+  */
+	
+/**
+  * @brief  Sets the fixed programming time
+  * @param  FLASH_ProgTime : Indicates the programming time to be fixed
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_ProgramTime_Standard: Standard programming time fixed at 1/2 tprog
+  *            @arg FLASH_ProgramTime_TProg: Programming time fixed at tprog 
+  * @retval None
+  */
+void FLASH_SetProgrammingTime(FLASH_ProgramTime_TypeDef FLASH_ProgTime)
+{
+  /* Check parameter */
+  assert_param(IS_FLASH_PROGRAM_TIME(FLASH_ProgTime));
+
+  FLASH->CR1 &= (uint8_t)(~FLASH_CR1_FIX);
+  FLASH->CR1 |= (uint8_t)FLASH_ProgTime;
+}
+
+/**
+  * @brief  Returns the fixed programming time
+  * @param  None
+  * @retval Fixed programming time value
+  */
+FLASH_ProgramTime_TypeDef FLASH_GetProgrammingTime(void)
+{
+  return((FLASH_ProgramTime_TypeDef)(FLASH->CR1 & FLASH_CR1_FIX));
+}
+
+/**
+  * @brief  Configures the power state for Flash program and data EEPROM during
+  *          wait for interrupt mode
+  * @param  FLASH_Power: The power state for Flash program and data EEPROM during
+  *         wait for interrupt mode
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_Power_IDDQ: Flash program and data EEPROM in IDDQ
+  *            @arg FLASH_Power_On: Flash program and data EEPROM not in IDDQ 
+  * @retval None
+  */
+void FLASH_PowerWaitModeConfig(FLASH_Power_TypeDef FLASH_Power)
+{
+  /* Check parameter */
+  assert_param(IS_FLASH_POWER(FLASH_Power));
+
+  /* Flash program and data EEPROM in IDDQ during wait for interrupt mode*/
+  if (FLASH_Power != FLASH_Power_On)
+  {
+    FLASH->CR1 |= (uint8_t)FLASH_CR1_WAITM;
+  }
+  /* Flash program and data EEPROM not in IDDQ during wait for interrupt mode*/
+  else
+  {
+    FLASH->CR1 &= (uint8_t)(~FLASH_CR1_WAITM);
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Group2 FLASH Memory Programming functions
+ *  @brief   FLASH Memory Programming functions
+ *
+@verbatim   
+ ===============================================================================
+                      FLASH Memory Programming functions
+ ===============================================================================  
+
+   The FLASH Memory Programming functions, includes the following functions:
+    - void FLASH_DeInit(void);
+    - void FLASH_Unlock(FLASH_MemType_TypeDef FLASH_MemType);
+    - void FLASH_Lock(FLASH_MemType_TypeDef FLASH_MemType);
+    - void FLASH_ProgramByte(uint32_t Address, uint8_t Data);
+    - void FLASH_EraseByte(uint32_t Address);
+    - void FLASH_ProgramWord(uint32_t Address, uint32_t Data);
+    - uint8_t FLASH_ReadByte(uint32_t Address);
+   
+   Any operation of erase or program should follow these steps:
+
+   1. Call the FLASH_Unlock(FLASH_MemType) function to enable the memory access
+
+   2. Call the desired function to erase or program data
+
+   3. Call the FLASH_Lock() function to disable the memory access 
+     (it is recommended to protect the FLASH memory against possible unwanted operation)
+
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Deinitializes the FLASH registers to their default reset values.
+  * @param  None
+  * @retval None
+  */
+void FLASH_DeInit(void)
+{
+  FLASH->CR1 = FLASH_CR1_RESET_VALUE;
+  FLASH->CR2 = FLASH_CR2_RESET_VALUE;
+  FLASH->IAPSR = FLASH_IAPSR_RESET_VALUE;
+  (void) FLASH->IAPSR; /* Reading of this register causes the clearing of status flags */
+}
+  
+/**
+  * @brief  Unlocks the program or data EEPROM memory
+  * @param  FLASH_MemType : Memory type to unlock
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_MemType_Program: Program memory
+  *            @arg FLASH_MemType_Data: Data EEPROM memory 
+  * @retval None
+  */
+void FLASH_Unlock(FLASH_MemType_TypeDef FLASH_MemType)
+{
+  /* Check parameter */
+  assert_param(IS_FLASH_MEMORY_TYPE(FLASH_MemType));
+
+  /* Unlock program memory */
+  if (FLASH_MemType == FLASH_MemType_Program)
+  {
+    FLASH->PUKR = FLASH_RASS_KEY1;
+    FLASH->PUKR = FLASH_RASS_KEY2;
+  }
+
+  /* Unlock data memory */
+  if (FLASH_MemType == FLASH_MemType_Data)
+  {
+    FLASH->DUKR = FLASH_RASS_KEY2; /* Warning: keys are reversed on data memory !!! */
+    FLASH->DUKR = FLASH_RASS_KEY1;
+  }
+}
+
+/**
+  * @brief  Locks the program or data EEPROM memory
+  * @param  FLASH_MemType : Memory type
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_MemType_Program: Program memory
+  *            @arg FLASH_MemType_Data: Data EEPROM memory 
+  * @retval None
+  */
+void FLASH_Lock(FLASH_MemType_TypeDef FLASH_MemType)
+{
+  /* Check parameter */
+  assert_param(IS_FLASH_MEMORY_TYPE(FLASH_MemType));
+  /* Lock memory */
+  FLASH->IAPSR &= (uint8_t)FLASH_MemType;
+}
+
+/**
+  * @brief  Programs one byte in program or data EEPROM memory
+  * @param  Address : Address where the byte will be programmed
+  * @param  Data : Value to be programmed
+  * @retval None
+  */
+void FLASH_ProgramByte(uint32_t Address, uint8_t Data)
+{
+  /* Check parameters */
+  assert_param(IS_FLASH_ADDRESS(Address));
+
+  *(PointerAttr uint8_t*) (MemoryAddressCast)Address = Data;
+}
+
+/**
+  * @brief  Erases one byte in the program or data EEPROM memory
+  * @param  Address : Address of the byte to erase
+  * @retval None
+  */
+void FLASH_EraseByte(uint32_t Address)
+{
+  /* Check parameter */
+  assert_param(IS_FLASH_ADDRESS(Address));
+
+  *(PointerAttr uint8_t*) (MemoryAddressCast)Address = FLASH_CLEAR_BYTE; /* Erase byte */
+}
+
+/**
+  * @brief  Programs one word (4 bytes) in program or data EEPROM memory
+  * @param  Address : The address where the data will be programmed
+  * @param  Data : Value to be programmed
+  * @retval None
+  */
+void FLASH_ProgramWord(uint32_t Address, uint32_t Data)
+{
+  /* Check parameters */
+  assert_param(IS_FLASH_ADDRESS(Address));
+  /* Enable Word Write Once */
+  FLASH->CR2 |= FLASH_CR2_WPRG;
+
+  /* Write one byte - from lowest address*/
+  *((PointerAttr uint8_t*)(MemoryAddressCast)Address)       = *((uint8_t*)(&Data));   
+  /* Write one byte*/
+  *(((PointerAttr uint8_t*)(MemoryAddressCast)Address) + 1) = *((uint8_t*)(&Data) + 1);
+  /* Write one byte*/
+  *(((PointerAttr uint8_t*)(MemoryAddressCast)Address) + 2) = *((uint8_t*)(&Data) + 2); 
+  /* Write one byte - from higher address*/
+  *(((PointerAttr uint8_t*)(MemoryAddressCast)Address) + 3) = *((uint8_t*)(&Data) + 3); 
+}
+
+/**
+  * @brief  Reads one byte from flash memory
+  * @param  Address : Address to read
+  * @retval Value of the byte
+  */
+uint8_t FLASH_ReadByte(uint32_t Address)
+{
+  /* Read byte */
+  return(*(PointerAttr uint8_t *) (MemoryAddressCast)Address);
+}
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Group3 Option Bytes Programming functions
+ *  @brief   Option Bytes Programming functions 
+ *
+@verbatim   
+ ===============================================================================
+                        Option Bytes Programming functions
+ ===============================================================================  
+
+   The FLASH_Option Bytes Programming_functions, includes the following functions:
+
+   - void FLASH_ProgramOptionByte(uint16_t Address, uint8_t Data);
+   - void FLASH_EraseOptionByte(uint16_t Address);
+   - FunctionalState FLASH_GetReadOutProtectionStatus(void);
+   - uint16_t FLASH_GetBootSize(void);
+   - uint16_t FLASH_GetCodeSize(void);
+   
+   Any operation of erase or program should follow these steps:
+   
+   1. Call the FLASH_Unlock(FLASH_MemType_Data); function to enable the Flash 
+      option control register access
+   
+   2. Call the desired function to erase or program data
+      - void FLASH_ProgramOptionByte(uint16_t Address, uint8_t Data); => to program
+        the option byte Address with the desired Data value.  
+      - void FLASH_EraseOptionByte(uint16_t Address); => to erase the option byte
+        Address. 			 
+   
+   3. Once all needed option bytes to be programmed are correctly written, call the
+      FLASH_Lock(FLASH_MemType_Data) to disable the memory access ( It is recommended to
+      protect the FLASH memory against possible unwanted operation)
+
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Programs option byte
+  * @param  Address : option byte address to program
+  * @param  Data : Value to write
+  * @retval None
+  */
+void FLASH_ProgramOptionByte(uint16_t Address, uint8_t Data)
+{
+  /* Check parameter */
+  assert_param(IS_OPTION_BYTE_ADDRESS(Address));
+
+  /* Enable write access to option bytes */
+  FLASH->CR2 |= FLASH_CR2_OPT;
+
+  /* Program option byte and his complement */
+  *((PointerAttr uint8_t*)Address) = Data;
+
+  FLASH_WaitForLastOperation(FLASH_MemType_Program);
+
+  /* Disable write access to option bytes */
+  FLASH->CR2 &= (uint8_t)(~FLASH_CR2_OPT);
+}
+
+/**
+  * @brief  Erases option byte
+  * @param  Address : Option byte address to erase
+  * @retval None
+  */
+void FLASH_EraseOptionByte(uint16_t Address)
+{
+  /* Check parameter */
+  assert_param(IS_OPTION_BYTE_ADDRESS(Address));
+
+  /* Enable write access to option bytes */
+  FLASH->CR2 |= FLASH_CR2_OPT;
+
+  /* Erase option byte and his complement */
+  *((PointerAttr uint8_t*)Address) = FLASH_CLEAR_BYTE;
+
+  FLASH_WaitForLastOperation(FLASH_MemType_Program);
+
+  /* Disable write access to option bytes */
+  FLASH->CR2 &= (uint8_t)(~FLASH_CR2_OPT);
+}
+
+/**
+  * @brief  Returns the FLASH Read Out Protection Status.
+  * @param  None
+  * @retval FLASH Read Out Protection Status.
+  *         This parameter can be a ENABLE or DISABLE
+  */
+FunctionalState FLASH_GetReadOutProtectionStatus(void)
+{
+  FunctionalState state = DISABLE;
+
+  if (OPT->ROP == FLASH_READOUTPROTECTION_KEY)
+  {
+    /* The status of the Flash read out protection is enabled*/
+    state =  ENABLE;
+  }
+  else
+  {
+    /* The status of the Flash read out protection is disabled*/
+    state =  DISABLE;
+  }
+
+  return state;
+}
+
+/**
+  * @brief  Returns the Boot memory size in bytes
+  * @param  None
+  * @retval Boot memory size in bytes
+  */
+uint16_t FLASH_GetBootSize(void)
+{
+  uint16_t temp = 0;
+
+  /* Calculates the number of bytes */
+  temp = (uint16_t)((uint16_t)OPT->UBC * (uint16_t)128);
+
+  /* Correction because size upper 8kb doesn't exist */
+  if (OPT->UBC > 0x7F)
+  {
+    temp = 8192;
+  }
+
+  /* Return value */
+  return(temp);
+
+}
+
+/**
+ *
+  * @brief  Returns the Code Area size in bytes
+  * @param  None
+  * @retval Code Area size in bytes
+  */
+uint16_t FLASH_GetCodeSize(void)
+{
+  uint16_t temp = 0;
+
+  /* Calculates the number of bytes */
+  temp = (uint16_t)((uint16_t)OPT->PCODESIZE * (uint16_t)128);
+
+  /* Correction because size upper of 8kb doesn't exist */
+  if (OPT->PCODESIZE > 0x7F)
+  {
+    temp = 8192;
+  }
+
+  /* Return value */
+  return(temp);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Group4 Interrupts and flags management functions
+ *  @brief   Interrupts and flags management functions
+ *
+@verbatim   
+ ===============================================================================
+                  Interrupts and flags management functions
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Enables or Disables the Flash interrupt mode
+  * @param  NewState : The new state of the flash interrupt mode
+    *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void FLASH_ITConfig(FunctionalState NewState)
+{
+
+  /* Check parameter */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enables the interrupt sources */
+    FLASH->CR1 |= FLASH_CR1_IE;
+  }
+  else
+  {
+    /* Disables the interrupt sources */
+    FLASH->CR1 &= (uint8_t)(~FLASH_CR1_IE);
+  }
+}
+
+/**
+  * @brief  Checks whether the specified FLASH flag is set or not.
+  * @param  FLASH_FLAG : specifies the Flash Flag to check.
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_FLAG_HVOFF: End of high voltage
+  *            @arg FLASH_FLAG_DUL: Data EEPROM unlocked
+  *            @arg FLASH_FLAG_EOP: End of programming (write or erase operation)
+  *            @arg FLASH_FLAG_PUL: Flash Program memory unlocked
+  *            @arg FLASH_FLAG_WR_PG_DIS: Write attempted to protected page       
+  * @retval Indicates the state of the Flash_FLAG.
+  *         This parameter can be SET or RESET
+  */
+FlagStatus FLASH_GetFlagStatus(FLASH_FLAG_TypeDef FLASH_FLAG)
+{
+  FlagStatus status = RESET;
+  assert_param(IS_FLASH_FLAGS(FLASH_FLAG));
+
+  /* Check the status of the specified flash flag*/
+  if ((FLASH->IAPSR  & (uint8_t)FLASH_FLAG) != (uint8_t)RESET)
+  {
+    status = SET; /* Flash_FLAG is set*/
+  }
+  else
+  {
+    status = RESET; /* Flash_FLAG is reset*/
+  }
+
+  /* Return the Flash_FLAG status*/
+  return status;
+}
+
+/**
+  * @}
+  */ 
+  
+/** @defgroup FLASH_Group5 Functions to be executed from RAM
+ *  @brief  Functions to be executed from RAM
+ *
+@verbatim   
+ ===============================================================================
+                         Functions to be executed from RAM
+ ===============================================================================  
+ 
+ All the functions defined below must be executed from RAM exclusively, except
+ for the FLASH_WaitForLastOperation function which can be executed from Flash.
+
+ Steps of the execution from RAM differs from one toolchain to another:
+ - For Cosmic Compiler:
+    1- Define a segment FLASH_CODE by the mean of " #pragma section (FLASH_CODE)".
+    This segment is defined in the stm8l15x_flash.c file.
+  2- Uncomment the "#define RAM_EXECUTION  (1)" line in the stm8l15x.h file,
+    or define it in Cosmic compiler preprocessor to enable the FLASH_CODE segment
+   definition.
+  3- In STVD Select Project\Settings\Linker\Category "input" and in the RAM section
+    add the FLASH_CODE segment with "-ic" options.
+  4- In main.c file call the _fctcpy() function with first segment character as 
+    parameter "_fctcpy('F');" to load the declared moveable code segment
+    (FLASH_CODE) in RAM before execution.
+  5- By default the _fctcpy function is packaged in the Cosmic machine library,
+    so the function prototype "int _fctcopy(char name);" must be added in main.c
+    file.
+
+  - For Raisonance Compiler
+   1- Use the inram keyword in the function declaration to specify that it can be
+    executed from RAM.
+    This is done within the stm8l15x_flash.c file, and it's conditioned by 
+    RAM_EXECUTION definition.
+   2- Uncomment the "#define RAM_EXECUTION  (1)" line in the stm8l15x.h file, or 
+   define it in Raisonance compiler preprocessor to enable the access for the 
+   inram functions.
+   3- An inram function code is copied from Flash to RAM by the C startup code. 
+   In some applications, the RAM area where the code was initially stored may be
+   erased or corrupted, so it may be desirable to perform the copy again. 
+   Depending on the application memory model, the memcpy() or fmemcpy() functions
+   should be used to perform the copy.
+      • In case your project uses the SMALL memory model (code smaller than 64K),
+       memcpy()function is recommended to perform the copy
+      • In case your project uses the LARGE memory model, functions can be 
+      everywhere in the 24-bits address space (not limited to the first 64KB of
+      code), In this case, the use of memcpy() function will not be appropriate,
+      you need to use the specific fmemcpy() function (which copies objects with
+      24-bit addresses).
+      - The linker automatically defines 2 symbols for each inram function:
+           • __address__functionname is a symbol that holds the Flash address 
+           where the given function code is stored.
+           • __size__functionname is a symbol that holds the function size in bytes.
+     And we already have the function address (which is itself a pointer)
+  4- In main.c file these two steps should be performed for each inram function:
+     • Import the "__address__functionname" and "__size__functionname" symbols
+       as global variables:
+         extern int __address__functionname; // Symbol holding the flash address
+         extern int __size__functionname;    // Symbol holding the function size
+     • In case of SMALL memory model use, Call the memcpy() function to copy the
+      inram function to the RAM destination address:
+                memcpy(functionname, // RAM destination address
+                      (void*)&__address__functionname, // Flash source address
+                      (int)&__size__functionname); // Code size of the function
+     • In case of LARGE memory model use, call the fmemcpy() function to copy 
+     the inram function to the RAM destination address:
+                 memcpy(functionname, // RAM destination address
+                      (void @far*)&__address__functionname, // Flash source address
+                      (int)&__size__functionname); // Code size of the function
+
+ - For IAR Compiler:
+    1- Use the __ramfunc keyword in the function declaration to specify that it 
+    can be executed from RAM.
+    This is done within the stm8l15x_flash.c file, and it's conditioned by 
+    RAM_EXECUTION definition.
+    2- Uncomment the "#define RAM_EXECUTION  (1)" line in the stm8l15x.h file, or 
+   define it in IAR compiler preprocessor to enable the access for the 
+   __ramfunc functions.
+ 
+ The Flash_DataProgram example provided within the STM8L15x_StdPeriph_Lib package
+ details all the steps described above.
+
+@endverbatim
+  * @{
+  */
+   
+/**
+  * @brief
+  *******************************************************************************
+  *                         Execution from RAM enable
+  *******************************************************************************
+  *
+  * To enable execution from RAM you can either uncomment the following define 
+  * in the stm8l15x.h file or define it in your toolchain compiler preprocessor
+  * - #define RAM_EXECUTION  (1) 
+  */
+
+#if defined (_COSMIC_) && defined (RAM_EXECUTION)
+ #pragma section (FLASH_CODE)
+#endif  /* _COSMIC_ && RAM_EXECUTION */
+
+/**
+  * @brief  Configures the power state for Flash program and data EEPROM during
+  *         run, low power run and low power wait modes
+  * @note   This function must be called and executed from RAM.
+  * @param  FLASH_Power: power state of the Flash program and data EEPROM
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_Power_IDDQ: Flash program and data EEPROM in IDDQ
+  *            @arg FLASH_Power_On: Flash program and data EEPROM not in IDDQ 
+  * @retval None
+  */
+IN_RAM(void FLASH_PowerRunModeConfig(FLASH_Power_TypeDef FLASH_Power))
+{
+  /* Check parameter */
+  assert_param(IS_FLASH_POWER(FLASH_Power));
+
+  if (FLASH_Power != FLASH_Power_On)
+  {
+  FLASH->CR1 |= (uint8_t)FLASH_CR1_EEPM;
+  }
+  else
+  {
+    FLASH->CR1 &= (uint8_t)(~FLASH_CR1_EEPM);
+  }
+}
+
+/**
+  * @brief  Checks the power status for Flash program and data EEPROM
+  * @note   This function should be called and executed from RAM.
+  * @param  None
+  * @retval Flash program and data EEPROM power status
+  *         The returned value can be one of the following:
+  *         - FLASH_PowerStatus_IDDQDuringWaitMode: IDDQ during Wait mode
+  *         - FLASH_PowerStatus_IDDQDuringRunMode: IDDQ during Run mode
+  *         - FLASH_PowerStatus_IDDQDuringWaitAndRunModes: IDDQ during Wait/Run mode
+  *         - FLASH_PowerStatus_On: Powered on during Wait and Run modes
+  */
+IN_RAM(FLASH_PowerStatus_TypeDef FLASH_GetPowerStatus(void))
+{
+  return((FLASH_PowerStatus_TypeDef)(FLASH->CR1 & (uint8_t)0x0C));
+}
+
+/**
+  * @brief  Programs a memory block
+  * @note   This function should be called and executed from RAM.
+  * @param  FLASH_MemType : The type of memory to program
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_MemType_Program: Program memory
+  *            @arg FLASH_MemType_Data: Data EEPROM memory 
+  * @param  BlockNum : The block number
+  * @param  FLASH_ProgMode : The programming mode.
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_ProgramMode_Standard: Standard programming mode
+  *            @arg FLASH_ProgramMode_Fast: Fast programming mode
+  * @param  Buffer : Pointer to buffer containing source data.
+  * @retval None.
+  */
+IN_RAM(void FLASH_ProgramBlock(uint16_t BlockNum, FLASH_MemType_TypeDef FLASH_MemType,
+                        FLASH_ProgramMode_TypeDef FLASH_ProgMode, uint8_t *Buffer))
+{
+  uint16_t Count = 0;
+  uint32_t startaddress = 0;
+
+  /* Check parameters */
+  assert_param(IS_FLASH_MEMORY_TYPE(FLASH_MemType));
+  assert_param(IS_FLASH_PROGRAM_MODE(FLASH_ProgMode));
+  if (FLASH_MemType == FLASH_MemType_Program)
+  {
+  assert_param(IS_FLASH_PROGRAM_BLOCK_NUMBER(BlockNum));
+    startaddress = FLASH_PROGRAM_START_PHYSICAL_ADDRESS;
+  }
+  else
+  {
+    assert_param(IS_FLASH_DATA_EEPROM_BLOCK_NUMBER(BlockNum));
+    startaddress = FLASH_DATA_EEPROM_START_PHYSICAL_ADDRESS;
+  }
+
+  /* Point to the first block address */
+  startaddress = startaddress + ((uint32_t)BlockNum * FLASH_BLOCK_SIZE);
+
+  /* Selection of Standard or Fast programming mode */
+  if (FLASH_ProgMode == FLASH_ProgramMode_Standard)
+  {
+  /* Standard programming mode */
+  FLASH->CR2 |= FLASH_CR2_PRG;
+  }
+  else
+  {
+  /* Fast programming mode */
+  FLASH->CR2 |= FLASH_CR2_FPRG;
+  }
+
+  /* Copy data bytes from RAM to FLASH memory */
+  for (Count = 0; Count < FLASH_BLOCK_SIZE; Count++)
+  {
+    *((PointerAttr uint8_t*) (MemoryAddressCast)startaddress + Count) = ((uint8_t)(Buffer[Count]));
+  }
+}
+
+/**
+  * @brief  Erases a block in the program or data memory.
+  * @note   This function should be called and executed from RAM.
+  * @param  BlockNum : Indicates the block number to erase
+  * @param  FLASH_MemType :  The type of memory to erase
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_MemType_Program: Program memory
+  *            @arg FLASH_MemType_Data: Data EEPROM memory 
+  * @retval None.
+  */
+IN_RAM(void FLASH_EraseBlock(uint16_t BlockNum, FLASH_MemType_TypeDef FLASH_MemType))
+{
+  uint32_t startaddress = 0;
+#if defined (STM8L15X_MD) || defined (STM8L15X_MDP) || defined (STM8L15X_LD) || \
+defined (STM8L05X_LD_VL) || defined (STM8L05X_MD_VL) || defined (STM8AL31_L_MD)
+  uint32_t PointerAttr  *pwFlash;
+  
+#elif defined (STM8L15X_HD) || defined (STM8L05X_HD_VL)
+  uint8_t PointerAttr  *pwFlash;
+#endif
+
+  /* Check parameters */
+  assert_param(IS_FLASH_MEMORY_TYPE(FLASH_MemType));
+  if (FLASH_MemType == FLASH_MemType_Program)
+  {
+  assert_param(IS_FLASH_PROGRAM_BLOCK_NUMBER(BlockNum));
+    startaddress = FLASH_PROGRAM_START_PHYSICAL_ADDRESS;
+  }
+  else
+  {
+    assert_param(IS_FLASH_DATA_EEPROM_BLOCK_NUMBER(BlockNum));
+    startaddress = FLASH_DATA_EEPROM_START_PHYSICAL_ADDRESS;
+  }
+
+  /* Point to the first block address */
+#if defined (STM8L15X_MD) || defined (STM8L15X_MDP)|| defined (STM8L15X_LD) || \
+defined (STM8L05X_LD_VL) || defined (STM8L05X_MD_VL) || defined (STM8AL31_L_MD)
+  pwFlash = (PointerAttr uint32_t *)(uint16_t)(startaddress + ((uint32_t)BlockNum * FLASH_BLOCK_SIZE));
+  
+#elif defined (STM8L15X_HD) || defined (STM8L05X_HD_VL)
+  pwFlash = (PointerAttr uint8_t *)(uint32_t)(startaddress + ((uint32_t)BlockNum * FLASH_BLOCK_SIZE));
+#endif
+
+  /* Enable erase block mode */
+  FLASH->CR2 |= FLASH_CR2_ERASE;
+
+#if defined (STM8L15X_MD) || defined (STM8L15X_MDP) || defined (STM8L15X_LD) || \
+defined (STM8L05X_LD_VL) || defined (STM8L05X_MD_VL) || defined (STM8AL31_L_MD)
+  *pwFlash = (uint32_t)0;  
+
+#elif defined (STM8L15X_HD) || defined (STM8L05X_HD_VL)
+  *pwFlash = (uint8_t)0;
+  *(pwFlash + 1) = (uint8_t)0;
+  *(pwFlash + 2) = (uint8_t)0;
+  *(pwFlash + 3) = (uint8_t)0;
+#endif
+}
+
+/**
+  * @brief  Waits for a Flash operation to complete.
+  * @note   The call and execution of this function must be done from RAM in case
+  *         of Block operation, otherwise it can be executed from Flash
+  * @param  FLASH_MemType : Memory type
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_MemType_Program: Program memory
+  *            @arg FLASH_MemType_Data: Data EEPROM memory 
+  * @retval FLASH status
+  */
+IN_RAM(FLASH_Status_TypeDef FLASH_WaitForLastOperation(FLASH_MemType_TypeDef FLASH_MemType))
+{
+  uint32_t timeout = OPERATION_TIMEOUT;
+  uint8_t flagstatus = 0x00;
+  /* Wait until operation completion or write protected page occurred */
+  if (FLASH_MemType == FLASH_MemType_Program)
+  {
+  while ((flagstatus == 0x00) && (timeout != 0x00))
+    {
+      flagstatus = (uint8_t)(FLASH->IAPSR & (uint8_t)(FLASH_IAPSR_EOP |
+                             FLASH_IAPSR_WR_PG_DIS));
+      timeout--;
+    }
+  }
+  else
+  {
+    while ((flagstatus == 0x00) && (timeout != 0x00))
+    {
+      flagstatus = (uint8_t)(FLASH->IAPSR & (uint8_t)(FLASH_IAPSR_HVOFF |
+                             FLASH_IAPSR_WR_PG_DIS));
+      timeout--;
+    }
+  }
+  if (timeout == 0x00 )
+  {
+  flagstatus = FLASH_Status_TimeOut;
+  }
+
+  return((FLASH_Status_TypeDef)flagstatus);
+}
+
+#if defined (_COSMIC_) && defined (RAM_EXECUTION)
+ /* End of FLASH_CODE section */
+ #pragma section ()
+#endif /* _COSMIC_ && RAM_EXECUTION */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+   
+  /**
+  * @}
+  */ 
+  
+  /**
+  * @}
+  */ 
+  
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
\ No newline at end of file
diff --git a/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_gpio.c b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_gpio.c
new file mode 100755
index 0000000..75509b9
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_gpio.c
@@ -0,0 +1,407 @@
+/**
+  ******************************************************************************
+  * @file    stm8l15x_gpio.c
+  * @author  MCD Application Team
+  * @version V1.6.0
+  * @date    28-June-2013
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the GPIO peripheral:
+  *           - Initialization and Configuration
+  *           - GPIO Read and Write
+  *
+  *          ===================================================================
+  *                                 How to use this driver
+  *          ===================================================================       
+  *           1. Configure the GPIO pin(s) using GPIO_Init()
+  *              Two main configuration are available for each pin:
+  *                - Input: Floating 
+  *                         Pull-up.
+  *                  In Input mode, external interrupt can be enabled or disabled
+  *                - Output: Push-Pull
+  *                          Open Drain.
+  *                  In output mode, the GPIO pin speed is configurable: 
+  *                  Slow (2 MHz) or Fast (10MHz).
+  *  
+  *           2. To get the level of a pin configured in input mode use GPIO_ReadInputDataBit()
+  * 
+  *           3. To set/reset GPIO pins sharing the same GPIO port use
+  *              GPIO_SetBits() / GPIO_ResetBits()
+  *
+  *           4. To enable external interrupt, the GPIO pin must be configured
+  *              in input mode with interrupt enabled. Interrupt sensitivity
+  *              (rising, falling...) is configurable using 
+  *              EXTI_SetPinSensitivity() in the EXTI peripheral driver "stm8l15x_exti.c"
+  *  
+  ******************************************************************************
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ****************************************************************************** 
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm8l15x_gpio.h"
+
+/** @addtogroup STM8L15x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup CLK 
+  * @brief CLK driver modules
+  * @{
+  */ 
+  
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup GPIO_Private_Functions
+  * @{
+  */ 
+
+
+/** @defgroup GPIO_Group1 Initialization and Configuration
+ *  @brief   Initialization and Configuration
+ *
+@verbatim   
+ ===============================================================================
+                        Initialization and Configuration
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the GPIOx peripheral registers to their default reset values.
+  * @param  GPIOx: Select the GPIO peripheral number (x = A to I).
+  * @retval None
+  */
+void GPIO_DeInit(GPIO_TypeDef* GPIOx)
+{
+  GPIOx->CR2 = GPIO_CR2_RESET_VALUE; /* Reset Control Register 2 */
+  GPIOx->ODR = GPIO_ODR_RESET_VALUE; /* Reset Output Data Register */
+  GPIOx->DDR = GPIO_DDR_RESET_VALUE; /* Reset Data Direction Register */
+  GPIOx->CR1 = GPIO_CR1_RESET_VALUE; /* Reset Control Register 1 */
+}
+
+/**
+  * @brief  Initializes the GPIOx according to the specified parameters.
+  * @param  GPIOx : Select the GPIO peripheral number (x = A to I).
+  * @param  GPIO_Pin : This parameter contains the pin number
+  *           This parameter can be one of the following values:
+  *            @arg GPIO_Pin_0: Pin 0
+  *            @arg GPIO_Pin_1: Pin 1
+  *            @arg GPIO_Pin_2: Pin 2
+  *            @arg GPIO_Pin_3: Pin 3
+  *            @arg GPIO_Pin_4: Pin 4
+  *            @arg GPIO_Pin_5: Pin 5
+  *            @arg GPIO_Pin_6: Pin 6
+  *            @arg GPIO_Pin_7: Pin 7              
+  * @param  GPIO_Mode : This parameter can be a value of the
+  *           This parameter can be one of the following values:
+  *            @arg GPIO_Mode_In_FL_No_IT: Input floating, no external interrupt
+  *            @arg GPIO_Mode_In_PU_No_IT: Input pull-up, no external interrupt
+  *            @arg GPIO_Mode_In_FL_IT: Input pull-up, external interrupt
+  *            @arg GPIO_Mode_Out_OD_Low_Fast: Output open-drain, low level, 10MHz
+  *            @arg GPIO_Mode_Out_PP_Low_Fast: Output push-pull, low level, 10MHz
+  *            @arg GPIO_Mode_Out_OD_Low_Slow: Output open-drain, low level, 2MHz
+  *            @arg GPIO_Mode_Out_PP_Low_Slow: Output push-pull, low level, 2MHz
+  *            @arg GPIO_Mode_Out_OD_HiZ_Fast: Output open-drain, high-impedance level, 10MHz
+  *            @arg GPIO_Mode_Out_PP_High_Fast: Output push-pull, high level, 10MHz
+  *            @arg GPIO_Mode_Out_OD_HiZ_Slow: Output open-drain, high-impedance level, 2MHz
+  *            @arg GPIO_Mode_Out_PP_High_Slow: Output push-pull, high level, 2MHz
+  * @retval None
+  */
+
+void GPIO_Init(GPIO_TypeDef* GPIOx, uint8_t GPIO_Pin, GPIO_Mode_TypeDef GPIO_Mode)
+{
+  /*----------------------*/
+  /* Check the parameters */
+  /*----------------------*/
+
+  assert_param(IS_GPIO_MODE(GPIO_Mode));
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+  /* Reset corresponding bit to GPIO_Pin in CR2 register */
+  GPIOx->CR2 &= (uint8_t)(~(GPIO_Pin));
+
+  /*-----------------------------*/
+  /* Input/Output mode selection */
+  /*-----------------------------*/
+
+  if ((((uint8_t)(GPIO_Mode)) & (uint8_t)0x80) != (uint8_t)0x00) /* Output mode */
+  {
+    if ((((uint8_t)(GPIO_Mode)) & (uint8_t)0x10) != (uint8_t)0x00) /* High level */
+    {
+      GPIOx->ODR |= GPIO_Pin;
+    } else /* Low level */
+    {
+      GPIOx->ODR &= (uint8_t)(~(GPIO_Pin));
+    }
+    /* Set Output mode */
+    GPIOx->DDR |= GPIO_Pin;
+  } else /* Input mode */
+  {
+    /* Set Input mode */
+    GPIOx->DDR &= (uint8_t)(~(GPIO_Pin));
+  }
+
+  /*------------------------------------------------------------------------*/
+  /* Pull-Up/Float (Input) or Push-Pull/Open-Drain (Output) modes selection */
+  /*------------------------------------------------------------------------*/
+
+  if ((((uint8_t)(GPIO_Mode)) & (uint8_t)0x40) != (uint8_t)0x00) /* Pull-Up or Push-Pull */
+  {
+    GPIOx->CR1 |= GPIO_Pin;
+  } else /* Float or Open-Drain */
+  {
+    GPIOx->CR1 &= (uint8_t)(~(GPIO_Pin));
+  }
+
+  /*-----------------------------------------------------*/
+  /* Interrupt (Input) or Slope (Output) modes selection */
+  /*-----------------------------------------------------*/
+
+  if ((((uint8_t)(GPIO_Mode)) & (uint8_t)0x20) != (uint8_t)0x00) /* Interrupt or Slow slope */
+  {
+    GPIOx->CR2 |= GPIO_Pin;
+  } else /* No external interrupt or No slope control */
+  {
+    GPIOx->CR2 &= (uint8_t)(~(GPIO_Pin));
+  }
+
+}
+
+/**
+  * @brief  Configures the external pull-up on GPIOx pins.
+  * @param  GPIOx : Select the GPIO peripheral number (x = A to I).
+  * @param  GPIO_Pin : Specifies the pin number
+  *           This parameter can be one of the following values:
+  *            @arg GPIO_Pin_0: Pin 0
+  *            @arg GPIO_Pin_1: Pin 1
+  *            @arg GPIO_Pin_2: Pin 2
+  *            @arg GPIO_Pin_3: Pin 3
+  *            @arg GPIO_Pin_4: Pin 4
+  *            @arg GPIO_Pin_5: Pin 5
+  *            @arg GPIO_Pin_6: Pin 6
+  *            @arg GPIO_Pin_7: Pin 7     
+  * @param  NewState : The new state of the pull up pin.
+  *           Can be ENABLE or DISABLE  
+  * @retval None
+  */
+void GPIO_ExternalPullUpConfig(GPIO_TypeDef* GPIOx, uint8_t GPIO_Pin, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE) /* External Pull-Up Set*/
+  {
+    GPIOx->CR1 |= GPIO_Pin;
+  } else /* External Pull-Up Reset*/
+  {
+    GPIOx->CR1 &= (uint8_t)(~(GPIO_Pin));
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Group2 GPIO Read and Write
+ *  @brief   GPIO Read and Write
+ *
+@verbatim   
+ ===============================================================================
+                              GPIO Read and Write
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Writes data to the specified GPIO data port.
+  * @note   The port must be configured in output mode.
+  * @param  GPIOx : Select the GPIO peripheral number (x = A to I).
+  * @param  GPIO_PortVal : Specifies the value to be written to the port output
+  *         data register.
+  * @retval None
+  */
+void GPIO_Write(GPIO_TypeDef* GPIOx, uint8_t GPIO_PortVal)
+{
+  GPIOx->ODR = GPIO_PortVal;
+}
+
+/**
+  * @brief  Sets or clears the selected data port bit.
+  * @param  GPIOx : Select the GPIO peripheral number (x = A to I).
+  * @param  GPIO_Pin: Specifies the port bit to be written.
+  *           This parameter can be one of the following values:
+  *            @arg GPIO_Pin_0: Pin 0
+  *            @arg GPIO_Pin_1: Pin 1
+  *            @arg GPIO_Pin_2: Pin 2
+  *            @arg GPIO_Pin_3: Pin 3
+  *            @arg GPIO_Pin_4: Pin 4
+  *            @arg GPIO_Pin_5: Pin 5
+  *            @arg GPIO_Pin_6: Pin 6
+  *            @arg GPIO_Pin_7: Pin 7   
+  * @param  GPIO_BitVal: specifies the desired status to be written.
+  *         This parameter can be SET or RESET
+  * @retval None
+  */
+void GPIO_WriteBit(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef GPIO_Pin, BitAction GPIO_BitVal)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+  assert_param(IS_STATE_VALUE(GPIO_BitVal));
+
+  if (GPIO_BitVal != RESET)
+  {
+    GPIOx->ODR |= GPIO_Pin;
+
+  }
+  else
+  {
+    GPIOx->ODR &= (uint8_t)(~GPIO_Pin);
+  }
+}
+
+/**
+  * @brief  Writes high level to the specified GPIO pins.
+  * @note   The port must be configured in output mode.
+  * @param  GPIOx : Select the GPIO peripheral number (x = A to I).
+  * @param  GPIO_Pin : Specifies the pins to be turned high.
+  *           This parameter can be one of the following values:
+  *            @arg GPIO_Pin_0: Pin 0
+  *            @arg GPIO_Pin_1: Pin 1
+  *            @arg GPIO_Pin_2: Pin 2
+  *            @arg GPIO_Pin_3: Pin 3
+  *            @arg GPIO_Pin_4: Pin 4
+  *            @arg GPIO_Pin_5: Pin 5
+  *            @arg GPIO_Pin_6: Pin 6
+  *            @arg GPIO_Pin_7: Pin 7   
+  * @retval None
+  */
+void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint8_t GPIO_Pin)
+{
+  GPIOx->ODR |= GPIO_Pin;
+}
+
+/**
+  * @brief  Writes low level to the specified GPIO pins.
+  * @note   The port must be configured in output mode.
+  * @param  GPIOx : Select the GPIO peripheral number (x = A to I).
+  * @param  GPIO_Pin : Specifies the pins to be turned low
+  *           This parameter can be one of the following values:
+  *            @arg GPIO_Pin_0: Pin 0
+  *            @arg GPIO_Pin_1: Pin 1
+  *            @arg GPIO_Pin_2: Pin 2
+  *            @arg GPIO_Pin_3: Pin 3
+  *            @arg GPIO_Pin_4: Pin 4
+  *            @arg GPIO_Pin_5: Pin 5
+  *            @arg GPIO_Pin_6: Pin 6
+  *            @arg GPIO_Pin_7: Pin 7 
+  * @retval None
+  */
+void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint8_t GPIO_Pin)
+{
+  GPIOx->ODR &= (uint8_t)(~GPIO_Pin);
+}
+
+/**
+  * @brief  Toggles the specified GPIO pins.
+  * @note   The port must be configured in output mode.
+  * @param  GPIOx : Select the GPIO peripheral number (x = A to I).
+  * @param  GPIO_Pin : Specifies the pins to be toggled.
+  * @retval None
+  */
+void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint8_t GPIO_Pin)
+{
+  GPIOx->ODR ^= GPIO_Pin;
+}
+
+/**
+  * @brief  Reads the specified GPIO input data port.
+  * @note   The port must be configured in input mode.
+  * @param  GPIOx : Select the GPIO peripheral number (x = A to I).
+  * @retval The GPIOx input data port value.
+  */
+uint8_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)
+{
+  return ((uint8_t)GPIOx->IDR);
+}
+
+/**
+  * @brief  Reads the specified GPIO output data port.
+  * @note   The port must be configured in input mode.
+  * @param  GPIOx : Select the GPIO peripheral number (x = A to I).
+  * @retval The GPIOx  output data port value.
+  */
+uint8_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)
+{
+  return ((uint8_t)GPIOx->ODR);
+}
+
+/**
+  * @brief  Reads the specified GPIO input data pin.
+  * @param  GPIOx : Select the GPIO peripheral number (x = A to I).
+  * @param  GPIO_Pin : Specifies the pin number.
+  *           This parameter can be one of the following values:
+  *            @arg GPIO_Pin_0: Pin 0
+  *            @arg GPIO_Pin_1: Pin 1
+  *            @arg GPIO_Pin_2: Pin 2
+  *            @arg GPIO_Pin_3: Pin 3
+  *            @arg GPIO_Pin_4: Pin 4
+  *            @arg GPIO_Pin_5: Pin 5
+  *            @arg GPIO_Pin_6: Pin 6
+  *            @arg GPIO_Pin_7: Pin 7 
+  * @retval BitStatus : GPIO input pin status.
+  */
+BitStatus GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef GPIO_Pin)
+{
+  return ((BitStatus)(GPIOx->IDR & (uint8_t)GPIO_Pin));
+}
+
+/**
+  * @brief  Reads the specified GPIO Output data pin.
+  * @param  GPIOx : Select the GPIO peripheral number (x = A to I).
+  * @param  GPIO_Pin : Specifies the pin number
+  * @retval BitStatus : GPIO output pin status.
+  */
+BitStatus GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef GPIO_Pin)
+{
+  return ((BitStatus)(GPIOx->ODR & (uint8_t)GPIO_Pin));
+}
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+  
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_i2c.c b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_i2c.c
new file mode 100755
index 0000000..8e5e319
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_i2c.c
@@ -0,0 +1,1366 @@
+/**
+  ******************************************************************************
+  * @file    stm8l15x_i2c.c
+  * @author  MCD Application Team
+  * @version V1.6.0
+  * @date    28-June-2013
+  * @brief   This file provides firmware functions to manage the following
+  *          functionalities of the Inter-integrated circuit (I2C)
+  *           - Initialization and Configuration
+  *           - Data transfers
+  *           - PEC management
+  *           - DMA transfers management
+  *           - Interrupts, events and flags management
+  *
+  *  @verbatim
+  *
+  *          ===================================================================
+  *                                 How to use this driver
+  *          ===================================================================
+  *          1. Enable peripheral clock using CLK_PeripheralClockConfig(CLK_Peripheral_I2Cx,
+  *             ENABLE) function (Refer to the product datasheet for the available I2C
+  *           	peripherals)
+  *
+  *
+  *          2. Program the Mode, duty cycle , Own address, Ack, Speed and Acknowledged
+  *             Address using the I2C_Init() function.
+  *
+  *          3. Optionally you can enable/configure the following parameters without
+  *             re-initialization (i.e there is no need to call again I2C_Init() function):
+  *              - Enable the acknowledge feature using I2C_AcknowledgeConfig() function
+  *              - Enable the dual addressing mode using I2C_DualAddressCmd() function
+  *              - Enable the general call using the I2C_GeneralCallCmd() function
+  *              - Enable the clock stretching using I2C_StretchClockCmd() function
+  *              - Enable the fast mode duty cycle using the I2C_FastModeDutyCycleConfig()
+  *                function
+  *              - Enable the PEC Calculation using I2C_CalculatePEC() function
+  *              - For SMBus Mode:
+  *                   - Enable the Address Resolution Protocol (ARP) using I2C_ARPCmd() function
+  *                   - Configure the SMBusAlert pin using I2C_SMBusAlertConfig() function
+  *
+  *          4. Enable the interrupt using the function I2C_ITConfig() if you need
+  *             to use interrupt mode.
+  *
+  *          5. When using the DMA mode
+  *                   - Configure the DMA using DMA_Init() function
+  *                   - Active the needed channel Request using I2C_DMACmd() or
+  *                     I2C_DMALastTransferCmd() function
+  *              Note: When using DMA mode, I2C interrupts may be used at the same time to
+  *                    control the communication flow (Start/Stop/Ack... events and errors).
+  *
+  *          6. Enable the I2C using the I2C_Cmd() function.
+  *
+  *          7. Enable the DMA using the DMA_Cmd() function when using DMA mode in the
+  *             transfers.
+  *
+  *         Note: The external Pull-up resistors must be connected on SDA and SCL.
+  *
+  *  @endverbatim
+  *
+  ******************************************************************************
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm8l15x_i2c.h"
+#include "stm8l15x_clk.h"
+
+/** @addtogroup STM8L15x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup I2C
+  * @brief I2C driver modules
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup I2C_Private_Define
+  * @{
+  */
+
+/* I2C register mask */
+#define REGISTER_Mask               ((uint16_t)0x3000)
+#define REGISTER_SR1_Index          ((uint16_t)0x0100)
+#define REGISTER_SR2_Index          ((uint16_t)0x0200)
+/* I2C Interrupt Enable mask */
+#define ITEN_Mask                   ((uint16_t)0x0700)
+/* I2C FLAG mask */
+#define FLAG_Mask                   ((uint16_t)0x00FF)
+/* I2C ADD0 mask */
+#define OAR1_ADD0_Set               ((uint8_t)0x01)
+#define OAR1_ADD0_Reset             ((uint8_t)0xFE)
+
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup I2C_Private_Functions
+  * @{
+  */
+
+/** @defgroup I2C_Group1 Initialization and Configuration functions
+ *  @brief   Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+                   Initialization and Configuration functions
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the I2C peripheral registers to their default reset values.
+  * @param  I2Cx: where x can be 1 to select the specified I2C peripheral.
+  * @retval None
+  */
+void I2C_DeInit(I2C_TypeDef* I2Cx)
+{
+  I2Cx->CR1 = I2C_CR1_RESET_VALUE;
+  I2Cx->CR2 = I2C_CR2_RESET_VALUE;
+  I2Cx->FREQR = I2C_FREQR_RESET_VALUE;
+  I2Cx->OARL = I2C_OARL_RESET_VALUE;
+  I2Cx->OARH = I2C_OARH_RESET_VALUE;
+  I2Cx->OAR2 = I2C_OAR2_RESET_VALUE;
+  I2Cx->ITR = I2C_ITR_RESET_VALUE;
+  I2Cx->CCRL = I2C_CCRL_RESET_VALUE;
+  I2Cx->CCRH = I2C_CCRH_RESET_VALUE;
+  I2Cx->TRISER = I2C_TRISER_RESET_VALUE;
+}
+
+/**
+  * @brief  Initializes the I2C according to the specified parameters in standard
+  *         or fast mode.
+  * @param  I2Cx: where x can be 1 to select the specified I2C peripheral.
+  * @param  OutputClockFrequency: Specifies the output clock frequency in Hz.
+  * @param  OwnAddress: Specifies the own address.
+  * @param  I2C_Mode: Specifies the addressing mode to apply.
+  *          This parameter can be one of the following values:
+  *            @arg I2C_Mode_I2C: I2C mode
+  *            @arg I2C_Mode_SMBusDevice: SMBus Device mode
+  *            @arg I2C_Mode_SMBusHost: SMBus Host mode
+  * @param  I2C_DutyCycle: Specifies the duty cycle to apply in fast mode.
+  *          This parameter can be one of the following values:
+  *            @arg I2C_DutyCycle_2: I2C fast mode Tlow/Thigh = 2
+  *            @arg I2C_DutyCycle_16_9: I2C fast mode Tlow/Thigh = 16/9
+  * @note   The I2C_DutyCycle parameter doesn't have impact when the OutputClockFrequency
+  *         is lower than 100KHz.
+  * @param  I2C_Ack: Specifies the acknowledge mode to apply.
+  *          This parameter can be one of the following values:
+  *            @arg I2C_Ack_Disable: No acknowledge
+  *            @arg I2C_Ack_Enable: Acknowledge Enabled
+  * @param  I2C_AcknowledgedAddress: Specifies the acknowledge address to apply.
+  *          This parameter can be one of the following values:
+  *            @arg I2C_AcknowledgedAddress_7bit: 7-bit slave address
+  *            @arg I2C_AcknowledgedAddress_10bit: 10-bit slave address
+  * @note   To use the I2C at 400 KHz (in fast mode), the PCLK frequency
+  *         (I2C peripheral input clock) must be a multiple of 10 MHz.
+  * @retval None
+  */
+void I2C_Init(I2C_TypeDef* I2Cx, uint32_t OutputClockFrequency, uint16_t OwnAddress,
+              I2C_Mode_TypeDef I2C_Mode, I2C_DutyCycle_TypeDef I2C_DutyCycle,
+              I2C_Ack_TypeDef I2C_Ack, I2C_AcknowledgedAddress_TypeDef I2C_AcknowledgedAddress)
+{
+  uint32_t result = 0x0004;
+  uint16_t tmpval = 0;
+  uint8_t tmpccrh = 0;
+  uint8_t input_clock = 0;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_MODE(I2C_Mode));
+  assert_param(IS_I2C_ACK_STATE(I2C_Ack));
+  assert_param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_AcknowledgedAddress));
+  assert_param(IS_I2C_DUTY_CYCLE(I2C_DutyCycle));
+  assert_param(IS_I2C_OWN_ADDRESS(OwnAddress));
+  assert_param(IS_I2C_OUTPUT_CLOCK_FREQ(OutputClockFrequency));
+
+
+  /* Get system clock frequency */
+  input_clock = (uint8_t) (CLK_GetClockFreq() / 1000000);
+
+  /*------------------------- I2C FREQ Configuration ------------------------*/
+  /* Clear frequency bits */
+  I2Cx->FREQR &= (uint8_t)(~I2C_FREQR_FREQ);
+  /* Write new value */
+  I2Cx->FREQR |= input_clock;
+
+  /*--------------------------- I2C CCR Configuration ------------------------*/
+  /* Disable I2C to configure TRISER */
+  I2Cx->CR1 &= (uint8_t)(~I2C_CR1_PE);
+
+  /* Clear CCRH & CCRL */
+  I2Cx->CCRH &= (uint8_t)(~(I2C_CCRH_FS | I2C_CCRH_DUTY | I2C_CCRH_CCR));
+  I2Cx->CCRL &= (uint8_t)(~I2C_CCRL_CCR);
+
+  /* Detect Fast or Standard mode depending on the Output clock frequency selected */
+  if (OutputClockFrequency > I2C_MAX_STANDARD_FREQ) /* FAST MODE */
+  {
+    /* Set F/S bit for fast mode */
+    tmpccrh = I2C_CCRH_FS;
+
+    if (I2C_DutyCycle == I2C_DutyCycle_2)
+    {
+      /* Fast mode speed calculate: Tlow/Thigh = 2 */
+      result = (uint32_t) ((input_clock * 1000000) / (OutputClockFrequency * 3));
+    }
+    else /* I2C_DUTYCYCLE_16_9 */
+    {
+      /* Fast mode speed calculate: Tlow/Thigh = 16/9 */
+      result = (uint32_t) ((input_clock * 1000000) / (OutputClockFrequency * 25));
+      /* Set DUTY bit */
+      tmpccrh |= I2C_CCRH_DUTY;
+    }
+
+    /* Verify and correct CCR value if below minimum value */
+    if (result < (uint16_t)0x01)
+    {
+      /* Set the minimum allowed value */
+      result = (uint16_t)0x0001;
+    }
+
+    /* Set Maximum Rise Time: 300ns max in Fast Mode
+    = [300ns/(1/input_clock.10e6)]+1
+    = [(input_clock * 3)/10]+1 */
+    tmpval = ((input_clock * 3) / 10) + 1;
+    I2Cx->TRISER = (uint8_t)tmpval;
+
+  }
+  else /* STANDARD MODE */
+  {
+
+    /* Calculate standard mode speed */
+    result = (uint16_t)((input_clock * 1000000) / (OutputClockFrequency << (uint8_t)1));
+
+    /* Verify and correct CCR value if below minimum value */
+    if (result < (uint16_t)0x0004)
+    {
+      /* Set the minimum allowed value */
+      result = (uint16_t)0x0004;
+    }
+
+    /* Set Maximum Rise Time: 1000ns max in Standard Mode
+    = [1000ns/(1/input_clock.10e6)]+1
+    = input_clock+1 */
+    I2Cx->TRISER = (uint8_t)((uint8_t)input_clock + (uint8_t)1);
+
+  }
+
+  /* Write CCR with new calculated value */
+  I2Cx->CCRL = (uint8_t)result;
+  I2Cx->CCRH = (uint8_t)((uint8_t)((uint8_t)((uint8_t)result >> 8) & I2C_CCRH_CCR) | tmpccrh);
+
+  /* Enable I2C and  Configure its mode*/
+  I2Cx->CR1 |= (uint8_t)(I2C_CR1_PE | I2C_Mode);
+
+  /* Configure I2C acknowledgement */
+  I2Cx->CR2 |= (uint8_t)I2C_Ack;
+
+  /*--------------------------- I2C OAR Configuration ------------------------*/
+  I2Cx->OARL = (uint8_t)(OwnAddress);
+  I2Cx->OARH = (uint8_t)((uint8_t)(I2C_AcknowledgedAddress | I2C_OARH_ADDCONF ) | \
+                         (uint8_t)((uint16_t)( (uint16_t)OwnAddress &  (uint16_t)0x0300) >> 7));
+}
+
+/**
+  * @brief  Enables or disables the I2C peripheral.
+  * @param  I2Cx: where x can be 1 to select the specified I2C peripheral.
+  * @param  NewState: Indicate the new I2C peripheral state.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+
+  /* Check function parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable I2C peripheral */
+    I2Cx->CR1 |= I2C_CR1_PE;
+  }
+  else /* NewState == DISABLE */
+  {
+    /* Disable I2C peripheral */
+    I2Cx->CR1 &= (uint8_t)(~I2C_CR1_PE);
+  }
+}
+
+/**
+  * @brief  Enables or disables the I2C General Call feature.
+  * @param  I2Cx: where x can be 1 to select the specified I2C peripheral.
+  * @param  NewState: State of the General Call feature.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+
+  /* Check function parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable General Call */
+    I2Cx->CR1 |= I2C_CR1_ENGC;
+  }
+  else /* NewState == DISABLE */
+  {
+    /* Disable General Call */
+    I2Cx->CR1 &= (uint8_t)(~I2C_CR1_ENGC);
+  }
+}
+
+/**
+  * @brief  Generates I2C communication START condition.
+  * @note   CCR must be programmed, i.e. I2C_Init function must have been called
+  *         with a valid I2C_ClockSpeed
+  * @param  I2Cx: where x can be 1 to select the specified I2C peripheral.
+  * @param  NewState: Enable or disable the start condition.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+
+  /* Check function parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Generate a START condition */
+    I2Cx->CR2 |= I2C_CR2_START;
+  }
+  else /* NewState == DISABLE */
+  {
+    /* Disable the START condition generation */
+    I2Cx->CR2 &= (uint8_t)(~I2C_CR2_START);
+  }
+}
+
+/**
+  * @brief  Generates I2C communication STOP condition.
+  * @param  I2Cx: where x can be 1 to select the specified I2C peripheral.
+  * @param  NewState: Enable or disable the stop condition.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+
+  /* Check function parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Generate a STOP condition */
+    I2Cx->CR2 |= I2C_CR2_STOP;
+  }
+  else /* NewState == DISABLE */
+  {
+    /* Disable the STOP condition generation */
+    I2Cx->CR2 &= (uint8_t)(~I2C_CR2_STOP);
+  }
+}
+
+/**
+  * @brief  Enables or disables I2C software reset.
+  * @param  I2Cx: where x can be 1 to select the specified I2C peripheral.
+  * @param  NewState: Specifies the new state of the I2C software reset.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check function parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Peripheral under reset */
+    I2Cx->CR2 |= I2C_CR2_SWRST;
+  }
+  else /* NewState == DISABLE */
+  {
+    /* Peripheral not under reset */
+    I2Cx->CR2 &= (uint8_t)(~I2C_CR2_SWRST);
+  }
+}
+
+/**
+  * @brief  Enables or disables the I2C clock stretching.
+  * @param  I2Cx: where x can be 1 to select the specified I2C peripheral.
+  * @param  NewState: Specifies the new state of the I2C Clock stretching.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check function parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Clock Stretching Enable */
+    I2Cx->CR1 &= (uint8_t)(~I2C_CR1_NOSTRETCH);
+
+  }
+  else /* NewState == DISABLE */
+  {
+    /* Clock Stretching Disable (Slave mode) */
+    I2Cx->CR1 |= I2C_CR1_NOSTRETCH;
+  }
+}
+
+/**
+  * @brief  Enables or disables the I2C ARP.
+  * @param  I2Cx: where x can be 1 to select the specified I2C peripheral.
+  * @param  NewState: Specifies the new state of the I2C ARP
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check function parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* ARP Enable */
+    I2Cx->CR1 |= I2C_CR1_ARP;
+
+  }
+  else /* NewState == DISABLE */
+  {
+    /* ARP Disable  */
+    I2Cx->CR1 &= (uint8_t)(~I2C_CR1_ARP);
+  }
+}
+
+/**
+  * @brief  Enable or Disable the I2C acknowledge feature.
+  * @param  I2Cx: where x can be 1 to select the specified I2C peripheral.
+  * @param  NewState: Specifies the new state of the I2C acknowledge.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check function parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the acknowledgement */
+    I2Cx->CR2 |= I2C_CR2_ACK;
+  }
+  else
+  {
+    /* Disable the acknowledgement */
+    I2Cx->CR2 &= (uint8_t)(~I2C_CR2_ACK);
+  }
+}
+
+/**
+  * @brief  Configures the specified I2C own address2.
+  * @param  I2Cx: where x can be 1 to select the specified I2C peripheral.
+  * @param  Address: specifies the 7bit I2C own address2.
+  * @retval None.
+  */
+void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address)
+{
+  uint8_t tmpreg = 0;
+
+  /* Get the old register value */
+  tmpreg = I2Cx->OAR2;
+
+  /* Reset I2Cx Own address2 bit [7:1] */
+  tmpreg &= (uint8_t)(~I2C_OAR2_ADD2);
+
+  /* Set I2Cx Own address2 */
+  tmpreg |= (uint8_t) ((uint8_t)Address & (uint8_t)0xFE);
+
+  /* Store the new register value */
+  I2Cx->OAR2 = tmpreg;
+}
+
+/**
+  * @brief  Enables or disables the specified I2C dual addressing mode.
+  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+  * @param  NewState: new state of the I2C dual addressing mode.
+    *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable dual addressing mode */
+    I2Cx->OAR2 |= I2C_OAR2_ENDUAL;
+  }
+  else
+  {
+    /* Disable dual addressing mode */
+    I2Cx->OAR2 &= (uint8_t)(~I2C_OAR2_ENDUAL);
+  }
+}
+
+/**
+  * @brief  Selects the specified I2C Ack position.
+  * @note   This function must be called before data reception starts.
+  * @param  I2Cx: where x can be 1 to select the specified I2C peripheral.
+  * @param  I2C_AckPosition: specifies the Ack position.
+  *          This parameter can be one of the following values:
+  *            @arg I2C_AckPosition_Current: Acknowledge on the current byte
+  *            @arg I2C_AckPosition_Next: Acknowledge on the next byte
+  * @retval None
+  */
+void I2C_AckPositionConfig(I2C_TypeDef* I2Cx, I2C_AckPosition_TypeDef I2C_AckPosition)
+{
+  /* Check function parameters */
+  assert_param(IS_I2C_ACK_POSITION(I2C_AckPosition));
+
+  /* Clear the I2C Ack position */
+  I2Cx->CR2 &= (uint8_t)(~I2C_CR2_POS);
+  /* Configure the specified I2C Ack position*/
+  I2Cx->CR2 |= (uint8_t)I2C_AckPosition;
+}
+
+/**
+  * @brief  Drives the SMBusAlert pin high or low.
+  * @param  I2Cx: where x can be 1 to select the specified I2C peripheral.
+  * @param  I2C_SMBusAlert: SMBusAlert pin state.
+  *          This parameter can be one of the following values:
+  *            @arg I2C_SMBusAlert_High: SMBAlert pin high
+  *            @arg I2C_SMBusAlert_Low: SMBAlert pin Low
+  * @retval None
+  */
+void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, I2C_SMBusAlert_TypeDef I2C_SMBusAlert)
+{
+
+  /* Check functions parameters */
+  assert_param(IS_I2C_SMBUS_ALERT(I2C_SMBusAlert));
+
+  if (I2C_SMBusAlert != I2C_SMBusAlert_High)
+  {
+    /* SMBus Alert pin low */
+    I2Cx->CR2 |= (uint8_t)I2C_CR2_ALERT;
+  }
+  else /*I2C_SMBusAlert = I2C_SMBusAlert_High */
+  {
+    /* SMBus Alert pin high */
+    I2Cx->CR2 &= (uint8_t)(~I2C_CR2_ALERT);
+  }
+}
+
+/**
+  * @brief  Selects I2C fast mode duty cycle.
+  * @param  I2Cx: where x can be 1 to select the specified I2C peripheral.
+  * @param  I2C_DutyCycle: specifies the fast mode duty cycle.
+  *          This parameter can be one of the following values:
+  *            @arg I2C_DutyCycle_2: I2C fast mode Tlow/Thigh = 2
+  *            @arg I2C_DutyCycle_16_9: I2C fast mode Tlow/Thigh = 16/9
+  * @retval None
+  */
+void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, I2C_DutyCycle_TypeDef I2C_DutyCycle)
+{
+
+  /* Check function parameters */
+  assert_param(IS_I2C_DUTY_CYCLE(I2C_DutyCycle));
+
+  if (I2C_DutyCycle == I2C_DutyCycle_16_9)
+  {
+    /* I2C fast mode Tlow/Thigh = 16/9 */
+    I2Cx->CCRH |= I2C_CCRH_DUTY;
+  }
+  else /* I2C_DUTYCYCLE_2 */
+  {
+    /* I2C fast mode Tlow/Thigh = 2 */
+    I2Cx->CCRH &= (uint8_t)(~I2C_CCRH_DUTY);
+  }
+}
+
+/**
+  * @brief  Transmits the 7-bit address (to select the) slave device.
+  * @param  I2Cx: where x can be 1 to select the specified I2C peripheral.
+  * @param  Address: Specifies the slave address which will be transmitted.
+  * @param  I2C_Direction: specifies whether the I2C device will be a Transmitter
+  *         or a Receiver.
+  *          This parameter can be one of the following values
+  *            @arg I2C_Direction_Transmitter: Transmitter mode
+  *            @arg I2C_Direction_Receiver: Receiver mode
+  * @retval None
+  */
+void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, I2C_Direction_TypeDef I2C_Direction)
+{
+  /* Check function parameters */
+  assert_param(IS_I2C_ADDRESS(Address));
+  assert_param(IS_I2C_DIRECTION(I2C_Direction));
+
+  /* Test on the direction to set/reset the read/write bit */
+  if (I2C_Direction != I2C_Direction_Transmitter)
+  {
+    /* Set the address bit0 for read */
+    Address |= OAR1_ADD0_Set;
+  }
+  else
+  {
+    /* Reset the address bit0 for write */
+    Address &= OAR1_ADD0_Reset;
+  }
+  /* Send the address */
+  I2Cx->DR = Address;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Group2 Data transfers functions
+ *  @brief   Data transfers functions
+ *
+@verbatim
+ ===============================================================================
+                        Data transfers functions
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Send a byte by writing in the DR register.
+  * @param  I2Cx: where x can be 1 to select the specified I2C peripheral.
+  * @param  Data: Byte to be sent.
+  * @retval None
+  */
+void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data)
+{
+  /* Write in the DR register the data to be sent */
+  I2Cx->DR = Data;
+}
+
+/**
+  * @brief  Returns the most recent received data.
+  * @param  I2Cx: where x can be 1 to select the specified I2C peripheral.
+  * @param  None
+  * @retval The value of the received byte data.
+  */
+uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx)
+{
+  /* Return the data present in the DR register */
+  return ((uint8_t)I2Cx->DR);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Group3 PEC management functions
+ *  @brief   PEC management functions
+ *
+@verbatim
+ ===============================================================================
+                         PEC management functions
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables PEC transfer.
+  * @param  I2Cx: where x can be 1 to select the specified I2C peripheral.
+  * @param  NewState: indicates the PEC  transfer state.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the PEC transmission */
+    I2Cx->CR2 |= I2C_CR2_PEC;
+  }
+  else
+  {
+    /* Disable the PEC transmission */
+    I2Cx->CR2 &= (uint8_t)(~I2C_CR2_PEC);
+  }
+}
+
+/**
+  * @brief  Enables or disables PEC calculation.
+  * @param  I2Cx: where x can be 1 to select the specified I2C peripheral.
+  * @param  NewState: indicates the PEC  calculation state.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable PEC calculation */
+    I2Cx->CR1 |= I2C_CR1_ENPEC;
+  }
+  else
+  {
+    /* Disable PEC calculation */
+    I2Cx->CR1 &= (uint8_t)(~I2C_CR1_ENPEC);
+  }
+}
+
+/**
+  * @brief  Selects I2C PEC position..
+  * @param  I2Cx: where x can be 1 to select the specified I2C peripheral.
+  * @param  I2C_PECPosition:PEC position.
+  *          This parameter can be one of the following values:
+  *            @arg I2C_PECPosition_Current: Current byte in shift register is PEC
+  *            @arg I2C_PECPosition_Next: Next  byte in shift register is PEC
+  * @retval None
+  */
+void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, I2C_PECPosition_TypeDef I2C_PECPosition)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_PEC_POSITION(I2C_PECPosition));
+
+  /* Clear the I2C PEC position */
+  I2Cx->CR2 &= (uint8_t)(~I2C_CR2_POS);
+  /* Configure the specified I2C PEC position*/
+  I2Cx->CR2 |= (uint8_t)I2C_PECPosition;
+}
+
+/**
+  * @brief  Returns PEC value.
+  * @param  I2Cx: where x can be 1 to select the specified I2C peripheral.
+  * @param  None
+  * @retval The value of the PEC.
+  */
+uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx)
+{
+  /* Return the PEC value */
+  return (I2Cx->PECR);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Group4 DMA transfers management functions
+ *  @brief   DMA transfers management functions
+ *
+@verbatim
+ ===============================================================================
+                         DMA transfers management functions
+ ===============================================================================
+  This section provides functions allowing to configure the I2C DMA channels
+  requests.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the I2C DMA requests .
+  * @param  I2Cx: where x can be 1 to select the specified I2C peripheral.
+  * @param  NewState: Indicate the new I2C DMA state.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable I2C DMA requests */
+    I2Cx->ITR |= I2C_ITR_DMAEN;
+  }
+  else
+  {
+    /* Disable I2C DMA requests */
+    I2Cx->ITR &= (uint8_t)(~I2C_ITR_DMAEN);
+  }
+}
+
+/**
+  * @brief  Specifies that the next DMA transfer is the last one .
+  * @param  I2Cx: where x can be 1 to select the specified I2C peripheral.
+  * @param  NewState: Indicate the new I2C DMA state.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable I2C DMA requests */
+    I2Cx->ITR |= I2C_ITR_LAST;
+  }
+  else
+  {
+    /* Disable I2C DMA requests */
+    I2Cx->ITR &= (uint8_t)(~I2C_ITR_LAST);
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Group5 Interrupts events and flags management functions
+ *  @brief   Interrupts, events and flags management functions
+ *
+@verbatim
+ ===============================================================================
+                Interrupts, events and flags management functions
+ ===============================================================================
+  This section provides functions allowing to configure the I2C Interrupts
+  sources and check or clear the flags or pending bits status.
+  The user should identify which mode will be used in his application to manage
+  the communication: Polling mode, Interrupt mode or DMA mode.
+
+ ===============================================================================
+                          I2C State Monitoring Functions
+ ===============================================================================
+ This I2C driver provides three different ways for I2C state monitoring
+  depending on the application requirements and constraints:
+
+
+     1. Basic state monitoring (Using I2C_CheckEvent() function)
+     -----------------------------------------------------------
+    It compares the status registers (SR1, SR2 and SR3) content to a given event
+    (can be the combination of one or more flags).
+    It returns SUCCESS if the current status includes the given flags
+    and returns ERROR if one or more flags are missing in the current status.
+    - When to use:
+      - This function is suitable for most applications as well as for startup
+      activity since the events are fully described in the product reference manual
+      (RM0031).
+      - It is also suitable for users who need to define their own events.
+    - Limitations:
+      - If an error occurs (ie. error flags are set besides to the monitored flags),
+        the I2C_CheckEvent() function may return SUCCESS despite the communication
+        hold or corrupted real state.
+        In this case, it is advised to use error interrupts to monitor the error
+        events and handle them in the interrupt IRQ handler.
+
+        @note
+        For error management, it is advised to use the following functions:
+          - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).
+          - I2Cx_IRQHandler() which is called when the I2C interrupts occur.
+            Where x is the peripheral instance (I2C1,...)
+         - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into the
+           I2Cx_IRQHandler() function in order to determine which error occurred.
+          - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd()
+            and/or I2C_GenerateStop() in order to clear the error flag and
+            source and return to correct communication status.
+
+
+     2. Advanced state monitoring (Using the function I2C_GetLastEvent())
+     --------------------------------------------------------------------
+     Using the function I2C_GetLastEvent() which returns the image of both SR1
+     & SR3 status registers in a single word (uint16_t) (Status Register 3 value
+     is shifted left by 8 bits and concatenated to Status Register 1).
+     - When to use:
+       - This function is suitable for the same applications above but it allows to
+         overcome the limitations of I2C_GetFlagStatus() function (see below).
+         The returned value could be compared to events already defined in the
+         library (stm8l15x_i2c.h) or to custom values defined by user.
+       - This function is suitable when multiple flags are monitored at the same time.
+       - At the opposite of I2C_CheckEvent() function, this function allows user to
+         choose when an event is accepted (when all events flags are set and no
+         other flags are set or just when the needed flags are set like
+         I2C_CheckEvent() function).
+     - Limitations:
+       - User may need to define his own events.
+       - Same remark concerning the error management is applicable for this
+         function if user decides to check only regular communication flags (and
+         ignores error flags).
+
+
+     3. Flag-based state monitoring (Using the function I2C_GetFlagStatus())
+     -----------------------------------------------------------------------
+     Using the function I2C_GetFlagStatus() which simply returns the status of
+     one single flag (ie. I2C_FLAG_RXNE ...).
+     - When to use:
+        - This function could be used for specific applications or in debug phase.
+        - It is suitable when only one flag checking is needed (most I2C events
+          are monitored through multiple flags).
+     - Limitations:
+        - When calling this function, the Status register is accessed. Some flags are
+          cleared when the status register is accessed. So checking the status
+          of one Flag, may clear other ones.
+        - Function may need to be called twice or more in order to monitor one
+          single event.
+
+  For detailed description of Events, please refer to section I2C_Events in
+  stm8l15x_i2c.h file.
+
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the specified I2C interrupt.
+  * @param  I2Cx: where x can be 1 to select the specified I2C peripheral.
+  * @param  I2C_IT: specifies the I2C interrupts sources to be enabled or disabled.
+  *          This parameter can be any combination of the following values:
+  *            @arg I2C_IT_BUF: Buffer interrupt mask
+  *            @arg I2C_IT_EVT: Event interrupt mask
+  *            @arg I2C_IT_ERR: Error interrupt mask
+  * @param  NewState: State of the interrupt.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_ITConfig(I2C_TypeDef* I2Cx, I2C_IT_TypeDef I2C_IT, FunctionalState NewState)
+{
+  /* Check functions parameters */
+  assert_param(IS_I2C_CONFIG_IT(I2C_IT));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected I2C interrupts */
+    I2Cx->ITR |= (uint8_t)I2C_IT;
+  }
+  else /* NewState == DISABLE */
+  {
+    /* Disable the selected I2C interrupts */
+    I2Cx->ITR &= (uint8_t)(~(uint8_t)I2C_IT);
+  }
+}
+
+/**
+  * @brief  Reads the specified I2C register and returns its value.
+  * @param  I2Cx: where x can be 1 to select the specified I2C peripheral.
+  * @param  I2C_Register: specifies the register to read.
+  *          This parameter can be one of the following values:
+  *            @arg I2C_Register_CR1: CR1 register.
+  *            @arg I2C_Register_CR2: CR2 register.
+  *            @arg I2C_Register_FREQR: Frequency register.
+  *            @arg I2C_Register_OARL: Own address register LSB.
+  *            @arg I2C_Register_OARH: Own address register MSB
+  *            @arg I2C_Register_DR: DR register.
+  *            @arg I2C_Register_SR1: SR1 register.
+  *            @arg I2C_Register_SR2: SR2 register.
+  *            @arg I2C_Register_SR3: SR3 register.
+  *            @arg I2C_Register_ITR: Interrupt and DMA register.
+  *            @arg I2C_Register_CCRL: Clock control register low.
+  *            @arg I2C_Register_CCRH: Clock control register high.
+  *            @arg I2C_Register_TRISER: TRISE register.
+  *            @arg I2C_Register_PECR: PEC register.
+  * @retval The value of the read register.
+  */
+
+uint8_t I2C_ReadRegister(I2C_TypeDef* I2Cx, I2C_Register_TypeDef I2C_Register)
+{
+  __IO uint16_t tmp = 0;
+  /* Check the parameters */
+  assert_param(IS_I2C_REGISTER(I2C_Register));
+
+  tmp = (uint16_t) I2Cx;
+  tmp += I2C_Register;
+
+  /* Return the selected register value */
+  return (*(__IO uint8_t *) tmp);
+}
+
+
+/**
+ ===============================================================================
+                          1. Basic state monitoring
+ ===============================================================================
+ */
+
+/**
+  * @brief  Checks whether the last I2Cx Event is equal to the one passed
+  *   as parameter.
+  * @param  I2Cx: where x can be 1 to select the I2C peripheral.
+  * @param  I2C_EVENT: specifies the event to be checked.
+  *          This parameter can be one of the following values:
+  *            @arg I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED: EV1
+  *            @arg I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED: EV1
+  *            @arg I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED: EV1
+  *            @arg I2C_EVENT_SLAVE_BYTE_RECEIVED: EV2
+  *            @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL): EV2
+  *            @arg I2C_EVENT_SLAVE_BYTE_TRANSMITTED: EV3
+  *            @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL): EV3
+  *            @arg I2C_EVENT_SLAVE_ACK_FAILURE: EV3_2
+  *            @arg I2C_EVENT_SLAVE_STOP_DETECTED: EV4
+  *            @arg I2C_EVENT_MASTER_MODE_SELECT: EV5
+  *            @arg I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED: EV6
+  *            @arg I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED: EV6
+  *            @arg I2C_EVENT_MASTER_BYTE_RECEIVED: EV7
+  *            @arg I2C_EVENT_MASTER_BYTE_TRANSMITTING: EV8
+  *            @arg I2C_EVENT_MASTER_BYTE_TRANSMITTED: EV8_2
+  *            @arg I2C_EVENT_MASTER_MODE_ADDRESS10: EV9
+  *
+  * @note: For detailed description of Events, please refer to section
+  *    I2C_Events in stm8l15x_i2c.h file.
+  *
+  * @retval An ErrorStatus enumeration value:
+  *         - SUCCESS: Last event is equal to the I2C_EVENT
+  *         - ERROR: Last event is different from the I2C_EVENT
+  */
+ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, I2C_Event_TypeDef I2C_Event)
+{
+  __IO uint16_t lastevent = 0x00;
+  uint8_t flag1 = 0x00 ;
+  uint8_t flag2 = 0x00;
+  ErrorStatus status = ERROR;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_EVENT(I2C_Event));
+
+  if (I2C_Event == I2C_EVENT_SLAVE_ACK_FAILURE)
+  {
+    lastevent = I2Cx->SR2 & I2C_SR2_AF;
+  }
+  else
+  {
+    flag1 = I2Cx->SR1;
+    flag2 = I2Cx->SR3;
+    lastevent = ((uint16_t)((uint16_t)flag2 << (uint16_t)8) | (uint16_t)flag1);
+  }
+  /* Check whether the last event is equal to I2C_EVENT */
+  if (((uint16_t)lastevent & (uint16_t)I2C_Event) == (uint16_t)I2C_Event)
+  {
+    /* SUCCESS: last event is equal to I2C_EVENT */
+    status = SUCCESS;
+  }
+  else
+  {
+    /* ERROR: last event is different from I2C_EVENT */
+    status = ERROR;
+  }
+
+  /* Return status */
+  return status;
+}
+
+/**
+ ===============================================================================
+                          2. Advanced state monitoring
+ ===============================================================================
+ */
+
+/**
+  * @brief  Returns the last I2C Event.
+  * @param  I2Cx: where x can be 1 to select the specified I2C peripheral.
+  *
+  * @note: For detailed description of Events, please refer to section
+  *    I2C_Events in stm8l15xx_i2c.h file.
+  *
+  * @retval The last event
+  */
+I2C_Event_TypeDef I2C_GetLastEvent(I2C_TypeDef* I2Cx)
+{
+  __IO uint16_t lastevent = 0;
+  uint16_t flag1 = 0;
+  uint16_t flag2 = 0;
+
+  if ((I2Cx->SR2 & I2C_SR2_AF) != 0x00)
+  {
+    lastevent = I2C_EVENT_SLAVE_ACK_FAILURE;
+  }
+  else
+  {
+    /* Read the I2C status register */
+    flag1 = I2Cx->SR1;
+    flag2 = I2Cx->SR3;
+
+    /* Get the last event value from I2C status register */
+    lastevent = ((uint16_t)((uint16_t)flag2 << 8) | (uint16_t)flag1);
+  }
+  /* Return status */
+  return (I2C_Event_TypeDef)lastevent;
+}
+
+/**
+ ===============================================================================
+                          3. Flag-based state monitoring
+ ===============================================================================
+ */
+
+/**
+  * @brief  Checks whether the specified I2C flag is set or not.
+  * @param  I2Cx: where x can be 1 select the I2C peripheral.
+  * @param  I2C_FLAG: specifies the flag to check.
+  *          This parameter can be one of the following values:
+  *            @arg I2C_FLAG_SMBHOST: SMBus host header (Slave mode)
+  *            @arg I2C_FLAG_SMBDEFAULT: SMBus default header (Slave mode)
+  *            @arg I2C_FLAG_GENCALL: General call header flag (Slave mode)
+  *            @arg I2C_FLAG_TRA: Transmitter/Receiver flag
+  *            @arg I2C_FLAG_BUSY: Bus busy flag
+  *            @arg I2C_FLAG_MSL: Master/Slave flag
+  *            @arg I2C_FLAG_SMBALERT: SMBus Alert flag
+  *            @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
+  *            @arg I2C_FLAG_PECERR: PEC error in reception flag
+  *            @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
+  *            @arg I2C_FLAG_AF: Acknowledge failure flag
+  *            @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
+  *            @arg I2C_FLAG_BERR: Bus error flag
+  *            @arg I2C_FLAG_TXE: Data register empty flag (Transmitter)
+  *            @arg I2C_FLAG_RXNE: Data register not empty (Receiver) flag
+  *            @arg I2C_FLAG_STOPF: Stop detection flag (Slave mode)
+  *            @arg I2C_FLAG_ADD10: 10-bit header sent flag (Master mode)
+  *            @arg I2C_FLAG_BTF: Byte transfer finished flag
+  *            @arg I2C_FLAG_ADDR: Address sent flag (Master mode) “ADSL”
+  *   Address matched flag (Slave mode)”ENDAD”
+  *            @arg I2C_FLAG_SB: Start bit flag (Master mode)
+  * @retval The new state of I2C_FLAG (SET or RESET).
+  */
+FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, I2C_FLAG_TypeDef I2C_FLAG)
+{
+  uint8_t tempreg = 0;
+  uint8_t regindex = 0;
+  FlagStatus bitstatus = RESET;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_GET_FLAG(I2C_FLAG));
+
+  /* Read flag register index */
+  regindex = (uint8_t)((uint16_t)I2C_FLAG >> 8);
+  /* Check SRx index */
+  switch (regindex)
+  {
+      /* Returns whether the status register to check is SR1 */
+    case 0x01:
+      tempreg = (uint8_t)I2Cx->SR1;
+      break;
+
+      /* Returns whether the status register to check is SR2 */
+    case 0x02:
+      tempreg = (uint8_t)I2Cx->SR2;
+      break;
+
+      /* Returns whether the status register to check is SR3 */
+    case 0x03:
+      tempreg = (uint8_t)I2Cx->SR3;
+      break;
+
+    default:
+      break;
+  }
+
+  /* Check the status of the specified I2C flag */
+  if ((tempreg & (uint8_t)I2C_FLAG ) != 0)
+  {
+    /* Flag is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* Flag is reset */
+    bitstatus = RESET;
+  }
+  /* Return the flag status */
+  return bitstatus;
+}
+/**
+  * @brief  Clear flags
+  * @param  I2Cx: where x can be 1 to select the specified I2C peripheral.
+  * @param  I2C_Flag: Specifies the flag to clear
+  *          This parameter can be any combination of the following values:
+  *            @arg I2C_FLAG_SMBALERT: SMBus Alert flag
+  *            @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
+  *            @arg I2C_FLAG_PECERR: PEC error in reception flag
+  *            @arg I2C_FLAG_WUFH: Wakeup from Halt
+  *            @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
+  *            @arg I2C_FLAG_AF: Acknowledge failure flag
+  *            @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
+  *            @arg I2C_FLAG_BERR: Bus error flag.
+  * @note   STOPF (STOP detection) is cleared by software sequence: a read operation
+  *          to I2C_SR1 register (I2C_GetFlagStatus()) followed by a write operation
+  *          to I2C_CR2 register.
+  * @note   ADD10 (10-bit header sent) is cleared by software sequence: a read
+  *          operation to I2C_SR1 (I2C_GetFlagStatus()) followed by writing the
+  *          second byte of the address in DR register.
+  * @note   BTF (Byte Transfer Finished) is cleared by software sequence: a read
+  *         operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a
+  *         read/write to I2C_DR register (I2C_SendData()).
+  * @note   ADDR (Address sent) is cleared by software sequence: a read operation
+  *         to I2C_SR1 register(I2C_GetFlagStatus()) followed by a read operation
+  *         to I2C_SR3 register ((void)(I2Cx->SR3)).
+  * @note   SB (Start Bit) is cleared software sequence: a read operation to
+  *         I2C_SR1 register (I2C_GetFlagStatus()) followed by a write operation
+  *         to I2C_DR register (I2C_SendData()).
+  * @retval None
+  */
+void I2C_ClearFlag(I2C_TypeDef* I2Cx, I2C_FLAG_TypeDef I2C_FLAG)
+{
+  uint16_t flagpos = 0;
+  /* Check the parameters */
+  assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG));
+
+  /* Get the I2C flag position */
+  flagpos = (uint16_t)I2C_FLAG & FLAG_Mask;
+  /* Clear the selected I2C flag */
+  I2Cx->SR2 = (uint8_t)((uint16_t)(~flagpos));
+}
+
+/**
+  * @brief  Checks whether the specified I2C interrupt has occurred or not.
+  * @param  I2Cx: where x can be 1 to select the specified I2C peripheral.
+  * @param  I2C_IT: specifies the interrupt source to check.
+  *            This parameter can be one of the following values:
+  *            @arg I2C_IT_SMBALERT: SMBus Alert interrupt
+  *            @arg I2C_IT_TIMEOUT: Timeout or Tlow error interrupt
+  *            @arg I2C_IT_PECERR: PEC error in reception  interrupt
+  *            @arg I2C_IT_WUFH: Wakeup from Halt
+  *            @arg I2C_IT_OVR: Overrun/Underrun flag (Slave mode)
+  *            @arg I2C_IT_AF: Acknowledge failure flag
+  *            @arg I2C_IT_ARLO: Arbitration lost flag (Master mode)
+  *            @arg I2C_IT_BERR: Bus error flag
+  *            @arg I2C_IT_TXE: Data register empty flag (Transmitter)
+  *            @arg I2C_IT_RXNE: Data register not empty (Receiver) flag
+  *            @arg I2C_IT_STOPF: Stop detection flag (Slave mode)
+  *            @arg I2C_IT_ADD10: 10-bit header sent flag (Master mode)
+  *            @arg I2C_IT_BTF: Byte transfer finished flag
+  *            @arg I2C_IT_ADDR: Address sent flag (Master mode) “ADSL”
+  *                              Address matched flag (Slave mode)“ENDAD”
+  *            @arg I2C_IT_SB: Start bit flag (Master mode)
+  * @retval The new state of I2C_IT
+  */
+ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, I2C_IT_TypeDef I2C_IT)
+{
+  ITStatus bitstatus = RESET;
+  __IO uint8_t enablestatus = 0;
+  uint16_t tempregister = 0;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_GET_IT(I2C_IT));
+
+  tempregister = (uint8_t)( ((uint16_t)((uint16_t)I2C_IT & ITEN_Mask)) >> 8);
+
+  /* Check if the interrupt source is enabled or not */
+  enablestatus = (uint8_t)(I2Cx->ITR & ( uint8_t)tempregister);
+
+  if ((uint16_t)((uint16_t)I2C_IT & REGISTER_Mask) == REGISTER_SR1_Index)
+  {
+    /* Check the status of the specified I2C flag */
+    if (((I2Cx->SR1 & (uint8_t)I2C_IT) != RESET) && enablestatus)
+    {
+      /* I2C_IT is set */
+      bitstatus = SET;
+    }
+    else
+    {
+      /* I2C_IT is reset */
+      bitstatus = RESET;
+    }
+  }
+  else
+  {
+    /* Check the status of the specified I2C flag */
+    if (((I2Cx->SR2 & (uint8_t)I2C_IT) != RESET) && enablestatus)
+    {
+      /* I2C_IT is set */
+      bitstatus = SET;
+    }
+    else
+    {
+      /* I2C_IT is reset */
+      bitstatus = RESET;
+    }
+  }
+  /* Return the I2C_IT status */
+  return  bitstatus;
+}
+/**
+  * @brief  Clear IT pending bit
+  * @param  I2Cx: where x can be 1 to select the specified I2C peripheral.
+  * @param  I2C_IT: specifies the interrupt pending bit to clear.
+  *            This parameter can be any combination of the following values:
+  *            @arg I2C_IT_SMBALERT: SMBus Alert interrupt
+  *            @arg I2C_IT_TIMEOUT: Timeout or Tlow error interrupt
+  *            @arg I2C_IT_PECERR: PEC error in reception  interrupt
+  *            @arg I2C_IT_WUFH: Wakeup from Halt
+  *            @arg I2C_IT_OVR: Overrun/Underrun interrupt (Slave mode)
+  *            @arg I2C_IT_AF: Acknowledge failure interrupt
+  *            @arg I2C_IT_ARLO: Arbitration lost interrupt (Master mode)
+  *            @arg I2C_IT_BERR: Bus error interrupt
+  *
+  * @note   STOPF (STOP detection) is cleared by software sequence: a read operation
+  *         to I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to
+  *         I2C_CR2 register (I2C_AcknowledgeConfig() to configure the I2C peripheral Acknowledge).
+  * @note   ADD10 (10-bit header sent) is cleared by software sequence: a read
+  *         operation to I2C_SR1 (I2C_GetITStatus()) followed by writing the second
+  *         byte of the address in I2C_DR register.
+  * @note   BTF (Byte Transfer Finished) is cleared by software sequence: a read
+  *         operation to I2C_SR1 register (I2C_GetITStatus()) followed by a read/write to
+  *         I2C_DR register (I2C_SendData()).
+  * @note   ADDR (Address sent) is cleared by software sequence: a read operation
+  *         to I2C_SR1 register (I2C_GetITStatus()) followed by a read operation
+  *         to I2C_SR3 register ((void)(I2Cx->SR3)).
+  * @note   SB (Start Bit) is cleared by software sequence: a read operation to
+  *         I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to
+  *         I2C_DR register (I2C_SendData()).
+  * @retval None
+  */
+void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, I2C_IT_TypeDef I2C_IT)
+{
+  uint16_t flagpos = 0;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_CLEAR_IT(I2C_IT));
+
+  /* Get the I2C flag position */
+  flagpos = (uint16_t)I2C_IT & FLAG_Mask;
+
+  /* Clear the selected I2C flag */
+  I2Cx->SR2 = (uint8_t)((uint16_t)~flagpos);
+}
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_irtim.c b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_irtim.c
new file mode 100755
index 0000000..c4cfd56
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_irtim.c
@@ -0,0 +1,196 @@
+/**
+  ******************************************************************************
+  * @file    stm8l15x_irtim.c
+  * @author  MCD Application Team
+  * @version V1.6.0
+  * @date    28-June-2013
+  * @brief   This file provides firmware functions to configure the IRTIM peripheral.
+  *
+  *  @verbatim
+  *  
+  *          ===================================================================
+  *                                 How to use this driver
+  *          ===================================================================
+  *          This driver provides functions to:
+  *             1. Enable the IRTIM peripheral
+  *             2. Enable the high sink mode on the IRTIM pin 
+  *               
+  *  @endverbatim
+  *    
+  ******************************************************************************
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ****************************************************************************** 
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm8l15x_irtim.h"
+
+/** @addtogroup STM8L15x_StdPeriph_Driver
+  * @{
+  */
+  
+/** @defgroup IRTIM 
+  * @brief IRTIM driver modules
+  * @{
+  */
+   
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/** @defgroup IRTIM_Private_Functions
+  * @{
+  */
+
+/** @defgroup IRTIM_Group1 IRTIM configuration functions
+ *  @brief   IRTIM configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+                       IRTIM configuration functions
+ ===============================================================================  
+  
+       ===================================================================      
+                       IRTIM Driver: how to use it
+       =================================================================== 
+       To generate the infrared remote control signal, perform the following steps:
+          1. Use TIM2 channel 1 to generate the high frequency carrier signal
+             by calling TIM2_OC1Init()
+          2. Use TIM3 channel 1 to generate the modulation envelope by
+             calling TIM3_OC1Init()
+          3. Enable the IRTIM peripheral using IRTIM_Cmd()
+
+          Note1: When IRTIM peripheral is enabled, TIM2 channel 1 and TIM3 channel 1
+                 become inactive (no signal on output) and can be used as GPIO.
+                 
+          Note2: The high sink LED driver capability (only available on the IRTIM pin)
+                 can be activated using IRTIM_HighSinkODCmd() to sink the high 
+                 current needed to directly control an infrared LED
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the IRTIM peripheral registers to their default reset values.
+  * @param  None
+  * @retval None
+  */
+void IRTIM_DeInit(void)
+{
+  IRTIM->CR = IRTIM_CR_RESET_VALUE;
+}
+
+/**
+  * @brief  Enables or disables the IRTIM peripheral.
+  * @param  NewState : The new state of the IRTIM peripheral.
+    *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void IRTIM_Cmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* set or Reset the EN Bit */
+  if (NewState ==   DISABLE)
+  {
+    IRTIM->CR &= (uint8_t)(~IRTIM_CR_EN) ;
+  }
+  else
+  {
+    IRTIM->CR |= IRTIM_CR_EN ;
+  }
+}
+
+/**
+  * @brief  Enables or disables the High sink open drain buffer of the IRTIM peripheral.
+  * @param  NewState : The new state of the High sink open drain buffer.
+    *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void IRTIM_HighSinkODCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* set or Reset the EN Bit */
+  if (NewState == DISABLE)
+  {
+    IRTIM->CR &= (uint8_t)(~IRTIM_CR_HSEN) ;
+  }
+  else
+  {
+    IRTIM->CR |= IRTIM_CR_HSEN ;
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup IRTIM_Group2 IRITM status management functions
+ *  @brief    IRITM status management functions 
+ *
+@verbatim   
+ ===============================================================================
+                     IRITM status management functions
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Checks whether the IRTIM device is enabled or not.
+  * @param  None
+  * @retval state of the IRTIM device.
+  */
+
+FunctionalState IRTIM_GetStatus(void)
+{
+  return ((FunctionalState) (IRTIM->CR & IRTIM_CR_EN));
+}
+
+/**
+  * @brief  Checks whether the IRTIM High Sink Open Drain buffer is Enabled or not.
+  * @param  None
+  * @retval state of High Sink Open Drain buffer.
+  */
+FunctionalState IRTIM_GetHighSinkODStatus(void)
+{
+  return ((FunctionalState)(IRTIM->CR & IRTIM_CR_HSEN));
+}
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+  
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_itc.c b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_itc.c
new file mode 100755
index 0000000..fe9c553
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_itc.c
@@ -0,0 +1,390 @@
+/**
+  ******************************************************************************
+  * @file    stm8l15x_itc.c
+  * @author  MCD Application Team
+  * @version V1.6.0
+  * @date    28-June-2013
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionality of the Interrupt controller (ITC) peripheral:           
+  *           - Configuration and management
+  ******************************************************************************
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ****************************************************************************** 
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm8l15x_itc.h"
+
+/** @addtogroup STM8L15x_StdPeriph_Driver
+  * @{
+  */
+  
+/** @defgroup ITC 
+  * @brief ITC driver modules
+  * @{
+  */ 
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup ITC_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Utility function used to read CC register.
+  * @param  None
+  * @retval CPU CC register value
+  */
+uint8_t ITC_GetCPUCC(void)
+{
+#ifdef _COSMIC_
+  _asm("push cc");
+  _asm("pop a");
+  return; /* Ignore compiler warning, the returned value is in A register */
+#elif defined _RAISONANCE_ /* _RAISONANCE_ */
+  return _getCC_();
+#else /* _IAR_ */
+  asm("push cc");
+  asm("pop a"); /* Ignore compiler warning, the returned value is in A register */
+#endif /* _COSMIC_*/
+}
+
+/** @defgroup ITC_Group1 ITC configuration and management functions
+ *  @brief   ITC configuration and management functions
+ *
+@verbatim   
+ ===============================================================================
+                  ITC configuration and management functions
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Deinitializes the ITC registers to their default reset value.
+  * @param  None
+  * @retval None
+ */
+void ITC_DeInit(void)
+{
+  ITC->ISPR1 = ITC_SPRX_RESET_VALUE;
+  ITC->ISPR2 = ITC_SPRX_RESET_VALUE;
+  ITC->ISPR3 = ITC_SPRX_RESET_VALUE;
+  ITC->ISPR4 = ITC_SPRX_RESET_VALUE;
+  ITC->ISPR5 = ITC_SPRX_RESET_VALUE;
+  ITC->ISPR6 = ITC_SPRX_RESET_VALUE;
+  ITC->ISPR7 = ITC_SPRX_RESET_VALUE;
+  ITC->ISPR8 = ITC_SPRX_RESET_VALUE;
+}
+
+/**
+  * @brief  Gets the interrupt software priority bits (I1, I0) value from CPU CC register.
+  * @param  None
+  * @retval The interrupt software priority bits value.
+ */
+uint8_t ITC_GetSoftIntStatus(void)
+{
+  return ((uint8_t)(ITC_GetCPUCC() & CPU_SOFT_INT_DISABLED));
+}
+
+/**
+  * @brief  Gets the software priority of the specified interrupt source.
+  * @param  IRQn : Specifies the peripheral interrupt source.
+  * @retval Specifies the software priority of the interrupt source.
+ */
+ITC_PriorityLevel_TypeDef ITC_GetSoftwarePriority(IRQn_TypeDef IRQn)
+{
+  uint8_t Value = 0;
+  uint8_t Mask = 0;
+
+  /* Check function parameters */
+  assert_param(IS_ITC_IRQ(IRQn));
+
+  /* Define the mask corresponding to the bits position in the SPR register */
+  Mask = (uint8_t)(0x03U << ((IRQn % 4U) * 2U));
+
+  switch (IRQn)
+  {
+    case FLASH_IRQn:
+    case DMA1_CHANNEL0_1_IRQn:
+    case DMA1_CHANNEL2_3_IRQn:
+      Value = (uint8_t)(ITC->ISPR1 & Mask); /* Read software priority */
+      break;
+
+    case EXTIE_F_PVD_IRQn:
+#if defined (STM8L15X_MD) || defined (STM8L05X_MD_VL) || defined (STM8AL31_L_MD)
+    case RTC_IRQn:
+    case EXTIB_IRQn:
+    case EXTID_IRQn:
+#elif defined (STM8L15X_LD) || defined (STM8L05X_LD_VL)
+    case RTC_CSSLSE_IRQn:
+    case EXTIB_IRQn:
+    case EXTID_IRQn:
+#elif defined (STM8L15X_HD) || defined (STM8L15X_MDP) || defined (STM8L05X_HD_VL)
+    case RTC_CSSLSE_IRQn:
+    case EXTIB_G_IRQn:
+    case EXTID_H_IRQn:
+#endif  /* STM8L15X_MD */
+      Value = (uint8_t)(ITC->ISPR2 & Mask); /* Read software priority */
+      break;
+
+    case EXTI0_IRQn:
+    case EXTI1_IRQn:
+    case EXTI2_IRQn:
+    case EXTI3_IRQn:
+      Value = (uint8_t)(ITC->ISPR3 & Mask); /* Read software priority */
+      break;
+
+    case EXTI4_IRQn:
+    case EXTI5_IRQn:
+    case EXTI6_IRQn:
+    case EXTI7_IRQn:
+      Value = (uint8_t)(ITC->ISPR4 & Mask); /* Read software priority */
+      break;
+
+#if defined (STM8L15X_LD) || defined (STM8L05X_LD_VL)
+    case SWITCH_CSS_IRQn:
+#else
+    case SWITCH_CSS_BREAK_DAC_IRQn:
+#endif /* STM8L15X_LD */		
+    case ADC1_COMP_IRQn:
+#if defined (STM8L15X_MD) || defined (STM8L05X_MD_VL) || defined (STM8AL31_L_MD)
+    case LCD_IRQn:
+    case TIM2_UPD_OVF_TRG_BRK_IRQn:
+#elif defined (STM8L15X_LD) || defined (STM8L05X_LD_VL)
+    case TIM2_UPD_OVF_TRG_BRK_IRQn:
+#elif defined (STM8L15X_HD) || defined (STM8L15X_MDP) || defined (STM8L05X_HD_VL)
+    case LCD_AES_IRQn:
+    case TIM2_UPD_OVF_TRG_BRK_USART2_TX_IRQn:
+#endif  /* STM8L15X_MD */
+      Value = (uint8_t)(ITC->ISPR5 & Mask); /* Read software priority */
+      break;
+			
+#if !defined (STM8L15X_LD) && !defined (STM8L05X_LD_VL)
+    case TIM1_UPD_OVF_TRG_IRQn:
+#endif /* STM8L15X_LD */		
+#if defined (STM8L15X_MD) || defined (STM8L15X_LD) || defined (STM8L05X_MD_VL) ||\
+ defined (STM8AL31_L_MD) || defined (STM8L05X_LD_VL)
+    case TIM2_CC_IRQn:
+    case TIM3_UPD_OVF_TRG_BRK_IRQn :
+    case TIM3_CC_IRQn:
+#elif defined (STM8L15X_HD) || defined (STM8L15X_MDP) || defined (STM8L05X_HD_VL)
+    case TIM2_CC_USART2_RX_IRQn:
+    case TIM3_UPD_OVF_TRG_BRK_USART3_TX_IRQn :
+    case TIM3_CC_USART3_RX_IRQn:
+#endif  /* STM8L15X_MD */
+      Value = (uint8_t)(ITC->ISPR6 & Mask); /* Read software priority */
+      break;
+			
+#if !defined (STM8L15X_LD) && !defined (STM8L05X_LD_VL)
+    case TIM1_CC_IRQn:
+#endif /* STM8L15X_LD */	
+    case TIM4_UPD_OVF_TRG_IRQn:
+    case SPI1_IRQn:
+#if defined (STM8L15X_MD) || defined (STM8L15X_LD) || defined (STM8L05X_MD_VL) ||\
+ defined (STM8AL31_L_MD) || defined (STM8L05X_LD_VL)
+    case USART1_TX_IRQn:
+#elif defined (STM8L15X_HD) || defined (STM8L15X_MDP) || defined (STM8L05X_HD_VL)
+    case USART1_TX_TIM5_UPD_OVF_TRG_BRK_IRQn:
+#endif  /* STM8L15X_MD || STM8L15X_LD */
+      Value = (uint8_t)(ITC->ISPR7 & Mask); /* Read software priority */
+      break;
+
+#if defined (STM8L15X_MD) || defined (STM8L15X_LD) || defined (STM8L05X_MD_VL) ||\
+ defined (STM8AL31_L_MD) || defined (STM8L05X_LD_VL)
+    case USART1_RX_IRQn:
+    case I2C1_IRQn:
+#elif defined (STM8L15X_HD) || defined (STM8L15X_MDP) || defined (STM8L05X_HD_VL)
+    case USART1_RX_TIM5_CC_IRQn:
+    case I2C1_SPI2_IRQn:
+#endif  /* STM8L15X_MD || STM8L15X_LD*/
+      Value = (uint8_t)(ITC->ISPR8 & Mask); /* Read software priority */
+      break;
+
+    default:
+      break;
+  }
+
+  Value >>= (uint8_t)((IRQn % 4u) * 2u);
+
+  return((ITC_PriorityLevel_TypeDef)Value);
+
+}
+
+/**
+  * @brief  Sets the software priority of the specified interrupt source.
+  * @note   The modification of the software priority is only possible when
+  *         the interrupts are disabled.
+  * @note   The normal behavior is to disable the interrupt before calling
+  *         this function, and re-enable it after.
+  * @note   The priority level 0 cannot be set (see product specification
+  *         for more details).
+  * @param  IRQn : Specifies the peripheral interrupt source.
+  * @param  ITC_PriorityLevel : Specifies the software priority value to set
+  *          This parameter can be one of the following values:
+  *            @arg ITC_PriorityLevel_0: Software priority level 0 (cannot be written)
+  *            @arg ITC_PriorityLevel_1: Software priority level 1
+  *            @arg ITC_PriorityLevel_2: Software priority level 2
+  *            @arg ITC_PriorityLevel_3: Software priority level 3     
+  * @retval None
+  */
+void ITC_SetSoftwarePriority(IRQn_TypeDef IRQn, ITC_PriorityLevel_TypeDef ITC_PriorityLevel)
+{
+  uint8_t Mask = 0;
+  uint8_t NewPriority = 0;
+
+  /* Check function parameters */
+  assert_param(IS_ITC_IRQ(IRQn));
+  assert_param(IS_ITC_PRIORITY(ITC_PriorityLevel));
+
+  /* Check if interrupts are disabled */
+  assert_param(IS_ITC_INTERRUPTS_DISABLED);
+
+  /* Define the mask corresponding to the bits position in the SPR register */
+  /* The mask is reversed in order to clear the 2 bits after more easily */
+  Mask = (uint8_t)(~(uint8_t)(0x03U << ((IRQn % 4U) * 2U)));
+  /* Define the new priority to write */
+  NewPriority = (uint8_t)((uint8_t)(ITC_PriorityLevel) << ((IRQn % 4U) * 2U));
+
+  switch (IRQn)
+  {
+    case FLASH_IRQn:
+    case DMA1_CHANNEL0_1_IRQn:
+    case DMA1_CHANNEL2_3_IRQn:
+      ITC->ISPR1 &= Mask;
+      ITC->ISPR1 |= NewPriority;
+      break;
+
+    case EXTIE_F_PVD_IRQn:
+#if defined (STM8L15X_MD) || defined (STM8L05X_MD_VL) || defined (STM8AL31_L_MD)
+    case RTC_IRQn:
+    case EXTIB_IRQn:
+    case EXTID_IRQn:
+#elif defined (STM8L15X_LD) || defined (STM8L05X_LD_VL)
+    case RTC_CSSLSE_IRQn:
+    case EXTIB_IRQn:
+    case EXTID_IRQn:
+#elif defined (STM8L15X_HD) || defined (STM8L15X_MDP) || defined (STM8L05X_HD_VL)
+    case RTC_CSSLSE_IRQn:
+    case EXTIB_G_IRQn:
+    case EXTID_H_IRQn:
+#endif  /* STM8L15X_MD */
+      ITC->ISPR2 &= Mask;
+      ITC->ISPR2 |= NewPriority;
+      break;
+
+    case EXTI0_IRQn:
+    case EXTI1_IRQn:
+    case EXTI2_IRQn:
+    case EXTI3_IRQn:
+      ITC->ISPR3 &= Mask;
+      ITC->ISPR3 |= NewPriority;
+      break;
+
+    case EXTI4_IRQn:
+    case EXTI5_IRQn:
+    case EXTI6_IRQn:
+    case EXTI7_IRQn:
+      ITC->ISPR4 &= Mask;
+      ITC->ISPR4 |= NewPriority;
+      break;
+#if !defined (STM8L15X_LD) && !defined (STM8L05X_LD_VL)
+    case SWITCH_CSS_BREAK_DAC_IRQn:
+#else
+    case SWITCH_CSS_IRQn:
+#endif /*	STM8L15X_LD	*/
+    case ADC1_COMP_IRQn:
+#if defined (STM8L15X_MD) || defined (STM8L05X_MD_VL) || defined (STM8AL31_L_MD)
+    case LCD_IRQn:
+    case TIM2_UPD_OVF_TRG_BRK_IRQn:
+#elif defined (STM8L15X_LD) || defined (STM8L05X_LD_VL)
+    case TIM2_UPD_OVF_TRG_BRK_IRQn:
+#elif defined (STM8L15X_HD) || defined (STM8L15X_MDP) || defined (STM8L05X_HD_VL)
+    case LCD_AES_IRQn:
+    case TIM2_UPD_OVF_TRG_BRK_USART2_TX_IRQn:
+#endif  /* STM8L15X_MD */
+      ITC->ISPR5 &= Mask;
+      ITC->ISPR5 |= NewPriority;
+      break;
+#if !defined (STM8L15X_LD) && !defined (STM8L05X_LD_VL)
+    case TIM1_UPD_OVF_TRG_IRQn:
+#endif  /* STM8L15X_LD */
+#if defined (STM8L15X_MD) || defined (STM8L15X_LD) || defined (STM8L05X_MD_VL) ||\
+ defined (STM8AL31_L_MD) || defined (STM8L05X_LD_VL)
+    case TIM2_CC_IRQn:
+    case TIM3_UPD_OVF_TRG_BRK_IRQn :
+    case TIM3_CC_IRQn:
+#elif defined (STM8L15X_HD) || defined (STM8L15X_MDP) || defined (STM8L05X_HD_VL)
+    case TIM2_CC_USART2_RX_IRQn:
+    case TIM3_UPD_OVF_TRG_BRK_USART3_TX_IRQn :
+    case TIM3_CC_USART3_RX_IRQn:
+#endif  /* STM8L15X_MD */
+      ITC->ISPR6 &= Mask;
+      ITC->ISPR6 |= NewPriority;
+      break;
+
+#if !defined (STM8L15X_LD) && !defined (STM8L05X_LD_VL)
+    case TIM1_CC_IRQn:
+#endif  /* STM8L15X_LD */
+    case TIM4_UPD_OVF_TRG_IRQn:
+    case SPI1_IRQn:
+#if defined (STM8L15X_MD) || defined (STM8L15X_LD) || defined (STM8L05X_MD_VL) ||\
+ defined (STM8AL31_L_MD) || defined (STM8L05X_LD_VL)
+    case USART1_TX_IRQn:
+#elif defined (STM8L15X_HD) || defined (STM8L15X_MDP) || defined (STM8L05X_HD_VL)
+    case USART1_TX_TIM5_UPD_OVF_TRG_BRK_IRQn:
+#endif  /* STM8L15X_MD */
+      ITC->ISPR7 &= Mask;
+      ITC->ISPR7 |= NewPriority;
+      break;
+
+#if defined (STM8L15X_MD) || defined (STM8L15X_LD) || defined (STM8L05X_MD_VL) ||\
+ defined (STM8AL31_L_MD) || defined (STM8L05X_LD_VL)
+    case USART1_RX_IRQn:
+    case I2C1_IRQn:
+#elif defined (STM8L15X_HD) || defined (STM8L15X_MDP) || defined (STM8L05X_HD_VL)
+    case USART1_RX_TIM5_CC_IRQn:
+    case I2C1_SPI2_IRQn:
+#endif  /* STM8L15X_MD */
+      ITC->ISPR8 &= Mask;
+      ITC->ISPR8 |= NewPriority;
+      break;
+
+    default:
+      break;
+  }
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_iwdg.c b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_iwdg.c
new file mode 100755
index 0000000..4a44a7f
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_iwdg.c
@@ -0,0 +1,217 @@
+/**
+  ********************************************************************************
+  * @file    stm8l15x_iwdg.c
+  * @author  MCD Application Team
+  * @version V1.6.0
+  * @date    28-June-2013
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Independent watchdog (IWDG) peripheral:           
+  *           - Prescaler and Counter configuration
+  *           - IWDG activation
+  *
+  *  @verbatim  
+  *  
+  *          ===================================================================
+  *                                     IWDG features
+  *          ===================================================================
+  *    
+  *          The IWDG can be started by either software or hardware (configurable
+  *          through option byte).
+  *            
+  *          The IWDG is clocked by its own dedicated low-speed clock (LSI) and
+  *          thus stays active even if the main clock fails.
+  *          Once the IWDG is started, the LSI is forced ON and cannot be disabled
+  *          (LSI cannot be disabled too), and the counter starts counting down from 
+  *          the reset value of 0xFF. When it reaches the end of count value (0x00)
+  *          a system reset is generated.
+  *          The IWDG counter should be reloaded at regular intervals to prevent
+  *          an MCU reset.
+  *                           
+  *          The IWDG is implemented in the VDD voltage domain that is still functional
+  *          in Halt and Active Halt mode depending on the configuration of the IWDG_HALT
+  *          option byte. (IWDG reset can wake-up from Halt).          
+  *            
+  *          IWDGF flag in RST_SR register can be used to inform when a IWDG
+  *          reset occurs.
+  *            
+  *          Min-max timeout value @38KHz (LSI): 0.10 ms / ~1.724s
+  *          The IWDG timeout may vary due to LSI frequency dispersion. STM8L15x
+  *          devices provide the capability to measure the LSI frequency (LSI clock
+  *          connected internally to TIM2 CH1 input capture). The measured value
+  *          can be used to have an IWDG timeout with an acceptable accuracy. 
+  *          For more information, please refer to the STM8L15x Reference manual
+  *          
+  *                            
+  *          ===================================================================
+  *                                 How to use this driver
+  *          ===================================================================
+  *          1. Enable write access to IWDG_PR and IWDG_RLR registers using
+  *             IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable) function
+  *               
+  *          2. Configure the IWDG prescaler using IWDG_SetPrescaler() function
+  *            
+  *          3. Configure the IWDG counter value using IWDG_SetReload() function.
+  *             This value will be loaded in the IWDG counter each time the counter
+  *             is reloaded, then the IWDG will start counting down from this value.
+  *            
+  *          4. Start the IWDG using IWDG_Enable() function, when the IWDG is used
+  *             in software mode (no need to enable the LSI, it will be enabled
+  *             by hardware)
+  *             
+  *          5. Then the application program must reload the IWDG counter at regular
+  *             intervals during normal operation to prevent an MCU reset, using
+  *             IWDG_ReloadCounter() function.      
+  *          
+  *  @endverbatim
+  *    
+  ******************************************************************************
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm8l15x_iwdg.h"
+
+/** @addtogroup STM8L15x_StdPeriph_Driver
+  * @{
+  */
+  
+/** @defgroup IWDG 
+  * @brief IWDG driver modules
+  * @{
+  */ 
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup IWDG_Private_Functions
+  * @{
+  */
+
+/** @defgroup IWDG_Group1 Prescaler and Counter configuration functions
+ *  @brief   Prescaler and Counter configuration functions
+ *
+@verbatim   
+ ===============================================================================
+                  Prescaler and Counter configuration functions
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Enables or disables write access to IWDG_PR and IWDG_RLR registers.
+  * @param  IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers.
+  *          This parameter can be one of the following values:
+  *            @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers
+  *            @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers
+  * @retval None
+  */
+void IWDG_WriteAccessCmd(IWDG_WriteAccess_TypeDef IWDG_WriteAccess)
+{
+  /* Check the parameters */
+  assert_param(IS_IWDG_WRITE_ACCESS_MODE(IWDG_WriteAccess));
+  IWDG->KR = IWDG_WriteAccess; /* Write Access */
+}
+
+/**
+  * @brief  Sets IWDG Prescaler value.
+  * @param  IWDG_Prescaler: specifies the IWDG Prescaler value.
+  *          This parameter can be one of the following values:
+  *            @arg IWDG_Prescaler_4: IWDG prescaler set to 4
+  *            @arg IWDG_Prescaler_8: IWDG prescaler set to 8
+  *            @arg IWDG_Prescaler_16: IWDG prescaler set to 16
+  *            @arg IWDG_Prescaler_32: IWDG prescaler set to 32
+  *            @arg IWDG_Prescaler_64: IWDG prescaler set to 64
+  *            @arg IWDG_Prescaler_128: IWDG prescaler set to 128
+  *            @arg IWDG_Prescaler_256: IWDG prescaler set to 256
+  * @retval None
+  */
+void IWDG_SetPrescaler(IWDG_Prescaler_TypeDef IWDG_Prescaler)
+{
+  /* Check the parameters */
+  assert_param(IS_IWDG_PRESCALER_VALUE(IWDG_Prescaler));
+  IWDG->PR = IWDG_Prescaler;
+}
+
+/**
+  * @brief  Sets IWDG Reload value.
+  * @note   Write access should be enabled
+  * @param  IWDG_Reload : Reload register value.
+  *         This parameter must be a number between 0 and 0xFF.
+  * @retval None
+  */
+void IWDG_SetReload(uint8_t IWDG_Reload)
+{
+  IWDG->RLR = IWDG_Reload;
+}
+
+/**
+  * @brief  Reloads IWDG counter with value defined in the reload register
+  *         (write access to IWDG_PR and IWDG_RLR registers disabled).
+  * @param  None
+  * @retval None
+  */
+void IWDG_ReloadCounter(void)
+{
+  IWDG->KR = IWDG_KEY_REFRESH;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_Group2 IWDG activation function
+ *  @brief   IWDG activation function 
+ *
+@verbatim   
+ ===============================================================================
+                          IWDG activation function
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).
+  * @param  None
+  * @retval None
+  */
+void IWDG_Enable(void)
+{
+  IWDG->KR = IWDG_KEY_ENABLE;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
\ No newline at end of file
diff --git a/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_lcd.c b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_lcd.c
new file mode 100755
index 0000000..3cc22cc
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_lcd.c
@@ -0,0 +1,629 @@
+/**
+  ******************************************************************************
+  * @file    stm8l15x_lcd.c
+  * @author  MCD Application Team
+  * @version V1.6.0
+  * @date    28-June-2013
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the LCD controller (LCD) peripheral:           
+  *           - Initialization and configuration
+  *           - LCD RAM memory write
+  *           - Interrupts and flags management   
+  *           
+  *  @verbatim
+  *      
+  *          ===================================================================      
+  *                                    LCD Clock
+  *          ===================================================================    
+  *          LCD has tow clock sources:
+  *            - RTCCLK divided by 2 used to generate LCD frame rate
+  *            - LCDCLK to used for LCD registers read/write access
+  *                   
+  *          To configure the RTCCLK/LCDCLK, proceed as follows:
+  *            - Enable RTC clock using CLK_PeripheralClockConfig(CLK_Peripheral_RTC, ENABLE)
+  *              function
+  *            - Enable LCD clock using CLK_PeripheralClockConfig(CLK_Peripheral_LCD, ENABLE)
+  *              function  
+  *            - Select the RTC clock source using the CLK_RTCClockConfig() function.    
+  *            
+  *          ===================================================================      
+  *                                  LCD and low power modes
+  *          =================================================================== 
+  *          The LCD remains active during Active-halt, Wait, Low power run and 
+  *          Low power wait modes unless disabled
+  *              
+  *          ===================================================================
+  *                                 How to use this driver
+  *          =================================================================== 
+  *          1. Enable RTC clock using CLK_PeripheralClockConfig(CLK_Peripheral_RTC, ENABLE) function 
+  *            
+  *          2. Enable LCD clock using CLK_PeripheralClockConfig(CLK_Peripheral_LCD, ENABLE) function
+  *            
+  *          3. Select the RTC clock source using the CLK_RTCClockConfig() function. 
+  *          
+  *          4. Configure the LCD prescaler, divider, duty, bias and voltage source
+  *             using LCD_Init() function     
+  *            
+  *          5. Call the LCD_PortMaskConfig() function to assign the unused SEGx
+  *             (segment) and COMx (common) pins as standard general purpose IOs
+  *
+  *          6. Optionally you can enable/configure:
+  *              -  LCD High Drive using the LCD_HighDriveCmd() function
+  *              -  LCD Pulse ON Duration using the LCD_PulseOnDurationConfig() function
+  *              -  LCD Dead Time using the LCD_DeadTimeConfig() function  
+  *              -  The LCD Blink mode and frequency using the LCD_BlinkConfig() function
+  *              -  The LCD Contrast using the LCD_ContrastConfig() function  
+  *
+  *          7. Call the LCD_Cmd() to enable the LCD controller
+  *          
+  *          8. Write to the LCD RAM memory using the LCD_WriteRAM() function.
+  *          
+  *  @endverbatim
+  *           
+  ******************************************************************************
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ****************************************************************************** 
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm8l15x_lcd.h"
+
+/** @addtogroup STM8L15x_StdPeriph_Driver
+  * @{
+  */
+  
+/** @defgroup LCD 
+  * @brief LCD driver modules
+  * @{
+  */
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup LCD_Private_Functions
+  * @{
+  */
+
+/** @defgroup LCD_Group1 Initialization and Configuration functions
+ *  @brief   Initialization and Configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+                    Initialization and Configuration functions
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Deinitializes the LCD Controller registers to their default reset values.
+  * @param  None
+  * @retval None
+  */
+void LCD_DeInit(void)
+{
+  uint8_t counter = 0;
+
+  LCD->CR1 = LCD_CR1_RESET_VALUE;
+  LCD->CR2 = LCD_CR2_RESET_VALUE;
+  LCD->CR3 = LCD_CR3_RESET_VALUE;
+  LCD->FRQ = LCD_FRQ_RESET_VALUE;
+
+  for (counter = 0;counter < 0x05; counter++)
+  {
+    LCD->PM[counter] = LCD_PM_RESET_VALUE;
+  }
+
+  for (counter = 0;counter < 0x16; counter++)
+  {
+    LCD->RAM[counter] =  LCD_RAM_RESET_VALUE;
+  }
+
+  LCD->CR4 = LCD_CR4_RESET_VALUE;
+
+}
+
+/**
+  * @brief  Initializes the LCD according to the specified parameters.
+  * @param  LCD_CLKPrescalerDiv : LCD clock prescaler 
+  *          This parameter can be one of the following values:
+  *            @arg LCD_Prescaler_1: CLKprescaler = ClKinput 
+  *            @arg LCD_Prescaler_2: CLKprescaler = ClKinput/2 
+  *            @arg LCD_Prescaler_4: CLKprescaler = ClKinput/4
+  *            @arg LCD_Prescaler_8: CLKprescaler = ClKinput/8 
+  *            @arg LCD_Prescaler_16: CLKprescaler = ClKinput/16
+  *            @arg LCD_Prescaler_32: CLKprescaler = ClKinput/32
+  *            @arg LCD_Prescaler_64: CLKprescaler = ClKinput/64 
+  *            @arg LCD_Prescaler_128: CLKprescaler = ClKinput/128 
+  *            @arg LCD_Prescaler_256: CLKprescaler = ClKinput/256 
+  *            @arg LCD_Prescaler_512: CLKprescaler = ClKinput/512 
+  *            @arg LCD_Prescaler_1024: CLKprescaler = ClKinput/1024 
+  *            @arg LCD_Prescaler_2048: CLKprescaler = ClKinput/2048 
+  *            @arg LCD_Prescaler_4096: CLKprescaler = ClKinput/4096 
+  *            @arg LCD_Prescaler_8192: CLKprescaler = ClKinput/8192 
+  *            @arg LCD_Prescaler_16384: CLKprescaler = ClKinput/16384 
+  *            @arg LCD_Prescaler_32768: CLKprescaler = ClKinput/32768              
+  * @param  LCD_Divider : LCD clock divider
+  *          This parameter can be one of the following values:
+  *            @arg LCD_Divider_16: LCD frequency = CLKprescaler/16 
+  *            @arg LCD_Divider_17: LCD frequency = CLKprescaler/17
+  *            @arg LCD_Divider_18: LCD frequency = CLKprescaler/18
+  *            @arg LCD_Divider_19: LCD frequency = CLKprescaler/19
+  *            @arg LCD_Divider_20: LCD frequency = CLKprescaler/20
+  *            @arg LCD_Divider_21: LCD frequency = CLKprescaler/21
+  *            @arg LCD_Divider_22: LCD frequency = CLKprescaler/22
+  *            @arg LCD_Divider_23: LCD frequency = CLKprescaler/23
+  *            @arg LCD_Divider_24: LCD frequency = CLKprescaler/24
+  *            @arg LCD_Divider_25: LCD frequency = CLKprescaler/25
+  *            @arg LCD_Divider_26: LCD frequency = CLKprescaler/26
+  *            @arg LCD_Divider_27: LCD frequency = CLKprescaler/27
+  *            @arg LCD_Divider_28: LCD frequency = CLKprescaler/28
+  *            @arg LCD_Divider_29: LCD frequency = CLKprescaler/29
+  *            @arg LCD_Divider_30: LCD frequency = CLKprescaler/30
+  *            @arg LCD_Divider_31: LCD frequency = CLKprescaler/31
+  * @param  LCD_Duty : LCD duty
+  *          This parameter can be one of the following values:
+  *            @arg LCD_Duty_Static: Static duty 
+  *            @arg LCD_Duty_1_2: 1/2 duty
+  *            @arg LCD_Duty_1_3: 1/3 duty
+  *            @arg LCD_Duty_1_4: 1/4 duty
+  *            @arg LCD_Duty_1_8: 1/8 duty   
+  * @param  LCD_Bias : LCD bias
+  *          This parameter can be one of the following values:
+  *            @arg LCD_Bias_1_4: 1/4 bias
+  *            @arg LCD_Bias_1_3: 1/3 bias
+  *            @arg LCD_Bias_1_2: 1/2 bias
+  * @param  LCD_VoltageSource : LCD voltage source
+  *          This parameter can be one of the following values:
+  *            @arg LCD_VoltageSource_Internal: Internal voltage source
+  *            @arg LCD_VoltageSource_External: External voltage source
+  * @retval None
+  */
+void LCD_Init(LCD_Prescaler_TypeDef LCD_Prescaler, LCD_Divider_TypeDef LCD_Divider,
+              LCD_Duty_TypeDef LCD_Duty, LCD_Bias_TypeDef LCD_Bias,
+              LCD_VoltageSource_TypeDef LCD_VoltageSource)
+{
+  /* Check function parameters */
+  assert_param(IS_LCD_CLOCK_PRESCALER(LCD_Prescaler));
+  assert_param(IS_LCD_CLOCK_DIVIDER(LCD_Divider));
+  assert_param(IS_LCD_DUTY(LCD_Duty));
+  assert_param(IS_LCD_BIAS(LCD_Bias));
+  assert_param(IS_LCD_VOLTAGE_SOURCE(LCD_VoltageSource));
+
+  LCD->FRQ &= (uint8_t)(~LCD_FRQ_PS);     /* Clear the prescaler bits */
+  LCD->FRQ |= LCD_Prescaler;
+
+  LCD->FRQ &= (uint8_t)(~LCD_FRQ_DIV);     /* Clear the divider bits */
+  LCD->FRQ |= LCD_Divider;
+
+  /* Configure the Duty cycle */
+  LCD->CR1 &= (uint8_t)(~LCD_CR1_DUTY);    /* Clear the duty bits */
+  LCD->CR4 &= (uint8_t)(~LCD_CR4_DUTY8);   /* Clear the DUTY8 bit */
+
+  if (LCD_Duty == LCD_Duty_1_8)
+  {
+    LCD->CR4 |= (uint8_t)((uint8_t)((uint8_t)LCD_Duty & (uint8_t)0xF0) >> 4);
+  }
+  else
+  {
+    LCD->CR1 |= (uint8_t)((uint8_t)LCD_Duty & (uint8_t)0x0F);
+  }
+
+  /* Configure the Bias */
+  LCD->CR1 &= (uint8_t)(~LCD_CR1_B2);      /* Clear the B2 bit */
+  LCD->CR4 &= (uint8_t)(~LCD_CR4_B4);      /* Clear the B4 bit */
+
+  if (LCD_Bias == LCD_Bias_1_4)
+  {
+    LCD->CR1 |= (uint8_t)((uint8_t)LCD_Bias & (uint8_t)0x0F);
+    LCD->CR4 |= (uint8_t)((uint8_t)((uint8_t)LCD_Bias & (uint8_t)0xF0) >> 4);
+  }
+  else
+  {
+    LCD->CR1 |= (uint8_t)((uint8_t)LCD_Bias & (uint8_t)0x0F);
+  }
+
+  LCD->CR2 &= (uint8_t)(~LCD_CR2_VSEL);    /* Clear the voltage source bit */
+  LCD->CR2 |= LCD_VoltageSource;
+
+}
+
+/**
+  * @brief  Configures the LCD Port Mask.
+  * @param  LCD_PortMaskRegister: The LCD register index in the port mask matrix.
+  *          This parameter can be one of the following values:
+  *            @arg LCD_PortMaskRegister_0: PortMask Register 0  
+  *            @arg LCD_PortMaskRegister_1: PortMask Register 1
+  *            @arg LCD_PortMaskRegister_2: PortMask Register 2
+  *            @arg LCD_PortMaskRegister_3: PortMask Register 3
+  *            @arg LCD_PortMaskRegister_4: PortMask Register 4
+  *            @arg LCD_PortMaskRegister_5: PortMask Register 5        
+  * @param  LCD_Mask : Value to be written
+  * @retval None
+  */
+void LCD_PortMaskConfig(LCD_PortMaskRegister_TypeDef LCD_PortMaskRegister, uint8_t LCD_Mask)
+{
+  /* Check function parameters */
+  assert_param(IS_LCD_PORT_MASK(LCD_PortMaskRegister));
+
+  /* Copy data bytes to Port mask register */
+  LCD->PM[LCD_PortMaskRegister] =  LCD_Mask;
+
+}
+
+/**
+  * @brief  Enables or disables the LCD Controller.
+  * @param  NewState: new state of the LCD peripheral.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  * @retval None
+  */
+void LCD_Cmd(FunctionalState NewState)
+{
+  /* Check function parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    LCD->CR3 |= LCD_CR3_LCDEN; /* Enable the LCD peripheral*/
+  }
+  else
+  {
+    LCD->CR3 &= (uint8_t)(~LCD_CR3_LCDEN); /* Disable the LCD peripheral*/
+  }
+}
+
+/**
+  * @brief  Enables or disables the low resistance divider. Displays with high 
+  *         internal resistance may need a longer drive time to achieve 
+  *         satisfactory contrast. This function is useful in this case if some 
+  *         additional power consumption can be tolerated.
+  * @note   When this mode is enabled, the PulseOn Duration (PON) have to be 
+  *         programmed to 1/CK_PS (LCD_PulseOnDuration_1).    
+  * @param  NewState: new state of the low resistance divider.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void LCD_HighDriveCmd(FunctionalState NewState)
+{
+  /* Check function parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    LCD->CR2 |= LCD_CR2_HD; /* Permanently enable low resistance divider */
+  }
+  else
+  {
+    LCD->CR2 &= (uint8_t)(~LCD_CR2_HD); /* Permanently disable low resistance divider */
+  }
+}
+
+/**
+  * @brief  Configures the LCD pulses on duration.
+  * @param  LCD_PulseOnDuration: specifies the LCD pulse on duration in terms of 
+  *         CLKprescaler (prescaled LCD clock period) pulses.
+  *          This parameter can be one of the following values:
+  *            @arg LCD_PulseOnDuration_0: 0 pulse
+  *            @arg LCD_PulseOnDuration_1: Pulse ON duration = 1/CLKprescaler
+  *            @arg LCD_PulseOnDuration_2: Pulse ON duration = 2/CLKprescaler
+  *            @arg LCD_PulseOnDuration_3: Pulse ON duration = 3/CLKprescaler
+  *            @arg LCD_PulseOnDuration_4: Pulse ON duration = 4/CLKprescaler
+  *            @arg LCD_PulseOnDuration_5: Pulse ON duration = 5/CLKprescaler
+  *            @arg LCD_PulseOnDuration_6: Pulse ON duration = 6/CLKprescaler
+  *            @arg LCD_PulseOnDuration_7: Pulse ON duration = 7/CLKprescaler
+  * @retval None
+  */
+void LCD_PulseOnDurationConfig(LCD_PulseOnDuration_TypeDef LCD_PulseOnDuration)
+{
+  /* Check function parameters */
+  assert_param(IS_LCD_PULSE_DURATION(LCD_PulseOnDuration));
+
+  LCD->CR2 &= (uint8_t)(~LCD_CR2_PON); /* Clear the pulses on duration bits */
+  LCD->CR2 |= LCD_PulseOnDuration;
+}
+
+/**
+  * @brief  Configures the LCD dead time.
+  * @param  LCD_DeadTime: specifies the LCD dead time.
+  *          This parameter can be one of the following values:
+  *            @arg LCD_DeadTime_0: No dead Time
+  *            @arg LCD_DeadTime_1: One Phase between different couple of Frame
+  *            @arg LCD_DeadTime_2: Two Phase between different couple of Frame
+  *            @arg LCD_DeadTime_3: Three Phase between different couple of Frame
+  *            @arg LCD_DeadTime_4: Four Phase between different couple of Frame
+  *            @arg LCD_DeadTime_5: Five Phase between different couple of Frame
+  *            @arg LCD_DeadTime_6: Six Phase between different couple of Frame 
+  *            @arg LCD_DeadTime_7: Seven Phase between different couple of Frame
+  * @retval None
+  */
+void LCD_DeadTimeConfig(LCD_DeadTime_TypeDef LCD_DeadTime)
+{
+  /* Check function parameters */
+  assert_param(IS_LCD_DEAD_TIME(LCD_DeadTime));
+
+  LCD->CR3 &= (uint8_t)(~LCD_CR3_DEAD);  /* Clear the dead time bits  */
+
+  LCD->CR3 |= LCD_DeadTime;
+
+}
+
+/**
+  * @brief  Configures the LCD Blink mode and Blink frequency.
+  * @param  LCD_BlinkMode: specifies the LCD blink mode.
+  *          This parameter can be one of the following values:
+  *            @arg LCD_BlinkMode_Off:           Blink disabled
+  *            @arg LCD_BlinkMode_SEG0_COM0:     Blink enabled on SEG[0], COM[0] (1 pixel)
+  *            @arg LCD_BlinkMode_SEG0_AllCOM:   Blink enabled on SEG[0], all COM (up to 8 
+  *                                       pixels according to the programmed duty)
+  *            @arg LCD_BlinkMode_AllSEG_AllCOM: Blink enabled on all SEG and all COM 
+  *                                       (all pixels)
+  * @param  LCD_BlinkFrequency: specifies the LCD blink frequency.
+  *          This parameter can be one of the following values:
+  *            @arg LCD_BlinkFrequency_Div8:    The Blink frequency = fLcd/8
+  *            @arg LCD_BlinkFrequency_Div16:   The Blink frequency = fLcd/16
+  *            @arg LCD_BlinkFrequency_Div32:   The Blink frequency = fLcd/32
+  *            @arg LCD_BlinkFrequency_Div64:   The Blink frequency = fLcd/64 
+  *            @arg LCD_BlinkFrequency_Div128:  The Blink frequency = fLcd/128
+  *            @arg LCD_BlinkFrequency_Div256:  The Blink frequency = fLcd/256
+  *            @arg LCD_BlinkFrequency_Div512:  The Blink frequency = fLcd/512
+  *            @arg LCD_BlinkFrequency_Div1024: The Blink frequency = fLcd/1024
+  * @retval None
+  */
+void LCD_BlinkConfig(LCD_BlinkMode_TypeDef LCD_BlinkMode, LCD_BlinkFrequency_TypeDef LCD_BlinkFrequency)
+{
+  /* Check function parameters */
+  assert_param(IS_LCD_BLINK_MODE(LCD_BlinkMode));
+  assert_param(IS_LCD_BLINK_FREQUENCY(LCD_BlinkFrequency));
+
+  LCD->CR1 &= (uint8_t)(~LCD_CR1_BLINK); /* Clear the blink mode bits */
+  LCD->CR1 |= LCD_BlinkMode; /* Config the LCD Blink Mode */
+
+  LCD->CR1 &= (uint8_t)(~LCD_CR1_BLINKF); /* Clear the blink frequency bits */
+  LCD->CR1 |= LCD_BlinkFrequency; /* Config the LCD Blink Frequency */
+
+}
+
+/**
+  * @brief  Configures the LCD Contrast.
+  * @param  LCD_Contrast: specifies the LCD Contrast.
+  *          This parameter can be one of the following values:
+  *            @arg LCD_Contrast_Level_0: Medium Density / High Density Maximum Voltage = 2.60V / 2.60V 
+  *            @arg LCD_Contrast_Level_1: Medium Density / High Density Maximum Voltage = 2.70V / 2.73V
+  *            @arg LCD_Contrast_Level_2: Medium Density / High Density Maximum Voltage = 2.80V / 2.86V
+  *            @arg LCD_Contrast_Level_3: Medium Density / High Density Maximum Voltage = 2.90V / 2.99V
+  *            @arg LCD_Contrast_Level_4: Medium Density / High Density Maximum Voltage = 3.00V / 3.12V
+  *            @arg LCD_Contrast_Level_5: Medium Density / High Density Maximum Voltage = 3.10V / 3.25V
+  *            @arg LCD_Contrast_Level_6: Medium Density / High Density Maximum Voltage = 3.20V / 3.38V
+  *            @arg LCD_Contrast_Level_7: Medium Density / High Density Maximum Voltage = 3.30V / 3.51V
+  * @retval None
+  */
+void LCD_ContrastConfig(LCD_Contrast_TypeDef LCD_Contrast)
+{
+  /* Check function parameters */
+  assert_param(IS_LCD_CONTRAST(LCD_Contrast));
+
+  LCD->CR2 &= (uint8_t)(~LCD_CR2_CC); /* Clear the contrast bits  */
+  LCD->CR2 |= LCD_Contrast; /* Select the maximum voltage value Vlcd */
+
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LCD_Group2  LCD RAM memory write functions
+ *  @brief    LCD RAM memory write functions 
+ *
+@verbatim   
+ ===============================================================================
+                           LCD RAM memory write functions
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Writes a word in the specific LCD RAM.
+  * @param  LCD_RAMRegister: specifies the LCD Contrast.
+  *          This parameter can be one of the following values:
+  *            @arg LCD_RAMRegister_0: LCD RAM Register 0
+  *            @arg LCD_RAMRegister_1: LCD RAM Register 1
+  *            @arg LCD_RAMRegister_2: LCD RAM Register 2
+  *            @arg LCD_RAMRegister_3: LCD RAM Register 3
+  *            @arg LCD_RAMRegister_4: LCD RAM Register 4
+  *            @arg LCD_RAMRegister_5: LCD RAM Register 5
+  *            @arg LCD_RAMRegister_6: LCD RAM Register 6 
+  *            @arg LCD_RAMRegister_7: LCD RAM Register 7  
+  *            @arg LCD_RAMRegister_8: LCD RAM Register 8
+  *            @arg LCD_RAMRegister_9: LCD RAM Register 9
+  *            @arg LCD_RAMRegister_10: LCD RAM Register 10
+  *            @arg LCD_RAMRegister_11: LCD RAM Register 11
+  *            @arg LCD_RAMRegister_12: LCD RAM Register 12 
+  *            @arg LCD_RAMRegister_13: LCD RAM Register 13 
+  *            @arg LCD_RAMRegister_14: LCD RAM Register 14 
+  *            @arg LCD_RAMRegister_15: LCD RAM Register 15
+  *            @arg LCD_RAMRegister_15: LCD RAM Register 16 
+  *            @arg LCD_RAMRegister_15: LCD RAM Register 17 
+  *            @arg LCD_RAMRegister_15: LCD RAM Register 18 
+  *            @arg LCD_RAMRegister_15: LCD RAM Register 19 
+  *            @arg LCD_RAMRegister_15: LCD RAM Register 20 
+  *            @arg LCD_RAMRegister_15: LCD RAM Register 21             
+  * @param  LCD_Data: specifies LCD Data Value to be written.
+  * @retval None
+  */
+void LCD_WriteRAM(LCD_RAMRegister_TypeDef LCD_RAMRegister, uint8_t LCD_Data)
+{
+  /* Check function parameters */
+  assert_param(IS_LCD_RAM_REGISTER(LCD_RAMRegister));
+
+  /* Copy data bytes to RAM register */
+  LCD->RAM[LCD_RAMRegister] =  LCD_Data;
+
+}
+
+/**
+  * @brief  Select the LCD page where the data will be written.
+  * @param  LCD_Page: The accessed LCD page.
+  *          This parameter can be one of the following values:
+  *            @arg LCD_PageSelection_FirstPage: The LCD RAM is selected as the first page
+  *            @arg LCD_PageSelection_SecondPage: The LCD RAM is selected as the second page  
+  * @retval None
+  */
+void LCD_PageSelect(LCD_PageSelection_TypeDef LCD_PageSelection)
+{
+  /* Check function parameters */
+  assert_param(IS_LCD_PAGE_SELECT(LCD_PageSelection));
+
+  LCD->CR4 &= (uint8_t)(~LCD_CR4_PAGECOM); /* Clear the PAGE COM bit */
+  LCD->CR4 |= LCD_PageSelection; /* Select the LCD page */
+
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LCD_Group3 Interrupts and flags management functions
+ *  @brief   Interrupts and flags management functions 
+ *
+@verbatim   
+ ===============================================================================
+                   Interrupts and flags management functions
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+  
+  
+/**
+  * @brief  Enables or disables the start of frame interrupt.
+  * @param NewState: new state of the specified LCD interrupts.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void LCD_ITConfig(FunctionalState NewState)
+{
+  /* Check function parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    LCD->CR3 |= LCD_CR3_SOFIE; /* Enable interrupt*/
+  }
+  else
+  {
+    LCD->CR3 &= (uint8_t)(~LCD_CR3_SOFIE); /* Disable interrupt*/
+  }
+
+}
+
+/**
+  * @brief  Checks whether the LCD start of new frame flag is set or not.
+  * @retval The new state of the start of new frame flag.
+  *   This returned value can be: SET or RESET.   
+  */
+FlagStatus LCD_GetFlagStatus(void)
+{
+  FlagStatus status = RESET;
+
+  /* Check the status of the start of new frame LCD flag */
+  if ((LCD->CR3 & (uint8_t)LCD_CR3_SOF) != (uint8_t)RESET)
+  {
+    status = SET; /* Flag is set */
+  }
+  else
+  {
+    status = RESET; /* Flag is reset*/
+  }
+  /* Return the FLAG status */
+  return status;
+
+}
+
+/**
+  * @brief  Clears the start of frame LCD flag.
+  * @param  None
+  * @retval None
+  */
+void LCD_ClearFlag(void)
+{
+  /* Clear the flag bit */
+  LCD->CR3 |= (uint8_t)(LCD_CR3_SOFC);
+
+}
+
+/**
+  * @brief  Checks whether the start of frame interrupt has occurred or not.
+  * @param  None
+  * @retval The new state of the start of new frame interrupt.
+  *   This returned value can be: SET or RESET.   
+  */
+ITStatus LCD_GetITStatus(void)
+{
+  ITStatus pendingbitstatus = RESET;
+  uint8_t enablestatus = 0;
+
+  enablestatus = (uint8_t)((uint8_t)LCD->CR3 & LCD_CR3_SOFIE);
+  /* Check the status of the start of frame interrupt */
+  if (((LCD->CR3 & LCD_CR3_SOF) != RESET) && enablestatus)
+  {
+    /* ITPENDINGBIT is set */
+    pendingbitstatus = SET;
+  }
+  else
+  {
+    /* ITPENDINGBIT is reset */
+    pendingbitstatus = RESET;
+  }
+  /* Return the ITPENDINGBIT status */
+  return  pendingbitstatus;
+
+}
+
+/**
+  * @brief  Clears the start of frame interrupt pending bits.
+  * @param  None
+  * @retval None
+  */
+void LCD_ClearITPendingBit(void)
+{
+  /* Clear the flag bit */
+  LCD->CR3 |= (uint8_t)(LCD_CR3_SOFC);
+
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_pwr.c b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_pwr.c
new file mode 100755
index 0000000..e656ae7
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_pwr.c
@@ -0,0 +1,355 @@
+/**
+  ******************************************************************************
+  * @file    stm8l15x_pwr.c
+  * @author  MCD Application Team
+  * @version V1.6.0
+  * @date    28-June-2013
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Power Controller (PWR) peripheral:           
+  *           - PVD configuration
+  *           - Ultra Low Power mode configuration
+  *           - Interrupts and flags management
+  *               
+  ******************************************************************************
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ****************************************************************************** 
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm8l15x_pwr.h"
+
+/** @addtogroup STM8L15x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup PWR 
+  * @brief PWR driver modules
+  * @{
+  */
+  
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup PWR_Private_Functions
+  * @{
+  */
+
+/** @defgroup PWR_Group1 PVD configuration functions
+ *  @brief   PVD configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+                           PVD configuration functions
+ ===============================================================================  
+
+ - The PVD is used to monitor the VDD power supply by comparing it to a threshold
+   selected by the PVD Level (PLS[2:0] bits in the PWR_CSR1).
+ - The PVD can use an external input analog voltage (PVD_IN) which is compared 
+   internally to VREFINT. The PVD_IN (PE6) has to be configured in Analog mode 
+   when PWR_PVDLevel_PVDIn is selected (PLS[2:0] = 111).
+ - A PVDO flag is available to indicate if VDD/VDDA is higher or lower than the 
+   PVD threshold. An interrupt is generated in case enabled for PVD. 
+ - The PVD interrup event has the capability to wake up the CPU from Halt/Active Halt modes.
+
+@endverbatim
+  * @{
+  */
+    
+/**
+  * @brief  Deinitializes the PWR peripheral registers to their default reset values.
+  * @param  None
+  * @retval None
+  */
+void PWR_DeInit(void)
+{
+  PWR->CSR1 = PWR_CSR1_PVDIF;
+  PWR->CSR2 = PWR_CSR2_RESET_VALUE;
+}
+
+/**
+  * @brief  Configures the voltage threshold detected by the Power Voltage Detector(PVD).
+  * @param  PWR_PVDLevel: specifies the PVD detection level
+  *          This parameter can be one of the following values:
+  *            @arg PWR_PVDLevel_1V85: PVD detection level set to 1.85V
+  *            @arg PWR_PVDLevel_2V05: PVD detection level set to 2.05V
+  *            @arg PWR_PVDLevel_2V26: PVD detection level set to 2.26V
+  *            @arg PWR_PVDLevel_2V45: PVD detection level set to 2.45V
+  *            @arg PWR_PVDLevel_2V65: PVD detection level set to 2.65V
+  *            @arg PWR_PVDLevel_2V85: PVD detection level set to 2.85V
+  *            @arg PWR_PVDLevel_3V05: PVD detection level set to 3.05V
+  *            @arg PWR_PVDLevel_PVDIn: External input analog voltage (Compare internally to VREFINT)
+  * @retval None
+  */
+void PWR_PVDLevelConfig(PWR_PVDLevel_TypeDef PWR_PVDLevel)
+{
+  /* Check the parameters */
+  assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
+
+  /* Clear the PVD level */
+  PWR->CSR1 &= (uint8_t)(~PWR_CSR1_PLS);
+
+  /* Configure the PVD level */
+  PWR->CSR1 |= PWR_PVDLevel;
+
+}
+
+/**
+  * @brief  Enables or disables the Power Voltage Detector(PVD).
+  * @param  NewState: new state of the PVD.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void PWR_PVDCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the PWR PVD */
+    PWR->CSR1 |= PWR_CSR1_PVDE;
+  }
+  else
+  {
+    /* Disable the PWR PVD */
+    PWR->CSR1 &= (uint8_t)(~PWR_CSR1_PVDE);
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Group2 Ultra Low Power mode configuration functions
+ *  @brief   Ultra Low Power mode configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+                    Ultra Low Power mode configuration functions
+ ===============================================================================  
+
+ - The internal voltage reference consumption is not negligible, in particular 
+   in Halt and Active Halt modes. To reduce power consumption, use the PWR_UltraLowPowerCmd()
+   function (ULP bit (Ultra low power) in the PWR_CSR2 register) to disable the 
+   internal voltage reference. However, in this case, when exiting from the 
+   Halt/Active Halt modes, the functions managed through the internal voltage reference 
+   are not reliable during the internal voltage reference startup time (up to 3 ms).
+   To reduce the wakeup time, the device can exit from Halt/Active Halt modes without 
+   waiting for the internal voltage reference startup time. This is performed 
+   by using the PWR_FastWakeUpCmd() function (setting the FWU bit (Fast
+   wakeup) in the PWR_CSR2 register) before entering Halt/Active Halt mode.
+
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Enables or disables the Fast WakeUp from Ultra Low Power mode.
+  * @param  NewState: new state of the Fast WakeUp  functionality.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void PWR_FastWakeUpCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the PWR FWU */
+    PWR->CSR2 |= PWR_CSR2_FWU;
+  }
+  else
+  {
+    /* Disable the PWR FWU */
+    PWR->CSR2 &= (uint8_t)(~PWR_CSR2_FWU);
+  }
+}
+
+/**
+  * @brief  Enables or disables the Ultra Low Power mode.
+  * @param  NewState: new state of the Ultra Low Power mode.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void PWR_UltraLowPowerCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the PWR ULP */
+    PWR->CSR2 |= PWR_CSR2_ULP;
+  }
+  else
+  {
+    /* Disable the PWR ULP */
+    PWR->CSR2 &= (uint8_t)(~PWR_CSR2_ULP);
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Group3 Interrupts and Flags management functions
+ *  @brief   Interrupts and Flags management functions 
+ *
+@verbatim   
+ ===============================================================================
+                 Interrupts and Flags management functions
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures the Programmable Voltage Detector (PVD) Interrupt .
+  * @param  NewState : Indicates the new state of the PVD interrupt.
+  * @retval None
+  */
+void PWR_PVDITConfig(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the PVD interrupt */
+    PWR->CSR1 |= PWR_CSR1_PVDIEN;
+  }
+  else
+  {
+    /* Disable the PVD interrupt */
+    PWR->CSR1 &= (uint8_t)(~PWR_CSR1_PVDIEN);
+  }
+}
+
+/**
+  * @brief  Checks whether the specified PWR flag is set or not.
+  * @param  PWR_FLAG: specifies the flag to check.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_FLAG_PVDOF: PVD Output. This flag is valid only if PVD is enabled 
+  *                                 by the PWR_PVDCmd() function.
+  *            @arg PWR_FLAG_VREFINTF: Internal Voltage Reference Ready flag. This 
+  *                                    flag indicates the state of the internal voltage reference, VREFINT.
+  *            @arg PWR_FLAG_PVDIF: PVD Interrupt Flag, it's set by hardware when a PVD
+  *       event occurs  
+  * @retval The new state of PWR_FLAG (SET or RESET).
+  */
+FlagStatus PWR_GetFlagStatus(PWR_FLAG_TypeDef PWR_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+
+  /* Check the parameters */
+  assert_param(IS_PWR_FLAG(PWR_FLAG));
+
+  if ((PWR_FLAG & PWR_FLAG_VREFINTF) != 0)
+  {
+    if ((PWR->CSR2 & PWR_CR2_VREFINTF) != (uint8_t)RESET )
+    {
+      bitstatus = SET;
+    }
+    else
+    {
+      bitstatus = RESET;
+    }
+  }
+  else
+  {
+    if ((PWR->CSR1 & PWR_FLAG) != (uint8_t)RESET )
+    {
+      bitstatus = SET;
+    }
+    else
+    {
+      bitstatus = RESET;
+    }
+  }
+
+  /* Return the flag status */
+  return((FlagStatus)bitstatus);
+}
+
+/**
+  * @brief  Clears the PWR PVDIF Flag.
+  * @param  None
+  * @retval None
+  */
+void PWR_PVDClearFlag(void)
+{
+  /* Set the PVDIF to clear it */
+  PWR->CSR1 |= PWR_CSR1_PVDIF;
+}
+
+/**
+  * @brief  Checks whether the PVD interrupt has occurred or not.
+  * @param  None
+  * @retval The new state of the PVD Interrupt (SET or RESET).
+  */
+ITStatus PWR_PVDGetITStatus(void)
+{
+  ITStatus bitstatus = RESET;
+
+  uint8_t PVD_itStatus = 0x0, PVD_itEnable = 0x0;
+
+  PVD_itStatus = (uint8_t)(PWR->CSR1 & (uint8_t)PWR_CSR1_PVDIF);
+  PVD_itEnable = (uint8_t)(PWR->CSR1 & (uint8_t)PWR_CSR1_PVDIEN);
+
+  if ((PVD_itStatus != (uint8_t)RESET ) && (PVD_itEnable != (uint8_t)RESET))
+  {
+    bitstatus = (ITStatus)SET;
+  }
+  else
+  {
+    bitstatus = (ITStatus)RESET;
+  }
+  return ((ITStatus)bitstatus);
+}
+
+/**
+  * @brief  Clears the PWR interrupt pending bit.
+  * @param  None
+  * @retval None
+  */
+void PWR_PVDClearITPendingBit(void)
+{
+  /* Set the PVDIF to clear it */
+  PWR->CSR1 |= PWR_CSR1_PVDIF;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_rst.c b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_rst.c
new file mode 100755
index 0000000..82bcfe8
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_rst.c
@@ -0,0 +1,169 @@
+/**
+  ******************************************************************************
+  * @file    stm8l15x_rst.c
+  * @author  MCD Application Team
+  * @version V1.6.0
+  * @date    28-June-2013
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the RST peripheral:
+  *           - Flag management
+  *           - NRST Pin configuration
+  *
+  *  @verbatim
+  *               
+  *          ===================================================================
+  *                               RST specific features
+  *          ===================================================================
+  *
+  *           When a reset occurs, there is a reset phase from the external pin 
+  *           pull-down to the internal reset signal release. During this phase,
+  *           the microcontroller sets some hardware configurations before going
+  *           to the reset vector.
+  *           At the end of this phase, most of the registers are configured with
+  *           their “reset state” values. 
+  *           During the reset phase, some pin configurations may be different from
+  *           their “reset state” configuration.
+  *           
+  *           The NRST pin is an input and can be configured as open-drain output
+  *           using the RST_GPOutputEnable() function 
+  *
+  *  @endverbatim
+  *    
+  ******************************************************************************
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ****************************************************************************** 
+  */
+
+/* Includes ------------------------------------------------------------------*/
+
+#include "stm8l15x_rst.h"
+
+/** @addtogroup STM8L15x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup RST 
+  * @brief RST driver modules
+  * @{
+  */ 
+/* Private define ------------------------------------------------------------*/
+#define RST_CR_MASK  0xD0 /*!< Enable the GPIO */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup RST_Private_Functions
+  * @{
+  */
+
+/** @defgroup RST_Group1 Flag management functions
+ *  @brief   Flag management functions 
+ *
+@verbatim   
+ ===============================================================================
+                       Flag management functions
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief   Checks whether the specified RST flag is set or not.
+  * @param   RST_Flag : specify the reset flag to check.
+  *          This parameter can be one of the following values:
+  *            @arg RST_FLAG_PORF: POR reset flag
+  *            @arg RST_FLAG_SWIMF: SWIM reset flag
+  *            @arg RST_FLAG_ILLOPF: Illegal opcode reset flag
+  *            @arg RST_FLAG_IWDGF: Independent watchdog reset flag 
+  *            @arg RST_FLAG_WWDGF: Window watchdog reset flag
+  *            @arg RST_FLAG_BORF: BOR reset flag
+  * @retval The new state of RST_Flag (SET or RESET).
+  */
+FlagStatus RST_GetFlagStatus(RST_FLAG_TypeDef RST_Flag)
+{
+  /* Check the parameters */
+  assert_param(IS_RST_FLAG(RST_Flag));
+
+  /* Get flag status */
+
+  return ((FlagStatus)((uint8_t)RST->SR & (uint8_t)RST_Flag));
+}
+
+/**
+  * @brief  Clears the specified RST flag.
+  * @param   RST_Flag : specify the reset flag to check.
+  *          This parameter can be one of the following values:
+  *            @arg RST_FLAG_PORF: POR reset flag
+  *            @arg RST_FLAG_SWIMF: SWIM reset flag
+  *            @arg RST_FLAG_ILLOPF: Illegal opcode reset flag
+  *            @arg RST_FLAG_IWDGF: Independent watchdog reset flag 
+  *            @arg RST_FLAG_WWDGF: Window watchdog reset flag
+  *            @arg RST_FLAG_BORF: BOR reset flag
+  * @retval None
+  */
+void RST_ClearFlag(RST_FLAG_TypeDef RST_Flag)
+{
+  /* Check the parameters */
+  assert_param(IS_RST_FLAG(RST_Flag));
+
+  RST->SR = (uint8_t)RST_Flag;
+}
+
+/**
+  * @}
+  */
+  
+/** @defgroup RST_Group2 NRST Pin configuration function
+ *  @brief   NRST Pin configuration function 
+ *
+@verbatim   
+ ===============================================================================
+                      NRST Pin configuration function
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Configures the reset pad as GP output.
+  * @param  None
+  * @retval None
+  */
+void RST_GPOutputEnable(void)
+{
+
+  RST->CR = RST_CR_MASK;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_rtc.c b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_rtc.c
new file mode 100755
index 0000000..5253c06
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_rtc.c
@@ -0,0 +1,2242 @@
+/**
+  ******************************************************************************
+  * @file    stm8l15x_rtc.c
+  * @author  MCD Application Team
+  * @version V1.6.0
+  * @date    28-June-2013
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Real-Time Clock (RTC) peripheral:           
+  *           - Initialization
+  *           - Calendar (Time and Date) configuration
+  *           - Alarm configuration
+  *           - WakeUp Timer configuration
+  *           - Daylight Saving configuration
+  *           - Output pin Configuration
+  *           - Smooth Calibration configuration
+  *           - Tampers configuration
+  *           - Output Type configuration
+  *           - Interrupts and flags management       
+  *                     
+  *  @verbatim
+  *       
+  *          ===================================================================      
+  *                                    RTC Domain Reset
+  *          ===================================================================          
+  *          After power-on reset, the RTC domain (RTC registers) is reset.        
+  *         
+  *          ===================================================================      
+  *                                  RTC Operating Condition      
+  *          ===================================================================            
+  *          As long as the supply voltage remains in the operating range, 
+  *          the RTC never stops, regardless of the device status (Run mode, 
+  *          low power modes or under reset).
+  *              
+  *          ===================================================================      
+  *                                   RTC Domain Access     
+  *          ===================================================================         
+  *          After reset, the RTC domain (RTC registers) is protected against 
+  *          possible stray write accesses. 
+  *          To enable access to the RTC registers, proceed as follows:
+  *            - Select the RTC clock source using the CLK_RTCClockConfig()
+  *              function : HSE, HSI, LSE or LSI.
+  *              CLK_RTCClockConfig(CLK_RTCCLKSource_HSI, CLK_RTCCLKDiv_1)    
+  *            - Enable RTC Clock using the CLK_PeripheralClockConfig() function 
+  *               : CLK_PeripheralClockConfig(CLK_Peripheral_RTC, ENABLE).
+  *              
+  *          ===================================================================      
+  *                                   RTC Driver: how to use it
+  *          ===================================================================          
+  *            - Enable the RTC domain access (see description in the section above)
+  *            - Configure the RTC Prescaler (Asynchronous and Synchronous) and
+  *              RTC hour format using the RTC_Init() function.
+  *                
+  *          Time and Date configuration
+  *          ===========================    
+  *            - To configure the RTC Calendar (Time and Date) use the RTC_SetTime()
+  *              and RTC_SetDate() functions.
+  *            - To read the RTC Calendar, use the RTC_GetTime() and RTC_GetDate()
+  *              functions.
+  *            - Use the RTC_DayLightSavingConfig() function to add or sub 1hour
+  *              to the RTC Calendar.    
+  *                
+  *          Alarm configuration
+  *          ===================    
+  *            - To configure the RTC Alarm use the RTC_SetAlarm() function.
+  *            - Enable the selected RTC Alarm using the RTC_AlarmCmd() function  
+  *            - To read the RTC Alarm, use the RTC_GetAlarm() function.
+  *              
+  *          RTC Wakeup configuration
+  *          ========================    
+  *            - Configure the RTC Wakeup Clock source use the RTC_WakeUpClockConfig()
+  *              function.
+  *            - Configure the RTC WakeUp Counter using the RTC_SetWakeUpCounter() 
+  *              function  
+  *            - Enable the RTC WakeUp using the RTC_WakeUpCmd() function  
+  *            - To read the RTC WakeUp Counter register, use the RTC_GetWakeUpCounter() 
+  *              function.
+  *                
+  *          Outputs configuration
+  *          =====================  
+  *          The RTC has 2 different outputs:
+  *            - AFO_ALARM: this output is used to manage the RTC Alarm and 
+  *              WaKeUp signals.          
+  *              To output the selected RTC signal on RTC_ALARM pin, use the 
+  *              RTC_OutputConfig() function.                
+  *            - AFO_CALIB: this output is used to manage the RTC Clock divided 
+  *              by 64 (512Hz) signal or divided by 32768 (1Hz) which can be 
+  *              configured using RTC_CalibOutputConfig() function.
+  *              To output the RTC Clock on RTC_CALIB pin, use the 
+  *              RTC_CalibOutputCmd() function.                
+  *                                                           
+  *          Smooth Calibration configuration                    
+  *          =================================    
+  *            - Configure the RTC Smooth Calibration Value and the corresponding
+  *              sign using the RTC_SmoothCalibConfig() function.
+
+  *                
+  *
+  *          Tamper configuration                     
+  *          ====================    
+  *            - Configure the RTC Tamper Level using the RTC_TamperConfig() 
+  *              function.
+  *            - Enable the RTC Tamper using the RTC_TamperCmd() function.
+  *
+  *                                  
+  *          ===================================================================      
+  *                                  RTC and low power modes
+  *          =================================================================== 
+  *           The MCU can be woken up from a low power mode by an RTC alternate 
+  *           function.
+  *           The RTC alternate functions are the RTC alarms, 
+  *           RTC wakeup and RTC tamper event detection.
+  *           These RTC alternate functions can wake up the system from the 
+  *           lowpower modes.
+  *           The system can also wake up from low power modes without depending 
+  *           on an external interrupt (Auto-wakeup mode), by using the RTC alarm 
+  *           or the RTC wakeup events.
+  *           The RTC provides a programmable time base for waking up from the 
+  *           halt or wfe or wfi modes at regular intervals.
+  *           
+  *                         
+  *  @endverbatim
+  *                      
+  ******************************************************************************
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ****************************************************************************** 
+  */    
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm8l15x_rtc.h"
+
+/** @addtogroup STM8L15x_StdPeriph_Driver
+  * @{
+  */
+  
+/** @defgroup RTC 
+  * @brief RTC driver modules
+  * @{
+  */
+  
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define INIT_TIMEOUT       ((uint16_t)0xFFFF)
+#define RSF_TIMEOUT        ((uint16_t)0xFFFF)
+#define INITF_TIMEOUT      ((uint16_t)0xFFFF)
+#define WUTWF_TIMEOUT      ((uint16_t)0xFFFF)
+#define ALRAWF_TIMEOUT     ((uint16_t)0xFFFF)
+#define RECALPF_TIMEOUT    ((uint16_t)0xFFFF)
+#define SHPF_TIMEOUT       ((uint16_t)0xFFFF)
+
+#define TEN_VALUE_BCD      ((uint8_t)0x10)
+#define TEN_VALUE_BIN      ((uint8_t)0x0A)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/** @defgroup RTC_Private_Functions_Prototype
+  * @{
+  */
+static uint8_t ByteToBcd2(uint8_t Value);
+static uint8_t Bcd2ToByte(uint8_t Value);
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Private_Functions
+  * @{
+  */
+
+/** @defgroup RTC_Group1 Initialization and Configuration functions
+ *  @brief   Initialization and Configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+                 Initialization and Configuration functions
+ ===============================================================================  
+
+  This section provide functions allowing to initialize and configure the RTC
+  Prescaler (Synchronous and Asynchronous), RTC Hour format, disable RTC registers
+  Write protection, enter and exit the RTC initialization mode, RTC registers
+  synchronization check and reference clock detection enable.
+  
+  1. The RTC Prescaler is programmed to generate the RTC 1Hz time base. It is
+     split into 2 programmable prescaler to minimize power consumption.
+     - A 7-bit asynchronous prescaler and A 13-bit or 15-bit synchronous 
+       prescaler depending to density of the mcu package.
+     - When both prescaler are used, it is recommended to configure the 
+       asynchronous prescaler to a high value to minimize consumption.
+
+  2. All RTC registers are Write protected. Writing to the RTC registers
+     is enabled by writing a key into the Write Protection register, RTC_WPR.
+
+  3. To Configure the RTC Calendar, user application should enter initialization
+     mode. In this mode, the Calendar counter is stopped and its value can be 
+     updated. When the initialization sequence is complete, the Calendar restarts 
+     counting after 4 RTCCLK cycles.
+
+  4. To read the Calendar through the shadow registers after Calendar initialization,
+     Calendar update or after wakeup from low power modes the software must first 
+     clear the RSF flag. The software must then wait until it is set again before 
+     reading the Calendar, which means that the Calendar registers have been 
+     correctly copied into the RTC_TR and RTC_DR shadow registers.
+     The RTC_WaitForSynchro() function implements the above software sequence 
+     (RSF clear and RSF check).
+
+@endverbatim
+  * @{
+  */
+/**
+* @brief  Deinitializes the RTC registers to their default reset values.
+* @note   This function doesn't reset the RTC Clock source.  
+* @param  None
+* @retval An ErrorStatus enumeration value:
+*          - SUCCESS: RTC registers are deinitialized
+*          - ERROR: RTC registers are not deinitialized
+*/
+ErrorStatus RTC_DeInit(void)
+{
+  ErrorStatus status = ERROR;
+  uint16_t wutwfcount = 0;
+  uint16_t recalpfcount = 0;
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* Set Initialization mode */
+  if (RTC_EnterInitMode() == ERROR)
+  {
+    status = ERROR;
+    /* Enable the write protection for RTC registers */
+    RTC->WPR = 0xFF; 
+  }
+  else
+  {
+    /* Reset TR registers */
+    RTC->TR1 = RTC_TR1_RESET_VALUE;
+    RTC->TR2 = RTC_TR2_RESET_VALUE;
+    RTC->TR3 = RTC_TR3_RESET_VALUE;
+
+    /* Reset DR registers */
+    RTC->DR1 = RTC_DR1_RESET_VALUE;
+    RTC->DR2 = RTC_DR2_RESET_VALUE;
+    RTC->DR3 = RTC_DR3_RESET_VALUE;
+
+    /* Reset SPER & ARPER registers */
+    RTC->SPRERH = RTC_SPRERH_RESET_VALUE;
+    RTC->SPRERL = RTC_SPRERL_RESET_VALUE;
+    RTC->APRER  = RTC_APRER_RESET_VALUE;
+
+    RTC->TCR1 = RTC_TCR1_RESET_VALUE;
+    RTC->TCR2 = RTC_TCR2_RESET_VALUE;
+
+    /* Reset All CR1 bits except CR1[2:0] */
+
+    RTC->CR1 = RTC_CR1_RESET_VALUE;
+    RTC->CR2 = RTC_CR2_RESET_VALUE;
+    RTC->CR3 = RTC_CR3_RESET_VALUE;
+
+    /* Wait till RTC WUTWF flag is set or if Time out is reached exit */
+    while (((RTC->ISR1 & RTC_ISR1_WUTWF) == RESET) && ( wutwfcount != WUTWF_TIMEOUT))
+    {
+      wutwfcount++;
+      RTC->ISR1 = 0;
+    }
+
+    if ((RTC->ISR1 & RTC_ISR1_WUTWF) == RESET)
+    {
+      status = ERROR;
+      /* Enable the write protection for RTC registers */
+      RTC->WPR = 0xFF; 
+    }
+    else
+    {
+      /* Reset All CR1 bits */
+      RTC->CR1 = RTC_CR1_RESET_VALUE;
+
+      /* Reset WUTR registers */
+      RTC->WUTRH = RTC_WUTRH_RESET_VALUE;
+      RTC->WUTRL = RTC_WUTRL_RESET_VALUE;
+
+      /* Reset ALARM registers */
+      RTC->ALRMAR1 = RTC_ALRMAR1_RESET_VALUE;
+      RTC->ALRMAR2 = RTC_ALRMAR2_RESET_VALUE;
+      RTC->ALRMAR3 = RTC_ALRMAR3_RESET_VALUE;
+      RTC->ALRMAR4 = RTC_ALRMAR4_RESET_VALUE;
+
+      RTC->ALRMASSRH = RTC_ALRMASSRH_RESET_VALUE;
+      RTC->ALRMASSRL = RTC_ALRMASSRL_RESET_VALUE;
+      RTC->ALRMASSMSKR = RTC_ALRMASSMSKR_RESET_VALUE;
+
+      /* Reset ISR register and exit initialization mode */
+      RTC->ISR1 = (uint8_t)0x00;
+      RTC->ISR2 = RTC_ISR2_RESET_VALUE;
+
+      if ((RTC->ISR1 & RTC_ISR1_RECALPF) != RESET)
+      {
+        while (((RTC->ISR1 & RTC_ISR1_RECALPF) != RESET) && (recalpfcount != RECALPF_TIMEOUT))
+        {
+          recalpfcount++;
+        }
+      }
+      if ((RTC->ISR1 & RTC_ISR1_RECALPF) == RESET)
+      {
+        RTC->CALRH = RTC_CALRH_RESET_VALUE;
+        RTC->CALRL = RTC_CALRL_RESET_VALUE;
+
+        if (RTC_WaitForSynchro() == ERROR)
+        {
+          status = ERROR;
+        }
+        else
+        {
+          status = SUCCESS;
+        }
+      }
+      else
+      {
+        status = ERROR;
+      }
+
+      /* Enable the write protection for RTC registers */
+      RTC->WPR = 0xFF; 
+    }
+  }
+
+  /* return Deinitialize RTC registers status*/
+  return (ErrorStatus)status;
+}
+
+
+
+/**
+* @brief  Initializes the RTC registers according to the specified parameters
+*         in RTC_InitStruct.
+* @param  RTC_InitStruct: pointer to a RTC_InitTypeDef structure that contains
+*         the configuration information for the RTC peripheral.
+* @note   The RTC Prescaler register is write protected and can be written in 
+*         initialization mode only.  
+* @retval An ErrorStatus enumeration value:
+*          - SUCCESS: RTC registers are initialized
+*          - ERROR: RTC registers are not initialized
+*/
+ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct)
+{
+  ErrorStatus status = ERROR;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_HOUR_FORMAT(RTC_InitStruct->RTC_HourFormat));
+  assert_param(IS_RTC_ASYNCH_PREDIV(RTC_InitStruct->RTC_AsynchPrediv));
+  assert_param(IS_RTC_SYNCH_PREDIV(RTC_InitStruct->RTC_SynchPrediv));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* Set Initialization mode */
+  if (RTC_EnterInitMode() == ERROR)
+  {
+    status = ERROR;
+  }
+  else
+  {
+    /* Clear the bits to be configured first */
+    RTC->CR1 &= ((uint8_t)~( RTC_CR1_FMT ));
+
+    /* Set RTC_CR1 register */
+    RTC->CR1 |=  ((uint8_t)(RTC_InitStruct->RTC_HourFormat));
+
+    /* Set Prescalers registers */
+    RTC->SPRERH = (uint8_t)(RTC_InitStruct->RTC_SynchPrediv >> 8);
+    RTC->SPRERL = (uint8_t)(RTC_InitStruct->RTC_SynchPrediv);
+    RTC->APRER =  (uint8_t)(RTC_InitStruct->RTC_AsynchPrediv);
+
+    /* Exit Initialization mode */
+    RTC->ISR1 &= (uint8_t)~RTC_ISR1_INIT;
+
+    status = SUCCESS;
+  }
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF; 
+
+  /* return Initialize the RTC registers status*/
+  return (ErrorStatus)(status);
+}
+
+/**
+* @brief  Fills each RTC_InitStruct member with its default value
+*         Hour format = 24h / Prescalers configured to their reset values.
+* @param  RTC_InitStruct: pointer to a RTC_InitTypeDef structure which will be
+*         initialized.
+* @retval None
+*/
+void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct)
+{
+  /* Initialize the RTC_Hourformat member */
+  RTC_InitStruct->RTC_HourFormat = RTC_HourFormat_24;
+
+  /* Initialize the RTC_AsynchPrediv member */
+  RTC_InitStruct->RTC_AsynchPrediv = RTC_APRER_RESET_VALUE;
+
+  /* Initialize the RTC_SynchPrediv member */
+  RTC_InitStruct->RTC_SynchPrediv = RTC_SPRERL_RESET_VALUE;
+}
+
+/**
+* @brief  Enables or disables the RTC registers write protection.
+* @param  NewState: new state of the write protection.
+  *         This parameter can be: ENABLE or DISABLE.
+* @note   Writing a wrong key reactivates the write protection.
+* @note   The protection mechanism is not affected by system reset.  
+* @retval None
+*/
+void RTC_WriteProtectionCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the write protection for RTC registers */
+    RTC->WPR = RTC_WPR_EnableKey;
+  }
+  else
+  {
+    /* Disable the write protection for RTC registers */
+    RTC->WPR = RTC_WPR_DisableKey1;
+    RTC->WPR = RTC_WPR_DisableKey2;
+  }
+}
+
+
+/**
+* @brief  Enters the RTC Initialization mode.
+* @note   The RTC Initialization mode is write protected, use the 
+*         RTC_WriteProtectionCmd(DISABLE) before calling this function. 
+* @param  None
+* @retval An ErrorStatus enumeration value:
+*          - SUCCESS: RTC is in Init mode
+*          - ERROR: RTC is not in Init mode
+*/
+ErrorStatus RTC_EnterInitMode(void)
+{
+  ErrorStatus status = ERROR;
+  uint16_t initfcount = 0;
+
+  /* Check if the Initialization mode is set */
+  if ((RTC->ISR1 & RTC_ISR1_INITF) == RESET)
+  {
+    /* Set the Initialization mode */
+    RTC->ISR1 = (uint8_t)RTC_ISR1_INIT;
+
+    /* Wait until INITF flag is set */
+    while (((RTC->ISR1 & RTC_ISR1_INITF) == RESET) && ( initfcount != INITF_TIMEOUT))
+    {
+      initfcount++;
+    }
+  }
+
+  if ((RTC->ISR1 & RTC_ISR1_INITF) == RESET)
+  {
+    status = ERROR;
+  }
+  else
+  {
+    status = SUCCESS;
+  }
+
+  return (ErrorStatus)status;
+}
+
+
+/**
+* @brief  Exits the RTC Initialization mode.
+* @note   When the initialization sequence is complete, the Calendar restarts 
+*         counting after 4 RTCCLK cycles.  
+* @note   The RTC Initialization mode is write protected, use the 
+*         RTC_WriteProtectionCmd(DISABLE) before calling this function.     
+* @param  None
+* @retval None
+*/
+void RTC_ExitInitMode(void)
+{
+  /* Exit Initialization mode */
+  RTC->ISR1 &= (uint8_t)~RTC_ISR1_INIT;
+}
+
+
+/**
+* @brief  Waits until the RTC Calendar registers (Time and Date)
+*         are synchronized with RTC clock.
+* @note   This function is meaningless when BAYPASS feature is enabled in RTC_CR1
+*         register.
+* @note   To read the Calendar through the shadow registers after Calendar 
+*         initialization, Calendar update or after wakeup from low power modes 
+*         the software must first clear the RSF flag. 
+*         The software must then wait until it is set again before reading 
+*         the Calendar (if not yet done), which means that the Calendar registers
+*         have been correctly copied into the RTC_TRx and RTC_DRx shadow registers.
+* @note   RTC_SetTime() and RTC_SetDate() functions call RTC_WaitForSynchro() function
+*         after updating the Calendar. In Run mode, User can use RTC_GetDate(), 
+*         RTC_GetTime() and/or RTC_GetSubSecond() without need to call 
+*         RTC_WaitForSynchro() function. After waking up from low power mode, this 
+*         function must be called before calling RTC_GetDate(), RTC_GetTime() or 
+*         RTC_GetSubSecond() functions.   
+* @param  None
+* @retval An ErrorStatus enumeration value:
+*          - SUCCESS: RTC registers are synchronized
+*          - ERROR: RTC registers are not synchronized
+*/
+ErrorStatus RTC_WaitForSynchro(void)
+{
+  uint16_t rsfcount = 0;
+  ErrorStatus status = ERROR;
+  
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* Clear RSF flag by writing 0 in RSF bit  */
+  RTC->ISR1 &= (uint8_t)~(RTC_ISR1_RSF | RTC_ISR1_INIT);
+
+  /* Wait the registers to be synchronised */
+  while (((RTC->ISR1 & RTC_ISR1_RSF) == RESET) && ( rsfcount != RSF_TIMEOUT))
+  {
+    rsfcount++;
+  }
+
+  /* Check if RSF flag occurs*/
+  if ((RTC->ISR1 & RTC_ISR1_RSF) != RESET)
+  {
+    status = SUCCESS;
+  }
+  else
+  {
+    status = ERROR;
+  }
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF; 
+  
+  return (ErrorStatus)status;
+}
+
+
+/**
+* @brief  Enables or Disables the RTC Ratio.
+* @param  NewState: new state of the Ratio feature.
+  *         This parameter can be: ENABLE or DISABLE.
+* @retval None
+*/
+void RTC_RatioCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  if (NewState != DISABLE)
+  {
+    /* Set the RATIO bit */
+    RTC->CR1 |= (uint8_t)RTC_CR1_RATIO;
+  }
+  else
+  {
+    /* Reset the RATIO bit */
+    RTC->CR1 &= (uint8_t)~RTC_CR1_RATIO;
+  }
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF; 
+}
+
+/**
+* @brief  Enables or Disables the Bypass Shadow feature.
+* @param  NewState: new state of the Bypass Shadow feature.
+  *         This parameter can be: ENABLE or DISABLE.
+* @retval None
+*/
+void RTC_BypassShadowCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  if (NewState != DISABLE)
+  {
+    /* Set the BYPSHAD bit */
+    RTC->CR1 |= (uint8_t)RTC_CR1_BYPSHAD;
+  }
+  else
+  {
+    /* Reset the BYPSHAD bit */
+    RTC->CR1 &= (uint8_t)~RTC_CR1_BYPSHAD;
+  }
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF; 
+}
+
+
+
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Group2 Time and Date configuration functions
+ *  @brief   Time and Date configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+                   Time and Date configuration functions
+ ===============================================================================  
+
+  This section provide functions allowing to program and read the RTC Calendar
+  (Time and Date).
+
+@endverbatim
+  * @{
+  */
+
+
+/**
+* @brief Sets the RTC current time.
+* @note   After updating the Calendar, this routine clears the RSF flag and waits
+*         until it is set again (using RTC_WaitForSynchro() function) , which means
+*         that the Calendar registers have been correctly copied into the RTC_TRx
+*         and RTC_DRx shadow registers. 
+* @param  RTC_Format: specifies the format of the entered parameters.
+*         This parameter can be one of the @ref RTC_Format_TypeDef enumeration.
+* @param  RTC_TimeStruct:  pointer to a  @ref RTC_TimeTypeDef structure that
+*         contains the time configuration information for the RTC
+* @retval An ErrorStatus enumeration value:
+*          - SUCCESS: RTC Time register is configured
+*          - ERROR: RTC Time register is not configured
+*/
+ErrorStatus RTC_SetTime(RTC_Format_TypeDef RTC_Format,
+                        RTC_TimeTypeDef* RTC_TimeStruct)
+{
+  ErrorStatus status = ERROR;
+  uint8_t temp = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_FORMAT(RTC_Format));
+
+  if (RTC_Format == RTC_Format_BIN)
+  {
+    /* Check Hour Format (24h or 12h)*/
+    if ((RTC->CR1 & RTC_CR1_FMT) != RESET)
+    {
+      assert_param(IS_RTC_HOUR12_MAX(RTC_TimeStruct->RTC_Hours));
+      assert_param(IS_RTC_HOUR12_MIN(RTC_TimeStruct->RTC_Hours));
+    }
+    else
+    {
+      assert_param(IS_RTC_HOUR24(RTC_TimeStruct->RTC_Hours));
+    }
+    assert_param(IS_RTC_MINUTES(RTC_TimeStruct->RTC_Minutes));
+    assert_param(IS_RTC_SECONDS(RTC_TimeStruct->RTC_Seconds));
+  }
+  else
+  {
+    /* Check Hour Format (24h or 12h)*/
+    if ((RTC->CR1 & RTC_CR1_FMT) != RESET)
+    {
+      assert_param(IS_RTC_HOUR12_MAX(Bcd2ToByte(RTC_TimeStruct->RTC_Hours)));
+      assert_param(IS_RTC_HOUR12_MIN(Bcd2ToByte(RTC_TimeStruct->RTC_Hours)));
+    }
+    else
+    {
+      assert_param(IS_RTC_HOUR24(Bcd2ToByte(RTC_TimeStruct->RTC_Hours)));
+    }
+    assert_param(IS_RTC_MINUTES(Bcd2ToByte(RTC_TimeStruct->RTC_Minutes)));
+    assert_param(IS_RTC_SECONDS(Bcd2ToByte(RTC_TimeStruct->RTC_Seconds)));
+  }
+
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* Set Initialization mode */
+  if (RTC_EnterInitMode() == ERROR)
+  {
+    status = ERROR;
+    /* Enable the write protection for RTC registers */
+    RTC->WPR = 0xFF; 
+  }
+  else
+  {
+    /* Check Hour Format is 12h)*/
+    if ((RTC->CR1 & RTC_CR1_FMT) != RESET)
+    {
+      assert_param(IS_RTC_H12(RTC_TimeStruct->RTC_H12));
+      temp = RTC_TimeStruct->RTC_H12;
+    }
+    else
+    {
+      temp = 0;
+    }
+    /* Check the input parameters format */
+    if (RTC_Format != RTC_Format_BIN)
+    {
+      RTC->TR1 = (uint8_t)(RTC_TimeStruct->RTC_Seconds);
+      RTC->TR2 = (uint8_t)(RTC_TimeStruct->RTC_Minutes) ;
+      RTC->TR3 = (uint8_t)( temp | RTC_TimeStruct->RTC_Hours) ;
+    }
+    else
+    {
+      RTC->TR1 = (uint8_t)(ByteToBcd2(RTC_TimeStruct->RTC_Seconds));
+      RTC->TR2 = (uint8_t)(ByteToBcd2(RTC_TimeStruct->RTC_Minutes)) ;
+      RTC->TR3 = (uint8_t)( temp | ByteToBcd2(RTC_TimeStruct->RTC_Hours));
+    }
+    /* Read DR3 register to unfreeze calender registers */
+    (void)(RTC->DR3);
+
+    /* Exit Initialization mode */
+    RTC->ISR1 &= (uint8_t)~RTC_ISR1_INIT;
+
+    /* Enable the write protection for RTC registers */
+    RTC->WPR = 0xFF; 
+
+    /* if RTC_CR1_BYPSHAD bit = 0, wait for synchro else this check is not needed */
+    if ((RTC->CR1 & RTC_CR1_BYPSHAD) == RESET)
+    {
+      if (RTC_WaitForSynchro() == ERROR)
+      {
+        status = ERROR;
+      }
+      else
+      {
+        status = SUCCESS;
+      }
+    }
+    else
+    {
+      status = SUCCESS;
+    }
+  }
+
+  return (ErrorStatus)status;
+}
+
+
+
+/**
+* @brief  Fills each RTC_TimeStruct member with its default value
+*         (Time = 00h:00min:00sec).
+* @param  RTC_TimeStruct: pointer to a @ref RTC_TimeTypeDef structure which will be
+*         initialized.
+* @retval None
+*/
+void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct)
+{
+  /* Time = 00h:00min:00sec*/
+  RTC_TimeStruct->RTC_H12 = RTC_H12_AM;
+  RTC_TimeStruct->RTC_Hours = 0;
+  RTC_TimeStruct->RTC_Minutes = 0;
+  RTC_TimeStruct->RTC_Seconds = 0;
+}
+
+          
+/**
+* @brief  Gets the RTC current Time.
+* @note   To read the Calendar after wake up from low power mode, user software 
+*         must first check that the RSF flag is set in RTC_ISR1, using 
+*         RTC_WaitForSynchro() function, which means that the Calendar registers
+*         have been correctly copied into the shadow registers (RTC_TRx and RTC_DRx).
+* @param  RTC_Format: specifies the format of the returned parameters.
+*         This parameter can be one of the @ref RTC_Format_TypeDef enumeration.
+* @param  RTC_TimeStruct: pointer to a @ref RTC_TimeTypeDef structure that
+*         will contain the returned current time configuration.
+* @retval None
+
+*/
+void RTC_GetTime(RTC_Format_TypeDef RTC_Format,
+                 RTC_TimeTypeDef* RTC_TimeStruct)
+{
+  uint8_t  tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_FORMAT(RTC_Format));
+
+  /* Fill the structure fields with the read parameters */
+  /* Get RTC seconds */
+  RTC_TimeStruct->RTC_Seconds = RTC->TR1;
+
+  /* Get RTC Minutes */
+  RTC_TimeStruct->RTC_Minutes = RTC->TR2;
+
+  /* Get the RTC_TR3 register */
+  tmpreg = (uint8_t)RTC->TR3;
+
+  /* Read DR3 register to unfreeze calender registers */
+  (void) (RTC->DR3) ;
+
+
+  /* Get RTC Hours */
+  RTC_TimeStruct->RTC_Hours = (uint8_t)(tmpreg & (uint8_t)~(RTC_TR3_PM));
+
+  /* Get RTC H12 state */
+  RTC_TimeStruct->RTC_H12 = (RTC_H12_TypeDef)(tmpreg & RTC_TR3_PM);
+
+  /* Check the input parameters format */
+  if (RTC_Format == RTC_Format_BIN)
+  {
+    /* Convert the structure parameters to Binary format */
+    RTC_TimeStruct->RTC_Hours = (uint8_t)Bcd2ToByte(RTC_TimeStruct->RTC_Hours);
+    RTC_TimeStruct->RTC_Minutes = (uint8_t)Bcd2ToByte(RTC_TimeStruct->RTC_Minutes);
+    RTC_TimeStruct->RTC_Seconds = (uint8_t)Bcd2ToByte(RTC_TimeStruct->RTC_Seconds);
+  }
+}
+
+/**
+* @brief  Gets the RTC current Calendar Subseconds value.
+* @note   To read the Calendar after wake up from low power mode, user software 
+*         must first check that the RSF flag is set in RTC_ISR1, using 
+*         RTC_WaitForSynchro() function, which means that the Calendar registers
+*         have been correctly copied into the shadow registers (RTC_TRx and RTC_DRx).
+* @param  None
+* @retval RTC current Calendar Subseconds value.
+*/
+uint16_t RTC_GetSubSecond(void)
+{
+  uint8_t ssrhreg = 0, ssrlreg = 0;
+  uint16_t ssrreg = 0;
+
+  /* Get subseconds values from the correspondent registers*/
+  ssrhreg = RTC->SSRH;
+  ssrlreg = RTC->SSRL;
+
+  /* Read DR3 register to unfreeze calender registers */
+  (void) (RTC->DR3);
+
+
+  ssrreg = (uint16_t)((uint16_t)((uint16_t)ssrhreg << 8) | (uint16_t)(ssrlreg));
+  return (uint16_t)(ssrreg);
+}
+
+/**
+* @brief  Set the RTC current date.
+* @note   After updating the Calendar, this routine clears the RSF flag and waits
+*         until it is set again (using RTC_WaitForSynchro() function) , which means
+*         that the Calendar registers have been correctly copied into the RTC_TRx
+*         and RTC_DRx shadow registers.   
+* @param  RTC_Format: specifies the format of the entered parameters.
+*         This parameter can be one of the @ref RTC_Format_TypeDef enumeration.
+* @param  RTC_DateStruct:  pointer to a  @ref RTC_TimeTypeDef structure that
+*         contains the date configuration information for the RTC.
+* @retval An ErrorStatus enumeration value:
+*          - SUCCESS: RTC Date register is configured
+*          - ERROR: RTC Date register is not configured
+*/
+ErrorStatus RTC_SetDate(RTC_Format_TypeDef RTC_Format,
+                        RTC_DateTypeDef* RTC_DateStruct)
+{
+  ErrorStatus status = ERROR;
+
+  if ((RTC_Format == RTC_Format_BIN) && ((RTC_DateStruct->RTC_Month & TEN_VALUE_BCD) == TEN_VALUE_BCD))
+  {
+    RTC_DateStruct->RTC_Month = (RTC_Month_TypeDef)((RTC_DateStruct->RTC_Month & (uint8_t)~(TEN_VALUE_BCD)) + TEN_VALUE_BIN);
+  }
+
+  /* Check the parameters */
+  assert_param(IS_RTC_FORMAT(RTC_Format));
+  if (RTC_Format == RTC_Format_BIN)
+  {
+    assert_param(IS_RTC_YEAR(RTC_DateStruct->RTC_Year));
+    assert_param(IS_RTC_MONTH_MIN(RTC_DateStruct->RTC_Month));
+    assert_param(IS_RTC_MONTH_MAX(RTC_DateStruct->RTC_Month));
+    assert_param(IS_RTC_DATE_MIN(RTC_DateStruct->RTC_Date));
+    assert_param(IS_RTC_DATE_MAX(RTC_DateStruct->RTC_Date));
+  }
+  else
+  {
+    assert_param(IS_RTC_YEAR(Bcd2ToByte(RTC_DateStruct->RTC_Year)));
+    assert_param(IS_RTC_MONTH_MAX(Bcd2ToByte((uint8_t)RTC_DateStruct->RTC_Month)));
+    assert_param(IS_RTC_MONTH_MIN(Bcd2ToByte((uint8_t)RTC_DateStruct->RTC_Month)));
+    assert_param(IS_RTC_DATE_MIN(Bcd2ToByte((uint8_t)RTC_DateStruct->RTC_Date)));
+    assert_param(IS_RTC_DATE_MAX(Bcd2ToByte((uint8_t)RTC_DateStruct->RTC_Date)));
+  }
+  assert_param(IS_RTC_WEEKDAY(RTC_DateStruct->RTC_WeekDay));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* Set Initialization mode */
+  if (RTC_EnterInitMode() == ERROR)
+  {
+    status = ERROR;
+    /* Enable the write protection for RTC registers */
+    RTC->WPR = 0xFF; 
+  }
+  else
+  {
+    (void)(RTC->TR1);
+    /* Set the RTC_DR registers */
+    /* Check the input parameters format */
+    if (RTC_Format != RTC_Format_BIN)
+    {
+      RTC->DR1 = (uint8_t)(RTC_DateStruct->RTC_Date);
+      RTC->DR2 = (uint8_t)((RTC_DateStruct->RTC_Month) | (uint8_t)((RTC_DateStruct->RTC_WeekDay) << 5));
+      RTC->DR3 = (uint8_t)((RTC_DateStruct->RTC_Year));
+    }
+    else
+    {
+      RTC->DR1 = (uint8_t)(ByteToBcd2 ((uint8_t)RTC_DateStruct->RTC_Date));
+      RTC->DR2 = (uint8_t)((ByteToBcd2((uint8_t)RTC_DateStruct->RTC_Month)) | (uint8_t)((RTC_DateStruct->RTC_WeekDay) << 5));
+      RTC->DR3 = (uint8_t)(ByteToBcd2((uint8_t)RTC_DateStruct->RTC_Year));
+    }
+
+    /* Exit Initialization mode */
+    RTC->ISR1 &= (uint8_t)~RTC_ISR1_INIT;
+
+    /* Enable the write protection for RTC registers */
+    RTC->WPR = 0xFF; 
+
+    /* if  RTC_CR1_BYPSHAD bit = 0, wait for synchro else this check is not needed */
+    if ((RTC->CR1 & RTC_CR1_BYPSHAD) == RESET)
+    {
+      if (RTC_WaitForSynchro() == ERROR)
+      {
+        status = ERROR;
+      }
+      else
+      {
+        status = SUCCESS;
+      }
+    }
+    else
+    {
+      status = SUCCESS;
+    }
+  }
+
+  return (ErrorStatus)status;
+}
+/**
+* @brief  Fills each RTC_DateStruct member with its default value
+*         (Monday 01 January xx00).
+* @param  RTC_DateStruct: pointer to a @ref RTC_DateTypeDef structure which will be
+*         initialized.
+* @retval None
+*/
+void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct)
+{
+  /* * (Monday 01 January xx00)*/
+  RTC_DateStruct->RTC_WeekDay = RTC_Weekday_Monday;
+  RTC_DateStruct->RTC_Date = 1;
+  RTC_DateStruct->RTC_Month = RTC_Month_January;
+  RTC_DateStruct->RTC_Year = 0;
+}
+/**
+* @brief  Get the RTC current date.
+* @note   To read the Calendar after wake up from low power mode, user software 
+*         must first check that the RSF flag is set in RTC_ISR1, using 
+*         RTC_WaitForSynchro() function, which means that the Calendar registers
+*         have been correctly copied into the shadow registers (RTC_TRx and RTC_DRx).
+* @param  RTC_Format: specifies the format of the returned parameters.
+*         This parameter can be one of the @ref RTC_Format_TypeDef enumeration.
+* @param  RTC_DateStruct: pointer to a @ref RTC_DateTypeDef structure that
+*         will contain the returned current Date configuration.
+* @retval None
+*/
+void RTC_GetDate(RTC_Format_TypeDef RTC_Format,
+                 RTC_DateTypeDef* RTC_DateStruct)
+{
+  uint8_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_FORMAT(RTC_Format));
+
+  /* Fill the structure fields with the read parameters */
+  (void) (RTC->TR1) ;
+  RTC_DateStruct->RTC_Date = (uint8_t)(RTC->DR1);
+  tmpreg = (uint8_t)RTC->DR2;
+  RTC_DateStruct->RTC_Year = (uint8_t)(RTC->DR3);
+
+
+  RTC_DateStruct->RTC_Month = (RTC_Month_TypeDef)(tmpreg & (uint8_t)(RTC_DR2_MT | RTC_DR2_MU));
+  RTC_DateStruct->RTC_WeekDay = (RTC_Weekday_TypeDef)((uint8_t)((uint8_t)tmpreg & (uint8_t)(RTC_DR2_WDU)) >> (uint8_t)5);
+
+  /* Check the input parameters format */
+  if (RTC_Format == RTC_Format_BIN)
+  {
+    /* Convert the structure parameters to Binary format */
+    RTC_DateStruct->RTC_Year = (uint8_t)Bcd2ToByte((uint8_t)RTC_DateStruct->RTC_Year);
+    RTC_DateStruct->RTC_Month = (RTC_Month_TypeDef)Bcd2ToByte((uint8_t)RTC_DateStruct->RTC_Month);
+    RTC_DateStruct->RTC_Date = (uint8_t)(Bcd2ToByte((uint8_t)RTC_DateStruct->RTC_Date));
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Group3 Alarms configuration functions
+ *  @brief   Alarms (Alarm A and Alarm B) configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+              Alarms (Alarm A and Alarm B) configuration functions
+ ===============================================================================  
+
+  This section provide functions allowing to program and read the RTC Alarms.
+
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Sets the RTC Alarm configuration.
+  * @note   Before configuring the Alarm settings, the Alarm Unit must be disabled
+  *         (if enabled) using RTC_AlarmCmd(DISABLE) function.
+  * @param  RTC_Format: specifies the format of the entered parameters.
+  *         This parameter can be one of the @ref RTC_Format_TypeDef enumeration.
+  * @param  RTC_AlarmStruct:  pointer to a  @ref RTC_AlarmTypeDef structure that
+  *         contains the Alarm configuration information for the RTC.
+  * @retval None.
+  */
+void RTC_SetAlarm(RTC_Format_TypeDef RTC_Format,
+                  RTC_AlarmTypeDef* RTC_AlarmStruct)
+{
+  uint8_t tmpreg1 = 0;
+  uint8_t tmpreg2 = 0;
+  uint8_t tmpreg3 = 0;
+  uint8_t tmpreg4 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_ALARM_MASK(RTC_AlarmStruct->RTC_AlarmMask));
+  assert_param(IS_RTC_FORMAT(RTC_Format));
+  assert_param(IS_RTC_H12(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12));
+  assert_param(IS_RTC_ALARM_DATEWEEKDAY_SEL(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel));
+
+
+  if (RTC_Format == RTC_Format_BIN)
+  {
+    /* Check Hour Format (24h or 12h)*/
+    if ((RTC->CR1 & RTC_CR1_FMT) != RESET)
+    {
+      assert_param(IS_RTC_HOUR12_MAX(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours));
+      assert_param(IS_RTC_HOUR12_MIN(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours));
+    }
+    else
+    {
+      assert_param(IS_RTC_HOUR24(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours));
+    }
+    assert_param(IS_RTC_MINUTES(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes));
+    assert_param(IS_RTC_SECONDS(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds));
+  }
+  else
+  {
+    /* Check Hour Format (24h or 12h)*/
+    if ((RTC->CR1 & RTC_CR1_FMT) != RESET)
+    {
+      assert_param(IS_RTC_HOUR12_MAX(Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours)));
+      assert_param(IS_RTC_HOUR12_MIN(Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours)));
+    }
+    else
+    {
+      assert_param(IS_RTC_HOUR24(Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours)));
+    }
+
+    assert_param(IS_RTC_MINUTES(Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes)));
+
+    assert_param(IS_RTC_SECONDS(Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)));
+
+  }
+
+  /* if Date/Weekday field is not masked */
+  if ((RTC_AlarmStruct->RTC_AlarmMask & RTC_AlarmMask_DateWeekDay) == RESET )
+  {
+    if (RTC_AlarmStruct->RTC_AlarmDateWeekDaySel == RTC_AlarmDateWeekDaySel_WeekDay)
+    {
+      assert_param(IS_RTC_WEEKDAY(RTC_AlarmStruct->RTC_AlarmDateWeekDay));
+    }
+    else
+    {
+      assert_param(IS_RTC_DATE_MIN(RTC_AlarmStruct->RTC_AlarmDateWeekDay));
+      assert_param(IS_RTC_DATE_MAX(RTC_AlarmStruct->RTC_AlarmDateWeekDay));
+    }
+  }
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+
+  /* Check the input parameters format & Configure the Alarm register */
+  if (RTC_Format != RTC_Format_BIN)
+  {
+    tmpreg1 = (uint8_t)((uint8_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds) | \
+                        (uint8_t)((uint8_t)(RTC_AlarmStruct->RTC_AlarmMask) & (uint8_t)RTC_ALRMAR1_MSK1));
+
+    tmpreg2 = (uint8_t)((uint8_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes) | \
+                        (uint8_t)((uint8_t)(RTC_AlarmStruct->RTC_AlarmMask << 1) & (uint8_t)RTC_ALRMAR2_MSK2));
+
+    tmpreg3 = (uint8_t)((uint8_t)((uint8_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours) | \
+                                  (uint8_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12)) | \
+                        (uint8_t)((uint8_t)(RTC_AlarmStruct->RTC_AlarmMask << 2) & (uint8_t)RTC_ALRMAR3_MSK3));
+
+    tmpreg4 = (uint8_t)((uint8_t)((uint8_t)(RTC_AlarmStruct->RTC_AlarmDateWeekDay) | \
+                                  (uint8_t)(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel)) | \
+                        (uint8_t)((uint8_t)(RTC_AlarmStruct->RTC_AlarmMask << 3) & (uint8_t)RTC_ALRMAR4_MSK4));
+
+  }
+  else
+  {
+    tmpreg1 = (uint8_t)((ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)) | \
+                        (uint8_t)(RTC_AlarmStruct->RTC_AlarmMask & RTC_ALRMAR1_MSK1));
+
+    tmpreg2 = (uint8_t)((ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes)) | \
+                        (uint8_t)((uint8_t)(RTC_AlarmStruct->RTC_AlarmMask << 1) & (uint8_t)RTC_ALRMAR2_MSK2));
+
+    tmpreg3 = (uint8_t)((uint8_t)((ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours)) | \
+                                  (uint8_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12)) | \
+                        (uint8_t)((uint8_t)(RTC_AlarmStruct->RTC_AlarmMask << 2) & (uint8_t)RTC_ALRMAR3_MSK3));
+
+    tmpreg4 = (uint8_t)((uint8_t)((ByteToBcd2(RTC_AlarmStruct->RTC_AlarmDateWeekDay)) | \
+                                  (uint8_t)(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel)) | \
+                        (uint8_t)((uint8_t)(RTC_AlarmStruct->RTC_AlarmMask << 3) & (uint8_t)(RTC_ALRMAR4_MSK4)));
+  }
+
+  /* Configure the Alarm register */
+  RTC->ALRMAR1 = tmpreg1;
+  RTC->ALRMAR2 = tmpreg2;
+  RTC->ALRMAR3 = tmpreg3;
+  RTC->ALRMAR4 = tmpreg4;
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF; 
+}
+
+/**
+* @brief  Fills each RTC_AlarmStruct member with its default value
+*         (Time = 00h:00mn:00sec / Date = 1st day of the month/Mask =
+*         all fields are masked).
+* @param  RTC_AlarmStruct: pointer to a @ref RTC_AlarmTypeDef structure which
+*         will be initialized.
+* @retval None
+*/
+void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct)
+{
+  /* Alarm Time Settings : Time = 00h:00mn:00sec */
+  RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = RTC_H12_AM;
+  RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = 0;
+  RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = 0;
+  RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = 0;
+
+  /* Alarm Date Settings : Date = 1st day of the month*/
+  RTC_AlarmStruct->RTC_AlarmDateWeekDaySel = RTC_AlarmDateWeekDaySel_Date;
+  RTC_AlarmStruct->RTC_AlarmDateWeekDay = 1;
+
+  /* Alarm Masks Settings : Mask =  all fields are masked*/
+  RTC_AlarmStruct->RTC_AlarmMask = RTC_AlarmMask_All;
+}
+/**
+  * @brief  Gets the RTC Alarm configuration.
+  * @param  RTC_Format: specifies the format of the entered parameters.
+  *         This parameter can be one of the @ref RTC_Format_TypeDef enumeration.
+  * @param  RTC_AlarmStruct:  pointer to a  @ref RTC_AlarmTypeDef structure that
+  *         will contain the Alarm configuration information of  the RTC.
+  * @retval None
+  */
+void RTC_GetAlarm(RTC_Format_TypeDef RTC_Format,
+                  RTC_AlarmTypeDef* RTC_AlarmStruct)
+{
+  uint8_t tmpreg1 = 0;
+  uint8_t tmpreg2 = 0;
+  uint8_t tmpreg3 = 0;
+  uint8_t tmpreg4 = 0;
+  uint8_t alarmmask = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_FORMAT(RTC_Format));
+
+  /* Get Alarm registers data */
+  tmpreg1 = (uint8_t)RTC->ALRMAR1;
+  tmpreg2 = (uint8_t)RTC->ALRMAR2;
+  tmpreg3 = (uint8_t)RTC->ALRMAR3;
+  tmpreg4 = (uint8_t)RTC->ALRMAR4;
+
+  /* Fill the structure with the read parameters */
+  RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = (uint8_t)((uint8_t)tmpreg1 & (uint8_t)((uint8_t)RTC_ALRMAR1_ST | (uint8_t)RTC_ALRMAR1_SU));
+  alarmmask = (uint8_t)(tmpreg1 & RTC_ALRMAR1_MSK1);
+
+  /* Fill the structure with the read parameters */
+  RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = (uint8_t)((uint8_t)tmpreg2 & (uint8_t)((uint8_t)RTC_ALRMAR2_MNT | (uint8_t)RTC_ALRMAR2_MNU));
+  alarmmask = (uint8_t)((alarmmask) | (uint8_t)((uint8_t)(tmpreg2 & RTC_ALRMAR2_MSK2) >> 1));
+
+  /* Fill the structure with the read parameters */
+  RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = (uint8_t)((uint8_t)tmpreg3 & (uint8_t)((uint8_t)RTC_ALRMAR3_HT | (uint8_t)RTC_ALRMAR3_HU));
+  RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = (RTC_H12_TypeDef)((uint8_t)tmpreg3 & (uint8_t)RTC_ALRMAR3_PM);
+  alarmmask = (uint8_t)((alarmmask) | (uint8_t)((uint8_t)((uint8_t)tmpreg3 & (uint8_t)RTC_ALRMAR3_MSK3) >> 2));
+
+  /* Fill the structure with the read parameters */
+  RTC_AlarmStruct->RTC_AlarmDateWeekDay = (uint8_t)((uint8_t)tmpreg4 & (uint8_t)((uint8_t)RTC_ALRMAR4_DT | (uint8_t)RTC_ALRMAR4_DU));
+  RTC_AlarmStruct->RTC_AlarmDateWeekDaySel = (RTC_AlarmDateWeekDaySel_TypeDef)((uint8_t)tmpreg4 & (uint8_t)RTC_ALRMAR4_WDSEL);
+  alarmmask = (uint8_t)((alarmmask) | (uint8_t)((uint8_t)((uint8_t)tmpreg4 & RTC_ALRMAR4_MSK4) >> 3));
+
+  RTC_AlarmStruct->RTC_AlarmMask = alarmmask;
+
+  if (RTC_Format == RTC_Format_BIN)
+  {
+    RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours);
+    RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes);
+    RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds);
+    RTC_AlarmStruct->RTC_AlarmDateWeekDay = Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay);
+  }
+}
+
+/**
+  * @brief  Enables or disables the RTC Alarm.
+  * @param  NewState: new state of the alarm. This parameter can be: ENABLE or DISABLE.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC Alarm is enabled/disabled
+  *          - ERROR: RTC Alarm is not enabled/disabled
+  */
+ErrorStatus RTC_AlarmCmd(FunctionalState NewState)
+{
+  __IO uint16_t alrawfcount = 0;
+  ErrorStatus status = ERROR;
+  uint8_t temp1 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* Configure the Alarm state */
+  if (NewState != DISABLE)
+  { /*Enable the Alarm*/
+    RTC->CR2 |= (uint8_t)(RTC_CR2_ALRAE);
+    status = SUCCESS;
+  }
+  else
+  {  /* Disable the Alarm */
+    RTC->CR2 &= (uint8_t)~(RTC_CR2_ALRAE) ;
+
+    /* Wait until ALRxWF flag is set */
+    temp1 = (uint8_t)(RTC->ISR1 & RTC_ISR1_ALRAWF);
+    while ((alrawfcount != ALRAWF_TIMEOUT) && (temp1 == RESET))
+    {
+      alrawfcount++;
+    }
+
+    if ((RTC->ISR1 &  RTC_ISR1_ALRAWF) == RESET)
+    {
+      status = ERROR;
+    }
+    else
+    {
+      status = SUCCESS;
+    }
+  }
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF; 
+
+  /* Return the status*/
+  return (ErrorStatus)status;
+}
+/**
+* @brief  Configure the RTC Alarm Subseconds value and mask.
+* @param  RTC_AlarmSubSecondValue: specifies the Subseconds value.
+*         This parameter can be a value from 0 to 0x7FFF.
+* @param  RTC_AlarmSubSecondMask:  specifies the Subseconds Mask.
+*         This parameter can be one of the @ref RTC_AlarmSubSecondMask_TypeDef enumeration.
+* @retval An ErrorStatus enumeration value:
+*          - SUCCESS: Alarm Subseconds value and mask are configured
+*          - ERROR: Alarm Subseconds value and mask are  not configured
+*/
+ErrorStatus RTC_AlarmSubSecondConfig(uint16_t RTC_AlarmSubSecondValue,
+                                     RTC_AlarmSubSecondMask_TypeDef RTC_AlarmSubSecondMask)
+{
+  uint8_t alarmstatus = 0;
+  ErrorStatus status = ERROR;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_ALARM_SS_VALUE(RTC_AlarmSubSecondValue));
+  assert_param(IS_RTC_ALARM_SS_MASK(RTC_AlarmSubSecondMask));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* Check if the initialization mode is not set */
+  if ((RTC->ISR1 & RTC_ISR1_INITF) == RESET)
+  {
+    /* save  Alarm status */
+    alarmstatus = (uint8_t)(RTC->CR2 | RTC_CR2_ALRAE);
+
+    /* Disable the Alarm */
+    RTC->CR2 &= (uint8_t)~(RTC_CR2_ALRAE);
+
+    /* Configure the Alarm register */
+    RTC->ALRMASSRH = (uint8_t)(RTC_AlarmSubSecondValue >> 8);
+    RTC->ALRMASSRL = (uint8_t)(RTC_AlarmSubSecondValue);
+    RTC->ALRMASSMSKR = (uint8_t)RTC_AlarmSubSecondMask;
+
+    /* restore the saved  Alarm status */
+    RTC->CR2 |= alarmstatus;
+
+    status = SUCCESS;
+  }
+  else
+  {
+    status = ERROR;
+  }
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF; 
+
+  return (ErrorStatus)status;
+}
+
+
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Group4 WakeUp Timer configuration functions
+ *  @brief   WakeUp Timer configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+                     WakeUp Timer configuration functions
+ ===============================================================================  
+
+  This section provide functions allowing to program and read the RTC WakeUp.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Configures the RTC Wakeup clock source.
+  * @pre    Before configuring the wakeup unit Clock source, the wake up Unit must
+  *         be disabled (if enabled) using RTC_WakeUpCmd(Disable) .
+  * @param  RTC_WakeupClockSrc: specifies the Wakeup clock source,
+  *         this parameter  can be one of the @ref RTC_WakeupClockSrc_TypeDef enumeration.
+  * @retval None
+  */
+void RTC_WakeUpClockConfig(RTC_WakeUpClock_TypeDef RTC_WakeUpClock)
+{
+
+  /* Check the parameters */
+  assert_param(IS_RTC_WAKEUP_CLOCK(RTC_WakeUpClock));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* Disable the Wakeup timer in RTC_CR2 register */
+  RTC->CR2 &= (uint8_t)~RTC_CR2_WUTE;
+
+  /* Clear the Wakeup Timer clock source bits in CR1 register */
+  RTC->CR1 &= (uint8_t)~RTC_CR1_WUCKSEL;
+
+  /* Configure the clock source */
+  RTC->CR1 |= (uint8_t)RTC_WakeUpClock;
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF; 
+}
+
+/**
+  * @brief  Sets the RTC Wakeup counter.
+  * @note   Before configuring the wakeup unit counter, the wake up Unit must be
+  *         disabled (if enabled) using RTC_WakeUpCmd(Disable).
+  * @param  RTC_WakeupCounter: specifies the Wake up counter,
+  *         This parameter can be a value from 0x0000 to 0xFFFF.
+  * @retval None.
+  */
+void RTC_SetWakeUpCounter(uint16_t RTC_WakeupCounter)
+{
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+
+  /* Configure the Wakeup Timer counter */
+  RTC->WUTRH = (uint8_t)(RTC_WakeupCounter >> 8);
+  RTC->WUTRL = (uint8_t)(RTC_WakeupCounter);
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF; 
+}
+
+/**
+  * @brief  Returns the RTC Wakeup timer counter value.
+  * @param  None.
+  * @retval RTC Wakeup Counter value.
+  */
+uint16_t RTC_GetWakeUpCounter(void)
+{
+  uint16_t tmpreg = 0;
+
+  /* Get the counter value */
+  tmpreg = ((uint16_t)RTC->WUTRH) << 8;
+  tmpreg |= RTC->WUTRL;
+
+  /* return RTC Wakeup Counter value*/
+  return (uint16_t)tmpreg;
+}
+
+/**
+  * @brief  Enables or Disables the RTC Wakeup Unit.
+  * @param  NewState: new state of the Wakeup Unit. This parameter can 
+  *                   be: ENABLE or DISABLE.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS : RTC Wakeup Unit is enabled/disabled
+  *          - ERROR    : RTC Wakeup Unit is not enabled/disabled
+  */
+ErrorStatus RTC_WakeUpCmd(FunctionalState NewState)
+{
+  ErrorStatus status = ERROR;
+  uint16_t wutwfcount = 0;
+
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the Wakeup Timer */
+    RTC->CR2 |= (uint8_t)RTC_CR2_WUTE;
+
+    status = SUCCESS;
+  }
+  else
+  {
+    /* Disable the Wakeup Timer */
+    RTC->CR2 &= (uint8_t)~RTC_CR2_WUTE;
+
+    /* Wait until WUTWF flag is set */
+    while (((RTC->ISR1 & RTC_ISR1_WUTWF) == RESET) && ( wutwfcount != WUTWF_TIMEOUT))
+    {
+      wutwfcount++;
+    }
+
+    /* Check WUTWF flag is set or not */
+    if ((RTC->ISR1 & RTC_ISR1_WUTWF) == RESET)
+    {
+      status = ERROR;
+    }
+    else
+    {
+      status = SUCCESS;
+    }
+  }
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF; 
+
+  /* Return the status*/
+  return (ErrorStatus)status;
+}
+
+
+
+
+
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Group5 Daylight Saving configuration functions
+ *  @brief   Daylight Saving configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+                    Daylight Saving configuration functions
+ ===============================================================================  
+
+  This section provide functions allowing to configure the RTC DayLight Saving.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Adds or subtracts one hour from the current time depending on
+  *         the daylight saving parameter.
+  * @param  RTC_DayLightSaving: the day light saving Mode
+  *         This parameter can be one of the @ref RTC_DayLightSaving_TypeDef 
+  *         enumeration.
+  * @param  RTC_StoreOperation: the day light saving store operation
+  *         This parameter can be one of the @ref RTC_StoreOperation_TypeDef 
+  *         enumeration.
+  * @retval None
+  */
+void RTC_DayLightSavingConfig(RTC_DayLightSaving_TypeDef RTC_DayLightSaving,
+                              RTC_StoreOperation_TypeDef RTC_StoreOperation)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_DAYLIGHT_SAVING(RTC_DayLightSaving));
+  assert_param(IS_RTC_STORE_OPERATION(RTC_StoreOperation));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* Clear the bits to be configured */
+  RTC->CR3 &= (uint8_t)~(RTC_CR3_BCK);
+
+  /* Configure the RTC_CR3 register */
+  RTC->CR3 |= (uint8_t)((uint8_t)RTC_DayLightSaving | (uint8_t)RTC_StoreOperation);
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF; 
+}
+
+/**
+  * @brief  Returns the stored operation.
+  * @param  None
+  * @retval the store operation, this parameter can be one of
+  *         the @ref RTC_StoreOperation_TypeDef enumeration.
+  */
+RTC_StoreOperation_TypeDef  RTC_GetStoreOperation(void)
+{
+  /* Return the stored operation*/
+  return (RTC_StoreOperation_TypeDef)(RTC->CR3 & RTC_CR3_BCK);
+}
+
+
+
+
+
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Group6 Output pin Configuration function
+ *  @brief   Output pin Configuration function 
+ *
+@verbatim   
+ ===============================================================================
+                         Output pin Configuration function
+ ===============================================================================  
+
+  This section provide functions allowing to configure the RTC Output source.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Configures the RTC output for the output pin (RTC_ALARM output).
+  * @param  RTC_OutputSel: Specifies which signal will be mapped to the output.
+  *         This parameter can be one parameter from the 
+  *         @ref RTC_OutputSel_TypeDef enumeration.
+  * @param  RTC_OutputPolarity: Specifies the polarity of the output signal.
+  *         This parameter can be one parameter from the 
+  *         @ref RTC_OutputPolarity_TypeDef enumeration.
+  * @retval None
+  */
+void RTC_OutputConfig(RTC_Output_TypeDef RTC_Output,
+                      RTC_OutputPolarity_TypeDef RTC_OutputPolarity)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_OUTPUT_SEL(RTC_Output));
+  assert_param(IS_RTC_OUTPUT_POL(RTC_OutputPolarity));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* Clear the bits to be configured */
+  RTC->CR3 &= (uint8_t)~(RTC_CR3_OSEL | RTC_CR3_POL);
+
+  /* Configure the output selection and polarity */
+  RTC->CR3 |= (uint8_t)((uint8_t)RTC_Output | (uint8_t)RTC_OutputPolarity);
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF; 
+}
+
+
+
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Group7 Output pin Configuration function
+ *  @brief   Output pin Configuration function 
+ *
+@verbatim   
+ ===============================================================================
+                         Output pin Configuration function
+ ===============================================================================  
+
+  This section provide functions allowing to configure the RTC Output source.
+
+@endverbatim
+  * @{
+  */
+/**
+* @brief  Configures the Synchronization Shift Control Settings.
+* @param  RTC_ShiftAdd1S : Select to add or not 1 second to the time Calendar.
+*         This parameter can be one parameter from the @ref RTC_ShiftAdd1S_TypeDef
+*         enumeration.
+* @param  RTC_ShiftSubFS: Select the number of Second Fractions to Substitute.
+*         This parameter can be one any value from 0 to 0x7FFF.
+ * @retval An ErrorStatus enumeration value:
+*          - SUCCESS: RTC Shift registers are configured
+*          - ERROR: RTC Shift registers are not configured
+*/
+ErrorStatus RTC_SynchroShiftConfig(RTC_ShiftAdd1S_TypeDef RTC_ShiftAdd1S,
+                                   uint16_t RTC_ShiftSubFS)
+{
+  uint8_t shiftrhreg = 0;
+  ErrorStatus status = ERROR;
+  uint16_t shpfcount = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_SHIFT_ADD1S(RTC_ShiftAdd1S));
+  assert_param(IS_RTC_SHIFT_SUBFS(RTC_ShiftSubFS));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* Check if a Shift is pending*/
+  if ((RTC->ISR1 & RTC_ISR1_SHPF) != RESET)
+  {
+    /* wait until the shift is completed*/
+    while (((RTC->ISR1 & RTC_ISR1_SHPF) != RESET) && (shpfcount != SHPF_TIMEOUT))
+    {
+      shpfcount++;
+    }
+  }
+
+  /* check if the Shift pending is completed or if there is no Shift operation at all*/
+  if ((RTC->ISR1 & RTC_ISR1_SHPF) == RESET)
+  {
+    /* Configure the Shift settings */
+    shiftrhreg = (uint8_t)((uint8_t)(RTC_ShiftSubFS >> 8) | (uint8_t)(RTC_ShiftAdd1S));
+    RTC->SHIFTRH = (uint8_t)(shiftrhreg);
+    RTC->SHIFTRL = (uint8_t)(RTC_ShiftSubFS);
+
+    status = SUCCESS;
+  }
+  else
+  {
+    status = ERROR;
+  }
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF; 
+
+  return (ErrorStatus)(status);
+}
+
+
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Group8 Output pin Configuration function
+ *  @brief   Output pin Configuration function 
+ *
+@verbatim   
+ ===============================================================================
+                         Output pin Configuration function
+ ===============================================================================  
+
+  This section provide functions allowing to configure the RTC Output source.
+
+@endverbatim
+  * @{
+  */
+/**
+* @brief  Configures the Smooth Calibration Settings.
+* @param  RTC_SmoothCalibPeriod : Select the Smooth Calibration Period.
+*         This parameter can be one parameter from
+*         the @ref RTC_SmoothCalibPeriod_TypeDef enumeration.
+* @param  RTC_SmoothCalibPlusPulses : Select to Set or reset the CALP bit.
+*         This parameter can be one parameter from the
+*         @ref RTC_SmoothCalibPlusPulses_TypeDef enumeration.
+* @param  RTC_SmouthCalibMinusPulsesValue: Select the value of CALM[8:0] bits.
+*         This parameter can be one any value from 0 to 0x01FF.
+* @retval An ErrorStatus enumeration value:
+*          - SUCCESS: RTC Calib registers are configured
+*          - ERROR: RTC Calib registers are not configured
+*/
+ErrorStatus RTC_SmoothCalibConfig(RTC_SmoothCalibPeriod_TypeDef RTC_SmoothCalibPeriod,
+                                  RTC_SmoothCalibPlusPulses_TypeDef RTC_SmoothCalibPlusPulses,
+                                  uint16_t RTC_SmouthCalibMinusPulsesValue)
+{
+  ErrorStatus status = ERROR;
+  uint16_t recalpfcount = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(RTC_SmoothCalibPeriod));
+  assert_param(IS_RTC_SMOOTH_CALIB_PLUS(RTC_SmoothCalibPlusPulses));
+  assert_param(IS_RTC_SMOOTH_CALIB_MINUS(RTC_SmouthCalibMinusPulsesValue));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* check if a calibration is pending*/
+  if ((RTC->ISR1 & RTC_ISR1_RECALPF) != RESET)
+  {
+    /* wait until the Calibration is completed*/
+    while (((RTC->ISR1 & RTC_ISR1_RECALPF) != RESET) && (recalpfcount != RECALPF_TIMEOUT))
+    {
+      recalpfcount++;
+    }
+  }
+
+  /* check if the calibration pending is completed or if there is 
+     no calibration operation at all*/
+  if ((RTC->ISR1 & RTC_ISR1_RECALPF) == RESET)
+  {
+    /* Configure the Smooth calibration settings */
+    RTC->CALRH = (uint8_t)((uint8_t)((uint8_t)RTC_SmoothCalibPeriod | \
+                           (uint8_t)RTC_SmoothCalibPlusPulses) | \
+                           (uint8_t)((uint16_t)RTC_SmouthCalibMinusPulsesValue >> 8));
+    RTC->CALRL = (uint8_t)(RTC_SmouthCalibMinusPulsesValue);
+
+    status = SUCCESS;
+  }
+  else
+  {
+    status = ERROR;
+  }
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF; 
+
+  return (ErrorStatus)(status);
+}
+
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Group9 Digital Calibration configuration functions
+ *  @brief   Digital Calibration configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+                  Calibration configuration functions
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+/**
+* @brief  Configure the Calibration Pin-out (RTC_CALIB) Selection (1Hz or 512Hz).
+* @param  RTC_CalibOutput : Select the Calibration output Selection .
+*         This parameter can be one parameter from the
+*         @ref RTC_CalibOutput_TypeDef enumeration.
+* @retval None
+*/
+void RTC_CalibOutputConfig(RTC_CalibOutput_TypeDef RTC_CalibOutput)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_CALOUTPUT_SELECT(RTC_CalibOutput));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  if (RTC_CalibOutput != RTC_CalibOutput_512Hz)
+  {
+    /* Enable the RTC clock output */
+    RTC->CR3 |= (uint8_t)RTC_CR3_COSEL;
+  }
+  else
+  {
+    /* Disable the RTC clock output */
+    RTC->CR3 &= (uint8_t)~RTC_CR3_COSEL;
+  }
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF; 
+}
+
+/**
+* @brief  Enables or disables the RTC clock to be output through the relative pin.
+* @param  NewState: new state of the RTC Calibration output
+  *         This parameter can be: ENABLE or DISABLE.
+* @retval None
+*/
+void RTC_CalibOutputCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the RTC clock output */
+    RTC->CR3 |= (uint8_t)RTC_CR3_COE;
+  }
+  else
+  {
+    /* Disable the RTC clock output */
+    RTC->CR3 &= (uint8_t)~RTC_CR3_COE;
+  }
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF; 
+}
+
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Group10 Tampers configuration functions
+ *  @brief   Tampers configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+                       Tampers configuration functions
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+* @brief  Configures the Tamper Sensitive Level.
+* @param  RTC_Tamper: Select the tamper to configure.
+*         This parameter can be one parameter from the @ref RTC_Tamper_TypeDef
+*         enumeration.
+* @param  RTC_TamperLevel: Select the tamper Sensitive Level.
+*         This parameter can be one parameter from the 
+*         @ref RTC_TamperLevel_TypeDef enumeration.
+* @retval None
+*/
+void RTC_TamperLevelConfig(RTC_Tamper_TypeDef RTC_Tamper,
+                           RTC_TamperLevel_TypeDef RTC_TamperLevel)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_TAMPER((uint8_t)RTC_Tamper));
+  assert_param(IS_RTC_TAMPER_LEVEL(RTC_TamperLevel));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  if (RTC_TamperLevel != RTC_TamperLevel_Low)
+  {
+    /* Enable the selected Tampers */
+    RTC->TCR1 |= (uint8_t)(RTC_Tamper << 1);
+  }
+  else
+  {
+    /* Disable the selected Tampers */
+    RTC->TCR1 &= (uint8_t)~(uint8_t)(RTC_Tamper << 1);
+  }
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF; 
+}
+/**
+  * @brief  Configures the Tampers Filter.
+  * @param  RTC_TamperFilter: Specifies the tampers filter.
+  *         This parameter can be one parameter from the
+  *         @ref RTC_TamperFilter_TypeDef enumeration.
+  * @retval None
+  */
+void RTC_TamperFilterConfig(RTC_TamperFilter_TypeDef RTC_TamperFilter)
+{
+
+  /* Check the parameters */
+  assert_param(IS_RTC_TAMPER_FILTER(RTC_TamperFilter));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /*clear flags before configuration */
+  RTC->TCR2 &= (uint8_t)~(RTC_TCR2_TAMPFLT);
+
+  /* Configure the RTC_TCR register */
+  RTC->TCR2 |= (uint8_t)RTC_TamperFilter;
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF; 
+
+}
+
+/**
+  * @brief  Configures the Tampers Sampling Frequency.
+  * @param  RTC_TamperSamplingFreq: Specifies the tampers Sampling Frequency.
+  *         This parameter can be one parameter from the
+  *         @ref RTC_TamperSamplingFreq_TypeDef enumeration.
+  * @retval None
+  */
+void RTC_TamperSamplingFreqConfig(RTC_TamperSamplingFreq_TypeDef RTC_TamperSamplingFreq)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(RTC_TamperSamplingFreq));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* Clear flags before configuration */
+  RTC->TCR2 &= (uint8_t)~(RTC_TCR2_TAMPFREQ);
+
+  /* Configure the RTC_TCR register */
+  RTC->TCR2 |= (uint8_t)RTC_TamperSamplingFreq;
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF; 
+}
+
+/**
+* @brief  Configures the Tampers Pins input Precharge Duration.
+* @param  RTC_TamperPrechargeDuration: Specifies the Tampers Pins input
+*         Precharge Duration.
+*         This parameter can be one parameter from the
+*         @ref RTC_TamperPrechargeDuration_TypeDef enumeration.
+* @retval None
+*/
+void RTC_TamperPinsPrechargeDuration(RTC_TamperPrechargeDuration_TypeDef RTC_TamperPrechargeDuration)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_TAMPER_PINS_PRECHAR_DURATION(RTC_TamperPrechargeDuration));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* Clear the tampers  pull-up  and precharge/discharge duration Old settings*/
+  RTC->TCR2 &= (uint8_t)~(RTC_TCR2_TAMPPUDIS | RTC_TCR2_TAMPPRCH);
+
+  /* Configure the Tampers Precharge Duration  and pull-up New settings*/
+  RTC->TCR2 |= (uint8_t)RTC_TamperPrechargeDuration;
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF; 
+}
+
+
+/**
+* @brief  Enables or Disables the Tamper detection.
+* @param  RTC_Tamper: Select the tamper to configure.
+*         This parameter can be one parameter from the @ref RTC_Tamper_TypeDef
+*         enumeration.
+* @param  NewState: new state of the tamper pin.
+  *         This parameter can be: ENABLE or DISABLE.
+* @retval None
+*/
+void RTC_TamperCmd(RTC_Tamper_TypeDef RTC_Tamper,
+                   FunctionalState NewState)
+{
+
+  /* Check the parameters */
+  assert_param(IS_RTC_TAMPER((uint8_t)RTC_Tamper));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected Tampers */
+    RTC->TCR1 |= (uint8_t)RTC_Tamper;
+  }
+  else
+  {
+    /* Disable the selected Tampers */
+    RTC->TCR1 &= (uint8_t)~RTC_Tamper;
+  }
+
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF; 
+}
+
+
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Group11 Interrupts and flags management functions
+ *  @brief   Interrupts and flags management functions  
+ *
+@verbatim   
+ ===============================================================================
+                       Interrupts and flags management functions
+ ===============================================================================  
+ 
+ To enable the RTC Alarm interrupt, the following sequence is required:
+   - Configure the RTC to generate RTC alarm (Alarm A) using the RTC_SetAlarm() 
+     and RTC_AlarmCmd() functions.
+
+ To enable the RTC Wakeup interrupt, the following sequence is required:
+   - Configure the RTC to generate the RTC wakeup timer event using the 
+     RTC_WakeUpClockConfig(), RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions.
+
+ To enable the RTC Tamper interrupt, the following sequence is required:
+   - Configure the RTC to detect the RTC tamper event using the 
+     RTC_TamperTriggerConfig() and RTC_TamperCmd() functions.
+
+
+
+@endverbatim
+  * @{
+  */
+/**
+* @brief  Enables or Disables the specified RTC interrupts.
+* @param  RTC_IT: specifies the RTC interrupt sources to be enabled or disabled.
+*         This parameter can be any combination of the following values:
+*         @arg RTC_IT_ALRA:  Alarm A interrupt
+*         @arg RTC_IT_TAMP:  Tampers interrupt
+*         @arg RTC_IT_WUT:  WakeUp Timer interrupt
+* @param  NewState: new state of the specified RTC interrupts.
+  *         This parameter can be: ENABLE or DISABLE.
+* @retval None
+*/
+void RTC_ITConfig(RTC_IT_TypeDef RTC_IT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_CONFIG_IT(RTC_IT));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the Interrupts */
+    RTC->CR2 |= (uint8_t)((uint16_t)RTC_IT & (uint16_t)0x00F0);
+    RTC->TCR1 |= (uint8_t)((uint16_t)RTC_IT & RTC_TCR1_TAMPIE);
+  }
+  else
+  {
+    /* Disable the Interrupts */
+    RTC->CR2  &= (uint8_t)~(uint8_t)((uint16_t)RTC_IT & (uint16_t)0x00F0);
+    RTC->TCR1 &= (uint8_t)~(uint8_t)((uint16_t)RTC_IT & (uint16_t)RTC_TCR1_TAMPIE);
+  }
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF; 
+}
+/**
+* @brief  Checks whether the specified RTC flag is set or not.
+* @param  RTC_FLAG: specifies the flag to check.
+*         This parameter can be one of the @ref RTC_Flag_TypeDef enumeration.
+* @retval Status of RTC_FLAG (SET or RESET)
+*/
+FlagStatus RTC_GetFlagStatus(RTC_Flag_TypeDef RTC_FLAG)
+{
+  FlagStatus flagstatus = RESET;
+  uint16_t tmpreg1 = 0;
+  uint16_t tmpreg2 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_GET_FLAG(RTC_FLAG));
+
+  /* Get all the flags */
+  tmpreg2 = (uint16_t)((uint16_t)RTC->ISR1 << 8);
+  tmpreg1 = (uint16_t)((uint16_t)((uint16_t)(RTC->ISR2)) | tmpreg2);
+
+  /* Return the status of the flag */
+  if ((tmpreg1 & (uint16_t)RTC_FLAG) != RESET)
+  {
+    flagstatus = SET;
+  }
+  else
+  {
+    flagstatus = RESET;
+  }
+  return (FlagStatus)flagstatus;
+}
+
+/**
+* @brief  Clears the RTC's pending flags.
+* @param  RTC_FLAG: specifies the RTC flag to clear.
+*         This parameter can be any combination of the @ref RTC_Flag_TypeDef
+*         enumeration.
+* @retval None
+*/
+void RTC_ClearFlag(RTC_Flag_TypeDef RTC_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_CLEAR_FLAG((uint16_t)RTC_FLAG));
+
+  /* Clear the Flags in the RTC_ISR registers */
+  RTC->ISR2 = (uint8_t)~((uint8_t)RTC_FLAG) ;
+  RTC->ISR1 = (uint8_t)(((uint8_t)~(uint8_t)((uint16_t)RTC_FLAG >> (uint8_t)8)) & ((uint8_t)~(uint8_t)(RTC_ISR1_INIT)));
+}
+
+/**
+* @brief  Checks whether the specified RTC interrupt has occurred or not.
+* @param  RTC_IT: specifies the RTC interrupt source to check.
+*         This parameter can be one of the @ref RTC_IT_TypeDef enumeration.
+* @retval Status of RTC_IT (SET or RESET).
+*/
+ITStatus RTC_GetITStatus(RTC_IT_TypeDef RTC_IT)
+{
+  ITStatus itstatus = RESET;
+  uint8_t enablestatus = 0, tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_GET_IT(RTC_IT));
+
+  /* Get the Interrupt enable Status */
+  enablestatus = (uint8_t)(RTC->CR2 & (uint16_t)RTC_IT);
+
+  /* Get the Interrupt pending bit */
+  tmpreg = (uint8_t)(RTC->ISR2 & (uint8_t)((uint16_t)RTC_IT >> 4));
+
+  /* Get the status of the Interrupt */
+  if ((enablestatus != (uint8_t)RESET) && (tmpreg != (uint8_t)RESET))
+  {
+    itstatus = SET;
+  }
+  else
+  {
+    itstatus = RESET;
+  }
+
+  return (ITStatus)itstatus;
+}
+
+/**
+* @brief  Clears the RTC's interrupt pending bits.
+* @param  RTC_IT: specifies the RTC interrupt pending bit to clear.
+*         This parameter can be any combination of the @ref RTC_IT_TypeDef
+*         enumeration.
+* @retval None
+*/
+void RTC_ClearITPendingBit(RTC_IT_TypeDef RTC_IT)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_CLEAR_IT((uint16_t)RTC_IT));
+
+  /* Clear the interrupt pending bits in the RTC_ISR registers */
+  RTC->ISR2 = (uint8_t)~(uint8_t)((uint16_t)RTC_IT >> 4);
+}
+
+/**
+  * @}
+  */
+
+
+
+
+
+
+
+
+
+/**
+ * @addtogroup RTC_Private_Functions
+ * @{
+ */
+/**
+* @brief  Converts a 2 digit decimal to BCD format
+* @param  Value: Byte to be converted.
+* @retval Converted byte
+*/
+static uint8_t ByteToBcd2(uint8_t Value)
+{
+  uint8_t bcdhigh = 0;
+
+  while (Value >= 10)
+  {
+    bcdhigh++;
+    Value -= 10;
+  }
+
+  return  (uint8_t)((uint8_t)(bcdhigh << 4) | Value);
+}
+
+/**
+* @brief  Converts from 2 digit BCD to Binary format
+* @param  Value: BCD value to be converted.
+* @retval Converted word
+*/
+static uint8_t Bcd2ToByte(uint8_t Value)
+{
+  uint8_t tmp = 0;
+
+  tmp = (uint8_t)((uint8_t)((uint8_t)(Value & (uint8_t)0xF0) >> 4) * (uint8_t)10);
+
+  return (uint8_t)(tmp + (Value & (uint8_t)0x0F));
+}
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+  
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
\ No newline at end of file
diff --git a/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_spi.c b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_spi.c
new file mode 100755
index 0000000..2c0ec91
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_spi.c
@@ -0,0 +1,791 @@
+/**
+  ******************************************************************************
+  * @file    stm8l15x_spi.c
+  * @author  MCD Application Team
+  * @version V1.6.0
+  * @date    28-June-2013
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Serial peripheral interface (SPI):           
+  *           - Initialization and Configuration
+  *           - Data transfers functions
+  *           - Hardware CRC Calculation
+  *           - DMA transfers management
+  *           - Interrupts and flags management 
+  *           
+  *  @verbatim
+  *          
+  *          ===================================================================
+  *                                 How to use this driver
+  *          ===================================================================
+  *          1. Enable peripheral clock using CLK_PeripheralClockConfig(CLK_Peripheral_SPIx,
+  *             ENABLE) function (Refer to the product datasheet for the available SPI
+  *           	peripherals)
+  *
+  *          2.  Enable the external Pull-up on the used SPI Pins using the
+  *              GPIO_ExternalPullUpConfig() function or an eternal pull-up equivalent resistor
+	*              (RPU = 45 KOhm typical value). 
+  *
+  *        
+  *          3. Program the Polarity, Phase, First Data, Baud Rate Prescaler, Slave 
+  *             Management, Peripheral Mode and CRC Polynomial values using the SPI_Init()
+  *             function.
+  *
+  *          4. Enable the corresponding interrupt using the function SPI_ITConfig() if you
+  *           	need to use interrupt mode. 
+  *
+  *          5. When using the DMA mode 
+  *                   - Configure the DMA using DMA_Init() function
+  *                   - Active the needed channel Request using SPI_DMACmd() function
+  * 
+  *          6. Enable the SPI using the SPI_Cmd() function.
+  * 
+  *          7. Enable the DMA using the DMA_Cmd() function when using DMA mode. 
+  *
+  *          8. Optionally you can enable/configure the following parameters without
+  *             re-initialization (i.e there is no need to call again SPI_Init() function):
+  *              - When bidirectional mode (SPI_Direction_1Line_Rx or SPI_Direction_1Line_Tx)
+  *                is programmed as Data direction parameter using the SPI_Init() function
+  *                it can be possible to switch between SPI_Direction_Tx or SPI_Direction_Rx
+  *                using the SPI_BiDirectionalLineConfig() function.
+  *              - When SPI_NSS_Soft is selected as Slave Select Management parameter 
+  *                using the SPI_Init() function it can be possible to manage the 
+  *                NSS internal signal using the SPI_NSSInternalSoftwareConfig() function.
+  *          
+  *          9. To use the CRC Hardware calculation feature refer to the Peripheral 
+  *              CRC hardware Calculation subsection.
+  *
+  *  @endverbatim  
+  *                                  
+  ******************************************************************************
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ****************************************************************************** 
+  */ 
+	
+/* Includes ------------------------------------------------------------------*/
+#include "stm8l15x_spi.h"
+
+/** @addtogroup STM8L15x_StdPeriph_Driver
+  * @{
+  */
+	
+/** @defgroup SPI 
+  * @brief SPI driver modules
+  * @{
+  */ 
+	
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup SPI_Private_Functions
+  * @{
+  */
+
+/** @defgroup SPI_Group1 Initialization and Configuration functions
+ *  @brief   Initialization and Configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+                  Initialization and Configuration functions
+ ===============================================================================  
+
+  This section provides a set of functions allowing to initialize the SPI Direction,
+  SPI Mode, SPI Data Size, SPI Polarity, SPI Phase, SPI NSS Management, SPI Baud
+  Rate Prescaler, SPI First Bit and SPI CRC Polynomial.
+  
+  The SPI_Init() function follows the SPI configuration procedures for Master mode
+  and Slave mode (details for these procedures are available in reference manual
+  (RM0031)).
+  
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the SPI peripheral registers to their default reset values.
+  * @param  SPIx: where x can be 1 to select the specified SPI peripheral.
+  * @param  None
+  * @retval None
+  */
+void SPI_DeInit(SPI_TypeDef* SPIx)
+{
+  SPIx->CR1    = SPI_CR1_RESET_VALUE;
+  SPIx->CR2    = SPI_CR2_RESET_VALUE;
+  SPIx->CR3    = SPI_CR3_RESET_VALUE;
+  SPIx->SR     = SPI_SR_RESET_VALUE;
+  SPIx->CRCPR  = SPI_CRCPR_RESET_VALUE;
+}
+
+/**
+  * @brief  Initializes the SPI according to the specified parameters.
+  * @param  SPIx: where x can be 1 to select the specified SPI peripheral.
+  * @param  SPI_FirstBit: This parameter can be any of the
+  *          This parameter can be one of the following values:
+  *            @arg SPI_FirstBit_MSB: MSB bit will be transmitted first
+  *            @arg SPI_FirstBit_LSB: LSB bit will be transmitted first  
+  * @param  SPI_BaudRatePrescaler: This parameter can be any of the
+  *          This parameter can be one of the following values:
+  *            @arg SPI_BaudRatePrescaler_2: SPI frequency = frequency(CPU)/2
+  *            @arg SPI_BaudRatePrescaler_4: SPI frequency = frequency(CPU)/4
+  *            @arg SPI_BaudRatePrescaler_8: SPI frequency = frequency(CPU)/8
+  *            @arg SPI_BaudRatePrescaler_16: SPI frequency = frequency(CPU)/16
+  *            @arg SPI_BaudRatePrescaler_32: SPI frequency = frequency(CPU)/32
+  *            @arg SPI_BaudRatePrescaler_64: SPI frequency = frequency(CPU)/64
+  *            @arg SPI_BaudRatePrescaler_128: SPI frequency = frequency(CPU)/128
+  *            @arg SPI_BaudRatePrescaler_256: SPI frequency = frequency(CPU)/256            
+  * @param  SPI_Mode: Mode
+  *          This parameter can be one of the following values:
+  *            @arg SPI_Mode_Master: SPI Master configuration
+  *            @arg SPI_Mode_Slave: SPI Slave configuration
+  * @param  SPI_CPOL: Clock Polarity
+  *          This parameter can be one of the following values:
+  *            @arg SPI_CPOL_Low: Clock to 0 when idle
+  *            @arg SPI_CPOL_High: Clock to 1 when idle
+  * @param  SPI_CPHA: Clock Phase
+  *          This parameter can be one of the following values:
+  *            @arg SPI_CPHA_1Edge: The first clock transition is the first data capture edge
+  *            @arg SPI_CPHA_2Edge: The second clock transition is the first data capture edge
+  * @param  SPI_Data_Direction: Data direction
+  *          This parameter can be one of the following values:
+  *            @arg SPI_Direction_Rx: Select Rx receive direction in bi-directional mode
+  *            @arg SPI_Direction_Tx: Select Tx transmission direction in bi-directional mode
+  * @param  SPI_Slave_Management: Slave management
+  *          This parameter can be one of the following values:
+  *            @arg SPI_NSS_Soft: Software slave management disabled
+  *            @arg SPI_NSS_Hard: Software slave management enabled
+  * @param  CRCPolynomial: Configures the CRC polynomial.
+  * @retval None
+  */
+void SPI_Init(SPI_TypeDef* SPIx, SPI_FirstBit_TypeDef SPI_FirstBit,
+              SPI_BaudRatePrescaler_TypeDef SPI_BaudRatePrescaler,
+              SPI_Mode_TypeDef SPI_Mode, SPI_CPOL_TypeDef SPI_CPOL,
+              SPI_CPHA_TypeDef SPI_CPHA, SPI_DirectionMode_TypeDef SPI_Data_Direction,
+              SPI_NSS_TypeDef SPI_Slave_Management, uint8_t CRCPolynomial)
+{
+  /* Check structure elements */
+  assert_param(IS_SPI_FIRSTBIT(SPI_FirstBit));
+  assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_BaudRatePrescaler));
+  assert_param(IS_SPI_MODE(SPI_Mode));
+  assert_param(IS_SPI_POLARITY(SPI_CPOL));
+  assert_param(IS_SPI_PHASE(SPI_CPHA));
+  assert_param(IS_SPI_DATA_DIRECTION(SPI_Data_Direction));
+  assert_param(IS_SPI_SLAVEMANAGEMENT(SPI_Slave_Management));
+  assert_param(IS_SPI_CRC_POLYNOMIAL(CRCPolynomial));
+
+  /* Frame Format, BaudRate, Clock Polarity and Phase configuration */
+  SPIx->CR1 = (uint8_t)((uint8_t)((uint8_t)SPI_FirstBit |
+                                  (uint8_t)SPI_BaudRatePrescaler) |
+                        (uint8_t)((uint8_t)SPI_CPOL |
+                                  SPI_CPHA));
+
+  /* Data direction configuration: BDM, BDOE and RXONLY bits */
+  SPIx->CR2 = (uint8_t)((uint8_t)(SPI_Data_Direction) | (uint8_t)(SPI_Slave_Management));
+
+  if (SPI_Mode == SPI_Mode_Master)
+  {
+    SPIx->CR2 |= (uint8_t)SPI_CR2_SSI;
+  }
+  else
+  {
+    SPIx->CR2 &= (uint8_t)~(SPI_CR2_SSI);
+  }
+
+  /* Master/Slave mode configuration */
+  SPIx->CR1 |= (uint8_t)(SPI_Mode);
+
+  /* CRC configuration */
+  SPIx->CRCPR = (uint8_t)CRCPolynomial;
+}
+
+/**
+  * @brief  Enables or disables the SPI peripheral.
+  * @param  SPIx: where x can be 1 to select the specified SPI peripheral.
+  * @param  NewState New state of the SPI peripheral.
+  *         This parameter can be: ENABLE or DISABLE
+  * @retval None
+  */
+void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
+{
+  /* Check function parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    SPIx->CR1 |= SPI_CR1_SPE; /* Enable the SPI peripheral*/
+  }
+  else
+  {
+    SPIx->CR1 &= (uint8_t)(~SPI_CR1_SPE); /* Disable the SPI peripheral*/
+  }
+}
+
+/**
+  * @brief  Configures internally by software the NSS pin.
+  * @param  SPIx: where x can be 1 to select the specified SPI peripheral.
+  * @param  NewState Indicates the new state of the SPI Software slave management.
+    *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SPI_NSSInternalSoftwareCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
+{
+  /* Check function parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    SPIx->CR2 |= SPI_CR2_SSI; /* Set NSS pin internally by software*/
+  }
+  else
+  {
+    SPIx->CR2 &= (uint8_t)(~SPI_CR2_SSI); /* Reset NSS pin internally by software*/
+  }
+}
+
+/**
+  * @brief  Selects the data transfer direction in Bi-directional mode.
+  * @param  SPIx: where x can be 1 to select the specified SPI peripheral.
+  * @param  SPI_Direction Specifies the data transfer direction in Bi-directional mode.
+  *          This parameter can be one of the following values:
+  *            @arg SPI_Direction_Rx: Select Rx receive direction in bi-directional mode
+  *            @arg SPI_Direction_Tx: Select Tx transmission direction in bi-directional mode
+  * @retval None
+  */
+void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, SPI_Direction_TypeDef SPI_Direction)
+{
+  /* Check function parameters */
+  assert_param(IS_SPI_DIRECTION(SPI_Direction));
+
+  if (SPI_Direction != SPI_Direction_Rx)
+  {
+    SPIx->CR2 |= SPI_CR2_BDOE; /* Set the Tx only mode*/
+  }
+  else
+  {
+    SPIx->CR2 &= (uint8_t)(~SPI_CR2_BDOE); /* Set the Rx only mode*/
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Group2 Data transfers functions
+ *  @brief   Data transfers functions
+ *
+@verbatim   
+ ===============================================================================
+                         Data transfers functions
+ ===============================================================================  
+
+  This section provides a set of functions allowing to manage the SPI data transfers
+  
+  In reception, data are received and then stored into an internal Rx buffer while 
+  In transmission, data are first stored into an internal Tx buffer before being 
+  transmitted.
+
+  The read access of the SPI_DR register can be done using the SPI_ReceiveData()
+  function and returns the Rx buffered value. Whereas a write access to the SPI_DR 
+  can be done using SPI_SendData() function and stores the written data into 
+  Tx buffer.
+
+@endverbatim
+  * @{
+  */
+	
+/**
+  * @brief  Transmits a Data through the SPI peripheral.
+  * @param  SPIx: where x can be 1 to select the specified SPI peripheral.
+  * @param  Data: Byte to be transmitted.
+  * @retval None
+  */
+void SPI_SendData(SPI_TypeDef* SPIx, uint8_t Data)
+{
+  SPIx->DR = Data; /* Write in the DR register the data to be sent*/
+}
+
+/**
+  * @brief  Returns the most recent received data by the SPI peripheral.
+  * @param  SPIx: where x can be 1 to select the specified SPI peripheral.
+  * @retval The value of the received data.
+  */
+uint8_t SPI_ReceiveData(SPI_TypeDef* SPIx)
+{
+  return ((uint8_t)SPIx->DR); /* Return the data in the DR register*/
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Group3 Hardware CRC Calculation functions
+ *  @brief   Hardware CRC Calculation functions
+ *
+@verbatim   
+ ===============================================================================
+                         Hardware CRC Calculation functions
+ ===============================================================================  
+
+  This section provides a set of functions allowing to manage the SPI CRC hardware 
+  calculation
+
+  SPI communication using CRC is possible through the following procedure:
+     1. Program the Data direction, Polarity, Phase, First Data, Baud Rate Prescaler, 
+        Slave Management, Peripheral Mode and CRC Polynomial values using the SPI_Init()
+        function.
+     2. Enable the CRC calculation using the SPI_CalculateCRC() function.
+     3. Enable the SPI using the SPI_Cmd() function
+     4. Before writing the last data to the TX buffer, set the CRCNext bit using the 
+      SPI_TransmitCRC() function to indicate that after transmission of the last 
+      data, the CRC should be transmitted.
+     5. After transmitting the last data, the SPI transmits the CRC. The SPI_CR2_CRCNEXT
+        bit is reset. The CRC is also received and compared against the SPI_RXCRCR 
+        value. 
+        If the value does not match, the SPI_FLAG_CRCERR flag is set and an interrupt
+        can be generated when the SPI_IT_ERR interrupt is enabled.
+
+Note: 
+-----
+    - It is advised to don't read the calculate CRC values during the communication.
+
+    - When the SPI is in slave mode, be careful to enable CRC calculation only 
+      when the clock is stable, that is, when the clock is in the steady state. 
+      If not, a wrong CRC calculation may be done. In fact, the CRC is sensitive 
+      to the SCK slave input clock as soon as CRCEN is set, and this, whatever 
+      the value of the SPE bit.
+
+    - With high bitrate frequencies, be careful when transmitting the CRC.
+      As the number of used CPU cycles has to be as low as possible in the CRC 
+      transfer phase, it is forbidden to call software functions in the CRC 
+      transmission sequence to avoid errors in the last data and CRC reception. 
+      In fact, CRCNEXT bit has to be written before the end of the transmission/reception 
+      of the last data.
+
+    - For high bit rate frequencies, it is advised to use the DMA mode to avoid the
+      degradation of the SPI speed performance due to CPU accesses impacting the 
+      SPI bandwidth.
+
+    - When the STM8L15x are configured as slaves and the NSS hardware mode is 
+      used, the NSS pin needs to be kept low between the data phase and the CRC 
+      phase.
+
+    - When the SPI is configured in slave mode with the CRC feature enabled, CRC
+      calculation takes place even if a high level is applied on the NSS pin. 
+      This may happen for example in case of a multislave environment where the 
+      communication master addresses slaves alternately.
+
+    - Between a slave de-selection (high level on NSS) and a new slave selection 
+      (low level on NSS), the CRC value should be cleared on both master and slave
+      sides in order to resynchronize the master and slave for their respective 
+      CRC calculation.
+
+    To clear the CRC, follow the procedure below:
+      1. Disable SPI using the SPI_Cmd() function
+      2. Disable the CRC calculation using the SPI_CalculateCRC() function.
+      3. Enable the CRC calculation using the SPI_CalculateCRC() function.
+      4. Enable SPI using the SPI_Cmd() function.
+
+@endverbatim
+  * @{
+  */
+	
+/**
+  * @brief  Enables the transmit of the CRC value.
+  * @param  SPIx: where x can be 1 to select the specified SPI peripheral.
+  * @retval None
+  */
+void SPI_TransmitCRC(SPI_TypeDef* SPIx)
+{
+  SPIx->CR2 |= SPI_CR2_CRCNEXT; /* Enable the CRC transmission*/
+}
+
+/**
+  * @brief  Enables or disables the CRC value calculation of the transferred bytes.
+  * @param  SPIx: where x can be 1 to select the specified SPI peripheral.
+  * @param  NewState Indicates the new state of the SPI CRC value calculation.
+    *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SPI_CalculateCRCCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
+{
+  /* Check function parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* SPI must be disable for correct operation od Hardware CRC calculation */
+  SPI_Cmd(SPI1, DISABLE);
+
+  if (NewState != DISABLE)
+  {
+    SPIx->CR2 |= SPI_CR2_CRCEN; /* Enable the CRC calculation*/
+  }
+  else
+  {
+    SPIx->CR2 &= (uint8_t)(~SPI_CR2_CRCEN); /* Disable the CRC calculation*/
+  }
+}
+
+/**
+  * @brief  Returns the transmit or the receive CRC register value.
+  * @param  SPIx: where x can be 1 to select the specified SPI peripheral.
+  * @param  SPI_CRC: Specifies the CRC register to be read.
+  *          This parameter can be one of the following values:
+  *            @arg SPI_CRC_RX: Select Tx CRC register
+  *            @arg SPI_CRC_TX: Select Rx CRC register
+  * @retval The selected CRC register value.
+  */
+uint8_t SPI_GetCRC(SPI_TypeDef* SPIx, SPI_CRC_TypeDef SPI_CRC)
+{
+  uint8_t crcreg = 0;
+
+  /* Check function parameters */
+  assert_param(IS_SPI_CRC(SPI_CRC));
+
+  if (SPI_CRC != SPI_CRC_RX)
+  {
+    crcreg = SPIx->TXCRCR;  /* Get the Tx CRC register*/
+  }
+  else
+  {
+    crcreg = SPIx->RXCRCR; /* Get the Rx CRC register*/
+  }
+
+  /* Return the selected CRC register status*/
+  return crcreg;
+}
+
+/**
+  * @brief  Reset the Rx CRCR and Tx CRCR registers.
+  * @param  SPIx: where x can be 1 to select the specified SPI peripheral.
+  * @retval None
+  */
+void SPI_ResetCRC(SPI_TypeDef* SPIx)
+{
+  /* Rx CRCR & Tx CRCR registers are reset when CRCEN (hardware calculation)
+     bit in SPI_CR2 is written to 1 (enable) */
+  SPI_CalculateCRCCmd(SPIx, ENABLE);
+
+  /* Previous function disable the SPI */
+  SPI_Cmd(SPIx, ENABLE);
+}
+
+/**
+  * @brief  Returns the CRC Polynomial register value.
+  * @param  SPIx: where x can be 1 to select the specified SPI peripheral.
+  * @retval uint8_t The CRC Polynomial register value.
+  */
+uint8_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx)
+{
+  return SPIx->CRCPR; /* Return the CRC polynomial register */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Group4 DMA transfers management functions
+ *  @brief   DMA transfers management functions
+  *
+@verbatim   
+ ===============================================================================
+                         DMA transfers management functions
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+	
+/**
+  * @brief  Enables or disables the SPI DMA interface.
+  * @param  SPIx: where x can be 1 to select the specified SPI peripheral.
+  * @param  SPI_DMAReq Specifies the SPI DMA transfer request to be enabled or disabled.
+  *          This parameter can be one of the following values:
+  *            @arg SPI_DMAReq_RX: SPI DMA Rx transfer requests
+  *            @arg SPI_DMAReq_TX: SPI DMA Tx transfer requests
+  * @param  NewState Indicates the new state of the SPI DMA request.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SPI_DMACmd(SPI_TypeDef* SPIx, SPI_DMAReq_TypeDef SPI_DMAReq, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  assert_param(IS_SPI_DMAREQ(SPI_DMAReq));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected SPI DMA requests */
+    SPIx->CR3 |= (uint8_t) SPI_DMAReq;
+  }
+  else
+  {
+    /* Disable the selected SPI DMA requests */
+    SPIx->CR3 &= (uint8_t)~SPI_DMAReq;
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Group5 Interrupts and flags management functions
+ *  @brief   Interrupts and flags management functions
+  *
+@verbatim   
+ ===============================================================================
+                         Interrupts and flags management functions
+ ===============================================================================  
+
+  This section provides a set of functions allowing to configure the SPI Interrupts 
+  sources and check or clear the flags or pending bits status.
+  The user should identify which mode will be used in his application to manage 
+  the communication: Polling mode, Interrupt mode or DMA mode. 
+    
+  Polling Mode
+  =============
+  In Polling Mode, the SPI communication can be managed by 6 flags:
+     1. SPI_FLAG_TXE: to indicate the status of the transmit buffer register
+     2. SPI_FLAG_RXNE: to indicate the status of the receive buffer register
+     3. SPI_FLAG_WKUP: to indicate the state of the Wakeup event.
+     4. SPI_FLAG_CRCERR: to indicate if a CRC Calculation error occurs              
+     5. SPI_FLAG_MODF: to indicate if a Mode Fault error occurs
+     6. SPI_FLAG_OVR: to indicate if an Overrun error occurs
+
+  In this Mode it is advised to use the following functions:
+     - FlagStatus SPI_GetFlagStatus(SPI_TypeDef* SPIx, SPI_FLAG_TypeDef SPI_FLAG);
+     - void SPI_ClearFlag(SPI_TypeDef* SPIx, SPI_FLAG_TypeDef SPI_FLAG);
+
+  Interrupt Mode
+  ===============
+  In Interrupt Mode, the SPI communication can be managed by 4 interrupt sources
+  and 6 pending bits: 
+  Pending Bits:
+  ------------- 
+     1. SPI_IT_TXE: to indicate the status of the transmit buffer register
+     2. SPI_IT_RXNE: to indicate the status of the receive buffer register
+     3. SPI_IT_CRCERR: to indicate if a CRC Calculation error occurs              
+     4. SPI_IT_MODF: to indicate if a Mode Fault error occurs
+     5. SPI_IT_OVR: to indicate if an Overrun error occurs
+     6. SPI_IT_WKUP: to indicate if an Wake_up event occurs
+  Interrupt Source:
+  -----------------
+     1. SPI_IT_TXE: specifies the interrupt source for the Tx buffer empty 
+                        interrupt.  
+     2. SPI_IT_RXNE: specifies the interrupt source for the Rx buffer not 
+                          empty interrupt.
+     3. SPI_IT_ERR: specifies the interrupt source for the errors interrupt.
+		 4. SPI_IT_WKUP: specifies the interrupt source for the Wake-up interrupt.
+
+  In this Mode it is advised to use the following functions:
+     - void SPI_ITConfig(SPI_TypeDef* SPIx, SPI_IT_TypeDef SPI_IT, FunctionalState NewState);
+     - ITStatus SPI_GetITStatus(SPI_TypeDef* SPIx, SPI_IT_TypeDef SPI_IT);
+     - void SPI_ClearITPendingBit(SPI_TypeDef* SPIx, SPI_IT_TypeDef SPI_IT);
+
+  DMA Mode
+  ========
+  In DMA Mode, the SPI communication can be managed by 2 DMA Channel requests:
+     1. SPI_DMAReq_Tx: specifies the Tx buffer DMA transfer request
+     2. SPI_DMAReq_Rx: specifies the Rx buffer DMA transfer request
+
+  In this Mode it is advised to use the following function:
+    - void SPI_DMACmd(SPI_TypeDef* SPIx, SPI_DMAReq_TypeDef SPI_DMAReq, FunctionalState NewState);
+
+@endverbatim
+  * @{
+  */
+	
+/**
+  * @brief  Enables or disables the specified interrupts.
+  * @param  SPIx: where x can be 1 to select the specified SPI peripheral.
+  * @param  SPI_IT Specifies the SPI interrupts sources to be enabled or disabled.
+  *          This parameter can be one of the following values:
+  *            @arg SPI_IT_TXE: Transmit buffer empty
+  *            @arg SPI_IT_RXNE: Receive buffer not empty
+  *            @arg SPI_IT_ERR: Error
+  *            @arg SPI_IT_WKUP: Wake-up
+  * @param  NewState: The new state of the specified SPI interrupts.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SPI_ITConfig(SPI_TypeDef* SPIx, SPI_IT_TypeDef SPI_IT, FunctionalState NewState)
+{
+  uint8_t itpos = 0;
+  /* Check function parameters */
+  assert_param(IS_SPI_CONFIG_IT(SPI_IT));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Get the SPI IT index */
+  itpos = (uint8_t)((uint8_t)1 << (uint8_t)((uint8_t)SPI_IT & (uint8_t)0x0F));
+
+  if (NewState != DISABLE)
+  {
+    SPIx->CR3 |= itpos; /* Enable interrupt*/
+  }
+  else
+  {
+    SPIx->CR3 &= (uint8_t)(~itpos); /* Disable interrupt*/
+  }
+}
+
+/**
+  * @brief  Checks whether the specified SPI flag is set or not.
+  * @param  SPIx: where x can be 1 to select the specified SPI peripheral.
+  * @param  SPI_FLAG: Specifies the flag to check.
+  *          This parameter can be one of the following values:
+  *            @arg SPI_FLAG_BSY: Busy
+  *            @arg SPI_FLAG_OVR: Overrun
+  *            @arg SPI_FLAG_MODF: Mode fault
+  *            @arg SPI_FLAG_CRCERR: CRC error
+  *            @arg SPI_FLAG_WKUP: Wake-up 
+  *            @arg SPI_FLAG_TXE: Transmit buffer empty
+  *            @arg SPI_FLAG_RXNE: Receive buffer empty
+  * @retval Indicates the state of SPI_FLAG.
+  *         This parameter can be SET or RESET.
+  */
+FlagStatus SPI_GetFlagStatus(SPI_TypeDef* SPIx, SPI_FLAG_TypeDef SPI_FLAG)
+{
+  FlagStatus status = RESET;
+  /* Check parameters */
+  assert_param(IS_SPI_FLAG(SPI_FLAG));
+
+  /* Check the status of the specified SPI flag */
+  if ((SPIx->SR & (uint8_t)SPI_FLAG) != (uint8_t)RESET)
+  {
+    status = SET; /* SPI_FLAG is set */
+  }
+  else
+  {
+    status = RESET; /* SPI_FLAG is reset*/
+  }
+
+  /* Return the SPI_FLAG status */
+  return status;
+}
+
+/**
+  * @brief  Clears the SPI flags.
+  * @param  SPIx: where x can be 1 to select the specified SPI peripheral.
+  * @param  SPI_FLAG: Specifies the flag to clear.
+  *         This parameter can be one of the following values:
+  *            @arg SPI_FLAG_CRCERR
+  *            @arg SPI_FLAG_WKUP
+  * @note   OVR (OverRun Error) interrupt pending bit is cleared by software
+  *         sequence: a read operation to SPI_DR register (SPI_ReceiveData()) followed by
+  *         a read operation to SPI_SR register (SPI_GetFlagStatus()).
+  * @note   MODF (Mode Fault) interrupt pending bit is cleared by software sequence:
+  *         a read/write operation to SPI_SR register (SPI_GetFlagStatus()) followed by
+  *         a write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).
+  * @retval None
+  */
+void SPI_ClearFlag(SPI_TypeDef* SPIx, SPI_FLAG_TypeDef SPI_FLAG)
+{
+  assert_param(IS_SPI_CLEAR_FLAG(SPI_FLAG));
+  /* Clear the flag bit */
+  SPIx->SR = (uint8_t)(~SPI_FLAG);
+}
+
+/**
+  * @brief  Checks whether the specified interrupt has occurred or not.
+  * @param  SPIx: where x can be 1 to select the specified SPI peripheral.
+  * @param  SPI_IT: Specifies the SPI interrupt pending bit to check.
+  *         This parameter can be one of the following values:
+  *            @arg SPI_IT_CRCERR
+  *            @arg SPI_IT_WKUP
+  *            @arg SPI_IT_OVR
+  *            @arg SPI_IT_MODF
+  *            @arg SPI_IT_RXNE
+  *            @arg SPI_IT_TXE
+  * @retval Indicates the state of the SPI_IT.
+
+  */
+ITStatus SPI_GetITStatus(SPI_TypeDef* SPIx, SPI_IT_TypeDef SPI_IT)
+{
+  ITStatus pendingbitstatus = RESET;
+  uint8_t itpos = 0;
+  uint8_t itmask1 = 0;
+  uint8_t itmask2 = 0;
+  __IO uint8_t enablestatus = 0;
+  assert_param(IS_SPI_GET_IT(SPI_IT));
+  /* Get the SPI IT index */
+  itpos = (uint8_t)((uint8_t)1 << ((uint8_t)SPI_IT & (uint8_t)0x0F));
+
+  /* Get the SPI IT mask */
+  itmask1 = (uint8_t)((uint8_t)SPI_IT >> (uint8_t)4);
+  /* Set the IT mask */
+  itmask2 = (uint8_t)((uint8_t)1 << itmask1);
+  /* Get the SPI_IT enable bit status */
+  enablestatus = (uint8_t)((uint8_t)SPIx->SR & itmask2);
+  /* Check the status of the specified SPI interrupt */
+  if (((SPIx->CR3 & itpos) != RESET) && enablestatus)
+  {
+    /* SPI_IT is set */
+    pendingbitstatus = SET;
+  }
+  else
+  {
+    /* SPI_IT is reset */
+    pendingbitstatus = RESET;
+  }
+  /* Return the SPI_IT status */
+  return  pendingbitstatus;
+}
+
+/**
+  * @brief  Clears the interrupt pending bits.
+  * @param  SPIx: where x can be 1 to select the specified SPI peripheral.
+  * @param  SPI_IT: Specifies the interrupt pending bit to clear.
+  *         This parameter can be one of the following values:
+  *            @arg SPI_IT_CRCERR
+  *            @arg SPI_IT_WKUP
+  * @note   OVR (OverRun Error) interrupt pending bit is cleared by software sequence:
+  *         a read operation to SPI_DR register (SPI_ReceiveData()) followed by
+  *         a read operation to SPI_SR register (SPI_GetITStatus()).
+  * @note   MODF (Mode Fault) interrupt pending bit is cleared by software sequence:
+  *         a read/write operation to SPI_SR register (SPI_GetITStatus()) followed by
+  *         a write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).
+  * @retval None
+  */
+void SPI_ClearITPendingBit(SPI_TypeDef* SPIx, SPI_IT_TypeDef SPI_IT)
+{
+  uint8_t itpos = 0;
+  assert_param(IS_SPI_CLEAR_IT(SPI_IT));
+
+  /* Clear  SPI_IT_CRCERR or SPI_IT_WKUP interrupt pending bits */
+
+  /* Get the SPI pending bit index */
+  itpos = (uint8_t)((uint8_t)1 << (uint8_t)((uint8_t)(SPI_IT & (uint8_t)0xF0) >> 4));
+  /* Clear the pending bit */
+  SPIx->SR = (uint8_t)(~itpos);
+
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_syscfg.c b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_syscfg.c
new file mode 100755
index 0000000..a298b64
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_syscfg.c
@@ -0,0 +1,504 @@
+/**
+  ******************************************************************************
+  * @file    stm8l15x_syscfg.c
+  * @author  MCD Application Team
+  * @version V1.6.0
+  * @date    28-June-2013
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the RI and SYSCFG:
+  *            - RI configuration
+  *            - SYSCFG configuration
+  *
+  *  @verbatim
+  *  
+  *          ===================================================================
+  *                                 How to use this driver
+  *          ===================================================================
+  *          This driver provides functions to configure the RI and SYSCFG
+  *          These functions are split in 2 groups: 
+  *   
+  *          1. RI configuration: this group includes all needed functions 
+  *             to configure the RI:
+  *                   - Routing the TIM1 Input capture channels
+  *                   - Close and Open the I/O switches
+  *                   - Close and Open the analog switches
+  *                   - Configure the internal Pull-up and Pull-down resistors
+  *           
+  *          2. SYSCFG configuration: this group includes all needed functions 
+  *             to configure the SYSCFG:
+  *                   - Configure the alternate function remapping of some peripherals
+  *                     such as: USART, SPI, TIMs...
+  *                     Remapping possibilities depends on the device (low-density,
+  *                     medium-density or high density) so it is recommended to   
+  *                     refer to the product reference manual.
+  *                   - Configure the DMA channels remapping of ADC1 and TIM4
+  *
+  *  @endverbatim            
+  *    
+  ******************************************************************************
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm8l15x_syscfg.h"
+
+/** @addtogroup STM8L15x_StdPeriph_Driver
+  * @{
+  */
+  
+/** @defgroup SYSCFG
+  * @brief SYSCFG driver modules
+  * @{
+  */
+  
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup SYSCFG_Private_Functions
+  * @{
+  */
+
+/** @defgroup SYSCFG_Group1 RI configuration
+ *  @brief   RI configuration
+ *
+@verbatim   
+ ===============================================================================
+                           RI configuration functions
+ ===============================================================================  
+  
+       ===================================================================      
+                        SYSCFG Driver: how to configure RI
+       =================================================================== 
+       
+         1. By default, TIM1 Input Capture channels 2 and 3 are connected to the
+            I/O port assigned in the datasheet pinout (default routing).
+            TIM1 Input Capture channels 2 and 3 can be routed by calling 
+            SYSCFG_RITIMInputCaptureConfig()
+            Refer to the device reference manual for more details about 
+            TIM1 input capture routing
+          
+         2. For more details about using SYSCFG_RIIOSwitchConfig()
+            and SYSCFG_RIAnalogSwitchConfig() with COMP1 and COMP2, refer to
+            comparators driver
+            
+         3. To output the Internal reference voltage VREFINT, configure corresponding
+            GPIO pin in input mode using GPIO_Init() then use SYSCFG_RIIOSwitchConfig()
+       
+         4. To use the internal Pull-up and Pull-down resistors call
+            SYSCFG_RIResistorConfig()
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the RI registers to their default reset values.
+  * @param  None
+  * @retval None
+  */
+void SYSCFG_RIDeInit(void)
+{
+  RI->ICR1   = RI_ICR1_RESET_VALUE;     /*!< Set RI->ICR1 to reset value */
+  RI->ICR2   = RI_ICR2_RESET_VALUE;     /*!< Set RI->ICR2 to reset value */
+  RI->IOSR1  = RI_IOSR1_RESET_VALUE;    /*!< Set RI->IOSR1 to reset value */
+  RI->IOSR2  = RI_IOSR2_RESET_VALUE;    /*!< Set RI->IOSR2 to reset value */
+  RI->IOSR3  = RI_IOSR3_RESET_VALUE;    /*!< Set RI->IOSR3 to reset value */
+  RI->IOSR4  = RI_IOSR4_RESET_VALUE;    /*!< Set RI->IOSR3 to reset value */
+  RI->ASCR1  = RI_ASCR1_RESET_VALUE;    /*!< Set RI->ASCR1 to reset value */
+  RI->ASCR2  = RI_ASCR2_RESET_VALUE;    /*!< Set RI->ASCR2 to reset value */
+  RI->RCR    = RI_RCR_RESET_VALUE;      /*!< Set RI->RCR to reset value */
+}
+
+/**
+  * @brief  Configures the routing interface to select which Input Output pin
+  *         to be routed to TIM1 Input Capture.
+  * @param  RI_InputCapture: selects the TIM1 input capture2 RI_InputCapture_IC2
+  *         or the TIM1 input capture3 RI_InputCapture_IC3
+  * @param  RI_InputCaptureRouting: selects the value to set in TIM1 Input Capture
+  *         routing register ICRx and can be from RI_InputCaptureRouting_0 to
+  *         RI_InputCaptureRouting_22.
+  * @retval None.
+  */
+void SYSCFG_RITIMInputCaptureConfig(RI_InputCapture_TypeDef RI_InputCapture,
+                                    RI_InputCaptureRouting_TypeDef RI_InputCaptureRouting)
+{
+  /* Check the parameters */
+  assert_param(IS_RI_INPUTCAPTURE(RI_InputCapture));
+  assert_param(IS_RI_INPUTCAPTUREROUTING(RI_InputCaptureRouting));
+
+  /* Check whether Input Capture 2 is selected */
+  if (RI_InputCapture == RI_InputCapture_IC2)
+  {
+    /* Set the value in ICR1 register to route TIM input Capture 2 */
+    RI->ICR1 = (uint8_t) RI_InputCaptureRouting;
+  }
+
+  else /* The Input Capture 3 is selected */
+  {
+    /* Set the value in ICR2 register to route TIM input capture 3 */
+    RI->ICR2 = (uint8_t) RI_InputCaptureRouting;
+  }
+}
+
+/**
+  * @brief  Enables or disables the Routing Interface Analog switch.
+  * @param  RI_AnalogSwitch: Analog Switch
+  *          This parameter can be one of the following values:
+  *            @arg RI_AnalogSwitch_0: Analog switch 0
+  *            @arg RI_AnalogSwitch_1: Analog switch 1
+  *            @arg RI_AnalogSwitch_2: Analog switch 2
+  *            @arg RI_AnalogSwitch_3: Analog switch 3
+  *            @arg RI_AnalogSwitch_4: Analog switch 4
+  *            @arg RI_AnalogSwitch_5: Analog switch 5
+  *            @arg RI_AnalogSwitch_6: Analog switch 6
+  *            @arg RI_AnalogSwitch_7: Analog switch 7
+  *            @arg RI_AnalogSwitch_8: Analog switch 8
+  *            @arg RI_AnalogSwitch_9: Analog switch 9
+  *            @arg RI_AnalogSwitch_10: Analog switch 10
+  *            @arg RI_AnalogSwitch_11: Analog switch 11
+  *            @arg RI_AnalogSwitch_12: Analog switch 14                          
+  * @param  NewState: new state of the analog switch.
+  *         This parameter can be ENABLE or DISABLE.
+  * @retval None
+  */
+void SYSCFG_RIAnalogSwitchConfig(RI_AnalogSwitch_TypeDef RI_AnalogSwitch,
+                                 FunctionalState NewState)
+{
+  uint8_t AnalogSwitchRegister, AnalogSwitchIndex = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RI_ANALOGSWITCH(RI_AnalogSwitch));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Get the analog switch register ASCR1 or ASCR2 */
+  AnalogSwitchRegister = (uint8_t) (RI_AnalogSwitch & (uint8_t) 0xF0);
+
+  /* Get the analog switch bit index in ASCRx register */
+  AnalogSwitchIndex = (uint8_t) (RI_AnalogSwitch & (uint8_t) 0x0F);
+
+  if (NewState != DISABLE)
+  {
+    if (AnalogSwitchRegister == (uint8_t) 0x10)
+    {
+      /* Enable the analog switch */
+      RI->ASCR1 |= (uint8_t) ((uint8_t)1 << (uint8_t) AnalogSwitchIndex);
+    }
+    else
+    {
+      /* Enable the analog switch */
+      RI->ASCR2 |= (uint8_t) ((uint8_t)1 << (uint8_t) AnalogSwitchIndex);
+    }
+  }
+  else
+  {
+    if (AnalogSwitchRegister == (uint8_t) 0x10)
+    {
+      /* Disable the analog switch */
+      RI->ASCR1 &= (uint8_t) (~(uint8_t)((uint8_t)1 <<  AnalogSwitchIndex));
+    }
+    else
+    {
+      /* Disable the analog switch */
+      RI->ASCR2 &= (uint8_t) (~ (uint8_t)((uint8_t)1 << AnalogSwitchIndex));
+    }
+  }
+}
+
+/**
+  * @brief  Closes or Opens the routing interface Input Output switches.
+  * @param  RI_IOSwitch: can be one of RI_IOSwitch_1..RI_IOSwitch_24
+  * @param  NewState: new state of the Input Output Switch.
+  *         This parameter can be ENABLE or DISABLE.
+  * @retval None.
+  */
+void SYSCFG_RIIOSwitchConfig(RI_IOSwitch_TypeDef RI_IOSwitch,
+                             FunctionalState NewState)
+{
+  uint8_t IOSwitchRegsiter, IOSwitchIndex = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RI_IOSWITCH(RI_IOSwitch));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Get the Input Output switch bit index in IOSRx register */
+  IOSwitchIndex = (uint8_t) (RI_IOSwitch & (uint8_t) 0x0F);
+
+  /* Get the Input Output switch register IOSR1, IOSR2 or IOSR3 */
+  IOSwitchRegsiter = (uint8_t) (RI_IOSwitch & (uint8_t) 0xF0);
+
+  /* Check whether the Input Output switch control bit is in the IOSR1 register */
+  if (IOSwitchRegsiter == (uint8_t) 0x10)
+  {
+    if (NewState != DISABLE)
+    {
+      /* Close the Input Output switch */
+      RI->IOSR1 |= (uint8_t) ((uint8_t)1 << IOSwitchIndex);
+    }
+    else
+    {
+      /* Open the Input Output switch */
+      RI->IOSR1 &= (uint8_t) (~ (uint8_t)((uint8_t)1 << IOSwitchIndex));
+    }
+  }
+
+  /* Check whether the Input Output switch control bit is in the IOSR2 register */
+  else if (IOSwitchRegsiter == (uint8_t) 0x20)
+  {
+    if (NewState != DISABLE)
+    {
+      /* Close the Input Output switch */
+      RI->IOSR2 |= (uint8_t) ((uint8_t)1 << IOSwitchIndex);
+    }
+    else
+    {
+      /* Open the Input Output switch */
+      RI->IOSR2 &= (uint8_t) (~(uint8_t)((uint8_t)1 <<  IOSwitchIndex));
+    }
+  }
+
+  /* The Input Output switch control bit is in the IOSR3 register */
+  else if (IOSwitchRegsiter == (uint8_t) 0x30)
+  {
+    if (NewState != DISABLE)
+    {
+      /* Close the Input Output switch */
+      RI->IOSR3 |= (uint8_t) ((uint8_t)1 << IOSwitchIndex);
+    }
+    else
+    {
+      /* Open the Input Output switch */
+      RI->IOSR3 &= (uint8_t) (~ (uint8_t) ((uint8_t) 1 << IOSwitchIndex));
+    }
+  }
+
+  /* The Input Output switch control bit is in the IOSR4 register */
+  else
+  {
+    if (NewState != DISABLE)
+    {
+      /* Close the Input Output switch */
+      RI->IOSR4 |= (uint8_t) ((uint8_t)1 << IOSwitchIndex);
+    }
+    else
+    {
+      /* Open the Input Output switch */
+      RI->IOSR4 &= (uint8_t) (~ (uint8_t) ((uint8_t) 1 << IOSwitchIndex));
+    }
+  }
+}
+
+/**
+  * @brief  Configures the Pull-up and Pull-down Resistors
+  * @param  RI_Resistor: selects the resistor to connect,
+  *          This parameter can be one of the following values:
+  *            @arg RI_Resistor_10KPU: 10K pull up
+  *            @arg RI_Resistor_400KPU: 400K pull up
+  *            @arg RI_Resistor_10KPD: 10K pull down
+  *            @arg RI_Resistor_400KPD: 400K pull down      
+  * @retval None
+  */
+void SYSCFG_RIResistorConfig(RI_Resistor_TypeDef RI_Resistor, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_RI_RESISTOR(RI_Resistor));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the resistor */
+    RI->RCR |= (uint8_t) RI_Resistor;
+  }
+  else
+  {
+    /* Disable the Resistor */
+    RI->RCR &= (uint8_t) (~RI_Resistor);
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_Group2 SYSCFG configuration
+ *  @brief   SYSCFG configuration
+ *
+@verbatim   
+ ===============================================================================
+                           SYSCFG configuration functions
+ ===============================================================================  
+  
+       ===================================================================      
+                        SYSCFG Driver: how to use it for remapping
+       =================================================================== 
+       
+         1. To remap the alternate function of some peripherals (such as: USART,
+            SPI, TIMs...), use SYSCFG_REMAPPinConfig()
+          
+         2. To remap the DMA channels of ADC1 and TIM4, use SYSCFG_REMAPDMAChannelConfig()
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the Remapping registers to their default reset values.
+  * @param  None
+  * @retval None
+  */
+void SYSCFG_REMAPDeInit(void)
+{
+  /*!< Set RMPCR1 to reset value */
+  SYSCFG->RMPCR1 = SYSCFG_RMPCR1_RESET_VALUE;
+
+  /*!< Set RMPCR2 to reset value */
+  SYSCFG->RMPCR2 = SYSCFG_RMPCR2_RESET_VALUE;
+
+  /*!< Set RMPCR3 to reset value */
+  SYSCFG->RMPCR3 = SYSCFG_RMPCR3_RESET_VALUE;
+}
+
+/**
+  * @brief  Changes the mapping of the specified pins.
+  * @param  REMAP_Pin: selects the pin to remap.
+  *          This parameter can be one of the following values:
+  *            @arg REMAP_Pin_USART1TxRxPortA: USART1 Tx- Rx (PC3- PC2) remapping to PA2- PA3
+  *            @arg REMAP_Pin_USART1TxRxPortC: USART1 Tx- Rx (PC3- PC2) remapping to PC5- PC6 
+  *            @arg REMAP_Pin_USART1Clk: USART1 CK (PC4) remapping to PA0
+  *            @arg REMAP_Pin_SPI1Full: SPI1 MISO- MOSI- SCK- NSS(PB7- PB6- PB5- PB4)
+  *                                     remapping to PA2- PA3- PC6- PC5
+  *            @arg REMAP_Pin_ADC1ExtTRIG1: ADC1 External Trigger 1 (PA6) remapping to PD0
+  *            @arg REMAP_Pin_TIM2TRIGPortA: TIM2 Trigger (PB3) remapping to PA4
+  *            @arg REMAP_Pin_TIM3TRIGPortA: TIM3 Trigger (PD1) remapping to PA5
+  *            @arg REMAP_Pin_TIM2TRIGLSE: TIM2 Trigger remapping to LSE
+  *            @arg REMAP_Pin_TIM3TRIGLSE: TIM3 Trigger remapping to LSE
+  *            @arg REMAP_Pin_SPI2Full: SPI2 MISO- MOSI- SCK- NSS(PG7- PG6- PG5- PG4)
+  *                                     remapping to PI3- PI2- PI1- PI0
+  *            @arg REMAP_Pin_TIM3TRIGPortG: TIM3 Trigger (PD1) remapping to PG3
+  *            @arg REMAP_Pin_TIM23BKIN: TIM2 Break Input (PA4) remapping to PG0
+  *                                      and TIM3 Break Input (PA5) remapping to PG1
+  *            @arg REMAP_Pin_SPI1PortF: SPI1 MISO- MOSI- SCK- NSS(PB7- PB6- PB5- PB4)
+  *                                      remapping to PF0- PF1- PF2- PF3
+  *            @arg REMAP_Pin_USART3TxRxPortF: USART3 Tx- Rx (PG1- PG0) remapping to PF0- PF1
+  *            @arg REMAP_Pin_USART3Clk: USART3 CK (PG2) remapping to PF2
+  *            @arg REMAP_Pin_TIM3Channel1: TIM3 Channel 1 (PB1) remapping to PI0 
+  *            @arg REMAP_Pin_TIM3Channel2: TIM3 Channel 2 (PD0) remapping to PI3
+  *            @arg REMAP_Pin_CCO: CCO (PC4) remapping to PE2
+  *            @arg REMAP_Pin_TIM2Channel1: TIM2 Channel 1 (PB0) remapping to PC5
+  *            @arg REMAP_Pin_TIM2Channel2: TIM2 Channel 2 (PB2) remapping to PC6                                       
+  * @param  NewState: This parameter can be ENABLE or DISABLE.
+  * @retval None
+  */
+void SYSCFG_REMAPPinConfig(REMAP_Pin_TypeDef REMAP_Pin, FunctionalState NewState)
+{
+  uint8_t regindex = 0;
+  /* Check the parameters */
+  assert_param(IS_REMAP_PIN(REMAP_Pin));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Read register index */
+  regindex = (uint8_t) ((uint16_t) REMAP_Pin >> 8);
+
+  /* Check if REMAP_Pin is in RMPCR1 register */
+  if (regindex == 0x01)
+  {
+    SYSCFG->RMPCR1 &= (uint8_t)((uint8_t)((uint8_t)REMAP_Pin << 4) | (uint8_t)0x0F);
+    if (NewState != DISABLE)
+    {
+      SYSCFG->RMPCR1 |= (uint8_t)((uint16_t)REMAP_Pin & (uint16_t)0x00F0);
+    }
+  }
+  /* Check if REMAP_Pin is in RMPCR2 register */
+  else if (regindex == 0x02)
+  {
+    if (NewState != DISABLE)
+    {
+      SYSCFG->RMPCR2 |= (uint8_t) REMAP_Pin;
+    }
+    else
+    {
+      SYSCFG->RMPCR2 &= (uint8_t)((uint16_t)(~(uint16_t)REMAP_Pin));
+    }
+  }
+  /* REMAP_Pin is in RMPCR3 register */
+  else
+  {
+    if (NewState != DISABLE)
+    {
+      SYSCFG->RMPCR3 |= (uint8_t) REMAP_Pin;
+    }
+    else
+    {
+      SYSCFG->RMPCR3 &= (uint8_t)((uint16_t)(~(uint16_t)REMAP_Pin));
+    }
+  }
+}
+
+/**
+  * @brief  Remaps the DMA Channel to the specific peripheral (ADC or TIM4)
+  * @param  REMAP_DMAChannel: specifies the DMA Channel to remap.
+  *          This parameter can be one of the following values:
+  *            @arg REMAP_DMA1Channel_ADC1ToChannel0: ADC1 DMA1 req/ack mapped on DMA1 channel 0
+  *            @arg REMAP_DMA1Channel_ADC1ToChannel1: ADC1 DMA1 req/ack mapped on DMA1 channel 1
+  *            @arg REMAP_DMA1Channel_ADC1ToChannel2: ADC1 DMA1 req/ack mapped on DMA1 channel 2
+  *            @arg REMAP_DMA1Channel_ADC1ToChannel3: ADC1 DMA1 req/ack mapped on DMA1 channel 3
+  *            @arg REMAP_DMA1Channel_TIM4ToChannel0: TIM4 DMA1 req/ack mapped on DMA1 channel 0
+  *            @arg REMAP_DMA1Channel_TIM4ToChannel1: TIM4 DMA1 req/ack mapped on DMA1 channel 1
+  *            @arg REMAP_DMA1Channel_TIM4ToChannel2: TIM4 DMA1 req/ack mapped on DMA1 channel 2
+  *            @arg REMAP_DMA1Channel_TIM4ToChannel3: TIM4 DMA1 req/ack mapped on DMA1 channel 3              
+  * @retval None
+  */
+void SYSCFG_REMAPDMAChannelConfig(REMAP_DMAChannel_TypeDef REMAP_DMAChannel)
+{
+  /* Check the parameters */
+  assert_param(IS_REMAP_DMACHANNEL(REMAP_DMAChannel));
+
+  /* Check if the TIM4 DMA channel is selected: bits 4 --> 7 are set */
+  if ((REMAP_DMAChannel & 0xF0) != RESET)
+  {
+    /* Reset the TIM4 DMA channels */
+    SYSCFG->RMPCR1 &= (uint8_t) (~SYSCFG_RMPCR1_TIM4DMA_REMAP);
+  }
+  /* ADC DMA channel is selected: bits 4 --> 7 are reset */
+  else
+  {
+    /* Reset the ADC DMA channels */
+    SYSCFG->RMPCR1 &= (uint8_t) (~SYSCFG_RMPCR1_ADC1DMA_REMAP);
+  }
+  /* Set the DMA Channels remapping */
+  SYSCFG->RMPCR1 |= (uint8_t) ((uint8_t)0x0F & REMAP_DMAChannel);
+}
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+  
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_tim1.c b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_tim1.c
new file mode 100755
index 0000000..c9c1982
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_tim1.c
@@ -0,0 +1,2771 @@
+/**
+  ******************************************************************************
+  * @file    stm8l15x_tim1.c
+  * @author  MCD Application Team
+  * @version V1.6.0
+  * @date    28-June-2013
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the TIM1 peripheral:
+  *            - TimeBase management
+  *            - Output Compare management
+  *            - Input Capture management
+  *            - Interrupts, DMA and flags management
+  *            - Clocks management
+  *            - Synchronization management
+  *            - Specific interface management
+  *              
+  *  @verbatim
+  *  
+  *          ===================================================================
+  *                                 How to use this driver
+  *          ===================================================================
+  *          This driver provides functions to configure and initialise the TIM1 
+  *          peripheral
+  *          These functions are split in 7 groups: 
+  *   
+  *          1. TIM1 TimeBase management: this group includes all needed functions 
+  *             to configure the TIM Timebase unit:
+  *                   - Set/Get Prescaler
+  *                   - Set/Get Autoreload  
+  *                   - Counter modes configuration
+  *                   - Select the One Pulse mode
+  *                   - Update Request Configuration
+  *                   - Update Disable Configuration
+  *                   - Auto-Preload Configuration 
+  *                   - Enable/Disable the counter
+  *                 
+  *          2. TIM1 Output Compare management: this group includes all needed 
+  *             functions to configure the Capture/Compare unit used in Output 
+  *             compare mode: 
+  *                   - Configure each channel, independently, in Output Compare mode
+  *                   - Select the output compare modes
+  *                   - Select the Polarities of each channel
+  *                   - Set/Get the Capture/Compare register values
+  *                   - Select the Output Compare Fast mode 
+  *                   - Select the Output Compare Forced mode  
+  *                   - Output Compare-Preload Configuration 
+  *                   - Clear Output Compare Reference
+  *                   - Select the OCREF Clear signal
+  *                   - Enable/Disable the Capture/Compare Channels    
+  *                   
+  *          3. TIM1 Input Capture management: this group includes all needed 
+  *             functions to configure the Capture/Compare unit used in 
+  *             Input Capture mode:
+  *                   - Configure each channel in input capture mode
+  *                   - Configure Channel1/2 in PWM Input mode
+  *                   - Set the Input Capture Prescaler
+  *                   - Get the Capture/Compare values      
+  *        
+  *          4. TIM1 interrupts, DMA and flags management
+  *                   - Enable/Disable interrupt sources
+  *                   - Get flags status
+  *                   - Clear flags/ Pending bits
+  *                   - Enable/Disable DMA requests 
+  *                   - Configure DMA burst mode
+  *                   - Select CaptureCompare DMA request  
+  *              
+  *          5. TIM1 clocks management: this group includes all needed functions 
+  *             to configure the clock controller unit:
+  *                   - Select internal/External clock
+  *                   - Select the external clock mode: ETR(Mode1/Mode2) or TIx
+  *         
+  *          6. TIM1 synchronization management: this group includes all needed 
+  *             functions to configure the Synchronization unit:
+  *                   - Select Input Trigger  
+  *                   - Select Output Trigger  
+  *                   - Select Master Slave Mode 
+  *                   - ETR Configuration when used as external trigger   
+  *     
+  *          7. TIM1 specific interface management, this group includes all 
+  *             needed functions to use the specific TIM1 interface:
+  *                   - Encoder Interface Configuration
+  *                   - Select Hall Sensor        
+  *   
+  *  @endverbatim
+  *    
+  ******************************************************************************
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ****************************************************************************** 
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm8l15x_tim1.h"
+
+/** @addtogroup STM8L15x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup TIM1
+  * @brief TIM1 driver modules
+  * @{
+  */
+  
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup TIM1_Private_Functions_Prototypes
+  * @{
+  */
+
+static void TI1_Config(uint8_t TIM1_ICPolarity, uint8_t TIM1_ICSelection,
+                       uint8_t TIM1_ICFilter);
+static void TI2_Config(uint8_t TIM1_ICPolarity, uint8_t TIM1_ICSelection,
+                       uint8_t TIM1_ICFilter);
+static void TI3_Config(uint8_t TIM1_ICPolarity, uint8_t TIM1_ICSelection,
+                       uint8_t TIM1_ICFilter);
+static void TI4_Config(uint8_t TIM1_ICPolarity, uint8_t TIM1_ICSelection,
+                       uint8_t TIM1_ICFilter);
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/  
+/** @defgroup TIM1_Private_Functions
+  * @{
+  */
+
+/** @defgroup TIM1_Group1 TimeBase management functions
+ *  @brief   TimeBase management functions 
+ *
+@verbatim   
+ ===============================================================================
+                       TimeBase management functions
+ ===============================================================================  
+  
+       ===================================================================      
+              TIM1 Driver: how to use it in Timing(Time base) Mode
+       =================================================================== 
+       To use the Timer in Timing(Time base) mode, the following steps are mandatory:
+       
+       1. Enable TIM1 clock using CLK_PeripheralClockConfig(CLK_Peripheral_TIM1, ENABLE) function.
+        
+       2. Call TIM1_TimeBaseInit() to configure the Time Base unit with the
+          corresponding configuration.
+          
+       3. Enable global interrupts if you need to generate the update interrupt.
+          
+       4. Enable the corresponding interrupt using the function TIM1_ITConfig(TIM1_IT_Update) 
+          
+       5. Call the TIM1_Cmd(ENABLE) function to enable the TIM1 counter.
+       
+       Note1: All other functions can be used separately to modify, if needed,
+          a specific feature of the Timer. 
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the TIM1 peripheral registers to their default reset values.
+  * @param  None
+  * @retval None
+  */
+void TIM1_DeInit(void)
+{
+  TIM1->CR1  = TIM1_CR1_RESET_VALUE;
+  TIM1->CR2  = TIM1_CR2_RESET_VALUE;
+  TIM1->SMCR = TIM1_SMCR_RESET_VALUE;
+  TIM1->ETR  = TIM1_ETR_RESET_VALUE;
+  TIM1->IER  = TIM1_IER_RESET_VALUE;
+
+  /* Disable channels */
+  TIM1->CCER1 = TIM1_CCER1_RESET_VALUE;
+  TIM1->CCER2 = TIM1_CCER2_RESET_VALUE;
+  /* Configure channels as inputs: it is necessary if lock level is equal to 2 or 3 */
+  TIM1->CCMR1 = 0x01;
+  TIM1->CCMR2 = 0x01;
+  TIM1->CCMR3 = 0x01;
+  TIM1->CCMR4 = 0x01;
+  /* Then reset channel registers: it also works if lock level is equal to 2 or 3 */
+  TIM1->CCER1 = TIM1_CCER1_RESET_VALUE;
+  TIM1->CCER2 = TIM1_CCER2_RESET_VALUE;
+  TIM1->CCMR1 = TIM1_CCMR1_RESET_VALUE;
+  TIM1->CCMR2 = TIM1_CCMR2_RESET_VALUE;
+  TIM1->CCMR3 = TIM1_CCMR3_RESET_VALUE;
+  TIM1->CCMR4 = TIM1_CCMR4_RESET_VALUE;
+  TIM1->CNTRH = TIM1_CNTRH_RESET_VALUE;
+  TIM1->CNTRL = TIM1_CNTRL_RESET_VALUE;
+  TIM1->PSCRH = TIM1_PSCRH_RESET_VALUE;
+  TIM1->PSCRL = TIM1_PSCRL_RESET_VALUE;
+  TIM1->ARRH  = TIM1_ARRH_RESET_VALUE;
+  TIM1->ARRL  = TIM1_ARRL_RESET_VALUE;
+  TIM1->CCR1H = TIM1_CCR1H_RESET_VALUE;
+  TIM1->CCR1L = TIM1_CCR1L_RESET_VALUE;
+  TIM1->CCR2H = TIM1_CCR2H_RESET_VALUE;
+  TIM1->CCR2L = TIM1_CCR2L_RESET_VALUE;
+  TIM1->CCR3H = TIM1_CCR3H_RESET_VALUE;
+  TIM1->CCR3L = TIM1_CCR3L_RESET_VALUE;
+  TIM1->CCR4H = TIM1_CCR4H_RESET_VALUE;
+  TIM1->CCR4L = TIM1_CCR4L_RESET_VALUE;
+  TIM1->OISR  = TIM1_OISR_RESET_VALUE;
+  TIM1->EGR   = 0x01; /* TIM1_EGR_UG */
+  TIM1->DTR   = TIM1_DTR_RESET_VALUE;
+  TIM1->BKR   = TIM1_BKR_RESET_VALUE;
+  TIM1->RCR   = TIM1_RCR_RESET_VALUE;
+  TIM1->SR1   = TIM1_SR1_RESET_VALUE;
+  TIM1->SR2   = TIM1_SR2_RESET_VALUE;
+}
+
+/**
+  * @brief  Initializes the TIM1 Time Base Unit according to the specified parameters.
+  * @param  TIM1_Prescaler specifies the Prescaler value.
+  * @param  TIM1_CounterMode specifies the counter mode from
+  *          This parameter can be one of the following values:
+  *            @arg TIM1_CounterMode_Up: Counter mode Up
+  *            @arg TIM1_CounterMode_Down: Counter mode Down
+  *            @arg TIM1_CounterMode_CenterAligned1: Counter mode center aligned
+  *            @arg TIM1_CounterMode_CenterAligned2: Counter mode center aligned
+  *            @arg TIM1_CounterMode_CenterAligned3: Counter mode center aligned
+  * @param  TIM1_Period specifies the Period value.
+  * @param  TIM1_RepetitionCounter specifies the Repetition counter value
+  * @retval None
+  */
+void TIM1_TimeBaseInit(uint16_t TIM1_Prescaler,
+                       TIM1_CounterMode_TypeDef TIM1_CounterMode,
+                       uint16_t TIM1_Period,
+                       uint8_t TIM1_RepetitionCounter)
+{
+  /* Check parameters */
+  assert_param(IS_TIM1_COUNTER_MODE(TIM1_CounterMode));
+
+
+  /* Set the Autoreload value */
+  TIM1->ARRH = (uint8_t)(TIM1_Period >> 8);
+  TIM1->ARRL = (uint8_t)(TIM1_Period);
+
+  /* Set the Prescaler value */
+  TIM1->PSCRH = (uint8_t)(TIM1_Prescaler >> 8);
+  TIM1->PSCRL = (uint8_t)(TIM1_Prescaler);
+
+  /* Select the Counter Mode */
+  TIM1->CR1 = (uint8_t)((uint8_t)(TIM1->CR1 & (uint8_t)(~(TIM1_CR1_CMS | TIM1_CR1_DIR)))
+                        | (uint8_t)(TIM1_CounterMode));
+
+  /* Set the Repetition Counter value */
+  TIM1->RCR = TIM1_RepetitionCounter;
+
+}
+
+/**
+  * @brief  Configures the TIM1 Prescaler.
+  * @param  Prescaler specifies the Prescaler Register value
+  *          This parameter must be a value between 0x0000 and 0xFFFF
+  * @param  TIM1_PSCReloadMode specifies the TIM1 Prescaler Reload mode.
+  *          This parameter can be one of the following values
+  *            @arg TIM1_PSCReloadMode_Immediate: The Prescaler is loaded immediately.
+  *            @arg TIM1_PSCReloadMode_Update: The Prescaler is loaded at the update
+  *         event.
+  * @retval None
+  */
+
+void TIM1_PrescalerConfig(uint16_t Prescaler, TIM1_PSCReloadMode_TypeDef TIM1_PSCReloadMode)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM1_PRESCALER_RELOAD(TIM1_PSCReloadMode));
+
+  /* Set the Prescaler value */
+  TIM1->PSCRH = (uint8_t)(Prescaler >> 8);
+  TIM1->PSCRL = (uint8_t)(Prescaler);
+
+  /* Set or reset the UG Bit */
+  TIM1->EGR = (uint8_t)TIM1_PSCReloadMode;
+}
+
+/**
+  * @brief  Specifies the TIM1 Counter Mode to be used.
+  * @param  TIM1_CounterMode specifies the Counter Mode to be used
+  *          This parameter can be one of the following values:
+  *            @arg TIM1_CounterMode_Up: TIM1 Up Counting Mode
+  *            @arg TIM1_CounterMode_Down: TIM1 Down Counting Mode
+  *            @arg TIM1_CounterMode_CenterAligned1: TIM1 Center Aligned Mode1
+  *            @arg TIM1_CounterMode_CenterAligned2: TIM1 Center Aligned Mode2
+  *            @arg IM1_CounterMode_CenterAligned3: TIM1 Center Aligned Mode3
+  * @retval None
+  */
+void TIM1_CounterModeConfig(TIM1_CounterMode_TypeDef TIM1_CounterMode)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM1_COUNTER_MODE(TIM1_CounterMode));
+
+
+  /* Reset the CMS and DIR Bits & Set the Counter Mode */
+  TIM1->CR1 = (uint8_t)((uint8_t)(TIM1->CR1 & (uint8_t)((uint8_t)(~TIM1_CR1_CMS) & (uint8_t)(~TIM1_CR1_DIR)))
+                        | (uint8_t)TIM1_CounterMode);
+}
+
+/**
+  * @brief  Sets the TIM1 Counter Register value.
+  * @param  Counter specifies the Counter register new value.
+  *          This parameter is between 0x0000 and 0xFFFF.
+  * @retval None
+  */
+void TIM1_SetCounter(uint16_t Counter)
+{
+  /* Set the Counter Register value */
+  TIM1->CNTRH = (uint8_t)(Counter >> 8);
+  TIM1->CNTRL = (uint8_t)(Counter);
+}
+
+/**
+  * @brief  Sets the TIM1 Autoreload Register value.
+  * @param  Autoreload specifies the Autoreload register new value.
+  *          This parameter is between 0x0000 and 0xFFFF.
+  * @retval None
+  */
+void TIM1_SetAutoreload(uint16_t Autoreload)
+{
+  /* Set the Autoreload Register value */
+  TIM1->ARRH = (uint8_t)(Autoreload >> 8);
+  TIM1->ARRL = (uint8_t)(Autoreload);
+}
+
+/**
+  * @brief  Gets the TIM1 Counter value.
+  * @param  None
+  * @retval Counter Register value.
+  */
+uint16_t TIM1_GetCounter(void)
+{
+  /* Get the Counter Register value */
+  uint16_t tmpcntr = 0;
+  uint8_t tmpcntrl = 0, tmpcntrh = 0;
+
+  tmpcntrh = TIM1->CNTRH;
+  tmpcntrl = TIM1->CNTRL;
+
+  tmpcntr  = (uint16_t)(tmpcntrl);
+  tmpcntr |= (uint16_t)((uint16_t)tmpcntrh << 8);
+
+  /* Get the Counter Register value */
+  return (uint16_t)tmpcntr;
+}
+
+/**
+  * @brief  Gets the TIM1 Prescaler value.
+  * @param  None
+  * @retval Prescaler Register value.
+  */
+uint16_t TIM1_GetPrescaler(void)
+{
+  uint16_t tmpreg = 0;
+  tmpreg = (uint16_t)((uint16_t)TIM1->PSCRH << 8);
+  /* Get the Prescaler Register value */
+  return (uint16_t)(tmpreg | TIM1->PSCRL);
+}
+
+/**
+  * @brief  Enables or Disables the TIM1 Update event.
+  * @param  NewState new state of the TIM1 peripheral Preload register.
+  *          This parameter can be ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM1_UpdateDisableConfig(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Set or Reset the UDIS Bit */
+  if (NewState != DISABLE)
+  {
+    TIM1->CR1 |= TIM1_CR1_UDIS;
+  }
+  else
+  {
+    TIM1->CR1 &= (uint8_t)(~TIM1_CR1_UDIS);
+  }
+}
+
+/**
+  * @brief  Selects the TIM1 Update Request Interrupt source.
+  * @param  TIM1_UpdateSource specifies the Update source.
+  *          This parameter can be one of the following values
+  *            @arg TIM1_UpdateSource_Regular
+  *            @arg TIM1_UpdateSource_Global
+  * @retval None
+  */
+void TIM1_UpdateRequestConfig(TIM1_UpdateSource_TypeDef TIM1_UpdateSource)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM1_UPDATE_SOURCE(TIM1_UpdateSource));
+
+  /* Set or Reset the URS Bit */
+  if (TIM1_UpdateSource != TIM1_UpdateSource_Global)
+  {
+    TIM1->CR1 |= TIM1_CR1_URS;
+  }
+  else
+  {
+    TIM1->CR1 &= (uint8_t)(~TIM1_CR1_URS);
+  }
+}
+
+/**
+  * @brief  Enables or disables TIM1 peripheral Preload register on ARR.
+  * @param  NewState new state of the TIM1 peripheral Preload register.
+  *          This parameter can be ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM1_ARRPreloadConfig(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Set or Reset the ARPE Bit */
+  if (NewState != DISABLE)
+  {
+    TIM1->CR1 |= TIM1_CR1_ARPE;
+  }
+  else
+  {
+    TIM1->CR1 &= (uint8_t)(~TIM1_CR1_ARPE);
+  }
+}
+
+/**
+  * @brief  Selects the TIM1’s One Pulse Mode.
+  * @param  TIM1_OPMode specifies the OPM Mode to be used.
+  *          This parameter can be one of the following values
+  *            @arg TIM1_OPMode_Single
+  *            @arg TIM1_OPMode_Repetitive
+  * @retval None
+  */
+void TIM1_SelectOnePulseMode(TIM1_OPMode_TypeDef TIM1_OPMode)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM1_OPM_MODE(TIM1_OPMode));
+
+  /* Set or Reset the OPM Bit */
+  if (TIM1_OPMode != TIM1_OPMode_Repetitive)
+  {
+    TIM1->CR1 |= TIM1_CR1_OPM;
+  }
+  else
+  {
+    TIM1->CR1 &= (uint8_t)(~TIM1_CR1_OPM);
+  }
+}
+
+/**
+  * @brief  Enables or disables the TIM1 peripheral.
+  * @param  NewState new state of the TIM1 peripheral. 
+  *          This parameter can be ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM1_Cmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* set or Reset the CEN Bit */
+  if (NewState != DISABLE)
+  {
+    TIM1->CR1 |= TIM1_CR1_CEN;
+  }
+  else
+  {
+    TIM1->CR1 &= (uint8_t)(~TIM1_CR1_CEN);
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM1_Group2 Output Compare management functions
+ *  @brief    Output Compare management functions 
+ *
+@verbatim   
+ ===============================================================================
+                        Output Compare management functions
+ ===============================================================================  
+   
+       ===================================================================      
+              TIM1 Driver: how to use it in Output Compare Mode
+       =================================================================== 
+       To use the Timer in Output Compare mode, the following steps are mandatory:
+       
+       1. Enable TIM1 clock using CLK_PeripheralClockConfig(CLK_Peripheral_TIM1, ENABLE) function.
+       
+       2. Configure the TIM1 pins in output mode by configuring the corresponding GPIO pins
+          
+       3. Configure the Time base unit as described in the first part of this driver, if needed,
+          otherwise the Timer will run with the default configuration:
+          - Autoreload value = 0xFFFF
+          - Prescaler value = 0x0000
+          - Counter mode = Up counting
+      
+       4. Call TIM1_OCxInit() to configure the channel x with the desired parameters
+          including:
+          - TIM1 Output Compare mode: TIM1_OCMode
+          - TIM1 Output State: TIM1_OutputState
+          - TIM1 Complementary Output State: TIM1_OutputNState
+          - TIM1 Pulse value: TIM1_Pulse
+          - TIM1 Output Compare Polarity : TIM1_OCPolarity
+          - TIM1 Complementary Output Compare Polarity : TIM1_OCNPolarity
+          - TIM1 Output Idle State: TIM1_OCIdleState
+          - TIM1 Complementary Output Idle State: TIM1_OCNIdleState
+       
+       5. Call the TIM1_Cmd(ENABLE) function to enable the TIM1 counter.
+       
+       Note1: All other functions can be used separately to modify, if needed,
+          a specific feature of the Timer. 
+       
+       Note2: If the corresponding interrupt or DMA request are needed, the user should:
+              1. Enable global interrupts (or the DMA) to use the TIM1 interrupts (or DMA requests). 
+              2. Enable the corresponding interrupt (or DMA request) using the function 
+              TIM1_ITConfig(TIM1_IT_CCx) (or TIM1_DMACmd(TIM1_DMASource_CCx))   
+
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Initializes the TIM1 Channel1 according to the specified parameters.
+  * @param  TIM1_OCMode specifies the Output Compare mode
+  *          This parameter can be one of the following values:
+  *            @arg TIM1_OCMode_Timing: OC Mode Timing
+  *            @arg TIM1_OCMode_Active: OC Mode Active
+  *            @arg TIM1_OCMode_Inactive: OC Mode Inactive
+  *            @arg TIM1_OCMode_Toggle: OC Mode Toggle
+  *            @arg TIM1_OCMode_PWM1: OC Mode PWM1
+  *            @arg TIM1_OCMode_PWM2: OC Mode PWM2          
+  * @param  TIM1_OutputState specifies the Output State
+  *          This parameter can be one of the following values:
+  *            @arg TIM1_OutputState_Disable: Output state disable
+  *            @arg TIM1_OutputState_Enable: Output state enable
+  * @param  TIM1_OutputNState specifies the Complementary Output State
+  *          This parameter can be one of the following values:
+  *            @arg TIM1_OutputNState_Disable: Output N state disable
+  *            @arg TIM1_OutputNState_Enable: Output N state enable
+  * @param  TIM1_Pulse specifies the Pulse width value.
+  * @param  TIM1_OCPolarity specifies the Output Compare Polarity
+  *          This parameter can be one of the following values:
+  *            @arg TIM1_OCPolarity_High: Output Compare active low
+  *            @arg TIM1_OCPolarity_Low: Output Compare active high
+  * @param  TIM1_OCNPolarity specifies the Complementary Output Compare Polarity 
+  *          This parameter can be one of the following values:
+  *            @arg TIM1_OCNPolarity_High: Complementary Output Compare active low
+  *            @arg TIM1_OCNPolarity_Low: Complementary Output Compare active high
+  * @param  TIM1_OCIdleState specifies the Output Compare Idle State
+  *          This parameter can be one of the following values:
+  *            @arg TIM1_OCIdleState_Set: Output Compare Idle state set
+  *            @arg TIM1_OCIdleState_Reset: Output Compare Idle state reset
+  * @param  TIM1_OCNIdleState specifies the Complementary Output Compare Idle State
+  *          This parameter can be one of the following values:
+  *            @arg TIM1_OCNIdleState_Set: Complementary Output Compare Idle state set
+  *            @arg TIM1_OCNIdleState_Reset: Complementary Output Compare Idle state reset
+  * @retval None
+  */
+void TIM1_OC1Init(TIM1_OCMode_TypeDef TIM1_OCMode,
+                  TIM1_OutputState_TypeDef TIM1_OutputState,
+                  TIM1_OutputNState_TypeDef TIM1_OutputNState,
+                  uint16_t TIM1_Pulse,
+                  TIM1_OCPolarity_TypeDef TIM1_OCPolarity,
+                  TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity,
+                  TIM1_OCIdleState_TypeDef TIM1_OCIdleState,
+                  TIM1_OCNIdleState_TypeDef TIM1_OCNIdleState)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM1_OC_MODE(TIM1_OCMode));
+  assert_param(IS_TIM1_OUTPUT_STATE(TIM1_OutputState));
+  assert_param(IS_TIM1_OUTPUTN_STATE(TIM1_OutputNState));
+  assert_param(IS_TIM1_OC_POLARITY(TIM1_OCPolarity));
+  assert_param(IS_TIM1_OCN_POLARITY(TIM1_OCNPolarity));
+  assert_param(IS_TIM1_OCIDLE_STATE(TIM1_OCIdleState));
+  assert_param(IS_TIM1_OCNIDLE_STATE(TIM1_OCNIdleState));
+
+  /* Disable the Channel 1: Reset the CCE Bit, Set the Output State ,
+  the Output N State, the Output Polarity & the Output N Polarity*/
+  TIM1->CCER1 &= (uint8_t)(~(TIM1_CCER1_CC1E | TIM1_CCER1_CC1NE
+                             | TIM1_CCER1_CC1P | TIM1_CCER1_CC1NP));
+  /* Set the Output State & Set the Output N State & Set the Output Polarity
+  & Set the Output N Polarity */
+  TIM1->CCER1 |= (uint8_t)((uint8_t)((uint8_t)(TIM1_OutputState & TIM1_CCER1_CC1E)
+                                     | (uint8_t)(TIM1_OutputNState & TIM1_CCER1_CC1NE))
+                           | (uint8_t)( (uint8_t)(TIM1_OCPolarity  & TIM1_CCER1_CC1P)
+                                        | (uint8_t)(TIM1_OCNPolarity & TIM1_CCER1_CC1NP)));
+
+  /* Reset the Output Compare Bits & Set the Output Compare Mode */
+  TIM1->CCMR1 = (uint8_t)((uint8_t)(TIM1->CCMR1 & (uint8_t)(~TIM1_CCMR_OCM))
+                          | (uint8_t)TIM1_OCMode);
+
+  /* Reset the Output Idle state & the Output N Idle state bits */
+  TIM1->OISR &= (uint8_t)(~(TIM1_OISR_OIS1 | TIM1_OISR_OIS1N));
+  /* Set the Output Idle state & the Output N Idle state configuration */
+  TIM1->OISR |= (uint8_t)((uint8_t)(TIM1_OCIdleState & TIM1_OISR_OIS1)
+                          | (uint8_t)(TIM1_OCNIdleState & TIM1_OISR_OIS1N));
+
+  /* Set the Pulse value */
+  TIM1->CCR1H = (uint8_t)(TIM1_Pulse >> 8);
+  TIM1->CCR1L = (uint8_t)(TIM1_Pulse);
+}
+
+/**
+  * @brief  Initializes the TIM1 Channel2 according to the specified parameters.
+  * @param  TIM1_OCMode specifies the Output Compare mode
+  *          This parameter can be one of the following values:
+  *            @arg TIM1_OCMode_Timing: OC Mode Timing
+  *            @arg TIM1_OCMode_Active: OC Mode Active
+  *            @arg TIM1_OCMode_Inactive: OC Mode Inactive
+  *            @arg TIM1_OCMode_Toggle: OC Mode Toggle
+  *            @arg TIM1_OCMode_PWM1: OC Mode PWM1
+  *            @arg TIM1_OCMode_PWM2: OC Mode PWM2  
+  * @param  TIM1_OutputState specifies the Output State
+  *          This parameter can be one of the following values:
+  *            @arg TIM1_OutputState_Disable: Output state disable
+  *            @arg TIM1_OutputState_Enable: Output state enable
+  * @param  TIM1_OutputNState specifies the Complementary Output State
+  *          This parameter can be one of the following values:
+  *            @arg TIM1_OutputNState_Disable: Output N state disable
+  *            @arg TIM1_OutputNState_Enable: Output N state enable
+  * @param  TIM1_Pulse specifies the Pulse width value.
+  * @param  TIM1_OCPolarity specifies the Output Compare Polarity
+  *          This parameter can be one of the following values:
+  *            @arg TIM1_OCPolarity_High: Output Compare active low
+  *            @arg TIM1_OCPolarity_Low: Output Compare active high
+  * @param  TIM1_OCNPolarity specifies the Complementary Output Compare
+  *          This parameter can be one of the following values:
+  *            @arg TIM1_OCNPolarity_High: Complementary Output Compare active low
+  *            @arg TIM1_OCNPolarity_Low: Complementary Output Compare active high
+  * @param  TIM1_OCIdleState specifies the Output Compare Idle State
+  *          This parameter can be one of the following values:
+  *            @arg TIM1_OCIdleState_Set: Output Compare Idle state set
+  *            @arg TIM1_OCIdleState_Reset: Output Compare Idle state reset
+  * @param  TIM1_OCNIdleState specifies the Complementary Output Compare Idle State
+  *          This parameter can be one of the following values:
+  *            @arg TIM1_OCNIdleState_Set: Complementary Output Compare Idle state set
+  *            @arg TIM1_OCNIdleState_Reset: Complementary Output Compare Idle state reset
+  * @retval None
+  */
+void TIM1_OC2Init(TIM1_OCMode_TypeDef TIM1_OCMode,
+                  TIM1_OutputState_TypeDef TIM1_OutputState,
+                  TIM1_OutputNState_TypeDef TIM1_OutputNState,
+                  uint16_t TIM1_Pulse,
+                  TIM1_OCPolarity_TypeDef TIM1_OCPolarity,
+                  TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity,
+                  TIM1_OCIdleState_TypeDef TIM1_OCIdleState,
+                  TIM1_OCNIdleState_TypeDef TIM1_OCNIdleState)
+{
+
+  /* Check the parameters */
+  assert_param(IS_TIM1_OC_MODE(TIM1_OCMode));
+  assert_param(IS_TIM1_OUTPUT_STATE(TIM1_OutputState));
+  assert_param(IS_TIM1_OUTPUTN_STATE(TIM1_OutputNState));
+  assert_param(IS_TIM1_OC_POLARITY(TIM1_OCPolarity));
+  assert_param(IS_TIM1_OCN_POLARITY(TIM1_OCNPolarity));
+  assert_param(IS_TIM1_OCIDLE_STATE(TIM1_OCIdleState));
+  assert_param(IS_TIM1_OCNIDLE_STATE(TIM1_OCNIdleState));
+
+  /* Disable the Channel 1: Reset the CCE Bit, Set the Output State,
+     the Output N State, the Output Polarity & the Output N Polarity*/
+  TIM1->CCER1 &= (uint8_t)(~(TIM1_CCER1_CC2E | TIM1_CCER1_CC2NE | TIM1_CCER1_CC2P | TIM1_CCER1_CC2NP));
+
+  /* Set the Output State & Set the Output N State & Set the Output Polarity & Set the Output N Polarity */
+  TIM1->CCER1 |= (uint8_t)((uint8_t)((uint8_t)(TIM1_OutputState & TIM1_CCER1_CC2E) | (uint8_t)(TIM1_OutputNState & TIM1_CCER1_CC2NE))
+                           | (uint8_t) ((uint8_t)(TIM1_OCPolarity & TIM1_CCER1_CC2P) | (uint8_t)(TIM1_OCNPolarity & TIM1_CCER1_CC2NP)));
+
+  /* Reset the Output Compare Bits & Set the Output Compare Mode */
+  TIM1->CCMR2 = (uint8_t)((uint8_t)(TIM1->CCMR2 & (uint8_t)(~TIM1_CCMR_OCM)) | (uint8_t)TIM1_OCMode);
+
+  /* Reset the Output Idle state & the Output N Idle state bits */
+  TIM1->OISR &= (uint8_t)(~(TIM1_OISR_OIS2 | TIM1_OISR_OIS2N));
+  /* Set the Output Idle state & the Output N Idle state configuration */
+  TIM1->OISR |= (uint8_t)((uint8_t)(TIM1_OISR_OIS2 & TIM1_OCIdleState) | (uint8_t)(TIM1_OISR_OIS2N & TIM1_OCNIdleState));
+
+  /* Set the Pulse value */
+  TIM1->CCR2H = (uint8_t)(TIM1_Pulse >> 8);
+  TIM1->CCR2L = (uint8_t)(TIM1_Pulse);
+}
+
+/**
+  * @brief  Initializes the TIM1 Channel3 according to the specified parameters.
+  * @param  TIM1_OCMode specifies the Output Compare mode
+  *          This parameter can be one of the following values:
+  *            @arg TIM1_OCMode_Timing: OC Mode Timing
+  *            @arg TIM1_OCMode_Active: OC Mode Active
+  *            @arg TIM1_OCMode_Inactive: OC Mode Inactive
+  *            @arg TIM1_OCMode_Toggle: OC Mode Toggle
+  *            @arg TIM1_OCMode_PWM1: OC Mode PWM1
+  *            @arg TIM1_OCMode_PWM2: OC Mode PWM2     
+  * @param  TIM1_OutputState specifies the Output State
+  *          This parameter can be one of the following values:
+  *            @arg TIM1_OutputState_Disable: Output state disable
+  *            @arg TIM1_OutputState_Enable: Output state enable
+  * @param  TIM1_OutputNState specifies the Complementary Output State
+  *          This parameter can be one of the following values:
+  *            @arg TIM1_OutputNState_Disable: Output N state disable
+  *            @arg TIM1_OutputNState_Enable: Output N state enable
+  * @param  TIM1_Pulse specifies the Pulse width value.
+  * @param  TIM1_OCPolarity specifies the Output Compare Polarity
+  *          This parameter can be one of the following values:
+  *            @arg TIM1_OCPolarity_High: Output Compare active low
+  *            @arg TIM1_OCPolarity_Low: Output Compare active high
+  * @param  TIM1_OCNPolarity specifies the Complementary Output Compare Polarity
+  *          This parameter can be one of the following values:
+  *            @arg TIM1_OCNPolarity_High: Complementary Output Compare active low
+  *            @arg TIM1_OCNPolarity_Low: Complementary Output Compare active high
+  * @param  TIM1_OCIdleState specifies the Output Compare Idle State
+  *          This parameter can be one of the following values:
+  *            @arg TIM1_OCIdleState_Set: Output Compare Idle state set
+  *            @arg TIM1_OCIdleState_Reset: Output Compare Idle state reset
+  * @param  TIM1_OCNIdleState specifies the Complementary Output Compare Idle State
+  *          This parameter can be one of the following values:
+  *            @arg TIM1_OCNIdleState_Set: Complementary Output Compare Idle state set
+  *            @arg TIM1_OCNIdleState_Reset: Complementary Output Compare Idle state reset
+  * @retval None
+  */
+void TIM1_OC3Init(TIM1_OCMode_TypeDef TIM1_OCMode,
+                  TIM1_OutputState_TypeDef TIM1_OutputState,
+                  TIM1_OutputNState_TypeDef TIM1_OutputNState,
+                  uint16_t TIM1_Pulse,
+                  TIM1_OCPolarity_TypeDef TIM1_OCPolarity,
+                  TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity,
+                  TIM1_OCIdleState_TypeDef TIM1_OCIdleState,
+                  TIM1_OCNIdleState_TypeDef TIM1_OCNIdleState)
+{
+
+  /* Check the parameters */
+  assert_param(IS_TIM1_OC_MODE(TIM1_OCMode));
+  assert_param(IS_TIM1_OUTPUT_STATE(TIM1_OutputState));
+  assert_param(IS_TIM1_OUTPUTN_STATE(TIM1_OutputNState));
+  assert_param(IS_TIM1_OC_POLARITY(TIM1_OCPolarity));
+  assert_param(IS_TIM1_OCN_POLARITY(TIM1_OCNPolarity));
+  assert_param(IS_TIM1_OCIDLE_STATE(TIM1_OCIdleState));
+  assert_param(IS_TIM1_OCNIDLE_STATE(TIM1_OCNIdleState));
+
+  /* Disable the Channel 1: Reset the CCE Bit, Set the Output State,
+     the Output N State, the Output Polarity & the Output N Polarity */
+  TIM1->CCER2 &= (uint8_t)(~( TIM1_CCER2_CC3E | TIM1_CCER2_CC3NE | TIM1_CCER2_CC3P | TIM1_CCER2_CC3NP));
+
+  /* Set the Output State & Set the Output N State & Set the Output Polarity & Set the Output N Polarity */
+  TIM1->CCER2 |= (uint8_t)((uint8_t)((uint8_t)(TIM1_OutputState & TIM1_CCER2_CC3E) | (uint8_t)(TIM1_OutputNState & TIM1_CCER2_CC3NE))
+                           | (uint8_t)((uint8_t)(TIM1_OCPolarity & TIM1_CCER2_CC3P) | (uint8_t)(TIM1_OCNPolarity & TIM1_CCER2_CC3NP)));
+
+  /* Reset the Output Compare Bits & Set the Output Compare Mode */
+  TIM1->CCMR3 = (uint8_t)((uint8_t)(TIM1->CCMR3 & (uint8_t)(~TIM1_CCMR_OCM)) | (uint8_t)TIM1_OCMode);
+
+  /* Reset the Output Idle state & the Output N Idle state bits */
+  TIM1->OISR &= (uint8_t)(~(TIM1_OISR_OIS3 | TIM1_OISR_OIS3N));
+  /* Set the Output Idle state & the Output N Idle state configuration */
+  TIM1->OISR |= (uint8_t)((uint8_t)(TIM1_OISR_OIS3 & TIM1_OCIdleState) | (uint8_t) (TIM1_OISR_OIS3N & TIM1_OCNIdleState));
+
+  /* Set the Pulse value */
+  TIM1->CCR3H = (uint8_t)(TIM1_Pulse >> 8);
+  TIM1->CCR3L = (uint8_t)(TIM1_Pulse);
+}
+
+/**
+  * @brief  Configures the Break feature, dead time, Lock level, the OSSI,
+  *         and the AOE(automatic output enable).
+  * @param  TIM1_OSSIState specifies the OSSIS State
+  *          This parameter can be one of the following values:
+  *            @arg TIM1_OSSIState_Enable: OSSIS State enabled
+  *            @arg TIM1_OSSIState_Disable: OSSIS State disabled   
+  * @param  TIM1_LockLevel specifies the lock level
+  *          This parameter can be one of the following values:
+  *            @arg TIM1_LockLevel_Off: No lock level
+  *            @arg TIM1_LockLevel_1: Lock level 1  
+  *            @arg TIM1_LockLevel_2: Lock level 2
+  *            @arg TIM1_LockLevel_3: Lock level 3
+  * @param  TIM1_DeadTime specifies the dead time value.
+  * @param  TIM1_Break specifies the Break state
+  *          This parameter can be one of the following values:
+  *            @arg TIM1_BreakState_Enable: Break enabled
+  *            @arg TIM1_BreakState_Disable: Break disabled  
+  * @param  TIM1_BreakPolarity specifies the Break polarity
+  *          This parameter can be one of the following values:
+  *            @arg TIM1_BreakPolarity_Low: Break polarity high
+  *            @arg TIM1_BreakPolarity_High: Break polarity low
+  * @param  TIM1_AutomaticOutput specifies the Automatic Output configuration
+  *          This parameter can be one of the following values:
+  *            @arg TIM1_AutomaticOutput_Enable: Automatic Output enabled
+  *            @arg TIM1_AutomaticOutput_Disable: Automatic Output disabled  
+  * @retval None
+  */
+void TIM1_BDTRConfig(TIM1_OSSIState_TypeDef TIM1_OSSIState,
+                     TIM1_LockLevel_TypeDef TIM1_LockLevel,
+                     uint8_t TIM1_DeadTime,
+                     TIM1_BreakState_TypeDef TIM1_Break,
+                     TIM1_BreakPolarity_TypeDef TIM1_BreakPolarity,
+                     TIM1_AutomaticOutput_TypeDef TIM1_AutomaticOutput)
+{
+
+  /* Check the parameters */
+  assert_param(IS_TIM1_OSSI_STATE(TIM1_OSSIState));
+  assert_param(IS_TIM1_LOCK_LEVEL(TIM1_LockLevel));
+  assert_param(IS_TIM1_BREAK_STATE(TIM1_Break));
+  assert_param(IS_TIM1_BREAK_POLARITY(TIM1_BreakPolarity));
+  assert_param(IS_TIM1_AUTOMATIC_OUTPUT_STATE(TIM1_AutomaticOutput));
+
+  TIM1->DTR = (uint8_t)(TIM1_DeadTime);
+  /* Set the Lock level, the Break enable Bit and the Polarity, the OSSI State,
+     the dead time value  and the Automatic Output Enable Bit */
+
+  TIM1->BKR  =  (uint8_t)((uint8_t)((uint8_t)TIM1_OSSIState | (uint8_t)TIM1_LockLevel)
+                          | (uint8_t)((uint8_t)((uint8_t)TIM1_Break | (uint8_t)TIM1_BreakPolarity)
+                                      | (uint8_t)TIM1_AutomaticOutput));
+
+}
+
+/**
+  * @brief  Enables or disables the TIM1 peripheral Main Outputs.
+  * @param  NewState new state of the TIM1 peripheral. 
+  *          This parameter can be ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM1_CtrlPWMOutputs(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Set or Reset the MOE Bit */
+
+  if (NewState != DISABLE)
+  {
+    TIM1->BKR |= TIM1_BKR_MOE;
+  }
+  else
+  {
+    TIM1->BKR &= (uint8_t)(~TIM1_BKR_MOE);
+  }
+}
+
+/**
+  * @brief  Selects the TIM1 Output Compare Mode. This function disables the
+  *         selected channel before changing the Output Compare Mode. 
+  * @note   User has to enable this channel using TIM1_CCxCmd and TIM1_CCxNCmd functions.
+  * @param  TIM1_Channel specifies the TIM1 Channel.
+  *          This parameter can be one of the following values:
+  *            @arg TIM1_Channel_1: TIM1 Channel1
+  *            @arg TIM1_Channel_2: TIM1 Channel2
+  *            @arg TIM1_Channel_3: TIM1 Channel3
+  *            @arg TIM1_Channel_4: TIM1 Channel4
+  * @param  TIM1_OCMode specifies the TIM1 Output Compare Mode.
+  *          This parameter can be one of the following values:
+  *            @arg TIM1_OCMode_Timing: OC Mode Timing
+  *            @arg TIM1_OCMode_Active: OC Mode Active
+  *            @arg TIM1_OCMode_Inactive: OC Mode Inactive
+  *            @arg TIM1_OCMode_Toggle: OC Mode Toggle
+  *            @arg TIM1_OCMode_PWM1: OC Mode PWM1
+  *            @arg TIM1_OCMode_PWM2: OC Mode PWM2  
+  * @retval None
+  */
+void TIM1_SelectOCxM(TIM1_Channel_TypeDef TIM1_Channel, TIM1_OCMode_TypeDef TIM1_OCMode)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM1_CHANNEL(TIM1_Channel));
+  assert_param(IS_TIM1_OCM(TIM1_OCMode));
+
+  if (TIM1_Channel == TIM1_Channel_1)
+  {
+    /* Disable the Channel 1: Reset the CCE Bit */
+    TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC1E);
+
+    /* Reset the Output Compare Bits & Set the Output Compare Mode */
+    TIM1->CCMR1 = (uint8_t)((uint8_t)(TIM1->CCMR1 & (uint8_t)(~TIM1_CCMR_OCM)) | (uint8_t)TIM1_OCMode);
+  }
+  else if (TIM1_Channel == TIM1_Channel_2)
+  {
+    /* Disable the Channel 2: Reset the CCE Bit */
+    TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC2E);
+
+    /* Reset the Output Compare Bits & Set the Output Compare Mode */
+    TIM1->CCMR2 = (uint8_t)((uint8_t)(TIM1->CCMR2 & (uint8_t)(~TIM1_CCMR_OCM)) | (uint8_t)TIM1_OCMode);
+  }
+  else
+  {
+    /* Disable the Channel 3: Reset the CCE Bit */
+    TIM1->CCER2 &= (uint8_t)(~TIM1_CCER2_CC3E);
+
+    /* Reset the Output Compare Bits & Set the Output Compare Mode */
+    TIM1->CCMR3 = (uint8_t)((uint8_t)(TIM1->CCMR3 & (uint8_t)(~TIM1_CCMR_OCM)) | (uint8_t)TIM1_OCMode);
+
+  }
+}
+
+/**
+  * @brief  Sets the TIM1 Capture Compare1 Register value.
+  * @param  Compare1 specifies the Capture Compare1 register new value.
+  *          This parameter is between 0x0000 and 0xFFFF.
+  * @retval None
+  */
+void TIM1_SetCompare1(uint16_t Compare1)
+{
+  /* Set the Capture Compare1 Register value */
+  TIM1->CCR1H = (uint8_t)(Compare1 >> 8);
+  TIM1->CCR1L = (uint8_t)(Compare1);
+
+}
+
+/**
+  * @brief  Sets the TIM1 Capture Compare2 Register value.
+  * @param  Compare2 specifies the Capture Compare2 register new value.
+  *          This parameter is between 0x0000 and 0xFFFF.
+  * @retval None
+  */
+void TIM1_SetCompare2(uint16_t Compare2)
+{
+  /* Set the Capture Compare2 Register value */
+  TIM1->CCR2H = (uint8_t)(Compare2 >> 8);
+  TIM1->CCR2L = (uint8_t)(Compare2);
+}
+
+/**
+  * @brief  Sets the TIM1 Capture Compare3 Register value.
+  * @param  Compare3 specifies the Capture Compare3 register new value.
+  *          This parameter is between 0x0000 and 0xFFFF.
+  * @retval None
+  */
+void TIM1_SetCompare3(uint16_t Compare3)
+{
+  /* Set the Capture Compare3 Register value */
+  TIM1->CCR3H = (uint8_t)(Compare3 >> 8);
+  TIM1->CCR3L = (uint8_t)(Compare3);
+}
+
+/**
+  * @brief  Sets the TIM1 Capture Compare4 Register value.
+  * @param  Compare4 specifies the Capture Compare4 register new value.
+  *          This parameter is between 0x0000 and 0xFFFF.
+  * @retval None
+  */
+void TIM1_SetCompare4(uint16_t Compare4)
+{
+  /* Set the Capture Compare4 Register value */
+  TIM1->CCR4H = (uint8_t)(Compare4 >> 8);
+  TIM1->CCR4L = (uint8_t)(Compare4);
+}
+
+/**
+  * @brief  Sets or Resets the TIM1 peripheral Capture Compare Preload Control bit.
+  * @param  NewState new state of the Capture Compare Preload Control bit.
+  *          This parameter can be ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM1_CCPreloadControl(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Set or Reset the CCPC Bit */
+  if (NewState != DISABLE)
+  {
+    TIM1->CR2 |= TIM1_CR2_CCPC;
+  }
+  else
+  {
+    TIM1->CR2 &= (uint8_t)(~TIM1_CR2_CCPC);
+  }
+}
+
+/**
+  * @brief  Forces the TIM1 Channel1 output waveform to active or inactive level.
+  * @param  TIM1_ForcedAction specifies the forced Action to be set to the output waveform.
+  *          This parameter can be one of the following values:
+  *            @arg TIM1_ForcedAction_Active: Force active level on OC1REF
+  *            @arg TIM1_ForcedAction_Inactive: Force inactive level on OC1REF.
+  * @retval None
+  */
+void TIM1_ForcedOC1Config(TIM1_ForcedAction_TypeDef TIM1_ForcedAction)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM1_FORCED_ACTION(TIM1_ForcedAction));
+
+  /* Reset the OCM Bits & Configure the Forced output Mode */
+  TIM1->CCMR1 =  (uint8_t)((uint8_t)(TIM1->CCMR1 & (uint8_t)(~TIM1_CCMR_OCM)) | (uint8_t)TIM1_ForcedAction);
+}
+
+/**
+  * @brief  Forces the TIM1 Channel2 output waveform to active or inactive level.
+  * @param  TIM1_ForcedAction specifies the forced Action to be set to the output waveform.
+  *          This parameter can be one of the following values:
+  *            @arg TIM1_ForcedAction_Active: Force active level on OC2REF
+  *            @arg TIM1_ForcedAction_Inactive: Force inactive level on OC2REF.
+  * @retval None
+  */
+void TIM1_ForcedOC2Config(TIM1_ForcedAction_TypeDef TIM1_ForcedAction)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM1_FORCED_ACTION(TIM1_ForcedAction));
+
+  /* Reset the OCM Bits & Configure the Forced output Mode */
+  TIM1->CCMR2  =  (uint8_t)((uint8_t)(TIM1->CCMR2 & (uint8_t)(~TIM1_CCMR_OCM)) | (uint8_t)TIM1_ForcedAction);
+}
+
+/**
+  * @brief  Forces the TIM1 Channel3 output waveform to active or inactive level.
+  * @param  TIM1_ForcedAction specifies the forced Action to be set to the output waveform.
+  *          This parameter can be one of the following values:
+  *            @arg TIM1_ForcedAction_Active: Force active level on OC3REF
+  *            @arg TIM1_ForcedAction_Inactive: Force inactive level on OC3REF.
+  * @retval None
+  */
+void TIM1_ForcedOC3Config(TIM1_ForcedAction_TypeDef TIM1_ForcedAction)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM1_FORCED_ACTION(TIM1_ForcedAction));
+
+  /* Reset the OCM Bits */ /* Configure The Forced output Mode */
+  TIM1->CCMR3 = (uint8_t)((uint8_t)(TIM1->CCMR3 & (uint8_t)(~TIM1_CCMR_OCM)) | (uint8_t)TIM1_ForcedAction);
+}
+
+/**
+  * @brief  Enables or disables the TIM1 peripheral Preload Register on CCR1.
+  * @param  NewState new state of the Capture Compare Preload register.
+  *          This parameter can be ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM1_OC1PreloadConfig(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Set or Reset the OC1PE Bit */
+  if (NewState != DISABLE)
+  {
+    TIM1->CCMR1 |= TIM1_CCMR_OCxPE;
+  }
+  else
+  {
+    TIM1->CCMR1 &= (uint8_t)(~TIM1_CCMR_OCxPE);
+  }
+}
+
+/**
+  * @brief  Enables or disables the TIM1 peripheral Preload Register on CCR2.
+  * @param  NewState new state of the Capture Compare Preload register.
+  *          This parameter can be ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM1_OC2PreloadConfig(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Set or Reset the OC2PE Bit */
+  if (NewState != DISABLE)
+  {
+    TIM1->CCMR2 |= TIM1_CCMR_OCxPE;
+  }
+  else
+  {
+    TIM1->CCMR2 &= (uint8_t)(~TIM1_CCMR_OCxPE);
+  }
+}
+
+/**
+  * @brief  Enables or disables the TIM1 peripheral Preload Register on CCR3.
+  * @param  NewState new state of the Capture Compare Preload register.
+  *          This parameter can be ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM1_OC3PreloadConfig(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Set or Reset the OC3PE Bit */
+  if (NewState != DISABLE)
+  {
+    TIM1->CCMR3 |= TIM1_CCMR_OCxPE;
+  }
+  else
+  {
+    TIM1->CCMR3 &= (uint8_t)(~TIM1_CCMR_OCxPE);
+  }
+}
+
+/**
+  * @brief  Enables or disables the TIM1 peripheral Preload Register on CCR4.
+  * @param  NewState new state of the Capture Compare Preload register.
+  *          This parameter can be ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM1_OC4PreloadConfig(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Set or Reset the OC4PE Bit */
+  if (NewState != DISABLE)
+  {
+    TIM1->CCMR4 |= TIM1_CCMR_OCxPE;
+  }
+  else
+  {
+    TIM1->CCMR4 &= (uint8_t)(~TIM1_CCMR_OCxPE);
+  }
+}
+
+/**
+  * @brief  Configures the TIM1 Capture Compare 1 Fast feature.
+  * @param  NewState new state of the Output Compare Fast Enable bit.
+  *          This parameter can be ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM1_OC1FastConfig(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Set or Reset the OC1FE Bit */
+  if (NewState != DISABLE)
+  {
+    TIM1->CCMR1 |= TIM1_CCMR_OCxFE;
+  }
+  else
+  {
+    TIM1->CCMR1 &= (uint8_t)(~TIM1_CCMR_OCxFE);
+  }
+}
+
+/**
+  * @brief  Configures the TIM1 Capture Compare 2 Fast feature.
+  * @param  NewState new state of the Output Compare Fast Enable bit.
+  *          This parameter can be ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM1_OC2FastConfig(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Set or Reset the OC2FE Bit */
+  if (NewState != DISABLE)
+  {
+    TIM1->CCMR2 |= TIM1_CCMR_OCxFE;
+  }
+  else
+  {
+    TIM1->CCMR2 &= (uint8_t)(~TIM1_CCMR_OCxFE);
+  }
+}
+
+/**
+  * @brief  Configures the TIM1 Capture Compare 3 Fast feature.
+  * @param  NewState new state of the Output Compare Fast Enable bit.
+  *          This parameter can be ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM1_OC3FastConfig(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Set or Reset the OC3FE Bit */
+  if (NewState != DISABLE)
+  {
+    TIM1->CCMR3 |= TIM1_CCMR_OCxFE;
+  }
+  else
+  {
+    TIM1->CCMR3 &= (uint8_t)(~TIM1_CCMR_OCxFE);
+  }
+}
+
+/**
+  * @brief   Clears or safeguards the OC1REF signal.
+  * @param  NewState new state of the Output Compare 1 Clear Enable bit.
+  *          This parameter can be ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM1_ClearOC1Ref(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Set or Reset the OC1CE Bit */
+  if (NewState != DISABLE)
+  {
+    TIM1->CCMR1 |= TIM1_CCMR_OCxCE;
+  }
+  else
+  {
+    TIM1->CCMR1 &= (uint8_t)(~TIM1_CCMR_OCxCE);
+  }
+}
+
+/**
+  * @brief  Clears or safeguards the OC2REF signal.
+  * @param  NewState new state of the Output Compare 2 Clear Enable bit.
+  *          This parameter can be ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM1_ClearOC2Ref(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Set or Reset the OC2CE Bit */
+  if (NewState != DISABLE)
+  {
+    TIM1->CCMR2 |= TIM1_CCMR_OCxCE;
+  }
+  else
+  {
+    TIM1->CCMR2 &= (uint8_t)(~TIM1_CCMR_OCxCE);
+  }
+}
+
+/**
+  * @brief  Clears or safeguards the OC3REF signal.
+  * @param  NewState new state of the Output Compare 3 Clear Enable bit.
+  *          This parameter can be ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM1_ClearOC3Ref(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Set or Reset the OC3CE Bit */
+  if (NewState != DISABLE)
+  {
+    TIM1->CCMR3 |= TIM1_CCMR_OCxCE;
+  }
+  else
+  {
+    TIM1->CCMR3 &= (uint8_t)(~TIM1_CCMR_OCxCE);
+  }
+}
+
+/**
+  * @brief  Clears or safeguards the OC4REF signal.
+  * @param  NewState new state of the Output Compare 4 Clear Enable bit.
+  *          This parameter can be ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM1_ClearOC4Ref(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Set or Reset the OC4CE Bit */
+  if (NewState != DISABLE)
+  {
+    TIM1->CCMR4 |= TIM1_CCMR_OCxCE;
+  }
+  else
+  {
+    TIM1->CCMR4 &= (uint8_t)(~TIM1_CCMR_OCxCE);
+  }
+}
+
+/**
+  * @brief  Configures the TIM1 Channel 1 polarity.
+  * @param  TIM1_OCPolarity specifies the OC1 Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM1_OCPolarity_High: Output Compare active low
+  *            @arg TIM1_OCPolarity_Low: Output Compare active high
+  * @retval None
+  */
+void TIM1_OC1PolarityConfig(TIM1_OCPolarity_TypeDef TIM1_OCPolarity)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM1_OC_POLARITY(TIM1_OCPolarity));
+
+  /* Set or Reset the CC1P Bit */
+  if (TIM1_OCPolarity != TIM1_OCPolarity_High)
+  {
+    TIM1->CCER1 |= TIM1_CCER1_CC1P;
+  }
+  else
+  {
+    TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC1P);
+  }
+}
+
+/**
+  * @brief  Configures the TIM1 Channel 1N polarity.
+  * @param  TIM1_OCNPolarity specifies the OC1N Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM1_OCNPolarity_High: Complementary Output Compare active low
+  *            @arg TIM1_OCNPolarity_Low: Complementary Output Compare active high
+  * @retval None
+  */
+void TIM1_OC1NPolarityConfig(TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM1_OCN_POLARITY(TIM1_OCNPolarity));
+
+  /* Set or Reset the CC3P Bit */
+  if (TIM1_OCNPolarity != TIM1_OCNPolarity_High)
+  {
+    TIM1->CCER1 |= TIM1_CCER1_CC1NP;
+  }
+  else
+  {
+    TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC1NP);
+  }
+}
+
+/**
+  * @brief  Configures the TIM1 Channel 2 polarity.
+  * @param  TIM1_OCPolarity specifies the OC2 Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM1_OCPolarity_High: Output Compare active low
+  *            @arg TIM1_OCPolarity_Low: Output Compare active high
+  * @retval None
+  */
+void TIM1_OC2PolarityConfig(TIM1_OCPolarity_TypeDef TIM1_OCPolarity)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM1_OC_POLARITY(TIM1_OCPolarity));
+
+  /* Set or Reset the CC2P Bit */
+  if (TIM1_OCPolarity != TIM1_OCPolarity_High)
+  {
+    TIM1->CCER1 |= TIM1_CCER1_CC2P;
+  }
+  else
+  {
+    TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC2P);
+  }
+}
+
+/**
+  * @brief  Configures the TIM1 Channel 2N polarity.
+  * @param  TIM1_OCNPolarity specifies the OC2N Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM1_OCNPolarity_High: Complementary Output Compare active low
+  *            @arg TIM1_OCNPolarity_Low: Complementary Output Compare active high
+  * @retval None
+  */
+void TIM1_OC2NPolarityConfig(TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM1_OCN_POLARITY(TIM1_OCNPolarity));
+
+  /* Set or Reset the CC3P Bit */
+  if (TIM1_OCNPolarity != TIM1_OCNPolarity_High)
+  {
+    TIM1->CCER1 |= TIM1_CCER1_CC2NP;
+  }
+  else
+  {
+    TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC2NP);
+  }
+}
+
+/**
+  * @brief  Configures the TIM1 Channel 3 polarity.
+  * @param  TIM1_OCPolarity specifies the OC3 Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM1_OCPolarity_High: Output Compare active low
+  *            @arg TIM1_OCPolarity_Low: Output Compare active high
+  * @retval None
+  */
+void TIM1_OC3PolarityConfig(TIM1_OCPolarity_TypeDef TIM1_OCPolarity)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM1_OC_POLARITY(TIM1_OCPolarity));
+
+  /* Set or Reset the CC3P Bit */
+  if (TIM1_OCPolarity != TIM1_OCPolarity_High)
+  {
+    TIM1->CCER2 |= TIM1_CCER2_CC3P;
+  }
+  else
+  {
+    TIM1->CCER2 &= (uint8_t)(~TIM1_CCER2_CC3P);
+  }
+}
+
+/**
+  * @brief  Configures the TIM1 Channel 3N polarity.
+  * @param  TIM1_OCNPolarity specifies the OC3N Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM1_OCNPolarity_High: Complementary Output Compare active low
+  *            @arg TIM1_OCNPolarity_Low: Complementary Output Compare active high
+  * @retval None
+  */
+void TIM1_OC3NPolarityConfig(TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM1_OCN_POLARITY(TIM1_OCNPolarity));
+
+  /* Set or Reset the CC3P Bit */
+  if (TIM1_OCNPolarity != TIM1_OCNPolarity_High)
+  {
+    TIM1->CCER2 |= TIM1_CCER2_CC3NP;
+  }
+  else
+  {
+    TIM1->CCER2 &= (uint8_t)(~TIM1_CCER2_CC3NP);
+  }
+}
+
+/**
+  * @brief  Selects the OCReference Clear source.
+  * @param  TIM1_OCReferenceClear: specifies the OCReference Clear source.
+  *          This parameter can be one of the following values:
+  *            @arg TIM1_OCReferenceClear_ETRF: OCReference Clear source ETR
+  *            @arg TIM1_OCReferenceClear_OCREFCLR: OCReference Clear source OCREF 
+  * @retval None
+  */
+void TIM1_SelectOCREFClear(TIM1_OCReferenceClear_TypeDef TIM1_OCReferenceClear)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM1_OCREFERENCECECLEAR_SOURCE(TIM1_OCReferenceClear));
+
+  /* Set the TIM1_OCReferenceClear source */
+  TIM1->SMCR &=  (uint8_t) (~TIM1_SMCR_OCCS);
+  TIM1->SMCR |=  (uint8_t) TIM1_OCReferenceClear;
+}
+
+/**
+  * @brief  Selects the TIM1 peripheral Commutation event.
+  * @param  NewState new state of the Commutation event.
+  *          This parameter can be ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM1_SelectCOM(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Set or Reset the CCUS Bit */
+  if (NewState != DISABLE)
+  {
+    TIM1->CR2 |= TIM1_CR2_CCUS;
+  }
+  else
+  {
+    TIM1->CR2 &= (uint8_t)(~TIM1_CR2_CCUS);
+  }
+}
+
+/**
+  * @brief  Enables or disables the TIM1 Capture Compare Channel x (x=1,..,4).
+  * @param  TIM1_Channel specifies the TIM1 Channel.
+  *          This parameter can be one of the following values:
+  *            @arg TIM1_Channel_1: TIM1 Channel1
+  *            @arg TIM1_Channel_2: TIM1 Channel2
+  *            @arg TIM1_Channel_3: TIM1 Channel3
+  *            @arg TIM1_CHANNEL_4: TIM1 Channel4
+  * @param  NewState specifies the TIM1 Channel CCxE bit new state.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM1_CCxCmd(TIM1_Channel_TypeDef TIM1_Channel, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM1_CHANNEL(TIM1_Channel));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (TIM1_Channel == TIM1_Channel_1)
+  {
+    /* Set or Reset the CC1E Bit */
+    if (NewState != DISABLE)
+    {
+      TIM1->CCER1 |= TIM1_CCER1_CC1E;
+    }
+    else
+    {
+      TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC1E);
+    }
+  }
+  else if (TIM1_Channel == TIM1_Channel_2)
+  {
+    /* Set or Reset the CC2E Bit */
+    if (NewState != DISABLE)
+    {
+      TIM1->CCER1 |= TIM1_CCER1_CC2E;
+    }
+    else
+    {
+      TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC2E);
+    }
+  }
+  else if (TIM1_Channel == TIM1_Channel_3)
+  {
+    /* Set or Reset the CC3E Bit */
+    if (NewState != DISABLE)
+    {
+      TIM1->CCER2 |= TIM1_CCER2_CC3E;
+    }
+    else
+    {
+      TIM1->CCER2 &= (uint8_t)(~TIM1_CCER2_CC3E);
+    }
+  }
+  else
+  {
+    /* Set or Reset the CC4E Bit */
+    if (NewState != DISABLE)
+    {
+      TIM1->CCER2 |= TIM1_CCER2_CC4E;
+    }
+    else
+    {
+      TIM1->CCER2 &= (uint8_t)(~TIM1_CCER2_CC4E);
+    }
+  }
+}
+
+/**
+  * @brief  Enables or disables the TIM1 Capture Compare Channel xN (xN=1,..,3).
+  * @param  TIM1_Channel specifies the TIM1 Channel.
+  *          This parameter can be one of the following values:
+  *            @arg TIM1_Channel_1: TIM1 Channel1
+  *            @arg TIM1_Channel_2: TIM1 Channel2
+  *            @arg TIM1_Channel_3: TIM1 Channel3
+  * @param  NewState specifies the TIM1 Channel CCxNE bit new state.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM1_CCxNCmd(TIM1_Channel_TypeDef TIM1_Channel, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM1_COMPLEMENTARY_CHANNEL(TIM1_Channel));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (TIM1_Channel == TIM1_Channel_1)
+  {
+    /* Set or Reset the CC1NE Bit */
+    if (NewState != DISABLE)
+    {
+      TIM1->CCER1 |= TIM1_CCER1_CC1NE;
+    }
+    else
+    {
+      TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC1NE);
+    }
+  }
+  else if (TIM1_Channel == TIM1_Channel_2)
+  {
+    /* Set or Reset the CC2NE Bit */
+    if (NewState != DISABLE)
+    {
+      TIM1->CCER1 |= TIM1_CCER1_CC2NE;
+    }
+    else
+    {
+      TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC2NE);
+    }
+  }
+  else
+  {
+    /* Set or Reset the CC3NE Bit */
+    if (NewState != DISABLE)
+    {
+      TIM1->CCER2 |= TIM1_CCER2_CC3NE;
+    }
+    else
+    {
+      TIM1->CCER2 &= (uint8_t)(~TIM1_CCER2_CC3NE);
+    }
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM1_Group3 Input Capture management functions
+ *  @brief    Input Capture management functions 
+ *
+@verbatim   
+ ===============================================================================
+                      Input Capture management functions
+ ===============================================================================  
+   
+       ===================================================================      
+              TIM1 Driver: how to use it in Input Capture Mode
+       =================================================================== 
+       To use the Timer in Input Capture mode, the following steps are mandatory:
+       
+       1. Enable TIM1 clock using CLK_PeripheralClockConfig(CLK_Peripheral_TIM1, ENABLE) function.
+       
+       2. Configure the TIM1 pins in input mode by configuring the corresponding GPIO pins
+       
+       3. Configure the Time base unit as described in the first part of this driver, if needed,
+          otherwise the Timer will run with the default configuration:
+          - Autoreload value = 0xFFFF
+          - Prescaler value = 0x0000
+          - Counter mode = Up counting
+       
+       4. Call TIM1_ICInit() to configure the desired channel to measure only 
+          frequency or duty cycle of the input signal using the corresponding configuration: 
+          - TIM1 Channel: TIM1_Channel
+          - TIM1 Input Capture polarity: TIM1_ICPolarity
+          - TIM1 Input Capture selection: TIM1_ICSelection
+          - TIM1 Input Capture Prescaler: TIM1_ICPSC
+          - TIM1 Input Capture filter value
+          or,
+          Call TIM1_PWMIConfig() to configure the desired channels with the 
+          corresponding configuration and to measure the frequency and the duty
+          cycle of the input signal.
+          
+       5. Enable global interrupts or the DMA to read the measured frequency. 
+          
+       6. Enable the corresponding interrupt (or DMA request) to read the captured value,
+          using the function TIM1_ITConfig(TIM1_IT_CCx) (or TIM1_DMACmd(TIM1_DMASource_CCx))
+       
+       7. Call the TIM1_Cmd(ENABLE) function to enable the TIM1 counter.
+       
+       8. Use TIM1_GetCapturex() to read the captured value corresponding to
+          channel x.
+       
+       Note1: All other functions can be used separately to modify, if needed,
+          a specific feature of the Timer. 
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the TIM1 peripheral according to the specified parameters.
+  * @param  TIM1_Channel specifies the input capture channel
+  *          This parameter can be one of the following values:
+  *            @arg TIM1_Channel_1: TIM1 Channel1
+  *            @arg TIM1_Channel_2: TIM1 Channel2
+  *            @arg TIM1_Channel_3: TIM1 Channel3
+  *            @arg TIM1_Channel_4: TIM1 Channel4
+  * @param  TIM1_ICPolarity specifies the Input capture polarity
+  *          This parameter can be one of the following values:
+  *            @arg TIM1_ICPolarity_Rising: Input capture polarity rising
+  *            @arg TIM1_ICPolarity_Falling: Input capture polarity falling
+  * @param  TIM1_ICSelection specifies the Input capture source selection
+  *          This parameter can be one of the following values:
+  *            @arg TIM1_ICSelection_DirectTI: TIM1 Input x is selected to be connected to ICx.
+  *            @arg TIM1_ICSelection_IndirectTI: TIM1 Input x is selected to be connected to ICy.
+  *            @arg TIM1_ICSelection_TRGI: TIM1 Input x is selected to be connected to the TRGI   
+  * @param  TIM1_ICPrescaler specifies the Input capture Prescaler
+  *          This parameter can be one of the following values:
+  *            @arg TIM1_ICPSC_DIV1: Input Capture Prescaler = 1 (one capture every 1 event)
+  *            @arg TIM1_ICPSC_DIV2: Input Capture Prescaler = 2 (one capture every 2 events)
+  *            @arg TIM1_ICPSC_DIV4: Input Capture Prescaler = 4 (one capture every 4 events)
+  *            @arg TIM1_ICPSC_DIV8: Input Capture Prescaler = 8 (one capture every 8 events)   
+  * @param  TIM1_ICFilter specifies the Input capture filter value.
+  * @note   If the channel 3 is selected the TIM1_ICSelection_IndirectTI parameter is forbidden.
+  * @note   If the channel 4 is selected the TIM1_ICSelection_DirectTI parameter is forbidden.
+  * @retval None
+  */
+
+void TIM1_ICInit(TIM1_Channel_TypeDef TIM1_Channel,
+                 TIM1_ICPolarity_TypeDef TIM1_ICPolarity,
+                 TIM1_ICSelection_TypeDef TIM1_ICSelection,
+                 TIM1_ICPSC_TypeDef TIM1_ICPrescaler,
+                 uint8_t TIM1_ICFilter)
+{
+
+  /* Check the parameters */
+  assert_param(IS_TIM1_CHANNEL(TIM1_Channel));
+  assert_param(IS_TIM1_IC_POLARITY(TIM1_ICPolarity));
+  assert_param(IS_TIM1_IC_SELECTION(TIM1_ICSelection));
+  assert_param(IS_TIM1_IC_PRESCALER(TIM1_ICPrescaler));
+  assert_param(IS_TIM1_IC_FILTER(TIM1_ICFilter));
+
+  if (TIM1_Channel == TIM1_Channel_1)
+  {
+    /* TI1 Configuration */
+    TI1_Config(TIM1_ICPolarity, TIM1_ICSelection, TIM1_ICFilter);
+    /* Set the Input Capture Prescaler value */
+    TIM1_SetIC1Prescaler(TIM1_ICPrescaler);
+  }
+  else if (TIM1_Channel == TIM1_Channel_2)
+  {
+    /* TI2 Configuration */
+    TI2_Config(TIM1_ICPolarity, TIM1_ICSelection, TIM1_ICFilter);
+    /* Set the Input Capture Prescaler value */
+    TIM1_SetIC2Prescaler(TIM1_ICPrescaler);
+  }
+  else if (TIM1_Channel == TIM1_Channel_3)
+  {
+    /* TI3 Configuration */
+    TI3_Config(TIM1_ICPolarity, TIM1_ICSelection, TIM1_ICFilter);
+    /* Set the Input Capture Prescaler value */
+    TIM1_SetIC3Prescaler(TIM1_ICPrescaler);
+  }
+  else
+  {
+    /* TI4 Configuration */
+    TI4_Config(TIM1_ICPolarity, TIM1_ICSelection, TIM1_ICFilter);
+    /* Set the Input Capture Prescaler value */
+    TIM1_SetIC4Prescaler(TIM1_ICPrescaler);
+  }
+}
+
+/**
+  * @brief  Configures the TIM1 peripheral in PWM Input Mode according to the
+  *         specified parameters.
+  * @param  TIM1_Channel specifies the input capture channel
+  *          This parameter can be one of the following values:
+  *            @arg TIM1_Channel_1: TIM1 Channel1
+  *            @arg TIM1_Channel_2: TIM1 Channel2
+  * @param  TIM1_ICPolarity specifies the Input capture polarity
+  *          This parameter can be one of the following values:
+  *            @arg TIM1_ICPolarity_Rising: Input capture polarity rising
+  *            @arg TIM1_ICPolarity_Falling: Input capture polarity falling
+  * @param  TIM1_ICSelection specifies the Input capture source selection 
+  *          This parameter can be one of the following values:
+  *            @arg TIM1_ICSelection_DirectTI: TIM1 Input x is selected to be connected to ICx.
+  *            @arg TIM1_ICSelection_IndirectTI: TIM1 Input x is selected to be connected to ICy.
+  *            @arg TIM1_ICSelection_TRGI: TIM1 Input x is selected to be connected to the TRGI     
+  * @param  TIM1_ICPrescaler specifies the Input capture Prescaler
+  *          This parameter can be one of the following values:
+  *            @arg TIM1_ICPSC_DIV1: Input Capture Prescaler = 1 (one capture every 1 event)
+  *            @arg TIM1_ICPSC_DIV2: Input Capture Prescaler = 2 (one capture every 2 events)
+  *            @arg TIM1_ICPSC_DIV4: Input Capture Prescaler = 4 (one capture every 4 events)
+  *            @arg TIM1_ICPSC_DIV8: Input Capture Prescaler = 8 (one capture every 8 events)   
+  * @param  TIM1_ICFilter specifies the Input capture filter value.
+  * @retval None
+  */
+void TIM1_PWMIConfig(TIM1_Channel_TypeDef TIM1_Channel,
+                     TIM1_ICPolarity_TypeDef TIM1_ICPolarity,
+                     TIM1_ICSelection_TypeDef TIM1_ICSelection,
+                     TIM1_ICPSC_TypeDef TIM1_ICPrescaler,
+                     uint8_t TIM1_ICFilter)
+{
+  TIM1_ICPolarity_TypeDef icpolarity = TIM1_ICPolarity_Rising;
+  TIM1_ICSelection_TypeDef icselection = TIM1_ICSelection_DirectTI;
+
+  /* Check the parameters */
+  assert_param(IS_TIM1_PWMI_CHANNEL(TIM1_Channel));
+  assert_param(IS_TIM1_IC_POLARITY(TIM1_ICPolarity));
+  assert_param(IS_TIM1_IC_SELECTION(TIM1_ICSelection));
+  assert_param(IS_TIM1_IC_PRESCALER(TIM1_ICPrescaler));
+
+  /* Select the Opposite Input Polarity */
+  if (TIM1_ICPolarity != TIM1_ICPolarity_Falling)
+  {
+    icpolarity = TIM1_ICPolarity_Falling;
+  }
+  else
+  {
+    icpolarity = TIM1_ICPolarity_Rising;
+  }
+
+  /* Select the Opposite Input */
+  if (TIM1_ICSelection == TIM1_ICSelection_DirectTI)
+  {
+    icselection = TIM1_ICSelection_IndirectTI;
+  }
+  else
+  {
+    icselection = TIM1_ICSelection_DirectTI;
+  }
+
+  if (TIM1_Channel == TIM1_Channel_1)
+  {
+    /* TI1 Configuration */
+    TI1_Config(TIM1_ICPolarity, TIM1_ICSelection, TIM1_ICFilter);
+
+    /* Set the Input Capture Prescaler value */
+    TIM1_SetIC1Prescaler(TIM1_ICPrescaler);
+
+    /* TI2 Configuration */
+    TI2_Config(icpolarity, icselection, TIM1_ICFilter);
+
+    /* Set the Input Capture Prescaler value */
+    TIM1_SetIC2Prescaler(TIM1_ICPrescaler);
+  }
+  else
+  {
+    /* TI2 Configuration */
+    TI2_Config(TIM1_ICPolarity, TIM1_ICSelection, TIM1_ICFilter);
+
+    /* Set the Input Capture Prescaler value */
+    TIM1_SetIC2Prescaler(TIM1_ICPrescaler);
+
+    /* TI1 Configuration */
+    TI1_Config(icpolarity, icselection, TIM1_ICFilter);
+
+    /* Set the Input Capture Prescaler value */
+    TIM1_SetIC1Prescaler(TIM1_ICPrescaler);
+  }
+}
+
+/**
+  * @brief  Gets the TIM1 Input Capture 1 value.
+  * @param  None
+  * @retval Capture Compare 1 Register value.
+  */
+uint16_t TIM1_GetCapture1(void)
+{
+  /* Get the Capture 1 Register value */
+
+  uint16_t tmpccr1 = 0;
+  uint8_t tmpccr1l = 0, tmpccr1h = 0;
+
+  tmpccr1h = TIM1->CCR1H;
+  tmpccr1l = TIM1->CCR1L;
+
+  tmpccr1 = (uint16_t)(tmpccr1l);
+  tmpccr1 |= (uint16_t)((uint16_t)tmpccr1h << 8);
+  /* Get the Capture 1 Register value */
+  return (uint16_t)tmpccr1;
+}
+
+/**
+  * @brief  Gets the TIM1 Input Capture 2 value.
+  * @param  None
+  * @retval Capture Compare 2 Register value.
+  */
+uint16_t TIM1_GetCapture2(void)
+{
+  /* Get the Capture 2 Register value */
+
+  uint16_t tmpccr2 = 0;
+  uint8_t tmpccr2l = 0, tmpccr2h = 0;
+
+  tmpccr2h = TIM1->CCR2H;
+  tmpccr2l = TIM1->CCR2L;
+
+  tmpccr2 = (uint16_t)(tmpccr2l);
+  tmpccr2 |= (uint16_t)((uint16_t)tmpccr2h << 8);
+  /* Get the Capture 2 Register value */
+  return (uint16_t)tmpccr2;
+}
+
+/**
+  * @brief  Gets the TIM1 Input Capture 3 value.
+  * @param  None
+  * @retval Capture Compare 3 Register value.
+  */
+uint16_t TIM1_GetCapture3(void)
+{
+  /* Get the Capture 3 Register value */
+  uint16_t tmpccr3 = 0;
+  uint8_t tmpccr3l = 0, tmpccr3h = 0;
+
+  tmpccr3h = TIM1->CCR3H;
+  tmpccr3l = TIM1->CCR3L;
+
+  tmpccr3 = (uint16_t)(tmpccr3l);
+  tmpccr3 |= (uint16_t)((uint16_t)tmpccr3h << 8);
+  /* Get the Capture 3 Register value */
+  return (uint16_t)tmpccr3;
+}
+
+/**
+  * @brief  Gets the TIM1 Input Capture 4 value.
+  * @param  None
+  * @retval Capture Compare 4 Register value.
+  */
+uint16_t TIM1_GetCapture4(void)
+{
+  /* Get the Capture 4 Register value */
+  uint16_t tmpccr4 = 0;
+  uint8_t tmpccr4l = 0, tmpccr4h = 0;
+
+  tmpccr4h = TIM1->CCR4H;
+  tmpccr4l = TIM1->CCR4L;
+
+  tmpccr4 = (uint16_t)(tmpccr4l);
+  tmpccr4 |= (uint16_t)((uint16_t)tmpccr4h << 8);
+  /* Get the Capture 4 Register value */
+  return (uint16_t)tmpccr4;
+}
+
+/**
+  * @brief  Sets the TIM1 Input Capture 1 prescaler.
+  * @param  TIM1_IC1Prescaler specifies the Input Capture prescaler new value
+  *          This parameter can be one of the following values:
+  *            @arg TIM1_ICPSC_DIV1: Input Capture Prescaler = 1 (one capture every 1 event)
+  *            @arg TIM1_ICPSC_DIV2: Input Capture Prescaler = 2 (one capture every 2 events)
+  *            @arg TIM1_ICPSC_DIV4: Input Capture Prescaler = 4 (one capture every 4 events)
+  *            @arg TIM1_ICPSC_DIV8: Input Capture Prescaler = 8 (one capture every 8 events)   
+  * @retval None
+  */
+void TIM1_SetIC1Prescaler(TIM1_ICPSC_TypeDef TIM1_IC1Prescaler)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM1_IC_PRESCALER(TIM1_IC1Prescaler));
+
+  /* Reset the IC1PSC Bits */ /* Set the IC1PSC value */
+  TIM1->CCMR1 = (uint8_t)((uint8_t)(TIM1->CCMR1 & (uint8_t)(~TIM1_CCMR_ICxPSC)) | (uint8_t)TIM1_IC1Prescaler);
+}
+
+/**
+  * @brief  Sets the TIM1 Input Capture 2 prescaler.
+  * @param  TIM1_IC2Prescaler specifies the Input Capture prescaler new value
+  *          This parameter can be one of the following values:
+  *            @arg TIM1_ICPSC_DIV1: Input Capture Prescaler = 1 (one capture every 1 event)
+  *            @arg TIM1_ICPSC_DIV2: Input Capture Prescaler = 2 (one capture every 2 events)
+  *            @arg TIM1_ICPSC_DIV4: Input Capture Prescaler = 4 (one capture every 4 events)
+  *            @arg TIM1_ICPSC_DIV8: Input Capture Prescaler = 8 (one capture every 8 events)   
+  * @retval None
+  */
+void TIM1_SetIC2Prescaler(TIM1_ICPSC_TypeDef TIM1_IC2Prescaler)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM1_IC_PRESCALER(TIM1_IC2Prescaler));
+
+  /* Reset the IC1PSC Bits */ /* Set the IC1PSC value */
+  TIM1->CCMR2 = (uint8_t)((uint8_t)(TIM1->CCMR2 & (uint8_t)(~TIM1_CCMR_ICxPSC)) | (uint8_t)TIM1_IC2Prescaler);
+}
+
+/**
+  * @brief  Sets the TIM1 Input Capture 3 prescaler.
+  * @param  TIM1_IC3Prescaler specifies the Input Capture prescaler new value
+  *          This parameter can be one of the following values:
+  *            @arg TIM1_ICPSC_DIV1: Input Capture Prescaler = 1 (one capture every 1 event)
+  *            @arg TIM1_ICPSC_DIV2: Input Capture Prescaler = 2 (one capture every 2 events)
+  *            @arg TIM1_ICPSC_DIV4: Input Capture Prescaler = 4 (one capture every 4 events)
+  *            @arg TIM1_ICPSC_DIV8: Input Capture Prescaler = 8 (one capture every 8 events)   
+  * @retval None
+  */
+void TIM1_SetIC3Prescaler(TIM1_ICPSC_TypeDef TIM1_IC3Prescaler)
+{
+
+  /* Check the parameters */
+  assert_param(IS_TIM1_IC_PRESCALER(TIM1_IC3Prescaler));
+
+  /* Reset the IC1PSC Bits & Set the IC1PSC value */
+  TIM1->CCMR3 = (uint8_t)((uint8_t)(TIM1->CCMR3 & (uint8_t)(~TIM1_CCMR_ICxPSC)) | (uint8_t)TIM1_IC3Prescaler);
+}
+
+/**
+  * @brief  Sets the TIM1 Input Capture 4 prescaler.
+  * @param  TIM1_IC4Prescaler specifies the Input Capture prescaler new value
+  *          This parameter can be one of the following values:
+  *            @arg TIM1_ICPSC_DIV1: Input Capture Prescaler = 1 (one capture every 1 event)
+  *            @arg TIM1_ICPSC_DIV2: Input Capture Prescaler = 2 (one capture every 2 events)
+  *            @arg TIM1_ICPSC_DIV4: Input Capture Prescaler = 4 (one capture every 4 events)
+  *            @arg TIM1_ICPSC_DIV8: Input Capture Prescaler = 8 (one capture every 8 events)   
+  * @retval None
+  */
+void TIM1_SetIC4Prescaler(TIM1_ICPSC_TypeDef TIM1_IC4Prescaler)
+{
+
+  /* Check the parameters */
+  assert_param(IS_TIM1_IC_PRESCALER(TIM1_IC4Prescaler));
+
+  /* Reset the IC1PSC Bits &  Set the IC1PSC value */
+  TIM1->CCMR4 = (uint8_t)((uint8_t)(TIM1->CCMR4 & (uint8_t)(~TIM1_CCMR_ICxPSC)) | (uint8_t)TIM1_IC4Prescaler);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM1_Group4 Interrupts DMA and flags management functions
+ *  @brief    Interrupts, DMA and flags management functions 
+ *
+@verbatim   
+ ===============================================================================
+                 Interrupts, DMA and flags management functions
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the specified TIM1 interrupts.
+  * @param  NewState new state of the TIM1 peripheral.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @param  TIM1_IT specifies the TIM1 interrupts sources to be enabled or disabled.
+  *          This parameter can be any combination of the following values:
+  *            @arg TIM1_IT_Update: Update
+  *            @arg TIM1_IT_CC1: Capture Compare Channel1
+  *            @arg TIM1_IT_CC2: Capture Compare Channel2 
+  *            @arg TIM1_IT_CC3: Capture Compare Channel3
+  *            @arg TIM1_IT_CC4: Capture Compare Channel4 
+  *            @arg TIM1_IT_COM: Commutation
+  *            @arg TIM1_IT_Trigger: Trigger 
+  *            @arg TIM1_IT_Break: Break  
+  * @param  NewState new state of the TIM1 peripheral.
+  * @retval None
+  */
+void TIM1_ITConfig(TIM1_IT_TypeDef  TIM1_IT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM1_IT(TIM1_IT));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the Interrupt sources */
+    TIM1->IER |= (uint8_t)TIM1_IT;
+  }
+  else
+  {
+    /* Disable the Interrupt sources */
+    TIM1->IER &= (uint8_t)(~(uint8_t)TIM1_IT);
+  }
+}
+
+/**
+  * @brief  Configures the TIM1 event to be generated by software.
+  * @param  TIM1_EventSource specifies the event source.
+  *          This parameter can be any combination of the following values:
+  *            @arg TIM1_EventSource_Update: Update
+  *            @arg TIM1_EventSource_CC1: Capture Compare Channel1
+  *            @arg TIM1_EventSource_CC2: Capture Compare Channel2 
+  *            @arg TIM1_EventSource_CC3: Capture Compare Channel3
+  *            @arg TIM1_EventSource_CC4: Capture Compare Channel4 
+  *            @arg TIM1_EventSource_COM: Commutation
+  *            @arg TIM1_EventSource_Trigger: Trigger 
+  *            @arg TIM1_EventSource_Break: Break  
+  * @retval None
+  */
+void TIM1_GenerateEvent(TIM1_EventSource_TypeDef TIM1_EventSource)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM1_EVENT_SOURCE(TIM1_EventSource));
+
+  /* Set the event sources */
+  TIM1->EGR = (uint8_t)TIM1_EventSource;
+}
+/**
+  * @brief  Checks whether the specified TIM1 flag is set or not.
+  * @param  TIM1_FLAG specifies the flag to check.
+  *          This parameter can be one of the following values:
+  *            @arg TIM1_FLAG_Update: TIM1 update Flag
+  *            @arg TIM1_FLAG_CC1: TIM1 Capture Compare 1 Flag
+  *            @arg TIM1_FLAG_CC2: TIM1 Capture Compare 2 Flag
+  *            @arg TIM1_FLAG_CC3: TIM1 Capture Compare 3 Flag
+  *            @arg TIM1_FLAG_CC4: TIM1 Capture Compare 4 Flag
+  *            @arg TIM1_FLAG_COM: TIM1 Commutation Flag
+  *            @arg TIM1_FLAG_Trigger: TIM1 Trigger Flag
+  *            @arg TIM1_FLAG_Break: TIM1 Break Flag
+  *            @arg TIM1_FLAG_CC1OF: TIM1 Capture Compare 1 overcapture Flag
+  *            @arg TIM1_FLAG_CC2OF: TIM1 Capture Compare 2 overcapture Flag
+  *            @arg TIM1_FLAG_CC3OF: TIM1 Capture Compare 3 overcapture Flag
+  *            @arg TIM1_FLAG_CC4OF: TIM1 Capture Compare 4 overcapture Flag
+  * @retval FlagStatus The new state of TIM1_FLAG (SET or RESET).
+  */
+FlagStatus TIM1_GetFlagStatus(TIM1_FLAG_TypeDef TIM1_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  uint8_t tim1_flag_l = 0, tim1_flag_h = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM1_GET_FLAG(TIM1_FLAG));
+
+  tim1_flag_l = (uint8_t)(TIM1->SR1 & (uint8_t)TIM1_FLAG);
+  tim1_flag_h = (uint8_t)(TIM1->SR2 & (uint8_t)((uint16_t)TIM1_FLAG >> 8));
+
+  if ((uint8_t)((uint8_t)tim1_flag_l | (uint8_t)tim1_flag_h) != 0)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return (FlagStatus)(bitstatus);
+}
+
+/**
+  * @brief  Clears the TIM1’s pending flags.
+  * @param  TIM1_FLAG specifies the flag to clear.
+  *          This parameter can be one of the following values:
+  *            @arg TIM1_FLAG_Update: TIM1 update Flag
+  *            @arg TIM1_FLAG_CC1: TIM1 Capture Compare 1 Flag
+  *            @arg TIM1_FLAG_CC2: TIM1 Capture Compare 2 Flag
+  *            @arg TIM1_FLAG_CC3: TIM1 Capture Compare 3 Flag
+  *            @arg TIM1_FLAG_CC4: TIM1 Capture Compare 4 Flag
+  *            @arg TIM1_FLAG_COM: TIM1 Commutation Flag
+  *            @arg TIM1_FLAG_Trigger: TIM1 Trigger Flag
+  *            @arg TIM1_FLAG_Break: TIM1 Break Flag
+  *            @arg TIM1_FLAG_CC1OF: TIM1 Capture Compare 1 overcapture Flag
+  *            @arg TIM1_FLAG_CC2OF: TIM1 Capture Compare 2 overcapture Flag
+  *            @arg TIM1_FLAG_CC3OF: TIM1 Capture Compare 3 overcapture Flag
+  *            @arg TIM1_FLAG_CC4OF: TIM1 Capture Compare 4 overcapture Flag
+  * @retval None.
+  */
+void TIM1_ClearFlag(TIM1_FLAG_TypeDef TIM1_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM1_CLEAR_FLAG(TIM1_FLAG));
+
+  /* Clear the flags (rc_w0) clear this bit by writing 0. Writing ‘1’ has no effect*/
+  TIM1->SR1 = (uint8_t)(~(uint8_t)(TIM1_FLAG));
+  TIM1->SR2 = (uint8_t)((uint8_t)(~((uint8_t)((uint16_t)TIM1_FLAG >> 8))) & (uint8_t)0x1E);
+}
+
+/**
+  * @brief  Checks whether the TIM1 interrupt has occurred or not.
+  * @param  TIM1_IT specifies the TIM1 interrupt source to check.
+  *          This parameter can be any combination of the following values:
+  *            @arg TIM1_IT_Update: Update
+  *            @arg TIM1_IT_CC1: Capture Compare Channel1
+  *            @arg TIM1_IT_CC2: Capture Compare Channel2 
+  *            @arg TIM1_IT_CC3: Capture Compare Channel3
+  *            @arg TIM1_IT_CC4: Capture Compare Channel4 
+  *            @arg TIM1_IT_COM: Commutation
+  *            @arg TIM1_IT_Trigger: Trigger 
+  *            @arg TIM1_IT_Break: Break  
+  * @retval ITStatus The new state of the TIM1_IT(SET or RESET).
+  */
+
+ITStatus TIM1_GetITStatus(TIM1_IT_TypeDef TIM1_IT)
+{
+  ITStatus bitstatus = RESET;
+
+  uint8_t TIM1_itStatus = 0x0, TIM1_itEnable = 0x0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM1_GET_IT(TIM1_IT));
+
+  TIM1_itStatus = (uint8_t)(TIM1->SR1 & (uint8_t)TIM1_IT);
+
+  TIM1_itEnable = (uint8_t)(TIM1->IER & (uint8_t)TIM1_IT);
+
+  if ((TIM1_itStatus != (uint8_t)RESET ) && (TIM1_itEnable != (uint8_t)RESET ))
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return (ITStatus)(bitstatus);
+}
+
+/**
+  * @brief  Clears the TIM1's interrupt pending bits.
+  * @param  TIM1_IT specifies the pending bit to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg TIM1_IT_Update: Update
+  *            @arg TIM1_IT_CC1: Capture Compare Channel1
+  *            @arg TIM1_IT_CC2: Capture Compare Channel2 
+  *            @arg TIM1_IT_CC3: Capture Compare Channel3
+  *            @arg TIM1_IT_CC4: Capture Compare Channel4 
+  *            @arg TIM1_IT_COM: Commutation
+  *            @arg TIM1_IT_Trigger: Trigger 
+  *            @arg TIM1_IT_Break: Break  
+  * @retval None.
+  */
+void TIM1_ClearITPendingBit(TIM1_IT_TypeDef TIM1_IT)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM1_IT(TIM1_IT));
+
+  /* Clear the IT pending Bit */
+  TIM1->SR1 = (uint8_t)(~(uint8_t)TIM1_IT);
+}
+
+/**
+  * @brief  Configures the TIM1’s DMA interface.
+  * @param  TIM1_DMABase: DMA Base address.
+  * @param  TIM1_DMABurstLength: DMA Burst length.
+  * @retval None.
+  */
+void TIM1_DMAConfig(TIM1_DMABase_TypeDef TIM1_DMABase,
+                    TIM1_DMABurstLength_TypeDef TIM1_DMABurstLength)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM1_DMABase(TIM1_DMABase));
+  assert_param(IS_TIM1_DMABurstLength(TIM1_DMABurstLength));
+
+  /* Set the DMA Base and the DMA Burst Length */
+  TIM1->DCR1 = (uint8_t)TIM1_DMABase;
+  TIM1->DCR2 = (uint8_t)TIM1_DMABurstLength;
+}
+
+/**
+  * @brief  Enables or disables the TIM’s DMA Requests.
+  * @param  TIM1_DMASources: specifies the DMA Request sources.
+  *          This parameter can be any combination of the following values:
+  *            @arg TIM1_DMA_Update: TIM1 update Interrupt source
+  *            @arg DMA_Trigger: TIM1 Trigger DMA source
+  * @param  NewState  new state of the DMA Request sources.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None.
+  */
+void TIM1_DMACmd(TIM1_DMASource_TypeDef TIM1_DMASource, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  assert_param(IS_TIM1_DMA_SOURCE(TIM1_DMASource));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the DMA sources */
+    TIM1->DER |= (uint8_t)TIM1_DMASource;
+  }
+  else
+  {
+    /* Disable the DMA sources */
+    TIM1->DER &= (uint8_t)(~TIM1_DMASource);
+  }
+}
+
+/**
+  * @brief  Selects the TIM1 peripheral Capture Compare DMA source.
+  * @param   NewState: new state of the Capture Compare DMA source.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM1_SelectCCDMA(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Set the CCDS Bit */
+    TIM1->CR2 |= TIM1_CR2_CCDS;
+  }
+  else
+  {
+    /* Reset the CCDS Bit */
+    TIM1->CR2 &= (uint8_t)(~TIM1_CR2_CCDS);
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM1_Group5 Clocks management functions
+ *  @brief    Clocks management functions
+ *
+@verbatim   
+ ===============================================================================
+                         Clocks management functions
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures the TIM1 internal Clock.
+  * @param  None
+  * @retval None
+  */
+void TIM1_InternalClockConfig(void)
+{
+  /* Disable slave mode to clock the prescaler directly with the internal clock */
+  TIM1->SMCR &= (uint8_t)(~TIM1_SMCR_SMS);
+}
+
+/**
+  * @brief  Configures the TIM1 Trigger as External Clock.
+  * @param  TIM1_TIxExternalCLKSource specifies Trigger source.
+  *          This parameter can be one of the following values:
+  *            @arg TIM1_TIxExternalCLK1Source_TI1: TI1 Edge Detector
+  *            @arg TIM1_TIxExternalCLK1Source_TI2: Filtered TIM1 Input 1
+  *            @arg TIM1_TIxExternalCLK1Source_TI1ED: Filtered TIM1 Input 2
+  * @param  TIM1_ICPolarity specifies the TIx Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM1_ICPolarity_Rising: Input capture polarity rising
+  *            @arg TIM1_ICPolarity_Falling: Input capture polarity falling
+  * @param  ICFilter specifies the filter value.
+  *          This parameter must be a value between 0x00 and 0x0F
+  * @retval None
+  */
+void TIM1_TIxExternalClockConfig(TIM1_TIxExternalCLK1Source_TypeDef TIM1_TIxExternalCLKSource,
+                                 TIM1_ICPolarity_TypeDef TIM1_ICPolarity,
+                                 uint8_t ICFilter)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM1_TIXCLK_SOURCE(TIM1_TIxExternalCLKSource));
+  assert_param(IS_TIM1_IC_POLARITY(TIM1_ICPolarity));
+  assert_param(IS_TIM1_IC_FILTER(ICFilter));
+
+  /* Configure the TIM1 Input Clock Source */
+  if (TIM1_TIxExternalCLKSource == TIM1_TIxExternalCLK1Source_TI2)
+  {
+    TI2_Config(TIM1_ICPolarity, TIM1_ICSelection_DirectTI, ICFilter);
+  }
+  else
+  {
+    TI1_Config(TIM1_ICPolarity, TIM1_ICSelection_DirectTI, ICFilter);
+  }
+
+  /* Select the Trigger source */
+  TIM1_SelectInputTrigger((TIM1_TRGSelection_TypeDef)TIM1_TIxExternalCLKSource);
+
+  /* Select the External clock mode1 */
+  TIM1->SMCR |= (uint8_t)(TIM1_SlaveMode_External1);
+}
+
+/**
+  * @brief  Configures the TIM1 External clock Mode1.
+  * @param  TIM1_ExtTRGPrescaler specifies the external Trigger Prescaler.
+  *          This parameter can be one of the following values:
+  *            @arg TIM1_ExtTRGPSC_OFF
+  *            @arg TIM1_ExtTRGPSC_DIV2
+  *            @arg TIM1_ExtTRGPSC_DIV4
+  *            @arg TIM1_ExtTRGPSC_DIV8.
+  * @param  TIM1_ExtTRGPolarity specifies the external Trigger Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM1_ExtTRGPolarity_Inverted
+  *            @arg TIM1_ExtTRGPolarity_NonInverted
+  * @param  ExtTRGFilter specifies the External Trigger Filter.
+  *          This parameter must be a value between 0x00 and 0x0F
+  * @retval None
+  */
+void TIM1_ETRClockMode1Config(TIM1_ExtTRGPSC_TypeDef TIM1_ExtTRGPrescaler,
+                              TIM1_ExtTRGPolarity_TypeDef TIM1_ExtTRGPolarity,
+                              uint8_t ExtTRGFilter)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM1_EXT_PRESCALER(TIM1_ExtTRGPrescaler));
+  assert_param(IS_TIM1_EXT_POLARITY(TIM1_ExtTRGPolarity));
+  assert_param(IS_TIM1_EXT_TRG_FILTER(ExtTRGFilter));
+
+  /* Configure the ETR Clock source */
+  TIM1_ETRConfig(TIM1_ExtTRGPrescaler, TIM1_ExtTRGPolarity, ExtTRGFilter);
+
+  /* Select the External clock mode1 & Select the Trigger selection : ETRF */
+  TIM1->SMCR = (uint8_t)((uint8_t)(TIM1->SMCR & (uint8_t)(~(TIM1_SMCR_SMS | TIM1_SMCR_TS)))
+                         | (uint8_t)((uint8_t)TIM1_SlaveMode_External1 | (uint8_t) TIM1_TRGSelection_ETRF));
+}
+
+/**
+  * @brief  Configures the TIM1 External clock Mode2.
+  * @param  TIM1_ExtTRGPrescaler specifies the external Trigger Prescaler.
+  *          This parameter can be one of the following values:
+  *            @arg TIM1_ExtTRGPSC_OFF
+  *            @arg TIM1_ExtTRGPSC_DIV2
+  *            @arg TIM1_ExtTRGPSC_DIV4
+  *            @arg TIM1_ExtTRGPSC_DIV8.
+  * @param  TIM1_ExtTRGPolarity specifies the external Trigger Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM1_ExtTRGPolarity_Inverted
+  *            @arg TIM1_ExtTRGPolarity_NonInverted
+  * @param  ExtTRGFilter specifies the External Trigger Filter.
+  *          This parameter must be a value between 0x00 and 0x0F
+  * @retval None
+  */
+void TIM1_ETRClockMode2Config(TIM1_ExtTRGPSC_TypeDef TIM1_ExtTRGPrescaler,
+                              TIM1_ExtTRGPolarity_TypeDef TIM1_ExtTRGPolarity,
+                              uint8_t ExtTRGFilter)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM1_EXT_PRESCALER(TIM1_ExtTRGPrescaler));
+  assert_param(IS_TIM1_EXT_POLARITY(TIM1_ExtTRGPolarity));
+
+  /* Configure the ETR Clock source */
+  TIM1_ETRConfig(TIM1_ExtTRGPrescaler, TIM1_ExtTRGPolarity, ExtTRGFilter);
+
+  /* Enable the External clock mode2 */
+  TIM1->ETR |= TIM1_ETR_ECE;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM1_Group6 Synchronization management functions
+ *  @brief    Synchronization management functions 
+ *
+@verbatim   
+ ===============================================================================
+                       Synchronization management functions
+ ===============================================================================  
+                   
+       ===================================================================      
+              TIM1 Driver: how to use it in synchronization Mode
+       =================================================================== 
+       Case of two/several Timers
+       **************************
+       1. If TIM1 is used as master to other timers use the following functions:
+          - TIM1_SelectOutputTrigger()
+          - TIM1_SelectMasterSlaveMode()
+       2. If TIM1 is used as slave to other timers use the following functions:
+          - TIM1_SelectInputTrigger()
+          - TIM1_SelectSlaveMode()
+          
+       Case of Timers and external trigger (TRIG pin)
+       ********************************************       
+       1. Configure the External trigger using TIM1_ETRConfig()
+       2. Configure the Slave Timer using the following functions:
+          - TIM1_SelectInputTrigger()
+          - TIM1_SelectSlaveMode()
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Selects the TIM1 Input Trigger source.
+  * @param  TIM1_InputTriggerSource specifies Input Trigger source.
+  *          This parameter can be one of the following values:
+  *            @arg TIM1_TRGSelection_TIM4
+  *            @arg TIM1_TRGSelection_TIM3
+  *            @arg TIM1_TRGSelection_TIM2
+  *            @arg TIM1_TRGSelection_TI1F_ED: TI1 Edge Detector
+  *            @arg TIM1_TRGSelection_TI1FP1: Filtered Timer Input 1
+  *            @arg TIM1_TRGSelection_TI2FP2: Filtered Timer Input 2
+  *            @arg TIM1_TRGSelection_ETRF: External Trigger input
+  * @retval None
+  */
+void TIM1_SelectInputTrigger(TIM1_TRGSelection_TypeDef TIM1_InputTriggerSource)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM1_TRIGGER_SELECTION(TIM1_InputTriggerSource));
+
+  /* Select the Tgigger Source */
+  TIM1->SMCR = (uint8_t)((uint8_t)(TIM1->SMCR & (uint8_t)(~TIM1_SMCR_TS)) | (uint8_t)TIM1_InputTriggerSource);
+}
+
+/**
+  * @brief  Selects the TIM1 Trigger Output Mode.
+  * @param  TIM1_TRGOSource specifies the Trigger Output source.
+  *          This parameter can be one of the following values
+  *            @arg TIM1_TRGOSource_Reset
+  *            @arg TIM1_TRGOSource_Enable
+  *            @arg TIM1_TRGOSource_Update
+  *            @arg TIM1_TRGOSource_OC1
+  *            @arg TIM1_TRGOSource_OC1REF
+  *            @arg TIM1_TRGOSource_OC2REF
+  *            @arg TIM1_TRGOSource_OC3REF
+  *            @arg TIM1_TRGOSource_OC4REF
+  * @retval None
+  */
+void TIM1_SelectOutputTrigger(TIM1_TRGOSource_TypeDef TIM1_TRGOSource)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM1_TRGO_SOURCE(TIM1_TRGOSource));
+  /* Reset the MMS Bits & Select the TRGO source */
+  TIM1->CR2 = (uint8_t)((uint8_t)(TIM1->CR2 & (uint8_t)(~TIM1_CR2_MMS)) | (uint8_t) TIM1_TRGOSource);
+}
+
+/**
+  * @brief  Selects the TIM1 Slave Mode.
+  * @param  TIM1_SlaveMode specifies the TIM1 Slave Mode.
+  *          This parameter can be one of the following values
+  *            @arg TIM1_SlaveMode_Reset
+  *            @arg TIM1_SlaveMode_Gated
+  *            @arg TIM1_SlaveMode_Trigger
+  *            @arg TIM1_SlaveMode_External1
+  * @retval None
+  */
+void TIM1_SelectSlaveMode(TIM1_SlaveMode_TypeDef TIM1_SlaveMode)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM1_SLAVE_MODE(TIM1_SlaveMode));
+
+  /* Reset the SMS Bits and Select the Slave Mode */
+  TIM1->SMCR = (uint8_t)((uint8_t)(TIM1->SMCR & (uint8_t)(~TIM1_SMCR_SMS)) | (uint8_t)TIM1_SlaveMode);
+
+}
+
+/**
+  * @brief  Sets or Resets the TIM1 Master/Slave Mode.
+  * @param  NewState new state of the synchronization between TIM1 and its slaves
+  *         (through TRGO). This parameter can be ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM1_SelectMasterSlaveMode(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Set or Reset the MSM Bit */
+  if (NewState != DISABLE)
+  {
+    TIM1->SMCR |= TIM1_SMCR_MSM;
+  }
+  else
+  {
+    TIM1->SMCR &= (uint8_t)(~TIM1_SMCR_MSM);
+  }
+}
+
+/**
+  * @brief  Configures the TIM1 External Trigger.
+  * @param  TIM1_ExtTRGPrescaler specifies the external Trigger Prescaler.
+  *          This parameter can be one of the following values:
+  *            @arg TIM1_ExtTRGPSC_OFF
+  *            @arg TIM1_ExtTRGPSC_DIV2
+  *            @arg TIM1_ExtTRGPSC_DIV4
+  *            @arg TIM1_ExtTRGPSC_DIV8.
+  * @param  TIM1_ExtTRGPolarity specifies the external Trigger Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM1_ExtTRGPolarity_Inverted
+  *            @arg TIM1_ExtTRGPolarity_NonInverted
+  * @param  ExtTRGFilter specifies the External Trigger Filter.
+  *          This parameter must be a value between 0x00 and 0x0F
+  * @retval None
+  */
+void TIM1_ETRConfig(TIM1_ExtTRGPSC_TypeDef TIM1_ExtTRGPrescaler,
+                    TIM1_ExtTRGPolarity_TypeDef TIM1_ExtTRGPolarity,
+                    uint8_t ExtTRGFilter)
+{
+  assert_param(IS_TIM1_EXT_TRG_FILTER(ExtTRGFilter));
+
+  /* Set the Prescaler, the Filter value and the Polarity */
+  TIM1->ETR |= (uint8_t)((uint8_t)((uint8_t) TIM1_ExtTRGPrescaler
+                                   | (uint8_t) TIM1_ExtTRGPolarity)
+                         | (uint8_t) ExtTRGFilter);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM1_Group7 Specific interface management functions
+ *  @brief    Specific interface management functions 
+ *
+@verbatim   
+ ===============================================================================
+                    Specific interface management functions
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures the TIM1 Encoder Interface.
+  * @param  TIM1_EncoderMode specifies the TIM1 Encoder Mode.
+  *          This parameter can be one of the following values
+  *            @arg TIM1_EncoderMode_TI1: Counter counts on TI1FP1 edge
+  *          depending on TI2FP2 level.
+  *            @arg TIM1_EncoderMode_TI2: Counter counts on TI2FP2 edge
+  *         depending on TI1FP1 level.
+  *            @arg TIM1_EncoderMode_TI12: Counter counts on both TI1FP1 and
+  *         TI2FP2 edges depending on the level of the other input.
+  * @param  TIM1_IC1Polarity specifies the IC1 Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM1_ICPolarity_Rising: Input capture polarity rising
+  *            @arg TIM1_ICPolarity_Falling: Input capture polarity falling
+  * @param  TIM1_IC2Polarity specifies the IC2 Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM1_ICPolarity_Rising: Input capture polarity rising
+  *            @arg TIM1_ICPolarity_Falling: Input capture polarity falling
+  * @retval None
+  */
+void TIM1_EncoderInterfaceConfig(TIM1_EncoderMode_TypeDef TIM1_EncoderMode,
+                                 TIM1_ICPolarity_TypeDef TIM1_IC1Polarity,
+                                 TIM1_ICPolarity_TypeDef TIM1_IC2Polarity)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM1_ENCODER_MODE(TIM1_EncoderMode));
+  assert_param(IS_TIM1_IC_POLARITY(TIM1_IC1Polarity));
+  assert_param(IS_TIM1_IC_POLARITY(TIM1_IC2Polarity));
+
+  /* Set the TI1 and the TI2 Polarities */
+  if (TIM1_IC1Polarity != TIM1_ICPolarity_Rising)
+  {
+    TIM1->CCER1 |= TIM1_CCER1_CC1P;
+  }
+  else
+  {
+    TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC1P);
+  }
+
+  if (TIM1_IC2Polarity != TIM1_ICPolarity_Rising)
+  {
+    TIM1->CCER1 |= TIM1_CCER1_CC2P;
+  }
+  else
+  {
+    TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC2P);
+  }
+  /* Set the encoder Mode */
+  TIM1->SMCR = (uint8_t)((uint8_t)(TIM1->SMCR & (uint8_t)(TIM1_SMCR_MSM | TIM1_SMCR_TS)) | (uint8_t) TIM1_EncoderMode);
+
+  /* Select the Capture Compare 1 and the Capture Compare 2 as input */
+  TIM1->CCMR1 = (uint8_t)((uint8_t)(TIM1->CCMR1 & (uint8_t)(~TIM1_CCMR_CCxS))  | (uint8_t) CCMR_TIxDirect_Set);
+  TIM1->CCMR2 = (uint8_t)((uint8_t)(TIM1->CCMR2 & (uint8_t)(~TIM1_CCMR_CCxS)) | (uint8_t) CCMR_TIxDirect_Set);
+
+}
+
+/**
+  * @brief  Enables or Disables the TIM’s Hall sensor interface.
+  * @param  NewState : The new state of the TIM1 Hall sensor interface.
+  *          This parameter can be ENABLE or DISABLE
+  * @retval None
+  */
+void TIM1_SelectHallSensor(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Set or Reset the TI1S Bit */
+  if (NewState != DISABLE)
+  {
+    TIM1->CR2 |= TIM1_CR2_TI1S;
+  }
+  else
+  {
+    TIM1->CR2 &= (uint8_t)(~TIM1_CR2_TI1S);
+  }
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @brief  Configure the TI1 as Input.
+  * @param  TIM1_ICPolarity  The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM1_ICPolarity_Rising: Input capture polarity rising
+  *            @arg TIM1_ICPolarity_Falling: Input capture polarity falling
+  * @param  TIM1_ICSelection specifies the input to be used.
+  *          This parameter can be one of the following values:
+  *            @arg TIM1_ICSelection_DirectTI: TIM1 Input 1 is selected to be connected to IC1.
+  *            @arg TIM1_ICSelection_IndirectTI: TIM1 Input 1 is selected to be connected to IC2.
+  * @param  TIM1_ICFilter Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  */
+static void TI1_Config(uint8_t TIM1_ICPolarity, uint8_t TIM1_ICSelection, uint8_t TIM1_ICFilter)
+{
+
+  /* Disable the Channel 1: Reset the CCE Bit */
+  TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC1E);
+
+  /* Select the Input and set the filter */
+  TIM1->CCMR1 = (uint8_t)((uint8_t)(TIM1->CCMR1 & (uint8_t)(~( TIM1_CCMR_CCxS | TIM1_CCMR_ICxF)))
+                          | (uint8_t)(( (TIM1_ICSelection)) | ((uint8_t)( TIM1_ICFilter << 4))));
+
+
+
+  /* Select the Polarity */
+  if (TIM1_ICPolarity != TIM1_ICPolarity_Rising)
+  {
+    TIM1->CCER1 |= TIM1_CCER1_CC1P;
+  }
+  else
+  {
+    TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC1P);
+  }
+
+  /* Set the CCE Bit */
+  TIM1->CCER1 |=  TIM1_CCER1_CC1E;
+}
+
+/**
+  * @brief  Configure the TI2 as Input.
+  * @param  TIM1_ICPolarity  The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM1_ICPolarity_Rising: Input capture polarity rising
+  *            @arg TIM1_ICPolarity_Falling: Input capture polarity falling
+  * @param  TIM1_ICSelection specifies the input to be used.
+  *          This parameter can be one of the following values:
+  *            @arg TIM1_ICSelection_DirectTI: TIM1 Input 2 is selected to be connected to IC2.
+  *            @arg TIM1_ICSelection_IndirectTI: TIM1 Input 2 is selected to be connected to IC1.
+  * @param  TIM1_ICFilter Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  */
+static void TI2_Config(uint8_t TIM1_ICPolarity, uint8_t TIM1_ICSelection, uint8_t TIM1_ICFilter)
+{
+  /* Disable the Channel 2: Reset the CCE Bit */
+  TIM1->CCER1 &=  (uint8_t)(~TIM1_CCER1_CC2E);
+
+  /* Select the Input and set the filter */
+  TIM1->CCMR2  = (uint8_t)((uint8_t)(TIM1->CCMR2 & (uint8_t)(~( TIM1_CCMR_CCxS | TIM1_CCMR_ICxF)))
+                           | (uint8_t)(( (TIM1_ICSelection)) | ((uint8_t)( TIM1_ICFilter << 4))));
+  /* Select the Polarity */
+  if (TIM1_ICPolarity != TIM1_ICPolarity_Rising)
+  {
+    TIM1->CCER1 |= TIM1_CCER1_CC2P;
+  }
+  else
+  {
+    TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC2P);
+  }
+  /* Set the CCE Bit */
+  TIM1->CCER1 |=  TIM1_CCER1_CC2E;
+}
+
+/**
+  * @brief  Configure the TI3 as Input.
+  * @param  TIM1_ICPolarity  The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM1_ICPolarity_Rising: Input capture polarity rising
+  *            @arg TIM1_ICPolarity_Falling: Input capture polarity falling
+  * @param  TIM1_ICSelection specifies the input to be used.
+  *          This parameter can be one of the following values:
+  *            @arg TIM1_ICSelection_DirectTI: TIM1 Input 3 is selected to
+  *                         be connected to IC3.
+  * @param  TIM1_ICFilter Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  */
+static void TI3_Config(uint8_t TIM1_ICPolarity, uint8_t TIM1_ICSelection, uint8_t TIM1_ICFilter)
+{
+  /* Disable the Channel 3: Reset the CCE Bit */
+  TIM1->CCER2 &=  (uint8_t)(~TIM1_CCER2_CC3E);
+
+  /* Select the Input and set the filter */
+  TIM1->CCMR3 = (uint8_t)((uint8_t)(TIM1->CCMR3 & (uint8_t)(~( TIM1_CCMR_CCxS | TIM1_CCMR_ICxF)))
+                          | (uint8_t)(( (TIM1_ICSelection)) | ((uint8_t)( TIM1_ICFilter << 4))));
+
+  /* Select the Polarity */
+  if (TIM1_ICPolarity != TIM1_ICPolarity_Rising)
+  {
+    TIM1->CCER2 |= TIM1_CCER2_CC3P;
+  }
+  else
+  {
+    TIM1->CCER2 &= (uint8_t)(~TIM1_CCER2_CC3P);
+  }
+  /* Set the CCE Bit */
+  TIM1->CCER2 |=  TIM1_CCER2_CC3E;
+}
+
+/**
+  * @brief  Configure the TI4 as Input.
+  * @param  TIM1_ICPolarity  The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM1_ICPolarity_Rising: Input capture polarity rising
+  *            @arg TIM1_ICPolarity_Falling: Input capture polarity falling
+  * @param  TIM1_ICSelection specifies the input to be used.
+  *          This parameter can be one of the following values:
+  *            @arg TIM1_ICSelection_IndirectTI: TIM1 Input 4 is selected to be connected to IC3.
+  * @param  TIM1_ICFilter Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  */
+static void TI4_Config(uint8_t TIM1_ICPolarity, uint8_t TIM1_ICSelection, uint8_t TIM1_ICFilter)
+{
+
+  /* Disable the Channel 4: Reset the CCE Bit */
+  TIM1->CCER2 &=  (uint8_t)(~TIM1_CCER2_CC4E);
+
+  /* Select the Input and set the filter */
+  TIM1->CCMR4 = (uint8_t)((uint8_t)(TIM1->CCMR4 & (uint8_t)(~( TIM1_CCMR_CCxS | TIM1_CCMR_ICxF)))
+                          | (uint8_t)(( (TIM1_ICSelection)) | ((uint8_t)( TIM1_ICFilter << 4))));
+
+  /* Select the Polarity */
+  if (TIM1_ICPolarity != TIM1_ICPolarity_Rising)
+  {
+    TIM1->CCER2 |= TIM1_CCER2_CC4P;
+  }
+  else
+  {
+    TIM1->CCER2 &= (uint8_t)(~TIM1_CCER2_CC4P);
+  }
+
+  /* Set the CCE Bit */
+  TIM1->CCER2 |=  TIM1_CCER2_CC4E;
+}
+
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+  
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_tim2.c b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_tim2.c
new file mode 100755
index 0000000..61b964c
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_tim2.c
@@ -0,0 +1,2151 @@
+/**
+  ******************************************************************************
+  * @file    stm8l15x_tim2.c
+  * @author  MCD Application Team
+  * @version V1.6.0
+  * @date    28-June-2013
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the TIM2 peripheral:
+  *            - TimeBase management
+  *            - Output Compare management
+  *            - Input Capture management
+  *            - Interrupts, DMA and flags management
+  *            - Clocks management
+  *            - Synchronization management
+  *            - Specific interface management
+  *              
+  *  @verbatim
+  *  
+  *          ===================================================================
+  *                                 How to use this driver
+  *          ===================================================================
+  *          This driver provides functions to configure and initialise the TIM2
+  *          peripheral
+  *          These functions are split in 7 groups: 
+  *   
+  *          1. TIM2 TimeBase management: this group includes all needed functions 
+  *             to configure the TIM Timebase unit:
+  *                   - Set/Get Prescaler
+  *                   - Set/Get Autoreload  
+  *                   - Counter modes configuration
+  *                   - Select the One Pulse mode
+  *                   - Update Request Configuration
+  *                   - Update Disable Configuration
+  *                   - Auto-Preload Configuration 
+  *                   - Enable/Disable the counter
+  *                 
+  *          2. TIM2 Output Compare management: this group includes all needed 
+  *             functions to configure the Capture/Compare unit used in Output 
+  *             compare mode: 
+  *                   - Configure each channel, independently, in Output Compare mode
+  *                   - Select the output compare modes
+  *                   - Select the Polarities of each channel
+  *                   - Set/Get the Capture/Compare register values
+  *                   - Select the Output Compare Fast mode 
+  *                   - Select the Output Compare Forced mode  
+  *                   - Output Compare-Preload Configuration 
+  *                   - Enable/Disable the Capture/Compare Channels    
+  *                   
+  *          3. TIM2 Input Capture management: this group includes all needed 
+  *             functions to configure the Capture/Compare unit used in 
+  *             Input Capture mode:
+  *                   - Configure each channel in input capture mode
+  *                   - Configure Channel1/2 in PWM Input mode
+  *                   - Set the Input Capture Prescaler
+  *                   - Get the Capture/Compare values      
+  *        
+  *          4. TIM2 interrupts, DMA and flags management
+  *                   - Enable/Disable interrupt sources
+  *                   - Get flags status
+  *                   - Clear flags/ Pending bits
+  *                   - Enable/Disable DMA requests 
+  *                   - Select CaptureCompare DMA request  
+  *              
+  *          5. TIM2 clocks management: this group includes all needed functions 
+  *             to configure the clock controller unit:
+  *                   - Select internal/External clock
+  *                   - Select the external clock mode: ETR(Mode1/Mode2) or TIx
+  *         
+  *          6. TIM2 synchronization management: this group includes all needed 
+  *             functions to configure the Synchronization unit:
+  *                   - Select Input Trigger  
+  *                   - Select Output Trigger  
+  *                   - Select Master Slave Mode 
+  *                   - ETR Configuration when used as external trigger   
+  *     
+  *          7. TIM2 specific interface management, this group includes all 
+  *             needed functions to use the specific TIM2 interface:
+  *                   - Encoder Interface Configuration
+  *                   - Select Hall Sensor        
+  *   
+  *  @endverbatim
+  *    
+  ******************************************************************************
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ****************************************************************************** 
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm8l15x_TIM2.h"
+
+/** @addtogroup STM8L15x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup TIM2 
+  * @brief TIM2 driver modules
+  * @{
+  */
+  
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void TI1_Config(TIM2_ICPolarity_TypeDef TIM2_ICPolarity,
+                       TIM2_ICSelection_TypeDef TIM2_ICSelection,
+                       uint8_t TIM2_ICFilter);
+static void TI2_Config(TIM2_ICPolarity_TypeDef TIM2_ICPolarity,
+                       TIM2_ICSelection_TypeDef TIM2_ICSelection,
+                       uint8_t TIM2_ICFilter);
+
+
+/** @defgroup TIM2_Private_Functions
+  * @{
+  */
+
+/** @defgroup TIM2_Group1 TimeBase management functions
+ *  @brief   TimeBase management functions 
+ *
+@verbatim   
+ ===============================================================================
+                       TimeBase management functions
+ ===============================================================================  
+  
+       ===================================================================      
+              TIM2 Driver: how to use it in Timing(Time base) Mode
+       =================================================================== 
+       To use the Timer in Timing(Time base) mode, the following steps are mandatory:
+       
+       1. Enable TIM2 clock using CLK_PeripheralClockConfig(CLK_Peripheral_TIM2, ENABLE) function.
+        
+       2. Call TIM2_TimeBaseInit() to configure the Time Base unit with the
+          corresponding configuration.
+          
+       3. Enable global interrupts if you need to generate the update interrupt.
+          
+       4. Enable the corresponding interrupt using the function TIM2_ITConfig(TIM2_IT_Update) 
+          
+       5. Call the TIM2_Cmd(ENABLE) function to enable the TIM2 counter.
+       
+       Note1: All other functions can be used separately to modify, if needed,
+          a specific feature of the Timer. 
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitialize the TIM2 peripheral registers to their default reset values.
+  * @param  None
+  * @retval None
+  */
+void TIM2_DeInit(void)
+{
+  TIM2->CR1 = TIM_CR1_RESET_VALUE;
+  TIM2->CR2 = TIM_CR2_RESET_VALUE;
+  TIM2->SMCR = TIM_SMCR_RESET_VALUE;
+  TIM2->ETR = TIM_ETR_RESET_VALUE;
+  TIM2->IER = TIM_IER_RESET_VALUE;
+  TIM2->SR2 = TIM_SR2_RESET_VALUE;
+
+  /* Disable channels */
+  TIM2->CCER1 = TIM_CCER1_RESET_VALUE;
+  /* Configure channels as inputs: it is necessary if lock level is equal to 2 or 3 */
+  TIM2->CCMR1 = 0x01;/*TIM2_ICxSource_TIxFPx */
+  TIM2->CCMR2 = 0x01;/*TIM2_ICxSource_TIxFPx */
+
+  /* Then reset channel registers: it also works if lock level is equal to 2 or 3 */
+  TIM2->CCER1 = TIM_CCER1_RESET_VALUE;
+  TIM2->CCMR1 = TIM_CCMR1_RESET_VALUE;
+  TIM2->CCMR2 = TIM_CCMR2_RESET_VALUE;
+
+  TIM2->CNTRH = TIM_CNTRH_RESET_VALUE;
+  TIM2->CNTRL = TIM_CNTRL_RESET_VALUE;
+
+  TIM2->PSCR = TIM_PSCR_RESET_VALUE;
+
+  TIM2->ARRH = TIM_ARRH_RESET_VALUE;
+  TIM2->ARRL = TIM_ARRL_RESET_VALUE;
+
+  TIM2->CCR1H = TIM_CCR1H_RESET_VALUE;
+  TIM2->CCR1L = TIM_CCR1L_RESET_VALUE;
+  TIM2->CCR2H = TIM_CCR2H_RESET_VALUE;
+  TIM2->CCR2L = TIM_CCR2L_RESET_VALUE;
+
+
+  TIM2->OISR = TIM_OISR_RESET_VALUE;
+  TIM2->EGR = 0x01;/* TIM_EGR_UG */
+  TIM2->BKR = TIM_BKR_RESET_VALUE;
+  TIM2->SR1 = TIM_SR1_RESET_VALUE;
+}
+
+/**
+  * @brief  Initializes the TIM2 Time Base Unit according to the specified  parameters.
+  * @param  TIM2_Prescaler: Prescaler 
+  *          This parameter can be one of the following values:
+  *            @arg TIM2_Prescaler_1: Time base Prescaler = 1 (No effect)
+  *            @arg TIM2_Prescaler_2: Time base Prescaler = 2
+  *            @arg TIM2_Prescaler_4: Time base Prescaler = 4
+  *            @arg TIM2_Prescaler_8: Time base Prescaler = 8
+  *            @arg TIM2_Prescaler_16: Time base Prescaler = 16
+  *            @arg TIM2_Prescaler_32: Time base Prescaler = 32
+  *            @arg TIM2_Prescaler_64: Time base Prescaler = 64
+  *            @arg TIM2_Prescaler_128: Time base Prescaler = 128                            
+  * @param  TIM2_CounterMode: Counter mode
+  *          This parameter can be one of the following values:
+  *            @arg TIM2_CounterMode_Up: Counter Up Mode
+  *            @arg TIM2_CounterMode_Down: Counter Down Mode
+  *            @arg TIM2_CounterMode_CenterAligned1: Counter Central aligned Mode 1
+  *            @arg TIM2_CounterMode_CenterAligned2: Counter Central aligned Mode 2
+  *            @arg TIM2_CounterMode_CenterAligned3: Counter Central aligned Mode 3        
+  * @param  TIM2_Period: This parameter must be a value between 0x0000 and 0xFFFF.
+  * @retval None
+  */
+
+void TIM2_TimeBaseInit(TIM2_Prescaler_TypeDef TIM2_Prescaler,
+                       TIM2_CounterMode_TypeDef TIM2_CounterMode,
+                       uint16_t TIM2_Period)
+{
+
+  assert_param(IS_TIM2_PRESCALER(TIM2_Prescaler));
+  assert_param(IS_TIM2_COUNTER_MODE(TIM2_CounterMode));
+
+
+
+  /* Set the Autoreload value */
+  TIM2->ARRH = (uint8_t)(TIM2_Period >> 8) ;
+  TIM2->ARRL = (uint8_t)(TIM2_Period);
+
+  /* Set the Prescaler value */
+  TIM2->PSCR = (uint8_t)(TIM2_Prescaler);
+
+  /* Select the Counter Mode */
+  TIM2->CR1 &= (uint8_t)((uint8_t)(~TIM_CR1_CMS)) & ((uint8_t)(~TIM_CR1_DIR));
+  TIM2->CR1 |= (uint8_t)(TIM2_CounterMode);
+
+  /* Generate an update event to reload the Prescaler value immediately */
+  TIM2->EGR = TIM2_EventSource_Update;
+}
+
+/**
+  * @brief  Configures the TIM2 Prescaler.
+  * @param  Prescaler: Specifies the Prescaler Register value
+  *          This parameter can be one of the following values:
+  *            @arg TIM2_Prescaler_1: Time base Prescaler = 1 (No effect)
+  *            @arg TIM2_Prescaler_2: Time base Prescaler = 2
+  *            @arg TIM2_Prescaler_4: Time base Prescaler = 4
+  *            @arg TIM2_Prescaler_8: Time base Prescaler = 8
+  *            @arg TIM2_Prescaler_16: Time base Prescaler = 16
+  *            @arg TIM2_Prescaler_32: Time base Prescaler = 32
+  *            @arg TIM2_Prescaler_64: Time base Prescaler = 64
+  *            @arg TIM2_Prescaler_128: Time base Prescaler = 128  
+  * @param  TIM2_PSCReloadMode: Specifies the TIM2 Prescaler Reload mode.
+  *          This parameter can be one of the following values:
+  *            @arg TIM2_PSCReloadMode_Update: Prescaler value is reloaded at every update
+  *            @arg TIM2_PSCReloadMode_Immediate: Prescaler value is reloaded at every update  
+  * @retval None
+  */
+void TIM2_PrescalerConfig(TIM2_Prescaler_TypeDef Prescaler,
+                          TIM2_PSCReloadMode_TypeDef TIM2_PSCReloadMode)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM2_PRESCALER(Prescaler));
+  assert_param(IS_TIM2_PRESCALER_RELOAD(TIM2_PSCReloadMode));
+
+  /* Set the Prescaler value */
+  TIM2->PSCR = (uint8_t)(Prescaler);
+
+  /* Set or reset the UG Bit */
+  if (TIM2_PSCReloadMode == TIM2_PSCReloadMode_Immediate)
+  {
+    TIM2->EGR |= TIM_EGR_UG ;
+  }
+  else
+  {
+    TIM2->EGR &= (uint8_t)(~TIM_EGR_UG) ;
+  }
+}
+
+/**
+  * @brief  Specifies the TIM2 Counter Mode to be used.
+  * @param  TIM2_CounterMode: Specifies the Counter Mode to be used
+  *          This parameter can be one of the following values:
+  *            @arg TIM2_CounterMode_Up: Counter Up Mode
+  *            @arg TIM2_CounterMode_Down: Counter Down Mode
+  *            @arg TIM2_CounterMode_CenterAligned1: Counter Central aligned Mode 1
+  *            @arg TIM2_CounterMode_CenterAligned2: Counter Central aligned Mode 2
+  *            @arg TIM2_CounterMode_CenterAligned3: Counter Central aligned Mode 3      
+  * @retval None
+  */
+void TIM2_CounterModeConfig(TIM2_CounterMode_TypeDef TIM2_CounterMode)
+{
+  uint8_t tmpcr1 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM2_COUNTER_MODE(TIM2_CounterMode));
+
+  tmpcr1 = TIM2->CR1;
+
+  /* Reset the CMS and DIR Bits */
+  tmpcr1 &= (uint8_t)((uint8_t)(~TIM_CR1_CMS) & (uint8_t)(~TIM_CR1_DIR));
+
+  /* Set the Counter Mode */
+  tmpcr1 |= (uint8_t)TIM2_CounterMode;
+
+  TIM2->CR1 = tmpcr1;
+}
+
+/**
+  * @brief  Sets the TIM2 Counter Register value.
+  * @param  Counter: Specifies the Counter register new value.
+  *          This parameter is between 0x0000 and 0xFFFF.
+  * @retval None
+  */
+void TIM2_SetCounter(uint16_t Counter)
+{
+
+  /* Set the Counter Register value */
+  TIM2->CNTRH = (uint8_t)(Counter >> 8);
+  TIM2->CNTRL = (uint8_t)(Counter);
+}
+
+/**
+  * @brief  Sets the TIM2 Autoreload Register value.
+  * @param  Autoreload: Specifies the Autoreload register new value.
+  *          This parameter is between 0x0000 and 0xFFFF.
+  * @retval None
+  */
+void TIM2_SetAutoreload(uint16_t Autoreload)
+{
+  /* Set the Autoreload Register value */
+  TIM2->ARRH = (uint8_t)(Autoreload >> 8);
+  TIM2->ARRL = (uint8_t)(Autoreload);
+}
+
+/**
+  * @brief  Gets the TIM2 Counter value.
+  * @param  None
+  * @retval Counter Register value.
+  */
+uint16_t TIM2_GetCounter(void)
+{
+  uint16_t tmpcnt = 0;
+  uint8_t tmpcntrl, tmpcntrh;
+
+  tmpcntrh = TIM2->CNTRH;
+  tmpcntrl = TIM2->CNTRL;
+
+  tmpcnt = (uint16_t)(tmpcntrl);
+  tmpcnt |= (uint16_t)((uint16_t)tmpcntrh << 8);
+  /* Get the Counter Register value */
+  return ((uint16_t)tmpcnt);
+}
+
+/**
+  * @brief  Gets the TIM2 Prescaler value.
+  * @param  None
+  * @retval TIM2 Prescaler, it can be one of the following values:
+  *            - TIM2_Prescaler_1: Time base Prescaler = 1 (No effect)
+  *            - TIM2_Prescaler_2: Time base Prescaler = 2
+  *            - TIM2_Prescaler_4: Time base Prescaler = 4
+  *            - TIM2_Prescaler_8: Time base Prescaler = 8
+  *            - TIM2_Prescaler_16: Time base Prescaler = 16
+  *            - TIM2_Prescaler_32: Time base Prescaler = 32
+  *            - TIM2_Prescaler_64: Time base Prescaler = 64
+  *            - TIM2_Prescaler_128: Time base Prescaler = 128    
+  */
+TIM2_Prescaler_TypeDef TIM2_GetPrescaler(void)
+{
+  /* Get the Prescaler Register value */
+  return ((TIM2_Prescaler_TypeDef)TIM2->PSCR);
+}
+
+/**
+  * @brief  Enables or Disables the TIM2 Update event.
+  * @param  NewState: The new state of the TIM2 peripheral Preload register.
+  *          This parameter can be ENABLE or DISABLE
+  * @retval None
+  */
+
+void TIM2_UpdateDisableConfig(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Set or Reset the UDIS Bit */
+  if (NewState != DISABLE)
+  {
+    TIM2->CR1 |= TIM_CR1_UDIS;
+  }
+  else
+  {
+    TIM2->CR1 &= (uint8_t)(~TIM_CR1_UDIS);
+  }
+}
+
+/**
+  * @brief  Selects the TIM2 Update Request Interrupt source.
+  * @param  TIM2_UpdateSource: Specifies the Update source.
+  *          This parameter can be one of the following values:
+  *            @arg TIM2_UpdateSource_Global: Global Update request source
+  *            @arg TIM2_UpdateSource_Regular: Regular Update request source 
+  * @retval None
+  */
+void TIM2_UpdateRequestConfig(TIM2_UpdateSource_TypeDef TIM2_UpdateSource)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM2_UPDATE_SOURCE(TIM2_UpdateSource));
+
+  /* Set or Reset the URS Bit */
+  if (TIM2_UpdateSource == TIM2_UpdateSource_Regular)
+  {
+    TIM2->CR1 |= TIM_CR1_URS ;
+  }
+  else
+  {
+    TIM2->CR1 &= (uint8_t)(~TIM_CR1_URS);
+  }
+}
+
+/**
+  * @brief  Enables or disables TIM2 peripheral Preload register on ARR.
+  * @param  NewState: The new state of the TIM2 peripheral Preload register.
+  *          This parameter can be ENABLE or DISABLE
+  * @retval None
+  */
+void TIM2_ARRPreloadConfig(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Set or Reset the ARPE Bit */
+  if (NewState != DISABLE)
+  {
+    TIM2->CR1 |= TIM_CR1_ARPE;
+  }
+  else
+  {
+    TIM2->CR1 &= (uint8_t)(~TIM_CR1_ARPE);
+  }
+}
+
+/**
+  * @brief  Selects the TIM’s One Pulse Mode.
+  * @param  TIM2_OPMode: Specifies the OPM Mode to be used.
+  *          This parameter can be one of the following values:
+  *            @arg TIM2_OPMode_Single: Single one Pulse mode (OPM Active)
+  *            @arg TIM2_OPMode_Repetitive: Single one Pulse mode (OPM Active)  
+  * @retval None
+  */
+void TIM2_SelectOnePulseMode(TIM2_OPMode_TypeDef TIM2_OPMode)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM2_OPM_MODE(TIM2_OPMode));
+
+  /* Set or Reset the OPM Bit */
+  if (TIM2_OPMode == TIM2_OPMode_Single)
+  {
+    TIM2->CR1 |= TIM_CR1_OPM ;
+  }
+  else
+  {
+    TIM2->CR1 &= (uint8_t)(~TIM_CR1_OPM);
+  }
+}
+
+/**
+  * @brief  Enables or disables the TIM2 peripheral.
+  * @param  NewState: The new state of the TIM2 peripheral.
+  *          This parameter can be ENABLE or DISABLE
+  * @retval None
+  */
+void TIM2_Cmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* set or Reset the CEN Bit */
+  if (NewState != DISABLE)
+  {
+    TIM2->CR1 |= TIM_CR1_CEN;
+  }
+  else
+  {
+    TIM2->CR1 &= (uint8_t)(~TIM_CR1_CEN);
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM2_Group2 Output Compare management functions
+ *  @brief    Output Compare management functions 
+ *
+@verbatim   
+ ===============================================================================
+                        Output Compare management functions
+ ===============================================================================  
+   
+       ===================================================================      
+              TIM2 Driver: how to use it in Output Compare Mode
+       =================================================================== 
+       To use the Timer in Output Compare mode, the following steps are mandatory:
+       
+       1. Enable TIM2 clock using CLK_PeripheralClockConfig(CLK_Peripheral_TIM2, ENABLE) function.
+       
+       2. Configure the TIM2 pins in output mode by configuring the corresponding GPIO pins
+          
+       3. Configure the Time base unit as described in the first part of this driver, if needed,
+          otherwise the Timer will run with the default configuration:
+          - Autoreload value = 0xFFFF
+          - Prescaler value = 0x0000
+          - Counter mode = Up counting
+      
+       4. Call TIM2_OCxInit() to configure the channel x with the desired parameters
+          including:
+          - TIM2 Output Compare mode: TIM2_OCMode
+          - TIM2 Output State: TIM2_OutputState
+          - TIM2 Pulse value: TIM2_Pulse
+          - TIM2 Output Compare Polarity: TIM2_OCPolarity
+          - TIM2 Output Idle State: TIM2_OCIdleState
+       
+       5. Call the TIM2_Cmd(ENABLE) function to enable the TIM2 counter.
+       
+       Note1: All other functions can be used separately to modify, if needed,
+          a specific feature of the Timer. 
+       
+       Note2: If the corresponding interrupt or DMA request are needed, the user should:
+              1. Enable global interrupts (or the DMA) to use the TIM2 interrupts (or DMA requests). 
+              2. Enable the corresponding interrupt (or DMA request) using the function 
+              TIM2_ITConfig(TIM2_IT_CCx) (or TIM2_DMACmd(TIM2_DMASource_CCx))   
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the TIM2 Channel1 according to the specified parameters.
+  * @param  TIM2_OCMode: Output Compare Mode 
+  *          This parameter can be one of the following values:
+  *            @arg TIM2_OCMode_Timing: Timing (Frozen) Mode
+  *            @arg TIM2_OCMode_Active: Active Mode
+  *            @arg TIM2_OCMode_Inactive: Inactive Mode
+  *            @arg TIM2_OCMode_Toggle: Toggle Mode
+  *            @arg TIM2_OCMode_PWM1: PWM Mode 1
+  *            @arg TIM2_OCMode_PWM2: PWM Mode 2          
+  * @param  TIM2_OutputState: Output state
+  *          This parameter can be one of the following values:
+  *            @arg TIM2_OutputState_Disable: Output compare State disabled (channel output disabled)
+  *            @arg TIM2_OutputState_Enable: Output compare State enabled (channel output enabled)
+  * @param  TIM2_Pulse: This parameter must be a value between 0x0000 and 0xFFFF.
+  * @param  TIM2_OCPolarity: Polarity
+  *          This parameter can be one of the following values:
+  *            @arg TIM2_OCPolarity_High: Output compare polarity  = High
+  *            @arg TIM2_OCPolarity_Low: Output compare polarity  = Low 
+  * @param  TIM2_OCIdleState: Output Compare Idle State
+  *          This parameter can be one of the following values:
+  *            @arg TIM2_OCIdleState_Reset: Output Compare Idle state  = Reset
+  *            @arg TIM2_OCIdleState_Set: Output Compare Idle state  = Set
+  * @retval None
+  */
+void TIM2_OC1Init(TIM2_OCMode_TypeDef TIM2_OCMode,
+                  TIM2_OutputState_TypeDef TIM2_OutputState,
+                  uint16_t TIM2_Pulse,
+                  TIM2_OCPolarity_TypeDef TIM2_OCPolarity,
+                  TIM2_OCIdleState_TypeDef TIM2_OCIdleState)
+{
+  uint8_t tmpccmr1 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM2_OC_MODE(TIM2_OCMode));
+  assert_param(IS_TIM2_OUTPUT_STATE(TIM2_OutputState));
+  assert_param(IS_TIM2_OC_POLARITY(TIM2_OCPolarity));
+  assert_param(IS_TIM2_OCIDLE_STATE(TIM2_OCIdleState));
+
+  tmpccmr1 = TIM2->CCMR1;
+
+  /* Disable the Channel 1: Reset the CCE Bit */
+  TIM2->CCER1 &= (uint8_t)(~TIM_CCER1_CC1E);
+  /* Reset the Output Compare Bits */
+  tmpccmr1 &= (uint8_t)(~TIM_CCMR_OCM);
+
+  /* Set the Output Compare Mode */
+  tmpccmr1 |= (uint8_t)TIM2_OCMode;
+
+  TIM2->CCMR1 = tmpccmr1;
+
+  /* Set the Output State */
+  if (TIM2_OutputState == TIM2_OutputState_Enable)
+  {
+    TIM2->CCER1 |= TIM_CCER1_CC1E;
+  }
+  else
+  {
+    TIM2->CCER1 &= (uint8_t)(~TIM_CCER1_CC1E);
+  }
+
+  /* Set the Output Polarity */
+  if (TIM2_OCPolarity == TIM2_OCPolarity_Low)
+  {
+    TIM2->CCER1 |= TIM_CCER1_CC1P;
+  }
+  else
+  {
+    TIM2->CCER1 &= (uint8_t)(~TIM_CCER1_CC1P);
+  }
+
+  /* Set the Output Idle state */
+  if (TIM2_OCIdleState == TIM2_OCIdleState_Set)
+  {
+    TIM2->OISR |= TIM_OISR_OIS1;
+  }
+  else
+  {
+    TIM2->OISR &= (uint8_t)(~TIM_OISR_OIS1);
+  }
+
+  /* Set the Pulse value */
+  TIM2->CCR1H = (uint8_t)(TIM2_Pulse >> 8);
+  TIM2->CCR1L = (uint8_t)(TIM2_Pulse);
+}
+
+/**
+  * @brief  Initializes the TIM2 Channel2 according to the specified parameters.
+  * @param  TIM2_OCMode: Output Compare Mode 
+  *          This parameter can be one of the following values:
+  *            @arg TIM2_OCMode_Timing: Timing (Frozen) Mode
+  *            @arg TIM2_OCMode_Active: Active Mode
+  *            @arg TIM2_OCMode_Inactive: Inactive Mode
+  *            @arg TIM2_OCMode_Toggle: Toggle Mode
+  *            @arg TIM2_OCMode_PWM1: PWM Mode 1
+  *            @arg TIM2_OCMode_PWM2: PWM Mode 2          
+  * @param  TIM2_OutputState: Output state
+  *          This parameter can be one of the following values:
+  *            @arg TIM2_OutputState_Disable: Output compare State disabled (channel output disabled)
+  *            @arg TIM2_OutputState_Enable: Output compare State enabled (channel output enabled)
+  * @param  TIM2_Pulse: This parameter must be a value between 0x0000 and 0xFFFF.
+  * @param  TIM2_OCPolarity: Polarity
+  *          This parameter can be one of the following values:
+  *            @arg TIM2_OCPolarity_High: Output compare polarity  = High
+  *            @arg TIM2_OCPolarity_Low: Output compare polarity  = Low 
+  * @param  TIM2_OCIdleState: Output Compare Idle State
+  *          This parameter can be one of the following values:
+  *            @arg TIM2_OCIdleState_Reset: Output Compare Idle state  = Reset
+  *            @arg TIM2_OCIdleState_Set: Output Compare Idle state  = Set
+  * @retval None
+  */
+void TIM2_OC2Init(TIM2_OCMode_TypeDef TIM2_OCMode,
+                  TIM2_OutputState_TypeDef TIM2_OutputState,
+                  uint16_t TIM2_Pulse,
+                  TIM2_OCPolarity_TypeDef TIM2_OCPolarity,
+                  TIM2_OCIdleState_TypeDef TIM2_OCIdleState)
+{
+  uint8_t tmpccmr2 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM2_OC_MODE(TIM2_OCMode));
+  assert_param(IS_TIM2_OUTPUT_STATE(TIM2_OutputState));
+  assert_param(IS_TIM2_OC_POLARITY(TIM2_OCPolarity));
+  assert_param(IS_TIM2_OCIDLE_STATE(TIM2_OCIdleState));
+
+  tmpccmr2 = TIM2->CCMR2;
+
+  /* Disable the Channel 2: Reset the CCE Bit */
+  TIM2->CCER1 &= (uint8_t)(~TIM_CCER1_CC2E);
+
+  /* Reset the Output Compare Bits */
+  tmpccmr2 &= (uint8_t)(~TIM_CCMR_OCM);
+
+  /* Set the Output Compare Mode */
+  tmpccmr2 |= (uint8_t)TIM2_OCMode;
+
+  TIM2->CCMR2 = tmpccmr2;
+
+  /* Set the Output State */
+  if (TIM2_OutputState == TIM2_OutputState_Enable)
+  {
+    TIM2->CCER1 |= TIM_CCER1_CC2E;
+  }
+  else
+  {
+    TIM2->CCER1 &= (uint8_t)(~TIM_CCER1_CC2E);
+  }
+
+  /* Set the Output Polarity */
+  if (TIM2_OCPolarity == TIM2_OCPolarity_Low)
+  {
+    TIM2->CCER1 |= TIM_CCER1_CC2P;
+  }
+  else
+  {
+    TIM2->CCER1 &= (uint8_t)(~TIM_CCER1_CC2P);
+  }
+
+
+  /* Set the Output Idle state */
+  if (TIM2_OCIdleState == TIM2_OCIdleState_Set)
+  {
+    TIM2->OISR |= TIM_OISR_OIS2;
+  }
+  else
+  {
+    TIM2->OISR &= (uint8_t)(~TIM_OISR_OIS2);
+  }
+
+  /* Set the Pulse value */
+  TIM2->CCR2H = (uint8_t)(TIM2_Pulse >> 8);
+  TIM2->CCR2L = (uint8_t)(TIM2_Pulse);
+}
+
+/**
+  * @brief  Configures the Break feature, dead time, Lock level, the OSSI,
+  *         and the AOE(automatic output enable).
+  * @param  TIM2_OSSIState: Off-State Selection for Idle mode states.
+  *          This parameter can be one of the following values:
+  *            @arg TIM2_OSSIState_Enable: Off-State Selection for Idle mode enabled
+  *            @arg TIM2_OSSIState_Disable: Off-State Selection for Idle mode disabled 
+  * @param  TIM2_LockLevel: Lock level.
+  *          This parameter can be one of the following values:
+  *            @arg TIM2_LockLevel_Off: Lock option disabled
+  *            @arg TIM2_LockLevel_1: Select Lock Level 1
+  *            @arg TIM2_LockLevel_2: Select Lock Level 2
+  *            @arg TIM2_LockLevel_3: Select Lock Level 3    
+  * @param  TIM2_BreakState: Break Input enable/disable .
+  *          This parameter can be one of the following values:
+  *            @arg TIM2_BreakState_Disable: Break State disabled (break option disabled)
+  *            @arg TIM2_BreakState_Enable: Break State enabled (break option enabled) 
+  * @param  TIM2_BreakPolarity: Break Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM2_BreakPolarity_High: if Break, channel polarity = High
+  *            @arg TIM2_BreakPolarity_Low: if Break, channel polarity = Low   
+  * @param  TIM2_AutomaticOutput: TIM2 AOE Bit Set/Reset .
+  *          This parameter can be one of the following values:
+  *            @arg TIM2_AutomaticOutput_Enable: Automatic Output option enabled
+  *            @arg TIM2_AutomaticOutput_Disable: Automatic Output option disabled
+  * @retval None
+  */
+void TIM2_BKRConfig(TIM2_OSSIState_TypeDef TIM2_OSSIState,
+                    TIM2_LockLevel_TypeDef TIM2_LockLevel,
+                    TIM2_BreakState_TypeDef TIM2_BreakState,
+                    TIM2_BreakPolarity_TypeDef TIM2_BreakPolarity,
+                    TIM2_AutomaticOutput_TypeDef TIM2_AutomaticOutput)
+
+{
+  /* Check the parameters */
+  assert_param(IS_TIM2_OSSI_STATE(TIM2_OSSIState));
+  assert_param(IS_TIM2_LOCK_LEVEL(TIM2_LockLevel));
+  assert_param(IS_TIM2_BREAK_STATE(TIM2_BreakState));
+  assert_param(IS_TIM2_BREAK_POLARITY(TIM2_BreakPolarity));
+  assert_param(IS_TIM2_AUTOMATIC_OUTPUT_STATE(TIM2_AutomaticOutput));
+
+
+
+  /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSI State,
+  the dead time value and the Automatic Output Enable Bit */
+  TIM2->BKR = (uint8_t)((uint8_t)((uint8_t)((uint8_t)((uint8_t)TIM2_OSSIState | (uint8_t)TIM2_LockLevel) | \
+                                  (uint8_t)((uint8_t)TIM2_BreakState | (uint8_t)TIM2_BreakPolarity)) | \
+                                  TIM2_AutomaticOutput));
+}
+
+/**
+  * @brief  Enables or disables the TIM2 peripheral Main Outputs.
+  * @param  NewState: The new state of the TIM2 peripheral.
+  *          This parameter can be ENABLE or DISABLE
+  * @retval None
+  */
+void TIM2_CtrlPWMOutputs(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Set or Reset the MOE Bit */
+
+  if (NewState != DISABLE)
+  {
+    TIM2->BKR |= TIM_BKR_MOE ;
+  }
+  else
+  {
+    TIM2->BKR &= (uint8_t)(~TIM_BKR_MOE) ;
+  }
+}
+
+/**
+  * @brief  Selects the TIM2 Output Compare Mode. This function disables the
+  *         selected channel before changing the Output Compare Mode. User has to
+  *         enable this channel using TIM2_CCxCmd and TIM2_CCxNCmd functions.
+  * @param  TIM2_Channel: Specifies the TIM2 Channel.
+  *          This parameter can be one of the following values:
+  *            @arg TIM2_Channel_1: Channel 1
+  *            @arg TIM2_Channel_2: Channel 2  
+  * @param  TIM2_OCMode: Specifies the TIM2 Output Compare Mode.
+  *          This parameter can be one of the following values:
+  *            @arg TIM2_OCMode_Timing: Timing (Frozen) Mode
+  *            @arg TIM2_OCMode_Active: Active Mode
+  *            @arg TIM2_OCMode_Inactive: Inactive Mode
+  *            @arg TIM2_OCMode_Toggle: Toggle Mode
+  *            @arg TIM2_OCMode_PWM1: PWM Mode 1
+  *            @arg TIM2_OCMode_PWM2: PWM Mode 2    
+  * @retval None
+  */
+void TIM2_SelectOCxM(TIM2_Channel_TypeDef TIM2_Channel,
+                     TIM2_OCMode_TypeDef TIM2_OCMode)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM2_CHANNEL(TIM2_Channel));
+  assert_param(IS_TIM2_OCM(TIM2_OCMode));
+
+  if (TIM2_Channel == TIM2_Channel_1)
+  {
+    /* Disable the Channel 1: Reset the CCE Bit */
+    TIM2->CCER1 &= (uint8_t)(~TIM_CCER1_CC1E);
+
+    /* Reset the Output Compare Bits */
+    TIM2->CCMR1 &= (uint8_t)(~TIM_CCMR_OCM);
+
+    /* Set the Output Compare Mode */
+    TIM2->CCMR1 |= (uint8_t)TIM2_OCMode;
+  }
+  else /* if (TIM2_Channel == TIM2_Channel_2) */
+  {
+    /* Disable the Channel 2: Reset the CCE Bit */
+    TIM2->CCER1 &= (uint8_t)(~TIM_CCER1_CC2E);
+
+    /* Reset the Output Compare Bits */
+    TIM2->CCMR2 &= (uint8_t)(~TIM_CCMR_OCM);
+
+    /* Set the Output Compare Mode */
+    TIM2->CCMR2 |= (uint8_t)TIM2_OCMode;
+  }
+}
+
+/**
+  * @brief  Sets the TIM2 Capture Compare1 Register value.
+  * @param  Compare: Specifies the Capture Compare1 register new value.
+  *         This parameter is between 0x0000 and 0xFFFF.
+  * @retval None
+  */
+void TIM2_SetCompare1(uint16_t Compare)
+{
+  /* Set the Capture Compare1 Register value */
+  TIM2->CCR1H = (uint8_t)(Compare >> 8);
+  TIM2->CCR1L = (uint8_t)(Compare);
+}
+
+/**
+  * @brief  Sets the TIM2 Capture Compare2 Register value.
+  * @param  Compare: Specifies the Capture Compare2 register new value.
+  *         This parameter is between 0x0000 and 0xFFFF.
+  * @retval None
+  */
+void TIM2_SetCompare2(uint16_t Compare)
+{
+  /* Set the Capture Compare2 Register value */
+  TIM2->CCR2H = (uint8_t)(Compare >> 8);
+  TIM2->CCR2L = (uint8_t)(Compare);
+}
+
+/**
+  * @brief  Forces the TIM2 Channel1 output waveform to active or inactive level.
+  * @param  TIM2_ForcedAction: Specifies the forced Action to be set to the output waveform.
+  *          This parameter can be one of the following values:
+  *            @arg TIM2_ForcedAction_Active: Output Reference is forced low 
+  *            @arg TIM2_ForcedAction_Inactive: Output Reference is forced high 
+  * @retval None
+  */
+void TIM2_ForcedOC1Config(TIM2_ForcedAction_TypeDef TIM2_ForcedAction)
+{
+  uint8_t tmpccmr1 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM2_FORCED_ACTION(TIM2_ForcedAction));
+
+  tmpccmr1 = TIM2->CCMR1;
+
+  /* Reset the OCM Bits */
+  tmpccmr1 &= (uint8_t)(~TIM_CCMR_OCM);
+
+  /* Configure The Forced output Mode */
+  tmpccmr1 |= (uint8_t)TIM2_ForcedAction;
+
+  TIM2->CCMR1 = tmpccmr1;
+}
+
+/**
+  * @brief  Forces the TIM2 Channel2 output waveform to active or inactive level.
+  * @param  TIM2_ForcedAction: Specifies the forced Action to be set to the output waveform.
+  *          This parameter can be one of the following values:
+  *            @arg TIM2_ForcedAction_Active: Output Reference is forced low 
+  *            @arg TIM2_ForcedAction_Inactive: Output Reference is forced high 
+  * @retval None
+  */
+void TIM2_ForcedOC2Config(TIM2_ForcedAction_TypeDef TIM2_ForcedAction)
+{
+  uint8_t tmpccmr2 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM2_FORCED_ACTION(TIM2_ForcedAction));
+
+  tmpccmr2 = TIM2->CCMR2;
+
+  /* Reset the OCM Bits */
+  tmpccmr2 &= (uint8_t)(~TIM_CCMR_OCM);
+
+  /* Configure The Forced output Mode */
+  tmpccmr2 |= (uint8_t)TIM2_ForcedAction;
+
+  TIM2->CCMR2 = tmpccmr2;
+}
+
+/**
+  * @brief  Enables or disables the TIM2 peripheral Preload Register on CCR1.
+  * @param  NewState: The new state of the Capture Compare Preload register.
+  *          This parameter can be ENABLE or DISABLE
+  * @retval None
+  */
+void TIM2_OC1PreloadConfig(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Set or Reset the OC1PE Bit */
+  if (NewState != DISABLE)
+  {
+    TIM2->CCMR1 |= TIM_CCMR_OCxPE ;
+  }
+  else
+  {
+    TIM2->CCMR1 &= (uint8_t)(~TIM_CCMR_OCxPE) ;
+  }
+}
+
+/**
+  * @brief  Enables or disables the TIM2 peripheral Preload Register on CCR2.
+  * @param  NewState: The new state of the Capture Compare Preload register.
+  *          This parameter can be ENABLE or DISABLE
+  * @retval None
+  */
+void TIM2_OC2PreloadConfig(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Set or Reset the OC2PE Bit */
+  if (NewState != DISABLE)
+  {
+    TIM2->CCMR2 |= TIM_CCMR_OCxPE ;
+  }
+  else
+  {
+    TIM2->CCMR2 &= (uint8_t)(~TIM_CCMR_OCxPE) ;
+  }
+}
+
+/**
+  * @brief  Configures the TIM2 Capture Compare 1 Fast feature.
+  * @param  NewState: The new state of the Output Compare Fast Enable bit.
+  *          This parameter can be ENABLE or DISABLE
+  * @retval None
+  */
+void TIM2_OC1FastConfig(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Set or Reset the OC1FE Bit */
+  if (NewState != DISABLE)
+  {
+    TIM2->CCMR1 |= TIM_CCMR_OCxFE ;
+  }
+  else
+  {
+    TIM2->CCMR1 &= (uint8_t)(~TIM_CCMR_OCxFE) ;
+  }
+}
+
+/**
+  * @brief  Configures the TIM2 Capture Compare 2 Fast feature.
+  * @param  NewState: The new state of the Output Compare Fast Enable bit.
+  *          This parameter can be ENABLE or DISABLE
+  * @retval None
+  */
+
+void TIM2_OC2FastConfig(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Set or Reset the OC2FE Bit */
+  if (NewState != DISABLE)
+  {
+    TIM2->CCMR2 |= TIM_CCMR_OCxFE ;
+  }
+  else
+  {
+    TIM2->CCMR2 &= (uint8_t)(~TIM_CCMR_OCxFE) ;
+  }
+}
+
+/**
+  * @brief  Configures the TIM2 Channel 1 polarity.
+  * @param  TIM2_OCPolarity: Specifies the OC1 Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM2_OCPolarity_High: Output compare polarity  = High
+  *            @arg TIM2_OCPolarity_Low: Output compare polarity  = Low 
+  * @retval None
+  */
+void TIM2_OC1PolarityConfig(TIM2_OCPolarity_TypeDef TIM2_OCPolarity)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM2_OC_POLARITY(TIM2_OCPolarity));
+
+  /* Set or Reset the CC1P Bit */
+  if (TIM2_OCPolarity == TIM2_OCPolarity_Low)
+  {
+    TIM2->CCER1 |= TIM_CCER1_CC1P ;
+  }
+  else
+  {
+    TIM2->CCER1 &= (uint8_t)(~TIM_CCER1_CC1P) ;
+  }
+}
+
+/**
+  * @brief  Configures the TIM2 Channel 2 polarity.
+  * @param  TIM2_OCPolarity: Specifies the OC2 Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM2_OCPolarity_High: Output compare polarity  = High
+  *            @arg TIM2_OCPolarity_Low: Output compare polarity  = Low 
+  * @retval None
+  */
+void TIM2_OC2PolarityConfig(TIM2_OCPolarity_TypeDef TIM2_OCPolarity)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM2_OC_POLARITY(TIM2_OCPolarity));
+
+  /* Set or Reset the CC2P Bit */
+  if (TIM2_OCPolarity == TIM2_OCPolarity_Low)
+  {
+    TIM2->CCER1 |= TIM_CCER1_CC2P ;
+  }
+  else
+  {
+    TIM2->CCER1 &= (uint8_t)(~TIM_CCER1_CC2P) ;
+  }
+}
+
+/**
+  * @brief  Enables or disables the TIM2 Capture Compare Channel x.
+  * @param  TIM2_Channel: Specifies the TIM2 Channel.
+  *          This parameter can be one of the following values:
+  *            @arg TIM2_Channel_1: Channel 1
+  *            @arg TIM2_Channel_2: Channel 2  
+  * @param  NewState: Specifies the TIM2 Channel CCxE bit new state.
+  *          This parameter can be ENABLE or DISABLE
+  * @retval None
+  */
+void TIM2_CCxCmd(TIM2_Channel_TypeDef TIM2_Channel,
+                 FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM2_CHANNEL(TIM2_Channel));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (TIM2_Channel == TIM2_Channel_1)
+  {
+    /* Set or Reset the CC1E Bit */
+    if (NewState != DISABLE)
+    {
+      TIM2->CCER1 |= TIM_CCER1_CC1E ;
+    }
+    else
+    {
+      TIM2->CCER1 &= (uint8_t)(~TIM_CCER1_CC1E) ;
+    }
+
+  }
+  else /* if (TIM2_Channel == TIM2_Channel_2) */
+  {
+    /* Set or Reset the CC2E Bit */
+    if (NewState != DISABLE)
+    {
+      TIM2->CCER1 |= TIM_CCER1_CC2E;
+    }
+    else
+    {
+      TIM2->CCER1 &= (uint8_t)(~TIM_CCER1_CC2E) ;
+    }
+  }
+}
+
+/** @defgroup TIM2_Group3 Input Capture management functions
+ *  @brief    Input Capture management functions 
+ *
+@verbatim   
+ ===============================================================================
+                      Input Capture management functions
+ ===============================================================================  
+   
+       ===================================================================      
+              TIM2 Driver: how to use it in Input Capture Mode
+       =================================================================== 
+       To use the Timer in Input Capture mode, the following steps are mandatory:
+       
+       1. Enable TIM2 clock using CLK_PeripheralClockConfig(CLK_Peripheral_TIM2, ENABLE) function.
+       
+       2. Configure the TIM2 pins in input mode by configuring the corresponding GPIO pins
+       
+       3. Configure the Time base unit as described in the first part of this driver, if needed,
+          otherwise the Timer will run with the default configuration:
+          - Autoreload value = 0xFFFF
+          - Prescaler value = 0x0
+          - Counter mode = Up counting
+       
+       4. Call TIM2_ICInit() to configure the desired channel to measure only 
+          frequency or duty cycle of the input signal using the corresponding configuration: 
+          - TIM2 Channel: TIM2_Channel
+          - TIM2 Input Capture polarity: TIM2_ICPolarity
+          - TIM2 Input Capture selection: TIM2_ICSelection
+          - TIM2 Input Capture Prescaler: TIM2_ICPSC
+          - TIM2 Input Capture filter value
+          or,
+          Call TIM2_PWMIConfig() to configure the desired channels with the 
+          corresponding configuration and to measure the frequency and the duty
+          cycle of the input signal.
+          
+       5. Enable global interrupts or the DMA to read the measured frequency. 
+          
+       6. Enable the corresponding interrupt (or DMA request) to read the captured value,
+          using the function TIM2_ITConfig(TIM2_IT_CCx) (or TIM2_DMACmd(TIM2_DMASource_CCx))
+       
+       7. Call the TIM2_Cmd(ENABLE) function to enable the TIM2 counter.
+       
+       8. Use TIM2_GetCapturex() to read the captured value corresponding to
+          channel x.
+       
+       Note1: All other functions can be used separately to modify, if needed,
+          a specific feature of the Timer. 
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the TIM2 peripheral according to the specified parameters.
+  * @param  TIM2_Channel: TIM2 Channel
+  *          This parameter can be one of the following values:
+  *            @arg TIM2_Channel_1: Channel 1
+  *            @arg TIM2_Channel_2: Channel 2     
+  * @param  TIM2_ICPolarity: Input Capture Polarity
+  *          This parameter can be one of the following values:
+  *            @arg TIM2_ICPolarity_Rising: Input Capture on Rising Edge
+  *            @arg TIM2_ICPolarity_Falling: Input Capture on Falling Edge  
+  * @param  TIM2_ICSelection: Input Capture Selection
+  *          This parameter can be one of the following values:
+  *            @arg TIM2_ICSelection_DirectTI: Input Capture mapped on the direct input
+  *            @arg TIM2_ICSelection_IndirectTI: Input Capture mapped on the indirect input
+  *            @arg TIM2_ICSelection_TRGI: Input Capture mapped on the Trigger Input   
+  * @param  TIM2_ICPrescaler: Input Capture Prescaler
+  *          This parameter can be one of the following values:
+  *            @arg TIM2_ICPSC_DIV1: Input Capture Prescaler = 1 (one capture every 1 event)
+  *            @arg TIM2_ICPSC_DIV2: Input Capture Prescaler = 2 (one capture every 2 events)
+  *            @arg TIM2_ICPSC_DIV4: Input Capture Prescaler = 4 (one capture every 4 events)
+  *            @arg TIM2_ICPSC_DIV8: Input Capture Prescaler = 8 (one capture every 8 events)   
+  * @param  TIM2_ICFilter: This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  */
+void TIM2_ICInit(TIM2_Channel_TypeDef TIM2_Channel,
+                 TIM2_ICPolarity_TypeDef TIM2_ICPolarity,
+                 TIM2_ICSelection_TypeDef TIM2_ICSelection,
+                 TIM2_ICPSC_TypeDef TIM2_ICPrescaler,
+                 uint8_t TIM2_ICFilter)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM2_CHANNEL(TIM2_Channel));
+
+  if (TIM2_Channel == TIM2_Channel_1)
+  {
+    /* TI1 Configuration */
+    TI1_Config(TIM2_ICPolarity, TIM2_ICSelection, TIM2_ICFilter);
+
+    /* Set the Input Capture Prescaler value */
+    TIM2_SetIC1Prescaler(TIM2_ICPrescaler);
+  }
+  else /* if (TIM2_Channel == TIM2_Channel_2) */
+  {
+    /* TI2 Configuration */
+    TI2_Config(TIM2_ICPolarity, TIM2_ICSelection, TIM2_ICFilter);
+
+    /* Set the Input Capture Prescaler value */
+    TIM2_SetIC2Prescaler(TIM2_ICPrescaler);
+  }
+}
+
+/**
+  * @brief  Configures the TIM2 peripheral in PWM Input Mode according to the
+  *         specified parameters.
+  * @param  TIM2_Channel: TIM2 Channel
+  *          This parameter can be one of the following values:
+  *            @arg TIM2_Channel_1: Channel 1
+  *            @arg TIM2_Channel_2: Channel 2     
+  * @param  TIM2_ICPolarity: Input Capture Polarity
+  *          This parameter can be one of the following values:
+  *            @arg TIM2_ICPolarity_Rising: Input Capture on Rising Edge
+  *            @arg TIM2_ICPolarity_Falling: Input Capture on Falling Edge  
+  * @param  TIM2_ICSelection: Input Capture Selection
+  *          This parameter can be one of the following values:
+  *            @arg TIM2_ICSelection_DirectTI: Input Capture mapped on the direct input
+  *            @arg TIM2_ICSelection_IndirectTI: Input Capture mapped on the indirect input
+  *            @arg TIM2_ICSelection_TRGI: Input Capture mapped on the Trigger Input   
+  * @param  TIM2_ICPrescaler: Input Capture Prescaler
+  *          This parameter can be one of the following values:
+  *            @arg TIM2_ICPSC_DIV1: Input Capture Prescaler = 1 (one capture every 1 event)
+  *            @arg TIM2_ICPSC_DIV2: Input Capture Prescaler = 2 (one capture every 2 events)
+  *            @arg TIM2_ICPSC_DIV4: Input Capture Prescaler = 4 (one capture every 4 events)
+  *            @arg TIM2_ICPSC_DIV8: Input Capture Prescaler = 8 (one capture every 8 events) 
+  * @retval None
+  */
+void TIM2_PWMIConfig(TIM2_Channel_TypeDef TIM2_Channel,
+                     TIM2_ICPolarity_TypeDef TIM2_ICPolarity,
+                     TIM2_ICSelection_TypeDef TIM2_ICSelection,
+                     TIM2_ICPSC_TypeDef TIM2_ICPrescaler,
+                     uint8_t TIM2_ICFilter)
+{
+  uint8_t icpolarity = TIM2_ICPolarity_Rising;
+  uint8_t icselection = TIM2_ICSelection_DirectTI;
+
+  /* Check the parameters */
+  assert_param(IS_TIM2_CHANNEL(TIM2_Channel));
+
+  /* Select the Opposite Input Polarity */
+  if (TIM2_ICPolarity == TIM2_ICPolarity_Rising)
+  {
+    icpolarity = TIM2_ICPolarity_Falling;
+  }
+  else
+  {
+    icpolarity = TIM2_ICPolarity_Rising;
+  }
+
+  /* Select the Opposite Input */
+  if (TIM2_ICSelection == TIM2_ICSelection_DirectTI)
+  {
+    icselection = TIM2_ICSelection_IndirectTI;
+  }
+  else
+  {
+    icselection = TIM2_ICSelection_DirectTI;
+  }
+
+  if (TIM2_Channel == TIM2_Channel_1)
+  {
+    /* TI1 Configuration */
+    TI1_Config(TIM2_ICPolarity, TIM2_ICSelection,
+               TIM2_ICFilter);
+
+    /* Set the Input Capture Prescaler value */
+    TIM2_SetIC1Prescaler(TIM2_ICPrescaler);
+
+    /* TI2 Configuration */
+    TI2_Config((TIM2_ICPolarity_TypeDef)icpolarity, (TIM2_ICSelection_TypeDef)icselection, TIM2_ICFilter);
+
+    /* Set the Input Capture Prescaler value */
+    TIM2_SetIC2Prescaler(TIM2_ICPrescaler);
+  }
+  else
+  {
+    /* TI2 Configuration */
+    TI2_Config(TIM2_ICPolarity, TIM2_ICSelection,
+               TIM2_ICFilter);
+
+    /* Set the Input Capture Prescaler value */
+    TIM2_SetIC2Prescaler(TIM2_ICPrescaler);
+
+    /* TI1 Configuration */
+    TI1_Config((TIM2_ICPolarity_TypeDef)icpolarity, (TIM2_ICSelection_TypeDef)icselection, TIM2_ICFilter);
+
+    /* Set the Input Capture Prescaler value */
+    TIM2_SetIC1Prescaler(TIM2_ICPrescaler);
+  }
+}
+
+/**
+  * @brief  Gets the TIM2 Input Capture 1 value.
+  * @param  None
+  * @retval Capture Compare 1 Register value.
+  */
+uint16_t TIM2_GetCapture1(void)
+{
+  uint16_t tmpccr1 = 0;
+  uint8_t tmpccr1l, tmpccr1h;
+
+  tmpccr1h = TIM2->CCR1H;
+  tmpccr1l = TIM2->CCR1L;
+
+  tmpccr1 = (uint16_t)(tmpccr1l);
+  tmpccr1 |= (uint16_t)((uint16_t)tmpccr1h << 8);
+  /* Get the Capture 1 Register value */
+  return ((uint16_t)tmpccr1);
+}
+
+/**
+  * @brief  Gets the TIM2 Input Capture 2 value.
+  * @param  None
+  * @retval Capture Compare 2 Register value.
+  */
+uint16_t TIM2_GetCapture2(void)
+{
+  uint16_t tmpccr2 = 0;
+  uint8_t tmpccr2l, tmpccr2h;
+
+  tmpccr2h = TIM2->CCR2H;
+  tmpccr2l = TIM2->CCR2L;
+
+  tmpccr2 = (uint16_t)(tmpccr2l);
+  tmpccr2 |= (uint16_t)((uint16_t)tmpccr2h << 8);
+  /* Get the Capture 2 Register value */
+  return ((uint16_t)tmpccr2);
+}
+
+/**
+  * @brief  Sets the TIM2 Input Capture 1 prescaler.
+  * @param  TIM2_IC1Prescaler: Specifies the Input Capture prescaler new value
+  *          This parameter can be one of the following values:
+  *            @arg TIM2_ICPSC_DIV1: Input Capture Prescaler = 1 (one capture every 1 event)
+  *            @arg TIM2_ICPSC_DIV2: Input Capture Prescaler = 2 (one capture every 2 events)
+  *            @arg TIM2_ICPSC_DIV4: Input Capture Prescaler = 4 (one capture every 4 events)
+  *            @arg TIM2_ICPSC_DIV8: Input Capture Prescaler = 8 (one capture every 8 events) 
+  * @retval None
+  */
+void TIM2_SetIC1Prescaler(TIM2_ICPSC_TypeDef TIM2_IC1Prescaler)
+{
+  uint8_t tmpccmr1 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM2_IC_PRESCALER(TIM2_IC1Prescaler));
+
+  tmpccmr1 = TIM2->CCMR1;
+
+  /* Reset the IC1PSC Bits */
+  tmpccmr1 &= (uint8_t)(~TIM_CCMR_ICxPSC);
+
+  /* Set the IC1PSC value */
+  tmpccmr1 |= (uint8_t)TIM2_IC1Prescaler;
+
+  TIM2->CCMR1 = tmpccmr1;
+}
+
+/**
+  * @brief  Sets the TIM2 Input Capture 2 prescaler.
+  * @param  TIM2_IC2Prescaler: Specifies the Input Capture prescaler new value
+  *          This parameter can be one of the following values:
+  *            @arg TIM2_ICPSC_DIV1: Input Capture Prescaler = 1 (one capture every 1 event)
+  *            @arg TIM2_ICPSC_DIV2: Input Capture Prescaler = 2 (one capture every 2 events)
+  *            @arg TIM2_ICPSC_DIV4: Input Capture Prescaler = 4 (one capture every 4 events)
+  *            @arg TIM2_ICPSC_DIV8: Input Capture Prescaler = 8 (one capture every 8 events) 
+  * @retval None
+  */
+void TIM2_SetIC2Prescaler(TIM2_ICPSC_TypeDef TIM2_IC2Prescaler)
+{
+  uint8_t tmpccmr2 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM2_IC_PRESCALER(TIM2_IC2Prescaler));
+
+  tmpccmr2 = TIM2->CCMR2;
+
+  /* Reset the IC2PSC Bits */
+  tmpccmr2 &= (uint8_t)(~TIM_CCMR_ICxPSC);
+
+  /* Set the IC2PSC value */
+  tmpccmr2 |= (uint8_t)TIM2_IC2Prescaler;
+
+  TIM2->CCMR2 = tmpccmr2;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM2_Group4 Interrupts DMA and flags management functions
+ *  @brief    Interrupts, DMA and flags management functions 
+ *
+@verbatim   
+ ===============================================================================
+                 Interrupts, DMA and flags management functions
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the specified TIM2 interrupts.
+  * @param  TIM2_IT: Specifies the TIM2 interrupts sources to be enabled or disabled.
+  *          This parameter can be any combination of the following values:
+  *            @arg TIM2_IT_Update: Update
+  *            @arg TIM2_IT_CC1: Capture Compare Channel1
+  *            @arg TIM2_IT_CC2: Capture Compare Channel2 
+  *            @arg TIM2_IT_Trigger: Trigger 
+  *            @arg TIM2_IT_Break: Break  
+  * @param  NewState: The new state of the TIM2 peripheral.
+  *          This parameter can be ENABLE or DISABLE
+  * @retval None
+  */
+void TIM2_ITConfig(TIM2_IT_TypeDef TIM2_IT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM2_IT(TIM2_IT));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the Interrupt sources */
+    TIM2->IER |= (uint8_t)TIM2_IT;
+  }
+  else
+  {
+    /* Disable the Interrupt sources */
+    TIM2->IER &= (uint8_t)(~(uint8_t)TIM2_IT);
+  }
+}
+
+/**
+  * @brief  Configures the TIM2 event to be generated by software.
+  * @param  TIM2_EventSource: Specifies the event source.
+  *          This parameter can be any combination of the following values:
+  *            @arg TIM2_EventSource_Update: Update
+  *            @arg TIM2_EventSource_CC1: Capture Compare Channel1
+  *            @arg TIM2_EventSource_CC2: Capture Compare Channel2 
+  *            @arg TIM2_EventSource_Trigger: Trigger 
+  *            @arg TIM2_EventSource_Break: Break  
+  * @retval None
+  */
+void TIM2_GenerateEvent(TIM2_EventSource_TypeDef TIM2_EventSource)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM2_EVENT_SOURCE((uint8_t)TIM2_EventSource));
+
+  /* Set the event sources */
+  TIM2->EGR |= (uint8_t)TIM2_EventSource;
+}
+
+/**
+  * @brief  Checks whether the specified TIM2 flag is set or not.
+  * @param  TIM2_FLAG: Specifies the flag to check.
+  *          This parameter can be any combination of the following values:
+  *            @arg TIM2_FLAG_Update: Update
+  *            @arg TIM2_FLAG_CC1: Capture Compare Channel1
+  *            @arg TIM2_FLAG_CC2: Capture Compare Channel2 
+  *            @arg TIM2_FLAG_Trigger: Trigger 
+  *            @arg TIM2_FLAG_Break: Break  
+  *            @arg TIM2_FLAG_CC1OF: Capture compare 1 over capture
+  *            @arg TIM2_FLAG_CC2OF: Capture compare 2 over capture   
+  * @retval FlagStatus: The new state of TIM2_FLAG (SET or RESET)
+  */
+FlagStatus TIM2_GetFlagStatus(TIM2_FLAG_TypeDef TIM2_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  uint8_t tim2_flag_l = 0, tim2_flag_h = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM2_GET_FLAG(TIM2_FLAG));
+
+  tim2_flag_l = (uint8_t)(TIM2->SR1 & (uint8_t)(TIM2_FLAG));
+  tim2_flag_h = (uint8_t)(TIM2->SR2 & (uint8_t)((uint16_t)TIM2_FLAG >> 8));
+
+  if ((uint8_t)(tim2_flag_l | tim2_flag_h) != 0)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return ((FlagStatus)bitstatus);
+}
+
+/**
+  * @brief  Clears the TIM’s pending flags.
+  * @param  TIM2_FLAG: Specifies the flag to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg TIM2_FLAG_Update: Update
+  *            @arg TIM2_FLAG_CC1: Capture Compare Channel1
+  *            @arg TIM2_FLAG_CC2: Capture Compare Channel2 
+  *            @arg TIM2_FLAG_Trigger: Trigger 
+  *            @arg TIM2_FLAG_Break: Break  
+  * @retval None
+  */
+void TIM2_ClearFlag(TIM2_FLAG_TypeDef TIM2_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM2_CLEAR_FLAG((uint16_t)TIM2_FLAG));
+  /* Clear the flags (rc_w0) clear this bit by writing 0. Writing ‘1’ has no effect*/
+  TIM2->SR1 = (uint8_t)(~(uint8_t)(TIM2_FLAG));
+  TIM2->SR2 = (uint8_t)(~(uint8_t)((uint16_t)TIM2_FLAG >> 8));
+}
+
+/**
+  * @brief  Checks whether the TIM2 interrupt has occurred or not.
+  * @param  TIM2_IT: Specifies the TIM2 interrupt source to check.
+  *          This parameter can be any combination of the following values:
+  *            @arg TIM2_IT_Update: Update
+  *            @arg TIM2_IT_CC1: Capture Compare Channel1
+  *            @arg TIM2_IT_CC2: Capture Compare Channel2 
+  *            @arg TIM2_IT_Trigger: Trigger 
+  *            @arg TIM2_IT_Break: Break  
+  * @retval ITStatus: The new state of the TIM2_IT (SET or RESET)
+  */
+ITStatus TIM2_GetITStatus(TIM2_IT_TypeDef TIM2_IT)
+{
+  ITStatus bitstatus = RESET;
+
+  uint8_t TIM2_itStatus = 0x0, TIM2_itEnable = 0x0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM2_GET_IT(TIM2_IT));
+
+  TIM2_itStatus = (uint8_t)(TIM2->SR1 & (uint8_t)TIM2_IT);
+
+  TIM2_itEnable = (uint8_t)(TIM2->IER & (uint8_t)TIM2_IT);
+
+  if ((TIM2_itStatus != (uint8_t)RESET ) && (TIM2_itEnable != (uint8_t)RESET))
+  {
+    bitstatus = (ITStatus)SET;
+  }
+  else
+  {
+    bitstatus = (ITStatus)RESET;
+  }
+  return ((ITStatus)bitstatus);
+}
+
+/**
+  * @brief  Clears the TIM's interrupt pending bits.
+  * @param  TIM2_IT: Specifies the pending bit to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg TIM2_IT_Update: Update
+  *            @arg TIM2_IT_CC1: Capture Compare Channel1
+  *            @arg TIM2_IT_CC2: Capture Compare Channel2 
+  *            @arg TIM2_IT_Trigger: Trigger 
+  *            @arg TIM2_IT_Break: Break  
+  * @retval None
+  */
+void TIM2_ClearITPendingBit(TIM2_IT_TypeDef TIM2_IT)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM2_IT(TIM2_IT));
+
+  /* Clear the IT pending Bit */
+  TIM2->SR1 = (uint8_t)(~(uint8_t)TIM2_IT);
+}
+
+/**
+  * @brief  Enables or disables the TIM2 DMA Requests.
+  * @param  TIM2_DMASource: specifies the DMA Request sources.
+  *          This parameter can be any combination of the following values:
+  *            @arg TIM2_DMASource_Update: TIM2 DMA Update Request
+  *            @arg TIM2_DMASource_CC1: TIM2 DMA CC1 Request
+  *            @arg TIM2_DMASource_CC2: TIM2 DMA CC2 Request 
+  * @param  NewState: new state of the DMA Request sources.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM2_DMACmd( TIM2_DMASource_TypeDef TIM2_DMASource, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  assert_param(IS_TIM2_DMA_SOURCE(TIM2_DMASource));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the DMA sources */
+    TIM2->DER |= TIM2_DMASource;
+  }
+  else
+  {
+    /* Disable the DMA sources */
+    TIM2->DER &= (uint8_t)(~TIM2_DMASource);
+  }
+}
+
+/**
+  * @brief  Selects the TIM2 peripheral Capture Compare DMA source.
+  * @param   NewState: new state of the Capture Compare DMA source.
+  *           This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM2_SelectCCDMA(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Set the CCDS Bit */
+    TIM2->CR2 |= TIM_CR2_CCDS;
+  }
+  else
+  {
+    /* Reset the CCDS Bit */
+    TIM2->CR2 &= (uint8_t)(~TIM_CR2_CCDS);
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM2_Group5 Clocks management functions
+ *  @brief    Clocks management functions
+ *
+@verbatim   
+ ===============================================================================
+                         Clocks management functions
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables the TIM2 internal Clock.
+  * @par Parameters:
+  * None
+  * @retval None
+  */
+void TIM2_InternalClockConfig(void)
+{
+  /* Disable slave mode to clock the prescaler directly with the internal clock */
+  TIM2->SMCR &=  (uint8_t)(~TIM_SMCR_SMS);
+}
+
+/**
+  * @brief  Configures the TIM2 Trigger as External Clock.
+  * @param  TIM2_TIxExternalCLKSource: Specifies Trigger source.
+  *          This parameter can be one of the following values:
+  *            @arg TIM2_TIxExternalCLK1Source_TI1ED: External Clock mode 1 source = TI1ED
+  *            @arg TIM2_TIxExternalCLK1Source_TI1: External Clock mode 1 source = TI1 
+  *            @arg TIM2_TIxExternalCLK1Source_TI2: External Clock mode 1 source = TI2  
+  * @param  TIM2_ICPolarity: Specifies the TIx Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM2_ICPolarity_Rising: Input Capture on Rising Edge
+  *            @arg TIM2_ICPolarity_Falling: Input Capture on Falling Edge  
+  * @param  ICFilter: Specifies the filter value.
+  *          This parameter must be a value between 0x00 and 0x0F
+  * @retval None
+  */
+void TIM2_TIxExternalClockConfig(TIM2_TIxExternalCLK1Source_TypeDef TIM2_TIxExternalCLKSource,
+                                 TIM2_ICPolarity_TypeDef TIM2_ICPolarity,
+                                 uint8_t ICFilter)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM2_TIXCLK_SOURCE(TIM2_TIxExternalCLKSource));
+  assert_param(IS_TIM2_IC_POLARITY(TIM2_ICPolarity));
+  assert_param(IS_TIM2_IC_FILTER(ICFilter));
+
+  /* Configure the TIM2 Input Clock Source */
+  if (TIM2_TIxExternalCLKSource == TIM2_TIxExternalCLK1Source_TI2)
+  {
+    TI2_Config(TIM2_ICPolarity, TIM2_ICSelection_DirectTI, ICFilter);
+  }
+  else
+  {
+    TI1_Config(TIM2_ICPolarity, TIM2_ICSelection_DirectTI, ICFilter);
+  }
+
+  /* Select the Trigger source */
+  TIM2_SelectInputTrigger((TIM2_TRGSelection_TypeDef)TIM2_TIxExternalCLKSource);
+
+  /* Select the External clock mode1 */
+  TIM2->SMCR |= (uint8_t)(TIM2_SlaveMode_External1);
+}
+
+/**
+  * @brief  Configures the TIM2 External clock Mode1.
+  * @param  TIM2_ExtTRGPrescaler: Specifies the external Trigger Prescaler.
+  *          This parameter can be one of the following values:
+  *            @arg TIM2_ExtTRGPSC_OFF: No External Trigger prescaler
+  *            @arg TIM2_ExtTRGPSC_DIV2: External Trigger prescaler = 2 (ETRP frequency divided by 2)
+  *            @arg TIM2_ExtTRGPSC_DIV4: External Trigger prescaler = 4 (ETRP frequency divided by 4) 
+  *            @arg TIM2_ExtTRGPSC_DIV8: External Trigger prescaler = 8 (ETRP frequency divided by 8)   
+  * @param  TIM2_ExtTRGPolarity: Specifies the external Trigger Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM2_ExtTRGPolarity_Inverted: External Trigger Polarity = inverted
+  *            @arg TIM2_ExtTRGPolarity_NonInverted: External Trigger Polarity = non inverted
+  * @param  ExtTRGFilter: Specifies the External Trigger Filter.
+  *          This parameter must be a value between 0x00 and 0x0F
+  * @retval None
+  */
+void TIM2_ETRClockMode1Config(TIM2_ExtTRGPSC_TypeDef TIM2_ExtTRGPrescaler,
+                              TIM2_ExtTRGPolarity_TypeDef TIM2_ExtTRGPolarity,
+                              uint8_t ExtTRGFilter)
+{
+  /* Configure the ETR Clock source */
+  TIM2_ETRConfig(TIM2_ExtTRGPrescaler, TIM2_ExtTRGPolarity, ExtTRGFilter);
+
+  /* Select the External clock mode1 */
+  TIM2->SMCR &= (uint8_t)(~TIM_SMCR_SMS);
+  TIM2->SMCR |= (uint8_t)(TIM2_SlaveMode_External1);
+
+  /* Select the Trigger selection: ETRF */
+  TIM2->SMCR &= (uint8_t)(~TIM_SMCR_TS);
+  TIM2->SMCR |= (uint8_t)((TIM2_TRGSelection_TypeDef)TIM2_TRGSelection_ETRF);
+}
+
+/**
+  * @brief  Configures the TIM2 External clock Mode2.
+  * @param  TIM2_ExtTRGPrescaler: Specifies the external Trigger Prescaler.
+  *          This parameter can be one of the following values:
+  *            @arg TIM2_ExtTRGPSC_OFF: No External Trigger prescaler
+  *            @arg TIM2_ExtTRGPSC_DIV2: External Trigger prescaler = 2 (ETRP frequency divided by 2)
+  *            @arg TIM2_ExtTRGPSC_DIV4: External Trigger prescaler = 4 (ETRP frequency divided by 4) 
+  *            @arg TIM2_ExtTRGPSC_DIV8: External Trigger prescaler = 8 (ETRP frequency divided by 8) 
+  * @param  TIM2_ExtTRGPolarity: Specifies the external Trigger Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM2_ExtTRGPolarity_Inverted: External Trigger Polarity = inverted
+  *            @arg TIM2_ExtTRGPolarity_NonInverted: External Trigger Polarity = non inverted
+  * @param  ExtTRGFilter: Specifies the External Trigger Filter.
+  *          This parameter must be a value between 0x00 and 0x0F
+  * @retval None
+  */
+void TIM2_ETRClockMode2Config(TIM2_ExtTRGPSC_TypeDef TIM2_ExtTRGPrescaler,
+                              TIM2_ExtTRGPolarity_TypeDef TIM2_ExtTRGPolarity,
+                              uint8_t ExtTRGFilter)
+{
+  /* Configure the ETR Clock source */
+  TIM2_ETRConfig(TIM2_ExtTRGPrescaler, TIM2_ExtTRGPolarity, ExtTRGFilter);
+
+  /* Enable the External clock mode2 */
+  TIM2->ETR |= TIM_ETR_ECE ;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM2_Group6 Synchronization management functions
+ *  @brief    Synchronization management functions 
+ *
+@verbatim   
+ ===============================================================================
+                       Synchronization management functions
+ ===============================================================================  
+                   
+       ===================================================================      
+              TIM2 Driver: how to use it in synchronization Mode
+       =================================================================== 
+       Case of two/several Timers
+       **************************
+       1. If TIM2 is used as master to other timers use the following functions:
+          - TIM2_SelectOutputTrigger()
+          - TIM2_SelectMasterSlaveMode()
+       2. If TIM2 is used as slave to other timers use the following functions:
+          - TIM2_SelectInputTrigger()
+          - TIM2_SelectSlaveMode()
+          
+       Case of Timers and external trigger (TRIG pin)
+       ********************************************       
+       1. Configure the External trigger using TIM2_ETRConfig()
+       2. Configure the Slave Timer using the following functions:
+          - TIM2_SelectInputTrigger()
+          - TIM2_SelectSlaveMode()
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Selects the TIM2 Input Trigger source.
+  * @param  TIM2_InputTriggerSource: Specifies Input Trigger source.
+  *          This parameter can be one of the following values:
+  *            @arg TIM2_TRGSelection_TIM4: TRIG Input source =  TIM TRIG Output
+  *            @arg TIM2_TRGSelection_TIM1: TRIG Input source =  TIM TRIG Output
+  *            @arg TIM2_TRGSelection_TIM2: TRIG Input source =  TIM TRIG Output
+  *            @arg TIM2_TRGSelection_TIM2: TRIG Input source =  TIM TRIG Output
+  *            @arg TIM2_TRGSelection_TI1F_ED: TRIG Input source = TI1F_ED (TI1 Edge Detector)
+  *            @arg TIM2_TRGSelection_TI1FP1: TRIG Input source = TI1FP1 (Filtred Timer Input 1)
+  *            @arg TIM2_TRGSelection_TI2FP2: TRIG Input source = TI2FP2 (Filtred Timer Input 2)
+  *            @arg TIM2_TRGSelection_ETRF: TRIG Input source =  ETRF (External Trigger Input )      
+  * @retval None
+  */
+void TIM2_SelectInputTrigger(TIM2_TRGSelection_TypeDef TIM2_InputTriggerSource)
+{
+  uint8_t tmpsmcr = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM2_TRIGGER_SELECTION(TIM2_InputTriggerSource));
+
+  tmpsmcr = TIM2->SMCR;
+
+  /* Select the Trigger Source */
+  tmpsmcr &= (uint8_t)(~TIM_SMCR_TS);
+  tmpsmcr |= (uint8_t)TIM2_InputTriggerSource;
+
+  TIM2->SMCR = (uint8_t)tmpsmcr;
+}
+
+/**
+  * @brief  Selects the TIM2 Trigger Output Mode.
+  * @param  TIM2_TRGOSource: Specifies the Trigger Output source.
+  *          This parameter can be one of the following values:
+  *            @arg TIM2_TRGOSource_Reset: Trigger Output source = Reset 
+  *            @arg TIM2_TRGOSource_Enable: Trigger Output source = TIM2 is enabled 
+  *            @arg TIM2_TRGOSource_Update: Trigger Output source = Update event
+  *            @arg TIM2_TRGOSource_OC1: Trigger Output source = output compare channel1
+  *            @arg TIM2_TRGOSource_OC1REF: Trigger Output source = output compare channel 1 reference
+  *            @arg TIM2_TRGOSource_OC2REF: Trigger Output source = output compare channel 2 reference   
+  * @retval None
+  */
+void TIM2_SelectOutputTrigger(TIM2_TRGOSource_TypeDef TIM2_TRGOSource)
+{
+  uint8_t tmpcr2 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM2_TRGO_SOURCE(TIM2_TRGOSource));
+
+  tmpcr2 = TIM2->CR2;
+
+  /* Reset the MMS Bits */
+  tmpcr2 &= (uint8_t)(~TIM_CR2_MMS);
+
+  /* Select the TRGO source */
+  tmpcr2 |=  (uint8_t)TIM2_TRGOSource;
+
+  TIM2->CR2 = tmpcr2;
+}
+
+/**
+  * @brief  Selects the TIM2 Slave Mode.
+  * @param  TIM2_SlaveMode: Specifies the TIM2 Slave Mode.
+  *          This parameter can be one of the following values:
+  *            @arg TIM2_SlaveMode_Reset: Slave Mode Selection  = Reset
+  *            @arg TIM2_SlaveMode_Gated: Slave Mode Selection  = Gated
+  *            @arg TIM2_SlaveMode_Trigger: Slave Mode Selection  = Trigger
+  *            @arg TIM2_SlaveMode_External1: Slave Mode Selection  = External 1  
+  * @retval None
+  */
+void TIM2_SelectSlaveMode(TIM2_SlaveMode_TypeDef TIM2_SlaveMode)
+{
+  uint8_t tmpsmcr = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM2_SLAVE_MODE(TIM2_SlaveMode));
+
+  tmpsmcr = TIM2->SMCR;
+
+  /* Reset the SMS Bits */
+  tmpsmcr &= (uint8_t)(~TIM_SMCR_SMS);
+
+  /* Select the Slave Mode */
+  tmpsmcr |= (uint8_t)TIM2_SlaveMode;
+
+  TIM2->SMCR = tmpsmcr;
+}
+
+/**
+  * @brief  Sets or Resets the TIM2 Master/Slave Mode.
+  * @param  NewState: The new state of the synchronization between TIM2 and its slaves (through TRGO).
+  *          This parameter can be ENABLE or DISABLE
+  * @retval None
+  */
+void TIM2_SelectMasterSlaveMode(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Set or Reset the MSM Bit */
+  if (NewState != DISABLE)
+  {
+    TIM2->SMCR |= TIM_SMCR_MSM;
+  }
+  else
+  {
+    TIM2->SMCR &= (uint8_t)(~TIM_SMCR_MSM);
+  }
+}
+
+/**
+  * @brief  Configures the TIM2 External Trigger.
+  * @param  TIM2_ExtTRGPrescaler: Specifies the external Trigger Prescaler.
+  *          This parameter can be one of the following values:
+  *            @arg TIM2_ExtTRGPSC_OFF: No External Trigger prescaler
+  *            @arg TIM2_ExtTRGPSC_DIV2: External Trigger prescaler = 2 (ETRP frequency divided by 2)
+  *            @arg TIM2_ExtTRGPSC_DIV4: External Trigger prescaler = 4 (ETRP frequency divided by 4)
+  *            @arg TIM2_ExtTRGPSC_DIV8: External Trigger prescaler = 8 (ETRP frequency divided by 8)    
+  * @param  TIM2_ExtTRGPolarity: Specifies the external Trigger Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM2_ExtTRGPolarity_Inverted: External Trigger Polarity = inverted
+  *            @arg TIM2_ExtTRGPolarity_NonInverted: External Trigger Polarity = non inverted
+  * @param  ExtTRGFilter: Specifies the External Trigger Filter.
+  *          This parameter must be a value between 0x00 and 0x0F
+  * @retval None
+  */
+void TIM2_ETRConfig(TIM2_ExtTRGPSC_TypeDef TIM2_ExtTRGPrescaler,
+                    TIM2_ExtTRGPolarity_TypeDef TIM2_ExtTRGPolarity,
+                    uint8_t ExtTRGFilter)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM2_EXT_PRESCALER(TIM2_ExtTRGPrescaler));
+  assert_param(IS_TIM2_EXT_POLARITY(TIM2_ExtTRGPolarity));
+  assert_param(IS_TIM2_EXT_FILTER(ExtTRGFilter));
+
+  /* Set the Prescaler, the Filter value and the Polarity */
+  TIM2->ETR |= (uint8_t)((uint8_t)((uint8_t)TIM2_ExtTRGPrescaler | (uint8_t)TIM2_ExtTRGPolarity)
+                         | (uint8_t)ExtTRGFilter);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM2_Group7 Specific interface management functions
+ *  @brief    Specific interface management functions 
+ *
+@verbatim   
+ ===============================================================================
+                    Specific interface management functions
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures the TIM2 Encoder Interface.
+  * @param  TIM2_EncoderMode: Specifies the TIM2 Encoder Mode.
+  *          This parameter can be one of the following values:
+  *            @arg TIM2_EncoderMode_TI1: Encoder mode 1
+  *            @arg TIM2_EncoderMode_TI2: Encoder mode 2
+  *            @arg TIM2_EncoderMode_TI12: Encoder mode 3   
+  * @param  TIM2_IC1Polarity: Specifies the IC1 Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM2_ICPolarity_Rising: Input Capture on Rising Edge
+  *            @arg TIM2_ICPolarity_Falling: Input Capture on Falling Edge  
+  * @param  TIM2_IC2Polarity: Specifies the IC2 Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM2_ICPolarity_Rising: Input Capture on Rising Edge
+  *            @arg TIM2_ICPolarity_Falling: Input Capture on Falling Edge  
+  * @retval None
+  */
+void TIM2_EncoderInterfaceConfig(TIM2_EncoderMode_TypeDef TIM2_EncoderMode,
+                                 TIM2_ICPolarity_TypeDef TIM2_IC1Polarity,
+                                 TIM2_ICPolarity_TypeDef TIM2_IC2Polarity)
+{
+  uint8_t tmpsmcr = 0;
+  uint8_t tmpccmr1 = 0;
+  uint8_t tmpccmr2 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM2_ENCODER_MODE(TIM2_EncoderMode));
+  assert_param(IS_TIM2_IC_POLARITY(TIM2_IC1Polarity));
+  assert_param(IS_TIM2_IC_POLARITY(TIM2_IC2Polarity));
+
+  tmpsmcr = TIM2->SMCR;
+  tmpccmr1 = TIM2->CCMR1;
+  tmpccmr2 = TIM2->CCMR2;
+
+  /* Set the encoder Mode */
+  tmpsmcr &= (uint8_t)(TIM_SMCR_MSM | TIM_SMCR_TS)  ;
+  tmpsmcr |= (uint8_t)TIM2_EncoderMode;
+
+  /* Select the Capture Compare 1 and the Capture Compare 2 as input */
+  tmpccmr1 &= (uint8_t)(~TIM_CCMR_CCxS);
+  tmpccmr2 &= (uint8_t)(~TIM_CCMR_CCxS);
+  tmpccmr1 |= TIM_CCMR_TIxDirect_Set;
+  tmpccmr2 |= TIM_CCMR_TIxDirect_Set;
+
+  /* Set the TI1 and the TI2 Polarities */
+  if (TIM2_IC1Polarity == TIM2_ICPolarity_Falling)
+  {
+    TIM2->CCER1 |= TIM_CCER1_CC1P ;
+  }
+  else
+  {
+    TIM2->CCER1 &= (uint8_t)(~TIM_CCER1_CC1P) ;
+  }
+
+  if (TIM2_IC2Polarity == TIM2_ICPolarity_Falling)
+  {
+    TIM2->CCER1 |= TIM_CCER1_CC2P ;
+  }
+  else
+  {
+    TIM2->CCER1 &= (uint8_t)(~TIM_CCER1_CC2P) ;
+  }
+
+  TIM2->SMCR = tmpsmcr;
+  TIM2->CCMR1 = tmpccmr1;
+  TIM2->CCMR2 = tmpccmr2;
+}
+
+/**
+  * @brief  Enables or Disables the TIM’s Hall sensor interface.
+  * @param  NewState: The new state of the TIM2 Hall sensor interface.
+  *          This parameter can be ENABLE or DISABLE
+  * @retval None
+  */
+void TIM2_SelectHallSensor(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Set or Reset the TI1S Bit */
+  if (NewState != DISABLE)
+  {
+    TIM2->CR2 |= TIM_CR2_TI1S;
+  }
+  else
+  {
+    TIM2->CR2 &= (uint8_t)(~TIM_CR2_TI1S);
+  }
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @brief  Configure the TI1 as Input.
+  * @param  TIM2_ICPolarity: Input Capture Polarity
+  *          This parameter can be one of the following values:
+  *            @arg TIM2_ICPolarity_Rising: Input Capture on Rising Edge
+  *            @arg TIM2_ICPolarity_Falling: Input Capture on Falling Edge  
+  * @param  TIM2_ICSelection: Specifies the input to be used.
+  *          This parameter can be one of the following values:
+  *            @arg TIM2_ICSelection_DirectTI: Input Capture mapped on the direct input
+  *            @arg TIM2_ICSelection_IndirectTI: Input Capture mapped on the indirect input
+  *            @arg TIM2_ICSelection_TRGI: Input Capture mapped on the Trigger Input   
+  * @param  TIM2_ICFilter: Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  */
+static void TI1_Config(TIM2_ICPolarity_TypeDef TIM2_ICPolarity, \
+                       TIM2_ICSelection_TypeDef TIM2_ICSelection, \
+                       uint8_t TIM2_ICFilter)
+{
+  uint8_t tmpccmr1 = 0;
+  uint8_t tmpicpolarity = TIM2_ICPolarity;
+  tmpccmr1 = TIM2->CCMR1;
+
+  /* Check the parameters */
+  assert_param(IS_TIM2_IC_POLARITY(TIM2_ICPolarity));
+  assert_param(IS_TIM2_IC_SELECTION(TIM2_ICSelection));
+  assert_param(IS_TIM2_IC_FILTER(TIM2_ICFilter));
+
+  /* Disable the Channel 1: Reset the CCE Bit */
+  TIM2->CCER1 &=  (uint8_t)(~TIM_CCER1_CC1E);
+
+  /* Select the Input and set the filter */
+  tmpccmr1 &= (uint8_t)(~TIM_CCMR_CCxS) & (uint8_t)(~TIM_CCMR_ICxF);
+  tmpccmr1 |= (uint8_t)(((uint8_t)(TIM2_ICSelection)) | ((uint8_t)(TIM2_ICFilter << 4)));
+
+  TIM2->CCMR1 = tmpccmr1;
+
+  /* Select the Polarity */
+  if (tmpicpolarity == (uint8_t)(TIM2_ICPolarity_Falling))
+  {
+    TIM2->CCER1 |= TIM_CCER1_CC1P;
+  }
+  else
+  {
+    TIM2->CCER1 &= (uint8_t)(~TIM_CCER1_CC1P);
+  }
+
+  /* Set the CCE Bit */
+  TIM2->CCER1 |=  TIM_CCER1_CC1E;
+}
+
+/**
+  * @brief  Configure the TI2 as Input.
+  * @param  TIM2_ICPolarity: Input Capture Polarity
+  *          This parameter can be one of the following values:
+  *            @arg TIM2_ICPolarity_Rising: Input Capture on Rising Edge
+  *            @arg TIM2_ICPolarity_Falling: Input Capture on Falling Edge  
+  * @param  TIM2_ICSelection: Specifies the input to be used.
+  *          This parameter can be one of the following values:
+  *            @arg TIM2_ICSelection_DirectTI: Input Capture mapped on the direct input
+  *            @arg TIM2_ICSelection_IndirectTI: Input Capture mapped on the indirect input
+  *            @arg TIM2_ICSelection_TRGI: Input Capture mapped on the Trigger Input   
+  * @param  TIM2_ICFilter: Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  */
+static void TI2_Config(TIM2_ICPolarity_TypeDef TIM2_ICPolarity,
+                       TIM2_ICSelection_TypeDef TIM2_ICSelection,
+                       uint8_t TIM2_ICFilter)
+{
+  uint8_t tmpccmr2 = 0;
+  uint8_t tmpicpolarity = TIM2_ICPolarity;
+
+  /* Check the parameters */
+  assert_param(IS_TIM2_IC_POLARITY(TIM2_ICPolarity));
+  assert_param(IS_TIM2_IC_SELECTION(TIM2_ICSelection));
+  assert_param(IS_TIM2_IC_FILTER(TIM2_ICFilter));
+
+  tmpccmr2 = TIM2->CCMR2;
+
+  /* Disable the Channel 2: Reset the CCE Bit */
+  TIM2->CCER1 &=  (uint8_t)(~TIM_CCER1_CC2E);
+
+  /* Select the Input and set the filter */
+  tmpccmr2 &= (uint8_t)(~TIM_CCMR_CCxS) & (uint8_t)(~TIM_CCMR_ICxF);
+  tmpccmr2 |= (uint8_t)(((uint8_t)(TIM2_ICSelection)) | ((uint8_t)(TIM2_ICFilter << 4)));
+
+  TIM2->CCMR2 = tmpccmr2;
+
+  /* Select the Polarity */
+  if (tmpicpolarity == TIM2_ICPolarity_Falling)
+  {
+    TIM2->CCER1 |= TIM_CCER1_CC2P ;
+  }
+  else
+  {
+    TIM2->CCER1 &= (uint8_t)(~TIM_CCER1_CC2P) ;
+  }
+
+  /* Set the CCE Bit */
+  TIM2->CCER1 |=  TIM_CCER1_CC2E;
+}
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+  
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_tim3.c b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_tim3.c
new file mode 100755
index 0000000..0e12a04
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_tim3.c
@@ -0,0 +1,2151 @@
+/**
+  ******************************************************************************
+  * @file    stm8l15x_tim3.c
+  * @author  MCD Application Team
+  * @version V1.6.0
+  * @date    28-June-2013
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the TIM3 peripheral:
+  *            - TimeBase management
+  *            - Output Compare management
+  *            - Input Capture management
+  *            - Interrupts, DMA and flags management
+  *            - Clocks management
+  *            - Synchronization management
+  *            - Specific interface management
+  *              
+  *  @verbatim
+  *  
+  *          ===================================================================
+  *                                 How to use this driver
+  *          ===================================================================
+  *          This driver provides functions to configure and initialise the TIM3
+  *          peripheral
+  *          These functions are split in 7 groups: 
+  *   
+  *          1. TIM3 TimeBase management: this group includes all needed functions 
+  *             to configure the TIM Timebase unit:
+  *                   - Set/Get Prescaler
+  *                   - Set/Get Autoreload  
+  *                   - Counter modes configuration
+  *                   - Select the One Pulse mode
+  *                   - Update Request Configuration
+  *                   - Update Disable Configuration
+  *                   - Auto-Preload Configuration 
+  *                   - Enable/Disable the counter
+  *                 
+  *          2. TIM3 Output Compare management: this group includes all needed 
+  *             functions to configure the Capture/Compare unit used in Output 
+  *             compare mode: 
+  *                   - Configure each channel, independently, in Output Compare mode
+  *                   - Select the output compare modes
+  *                   - Select the Polarities of each channel
+  *                   - Set/Get the Capture/Compare register values
+  *                   - Select the Output Compare Fast mode 
+  *                   - Select the Output Compare Forced mode  
+  *                   - Output Compare-Preload Configuration 
+  *                   - Enable/Disable the Capture/Compare Channels    
+  *                   
+  *          3. TIM3 Input Capture management: this group includes all needed 
+  *             functions to configure the Capture/Compare unit used in 
+  *             Input Capture mode:
+  *                   - Configure each channel in input capture mode
+  *                   - Configure Channel1/2 in PWM Input mode
+  *                   - Set the Input Capture Prescaler
+  *                   - Get the Capture/Compare values      
+  *        
+  *          4. TIM3 interrupts, DMA and flags management
+  *                   - Enable/Disable interrupt sources
+  *                   - Get flags status
+  *                   - Clear flags/ Pending bits
+  *                   - Enable/Disable DMA requests 
+  *                   - Select CaptureCompare DMA request  
+  *              
+  *          5. TIM3 clocks management: this group includes all needed functions 
+  *             to configure the clock controller unit:
+  *                   - Select internal/External clock
+  *                   - Select the external clock mode: ETR(Mode1/Mode2) or TIx
+  *         
+  *          6. TIM3 synchronization management: this group includes all needed 
+  *             functions to configure the Synchronization unit:
+  *                   - Select Input Trigger  
+  *                   - Select Output Trigger  
+  *                   - Select Master Slave Mode 
+  *                   - ETR Configuration when used as external trigger   
+  *     
+  *          7. TIM3 specific interface management, this group includes all 
+  *             needed functions to use the specific TIM3 interface:
+  *                   - Encoder Interface Configuration
+  *                   - Select Hall Sensor        
+  *   
+  *  @endverbatim
+  *    
+  ******************************************************************************
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ****************************************************************************** 
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm8l15x_TIM3.h"
+
+/** @addtogroup STM8L15x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup TIM3 
+  * @brief TIM3 driver modules
+  * @{
+  */
+  
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void TI1_Config(TIM3_ICPolarity_TypeDef TIM3_ICPolarity,
+                       TIM3_ICSelection_TypeDef TIM3_ICSelection,
+                       uint8_t TIM3_ICFilter);
+static void TI2_Config(TIM3_ICPolarity_TypeDef TIM3_ICPolarity,
+                       TIM3_ICSelection_TypeDef TIM3_ICSelection,
+                       uint8_t TIM3_ICFilter);
+
+
+/** @defgroup TIM3_Private_Functions
+  * @{
+  */
+
+/** @defgroup TIM3_Group1 TimeBase management functions
+ *  @brief   TimeBase management functions 
+ *
+@verbatim   
+ ===============================================================================
+                       TimeBase management functions
+ ===============================================================================  
+  
+       ===================================================================      
+              TIM3 Driver: how to use it in Timing(Time base) Mode
+       =================================================================== 
+       To use the Timer in Timing(Time base) mode, the following steps are mandatory:
+       
+       1. Enable TIM3 clock using CLK_PeripheralClockConfig(CLK_Peripheral_TIM3, ENABLE) function.
+        
+       2. Call TIM3_TimeBaseInit() to configure the Time Base unit with the
+          corresponding configuration.
+          
+       3. Enable global interrupts if you need to generate the update interrupt.
+          
+       4. Enable the corresponding interrupt using the function TIM3_ITConfig(TIM3_IT_Update) 
+          
+       5. Call the TIM3_Cmd(ENABLE) function to enable the TIM3 counter.
+       
+       Note1: All other functions can be used separately to modify, if needed,
+          a specific feature of the Timer. 
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitialize the TIM3 peripheral registers to their default reset values.
+  * @param  None
+  * @retval None
+  */
+void TIM3_DeInit(void)
+{
+  TIM3->CR1 = TIM_CR1_RESET_VALUE;
+  TIM3->CR2 = TIM_CR2_RESET_VALUE;
+  TIM3->SMCR = TIM_SMCR_RESET_VALUE;
+  TIM3->ETR = TIM_ETR_RESET_VALUE;
+  TIM3->IER = TIM_IER_RESET_VALUE;
+  TIM3->SR2 = TIM_SR2_RESET_VALUE;
+
+  /* Disable channels */
+  TIM3->CCER1 = TIM_CCER1_RESET_VALUE;
+  /* Configure channels as inputs: it is necessary if lock level is equal to 2 or 3 */
+  TIM3->CCMR1 = 0x01;/*TIM3_ICxSource_TIxFPx */
+  TIM3->CCMR2 = 0x01;/*TIM3_ICxSource_TIxFPx */
+
+  /* Then reset channel registers: it also works if lock level is equal to 2 or 3 */
+  TIM3->CCER1 = TIM_CCER1_RESET_VALUE;
+  TIM3->CCMR1 = TIM_CCMR1_RESET_VALUE;
+  TIM3->CCMR2 = TIM_CCMR2_RESET_VALUE;
+
+  TIM3->CNTRH = TIM_CNTRH_RESET_VALUE;
+  TIM3->CNTRL = TIM_CNTRL_RESET_VALUE;
+
+  TIM3->PSCR = TIM_PSCR_RESET_VALUE;
+
+  TIM3->ARRH = TIM_ARRH_RESET_VALUE;
+  TIM3->ARRL = TIM_ARRL_RESET_VALUE;
+
+  TIM3->CCR1H = TIM_CCR1H_RESET_VALUE;
+  TIM3->CCR1L = TIM_CCR1L_RESET_VALUE;
+  TIM3->CCR2H = TIM_CCR2H_RESET_VALUE;
+  TIM3->CCR2L = TIM_CCR2L_RESET_VALUE;
+
+
+  TIM3->OISR = TIM_OISR_RESET_VALUE;
+  TIM3->EGR = 0x01;/* TIM_EGR_UG */
+  TIM3->BKR = TIM_BKR_RESET_VALUE;
+  TIM3->SR1 = TIM_SR1_RESET_VALUE;
+}
+
+/**
+  * @brief  Initializes the TIM3 Time Base Unit according to the specified  parameters.
+  * @param  TIM3_Prescaler: Prescaler 
+  *          This parameter can be one of the following values:
+  *            @arg TIM3_Prescaler_1: Time base Prescaler = 1 (No effect)
+  *            @arg TIM3_Prescaler_2: Time base Prescaler = 2
+  *            @arg TIM3_Prescaler_4: Time base Prescaler = 4
+  *            @arg TIM3_Prescaler_8: Time base Prescaler = 8
+  *            @arg TIM3_Prescaler_16: Time base Prescaler = 16
+  *            @arg TIM3_Prescaler_32: Time base Prescaler = 32
+  *            @arg TIM3_Prescaler_64: Time base Prescaler = 64
+  *            @arg TIM3_Prescaler_128: Time base Prescaler = 128                            
+  * @param  TIM3_CounterMode: Counter mode
+  *          This parameter can be one of the following values:
+  *            @arg TIM3_CounterMode_Up: Counter Up Mode
+  *            @arg TIM3_CounterMode_Down: Counter Down Mode
+  *            @arg TIM3_CounterMode_CenterAligned1: Counter Central aligned Mode 1
+  *            @arg TIM3_CounterMode_CenterAligned2: Counter Central aligned Mode 2
+  *            @arg TIM3_CounterMode_CenterAligned3: Counter Central aligned Mode 3        
+  * @param  TIM3_Period: This parameter must be a value between 0x0000 and 0xFFFF.
+  * @retval None
+  */
+
+void TIM3_TimeBaseInit(TIM3_Prescaler_TypeDef TIM3_Prescaler,
+                       TIM3_CounterMode_TypeDef TIM3_CounterMode,
+                       uint16_t TIM3_Period)
+{
+
+  assert_param(IS_TIM3_PRESCALER(TIM3_Prescaler));
+  assert_param(IS_TIM3_COUNTER_MODE(TIM3_CounterMode));
+
+
+
+  /* Set the Autoreload value */
+  TIM3->ARRH = (uint8_t)(TIM3_Period >> 8) ;
+  TIM3->ARRL = (uint8_t)(TIM3_Period);
+
+  /* Set the Prescaler value */
+  TIM3->PSCR = (uint8_t)(TIM3_Prescaler);
+
+  /* Select the Counter Mode */
+  TIM3->CR1 &= (uint8_t)((uint8_t)(~TIM_CR1_CMS)) & ((uint8_t)(~TIM_CR1_DIR));
+  TIM3->CR1 |= (uint8_t)(TIM3_CounterMode);
+
+  /* Generate an update event to reload the Prescaler value immediately */
+  TIM3->EGR = TIM3_EventSource_Update;
+}
+
+/**
+  * @brief  Configures the TIM3 Prescaler.
+  * @param  Prescaler: Specifies the Prescaler Register value
+  *          This parameter can be one of the following values:
+  *            @arg TIM3_Prescaler_1: Time base Prescaler = 1 (No effect)
+  *            @arg TIM3_Prescaler_2: Time base Prescaler = 2
+  *            @arg TIM3_Prescaler_4: Time base Prescaler = 4
+  *            @arg TIM3_Prescaler_8: Time base Prescaler = 8
+  *            @arg TIM3_Prescaler_16: Time base Prescaler = 16
+  *            @arg TIM3_Prescaler_32: Time base Prescaler = 32
+  *            @arg TIM3_Prescaler_64: Time base Prescaler = 64
+  *            @arg TIM3_Prescaler_128: Time base Prescaler = 128  
+  * @param  TIM3_PSCReloadMode: Specifies the TIM3 Prescaler Reload mode.
+  *          This parameter can be one of the following values:
+  *            @arg TIM3_PSCReloadMode_Update: Prescaler value is reloaded at every update
+  *            @arg TIM3_PSCReloadMode_Immediate: Prescaler value is reloaded at every update  
+  * @retval None
+  */
+void TIM3_PrescalerConfig(TIM3_Prescaler_TypeDef Prescaler,
+                          TIM3_PSCReloadMode_TypeDef TIM3_PSCReloadMode)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM3_PRESCALER(Prescaler));
+  assert_param(IS_TIM3_PRESCALER_RELOAD(TIM3_PSCReloadMode));
+
+  /* Set the Prescaler value */
+  TIM3->PSCR = (uint8_t)(Prescaler);
+
+  /* Set or reset the UG Bit */
+  if (TIM3_PSCReloadMode == TIM3_PSCReloadMode_Immediate)
+  {
+    TIM3->EGR |= TIM_EGR_UG ;
+  }
+  else
+  {
+    TIM3->EGR &= (uint8_t)(~TIM_EGR_UG) ;
+  }
+}
+
+/**
+  * @brief  Specifies the TIM3 Counter Mode to be used.
+  * @param  TIM3_CounterMode: Specifies the Counter Mode to be used
+  *          This parameter can be one of the following values:
+  *            @arg TIM3_CounterMode_Up: Counter Up Mode
+  *            @arg TIM3_CounterMode_Down: Counter Down Mode
+  *            @arg TIM3_CounterMode_CenterAligned1: Counter Central aligned Mode 1
+  *            @arg TIM3_CounterMode_CenterAligned2: Counter Central aligned Mode 2
+  *            @arg TIM3_CounterMode_CenterAligned3: Counter Central aligned Mode 3      
+  * @retval None
+  */
+void TIM3_CounterModeConfig(TIM3_CounterMode_TypeDef TIM3_CounterMode)
+{
+  uint8_t tmpcr1 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM3_COUNTER_MODE(TIM3_CounterMode));
+
+  tmpcr1 = TIM3->CR1;
+
+  /* Reset the CMS and DIR Bits */
+  tmpcr1 &= (uint8_t)((uint8_t)(~TIM_CR1_CMS) & (uint8_t)(~TIM_CR1_DIR));
+
+  /* Set the Counter Mode */
+  tmpcr1 |= (uint8_t)TIM3_CounterMode;
+
+  TIM3->CR1 = tmpcr1;
+}
+
+/**
+  * @brief  Sets the TIM3 Counter Register value.
+  * @param  Counter: Specifies the Counter register new value.
+  *          This parameter is between 0x0000 and 0xFFFF.
+  * @retval None
+  */
+void TIM3_SetCounter(uint16_t Counter)
+{
+
+  /* Set the Counter Register value */
+  TIM3->CNTRH = (uint8_t)(Counter >> 8);
+  TIM3->CNTRL = (uint8_t)(Counter);
+}
+
+/**
+  * @brief  Sets the TIM3 Autoreload Register value.
+  * @param  Autoreload: Specifies the Autoreload register new value.
+  *          This parameter is between 0x0000 and 0xFFFF.
+  * @retval None
+  */
+void TIM3_SetAutoreload(uint16_t Autoreload)
+{
+  /* Set the Autoreload Register value */
+  TIM3->ARRH = (uint8_t)(Autoreload >> 8);
+  TIM3->ARRL = (uint8_t)(Autoreload);
+}
+
+/**
+  * @brief  Gets the TIM3 Counter value.
+  * @param  None
+  * @retval Counter Register value.
+  */
+uint16_t TIM3_GetCounter(void)
+{
+  uint16_t tmpcnt = 0;
+  uint8_t tmpcntrl, tmpcntrh;
+
+  tmpcntrh = TIM3->CNTRH;
+  tmpcntrl = TIM3->CNTRL;
+
+  tmpcnt = (uint16_t)(tmpcntrl);
+  tmpcnt |= (uint16_t)((uint16_t)tmpcntrh << 8);
+  /* Get the Counter Register value */
+  return ((uint16_t)tmpcnt);
+}
+
+/**
+  * @brief  Gets the TIM3 Prescaler value.
+  * @param  None
+  * @retval TIM3 Prescaler, it can be one of the following values:
+  *            - TIM3_Prescaler_1: Time base Prescaler = 1 (No effect)
+  *            - TIM3_Prescaler_2: Time base Prescaler = 2
+  *            - TIM3_Prescaler_4: Time base Prescaler = 4
+  *            - TIM3_Prescaler_8: Time base Prescaler = 8
+  *            - TIM3_Prescaler_16: Time base Prescaler = 16
+  *            - TIM3_Prescaler_32: Time base Prescaler = 32
+  *            - TIM3_Prescaler_64: Time base Prescaler = 64
+  *            - TIM3_Prescaler_128: Time base Prescaler = 128    
+  */
+TIM3_Prescaler_TypeDef TIM3_GetPrescaler(void)
+{
+  /* Get the Prescaler Register value */
+  return ((TIM3_Prescaler_TypeDef)TIM3->PSCR);
+}
+
+/**
+  * @brief  Enables or Disables the TIM3 Update event.
+  * @param  NewState: The new state of the TIM3 peripheral Preload register.
+  *          This parameter can be ENABLE or DISABLE
+  * @retval None
+  */
+
+void TIM3_UpdateDisableConfig(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Set or Reset the UDIS Bit */
+  if (NewState != DISABLE)
+  {
+    TIM3->CR1 |= TIM_CR1_UDIS;
+  }
+  else
+  {
+    TIM3->CR1 &= (uint8_t)(~TIM_CR1_UDIS);
+  }
+}
+
+/**
+  * @brief  Selects the TIM3 Update Request Interrupt source.
+  * @param  TIM3_UpdateSource: Specifies the Update source.
+  *          This parameter can be one of the following values:
+  *            @arg TIM3_UpdateSource_Global: Global Update request source
+  *            @arg TIM3_UpdateSource_Regular: Regular Update request source 
+  * @retval None
+  */
+void TIM3_UpdateRequestConfig(TIM3_UpdateSource_TypeDef TIM3_UpdateSource)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM3_UPDATE_SOURCE(TIM3_UpdateSource));
+
+  /* Set or Reset the URS Bit */
+  if (TIM3_UpdateSource == TIM3_UpdateSource_Regular)
+  {
+    TIM3->CR1 |= TIM_CR1_URS ;
+  }
+  else
+  {
+    TIM3->CR1 &= (uint8_t)(~TIM_CR1_URS);
+  }
+}
+
+/**
+  * @brief  Enables or disables TIM3 peripheral Preload register on ARR.
+  * @param  NewState: The new state of the TIM3 peripheral Preload register.
+  *          This parameter can be ENABLE or DISABLE
+  * @retval None
+  */
+void TIM3_ARRPreloadConfig(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Set or Reset the ARPE Bit */
+  if (NewState != DISABLE)
+  {
+    TIM3->CR1 |= TIM_CR1_ARPE;
+  }
+  else
+  {
+    TIM3->CR1 &= (uint8_t)(~TIM_CR1_ARPE);
+  }
+}
+
+/**
+  * @brief  Selects the TIM’s One Pulse Mode.
+  * @param  TIM3_OPMode: Specifies the OPM Mode to be used.
+  *          This parameter can be one of the following values:
+  *            @arg TIM3_OPMode_Single: Single one Pulse mode (OPM Active)
+  *            @arg TIM3_OPMode_Repetitive: Single one Pulse mode (OPM Active)  
+  * @retval None
+  */
+void TIM3_SelectOnePulseMode(TIM3_OPMode_TypeDef TIM3_OPMode)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM3_OPM_MODE(TIM3_OPMode));
+
+  /* Set or Reset the OPM Bit */
+  if (TIM3_OPMode == TIM3_OPMode_Single)
+  {
+    TIM3->CR1 |= TIM_CR1_OPM ;
+  }
+  else
+  {
+    TIM3->CR1 &= (uint8_t)(~TIM_CR1_OPM);
+  }
+}
+
+/**
+  * @brief  Enables or disables the TIM3 peripheral.
+  * @param  NewState: The new state of the TIM3 peripheral.
+  *          This parameter can be ENABLE or DISABLE
+  * @retval None
+  */
+void TIM3_Cmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* set or Reset the CEN Bit */
+  if (NewState != DISABLE)
+  {
+    TIM3->CR1 |= TIM_CR1_CEN;
+  }
+  else
+  {
+    TIM3->CR1 &= (uint8_t)(~TIM_CR1_CEN);
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM3_Group2 Output Compare management functions
+ *  @brief    Output Compare management functions 
+ *
+@verbatim   
+ ===============================================================================
+                        Output Compare management functions
+ ===============================================================================  
+   
+       ===================================================================      
+              TIM3 Driver: how to use it in Output Compare Mode
+       =================================================================== 
+       To use the Timer in Output Compare mode, the following steps are mandatory:
+       
+       1. Enable TIM3 clock using CLK_PeripheralClockConfig(CLK_Peripheral_TIM3, ENABLE) function.
+       
+       2. Configure the TIM3 pins in output mode by configuring the corresponding GPIO pins
+          
+       3. Configure the Time base unit as described in the first part of this driver, if needed,
+          otherwise the Timer will run with the default configuration:
+          - Autoreload value = 0xFFFF
+          - Prescaler value = 0x0000
+          - Counter mode = Up counting
+      
+       4. Call TIM3_OCxInit() to configure the channel x with the desired parameters
+          including:
+          - TIM3 Output Compare mode: TIM3_OCMode
+          - TIM3 Output State: TIM3_OutputState
+          - TIM3 Pulse value: TIM3_Pulse
+          - TIM3 Output Compare Polarity: TIM3_OCPolarity
+          - TIM3 Output Idle State: TIM3_OCIdleState
+       
+       5. Call the TIM3_Cmd(ENABLE) function to enable the TIM3 counter.
+       
+       Note1: All other functions can be used separately to modify, if needed,
+          a specific feature of the Timer. 
+       
+       Note2: If the corresponding interrupt or DMA request are needed, the user should:
+              1. Enable global interrupts (or the DMA) to use the TIM3 interrupts (or DMA requests). 
+              2. Enable the corresponding interrupt (or DMA request) using the function 
+              TIM3_ITConfig(TIM3_IT_CCx) (or TIM3_DMACmd(TIM3_DMASource_CCx))   
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the TIM3 Channel1 according to the specified parameters.
+  * @param  TIM3_OCMode: Output Compare Mode 
+  *          This parameter can be one of the following values:
+  *            @arg TIM3_OCMode_Timing: Timing (Frozen) Mode
+  *            @arg TIM3_OCMode_Active: Active Mode
+  *            @arg TIM3_OCMode_Inactive: Inactive Mode
+  *            @arg TIM3_OCMode_Toggle: Toggle Mode
+  *            @arg TIM3_OCMode_PWM1: PWM Mode 1
+  *            @arg TIM3_OCMode_PWM2: PWM Mode 2          
+  * @param  TIM3_OutputState: Output state
+  *          This parameter can be one of the following values:
+  *            @arg TIM3_OutputState_Disable: Output compare State disabled (channel output disabled)
+  *            @arg TIM3_OutputState_Enable: Output compare State enabled (channel output enabled)
+  * @param  TIM3_Pulse: This parameter must be a value between 0x0000 and 0xFFFF.
+  * @param  TIM3_OCPolarity: Polarity
+  *          This parameter can be one of the following values:
+  *            @arg TIM3_OCPolarity_High: Output compare polarity  = High
+  *            @arg TIM3_OCPolarity_Low: Output compare polarity  = Low 
+  * @param  TIM3_OCIdleState: Output Compare Idle State
+  *          This parameter can be one of the following values:
+  *            @arg TIM3_OCIdleState_Reset: Output Compare Idle state  = Reset
+  *            @arg TIM3_OCIdleState_Set: Output Compare Idle state  = Set
+  * @retval None
+  */
+void TIM3_OC1Init(TIM3_OCMode_TypeDef TIM3_OCMode,
+                  TIM3_OutputState_TypeDef TIM3_OutputState,
+                  uint16_t TIM3_Pulse,
+                  TIM3_OCPolarity_TypeDef TIM3_OCPolarity,
+                  TIM3_OCIdleState_TypeDef TIM3_OCIdleState)
+{
+  uint8_t tmpccmr1 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM3_OC_MODE(TIM3_OCMode));
+  assert_param(IS_TIM3_OUTPUT_STATE(TIM3_OutputState));
+  assert_param(IS_TIM3_OC_POLARITY(TIM3_OCPolarity));
+  assert_param(IS_TIM3_OCIDLE_STATE(TIM3_OCIdleState));
+
+  tmpccmr1 = TIM3->CCMR1;
+
+  /* Disable the Channel 1: Reset the CCE Bit */
+  TIM3->CCER1 &= (uint8_t)(~TIM_CCER1_CC1E);
+  /* Reset the Output Compare Bits */
+  tmpccmr1 &= (uint8_t)(~TIM_CCMR_OCM);
+
+  /* Set the Output Compare Mode */
+  tmpccmr1 |= (uint8_t)TIM3_OCMode;
+
+  TIM3->CCMR1 = tmpccmr1;
+
+  /* Set the Output State */
+  if (TIM3_OutputState == TIM3_OutputState_Enable)
+  {
+    TIM3->CCER1 |= TIM_CCER1_CC1E;
+  }
+  else
+  {
+    TIM3->CCER1 &= (uint8_t)(~TIM_CCER1_CC1E);
+  }
+
+  /* Set the Output Polarity */
+  if (TIM3_OCPolarity == TIM3_OCPolarity_Low)
+  {
+    TIM3->CCER1 |= TIM_CCER1_CC1P;
+  }
+  else
+  {
+    TIM3->CCER1 &= (uint8_t)(~TIM_CCER1_CC1P);
+  }
+
+  /* Set the Output Idle state */
+  if (TIM3_OCIdleState == TIM3_OCIdleState_Set)
+  {
+    TIM3->OISR |= TIM_OISR_OIS1;
+  }
+  else
+  {
+    TIM3->OISR &= (uint8_t)(~TIM_OISR_OIS1);
+  }
+
+  /* Set the Pulse value */
+  TIM3->CCR1H = (uint8_t)(TIM3_Pulse >> 8);
+  TIM3->CCR1L = (uint8_t)(TIM3_Pulse);
+}
+
+/**
+  * @brief  Initializes the TIM3 Channel2 according to the specified parameters.
+  * @param  TIM3_OCMode: Output Compare Mode 
+  *          This parameter can be one of the following values:
+  *            @arg TIM3_OCMode_Timing: Timing (Frozen) Mode
+  *            @arg TIM3_OCMode_Active: Active Mode
+  *            @arg TIM3_OCMode_Inactive: Inactive Mode
+  *            @arg TIM3_OCMode_Toggle: Toggle Mode
+  *            @arg TIM3_OCMode_PWM1: PWM Mode 1
+  *            @arg TIM3_OCMode_PWM2: PWM Mode 2          
+  * @param  TIM3_OutputState: Output state
+  *          This parameter can be one of the following values:
+  *            @arg TIM3_OutputState_Disable: Output compare State disabled (channel output disabled)
+  *            @arg TIM3_OutputState_Enable: Output compare State enabled (channel output enabled)
+  * @param  TIM3_Pulse: This parameter must be a value between 0x0000 and 0xFFFF.
+  * @param  TIM3_OCPolarity: Polarity
+  *          This parameter can be one of the following values:
+  *            @arg TIM3_OCPolarity_High: Output compare polarity  = High
+  *            @arg TIM3_OCPolarity_Low: Output compare polarity  = Low 
+  * @param  TIM3_OCIdleState: Output Compare Idle State
+  *          This parameter can be one of the following values:
+  *            @arg TIM3_OCIdleState_Reset: Output Compare Idle state  = Reset
+  *            @arg TIM3_OCIdleState_Set: Output Compare Idle state  = Set
+  * @retval None
+  */
+void TIM3_OC2Init(TIM3_OCMode_TypeDef TIM3_OCMode,
+                  TIM3_OutputState_TypeDef TIM3_OutputState,
+                  uint16_t TIM3_Pulse,
+                  TIM3_OCPolarity_TypeDef TIM3_OCPolarity,
+                  TIM3_OCIdleState_TypeDef TIM3_OCIdleState)
+{
+  uint8_t tmpccmr2 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM3_OC_MODE(TIM3_OCMode));
+  assert_param(IS_TIM3_OUTPUT_STATE(TIM3_OutputState));
+  assert_param(IS_TIM3_OC_POLARITY(TIM3_OCPolarity));
+  assert_param(IS_TIM3_OCIDLE_STATE(TIM3_OCIdleState));
+
+  tmpccmr2 = TIM3->CCMR2;
+
+  /* Disable the Channel 2: Reset the CCE Bit */
+  TIM3->CCER1 &= (uint8_t)(~TIM_CCER1_CC2E);
+
+  /* Reset the Output Compare Bits */
+  tmpccmr2 &= (uint8_t)(~TIM_CCMR_OCM);
+
+  /* Set the Output Compare Mode */
+  tmpccmr2 |= (uint8_t)TIM3_OCMode;
+
+  TIM3->CCMR2 = tmpccmr2;
+
+  /* Set the Output State */
+  if (TIM3_OutputState == TIM3_OutputState_Enable)
+  {
+    TIM3->CCER1 |= TIM_CCER1_CC2E;
+  }
+  else
+  {
+    TIM3->CCER1 &= (uint8_t)(~TIM_CCER1_CC2E);
+  }
+
+  /* Set the Output Polarity */
+  if (TIM3_OCPolarity == TIM3_OCPolarity_Low)
+  {
+    TIM3->CCER1 |= TIM_CCER1_CC2P;
+  }
+  else
+  {
+    TIM3->CCER1 &= (uint8_t)(~TIM_CCER1_CC2P);
+  }
+
+
+  /* Set the Output Idle state */
+  if (TIM3_OCIdleState == TIM3_OCIdleState_Set)
+  {
+    TIM3->OISR |= TIM_OISR_OIS2;
+  }
+  else
+  {
+    TIM3->OISR &= (uint8_t)(~TIM_OISR_OIS2);
+  }
+
+  /* Set the Pulse value */
+  TIM3->CCR2H = (uint8_t)(TIM3_Pulse >> 8);
+  TIM3->CCR2L = (uint8_t)(TIM3_Pulse);
+}
+
+/**
+  * @brief  Configures the Break feature, dead time, Lock level, the OSSI,
+  *         and the AOE(automatic output enable).
+  * @param  TIM3_OSSIState: Off-State Selection for Idle mode states.
+  *          This parameter can be one of the following values:
+  *            @arg TIM3_OSSIState_Enable: Off-State Selection for Idle mode enabled
+  *            @arg TIM3_OSSIState_Disable: Off-State Selection for Idle mode disabled 
+  * @param  TIM3_LockLevel: Lock level.
+  *          This parameter can be one of the following values:
+  *            @arg TIM3_LockLevel_Off: Lock option disabled
+  *            @arg TIM3_LockLevel_1: Select Lock Level 1
+  *            @arg TIM3_LockLevel_2: Select Lock Level 2
+  *            @arg TIM3_LockLevel_3: Select Lock Level 3    
+  * @param  TIM3_BreakState: Break Input enable/disable .
+  *          This parameter can be one of the following values:
+  *            @arg TIM3_BreakState_Disable: Break State disabled (break option disabled)
+  *            @arg TIM3_BreakState_Enable: Break State enabled (break option enabled) 
+  * @param  TIM3_BreakPolarity: Break Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM3_BreakPolarity_High: if Break, channel polarity = High
+  *            @arg TIM3_BreakPolarity_Low: if Break, channel polarity = Low   
+  * @param  TIM3_AutomaticOutput: TIM3 AOE Bit Set/Reset .
+  *          This parameter can be one of the following values:
+  *            @arg TIM3_AutomaticOutput_Enable: Automatic Output option enabled
+  *            @arg TIM3_AutomaticOutput_Disable: Automatic Output option disabled
+  * @retval None
+  */
+void TIM3_BKRConfig(TIM3_OSSIState_TypeDef TIM3_OSSIState,
+                    TIM3_LockLevel_TypeDef TIM3_LockLevel,
+                    TIM3_BreakState_TypeDef TIM3_BreakState,
+                    TIM3_BreakPolarity_TypeDef TIM3_BreakPolarity,
+                    TIM3_AutomaticOutput_TypeDef TIM3_AutomaticOutput)
+
+{
+  /* Check the parameters */
+  assert_param(IS_TIM3_OSSI_STATE(TIM3_OSSIState));
+  assert_param(IS_TIM3_LOCK_LEVEL(TIM3_LockLevel));
+  assert_param(IS_TIM3_BREAK_STATE(TIM3_BreakState));
+  assert_param(IS_TIM3_BREAK_POLARITY(TIM3_BreakPolarity));
+  assert_param(IS_TIM3_AUTOMATIC_OUTPUT_STATE(TIM3_AutomaticOutput));
+
+
+
+  /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSI State,
+  the dead time value and the Automatic Output Enable Bit */
+  TIM3->BKR = (uint8_t)((uint8_t)((uint8_t)((uint8_t)((uint8_t)TIM3_OSSIState | (uint8_t)TIM3_LockLevel) | \
+                                  (uint8_t)((uint8_t)TIM3_BreakState | (uint8_t)TIM3_BreakPolarity)) | \
+                                  TIM3_AutomaticOutput));
+}
+
+/**
+  * @brief  Enables or disables the TIM3 peripheral Main Outputs.
+  * @param  NewState: The new state of the TIM3 peripheral.
+  *          This parameter can be ENABLE or DISABLE
+  * @retval None
+  */
+void TIM3_CtrlPWMOutputs(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Set or Reset the MOE Bit */
+
+  if (NewState != DISABLE)
+  {
+    TIM3->BKR |= TIM_BKR_MOE ;
+  }
+  else
+  {
+    TIM3->BKR &= (uint8_t)(~TIM_BKR_MOE) ;
+  }
+}
+
+/**
+  * @brief  Selects the TIM3 Output Compare Mode. This function disables the
+  *         selected channel before changing the Output Compare Mode. User has to
+  *         enable this channel using TIM3_CCxCmd and TIM3_CCxNCmd functions.
+  * @param  TIM3_Channel: Specifies the TIM3 Channel.
+  *          This parameter can be one of the following values:
+  *            @arg TIM3_Channel_1: Channel 1
+  *            @arg TIM3_Channel_2: Channel 2  
+  * @param  TIM3_OCMode: Specifies the TIM3 Output Compare Mode.
+  *          This parameter can be one of the following values:
+  *            @arg TIM3_OCMode_Timing: Timing (Frozen) Mode
+  *            @arg TIM3_OCMode_Active: Active Mode
+  *            @arg TIM3_OCMode_Inactive: Inactive Mode
+  *            @arg TIM3_OCMode_Toggle: Toggle Mode
+  *            @arg TIM3_OCMode_PWM1: PWM Mode 1
+  *            @arg TIM3_OCMode_PWM2: PWM Mode 2    
+  * @retval None
+  */
+void TIM3_SelectOCxM(TIM3_Channel_TypeDef TIM3_Channel,
+                     TIM3_OCMode_TypeDef TIM3_OCMode)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM3_CHANNEL(TIM3_Channel));
+  assert_param(IS_TIM3_OCM(TIM3_OCMode));
+
+  if (TIM3_Channel == TIM3_Channel_1)
+  {
+    /* Disable the Channel 1: Reset the CCE Bit */
+    TIM3->CCER1 &= (uint8_t)(~TIM_CCER1_CC1E);
+
+    /* Reset the Output Compare Bits */
+    TIM3->CCMR1 &= (uint8_t)(~TIM_CCMR_OCM);
+
+    /* Set the Output Compare Mode */
+    TIM3->CCMR1 |= (uint8_t)TIM3_OCMode;
+  }
+  else /* if (TIM3_Channel == TIM3_Channel_2) */
+  {
+    /* Disable the Channel 2: Reset the CCE Bit */
+    TIM3->CCER1 &= (uint8_t)(~TIM_CCER1_CC2E);
+
+    /* Reset the Output Compare Bits */
+    TIM3->CCMR2 &= (uint8_t)(~TIM_CCMR_OCM);
+
+    /* Set the Output Compare Mode */
+    TIM3->CCMR2 |= (uint8_t)TIM3_OCMode;
+  }
+}
+
+/**
+  * @brief  Sets the TIM3 Capture Compare1 Register value.
+  * @param  Compare: Specifies the Capture Compare1 register new value.
+  *         This parameter is between 0x0000 and 0xFFFF.
+  * @retval None
+  */
+void TIM3_SetCompare1(uint16_t Compare)
+{
+  /* Set the Capture Compare1 Register value */
+  TIM3->CCR1H = (uint8_t)(Compare >> 8);
+  TIM3->CCR1L = (uint8_t)(Compare);
+}
+
+/**
+  * @brief  Sets the TIM3 Capture Compare2 Register value.
+  * @param  Compare: Specifies the Capture Compare2 register new value.
+  *         This parameter is between 0x0000 and 0xFFFF.
+  * @retval None
+  */
+void TIM3_SetCompare2(uint16_t Compare)
+{
+  /* Set the Capture Compare2 Register value */
+  TIM3->CCR2H = (uint8_t)(Compare >> 8);
+  TIM3->CCR2L = (uint8_t)(Compare);
+}
+
+/**
+  * @brief  Forces the TIM3 Channel1 output waveform to active or inactive level.
+  * @param  TIM3_ForcedAction: Specifies the forced Action to be set to the output waveform.
+  *          This parameter can be one of the following values:
+  *            @arg TIM3_ForcedAction_Active: Output Reference is forced low 
+  *            @arg TIM3_ForcedAction_Inactive: Output Reference is forced high 
+  * @retval None
+  */
+void TIM3_ForcedOC1Config(TIM3_ForcedAction_TypeDef TIM3_ForcedAction)
+{
+  uint8_t tmpccmr1 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM3_FORCED_ACTION(TIM3_ForcedAction));
+
+  tmpccmr1 = TIM3->CCMR1;
+
+  /* Reset the OCM Bits */
+  tmpccmr1 &= (uint8_t)(~TIM_CCMR_OCM);
+
+  /* Configure The Forced output Mode */
+  tmpccmr1 |= (uint8_t)TIM3_ForcedAction;
+
+  TIM3->CCMR1 = tmpccmr1;
+}
+
+/**
+  * @brief  Forces the TIM3 Channel2 output waveform to active or inactive level.
+  * @param  TIM3_ForcedAction: Specifies the forced Action to be set to the output waveform.
+  *          This parameter can be one of the following values:
+  *            @arg TIM3_ForcedAction_Active: Output Reference is forced low 
+  *            @arg TIM3_ForcedAction_Inactive: Output Reference is forced high 
+  * @retval None
+  */
+void TIM3_ForcedOC2Config(TIM3_ForcedAction_TypeDef TIM3_ForcedAction)
+{
+  uint8_t tmpccmr2 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM3_FORCED_ACTION(TIM3_ForcedAction));
+
+  tmpccmr2 = TIM3->CCMR2;
+
+  /* Reset the OCM Bits */
+  tmpccmr2 &= (uint8_t)(~TIM_CCMR_OCM);
+
+  /* Configure The Forced output Mode */
+  tmpccmr2 |= (uint8_t)TIM3_ForcedAction;
+
+  TIM3->CCMR2 = tmpccmr2;
+}
+
+/**
+  * @brief  Enables or disables the TIM3 peripheral Preload Register on CCR1.
+  * @param  NewState: The new state of the Capture Compare Preload register.
+  *          This parameter can be ENABLE or DISABLE
+  * @retval None
+  */
+void TIM3_OC1PreloadConfig(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Set or Reset the OC1PE Bit */
+  if (NewState != DISABLE)
+  {
+    TIM3->CCMR1 |= TIM_CCMR_OCxPE ;
+  }
+  else
+  {
+    TIM3->CCMR1 &= (uint8_t)(~TIM_CCMR_OCxPE) ;
+  }
+}
+
+/**
+  * @brief  Enables or disables the TIM3 peripheral Preload Register on CCR2.
+  * @param  NewState: The new state of the Capture Compare Preload register.
+  *          This parameter can be ENABLE or DISABLE
+  * @retval None
+  */
+void TIM3_OC2PreloadConfig(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Set or Reset the OC2PE Bit */
+  if (NewState != DISABLE)
+  {
+    TIM3->CCMR2 |= TIM_CCMR_OCxPE ;
+  }
+  else
+  {
+    TIM3->CCMR2 &= (uint8_t)(~TIM_CCMR_OCxPE) ;
+  }
+}
+
+/**
+  * @brief  Configures the TIM3 Capture Compare 1 Fast feature.
+  * @param  NewState: The new state of the Output Compare Fast Enable bit.
+  *          This parameter can be ENABLE or DISABLE
+  * @retval None
+  */
+void TIM3_OC1FastConfig(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Set or Reset the OC1FE Bit */
+  if (NewState != DISABLE)
+  {
+    TIM3->CCMR1 |= TIM_CCMR_OCxFE ;
+  }
+  else
+  {
+    TIM3->CCMR1 &= (uint8_t)(~TIM_CCMR_OCxFE) ;
+  }
+}
+
+/**
+  * @brief  Configures the TIM3 Capture Compare 2 Fast feature.
+  * @param  NewState: The new state of the Output Compare Fast Enable bit.
+  *          This parameter can be ENABLE or DISABLE
+  * @retval None
+  */
+
+void TIM3_OC2FastConfig(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Set or Reset the OC2FE Bit */
+  if (NewState != DISABLE)
+  {
+    TIM3->CCMR2 |= TIM_CCMR_OCxFE ;
+  }
+  else
+  {
+    TIM3->CCMR2 &= (uint8_t)(~TIM_CCMR_OCxFE) ;
+  }
+}
+
+/**
+  * @brief  Configures the TIM3 Channel 1 polarity.
+  * @param  TIM3_OCPolarity: Specifies the OC1 Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM3_OCPolarity_High: Output compare polarity  = High
+  *            @arg TIM3_OCPolarity_Low: Output compare polarity  = Low 
+  * @retval None
+  */
+void TIM3_OC1PolarityConfig(TIM3_OCPolarity_TypeDef TIM3_OCPolarity)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM3_OC_POLARITY(TIM3_OCPolarity));
+
+  /* Set or Reset the CC1P Bit */
+  if (TIM3_OCPolarity == TIM3_OCPolarity_Low)
+  {
+    TIM3->CCER1 |= TIM_CCER1_CC1P ;
+  }
+  else
+  {
+    TIM3->CCER1 &= (uint8_t)(~TIM_CCER1_CC1P) ;
+  }
+}
+
+/**
+  * @brief  Configures the TIM3 Channel 2 polarity.
+  * @param  TIM3_OCPolarity: Specifies the OC2 Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM3_OCPolarity_High: Output compare polarity  = High
+  *            @arg TIM3_OCPolarity_Low: Output compare polarity  = Low 
+  * @retval None
+  */
+void TIM3_OC2PolarityConfig(TIM3_OCPolarity_TypeDef TIM3_OCPolarity)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM3_OC_POLARITY(TIM3_OCPolarity));
+
+  /* Set or Reset the CC2P Bit */
+  if (TIM3_OCPolarity == TIM3_OCPolarity_Low)
+  {
+    TIM3->CCER1 |= TIM_CCER1_CC2P ;
+  }
+  else
+  {
+    TIM3->CCER1 &= (uint8_t)(~TIM_CCER1_CC2P) ;
+  }
+}
+
+/**
+  * @brief  Enables or disables the TIM3 Capture Compare Channel x.
+  * @param  TIM3_Channel: Specifies the TIM3 Channel.
+  *          This parameter can be one of the following values:
+  *            @arg TIM3_Channel_1: Channel 1
+  *            @arg TIM3_Channel_2: Channel 2  
+  * @param  NewState: Specifies the TIM3 Channel CCxE bit new state.
+  *          This parameter can be ENABLE or DISABLE
+  * @retval None
+  */
+void TIM3_CCxCmd(TIM3_Channel_TypeDef TIM3_Channel,
+                 FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM3_CHANNEL(TIM3_Channel));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (TIM3_Channel == TIM3_Channel_1)
+  {
+    /* Set or Reset the CC1E Bit */
+    if (NewState != DISABLE)
+    {
+      TIM3->CCER1 |= TIM_CCER1_CC1E ;
+    }
+    else
+    {
+      TIM3->CCER1 &= (uint8_t)(~TIM_CCER1_CC1E) ;
+    }
+
+  }
+  else /* if (TIM3_Channel == TIM3_Channel_2) */
+  {
+    /* Set or Reset the CC2E Bit */
+    if (NewState != DISABLE)
+    {
+      TIM3->CCER1 |= TIM_CCER1_CC2E;
+    }
+    else
+    {
+      TIM3->CCER1 &= (uint8_t)(~TIM_CCER1_CC2E) ;
+    }
+  }
+}
+
+/** @defgroup TIM3_Group3 Input Capture management functions
+ *  @brief    Input Capture management functions 
+ *
+@verbatim   
+ ===============================================================================
+                      Input Capture management functions
+ ===============================================================================  
+   
+       ===================================================================      
+              TIM3 Driver: how to use it in Input Capture Mode
+       =================================================================== 
+       To use the Timer in Input Capture mode, the following steps are mandatory:
+       
+       1. Enable TIM3 clock using CLK_PeripheralClockConfig(CLK_Peripheral_TIM3, ENABLE) function.
+       
+       2. Configure the TIM3 pins in input mode by configuring the corresponding GPIO pins
+       
+       3. Configure the Time base unit as described in the first part of this driver, if needed,
+          otherwise the Timer will run with the default configuration:
+          - Autoreload value = 0xFFFF
+          - Prescaler value = 0x0
+          - Counter mode = Up counting
+       
+       4. Call TIM3_ICInit() to configure the desired channel to measure only 
+          frequency or duty cycle of the input signal using the corresponding configuration: 
+          - TIM3 Channel: TIM3_Channel
+          - TIM3 Input Capture polarity: TIM3_ICPolarity
+          - TIM3 Input Capture selection: TIM3_ICSelection
+          - TIM3 Input Capture Prescaler: TIM3_ICPSC
+          - TIM3 Input Capture filter value
+          or,
+          Call TIM3_PWMIConfig() to configure the desired channels with the 
+          corresponding configuration and to measure the frequency and the duty
+          cycle of the input signal.
+          
+       5. Enable global interrupts or the DMA to read the measured frequency. 
+          
+       6. Enable the corresponding interrupt (or DMA request) to read the captured value,
+          using the function TIM3_ITConfig(TIM3_IT_CCx) (or TIM3_DMACmd(TIM3_DMASource_CCx))
+       
+       7. Call the TIM3_Cmd(ENABLE) function to enable the TIM3 counter.
+       
+       8. Use TIM3_GetCapturex() to read the captured value corresponding to
+          channel x.
+       
+       Note1: All other functions can be used separately to modify, if needed,
+          a specific feature of the Timer. 
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the TIM3 peripheral according to the specified parameters.
+  * @param  TIM3_Channel: TIM3 Channel
+  *          This parameter can be one of the following values:
+  *            @arg TIM3_Channel_1: Channel 1
+  *            @arg TIM3_Channel_2: Channel 2     
+  * @param  TIM3_ICPolarity: Input Capture Polarity
+  *          This parameter can be one of the following values:
+  *            @arg TIM3_ICPolarity_Rising: Input Capture on Rising Edge
+  *            @arg TIM3_ICPolarity_Falling: Input Capture on Falling Edge  
+  * @param  TIM3_ICSelection: Input Capture Selection
+  *          This parameter can be one of the following values:
+  *            @arg TIM3_ICSelection_DirectTI: Input Capture mapped on the direct input
+  *            @arg TIM3_ICSelection_IndirectTI: Input Capture mapped on the indirect input
+  *            @arg TIM3_ICSelection_TRGI: Input Capture mapped on the Trigger Input   
+  * @param  TIM3_ICPrescaler: Input Capture Prescaler
+  *          This parameter can be one of the following values:
+  *            @arg TIM3_ICPSC_DIV1: Input Capture Prescaler = 1 (one capture every 1 event)
+  *            @arg TIM3_ICPSC_DIV2: Input Capture Prescaler = 2 (one capture every 2 events)
+  *            @arg TIM3_ICPSC_DIV4: Input Capture Prescaler = 4 (one capture every 4 events)
+  *            @arg TIM3_ICPSC_DIV8: Input Capture Prescaler = 8 (one capture every 8 events)   
+  * @param  TIM3_ICFilter: This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  */
+void TIM3_ICInit(TIM3_Channel_TypeDef TIM3_Channel,
+                 TIM3_ICPolarity_TypeDef TIM3_ICPolarity,
+                 TIM3_ICSelection_TypeDef TIM3_ICSelection,
+                 TIM3_ICPSC_TypeDef TIM3_ICPrescaler,
+                 uint8_t TIM3_ICFilter)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM3_CHANNEL(TIM3_Channel));
+
+  if (TIM3_Channel == TIM3_Channel_1)
+  {
+    /* TI1 Configuration */
+    TI1_Config(TIM3_ICPolarity, TIM3_ICSelection, TIM3_ICFilter);
+
+    /* Set the Input Capture Prescaler value */
+    TIM3_SetIC1Prescaler(TIM3_ICPrescaler);
+  }
+  else /* if (TIM3_Channel == TIM3_Channel_2) */
+  {
+    /* TI2 Configuration */
+    TI2_Config(TIM3_ICPolarity, TIM3_ICSelection, TIM3_ICFilter);
+
+    /* Set the Input Capture Prescaler value */
+    TIM3_SetIC2Prescaler(TIM3_ICPrescaler);
+  }
+}
+
+/**
+  * @brief  Configures the TIM3 peripheral in PWM Input Mode according to the
+  *         specified parameters.
+  * @param  TIM3_Channel: TIM3 Channel
+  *          This parameter can be one of the following values:
+  *            @arg TIM3_Channel_1: Channel 1
+  *            @arg TIM3_Channel_2: Channel 2     
+  * @param  TIM3_ICPolarity: Input Capture Polarity
+  *          This parameter can be one of the following values:
+  *            @arg TIM3_ICPolarity_Rising: Input Capture on Rising Edge
+  *            @arg TIM3_ICPolarity_Falling: Input Capture on Falling Edge  
+  * @param  TIM3_ICSelection: Input Capture Selection
+  *          This parameter can be one of the following values:
+  *            @arg TIM3_ICSelection_DirectTI: Input Capture mapped on the direct input
+  *            @arg TIM3_ICSelection_IndirectTI: Input Capture mapped on the indirect input
+  *            @arg TIM3_ICSelection_TRGI: Input Capture mapped on the Trigger Input   
+  * @param  TIM3_ICPrescaler: Input Capture Prescaler
+  *          This parameter can be one of the following values:
+  *            @arg TIM3_ICPSC_DIV1: Input Capture Prescaler = 1 (one capture every 1 event)
+  *            @arg TIM3_ICPSC_DIV2: Input Capture Prescaler = 2 (one capture every 2 events)
+  *            @arg TIM3_ICPSC_DIV4: Input Capture Prescaler = 4 (one capture every 4 events)
+  *            @arg TIM3_ICPSC_DIV8: Input Capture Prescaler = 8 (one capture every 8 events) 
+  * @retval None
+  */
+void TIM3_PWMIConfig(TIM3_Channel_TypeDef TIM3_Channel,
+                     TIM3_ICPolarity_TypeDef TIM3_ICPolarity,
+                     TIM3_ICSelection_TypeDef TIM3_ICSelection,
+                     TIM3_ICPSC_TypeDef TIM3_ICPrescaler,
+                     uint8_t TIM3_ICFilter)
+{
+  uint8_t icpolarity = TIM3_ICPolarity_Rising;
+  uint8_t icselection = TIM3_ICSelection_DirectTI;
+
+  /* Check the parameters */
+  assert_param(IS_TIM3_CHANNEL(TIM3_Channel));
+
+  /* Select the Opposite Input Polarity */
+  if (TIM3_ICPolarity == TIM3_ICPolarity_Rising)
+  {
+    icpolarity = TIM3_ICPolarity_Falling;
+  }
+  else
+  {
+    icpolarity = TIM3_ICPolarity_Rising;
+  }
+
+  /* Select the Opposite Input */
+  if (TIM3_ICSelection == TIM3_ICSelection_DirectTI)
+  {
+    icselection = TIM3_ICSelection_IndirectTI;
+  }
+  else
+  {
+    icselection = TIM3_ICSelection_DirectTI;
+  }
+
+  if (TIM3_Channel == TIM3_Channel_1)
+  {
+    /* TI1 Configuration */
+    TI1_Config(TIM3_ICPolarity, TIM3_ICSelection,
+               TIM3_ICFilter);
+
+    /* Set the Input Capture Prescaler value */
+    TIM3_SetIC1Prescaler(TIM3_ICPrescaler);
+
+    /* TI2 Configuration */
+    TI2_Config((TIM3_ICPolarity_TypeDef)icpolarity, (TIM3_ICSelection_TypeDef)icselection, TIM3_ICFilter);
+
+    /* Set the Input Capture Prescaler value */
+    TIM3_SetIC2Prescaler(TIM3_ICPrescaler);
+  }
+  else
+  {
+    /* TI2 Configuration */
+    TI2_Config(TIM3_ICPolarity, TIM3_ICSelection,
+               TIM3_ICFilter);
+
+    /* Set the Input Capture Prescaler value */
+    TIM3_SetIC2Prescaler(TIM3_ICPrescaler);
+
+    /* TI1 Configuration */
+    TI1_Config((TIM3_ICPolarity_TypeDef)icpolarity, (TIM3_ICSelection_TypeDef)icselection, TIM3_ICFilter);
+
+    /* Set the Input Capture Prescaler value */
+    TIM3_SetIC1Prescaler(TIM3_ICPrescaler);
+  }
+}
+
+/**
+  * @brief  Gets the TIM3 Input Capture 1 value.
+  * @param  None
+  * @retval Capture Compare 1 Register value.
+  */
+uint16_t TIM3_GetCapture1(void)
+{
+  uint16_t tmpccr1 = 0;
+  uint8_t tmpccr1l, tmpccr1h;
+
+  tmpccr1h = TIM3->CCR1H;
+  tmpccr1l = TIM3->CCR1L;
+
+  tmpccr1 = (uint16_t)(tmpccr1l);
+  tmpccr1 |= (uint16_t)((uint16_t)tmpccr1h << 8);
+  /* Get the Capture 1 Register value */
+  return ((uint16_t)tmpccr1);
+}
+
+/**
+  * @brief  Gets the TIM3 Input Capture 2 value.
+  * @param  None
+  * @retval Capture Compare 2 Register value.
+  */
+uint16_t TIM3_GetCapture2(void)
+{
+  uint16_t tmpccr2 = 0;
+  uint8_t tmpccr2l, tmpccr2h;
+
+  tmpccr2h = TIM3->CCR2H;
+  tmpccr2l = TIM3->CCR2L;
+
+  tmpccr2 = (uint16_t)(tmpccr2l);
+  tmpccr2 |= (uint16_t)((uint16_t)tmpccr2h << 8);
+  /* Get the Capture 2 Register value */
+  return ((uint16_t)tmpccr2);
+}
+
+/**
+  * @brief  Sets the TIM3 Input Capture 1 prescaler.
+  * @param  TIM3_IC1Prescaler: Specifies the Input Capture prescaler new value
+  *          This parameter can be one of the following values:
+  *            @arg TIM3_ICPSC_DIV1: Input Capture Prescaler = 1 (one capture every 1 event)
+  *            @arg TIM3_ICPSC_DIV2: Input Capture Prescaler = 2 (one capture every 2 events)
+  *            @arg TIM3_ICPSC_DIV4: Input Capture Prescaler = 4 (one capture every 4 events)
+  *            @arg TIM3_ICPSC_DIV8: Input Capture Prescaler = 8 (one capture every 8 events) 
+  * @retval None
+  */
+void TIM3_SetIC1Prescaler(TIM3_ICPSC_TypeDef TIM3_IC1Prescaler)
+{
+  uint8_t tmpccmr1 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM3_IC_PRESCALER(TIM3_IC1Prescaler));
+
+  tmpccmr1 = TIM3->CCMR1;
+
+  /* Reset the IC1PSC Bits */
+  tmpccmr1 &= (uint8_t)(~TIM_CCMR_ICxPSC);
+
+  /* Set the IC1PSC value */
+  tmpccmr1 |= (uint8_t)TIM3_IC1Prescaler;
+
+  TIM3->CCMR1 = tmpccmr1;
+}
+
+/**
+  * @brief  Sets the TIM3 Input Capture 2 prescaler.
+  * @param  TIM3_IC2Prescaler: Specifies the Input Capture prescaler new value
+  *          This parameter can be one of the following values:
+  *            @arg TIM3_ICPSC_DIV1: Input Capture Prescaler = 1 (one capture every 1 event)
+  *            @arg TIM3_ICPSC_DIV2: Input Capture Prescaler = 2 (one capture every 2 events)
+  *            @arg TIM3_ICPSC_DIV4: Input Capture Prescaler = 4 (one capture every 4 events)
+  *            @arg TIM3_ICPSC_DIV8: Input Capture Prescaler = 8 (one capture every 8 events) 
+  * @retval None
+  */
+void TIM3_SetIC2Prescaler(TIM3_ICPSC_TypeDef TIM3_IC2Prescaler)
+{
+  uint8_t tmpccmr2 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM3_IC_PRESCALER(TIM3_IC2Prescaler));
+
+  tmpccmr2 = TIM3->CCMR2;
+
+  /* Reset the IC2PSC Bits */
+  tmpccmr2 &= (uint8_t)(~TIM_CCMR_ICxPSC);
+
+  /* Set the IC2PSC value */
+  tmpccmr2 |= (uint8_t)TIM3_IC2Prescaler;
+
+  TIM3->CCMR2 = tmpccmr2;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM3_Group4 Interrupts DMA and flags management functions
+ *  @brief    Interrupts, DMA and flags management functions 
+ *
+@verbatim   
+ ===============================================================================
+                 Interrupts, DMA and flags management functions
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the specified TIM3 interrupts.
+  * @param  TIM3_IT: Specifies the TIM3 interrupts sources to be enabled or disabled.
+  *          This parameter can be any combination of the following values:
+  *            @arg TIM3_IT_Update: Update
+  *            @arg TIM3_IT_CC1: Capture Compare Channel1
+  *            @arg TIM3_IT_CC2: Capture Compare Channel2 
+  *            @arg TIM3_IT_Trigger: Trigger 
+  *            @arg TIM3_IT_Break: Break  
+  * @param  NewState: The new state of the TIM3 peripheral.
+  *          This parameter can be ENABLE or DISABLE
+  * @retval None
+  */
+void TIM3_ITConfig(TIM3_IT_TypeDef TIM3_IT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM3_IT(TIM3_IT));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the Interrupt sources */
+    TIM3->IER |= (uint8_t)TIM3_IT;
+  }
+  else
+  {
+    /* Disable the Interrupt sources */
+    TIM3->IER &= (uint8_t)(~(uint8_t)TIM3_IT);
+  }
+}
+
+/**
+  * @brief  Configures the TIM3 event to be generated by software.
+  * @param  TIM3_EventSource: Specifies the event source.
+  *          This parameter can be any combination of the following values:
+  *            @arg TIM3_EventSource_Update: Update
+  *            @arg TIM3_EventSource_CC1: Capture Compare Channel1
+  *            @arg TIM3_EventSource_CC2: Capture Compare Channel2 
+  *            @arg TIM3_EventSource_Trigger: Trigger 
+  *            @arg TIM3_EventSource_Break: Break  
+  * @retval None
+  */
+void TIM3_GenerateEvent(TIM3_EventSource_TypeDef TIM3_EventSource)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM3_EVENT_SOURCE((uint8_t)TIM3_EventSource));
+
+  /* Set the event sources */
+  TIM3->EGR |= (uint8_t)TIM3_EventSource;
+}
+
+/**
+  * @brief  Checks whether the specified TIM3 flag is set or not.
+  * @param  TIM3_FLAG: Specifies the flag to check.
+  *          This parameter can be any combination of the following values:
+  *            @arg TIM3_FLAG_Update: Update
+  *            @arg TIM3_FLAG_CC1: Capture Compare Channel1
+  *            @arg TIM3_FLAG_CC2: Capture Compare Channel2 
+  *            @arg TIM3_FLAG_Trigger: Trigger 
+  *            @arg TIM3_FLAG_Break: Break  
+  *            @arg TIM3_FLAG_CC1OF: Capture compare 1 over capture
+  *            @arg TIM3_FLAG_CC2OF: Capture compare 2 over capture   
+  * @retval FlagStatus: The new state of TIM3_FLAG (SET or RESET)
+  */
+FlagStatus TIM3_GetFlagStatus(TIM3_FLAG_TypeDef TIM3_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  uint8_t tim3_flag_l = 0, tim3_flag_h = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM3_GET_FLAG(TIM3_FLAG));
+
+  tim3_flag_l = (uint8_t)(TIM3->SR1 & (uint8_t)(TIM3_FLAG));
+  tim3_flag_h = (uint8_t)(TIM3->SR2 & (uint8_t)((uint16_t)TIM3_FLAG >> 8));
+
+  if ((uint8_t)(tim3_flag_l | tim3_flag_h) != 0)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return ((FlagStatus)bitstatus);
+}
+
+/**
+  * @brief  Clears the TIM’s pending flags.
+  * @param  TIM3_FLAG: Specifies the flag to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg TIM3_FLAG_Update: Update
+  *            @arg TIM3_FLAG_CC1: Capture Compare Channel1
+  *            @arg TIM3_FLAG_CC2: Capture Compare Channel2 
+  *            @arg TIM3_FLAG_Trigger: Trigger 
+  *            @arg TIM3_FLAG_Break: Break  
+  * @retval None
+  */
+void TIM3_ClearFlag(TIM3_FLAG_TypeDef TIM3_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM3_CLEAR_FLAG((uint16_t)TIM3_FLAG));
+  /* Clear the flags (rc_w0) clear this bit by writing 0. Writing ‘1’ has no effect*/
+  TIM3->SR1 = (uint8_t)(~(uint8_t)(TIM3_FLAG));
+  TIM3->SR2 = (uint8_t)(~(uint8_t)((uint16_t)TIM3_FLAG >> 8));
+}
+
+/**
+  * @brief  Checks whether the TIM3 interrupt has occurred or not.
+  * @param  TIM3_IT: Specifies the TIM3 interrupt source to check.
+  *          This parameter can be any combination of the following values:
+  *            @arg TIM3_IT_Update: Update
+  *            @arg TIM3_IT_CC1: Capture Compare Channel1
+  *            @arg TIM3_IT_CC2: Capture Compare Channel2 
+  *            @arg TIM3_IT_Trigger: Trigger 
+  *            @arg TIM3_IT_Break: Break  
+  * @retval ITStatus: The new state of the TIM3_IT (SET or RESET)
+  */
+ITStatus TIM3_GetITStatus(TIM3_IT_TypeDef TIM3_IT)
+{
+  ITStatus bitstatus = RESET;
+
+  uint8_t TIM3_itStatus = 0x0, TIM3_itEnable = 0x0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM3_GET_IT(TIM3_IT));
+
+  TIM3_itStatus = (uint8_t)(TIM3->SR1 & (uint8_t)TIM3_IT);
+
+  TIM3_itEnable = (uint8_t)(TIM3->IER & (uint8_t)TIM3_IT);
+
+  if ((TIM3_itStatus != (uint8_t)RESET ) && (TIM3_itEnable != (uint8_t)RESET))
+  {
+    bitstatus = (ITStatus)SET;
+  }
+  else
+  {
+    bitstatus = (ITStatus)RESET;
+  }
+  return ((ITStatus)bitstatus);
+}
+
+/**
+  * @brief  Clears the TIM's interrupt pending bits.
+  * @param  TIM3_IT: Specifies the pending bit to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg TIM3_IT_Update: Update
+  *            @arg TIM3_IT_CC1: Capture Compare Channel1
+  *            @arg TIM3_IT_CC2: Capture Compare Channel2 
+  *            @arg TIM3_IT_Trigger: Trigger 
+  *            @arg TIM3_IT_Break: Break  
+  * @retval None
+  */
+void TIM3_ClearITPendingBit(TIM3_IT_TypeDef TIM3_IT)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM3_IT(TIM3_IT));
+
+  /* Clear the IT pending Bit */
+  TIM3->SR1 = (uint8_t)(~(uint8_t)TIM3_IT);
+}
+
+/**
+  * @brief  Enables or disables the TIM3 DMA Requests.
+  * @param  TIM3_DMASource: specifies the DMA Request sources.
+  *          This parameter can be any combination of the following values:
+  *            @arg TIM3_DMASource_Update: TIM3 DMA Update Request
+  *            @arg TIM3_DMASource_CC1: TIM3 DMA CC1 Request
+  *            @arg TIM3_DMASource_CC2: TIM3 DMA CC2 Request 
+  * @param  NewState: new state of the DMA Request sources.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM3_DMACmd( TIM3_DMASource_TypeDef TIM3_DMASource, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  assert_param(IS_TIM3_DMA_SOURCE(TIM3_DMASource));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the DMA sources */
+    TIM3->DER |= TIM3_DMASource;
+  }
+  else
+  {
+    /* Disable the DMA sources */
+    TIM3->DER &= (uint8_t)(~TIM3_DMASource);
+  }
+}
+
+/**
+  * @brief  Selects the TIM3 peripheral Capture Compare DMA source.
+  * @param   NewState: new state of the Capture Compare DMA source.
+  *           This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM3_SelectCCDMA(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Set the CCDS Bit */
+    TIM3->CR2 |= TIM_CR2_CCDS;
+  }
+  else
+  {
+    /* Reset the CCDS Bit */
+    TIM3->CR2 &= (uint8_t)(~TIM_CR2_CCDS);
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM3_Group5 Clocks management functions
+ *  @brief    Clocks management functions
+ *
+@verbatim   
+ ===============================================================================
+                         Clocks management functions
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables the TIM3 internal Clock.
+  * @par Parameters:
+  * None
+  * @retval None
+  */
+void TIM3_InternalClockConfig(void)
+{
+  /* Disable slave mode to clock the prescaler directly with the internal clock */
+  TIM3->SMCR &=  (uint8_t)(~TIM_SMCR_SMS);
+}
+
+/**
+  * @brief  Configures the TIM3 Trigger as External Clock.
+  * @param  TIM3_TIxExternalCLKSource: Specifies Trigger source.
+  *          This parameter can be one of the following values:
+  *            @arg TIM3_TIxExternalCLK1Source_TI1ED: External Clock mode 1 source = TI1ED
+  *            @arg TIM3_TIxExternalCLK1Source_TI1: External Clock mode 1 source = TI1 
+  *            @arg TIM3_TIxExternalCLK1Source_TI2: External Clock mode 1 source = TI2  
+  * @param  TIM3_ICPolarity: Specifies the TIx Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM3_ICPolarity_Rising: Input Capture on Rising Edge
+  *            @arg TIM3_ICPolarity_Falling: Input Capture on Falling Edge  
+  * @param  ICFilter: Specifies the filter value.
+  *          This parameter must be a value between 0x00 and 0x0F
+  * @retval None
+  */
+void TIM3_TIxExternalClockConfig(TIM3_TIxExternalCLK1Source_TypeDef TIM3_TIxExternalCLKSource,
+                                 TIM3_ICPolarity_TypeDef TIM3_ICPolarity,
+                                 uint8_t ICFilter)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM3_TIXCLK_SOURCE(TIM3_TIxExternalCLKSource));
+  assert_param(IS_TIM3_IC_POLARITY(TIM3_ICPolarity));
+  assert_param(IS_TIM3_IC_FILTER(ICFilter));
+
+  /* Configure the TIM3 Input Clock Source */
+  if (TIM3_TIxExternalCLKSource == TIM3_TIxExternalCLK1Source_TI2)
+  {
+    TI2_Config(TIM3_ICPolarity, TIM3_ICSelection_DirectTI, ICFilter);
+  }
+  else
+  {
+    TI1_Config(TIM3_ICPolarity, TIM3_ICSelection_DirectTI, ICFilter);
+  }
+
+  /* Select the Trigger source */
+  TIM3_SelectInputTrigger((TIM3_TRGSelection_TypeDef)TIM3_TIxExternalCLKSource);
+
+  /* Select the External clock mode1 */
+  TIM3->SMCR |= (uint8_t)(TIM3_SlaveMode_External1);
+}
+
+/**
+  * @brief  Configures the TIM3 External clock Mode1.
+  * @param  TIM3_ExtTRGPrescaler: Specifies the external Trigger Prescaler.
+  *          This parameter can be one of the following values:
+  *            @arg TIM3_ExtTRGPSC_OFF: No External Trigger prescaler
+  *            @arg TIM3_ExtTRGPSC_DIV2: External Trigger prescaler = 2 (ETRP frequency divided by 2)
+  *            @arg TIM3_ExtTRGPSC_DIV4: External Trigger prescaler = 4 (ETRP frequency divided by 4) 
+  *            @arg TIM3_ExtTRGPSC_DIV8: External Trigger prescaler = 8 (ETRP frequency divided by 8)   
+  * @param  TIM3_ExtTRGPolarity: Specifies the external Trigger Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM3_ExtTRGPolarity_Inverted: External Trigger Polarity = inverted
+  *            @arg TIM3_ExtTRGPolarity_NonInverted: External Trigger Polarity = non inverted
+  * @param  ExtTRGFilter: Specifies the External Trigger Filter.
+  *          This parameter must be a value between 0x00 and 0x0F
+  * @retval None
+  */
+void TIM3_ETRClockMode1Config(TIM3_ExtTRGPSC_TypeDef TIM3_ExtTRGPrescaler,
+                              TIM3_ExtTRGPolarity_TypeDef TIM3_ExtTRGPolarity,
+                              uint8_t ExtTRGFilter)
+{
+  /* Configure the ETR Clock source */
+  TIM3_ETRConfig(TIM3_ExtTRGPrescaler, TIM3_ExtTRGPolarity, ExtTRGFilter);
+
+  /* Select the External clock mode1 */
+  TIM3->SMCR &= (uint8_t)(~TIM_SMCR_SMS);
+  TIM3->SMCR |= (uint8_t)(TIM3_SlaveMode_External1);
+
+  /* Select the Trigger selection: ETRF */
+  TIM3->SMCR &= (uint8_t)(~TIM_SMCR_TS);
+  TIM3->SMCR |= (uint8_t)((TIM3_TRGSelection_TypeDef)TIM3_TRGSelection_ETRF);
+}
+
+/**
+  * @brief  Configures the TIM3 External clock Mode2.
+  * @param  TIM3_ExtTRGPrescaler: Specifies the external Trigger Prescaler.
+  *          This parameter can be one of the following values:
+  *            @arg TIM3_ExtTRGPSC_OFF: No External Trigger prescaler
+  *            @arg TIM3_ExtTRGPSC_DIV2: External Trigger prescaler = 2 (ETRP frequency divided by 2)
+  *            @arg TIM3_ExtTRGPSC_DIV4: External Trigger prescaler = 4 (ETRP frequency divided by 4) 
+  *            @arg TIM3_ExtTRGPSC_DIV8: External Trigger prescaler = 8 (ETRP frequency divided by 8) 
+  * @param  TIM3_ExtTRGPolarity: Specifies the external Trigger Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM3_ExtTRGPolarity_Inverted: External Trigger Polarity = inverted
+  *            @arg TIM3_ExtTRGPolarity_NonInverted: External Trigger Polarity = non inverted
+  * @param  ExtTRGFilter: Specifies the External Trigger Filter.
+  *          This parameter must be a value between 0x00 and 0x0F
+  * @retval None
+  */
+void TIM3_ETRClockMode2Config(TIM3_ExtTRGPSC_TypeDef TIM3_ExtTRGPrescaler,
+                              TIM3_ExtTRGPolarity_TypeDef TIM3_ExtTRGPolarity,
+                              uint8_t ExtTRGFilter)
+{
+  /* Configure the ETR Clock source */
+  TIM3_ETRConfig(TIM3_ExtTRGPrescaler, TIM3_ExtTRGPolarity, ExtTRGFilter);
+
+  /* Enable the External clock mode2 */
+  TIM3->ETR |= TIM_ETR_ECE ;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM3_Group6 Synchronization management functions
+ *  @brief    Synchronization management functions 
+ *
+@verbatim   
+ ===============================================================================
+                       Synchronization management functions
+ ===============================================================================  
+                   
+       ===================================================================      
+              TIM3 Driver: how to use it in synchronization Mode
+       =================================================================== 
+       Case of two/several Timers
+       **************************
+       1. If TIM3 is used as master to other timers use the following functions:
+          - TIM3_SelectOutputTrigger()
+          - TIM3_SelectMasterSlaveMode()
+       2. If TIM3 is used as slave to other timers use the following functions:
+          - TIM3_SelectInputTrigger()
+          - TIM3_SelectSlaveMode()
+          
+       Case of Timers and external trigger (TRIG pin)
+       ********************************************       
+       1. Configure the External trigger using TIM3_ETRConfig()
+       2. Configure the Slave Timer using the following functions:
+          - TIM3_SelectInputTrigger()
+          - TIM3_SelectSlaveMode()
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Selects the TIM3 Input Trigger source.
+  * @param  TIM3_InputTriggerSource: Specifies Input Trigger source.
+  *          This parameter can be one of the following values:
+  *            @arg TIM3_TRGSelection_TIM4: TRIG Input source =  TIM TRIG Output
+  *            @arg TIM3_TRGSelection_TIM1: TRIG Input source =  TIM TRIG Output
+  *            @arg TIM3_TRGSelection_TIM3: TRIG Input source =  TIM TRIG Output
+  *            @arg TIM3_TRGSelection_TIM2: TRIG Input source =  TIM TRIG Output
+  *            @arg TIM3_TRGSelection_TI1F_ED: TRIG Input source = TI1F_ED (TI1 Edge Detector)
+  *            @arg TIM3_TRGSelection_TI1FP1: TRIG Input source = TI1FP1 (Filtred Timer Input 1)
+  *            @arg TIM3_TRGSelection_TI2FP2: TRIG Input source = TI2FP2 (Filtred Timer Input 2)
+  *            @arg TIM3_TRGSelection_ETRF: TRIG Input source =  ETRF (External Trigger Input )      
+  * @retval None
+  */
+void TIM3_SelectInputTrigger(TIM3_TRGSelection_TypeDef TIM3_InputTriggerSource)
+{
+  uint8_t tmpsmcr = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM3_TRIGGER_SELECTION(TIM3_InputTriggerSource));
+
+  tmpsmcr = TIM3->SMCR;
+
+  /* Select the Trigger Source */
+  tmpsmcr &= (uint8_t)(~TIM_SMCR_TS);
+  tmpsmcr |= (uint8_t)TIM3_InputTriggerSource;
+
+  TIM3->SMCR = (uint8_t)tmpsmcr;
+}
+
+/**
+  * @brief  Selects the TIM3 Trigger Output Mode.
+  * @param  TIM3_TRGOSource: Specifies the Trigger Output source.
+  *          This parameter can be one of the following values:
+  *            @arg TIM3_TRGOSource_Reset: Trigger Output source = Reset 
+  *            @arg TIM3_TRGOSource_Enable: Trigger Output source = TIM3 is enabled 
+  *            @arg TIM3_TRGOSource_Update: Trigger Output source = Update event
+  *            @arg TIM3_TRGOSource_OC1: Trigger Output source = output compare channel1
+  *            @arg TIM3_TRGOSource_OC1REF: Trigger Output source = output compare channel 1 reference
+  *            @arg TIM3_TRGOSource_OC2REF: Trigger Output source = output compare channel 2 reference   
+  * @retval None
+  */
+void TIM3_SelectOutputTrigger(TIM3_TRGOSource_TypeDef TIM3_TRGOSource)
+{
+  uint8_t tmpcr2 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM3_TRGO_SOURCE(TIM3_TRGOSource));
+
+  tmpcr2 = TIM3->CR2;
+
+  /* Reset the MMS Bits */
+  tmpcr2 &= (uint8_t)(~TIM_CR2_MMS);
+
+  /* Select the TRGO source */
+  tmpcr2 |=  (uint8_t)TIM3_TRGOSource;
+
+  TIM3->CR2 = tmpcr2;
+}
+
+/**
+  * @brief  Selects the TIM3 Slave Mode.
+  * @param  TIM3_SlaveMode: Specifies the TIM3 Slave Mode.
+  *          This parameter can be one of the following values:
+  *            @arg TIM3_SlaveMode_Reset: Slave Mode Selection  = Reset
+  *            @arg TIM3_SlaveMode_Gated: Slave Mode Selection  = Gated
+  *            @arg TIM3_SlaveMode_Trigger: Slave Mode Selection  = Trigger
+  *            @arg TIM3_SlaveMode_External1: Slave Mode Selection  = External 1  
+  * @retval None
+  */
+void TIM3_SelectSlaveMode(TIM3_SlaveMode_TypeDef TIM3_SlaveMode)
+{
+  uint8_t tmpsmcr = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM3_SLAVE_MODE(TIM3_SlaveMode));
+
+  tmpsmcr = TIM3->SMCR;
+
+  /* Reset the SMS Bits */
+  tmpsmcr &= (uint8_t)(~TIM_SMCR_SMS);
+
+  /* Select the Slave Mode */
+  tmpsmcr |= (uint8_t)TIM3_SlaveMode;
+
+  TIM3->SMCR = tmpsmcr;
+}
+
+/**
+  * @brief  Sets or Resets the TIM3 Master/Slave Mode.
+  * @param  NewState: The new state of the synchronization between TIM3 and its slaves (through TRGO).
+  *          This parameter can be ENABLE or DISABLE
+  * @retval None
+  */
+void TIM3_SelectMasterSlaveMode(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Set or Reset the MSM Bit */
+  if (NewState != DISABLE)
+  {
+    TIM3->SMCR |= TIM_SMCR_MSM;
+  }
+  else
+  {
+    TIM3->SMCR &= (uint8_t)(~TIM_SMCR_MSM);
+  }
+}
+
+/**
+  * @brief  Configures the TIM3 External Trigger.
+  * @param  TIM3_ExtTRGPrescaler: Specifies the external Trigger Prescaler.
+  *          This parameter can be one of the following values:
+  *            @arg TIM3_ExtTRGPSC_OFF: No External Trigger prescaler
+  *            @arg TIM3_ExtTRGPSC_DIV2: External Trigger prescaler = 2 (ETRP frequency divided by 2)
+  *            @arg TIM3_ExtTRGPSC_DIV4: External Trigger prescaler = 4 (ETRP frequency divided by 4)
+  *            @arg TIM3_ExtTRGPSC_DIV8: External Trigger prescaler = 8 (ETRP frequency divided by 8)    
+  * @param  TIM3_ExtTRGPolarity: Specifies the external Trigger Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM3_ExtTRGPolarity_Inverted: External Trigger Polarity = inverted
+  *            @arg TIM3_ExtTRGPolarity_NonInverted: External Trigger Polarity = non inverted
+  * @param  ExtTRGFilter: Specifies the External Trigger Filter.
+  *          This parameter must be a value between 0x00 and 0x0F
+  * @retval None
+  */
+void TIM3_ETRConfig(TIM3_ExtTRGPSC_TypeDef TIM3_ExtTRGPrescaler,
+                    TIM3_ExtTRGPolarity_TypeDef TIM3_ExtTRGPolarity,
+                    uint8_t ExtTRGFilter)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM3_EXT_PRESCALER(TIM3_ExtTRGPrescaler));
+  assert_param(IS_TIM3_EXT_POLARITY(TIM3_ExtTRGPolarity));
+  assert_param(IS_TIM3_EXT_FILTER(ExtTRGFilter));
+
+  /* Set the Prescaler, the Filter value and the Polarity */
+  TIM3->ETR |= (uint8_t)((uint8_t)((uint8_t)TIM3_ExtTRGPrescaler | (uint8_t)TIM3_ExtTRGPolarity)
+                         | (uint8_t)ExtTRGFilter);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM3_Group7 Specific interface management functions
+ *  @brief    Specific interface management functions 
+ *
+@verbatim   
+ ===============================================================================
+                    Specific interface management functions
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures the TIM3 Encoder Interface.
+  * @param  TIM3_EncoderMode: Specifies the TIM3 Encoder Mode.
+  *          This parameter can be one of the following values:
+  *            @arg TIM3_EncoderMode_TI1: Encoder mode 1
+  *            @arg TIM3_EncoderMode_TI2: Encoder mode 2
+  *            @arg TIM3_EncoderMode_TI12: Encoder mode 3   
+  * @param  TIM3_IC1Polarity: Specifies the IC1 Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM3_ICPolarity_Rising: Input Capture on Rising Edge
+  *            @arg TIM3_ICPolarity_Falling: Input Capture on Falling Edge  
+  * @param  TIM3_IC2Polarity: Specifies the IC2 Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM3_ICPolarity_Rising: Input Capture on Rising Edge
+  *            @arg TIM3_ICPolarity_Falling: Input Capture on Falling Edge  
+  * @retval None
+  */
+void TIM3_EncoderInterfaceConfig(TIM3_EncoderMode_TypeDef TIM3_EncoderMode,
+                                 TIM3_ICPolarity_TypeDef TIM3_IC1Polarity,
+                                 TIM3_ICPolarity_TypeDef TIM3_IC2Polarity)
+{
+  uint8_t tmpsmcr = 0;
+  uint8_t tmpccmr1 = 0;
+  uint8_t tmpccmr2 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM3_ENCODER_MODE(TIM3_EncoderMode));
+  assert_param(IS_TIM3_IC_POLARITY(TIM3_IC1Polarity));
+  assert_param(IS_TIM3_IC_POLARITY(TIM3_IC2Polarity));
+
+  tmpsmcr = TIM3->SMCR;
+  tmpccmr1 = TIM3->CCMR1;
+  tmpccmr2 = TIM3->CCMR2;
+
+  /* Set the encoder Mode */
+  tmpsmcr &= (uint8_t)(TIM_SMCR_MSM | TIM_SMCR_TS)  ;
+  tmpsmcr |= (uint8_t)TIM3_EncoderMode;
+
+  /* Select the Capture Compare 1 and the Capture Compare 2 as input */
+  tmpccmr1 &= (uint8_t)(~TIM_CCMR_CCxS);
+  tmpccmr2 &= (uint8_t)(~TIM_CCMR_CCxS);
+  tmpccmr1 |= TIM_CCMR_TIxDirect_Set;
+  tmpccmr2 |= TIM_CCMR_TIxDirect_Set;
+
+  /* Set the TI1 and the TI2 Polarities */
+  if (TIM3_IC1Polarity == TIM3_ICPolarity_Falling)
+  {
+    TIM3->CCER1 |= TIM_CCER1_CC1P ;
+  }
+  else
+  {
+    TIM3->CCER1 &= (uint8_t)(~TIM_CCER1_CC1P) ;
+  }
+
+  if (TIM3_IC2Polarity == TIM3_ICPolarity_Falling)
+  {
+    TIM3->CCER1 |= TIM_CCER1_CC2P ;
+  }
+  else
+  {
+    TIM3->CCER1 &= (uint8_t)(~TIM_CCER1_CC2P) ;
+  }
+
+  TIM3->SMCR = tmpsmcr;
+  TIM3->CCMR1 = tmpccmr1;
+  TIM3->CCMR2 = tmpccmr2;
+}
+
+/**
+  * @brief  Enables or Disables the TIM’s Hall sensor interface.
+  * @param  NewState: The new state of the TIM3 Hall sensor interface.
+  *          This parameter can be ENABLE or DISABLE
+  * @retval None
+  */
+void TIM3_SelectHallSensor(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Set or Reset the TI1S Bit */
+  if (NewState != DISABLE)
+  {
+    TIM3->CR2 |= TIM_CR2_TI1S;
+  }
+  else
+  {
+    TIM3->CR2 &= (uint8_t)(~TIM_CR2_TI1S);
+  }
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @brief  Configure the TI1 as Input.
+  * @param  TIM3_ICPolarity: Input Capture Polarity
+  *          This parameter can be one of the following values:
+  *            @arg TIM3_ICPolarity_Rising: Input Capture on Rising Edge
+  *            @arg TIM3_ICPolarity_Falling: Input Capture on Falling Edge  
+  * @param  TIM3_ICSelection: Specifies the input to be used.
+  *          This parameter can be one of the following values:
+  *            @arg TIM3_ICSelection_DirectTI: Input Capture mapped on the direct input
+  *            @arg TIM3_ICSelection_IndirectTI: Input Capture mapped on the indirect input
+  *            @arg TIM3_ICSelection_TRGI: Input Capture mapped on the Trigger Input   
+  * @param  TIM3_ICFilter: Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  */
+static void TI1_Config(TIM3_ICPolarity_TypeDef TIM3_ICPolarity, \
+                       TIM3_ICSelection_TypeDef TIM3_ICSelection, \
+                       uint8_t TIM3_ICFilter)
+{
+  uint8_t tmpccmr1 = 0;
+  uint8_t tmpicpolarity = TIM3_ICPolarity;
+  tmpccmr1 = TIM3->CCMR1;
+
+  /* Check the parameters */
+  assert_param(IS_TIM3_IC_POLARITY(TIM3_ICPolarity));
+  assert_param(IS_TIM3_IC_SELECTION(TIM3_ICSelection));
+  assert_param(IS_TIM3_IC_FILTER(TIM3_ICFilter));
+
+  /* Disable the Channel 1: Reset the CCE Bit */
+  TIM3->CCER1 &=  (uint8_t)(~TIM_CCER1_CC1E);
+
+  /* Select the Input and set the filter */
+  tmpccmr1 &= (uint8_t)(~TIM_CCMR_CCxS) & (uint8_t)(~TIM_CCMR_ICxF);
+  tmpccmr1 |= (uint8_t)(((uint8_t)(TIM3_ICSelection)) | ((uint8_t)(TIM3_ICFilter << 4)));
+
+  TIM3->CCMR1 = tmpccmr1;
+
+  /* Select the Polarity */
+  if (tmpicpolarity == (uint8_t)(TIM3_ICPolarity_Falling))
+  {
+    TIM3->CCER1 |= TIM_CCER1_CC1P;
+  }
+  else
+  {
+    TIM3->CCER1 &= (uint8_t)(~TIM_CCER1_CC1P);
+  }
+
+  /* Set the CCE Bit */
+  TIM3->CCER1 |=  TIM_CCER1_CC1E;
+}
+
+/**
+  * @brief  Configure the TI2 as Input.
+  * @param  TIM3_ICPolarity: Input Capture Polarity
+  *          This parameter can be one of the following values:
+  *            @arg TIM3_ICPolarity_Rising: Input Capture on Rising Edge
+  *            @arg TIM3_ICPolarity_Falling: Input Capture on Falling Edge  
+  * @param  TIM3_ICSelection: Specifies the input to be used.
+  *          This parameter can be one of the following values:
+  *            @arg TIM3_ICSelection_DirectTI: Input Capture mapped on the direct input
+  *            @arg TIM3_ICSelection_IndirectTI: Input Capture mapped on the indirect input
+  *            @arg TIM3_ICSelection_TRGI: Input Capture mapped on the Trigger Input   
+  * @param  TIM3_ICFilter: Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  */
+static void TI2_Config(TIM3_ICPolarity_TypeDef TIM3_ICPolarity,
+                       TIM3_ICSelection_TypeDef TIM3_ICSelection,
+                       uint8_t TIM3_ICFilter)
+{
+  uint8_t tmpccmr2 = 0;
+  uint8_t tmpicpolarity = TIM3_ICPolarity;
+
+  /* Check the parameters */
+  assert_param(IS_TIM3_IC_POLARITY(TIM3_ICPolarity));
+  assert_param(IS_TIM3_IC_SELECTION(TIM3_ICSelection));
+  assert_param(IS_TIM3_IC_FILTER(TIM3_ICFilter));
+
+  tmpccmr2 = TIM3->CCMR2;
+
+  /* Disable the Channel 2: Reset the CCE Bit */
+  TIM3->CCER1 &=  (uint8_t)(~TIM_CCER1_CC2E);
+
+  /* Select the Input and set the filter */
+  tmpccmr2 &= (uint8_t)(~TIM_CCMR_CCxS) & (uint8_t)(~TIM_CCMR_ICxF);
+  tmpccmr2 |= (uint8_t)(((uint8_t)(TIM3_ICSelection)) | ((uint8_t)(TIM3_ICFilter << 4)));
+
+  TIM3->CCMR2 = tmpccmr2;
+
+  /* Select the Polarity */
+  if (tmpicpolarity == TIM3_ICPolarity_Falling)
+  {
+    TIM3->CCER1 |= TIM_CCER1_CC2P ;
+  }
+  else
+  {
+    TIM3->CCER1 &= (uint8_t)(~TIM_CCER1_CC2P) ;
+  }
+
+  /* Set the CCE Bit */
+  TIM3->CCER1 |=  TIM_CCER1_CC2E;
+}
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+  
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_tim4.c b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_tim4.c
new file mode 100755
index 0000000..e80404a
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_tim4.c
@@ -0,0 +1,759 @@
+/**
+  ******************************************************************************
+  * @file    stm8l15x_tim4.c
+  * @author  MCD Application Team
+  * @version V1.6.0
+  * @date    28-June-2013
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the TIM4 peripheral:
+  *            - TimeBase management
+  *            - Interrupts, DMA and flags management
+  *            - Clocks management
+  *            - Synchronization management
+  *
+  *  @verbatim
+  *  
+  *          ===================================================================
+  *                                 How to use this driver
+  *          ===================================================================
+  *          This driver provides functions to configure and initialise the TIM4 
+  *          peripheral
+  *          These functions are split in 4 groups: 
+  *   
+  *          1. TIM4 TimeBase management: this group includes all needed functions 
+  *             to configure the TIM Timebase unit:
+  *                   - Set/Get Prescaler
+  *                   - Set/Get Autoreload  
+  *                   - Select the One Pulse mode
+  *                   - Update Request Configuration
+  *                   - Update Disable Configuration
+  *                   - Auto-Preload Configuration 
+  *                   - Enable/Disable the counter
+  *                         
+  *          2. TIM4 interrupts, DMA and flags management
+  *                   - Enable/Disable interrupt sources
+  *                   - Get flags status
+  *                   - Clear flags/ Pending bits
+  *                   - Enable/Disable DMA requests 
+  *              
+  *          3. TIM4 clocks management: this group includes all needed functions 
+  *             to configure the clock controller unit:
+  *                   - Select internal clock
+  *         
+  *          4. TIM4 synchronization management: this group includes all needed 
+  *             functions to configure the Synchronization unit:
+  *                   - Select Input Trigger  
+  *                   - Select Output Trigger  
+  *                   - Select Master Slave Mode    
+  *      
+  *   
+  *  @endverbatim
+  *    
+  ******************************************************************************
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ****************************************************************************** 
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm8l15x_tim4.h"
+
+/** @addtogroup STM8L15x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup TIM4
+  * @brief TIM4 driver modules
+  * @{
+  */
+  
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup TIM4_Private_Functions
+  * @{
+  */
+
+/** @defgroup TIM4_Group1 TimeBase management functions
+ *  @brief   TimeBase management functions 
+ *
+@verbatim   
+ ===============================================================================
+                       TimeBase management functions
+ ===============================================================================  
+  
+       ===================================================================      
+              TIM4 Driver: how to use it in Timing(Time base) Mode
+       =================================================================== 
+       To use the Timer in Timing(Time base) mode, the following steps are mandatory:
+       
+       1. Enable TIM4 clock using CLK_PeripheralClockConfig(CLK_Peripheral_TIM4, ENABLE) function.
+        
+       2. Call TIM4_TimeBaseInit() to configure the Time Base unit with the
+          corresponding configuration.
+          
+       3. Enable global interrupts if you need to generate the update interrupt.
+          
+       4. Enable the corresponding interrupt using the function TIM4_ITConfig(TIM4_IT_Update) 
+          
+       5. Call the TIM4_Cmd(ENABLE) function to enable the TIM4 counter.
+       
+       Note1: All other functions can be used separately to modify, if needed,
+          a specific feature of the Timer. 
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the TIM4 peripheral registers to their default reset values.
+  * @param  None
+  * @retval None
+  */
+void TIM4_DeInit(void)
+{
+  TIM4->CR1   = TIM4_CR1_RESET_VALUE;
+  TIM4->CR2   = TIM4_CR2_RESET_VALUE;
+  TIM4->SMCR   = TIM4_SMCR_RESET_VALUE;
+  TIM4->IER   = TIM4_IER_RESET_VALUE;
+  TIM4->CNTR   = TIM4_CNTR_RESET_VALUE;
+  TIM4->PSCR  = TIM4_PSCR_RESET_VALUE;
+  TIM4->ARR   = TIM4_ARR_RESET_VALUE;
+  TIM4->SR1   = TIM4_SR1_RESET_VALUE;
+}
+
+/**
+  * @brief  Initializes the TIM4 Time Base Unit according to the specified parameters.
+  * @param  TIM4_Prescaler: Prescaler
+  *          This parameter can be one of the following values:
+  *            @arg TIM4_Prescaler_1: Time base Prescaler = 1 (No effect)
+  *            @arg TIM4_Prescaler_2: Time base Prescaler = 2
+  *            @arg TIM4_Prescaler_4: Time base Prescaler = 4
+  *            @arg TIM4_Prescaler_8: Time base Prescaler = 8
+  *            @arg TIM4_Prescaler_16: Time base Prescaler = 16
+  *            @arg TIM4_Prescaler_32: Time base Prescaler = 32
+  *            @arg TIM4_Prescaler_64: Time base Prescaler = 64
+  *            @arg TIM4_Prescaler_128: Time base Prescaler = 128
+  *            @arg TIM4_Prescaler_256: Time base Prescaler = 256
+  *            @arg TIM4_Prescaler_512: Time base Prescaler = 512
+  *            @arg TIM4_Prescaler_1024: Time base Prescaler = 1024
+  *            @arg TIM4_Prescaler_2048: Time base Prescaler = 2048
+  *            @arg TIM4_Prescaler_4096: Time base Prescaler = 4096
+  *            @arg TIM4_Prescaler_8192: Time base Prescaler = 8192
+  *            @arg TIM4_Prescaler_16384: Time base Prescaler = 16384
+  *            @arg TIM4_Prescaler_32768: Time base Prescaler = 32768                              
+  * @param  TIM4_Period: This parameter must be a value between 0x00 and 0xFF.
+  * @retval None
+  */
+void TIM4_TimeBaseInit(TIM4_Prescaler_TypeDef TIM4_Prescaler,
+                       uint8_t TIM4_Period)
+{
+  /* Check TIM4 prescaler value */
+  assert_param(IS_TIM4_Prescaler(TIM4_Prescaler));
+  /* Set the Autoreload value */
+  TIM4->ARR = (uint8_t)(TIM4_Period);
+  /* Set the Prescaler value */
+  TIM4->PSCR = (uint8_t)(TIM4_Prescaler);
+
+  /* Generate an update event to reload the Prescaler value immediately */
+  TIM4->EGR = TIM4_EventSource_Update;
+}
+
+/**
+  * @brief  Configures the TIM4 Prescaler.
+  * @param  Prescaler: Specifies the Prescaler Register value
+  *          This parameter can be one of the following values:
+  *            @arg TIM4_Prescaler_1: Time base Prescaler = 1 (No effect)
+  *            @arg TIM4_Prescaler_2: Time base Prescaler = 2
+  *            @arg TIM4_Prescaler_4: Time base Prescaler = 4
+  *            @arg TIM4_Prescaler_8: Time base Prescaler = 8
+  *            @arg TIM4_Prescaler_16: Time base Prescaler = 16
+  *            @arg TIM4_Prescaler_32: Time base Prescaler = 32
+  *            @arg TIM4_Prescaler_64: Time base Prescaler = 64
+  *            @arg TIM4_Prescaler_128: Time base Prescaler = 128
+  *            @arg TIM4_Prescaler_256: Time base Prescaler = 256
+  *            @arg TIM4_Prescaler_512: Time base Prescaler = 512
+  *            @arg TIM4_Prescaler_1024: Time base Prescaler = 1024
+  *            @arg TIM4_Prescaler_2048: Time base Prescaler = 2048
+  *            @arg TIM4_Prescaler_4096: Time base Prescaler = 4096
+  *            @arg TIM4_Prescaler_8192: Time base Prescaler = 8192
+  *            @arg TIM4_Prescaler_16384: Time base Prescaler = 16384
+  *            @arg TIM4_Prescaler_32768: Time base Prescaler = 32768 
+  * @param  TIM4_PSCReloadMode: Specifies the TIM4 Prescaler Reload mode.
+  *          This parameter can be one of the following values:
+  *            @arg TIM4_PSCReloadMode_Update: Prescaler value is reloaded at every update
+  *            @arg TIM4_PSCReloadMode_Immediate: Prescaler value is reloaded immediatly
+  * @retval None
+  */
+void TIM4_PrescalerConfig(TIM4_Prescaler_TypeDef Prescaler,
+                          TIM4_PSCReloadMode_TypeDef TIM4_PSCReloadMode)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM4_Prescaler_RELOAD(TIM4_PSCReloadMode));
+  assert_param(IS_TIM4_Prescaler(Prescaler));
+
+  /* Set the Prescaler value */
+  TIM4->PSCR = (uint8_t) Prescaler;
+
+  /* Set or reset the UG Bit */
+  if (TIM4_PSCReloadMode == TIM4_PSCReloadMode_Immediate)
+  {
+    TIM4->EGR |= TIM4_EGR_UG ;
+  }
+  else
+  {
+    TIM4->EGR &= (uint8_t)(~TIM4_EGR_UG) ;
+  }
+}
+
+/**
+  * @brief  Sets the TIM4 Counter Register value.
+  * @param  Counter: Specifies the Counter register new value.
+  *          This parameter is between 0x00 and 0xFF.
+  * @retval None
+  */
+void TIM4_SetCounter(uint8_t Counter)
+{
+  /* Set the Counter Register value */
+  TIM4->CNTR = (uint8_t)(Counter);
+}
+
+/**
+  * @brief  Sets the TIM4 Autoreload Register value.
+  * @param  Autoreload: Specifies the Autoreload register new value.
+  *          This parameter is between 0x00 and 0xFF.
+  * @retval None
+  */
+void TIM4_SetAutoreload(uint8_t Autoreload)
+{
+  /* Set the Autoreload Register value */
+  TIM4->ARR = (uint8_t)(Autoreload);
+}
+
+/**
+  * @brief  Gets the TIM4 Counter value.
+  * @param  None
+  * @retval Counter Register value.
+  */
+uint8_t TIM4_GetCounter(void)
+{
+  uint8_t tmpcntr = 0;
+  tmpcntr = TIM4->CNTR;
+  /* Get the Counter Register value */
+  return ((uint8_t)tmpcntr);
+}
+
+/**
+  * @brief  Gets the TIM4 Prescaler value.
+  * @param  None
+  * @retval TIM4 Prescaler can be one of the following values:
+  *            - TIM4_Prescaler_1: Time base Prescaler = 1 (No effect)
+  *            - TIM4_Prescaler_2: Time base Prescaler = 2
+  *            - TIM4_Prescaler_4: Time base Prescaler = 4
+  *            - TIM4_Prescaler_8: Time base Prescaler = 8
+  *            - TIM4_Prescaler_16: Time base Prescaler = 16
+  *            - TIM4_Prescaler_32: Time base Prescaler = 32
+  *            - TIM4_Prescaler_64: Time base Prescaler = 64
+  *            - TIM4_Prescaler_128: Time base Prescaler = 128
+  *            - TIM4_Prescaler_256: Time base Prescaler = 256
+  *            - TIM4_Prescaler_512: Time base Prescaler = 512
+  *            - TIM4_Prescaler_1024: Time base Prescaler = 1024
+  *            - TIM4_Prescaler_2048: Time base Prescaler = 2048
+  *            - TIM4_Prescaler_4096: Time base Prescaler = 4096
+  *            - TIM4_Prescaler_8192: Time base Prescaler = 8192
+  *            - TIM4_Prescaler_16384: Time base Prescaler = 16384
+  *            - TIM4_Prescaler_32768: Time base Prescaler = 32768  
+  */
+TIM4_Prescaler_TypeDef TIM4_GetPrescaler(void)
+{
+  /* Get the Prescaler Register value */
+  return ((TIM4_Prescaler_TypeDef)TIM4->PSCR);
+}
+
+/**
+  * @brief  Enables or Disables the TIM4 Update event.
+  * @param  NewState: The new state of the TIM4 peripheral Preload register.
+  *          This parameter can be ENABLE or DISABLE
+  * @retval None
+  */
+void TIM4_UpdateDisableConfig(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Set or Reset the UDIS Bit */
+  if (NewState != DISABLE)
+  {
+    TIM4->CR1 |= TIM4_CR1_UDIS ;
+  }
+  else
+  {
+    TIM4->CR1 &= (uint8_t)(~TIM4_CR1_UDIS) ;
+  }
+}
+
+/**
+  * @brief  Selects the TIM4 Update Request Interrupt source.
+  * @param  TIM4_UpdateSource: Specifies the Update source.
+  *          This parameter can be one of the following values:
+  *            @arg TIM4_UpdateSource_Global: Global Update request source
+  *            @arg TIM4_UpdateSource_Regular: Regular Update request source
+  * @retval None
+  */
+void TIM4_UpdateRequestConfig(TIM4_UpdateSource_TypeDef TIM4_UpdateSource)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM4_UPDATE_SOURCE(TIM4_UpdateSource));
+
+  /* Set or Reset the URS Bit */
+  if (TIM4_UpdateSource == TIM4_UpdateSource_Regular)
+  {
+    TIM4->CR1 |= TIM4_CR1_URS ;
+  }
+  else
+  {
+    TIM4->CR1 &= (uint8_t)(~TIM4_CR1_URS) ;
+  }
+}
+
+/**
+  * @brief  Enables or disables TIM4 peripheral Preload register on ARR.
+  * @param  NewState: The new state of the TIM4 peripheral Preload register.
+  *          This parameter can be ENABLE or DISABLE
+  * @retval None
+  */
+void TIM4_ARRPreloadConfig(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Set or Reset the ARPE Bit */
+  if (NewState != DISABLE)
+  {
+    TIM4->CR1 |= TIM4_CR1_ARPE ;
+  }
+  else
+  {
+    TIM4->CR1 &= (uint8_t)(~TIM4_CR1_ARPE) ;
+  }
+}
+
+/**
+  * @brief  Selects the TIM4’s One Pulse Mode.
+  * @param  TIM4_OPMode: Specifies the OPM Mode to be used.
+  *          This parameter can be one of the following values:
+  *            @arg TIM4_OPMode_Single: Single one Pulse mode (OPM Active)
+  *            @arg TIM4_OPMode_Repetitive: Repetitive Pulse mode (OPM inactive)
+  * @retval None
+  */
+void TIM4_SelectOnePulseMode(TIM4_OPMode_TypeDef TIM4_OPMode)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM4_OPM_MODE(TIM4_OPMode));
+
+  /* Set or Reset the OPM Bit */
+  if (TIM4_OPMode == TIM4_OPMode_Single)
+  {
+    TIM4->CR1 |= TIM4_CR1_OPM ;
+  }
+  else
+  {
+    TIM4->CR1 &= (uint8_t)(~TIM4_CR1_OPM) ;
+  }
+}
+
+/**
+  * @brief  Enables or disables the TIM4 peripheral.
+  * @param  NewState: The new state of the TIM4 peripheral.
+  *          This parameter can be ENABLE or DISABLE
+  * @retval None
+  */
+void TIM4_Cmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* set or Reset the CEN Bit */
+  if (NewState != DISABLE)
+  {
+    TIM4->CR1 |= TIM4_CR1_CEN ;
+  }
+  else
+  {
+    TIM4->CR1 &= (uint8_t)(~TIM4_CR1_CEN) ;
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM4_Group2 Interrupts DMA and flags management functions
+ *  @brief    Interrupts, DMA and flags management functions 
+ *
+@verbatim   
+ ===============================================================================
+                 Interrupts, DMA and flags management functions
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the specified TIM4 interrupts.
+  * @param  TIM4_IT: Specifies the TIM4 interrupts sources to be enabled or disabled.
+  *          This parameter can be one of the following values:
+  *            @arg TIM4_IT_Update: Update
+  *            @arg TIM4_IT_Trigger: Trigger
+  * @param  NewState: The new state of the TIM4 peripheral.
+  *          This parameter can be ENABLE or DISABLE
+  * @retval None
+  */
+void TIM4_ITConfig(TIM4_IT_TypeDef TIM4_IT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM4_IT(TIM4_IT));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the Interrupt sources */
+    TIM4->IER |= (uint8_t)TIM4_IT;
+  }
+  else
+  {
+    /* Disable the Interrupt sources */
+    TIM4->IER &= (uint8_t)(~(uint8_t)TIM4_IT);
+  }
+}
+
+/**
+  * @brief  Configures the TIM4 event to be generated by software.
+  * @param  TIM4_EventSource: Specifies the event source.
+  *          This parameter can be one of the following values:
+  *            @arg TIM4_EventSource_Update: Update
+  *            @arg TIM4_EventSource_Trigger: Trigger
+  * @retval None
+  */
+void TIM4_GenerateEvent(TIM4_EventSource_TypeDef TIM4_EventSource)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM4_EVENT_SOURCE((uint8_t)TIM4_EventSource));
+
+  /* Set the event sources */
+  TIM4->EGR |= (uint8_t)TIM4_EventSource;
+}
+
+/**
+  * @brief  Checks whether the specified TIM4 flag is set or not.
+  * @param  TIM4_FLAG: Specifies the flag to check.
+  *          This parameter can be one of the following values:
+  *            @arg TIM4_FLAG_Update: Update
+  *            @arg TIM4_FLAG_Trigger: Trigger
+  * @retval FlagStatus: The new state of TIM4_FLAG.
+  *          This parameter can be SET or RESET.
+  */
+FlagStatus TIM4_GetFlagStatus(TIM4_FLAG_TypeDef TIM4_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+
+  /* Check the parameters */
+  assert_param(IS_TIM4_GET_FLAG(TIM4_FLAG));
+
+  if ((TIM4->SR1 & (uint8_t)TIM4_FLAG)  != 0)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return ((FlagStatus)bitstatus);
+}
+
+/**
+  * @brief  Clears the TIM’s pending flags.
+  * @param  TIM4_FLAG: Specifies the flag to clear.
+  *          This parameter can be one of the following values:
+  *            @arg TIM4_FLAG_Update: Update
+  *            @arg TIM4_FLAG_Trigger: Trigger
+  * @retval None
+  */
+void TIM4_ClearFlag(TIM4_FLAG_TypeDef TIM4_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM4_CLEAR_FLAG((uint8_t)TIM4_FLAG));
+  /* Clear the flags (rc_w0) clear this bit by writing 0. Writing ‘1’ has no effect*/
+  TIM4->SR1 = (uint8_t)(~((uint8_t)TIM4_FLAG));
+}
+
+/**
+  * @brief  Checks whether the TIM4 interrupt has occurred or not.
+  * @param  TIM4_IT: Specifies the TIM4 interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg TIM4_IT_Update: Update
+  *            @arg TIM4_IT_Trigger: Trigger
+  * @retval ITStatus: The new state of the TIM4_IT.
+  *          This parameter can be SET or RESET
+  */
+
+ITStatus TIM4_GetITStatus(TIM4_IT_TypeDef TIM4_IT)
+{
+  ITStatus bitstatus = RESET;
+
+  uint8_t itStatus = 0x0, itEnable = 0x0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM4_GET_IT(TIM4_IT));
+
+  itStatus = (uint8_t)(TIM4->SR1 & (uint8_t)TIM4_IT);
+
+  itEnable = (uint8_t)(TIM4->IER & (uint8_t)TIM4_IT);
+
+  if ((itStatus != (uint8_t)RESET ) && (itEnable != (uint8_t)RESET ))
+  {
+    bitstatus = (ITStatus)SET;
+  }
+  else
+  {
+    bitstatus = (ITStatus)RESET;
+  }
+  return ((ITStatus)bitstatus);
+}
+
+/**
+  * @brief  Clears the TIM4's interrupt pending bits.
+  * @param  TIM4_IT: Specifies the pending bit to clear.
+  *          This parameter can be one of the following values:
+  *            @arg TIM4_IT_Update: Update
+  *            @arg TIM4_IT_Trigger: Trigger
+  * @retval None
+  */
+void TIM4_ClearITPendingBit(TIM4_IT_TypeDef TIM4_IT)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM4_IT(TIM4_IT));
+
+  /* Clear the IT pending Bit */
+  TIM4->SR1 = (uint8_t)(~(uint8_t)TIM4_IT);
+}
+
+/**
+  * @brief  Enables or disables the TIMx’s DMA Requests.
+  * @param  TIM4_DMASources: specifies the DMA Request sources.
+  *          This parameter can be one of the following values:
+  *            @arg TIM4_DMASource_Update: Update
+  * @param  NewState: new state of the DMA Request sources.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM4_DMACmd( TIM4_DMASource_TypeDef TIM4_DMASource, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  assert_param(IS_TIM4_DMA_SOURCE(TIM4_DMASource));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the DMA sources */
+    TIM4->DER |= (uint8_t)TIM4_DMASource;
+  }
+  else
+  {
+    /* Disable the DMA sources */
+    TIM4->DER &= (uint8_t)~TIM4_DMASource;
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM4_Group3 Clocks management functions
+ *  @brief    Clocks management functions
+ *
+@verbatim   
+ ===============================================================================
+                         Clocks management functions
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables the TIM4 internal Clock.
+  * @param  None
+  * @retval None
+  */
+void TIM4_InternalClockConfig(void)
+{
+  /* Disable slave mode to clock the prescaler directly with the internal clock */
+  TIM4->SMCR &=  (uint8_t)(~TIM4_SMCR_SMS);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM4_Group4 Synchronization management functions
+ *  @brief    Synchronization management functions 
+ *
+@verbatim   
+ ===============================================================================
+                       Synchronization management functions
+ ===============================================================================  
+                   
+       ===================================================================      
+              TIM4 Driver: how to use it in synchronization Mode
+       =================================================================== 
+       Case of two/several Timers
+       **************************
+       1. If TIM4 is used as master to other timers use the following functions:
+          - TIM4_SelectOutputTrigger()
+          - TIM4_SelectMasterSlaveMode()
+       2. If TIM4 is used as slave to other timers use the following functions:
+          - TIM4_SelectInputTrigger()
+          - TIM4_SelectSlaveMode()
+          
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Selects the TIM4 Input Trigger source.
+  * @param  TIM4_InputTriggerSource: Specifies Input Trigger source.
+  *          This parameter can be one of the following values:
+  *            @arg TIM4_TRGSelection_TIM5: TRIG Input source =  TIM5 TRIG Output
+  *            @arg TIM4_TRGSelection_TIM1: TRIG Input source =  TIM1 TRIG Output
+  *            @arg TIM4_TRGSelection_TIM3: TRIG Input source =  TIM3 TRIG Output
+  *            @arg TIM4_TRGSelection_TIM2: TRIG Input source =  TIM2 TRIG Output
+  * @retval None
+  */
+void TIM4_SelectInputTrigger(TIM4_TRGSelection_TypeDef TIM4_InputTriggerSource)
+{
+  uint8_t tmpsmcr = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM4_TRIGGER_SELECTION(TIM4_InputTriggerSource));
+
+  tmpsmcr = TIM4->SMCR;
+
+  /* Select the Trigger Source */
+  tmpsmcr &= (uint8_t)(~TIM4_SMCR_TS);
+  tmpsmcr |= (uint8_t)TIM4_InputTriggerSource;
+
+  TIM4->SMCR = (uint8_t)tmpsmcr;
+}
+
+/**
+  * @brief  Selects the TIM4 Trigger Output Mode.
+  * @param  TIM4_TRGOSource: Specifies the Trigger Output source.
+  *          This parameter can be one of the following values:
+  *            @arg TIM4_TRGOSource_Reset: Trigger Output source = Reset
+  *            @arg TIM4_TRGOSource_Enable: Trigger Output source = TIM4 is enabled
+  *            @arg TIM4_TRGOSource_Update: Trigger Output source = Update event
+  * @retval None
+  */
+void TIM4_SelectOutputTrigger(TIM4_TRGOSource_TypeDef TIM4_TRGOSource)
+{
+  uint8_t tmpcr2 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM4_TRGO_SOURCE(TIM4_TRGOSource));
+
+  tmpcr2 = TIM4->CR2;
+
+  /* Reset the MMS Bits */
+  tmpcr2 &= (uint8_t)(~TIM4_CR2_MMS);
+
+  /* Select the TRGO source */
+  tmpcr2 |=  (uint8_t)TIM4_TRGOSource;
+
+  TIM4->CR2 = tmpcr2;
+}
+
+/**
+  * @brief  Selects the TIM4 Slave Mode.
+  * @param  TIM4_SlaveMode: Specifies the TIM4 Slave Mode.
+  *          This parameter can be one of the following values:
+  *            @arg TIM4_SlaveMode_Disable: Disable slave mode to clock the prescaler
+                                            directly with the internal clock
+  *            @arg TIM4_SlaveMode_Reset: Slave Mode Selection  = Reset
+  *            @arg TIM4_SlaveMode_Gated: Slave Mode Selection  = Gated
+  *            @arg TIM4_SlaveMode_Trigger: Slave Mode Selection  = Trigger
+  *            @arg TIM4_SlaveMode_External1: Slave Mode Selection  = External 1  
+  * @retval None
+  */
+void TIM4_SelectSlaveMode(TIM4_SlaveMode_TypeDef TIM4_SlaveMode)
+{
+  uint8_t tmpsmcr = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM4_SLAVE_MODE(TIM4_SlaveMode));
+
+  tmpsmcr = TIM4->SMCR;
+
+  /* Reset the SMS Bits */
+  tmpsmcr &= (uint8_t)(~TIM4_SMCR_SMS);
+
+  /* Select the Slave Mode */
+  tmpsmcr |= (uint8_t)TIM4_SlaveMode;
+
+  TIM4->SMCR = tmpsmcr;
+}
+
+/**
+  * @brief  Sets or Resets the TIM4 Master/Slave Mode.
+  * @param NewState: The new state of the synchronization between TIM4 and its slaves (through TRGO).
+  *          This parameter can be ENABLE or DISABLE
+  * @retval None
+  */
+void TIM4_SelectMasterSlaveMode(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Set or Reset the MSM Bit */
+  if (NewState != DISABLE)
+  {
+    TIM4->SMCR |= TIM4_SMCR_MSM;
+  }
+  else
+  {
+    TIM4->SMCR &= (uint8_t)(~TIM4_SMCR_MSM);
+  }
+}
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+  
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_tim5.c b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_tim5.c
new file mode 100755
index 0000000..619e739
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_tim5.c
@@ -0,0 +1,2151 @@
+/**
+  ******************************************************************************
+  * @file    stm8l15x_tim5.c
+  * @author  MCD Application Team
+  * @version V1.6.0
+  * @date    28-June-2013
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the TIM5 peripheral:
+  *            - TimeBase management
+  *            - Output Compare management
+  *            - Input Capture management
+  *            - Interrupts, DMA and flags management
+  *            - Clocks management
+  *            - Synchronization management
+  *            - Specific interface management
+  *              
+  *  @verbatim
+  *  
+  *          ===================================================================
+  *                                 How to use this driver
+  *          ===================================================================
+  *          This driver provides functions to configure and initialise the TIM5
+  *          peripheral
+  *          These functions are split in 7 groups: 
+  *   
+  *          1. TIM5 TimeBase management: this group includes all needed functions 
+  *             to configure the TIM Timebase unit:
+  *                   - Set/Get Prescaler
+  *                   - Set/Get Autoreload  
+  *                   - Counter modes configuration
+  *                   - Select the One Pulse mode
+  *                   - Update Request Configuration
+  *                   - Update Disable Configuration
+  *                   - Auto-Preload Configuration 
+  *                   - Enable/Disable the counter
+  *                 
+  *          2. TIM5 Output Compare management: this group includes all needed 
+  *             functions to configure the Capture/Compare unit used in Output 
+  *             compare mode: 
+  *                   - Configure each channel, independently, in Output Compare mode
+  *                   - Select the output compare modes
+  *                   - Select the Polarities of each channel
+  *                   - Set/Get the Capture/Compare register values
+  *                   - Select the Output Compare Fast mode 
+  *                   - Select the Output Compare Forced mode  
+  *                   - Output Compare-Preload Configuration 
+  *                   - Enable/Disable the Capture/Compare Channels    
+  *                   
+  *          3. TIM5 Input Capture management: this group includes all needed 
+  *             functions to configure the Capture/Compare unit used in 
+  *             Input Capture mode:
+  *                   - Configure each channel in input capture mode
+  *                   - Configure Channel1/2 in PWM Input mode
+  *                   - Set the Input Capture Prescaler
+  *                   - Get the Capture/Compare values      
+  *        
+  *          4. TIM5 interrupts, DMA and flags management
+  *                   - Enable/Disable interrupt sources
+  *                   - Get flags status
+  *                   - Clear flags/ Pending bits
+  *                   - Enable/Disable DMA requests 
+  *                   - Select CaptureCompare DMA request  
+  *              
+  *          5. TIM5 clocks management: this group includes all needed functions 
+  *             to configure the clock controller unit:
+  *                   - Select internal/External clock
+  *                   - Select the external clock mode: ETR(Mode1/Mode2) or TIx
+  *         
+  *          6. TIM5 synchronization management: this group includes all needed 
+  *             functions to configure the Synchronization unit:
+  *                   - Select Input Trigger  
+  *                   - Select Output Trigger  
+  *                   - Select Master Slave Mode 
+  *                   - ETR Configuration when used as external trigger   
+  *     
+  *          7. TIM5 specific interface management, this group includes all 
+  *             needed functions to use the specific TIM5 interface:
+  *                   - Encoder Interface Configuration
+  *                   - Select Hall Sensor        
+  *   
+  *  @endverbatim
+  *    
+  ******************************************************************************
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ****************************************************************************** 
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm8l15x_TIM5.h"
+
+/** @addtogroup STM8L15x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup TIM5 
+  * @brief TIM5 driver modules
+  * @{
+  */
+  
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void TI1_Config(TIM5_ICPolarity_TypeDef TIM5_ICPolarity,
+                       TIM5_ICSelection_TypeDef TIM5_ICSelection,
+                       uint8_t TIM5_ICFilter);
+static void TI2_Config(TIM5_ICPolarity_TypeDef TIM5_ICPolarity,
+                       TIM5_ICSelection_TypeDef TIM5_ICSelection,
+                       uint8_t TIM5_ICFilter);
+
+
+/** @defgroup TIM5_Private_Functions
+  * @{
+  */
+
+/** @defgroup TIM5_Group1 TimeBase management functions
+ *  @brief   TimeBase management functions 
+ *
+@verbatim   
+ ===============================================================================
+                       TimeBase management functions
+ ===============================================================================  
+  
+       ===================================================================      
+              TIM5 Driver: how to use it in Timing(Time base) Mode
+       =================================================================== 
+       To use the Timer in Timing(Time base) mode, the following steps are mandatory:
+       
+       1. Enable TIM5 clock using CLK_PeripheralClockConfig(CLK_Peripheral_TIM5, ENABLE) function.
+        
+       2. Call TIM5_TimeBaseInit() to configure the Time Base unit with the
+          corresponding configuration.
+          
+       3. Enable global interrupts if you need to generate the update interrupt.
+          
+       4. Enable the corresponding interrupt using the function TIM5_ITConfig(TIM5_IT_Update) 
+          
+       5. Call the TIM5_Cmd(ENABLE) function to enable the TIM5 counter.
+       
+       Note1: All other functions can be used separately to modify, if needed,
+          a specific feature of the Timer. 
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitialize the TIM5 peripheral registers to their default reset values.
+  * @param  None
+  * @retval None
+  */
+void TIM5_DeInit(void)
+{
+  TIM5->CR1 = TIM_CR1_RESET_VALUE;
+  TIM5->CR2 = TIM_CR2_RESET_VALUE;
+  TIM5->SMCR = TIM_SMCR_RESET_VALUE;
+  TIM5->ETR = TIM_ETR_RESET_VALUE;
+  TIM5->IER = TIM_IER_RESET_VALUE;
+  TIM5->SR2 = TIM_SR2_RESET_VALUE;
+
+  /* Disable channels */
+  TIM5->CCER1 = TIM_CCER1_RESET_VALUE;
+  /* Configure channels as inputs: it is necessary if lock level is equal to 2 or 3 */
+  TIM5->CCMR1 = 0x01;/*TIM5_ICxSource_TIxFPx */
+  TIM5->CCMR2 = 0x01;/*TIM5_ICxSource_TIxFPx */
+
+  /* Then reset channel registers: it also works if lock level is equal to 2 or 3 */
+  TIM5->CCER1 = TIM_CCER1_RESET_VALUE;
+  TIM5->CCMR1 = TIM_CCMR1_RESET_VALUE;
+  TIM5->CCMR2 = TIM_CCMR2_RESET_VALUE;
+
+  TIM5->CNTRH = TIM_CNTRH_RESET_VALUE;
+  TIM5->CNTRL = TIM_CNTRL_RESET_VALUE;
+
+  TIM5->PSCR = TIM_PSCR_RESET_VALUE;
+
+  TIM5->ARRH = TIM_ARRH_RESET_VALUE;
+  TIM5->ARRL = TIM_ARRL_RESET_VALUE;
+
+  TIM5->CCR1H = TIM_CCR1H_RESET_VALUE;
+  TIM5->CCR1L = TIM_CCR1L_RESET_VALUE;
+  TIM5->CCR2H = TIM_CCR2H_RESET_VALUE;
+  TIM5->CCR2L = TIM_CCR2L_RESET_VALUE;
+
+
+  TIM5->OISR = TIM_OISR_RESET_VALUE;
+  TIM5->EGR = 0x01;/* TIM_EGR_UG */
+  TIM5->BKR = TIM_BKR_RESET_VALUE;
+  TIM5->SR1 = TIM_SR1_RESET_VALUE;
+}
+
+/**
+  * @brief  Initializes the TIM5 Time Base Unit according to the specified  parameters.
+  * @param  TIM5_Prescaler: Prescaler 
+  *          This parameter can be one of the following values:
+  *            @arg TIM5_Prescaler_1: Time base Prescaler = 1 (No effect)
+  *            @arg TIM5_Prescaler_2: Time base Prescaler = 2
+  *            @arg TIM5_Prescaler_4: Time base Prescaler = 4
+  *            @arg TIM5_Prescaler_8: Time base Prescaler = 8
+  *            @arg TIM5_Prescaler_16: Time base Prescaler = 16
+  *            @arg TIM5_Prescaler_32: Time base Prescaler = 32
+  *            @arg TIM5_Prescaler_64: Time base Prescaler = 64
+  *            @arg TIM5_Prescaler_128: Time base Prescaler = 128                            
+  * @param  TIM5_CounterMode: Counter mode
+  *          This parameter can be one of the following values:
+  *            @arg TIM5_CounterMode_Up: Counter Up Mode
+  *            @arg TIM5_CounterMode_Down: Counter Down Mode
+  *            @arg TIM5_CounterMode_CenterAligned1: Counter Central aligned Mode 1
+  *            @arg TIM5_CounterMode_CenterAligned2: Counter Central aligned Mode 2
+  *            @arg TIM5_CounterMode_CenterAligned3: Counter Central aligned Mode 3        
+  * @param  TIM5_Period: This parameter must be a value between 0x0000 and 0xFFFF.
+  * @retval None
+  */
+
+void TIM5_TimeBaseInit(TIM5_Prescaler_TypeDef TIM5_Prescaler,
+                       TIM5_CounterMode_TypeDef TIM5_CounterMode,
+                       uint16_t TIM5_Period)
+{
+
+  assert_param(IS_TIM5_PRESCALER(TIM5_Prescaler));
+  assert_param(IS_TIM5_COUNTER_MODE(TIM5_CounterMode));
+
+
+
+  /* Set the Autoreload value */
+  TIM5->ARRH = (uint8_t)(TIM5_Period >> 8) ;
+  TIM5->ARRL = (uint8_t)(TIM5_Period);
+
+  /* Set the Prescaler value */
+  TIM5->PSCR = (uint8_t)(TIM5_Prescaler);
+
+  /* Select the Counter Mode */
+  TIM5->CR1 &= (uint8_t)((uint8_t)(~TIM_CR1_CMS)) & ((uint8_t)(~TIM_CR1_DIR));
+  TIM5->CR1 |= (uint8_t)(TIM5_CounterMode);
+
+  /* Generate an update event to reload the Prescaler value immediately */
+  TIM5->EGR = TIM5_EventSource_Update;
+}
+
+/**
+  * @brief  Configures the TIM5 Prescaler.
+  * @param  Prescaler: Specifies the Prescaler Register value
+  *          This parameter can be one of the following values:
+  *            @arg TIM5_Prescaler_1: Time base Prescaler = 1 (No effect)
+  *            @arg TIM5_Prescaler_2: Time base Prescaler = 2
+  *            @arg TIM5_Prescaler_4: Time base Prescaler = 4
+  *            @arg TIM5_Prescaler_8: Time base Prescaler = 8
+  *            @arg TIM5_Prescaler_16: Time base Prescaler = 16
+  *            @arg TIM5_Prescaler_32: Time base Prescaler = 32
+  *            @arg TIM5_Prescaler_64: Time base Prescaler = 64
+  *            @arg TIM5_Prescaler_128: Time base Prescaler = 128  
+  * @param  TIM5_PSCReloadMode: Specifies the TIM5 Prescaler Reload mode.
+  *          This parameter can be one of the following values:
+  *            @arg TIM5_PSCReloadMode_Update: Prescaler value is reloaded at every update
+  *            @arg TIM5_PSCReloadMode_Immediate: Prescaler value is reloaded at every update  
+  * @retval None
+  */
+void TIM5_PrescalerConfig(TIM5_Prescaler_TypeDef Prescaler,
+                          TIM5_PSCReloadMode_TypeDef TIM5_PSCReloadMode)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM5_PRESCALER(Prescaler));
+  assert_param(IS_TIM5_PRESCALER_RELOAD(TIM5_PSCReloadMode));
+
+  /* Set the Prescaler value */
+  TIM5->PSCR = (uint8_t)(Prescaler);
+
+  /* Set or reset the UG Bit */
+  if (TIM5_PSCReloadMode == TIM5_PSCReloadMode_Immediate)
+  {
+    TIM5->EGR |= TIM_EGR_UG ;
+  }
+  else
+  {
+    TIM5->EGR &= (uint8_t)(~TIM_EGR_UG) ;
+  }
+}
+
+/**
+  * @brief  Specifies the TIM5 Counter Mode to be used.
+  * @param  TIM5_CounterMode: Specifies the Counter Mode to be used
+  *          This parameter can be one of the following values:
+  *            @arg TIM5_CounterMode_Up: Counter Up Mode
+  *            @arg TIM5_CounterMode_Down: Counter Down Mode
+  *            @arg TIM5_CounterMode_CenterAligned1: Counter Central aligned Mode 1
+  *            @arg TIM5_CounterMode_CenterAligned2: Counter Central aligned Mode 2
+  *            @arg TIM5_CounterMode_CenterAligned3: Counter Central aligned Mode 3      
+  * @retval None
+  */
+void TIM5_CounterModeConfig(TIM5_CounterMode_TypeDef TIM5_CounterMode)
+{
+  uint8_t tmpcr1 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM5_COUNTER_MODE(TIM5_CounterMode));
+
+  tmpcr1 = TIM5->CR1;
+
+  /* Reset the CMS and DIR Bits */
+  tmpcr1 &= (uint8_t)((uint8_t)(~TIM_CR1_CMS) & (uint8_t)(~TIM_CR1_DIR));
+
+  /* Set the Counter Mode */
+  tmpcr1 |= (uint8_t)TIM5_CounterMode;
+
+  TIM5->CR1 = tmpcr1;
+}
+
+/**
+  * @brief  Sets the TIM5 Counter Register value.
+  * @param  Counter: Specifies the Counter register new value.
+  *          This parameter is between 0x0000 and 0xFFFF.
+  * @retval None
+  */
+void TIM5_SetCounter(uint16_t Counter)
+{
+
+  /* Set the Counter Register value */
+  TIM5->CNTRH = (uint8_t)(Counter >> 8);
+  TIM5->CNTRL = (uint8_t)(Counter);
+}
+
+/**
+  * @brief  Sets the TIM5 Autoreload Register value.
+  * @param  Autoreload: Specifies the Autoreload register new value.
+  *          This parameter is between 0x0000 and 0xFFFF.
+  * @retval None
+  */
+void TIM5_SetAutoreload(uint16_t Autoreload)
+{
+  /* Set the Autoreload Register value */
+  TIM5->ARRH = (uint8_t)(Autoreload >> 8);
+  TIM5->ARRL = (uint8_t)(Autoreload);
+}
+
+/**
+  * @brief  Gets the TIM5 Counter value.
+  * @param  None
+  * @retval Counter Register value.
+  */
+uint16_t TIM5_GetCounter(void)
+{
+  uint16_t tmpcnt = 0;
+  uint8_t tmpcntrl, tmpcntrh;
+
+  tmpcntrh = TIM5->CNTRH;
+  tmpcntrl = TIM5->CNTRL;
+
+  tmpcnt = (uint16_t)(tmpcntrl);
+  tmpcnt |= (uint16_t)((uint16_t)tmpcntrh << 8);
+  /* Get the Counter Register value */
+  return ((uint16_t)tmpcnt);
+}
+
+/**
+  * @brief  Gets the TIM5 Prescaler value.
+  * @param  None
+  * @retval TIM5 Prescaler, it can be one of the following values:
+  *            - TIM5_Prescaler_1: Time base Prescaler = 1 (No effect)
+  *            - TIM5_Prescaler_2: Time base Prescaler = 2
+  *            - TIM5_Prescaler_4: Time base Prescaler = 4
+  *            - TIM5_Prescaler_8: Time base Prescaler = 8
+  *            - TIM5_Prescaler_16: Time base Prescaler = 16
+  *            - TIM5_Prescaler_32: Time base Prescaler = 32
+  *            - TIM5_Prescaler_64: Time base Prescaler = 64
+  *            - TIM5_Prescaler_128: Time base Prescaler = 128    
+  */
+TIM5_Prescaler_TypeDef TIM5_GetPrescaler(void)
+{
+  /* Get the Prescaler Register value */
+  return ((TIM5_Prescaler_TypeDef)TIM5->PSCR);
+}
+
+/**
+  * @brief  Enables or Disables the TIM5 Update event.
+  * @param  NewState: The new state of the TIM5 peripheral Preload register.
+  *          This parameter can be ENABLE or DISABLE
+  * @retval None
+  */
+
+void TIM5_UpdateDisableConfig(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Set or Reset the UDIS Bit */
+  if (NewState != DISABLE)
+  {
+    TIM5->CR1 |= TIM_CR1_UDIS;
+  }
+  else
+  {
+    TIM5->CR1 &= (uint8_t)(~TIM_CR1_UDIS);
+  }
+}
+
+/**
+  * @brief  Selects the TIM5 Update Request Interrupt source.
+  * @param  TIM5_UpdateSource: Specifies the Update source.
+  *          This parameter can be one of the following values:
+  *            @arg TIM5_UpdateSource_Global: Global Update request source
+  *            @arg TIM5_UpdateSource_Regular: Regular Update request source 
+  * @retval None
+  */
+void TIM5_UpdateRequestConfig(TIM5_UpdateSource_TypeDef TIM5_UpdateSource)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM5_UPDATE_SOURCE(TIM5_UpdateSource));
+
+  /* Set or Reset the URS Bit */
+  if (TIM5_UpdateSource == TIM5_UpdateSource_Regular)
+  {
+    TIM5->CR1 |= TIM_CR1_URS ;
+  }
+  else
+  {
+    TIM5->CR1 &= (uint8_t)(~TIM_CR1_URS);
+  }
+}
+
+/**
+  * @brief  Enables or disables TIM5 peripheral Preload register on ARR.
+  * @param  NewState: The new state of the TIM5 peripheral Preload register.
+  *          This parameter can be ENABLE or DISABLE
+  * @retval None
+  */
+void TIM5_ARRPreloadConfig(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Set or Reset the ARPE Bit */
+  if (NewState != DISABLE)
+  {
+    TIM5->CR1 |= TIM_CR1_ARPE;
+  }
+  else
+  {
+    TIM5->CR1 &= (uint8_t)(~TIM_CR1_ARPE);
+  }
+}
+
+/**
+  * @brief  Selects the TIM’s One Pulse Mode.
+  * @param  TIM5_OPMode: Specifies the OPM Mode to be used.
+  *          This parameter can be one of the following values:
+  *            @arg TIM5_OPMode_Single: Single one Pulse mode (OPM Active)
+  *            @arg TIM5_OPMode_Repetitive: Single one Pulse mode (OPM Active)  
+  * @retval None
+  */
+void TIM5_SelectOnePulseMode(TIM5_OPMode_TypeDef TIM5_OPMode)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM5_OPM_MODE(TIM5_OPMode));
+
+  /* Set or Reset the OPM Bit */
+  if (TIM5_OPMode == TIM5_OPMode_Single)
+  {
+    TIM5->CR1 |= TIM_CR1_OPM ;
+  }
+  else
+  {
+    TIM5->CR1 &= (uint8_t)(~TIM_CR1_OPM);
+  }
+}
+
+/**
+  * @brief  Enables or disables the TIM5 peripheral.
+  * @param  NewState: The new state of the TIM5 peripheral.
+  *          This parameter can be ENABLE or DISABLE
+  * @retval None
+  */
+void TIM5_Cmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* set or Reset the CEN Bit */
+  if (NewState != DISABLE)
+  {
+    TIM5->CR1 |= TIM_CR1_CEN;
+  }
+  else
+  {
+    TIM5->CR1 &= (uint8_t)(~TIM_CR1_CEN);
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM5_Group2 Output Compare management functions
+ *  @brief    Output Compare management functions 
+ *
+@verbatim   
+ ===============================================================================
+                        Output Compare management functions
+ ===============================================================================  
+   
+       ===================================================================      
+              TIM5 Driver: how to use it in Output Compare Mode
+       =================================================================== 
+       To use the Timer in Output Compare mode, the following steps are mandatory:
+       
+       1. Enable TIM5 clock using CLK_PeripheralClockConfig(CLK_Peripheral_TIM5, ENABLE) function.
+       
+       2. Configure the TIM5 pins in output mode by configuring the corresponding GPIO pins
+          
+       3. Configure the Time base unit as described in the first part of this driver, if needed,
+          otherwise the Timer will run with the default configuration:
+          - Autoreload value = 0xFFFF
+          - Prescaler value = 0x0000
+          - Counter mode = Up counting
+      
+       4. Call TIM5_OCxInit() to configure the channel x with the desired parameters
+          including:
+          - TIM5 Output Compare mode: TIM5_OCMode
+          - TIM5 Output State: TIM5_OutputState
+          - TIM5 Pulse value: TIM5_Pulse
+          - TIM5 Output Compare Polarity: TIM5_OCPolarity
+          - TIM5 Output Idle State: TIM5_OCIdleState
+       
+       5. Call the TIM5_Cmd(ENABLE) function to enable the TIM5 counter.
+       
+       Note1: All other functions can be used separately to modify, if needed,
+          a specific feature of the Timer. 
+       
+       Note2: If the corresponding interrupt or DMA request are needed, the user should:
+              1. Enable global interrupts (or the DMA) to use the TIM5 interrupts (or DMA requests). 
+              2. Enable the corresponding interrupt (or DMA request) using the function 
+              TIM5_ITConfig(TIM5_IT_CCx) (or TIM5_DMACmd(TIM5_DMASource_CCx))   
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the TIM5 Channel1 according to the specified parameters.
+  * @param  TIM5_OCMode: Output Compare Mode 
+  *          This parameter can be one of the following values:
+  *            @arg TIM5_OCMode_Timing: Timing (Frozen) Mode
+  *            @arg TIM5_OCMode_Active: Active Mode
+  *            @arg TIM5_OCMode_Inactive: Inactive Mode
+  *            @arg TIM5_OCMode_Toggle: Toggle Mode
+  *            @arg TIM5_OCMode_PWM1: PWM Mode 1
+  *            @arg TIM5_OCMode_PWM2: PWM Mode 2          
+  * @param  TIM5_OutputState: Output state
+  *          This parameter can be one of the following values:
+  *            @arg TIM5_OutputState_Disable: Output compare State disabled (channel output disabled)
+  *            @arg TIM5_OutputState_Enable: Output compare State enabled (channel output enabled)
+  * @param  TIM5_Pulse: This parameter must be a value between 0x0000 and 0xFFFF.
+  * @param  TIM5_OCPolarity: Polarity
+  *          This parameter can be one of the following values:
+  *            @arg TIM5_OCPolarity_High: Output compare polarity  = High
+  *            @arg TIM5_OCPolarity_Low: Output compare polarity  = Low 
+  * @param  TIM5_OCIdleState: Output Compare Idle State
+  *          This parameter can be one of the following values:
+  *            @arg TIM5_OCIdleState_Reset: Output Compare Idle state  = Reset
+  *            @arg TIM5_OCIdleState_Set: Output Compare Idle state  = Set
+  * @retval None
+  */
+void TIM5_OC1Init(TIM5_OCMode_TypeDef TIM5_OCMode,
+                  TIM5_OutputState_TypeDef TIM5_OutputState,
+                  uint16_t TIM5_Pulse,
+                  TIM5_OCPolarity_TypeDef TIM5_OCPolarity,
+                  TIM5_OCIdleState_TypeDef TIM5_OCIdleState)
+{
+  uint8_t tmpccmr1 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM5_OC_MODE(TIM5_OCMode));
+  assert_param(IS_TIM5_OUTPUT_STATE(TIM5_OutputState));
+  assert_param(IS_TIM5_OC_POLARITY(TIM5_OCPolarity));
+  assert_param(IS_TIM5_OCIDLE_STATE(TIM5_OCIdleState));
+
+  tmpccmr1 = TIM5->CCMR1;
+
+  /* Disable the Channel 1: Reset the CCE Bit */
+  TIM5->CCER1 &= (uint8_t)(~TIM_CCER1_CC1E);
+  /* Reset the Output Compare Bits */
+  tmpccmr1 &= (uint8_t)(~TIM_CCMR_OCM);
+
+  /* Set the Output Compare Mode */
+  tmpccmr1 |= (uint8_t)TIM5_OCMode;
+
+  TIM5->CCMR1 = tmpccmr1;
+
+  /* Set the Output State */
+  if (TIM5_OutputState == TIM5_OutputState_Enable)
+  {
+    TIM5->CCER1 |= TIM_CCER1_CC1E;
+  }
+  else
+  {
+    TIM5->CCER1 &= (uint8_t)(~TIM_CCER1_CC1E);
+  }
+
+  /* Set the Output Polarity */
+  if (TIM5_OCPolarity == TIM5_OCPolarity_Low)
+  {
+    TIM5->CCER1 |= TIM_CCER1_CC1P;
+  }
+  else
+  {
+    TIM5->CCER1 &= (uint8_t)(~TIM_CCER1_CC1P);
+  }
+
+  /* Set the Output Idle state */
+  if (TIM5_OCIdleState == TIM5_OCIdleState_Set)
+  {
+    TIM5->OISR |= TIM_OISR_OIS1;
+  }
+  else
+  {
+    TIM5->OISR &= (uint8_t)(~TIM_OISR_OIS1);
+  }
+
+  /* Set the Pulse value */
+  TIM5->CCR1H = (uint8_t)(TIM5_Pulse >> 8);
+  TIM5->CCR1L = (uint8_t)(TIM5_Pulse);
+}
+
+/**
+  * @brief  Initializes the TIM5 Channel2 according to the specified parameters.
+  * @param  TIM5_OCMode: Output Compare Mode 
+  *          This parameter can be one of the following values:
+  *            @arg TIM5_OCMode_Timing: Timing (Frozen) Mode
+  *            @arg TIM5_OCMode_Active: Active Mode
+  *            @arg TIM5_OCMode_Inactive: Inactive Mode
+  *            @arg TIM5_OCMode_Toggle: Toggle Mode
+  *            @arg TIM5_OCMode_PWM1: PWM Mode 1
+  *            @arg TIM5_OCMode_PWM2: PWM Mode 2          
+  * @param  TIM5_OutputState: Output state
+  *          This parameter can be one of the following values:
+  *            @arg TIM5_OutputState_Disable: Output compare State disabled (channel output disabled)
+  *            @arg TIM5_OutputState_Enable: Output compare State enabled (channel output enabled)
+  * @param  TIM5_Pulse: This parameter must be a value between 0x0000 and 0xFFFF.
+  * @param  TIM5_OCPolarity: Polarity
+  *          This parameter can be one of the following values:
+  *            @arg TIM5_OCPolarity_High: Output compare polarity  = High
+  *            @arg TIM5_OCPolarity_Low: Output compare polarity  = Low 
+  * @param  TIM5_OCIdleState: Output Compare Idle State
+  *          This parameter can be one of the following values:
+  *            @arg TIM5_OCIdleState_Reset: Output Compare Idle state  = Reset
+  *            @arg TIM5_OCIdleState_Set: Output Compare Idle state  = Set
+  * @retval None
+  */
+void TIM5_OC2Init(TIM5_OCMode_TypeDef TIM5_OCMode,
+                  TIM5_OutputState_TypeDef TIM5_OutputState,
+                  uint16_t TIM5_Pulse,
+                  TIM5_OCPolarity_TypeDef TIM5_OCPolarity,
+                  TIM5_OCIdleState_TypeDef TIM5_OCIdleState)
+{
+  uint8_t tmpccmr2 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM5_OC_MODE(TIM5_OCMode));
+  assert_param(IS_TIM5_OUTPUT_STATE(TIM5_OutputState));
+  assert_param(IS_TIM5_OC_POLARITY(TIM5_OCPolarity));
+  assert_param(IS_TIM5_OCIDLE_STATE(TIM5_OCIdleState));
+
+  tmpccmr2 = TIM5->CCMR2;
+
+  /* Disable the Channel 2: Reset the CCE Bit */
+  TIM5->CCER1 &= (uint8_t)(~TIM_CCER1_CC2E);
+
+  /* Reset the Output Compare Bits */
+  tmpccmr2 &= (uint8_t)(~TIM_CCMR_OCM);
+
+  /* Set the Output Compare Mode */
+  tmpccmr2 |= (uint8_t)TIM5_OCMode;
+
+  TIM5->CCMR2 = tmpccmr2;
+
+  /* Set the Output State */
+  if (TIM5_OutputState == TIM5_OutputState_Enable)
+  {
+    TIM5->CCER1 |= TIM_CCER1_CC2E;
+  }
+  else
+  {
+    TIM5->CCER1 &= (uint8_t)(~TIM_CCER1_CC2E);
+  }
+
+  /* Set the Output Polarity */
+  if (TIM5_OCPolarity == TIM5_OCPolarity_Low)
+  {
+    TIM5->CCER1 |= TIM_CCER1_CC2P;
+  }
+  else
+  {
+    TIM5->CCER1 &= (uint8_t)(~TIM_CCER1_CC2P);
+  }
+
+
+  /* Set the Output Idle state */
+  if (TIM5_OCIdleState == TIM5_OCIdleState_Set)
+  {
+    TIM5->OISR |= TIM_OISR_OIS2;
+  }
+  else
+  {
+    TIM5->OISR &= (uint8_t)(~TIM_OISR_OIS2);
+  }
+
+  /* Set the Pulse value */
+  TIM5->CCR2H = (uint8_t)(TIM5_Pulse >> 8);
+  TIM5->CCR2L = (uint8_t)(TIM5_Pulse);
+}
+
+/**
+  * @brief  Configures the Break feature, dead time, Lock level, the OSSI,
+  *         and the AOE(automatic output enable).
+  * @param  TIM5_OSSIState: Off-State Selection for Idle mode states.
+  *          This parameter can be one of the following values:
+  *            @arg TIM5_OSSIState_Enable: Off-State Selection for Idle mode enabled
+  *            @arg TIM5_OSSIState_Disable: Off-State Selection for Idle mode disabled 
+  * @param  TIM5_LockLevel: Lock level.
+  *          This parameter can be one of the following values:
+  *            @arg TIM5_LockLevel_Off: Lock option disabled
+  *            @arg TIM5_LockLevel_1: Select Lock Level 1
+  *            @arg TIM5_LockLevel_2: Select Lock Level 2
+  *            @arg TIM5_LockLevel_3: Select Lock Level 3    
+  * @param  TIM5_BreakState: Break Input enable/disable .
+  *          This parameter can be one of the following values:
+  *            @arg TIM5_BreakState_Disable: Break State disabled (break option disabled)
+  *            @arg TIM5_BreakState_Enable: Break State enabled (break option enabled) 
+  * @param  TIM5_BreakPolarity: Break Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM5_BreakPolarity_High: if Break, channel polarity = High
+  *            @arg TIM5_BreakPolarity_Low: if Break, channel polarity = Low   
+  * @param  TIM5_AutomaticOutput: TIM5 AOE Bit Set/Reset .
+  *          This parameter can be one of the following values:
+  *            @arg TIM5_AutomaticOutput_Enable: Automatic Output option enabled
+  *            @arg TIM5_AutomaticOutput_Disable: Automatic Output option disabled
+  * @retval None
+  */
+void TIM5_BKRConfig(TIM5_OSSIState_TypeDef TIM5_OSSIState,
+                    TIM5_LockLevel_TypeDef TIM5_LockLevel,
+                    TIM5_BreakState_TypeDef TIM5_BreakState,
+                    TIM5_BreakPolarity_TypeDef TIM5_BreakPolarity,
+                    TIM5_AutomaticOutput_TypeDef TIM5_AutomaticOutput)
+
+{
+  /* Check the parameters */
+  assert_param(IS_TIM5_OSSI_STATE(TIM5_OSSIState));
+  assert_param(IS_TIM5_LOCK_LEVEL(TIM5_LockLevel));
+  assert_param(IS_TIM5_BREAK_STATE(TIM5_BreakState));
+  assert_param(IS_TIM5_BREAK_POLARITY(TIM5_BreakPolarity));
+  assert_param(IS_TIM5_AUTOMATIC_OUTPUT_STATE(TIM5_AutomaticOutput));
+
+
+
+  /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSI State,
+  the dead time value and the Automatic Output Enable Bit */
+  TIM5->BKR = (uint8_t)((uint8_t)((uint8_t)((uint8_t)((uint8_t)TIM5_OSSIState | (uint8_t)TIM5_LockLevel) | \
+                                  (uint8_t)((uint8_t)TIM5_BreakState | (uint8_t)TIM5_BreakPolarity)) | \
+                                  TIM5_AutomaticOutput));
+}
+
+/**
+  * @brief  Enables or disables the TIM5 peripheral Main Outputs.
+  * @param  NewState: The new state of the TIM5 peripheral.
+  *          This parameter can be ENABLE or DISABLE
+  * @retval None
+  */
+void TIM5_CtrlPWMOutputs(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Set or Reset the MOE Bit */
+
+  if (NewState != DISABLE)
+  {
+    TIM5->BKR |= TIM_BKR_MOE ;
+  }
+  else
+  {
+    TIM5->BKR &= (uint8_t)(~TIM_BKR_MOE) ;
+  }
+}
+
+/**
+  * @brief  Selects the TIM5 Output Compare Mode. This function disables the
+  *         selected channel before changing the Output Compare Mode. User has to
+  *         enable this channel using TIM5_CCxCmd and TIM5_CCxNCmd functions.
+  * @param  TIM5_Channel: Specifies the TIM5 Channel.
+  *          This parameter can be one of the following values:
+  *            @arg TIM5_Channel_1: Channel 1
+  *            @arg TIM5_Channel_2: Channel 2  
+  * @param  TIM5_OCMode: Specifies the TIM5 Output Compare Mode.
+  *          This parameter can be one of the following values:
+  *            @arg TIM5_OCMode_Timing: Timing (Frozen) Mode
+  *            @arg TIM5_OCMode_Active: Active Mode
+  *            @arg TIM5_OCMode_Inactive: Inactive Mode
+  *            @arg TIM5_OCMode_Toggle: Toggle Mode
+  *            @arg TIM5_OCMode_PWM1: PWM Mode 1
+  *            @arg TIM5_OCMode_PWM2: PWM Mode 2    
+  * @retval None
+  */
+void TIM5_SelectOCxM(TIM5_Channel_TypeDef TIM5_Channel,
+                     TIM5_OCMode_TypeDef TIM5_OCMode)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM5_CHANNEL(TIM5_Channel));
+  assert_param(IS_TIM5_OCM(TIM5_OCMode));
+
+  if (TIM5_Channel == TIM5_Channel_1)
+  {
+    /* Disable the Channel 1: Reset the CCE Bit */
+    TIM5->CCER1 &= (uint8_t)(~TIM_CCER1_CC1E);
+
+    /* Reset the Output Compare Bits */
+    TIM5->CCMR1 &= (uint8_t)(~TIM_CCMR_OCM);
+
+    /* Set the Output Compare Mode */
+    TIM5->CCMR1 |= (uint8_t)TIM5_OCMode;
+  }
+  else /* if (TIM5_Channel == TIM5_Channel_2) */
+  {
+    /* Disable the Channel 2: Reset the CCE Bit */
+    TIM5->CCER1 &= (uint8_t)(~TIM_CCER1_CC2E);
+
+    /* Reset the Output Compare Bits */
+    TIM5->CCMR2 &= (uint8_t)(~TIM_CCMR_OCM);
+
+    /* Set the Output Compare Mode */
+    TIM5->CCMR2 |= (uint8_t)TIM5_OCMode;
+  }
+}
+
+/**
+  * @brief  Sets the TIM5 Capture Compare1 Register value.
+  * @param  Compare: Specifies the Capture Compare1 register new value.
+  *         This parameter is between 0x0000 and 0xFFFF.
+  * @retval None
+  */
+void TIM5_SetCompare1(uint16_t Compare)
+{
+  /* Set the Capture Compare1 Register value */
+  TIM5->CCR1H = (uint8_t)(Compare >> 8);
+  TIM5->CCR1L = (uint8_t)(Compare);
+}
+
+/**
+  * @brief  Sets the TIM5 Capture Compare2 Register value.
+  * @param  Compare: Specifies the Capture Compare2 register new value.
+  *         This parameter is between 0x0000 and 0xFFFF.
+  * @retval None
+  */
+void TIM5_SetCompare2(uint16_t Compare)
+{
+  /* Set the Capture Compare2 Register value */
+  TIM5->CCR2H = (uint8_t)(Compare >> 8);
+  TIM5->CCR2L = (uint8_t)(Compare);
+}
+
+/**
+  * @brief  Forces the TIM5 Channel1 output waveform to active or inactive level.
+  * @param  TIM5_ForcedAction: Specifies the forced Action to be set to the output waveform.
+  *          This parameter can be one of the following values:
+  *            @arg TIM5_ForcedAction_Active: Output Reference is forced low 
+  *            @arg TIM5_ForcedAction_Inactive: Output Reference is forced high 
+  * @retval None
+  */
+void TIM5_ForcedOC1Config(TIM5_ForcedAction_TypeDef TIM5_ForcedAction)
+{
+  uint8_t tmpccmr1 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM5_FORCED_ACTION(TIM5_ForcedAction));
+
+  tmpccmr1 = TIM5->CCMR1;
+
+  /* Reset the OCM Bits */
+  tmpccmr1 &= (uint8_t)(~TIM_CCMR_OCM);
+
+  /* Configure The Forced output Mode */
+  tmpccmr1 |= (uint8_t)TIM5_ForcedAction;
+
+  TIM5->CCMR1 = tmpccmr1;
+}
+
+/**
+  * @brief  Forces the TIM5 Channel2 output waveform to active or inactive level.
+  * @param  TIM5_ForcedAction: Specifies the forced Action to be set to the output waveform.
+  *          This parameter can be one of the following values:
+  *            @arg TIM5_ForcedAction_Active: Output Reference is forced low 
+  *            @arg TIM5_ForcedAction_Inactive: Output Reference is forced high 
+  * @retval None
+  */
+void TIM5_ForcedOC2Config(TIM5_ForcedAction_TypeDef TIM5_ForcedAction)
+{
+  uint8_t tmpccmr2 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM5_FORCED_ACTION(TIM5_ForcedAction));
+
+  tmpccmr2 = TIM5->CCMR2;
+
+  /* Reset the OCM Bits */
+  tmpccmr2 &= (uint8_t)(~TIM_CCMR_OCM);
+
+  /* Configure The Forced output Mode */
+  tmpccmr2 |= (uint8_t)TIM5_ForcedAction;
+
+  TIM5->CCMR2 = tmpccmr2;
+}
+
+/**
+  * @brief  Enables or disables the TIM5 peripheral Preload Register on CCR1.
+  * @param  NewState: The new state of the Capture Compare Preload register.
+  *          This parameter can be ENABLE or DISABLE
+  * @retval None
+  */
+void TIM5_OC1PreloadConfig(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Set or Reset the OC1PE Bit */
+  if (NewState != DISABLE)
+  {
+    TIM5->CCMR1 |= TIM_CCMR_OCxPE ;
+  }
+  else
+  {
+    TIM5->CCMR1 &= (uint8_t)(~TIM_CCMR_OCxPE) ;
+  }
+}
+
+/**
+  * @brief  Enables or disables the TIM5 peripheral Preload Register on CCR2.
+  * @param  NewState: The new state of the Capture Compare Preload register.
+  *          This parameter can be ENABLE or DISABLE
+  * @retval None
+  */
+void TIM5_OC2PreloadConfig(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Set or Reset the OC2PE Bit */
+  if (NewState != DISABLE)
+  {
+    TIM5->CCMR2 |= TIM_CCMR_OCxPE ;
+  }
+  else
+  {
+    TIM5->CCMR2 &= (uint8_t)(~TIM_CCMR_OCxPE) ;
+  }
+}
+
+/**
+  * @brief  Configures the TIM5 Capture Compare 1 Fast feature.
+  * @param  NewState: The new state of the Output Compare Fast Enable bit.
+  *          This parameter can be ENABLE or DISABLE
+  * @retval None
+  */
+void TIM5_OC1FastConfig(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Set or Reset the OC1FE Bit */
+  if (NewState != DISABLE)
+  {
+    TIM5->CCMR1 |= TIM_CCMR_OCxFE ;
+  }
+  else
+  {
+    TIM5->CCMR1 &= (uint8_t)(~TIM_CCMR_OCxFE) ;
+  }
+}
+
+/**
+  * @brief  Configures the TIM5 Capture Compare 2 Fast feature.
+  * @param  NewState: The new state of the Output Compare Fast Enable bit.
+  *          This parameter can be ENABLE or DISABLE
+  * @retval None
+  */
+
+void TIM5_OC2FastConfig(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Set or Reset the OC2FE Bit */
+  if (NewState != DISABLE)
+  {
+    TIM5->CCMR2 |= TIM_CCMR_OCxFE ;
+  }
+  else
+  {
+    TIM5->CCMR2 &= (uint8_t)(~TIM_CCMR_OCxFE) ;
+  }
+}
+
+/**
+  * @brief  Configures the TIM5 Channel 1 polarity.
+  * @param  TIM5_OCPolarity: Specifies the OC1 Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM5_OCPolarity_High: Output compare polarity  = High
+  *            @arg TIM5_OCPolarity_Low: Output compare polarity  = Low 
+  * @retval None
+  */
+void TIM5_OC1PolarityConfig(TIM5_OCPolarity_TypeDef TIM5_OCPolarity)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM5_OC_POLARITY(TIM5_OCPolarity));
+
+  /* Set or Reset the CC1P Bit */
+  if (TIM5_OCPolarity == TIM5_OCPolarity_Low)
+  {
+    TIM5->CCER1 |= TIM_CCER1_CC1P ;
+  }
+  else
+  {
+    TIM5->CCER1 &= (uint8_t)(~TIM_CCER1_CC1P) ;
+  }
+}
+
+/**
+  * @brief  Configures the TIM5 Channel 2 polarity.
+  * @param  TIM5_OCPolarity: Specifies the OC2 Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM5_OCPolarity_High: Output compare polarity  = High
+  *            @arg TIM5_OCPolarity_Low: Output compare polarity  = Low 
+  * @retval None
+  */
+void TIM5_OC2PolarityConfig(TIM5_OCPolarity_TypeDef TIM5_OCPolarity)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM5_OC_POLARITY(TIM5_OCPolarity));
+
+  /* Set or Reset the CC2P Bit */
+  if (TIM5_OCPolarity == TIM5_OCPolarity_Low)
+  {
+    TIM5->CCER1 |= TIM_CCER1_CC2P ;
+  }
+  else
+  {
+    TIM5->CCER1 &= (uint8_t)(~TIM_CCER1_CC2P) ;
+  }
+}
+
+/**
+  * @brief  Enables or disables the TIM5 Capture Compare Channel x.
+  * @param  TIM5_Channel: Specifies the TIM5 Channel.
+  *          This parameter can be one of the following values:
+  *            @arg TIM5_Channel_1: Channel 1
+  *            @arg TIM5_Channel_2: Channel 2  
+  * @param  NewState: Specifies the TIM5 Channel CCxE bit new state.
+  *          This parameter can be ENABLE or DISABLE
+  * @retval None
+  */
+void TIM5_CCxCmd(TIM5_Channel_TypeDef TIM5_Channel,
+                 FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM5_CHANNEL(TIM5_Channel));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (TIM5_Channel == TIM5_Channel_1)
+  {
+    /* Set or Reset the CC1E Bit */
+    if (NewState != DISABLE)
+    {
+      TIM5->CCER1 |= TIM_CCER1_CC1E ;
+    }
+    else
+    {
+      TIM5->CCER1 &= (uint8_t)(~TIM_CCER1_CC1E) ;
+    }
+
+  }
+  else /* if (TIM5_Channel == TIM5_Channel_2) */
+  {
+    /* Set or Reset the CC2E Bit */
+    if (NewState != DISABLE)
+    {
+      TIM5->CCER1 |= TIM_CCER1_CC2E;
+    }
+    else
+    {
+      TIM5->CCER1 &= (uint8_t)(~TIM_CCER1_CC2E) ;
+    }
+  }
+}
+
+/** @defgroup TIM5_Group3 Input Capture management functions
+ *  @brief    Input Capture management functions 
+ *
+@verbatim   
+ ===============================================================================
+                      Input Capture management functions
+ ===============================================================================  
+   
+       ===================================================================      
+              TIM5 Driver: how to use it in Input Capture Mode
+       =================================================================== 
+       To use the Timer in Input Capture mode, the following steps are mandatory:
+       
+       1. Enable TIM5 clock using CLK_PeripheralClockConfig(CLK_Peripheral_TIM5, ENABLE) function.
+       
+       2. Configure the TIM5 pins in input mode by configuring the corresponding GPIO pins
+       
+       3. Configure the Time base unit as described in the first part of this driver, if needed,
+          otherwise the Timer will run with the default configuration:
+          - Autoreload value = 0xFFFF
+          - Prescaler value = 0x0
+          - Counter mode = Up counting
+       
+       4. Call TIM5_ICInit() to configure the desired channel to measure only 
+          frequency or duty cycle of the input signal using the corresponding configuration: 
+          - TIM5 Channel: TIM5_Channel
+          - TIM5 Input Capture polarity: TIM5_ICPolarity
+          - TIM5 Input Capture selection: TIM5_ICSelection
+          - TIM5 Input Capture Prescaler: TIM5_ICPSC
+          - TIM5 Input Capture filter value
+          or,
+          Call TIM5_PWMIConfig() to configure the desired channels with the 
+          corresponding configuration and to measure the frequency and the duty
+          cycle of the input signal.
+          
+       5. Enable global interrupts or the DMA to read the measured frequency. 
+          
+       6. Enable the corresponding interrupt (or DMA request) to read the captured value,
+          using the function TIM5_ITConfig(TIM5_IT_CCx) (or TIM5_DMACmd(TIM5_DMASource_CCx))
+       
+       7. Call the TIM5_Cmd(ENABLE) function to enable the TIM5 counter.
+       
+       8. Use TIM5_GetCapturex() to read the captured value corresponding to
+          channel x.
+       
+       Note1: All other functions can be used separately to modify, if needed,
+          a specific feature of the Timer. 
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the TIM5 peripheral according to the specified parameters.
+  * @param  TIM5_Channel: TIM5 Channel
+  *          This parameter can be one of the following values:
+  *            @arg TIM5_Channel_1: Channel 1
+  *            @arg TIM5_Channel_2: Channel 2     
+  * @param  TIM5_ICPolarity: Input Capture Polarity
+  *          This parameter can be one of the following values:
+  *            @arg TIM5_ICPolarity_Rising: Input Capture on Rising Edge
+  *            @arg TIM5_ICPolarity_Falling: Input Capture on Falling Edge  
+  * @param  TIM5_ICSelection: Input Capture Selection
+  *          This parameter can be one of the following values:
+  *            @arg TIM5_ICSelection_DirectTI: Input Capture mapped on the direct input
+  *            @arg TIM5_ICSelection_IndirectTI: Input Capture mapped on the indirect input
+  *            @arg TIM5_ICSelection_TRGI: Input Capture mapped on the Trigger Input   
+  * @param  TIM5_ICPrescaler: Input Capture Prescaler
+  *          This parameter can be one of the following values:
+  *            @arg TIM5_ICPSC_DIV1: Input Capture Prescaler = 1 (one capture every 1 event)
+  *            @arg TIM5_ICPSC_DIV2: Input Capture Prescaler = 2 (one capture every 2 events)
+  *            @arg TIM5_ICPSC_DIV4: Input Capture Prescaler = 4 (one capture every 4 events)
+  *            @arg TIM5_ICPSC_DIV8: Input Capture Prescaler = 8 (one capture every 8 events)   
+  * @param  TIM5_ICFilter: This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  */
+void TIM5_ICInit(TIM5_Channel_TypeDef TIM5_Channel,
+                 TIM5_ICPolarity_TypeDef TIM5_ICPolarity,
+                 TIM5_ICSelection_TypeDef TIM5_ICSelection,
+                 TIM5_ICPSC_TypeDef TIM5_ICPrescaler,
+                 uint8_t TIM5_ICFilter)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM5_CHANNEL(TIM5_Channel));
+
+  if (TIM5_Channel == TIM5_Channel_1)
+  {
+    /* TI1 Configuration */
+    TI1_Config(TIM5_ICPolarity, TIM5_ICSelection, TIM5_ICFilter);
+
+    /* Set the Input Capture Prescaler value */
+    TIM5_SetIC1Prescaler(TIM5_ICPrescaler);
+  }
+  else /* if (TIM5_Channel == TIM5_Channel_2) */
+  {
+    /* TI2 Configuration */
+    TI2_Config(TIM5_ICPolarity, TIM5_ICSelection, TIM5_ICFilter);
+
+    /* Set the Input Capture Prescaler value */
+    TIM5_SetIC2Prescaler(TIM5_ICPrescaler);
+  }
+}
+
+/**
+  * @brief  Configures the TIM5 peripheral in PWM Input Mode according to the
+  *         specified parameters.
+  * @param  TIM5_Channel: TIM5 Channel
+  *          This parameter can be one of the following values:
+  *            @arg TIM5_Channel_1: Channel 1
+  *            @arg TIM5_Channel_2: Channel 2     
+  * @param  TIM5_ICPolarity: Input Capture Polarity
+  *          This parameter can be one of the following values:
+  *            @arg TIM5_ICPolarity_Rising: Input Capture on Rising Edge
+  *            @arg TIM5_ICPolarity_Falling: Input Capture on Falling Edge  
+  * @param  TIM5_ICSelection: Input Capture Selection
+  *          This parameter can be one of the following values:
+  *            @arg TIM5_ICSelection_DirectTI: Input Capture mapped on the direct input
+  *            @arg TIM5_ICSelection_IndirectTI: Input Capture mapped on the indirect input
+  *            @arg TIM5_ICSelection_TRGI: Input Capture mapped on the Trigger Input   
+  * @param  TIM5_ICPrescaler: Input Capture Prescaler
+  *          This parameter can be one of the following values:
+  *            @arg TIM5_ICPSC_DIV1: Input Capture Prescaler = 1 (one capture every 1 event)
+  *            @arg TIM5_ICPSC_DIV2: Input Capture Prescaler = 2 (one capture every 2 events)
+  *            @arg TIM5_ICPSC_DIV4: Input Capture Prescaler = 4 (one capture every 4 events)
+  *            @arg TIM5_ICPSC_DIV8: Input Capture Prescaler = 8 (one capture every 8 events) 
+  * @retval None
+  */
+void TIM5_PWMIConfig(TIM5_Channel_TypeDef TIM5_Channel,
+                     TIM5_ICPolarity_TypeDef TIM5_ICPolarity,
+                     TIM5_ICSelection_TypeDef TIM5_ICSelection,
+                     TIM5_ICPSC_TypeDef TIM5_ICPrescaler,
+                     uint8_t TIM5_ICFilter)
+{
+  uint8_t icpolarity = TIM5_ICPolarity_Rising;
+  uint8_t icselection = TIM5_ICSelection_DirectTI;
+
+  /* Check the parameters */
+  assert_param(IS_TIM5_CHANNEL(TIM5_Channel));
+
+  /* Select the Opposite Input Polarity */
+  if (TIM5_ICPolarity == TIM5_ICPolarity_Rising)
+  {
+    icpolarity = TIM5_ICPolarity_Falling;
+  }
+  else
+  {
+    icpolarity = TIM5_ICPolarity_Rising;
+  }
+
+  /* Select the Opposite Input */
+  if (TIM5_ICSelection == TIM5_ICSelection_DirectTI)
+  {
+    icselection = TIM5_ICSelection_IndirectTI;
+  }
+  else
+  {
+    icselection = TIM5_ICSelection_DirectTI;
+  }
+
+  if (TIM5_Channel == TIM5_Channel_1)
+  {
+    /* TI1 Configuration */
+    TI1_Config(TIM5_ICPolarity, TIM5_ICSelection,
+               TIM5_ICFilter);
+
+    /* Set the Input Capture Prescaler value */
+    TIM5_SetIC1Prescaler(TIM5_ICPrescaler);
+
+    /* TI2 Configuration */
+    TI2_Config((TIM5_ICPolarity_TypeDef)icpolarity, (TIM5_ICSelection_TypeDef)icselection, TIM5_ICFilter);
+
+    /* Set the Input Capture Prescaler value */
+    TIM5_SetIC2Prescaler(TIM5_ICPrescaler);
+  }
+  else
+  {
+    /* TI2 Configuration */
+    TI2_Config(TIM5_ICPolarity, TIM5_ICSelection,
+               TIM5_ICFilter);
+
+    /* Set the Input Capture Prescaler value */
+    TIM5_SetIC2Prescaler(TIM5_ICPrescaler);
+
+    /* TI1 Configuration */
+    TI1_Config((TIM5_ICPolarity_TypeDef)icpolarity, (TIM5_ICSelection_TypeDef)icselection, TIM5_ICFilter);
+
+    /* Set the Input Capture Prescaler value */
+    TIM5_SetIC1Prescaler(TIM5_ICPrescaler);
+  }
+}
+
+/**
+  * @brief  Gets the TIM5 Input Capture 1 value.
+  * @param  None
+  * @retval Capture Compare 1 Register value.
+  */
+uint16_t TIM5_GetCapture1(void)
+{
+  uint16_t tmpccr1 = 0;
+  uint8_t tmpccr1l, tmpccr1h;
+
+  tmpccr1h = TIM5->CCR1H;
+  tmpccr1l = TIM5->CCR1L;
+
+  tmpccr1 = (uint16_t)(tmpccr1l);
+  tmpccr1 |= (uint16_t)((uint16_t)tmpccr1h << 8);
+  /* Get the Capture 1 Register value */
+  return ((uint16_t)tmpccr1);
+}
+
+/**
+  * @brief  Gets the TIM5 Input Capture 2 value.
+  * @param  None
+  * @retval Capture Compare 2 Register value.
+  */
+uint16_t TIM5_GetCapture2(void)
+{
+  uint16_t tmpccr2 = 0;
+  uint8_t tmpccr2l, tmpccr2h;
+
+  tmpccr2h = TIM5->CCR2H;
+  tmpccr2l = TIM5->CCR2L;
+
+  tmpccr2 = (uint16_t)(tmpccr2l);
+  tmpccr2 |= (uint16_t)((uint16_t)tmpccr2h << 8);
+  /* Get the Capture 2 Register value */
+  return ((uint16_t)tmpccr2);
+}
+
+/**
+  * @brief  Sets the TIM5 Input Capture 1 prescaler.
+  * @param  TIM5_IC1Prescaler: Specifies the Input Capture prescaler new value
+  *          This parameter can be one of the following values:
+  *            @arg TIM5_ICPSC_DIV1: Input Capture Prescaler = 1 (one capture every 1 event)
+  *            @arg TIM5_ICPSC_DIV2: Input Capture Prescaler = 2 (one capture every 2 events)
+  *            @arg TIM5_ICPSC_DIV4: Input Capture Prescaler = 4 (one capture every 4 events)
+  *            @arg TIM5_ICPSC_DIV8: Input Capture Prescaler = 8 (one capture every 8 events) 
+  * @retval None
+  */
+void TIM5_SetIC1Prescaler(TIM5_ICPSC_TypeDef TIM5_IC1Prescaler)
+{
+  uint8_t tmpccmr1 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM5_IC_PRESCALER(TIM5_IC1Prescaler));
+
+  tmpccmr1 = TIM5->CCMR1;
+
+  /* Reset the IC1PSC Bits */
+  tmpccmr1 &= (uint8_t)(~TIM_CCMR_ICxPSC);
+
+  /* Set the IC1PSC value */
+  tmpccmr1 |= (uint8_t)TIM5_IC1Prescaler;
+
+  TIM5->CCMR1 = tmpccmr1;
+}
+
+/**
+  * @brief  Sets the TIM5 Input Capture 2 prescaler.
+  * @param  TIM5_IC2Prescaler: Specifies the Input Capture prescaler new value
+  *          This parameter can be one of the following values:
+  *            @arg TIM5_ICPSC_DIV1: Input Capture Prescaler = 1 (one capture every 1 event)
+  *            @arg TIM5_ICPSC_DIV2: Input Capture Prescaler = 2 (one capture every 2 events)
+  *            @arg TIM5_ICPSC_DIV4: Input Capture Prescaler = 4 (one capture every 4 events)
+  *            @arg TIM5_ICPSC_DIV8: Input Capture Prescaler = 8 (one capture every 8 events) 
+  * @retval None
+  */
+void TIM5_SetIC2Prescaler(TIM5_ICPSC_TypeDef TIM5_IC2Prescaler)
+{
+  uint8_t tmpccmr2 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM5_IC_PRESCALER(TIM5_IC2Prescaler));
+
+  tmpccmr2 = TIM5->CCMR2;
+
+  /* Reset the IC2PSC Bits */
+  tmpccmr2 &= (uint8_t)(~TIM_CCMR_ICxPSC);
+
+  /* Set the IC2PSC value */
+  tmpccmr2 |= (uint8_t)TIM5_IC2Prescaler;
+
+  TIM5->CCMR2 = tmpccmr2;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM5_Group4 Interrupts DMA and flags management functions
+ *  @brief    Interrupts, DMA and flags management functions 
+ *
+@verbatim   
+ ===============================================================================
+                 Interrupts, DMA and flags management functions
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the specified TIM5 interrupts.
+  * @param  TIM5_IT: Specifies the TIM5 interrupts sources to be enabled or disabled.
+  *          This parameter can be any combination of the following values:
+  *            @arg TIM5_IT_Update: Update
+  *            @arg TIM5_IT_CC1: Capture Compare Channel1
+  *            @arg TIM5_IT_CC2: Capture Compare Channel2 
+  *            @arg TIM5_IT_Trigger: Trigger 
+  *            @arg TIM5_IT_Break: Break  
+  * @param  NewState: The new state of the TIM5 peripheral.
+  *          This parameter can be ENABLE or DISABLE
+  * @retval None
+  */
+void TIM5_ITConfig(TIM5_IT_TypeDef TIM5_IT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM5_IT(TIM5_IT));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the Interrupt sources */
+    TIM5->IER |= (uint8_t)TIM5_IT;
+  }
+  else
+  {
+    /* Disable the Interrupt sources */
+    TIM5->IER &= (uint8_t)(~(uint8_t)TIM5_IT);
+  }
+}
+
+/**
+  * @brief  Configures the TIM5 event to be generated by software.
+  * @param  TIM5_EventSource: Specifies the event source.
+  *          This parameter can be any combination of the following values:
+  *            @arg TIM5_EventSource_Update: Update
+  *            @arg TIM5_EventSource_CC1: Capture Compare Channel1
+  *            @arg TIM5_EventSource_CC2: Capture Compare Channel2 
+  *            @arg TIM5_EventSource_Trigger: Trigger 
+  *            @arg TIM5_EventSource_Break: Break  
+  * @retval None
+  */
+void TIM5_GenerateEvent(TIM5_EventSource_TypeDef TIM5_EventSource)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM5_EVENT_SOURCE((uint8_t)TIM5_EventSource));
+
+  /* Set the event sources */
+  TIM5->EGR |= (uint8_t)TIM5_EventSource;
+}
+
+/**
+  * @brief  Checks whether the specified TIM5 flag is set or not.
+  * @param  TIM5_FLAG: Specifies the flag to check.
+  *          This parameter can be any combination of the following values:
+  *            @arg TIM5_FLAG_Update: Update
+  *            @arg TIM5_FLAG_CC1: Capture Compare Channel1
+  *            @arg TIM5_FLAG_CC2: Capture Compare Channel2 
+  *            @arg TIM5_FLAG_Trigger: Trigger 
+  *            @arg TIM5_FLAG_Break: Break  
+  *            @arg TIM5_FLAG_CC1OF: Capture compare 1 over capture
+  *            @arg TIM5_FLAG_CC2OF: Capture compare 2 over capture   
+  * @retval FlagStatus: The new state of TIM5_FLAG (SET or RESET)
+  */
+FlagStatus TIM5_GetFlagStatus(TIM5_FLAG_TypeDef TIM5_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  uint8_t tim5_flag_l = 0, tim5_flag_h = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM5_GET_FLAG(TIM5_FLAG));
+
+  tim5_flag_l = (uint8_t)(TIM5->SR1 & (uint8_t)(TIM5_FLAG));
+  tim5_flag_h = (uint8_t)(TIM5->SR2 & (uint8_t)((uint16_t)TIM5_FLAG >> 8));
+
+  if ((uint8_t)(tim5_flag_l | tim5_flag_h) != 0)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return ((FlagStatus)bitstatus);
+}
+
+/**
+  * @brief  Clears the TIM’s pending flags.
+  * @param  TIM5_FLAG: Specifies the flag to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg TIM5_FLAG_Update: Update
+  *            @arg TIM5_FLAG_CC1: Capture Compare Channel1
+  *            @arg TIM5_FLAG_CC2: Capture Compare Channel2 
+  *            @arg TIM5_FLAG_Trigger: Trigger 
+  *            @arg TIM5_FLAG_Break: Break  
+  * @retval None
+  */
+void TIM5_ClearFlag(TIM5_FLAG_TypeDef TIM5_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM5_CLEAR_FLAG((uint16_t)TIM5_FLAG));
+  /* Clear the flags (rc_w0) clear this bit by writing 0. Writing ‘1’ has no effect*/
+  TIM5->SR1 = (uint8_t)(~(uint8_t)(TIM5_FLAG));
+  TIM5->SR2 = (uint8_t)(~(uint8_t)((uint16_t)TIM5_FLAG >> 8));
+}
+
+/**
+  * @brief  Checks whether the TIM5 interrupt has occurred or not.
+  * @param  TIM5_IT: Specifies the TIM5 interrupt source to check.
+  *          This parameter can be any combination of the following values:
+  *            @arg TIM5_IT_Update: Update
+  *            @arg TIM5_IT_CC1: Capture Compare Channel1
+  *            @arg TIM5_IT_CC2: Capture Compare Channel2 
+  *            @arg TIM5_IT_Trigger: Trigger 
+  *            @arg TIM5_IT_Break: Break  
+  * @retval ITStatus: The new state of the TIM5_IT (SET or RESET)
+  */
+ITStatus TIM5_GetITStatus(TIM5_IT_TypeDef TIM5_IT)
+{
+  ITStatus bitstatus = RESET;
+
+  uint8_t TIM5_itStatus = 0x0, TIM5_itEnable = 0x0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM5_GET_IT(TIM5_IT));
+
+  TIM5_itStatus = (uint8_t)(TIM5->SR1 & (uint8_t)TIM5_IT);
+
+  TIM5_itEnable = (uint8_t)(TIM5->IER & (uint8_t)TIM5_IT);
+
+  if ((TIM5_itStatus != (uint8_t)RESET ) && (TIM5_itEnable != (uint8_t)RESET))
+  {
+    bitstatus = (ITStatus)SET;
+  }
+  else
+  {
+    bitstatus = (ITStatus)RESET;
+  }
+  return ((ITStatus)bitstatus);
+}
+
+/**
+  * @brief  Clears the TIM's interrupt pending bits.
+  * @param  TIM5_IT: Specifies the pending bit to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg TIM5_IT_Update: Update
+  *            @arg TIM5_IT_CC1: Capture Compare Channel1
+  *            @arg TIM5_IT_CC2: Capture Compare Channel2 
+  *            @arg TIM5_IT_Trigger: Trigger 
+  *            @arg TIM5_IT_Break: Break  
+  * @retval None
+  */
+void TIM5_ClearITPendingBit(TIM5_IT_TypeDef TIM5_IT)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM5_IT(TIM5_IT));
+
+  /* Clear the IT pending Bit */
+  TIM5->SR1 = (uint8_t)(~(uint8_t)TIM5_IT);
+}
+
+/**
+  * @brief  Enables or disables the TIM5 DMA Requests.
+  * @param  TIM5_DMASource: specifies the DMA Request sources.
+  *          This parameter can be any combination of the following values:
+  *            @arg TIM5_DMASource_Update: TIM5 DMA Update Request
+  *            @arg TIM5_DMASource_CC1: TIM5 DMA CC1 Request
+  *            @arg TIM5_DMASource_CC2: TIM5 DMA CC2 Request 
+  * @param  NewState: new state of the DMA Request sources.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM5_DMACmd( TIM5_DMASource_TypeDef TIM5_DMASource, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  assert_param(IS_TIM5_DMA_SOURCE(TIM5_DMASource));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the DMA sources */
+    TIM5->DER |= TIM5_DMASource;
+  }
+  else
+  {
+    /* Disable the DMA sources */
+    TIM5->DER &= (uint8_t)(~TIM5_DMASource);
+  }
+}
+
+/**
+  * @brief  Selects the TIM5 peripheral Capture Compare DMA source.
+  * @param   NewState: new state of the Capture Compare DMA source.
+  *           This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM5_SelectCCDMA(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Set the CCDS Bit */
+    TIM5->CR2 |= TIM_CR2_CCDS;
+  }
+  else
+  {
+    /* Reset the CCDS Bit */
+    TIM5->CR2 &= (uint8_t)(~TIM_CR2_CCDS);
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM5_Group5 Clocks management functions
+ *  @brief    Clocks management functions
+ *
+@verbatim   
+ ===============================================================================
+                         Clocks management functions
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables the TIM5 internal Clock.
+  * @par Parameters:
+  * None
+  * @retval None
+  */
+void TIM5_InternalClockConfig(void)
+{
+  /* Disable slave mode to clock the prescaler directly with the internal clock */
+  TIM5->SMCR &=  (uint8_t)(~TIM_SMCR_SMS);
+}
+
+/**
+  * @brief  Configures the TIM5 Trigger as External Clock.
+  * @param  TIM5_TIxExternalCLKSource: Specifies Trigger source.
+  *          This parameter can be one of the following values:
+  *            @arg TIM5_TIxExternalCLK1Source_TI1ED: External Clock mode 1 source = TI1ED
+  *            @arg TIM5_TIxExternalCLK1Source_TI1: External Clock mode 1 source = TI1 
+  *            @arg TIM5_TIxExternalCLK1Source_TI2: External Clock mode 1 source = TI2  
+  * @param  TIM5_ICPolarity: Specifies the TIx Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM5_ICPolarity_Rising: Input Capture on Rising Edge
+  *            @arg TIM5_ICPolarity_Falling: Input Capture on Falling Edge  
+  * @param  ICFilter: Specifies the filter value.
+  *          This parameter must be a value between 0x00 and 0x0F
+  * @retval None
+  */
+void TIM5_TIxExternalClockConfig(TIM5_TIxExternalCLK1Source_TypeDef TIM5_TIxExternalCLKSource,
+                                 TIM5_ICPolarity_TypeDef TIM5_ICPolarity,
+                                 uint8_t ICFilter)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM5_TIXCLK_SOURCE(TIM5_TIxExternalCLKSource));
+  assert_param(IS_TIM5_IC_POLARITY(TIM5_ICPolarity));
+  assert_param(IS_TIM5_IC_FILTER(ICFilter));
+
+  /* Configure the TIM5 Input Clock Source */
+  if (TIM5_TIxExternalCLKSource == TIM5_TIxExternalCLK1Source_TI2)
+  {
+    TI2_Config(TIM5_ICPolarity, TIM5_ICSelection_DirectTI, ICFilter);
+  }
+  else
+  {
+    TI1_Config(TIM5_ICPolarity, TIM5_ICSelection_DirectTI, ICFilter);
+  }
+
+  /* Select the Trigger source */
+  TIM5_SelectInputTrigger((TIM5_TRGSelection_TypeDef)TIM5_TIxExternalCLKSource);
+
+  /* Select the External clock mode1 */
+  TIM5->SMCR |= (uint8_t)(TIM5_SlaveMode_External1);
+}
+
+/**
+  * @brief  Configures the TIM5 External clock Mode1.
+  * @param  TIM5_ExtTRGPrescaler: Specifies the external Trigger Prescaler.
+  *          This parameter can be one of the following values:
+  *            @arg TIM5_ExtTRGPSC_OFF: No External Trigger prescaler
+  *            @arg TIM5_ExtTRGPSC_DIV2: External Trigger prescaler = 2 (ETRP frequency divided by 2)
+  *            @arg TIM5_ExtTRGPSC_DIV4: External Trigger prescaler = 4 (ETRP frequency divided by 4) 
+  *            @arg TIM5_ExtTRGPSC_DIV8: External Trigger prescaler = 8 (ETRP frequency divided by 8)   
+  * @param  TIM5_ExtTRGPolarity: Specifies the external Trigger Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM5_ExtTRGPolarity_Inverted: External Trigger Polarity = inverted
+  *            @arg TIM5_ExtTRGPolarity_NonInverted: External Trigger Polarity = non inverted
+  * @param  ExtTRGFilter: Specifies the External Trigger Filter.
+  *          This parameter must be a value between 0x00 and 0x0F
+  * @retval None
+  */
+void TIM5_ETRClockMode1Config(TIM5_ExtTRGPSC_TypeDef TIM5_ExtTRGPrescaler,
+                              TIM5_ExtTRGPolarity_TypeDef TIM5_ExtTRGPolarity,
+                              uint8_t ExtTRGFilter)
+{
+  /* Configure the ETR Clock source */
+  TIM5_ETRConfig(TIM5_ExtTRGPrescaler, TIM5_ExtTRGPolarity, ExtTRGFilter);
+
+  /* Select the External clock mode1 */
+  TIM5->SMCR &= (uint8_t)(~TIM_SMCR_SMS);
+  TIM5->SMCR |= (uint8_t)(TIM5_SlaveMode_External1);
+
+  /* Select the Trigger selection: ETRF */
+  TIM5->SMCR &= (uint8_t)(~TIM_SMCR_TS);
+  TIM5->SMCR |= (uint8_t)((TIM5_TRGSelection_TypeDef)TIM5_TRGSelection_ETRF);
+}
+
+/**
+  * @brief  Configures the TIM5 External clock Mode2.
+  * @param  TIM5_ExtTRGPrescaler: Specifies the external Trigger Prescaler.
+  *          This parameter can be one of the following values:
+  *            @arg TIM5_ExtTRGPSC_OFF: No External Trigger prescaler
+  *            @arg TIM5_ExtTRGPSC_DIV2: External Trigger prescaler = 2 (ETRP frequency divided by 2)
+  *            @arg TIM5_ExtTRGPSC_DIV4: External Trigger prescaler = 4 (ETRP frequency divided by 4) 
+  *            @arg TIM5_ExtTRGPSC_DIV8: External Trigger prescaler = 8 (ETRP frequency divided by 8) 
+  * @param  TIM5_ExtTRGPolarity: Specifies the external Trigger Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM5_ExtTRGPolarity_Inverted: External Trigger Polarity = inverted
+  *            @arg TIM5_ExtTRGPolarity_NonInverted: External Trigger Polarity = non inverted
+  * @param  ExtTRGFilter: Specifies the External Trigger Filter.
+  *          This parameter must be a value between 0x00 and 0x0F
+  * @retval None
+  */
+void TIM5_ETRClockMode2Config(TIM5_ExtTRGPSC_TypeDef TIM5_ExtTRGPrescaler,
+                              TIM5_ExtTRGPolarity_TypeDef TIM5_ExtTRGPolarity,
+                              uint8_t ExtTRGFilter)
+{
+  /* Configure the ETR Clock source */
+  TIM5_ETRConfig(TIM5_ExtTRGPrescaler, TIM5_ExtTRGPolarity, ExtTRGFilter);
+
+  /* Enable the External clock mode2 */
+  TIM5->ETR |= TIM_ETR_ECE ;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM5_Group6 Synchronization management functions
+ *  @brief    Synchronization management functions 
+ *
+@verbatim   
+ ===============================================================================
+                       Synchronization management functions
+ ===============================================================================  
+                   
+       ===================================================================      
+              TIM5 Driver: how to use it in synchronization Mode
+       =================================================================== 
+       Case of two/several Timers
+       **************************
+       1. If TIM5 is used as master to other timers use the following functions:
+          - TIM5_SelectOutputTrigger()
+          - TIM5_SelectMasterSlaveMode()
+       2. If TIM5 is used as slave to other timers use the following functions:
+          - TIM5_SelectInputTrigger()
+          - TIM5_SelectSlaveMode()
+          
+       Case of Timers and external trigger (TRIG pin)
+       ********************************************       
+       1. Configure the External trigger using TIM5_ETRConfig()
+       2. Configure the Slave Timer using the following functions:
+          - TIM5_SelectInputTrigger()
+          - TIM5_SelectSlaveMode()
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Selects the TIM5 Input Trigger source.
+  * @param  TIM5_InputTriggerSource: Specifies Input Trigger source.
+  *          This parameter can be one of the following values:
+  *            @arg TIM5_TRGSelection_TIM4: TRIG Input source =  TIM TRIG Output
+  *            @arg TIM5_TRGSelection_TIM1: TRIG Input source =  TIM TRIG Output
+  *            @arg TIM5_TRGSelection_TIM3: TRIG Input source =  TIM TRIG Output
+  *            @arg TIM5_TRGSelection_TIM2: TRIG Input source =  TIM TRIG Output
+  *            @arg TIM5_TRGSelection_TI1F_ED: TRIG Input source = TI1F_ED (TI1 Edge Detector)
+  *            @arg TIM5_TRGSelection_TI1FP1: TRIG Input source = TI1FP1 (Filtred Timer Input 1)
+  *            @arg TIM5_TRGSelection_TI2FP2: TRIG Input source = TI2FP2 (Filtred Timer Input 2)
+  *            @arg TIM5_TRGSelection_ETRF: TRIG Input source =  ETRF (External Trigger Input )      
+  * @retval None
+  */
+void TIM5_SelectInputTrigger(TIM5_TRGSelection_TypeDef TIM5_InputTriggerSource)
+{
+  uint8_t tmpsmcr = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM5_TRIGGER_SELECTION(TIM5_InputTriggerSource));
+
+  tmpsmcr = TIM5->SMCR;
+
+  /* Select the Trigger Source */
+  tmpsmcr &= (uint8_t)(~TIM_SMCR_TS);
+  tmpsmcr |= (uint8_t)TIM5_InputTriggerSource;
+
+  TIM5->SMCR = (uint8_t)tmpsmcr;
+}
+
+/**
+  * @brief  Selects the TIM5 Trigger Output Mode.
+  * @param  TIM5_TRGOSource: Specifies the Trigger Output source.
+  *          This parameter can be one of the following values:
+  *            @arg TIM5_TRGOSource_Reset: Trigger Output source = Reset 
+  *            @arg TIM5_TRGOSource_Enable: Trigger Output source = TIM5 is enabled 
+  *            @arg TIM5_TRGOSource_Update: Trigger Output source = Update event
+  *            @arg TIM5_TRGOSource_OC1: Trigger Output source = output compare channel1
+  *            @arg TIM5_TRGOSource_OC1REF: Trigger Output source = output compare channel 1 reference
+  *            @arg TIM5_TRGOSource_OC2REF: Trigger Output source = output compare channel 2 reference   
+  * @retval None
+  */
+void TIM5_SelectOutputTrigger(TIM5_TRGOSource_TypeDef TIM5_TRGOSource)
+{
+  uint8_t tmpcr2 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM5_TRGO_SOURCE(TIM5_TRGOSource));
+
+  tmpcr2 = TIM5->CR2;
+
+  /* Reset the MMS Bits */
+  tmpcr2 &= (uint8_t)(~TIM_CR2_MMS);
+
+  /* Select the TRGO source */
+  tmpcr2 |=  (uint8_t)TIM5_TRGOSource;
+
+  TIM5->CR2 = tmpcr2;
+}
+
+/**
+  * @brief  Selects the TIM5 Slave Mode.
+  * @param  TIM5_SlaveMode: Specifies the TIM5 Slave Mode.
+  *          This parameter can be one of the following values:
+  *            @arg TIM5_SlaveMode_Reset: Slave Mode Selection  = Reset
+  *            @arg TIM5_SlaveMode_Gated: Slave Mode Selection  = Gated
+  *            @arg TIM5_SlaveMode_Trigger: Slave Mode Selection  = Trigger
+  *            @arg TIM5_SlaveMode_External1: Slave Mode Selection  = External 1  
+  * @retval None
+  */
+void TIM5_SelectSlaveMode(TIM5_SlaveMode_TypeDef TIM5_SlaveMode)
+{
+  uint8_t tmpsmcr = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM5_SLAVE_MODE(TIM5_SlaveMode));
+
+  tmpsmcr = TIM5->SMCR;
+
+  /* Reset the SMS Bits */
+  tmpsmcr &= (uint8_t)(~TIM_SMCR_SMS);
+
+  /* Select the Slave Mode */
+  tmpsmcr |= (uint8_t)TIM5_SlaveMode;
+
+  TIM5->SMCR = tmpsmcr;
+}
+
+/**
+  * @brief  Sets or Resets the TIM5 Master/Slave Mode.
+  * @param  NewState: The new state of the synchronization between TIM5 and its slaves (through TRGO).
+  *          This parameter can be ENABLE or DISABLE
+  * @retval None
+  */
+void TIM5_SelectMasterSlaveMode(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Set or Reset the MSM Bit */
+  if (NewState != DISABLE)
+  {
+    TIM5->SMCR |= TIM_SMCR_MSM;
+  }
+  else
+  {
+    TIM5->SMCR &= (uint8_t)(~TIM_SMCR_MSM);
+  }
+}
+
+/**
+  * @brief  Configures the TIM5 External Trigger.
+  * @param  TIM5_ExtTRGPrescaler: Specifies the external Trigger Prescaler.
+  *          This parameter can be one of the following values:
+  *            @arg TIM5_ExtTRGPSC_OFF: No External Trigger prescaler
+  *            @arg TIM5_ExtTRGPSC_DIV2: External Trigger prescaler = 2 (ETRP frequency divided by 2)
+  *            @arg TIM5_ExtTRGPSC_DIV4: External Trigger prescaler = 4 (ETRP frequency divided by 4)
+  *            @arg TIM5_ExtTRGPSC_DIV8: External Trigger prescaler = 8 (ETRP frequency divided by 8)    
+  * @param  TIM5_ExtTRGPolarity: Specifies the external Trigger Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM5_ExtTRGPolarity_Inverted: External Trigger Polarity = inverted
+  *            @arg TIM5_ExtTRGPolarity_NonInverted: External Trigger Polarity = non inverted
+  * @param  ExtTRGFilter: Specifies the External Trigger Filter.
+  *          This parameter must be a value between 0x00 and 0x0F
+  * @retval None
+  */
+void TIM5_ETRConfig(TIM5_ExtTRGPSC_TypeDef TIM5_ExtTRGPrescaler,
+                    TIM5_ExtTRGPolarity_TypeDef TIM5_ExtTRGPolarity,
+                    uint8_t ExtTRGFilter)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM5_EXT_PRESCALER(TIM5_ExtTRGPrescaler));
+  assert_param(IS_TIM5_EXT_POLARITY(TIM5_ExtTRGPolarity));
+  assert_param(IS_TIM5_EXT_FILTER(ExtTRGFilter));
+
+  /* Set the Prescaler, the Filter value and the Polarity */
+  TIM5->ETR |= (uint8_t)((uint8_t)((uint8_t)TIM5_ExtTRGPrescaler | (uint8_t)TIM5_ExtTRGPolarity)
+                         | (uint8_t)ExtTRGFilter);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM5_Group7 Specific interface management functions
+ *  @brief    Specific interface management functions 
+ *
+@verbatim   
+ ===============================================================================
+                    Specific interface management functions
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures the TIM5 Encoder Interface.
+  * @param  TIM5_EncoderMode: Specifies the TIM5 Encoder Mode.
+  *          This parameter can be one of the following values:
+  *            @arg TIM5_EncoderMode_TI1: Encoder mode 1
+  *            @arg TIM5_EncoderMode_TI2: Encoder mode 2
+  *            @arg TIM5_EncoderMode_TI12: Encoder mode 3   
+  * @param  TIM5_IC1Polarity: Specifies the IC1 Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM5_ICPolarity_Rising: Input Capture on Rising Edge
+  *            @arg TIM5_ICPolarity_Falling: Input Capture on Falling Edge  
+  * @param  TIM5_IC2Polarity: Specifies the IC2 Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM5_ICPolarity_Rising: Input Capture on Rising Edge
+  *            @arg TIM5_ICPolarity_Falling: Input Capture on Falling Edge  
+  * @retval None
+  */
+void TIM5_EncoderInterfaceConfig(TIM5_EncoderMode_TypeDef TIM5_EncoderMode,
+                                 TIM5_ICPolarity_TypeDef TIM5_IC1Polarity,
+                                 TIM5_ICPolarity_TypeDef TIM5_IC2Polarity)
+{
+  uint8_t tmpsmcr = 0;
+  uint8_t tmpccmr1 = 0;
+  uint8_t tmpccmr2 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM5_ENCODER_MODE(TIM5_EncoderMode));
+  assert_param(IS_TIM5_IC_POLARITY(TIM5_IC1Polarity));
+  assert_param(IS_TIM5_IC_POLARITY(TIM5_IC2Polarity));
+
+  tmpsmcr = TIM5->SMCR;
+  tmpccmr1 = TIM5->CCMR1;
+  tmpccmr2 = TIM5->CCMR2;
+
+  /* Set the encoder Mode */
+  tmpsmcr &= (uint8_t)(TIM_SMCR_MSM | TIM_SMCR_TS)  ;
+  tmpsmcr |= (uint8_t)TIM5_EncoderMode;
+
+  /* Select the Capture Compare 1 and the Capture Compare 2 as input */
+  tmpccmr1 &= (uint8_t)(~TIM_CCMR_CCxS);
+  tmpccmr2 &= (uint8_t)(~TIM_CCMR_CCxS);
+  tmpccmr1 |= TIM_CCMR_TIxDirect_Set;
+  tmpccmr2 |= TIM_CCMR_TIxDirect_Set;
+
+  /* Set the TI1 and the TI2 Polarities */
+  if (TIM5_IC1Polarity == TIM5_ICPolarity_Falling)
+  {
+    TIM5->CCER1 |= TIM_CCER1_CC1P ;
+  }
+  else
+  {
+    TIM5->CCER1 &= (uint8_t)(~TIM_CCER1_CC1P) ;
+  }
+
+  if (TIM5_IC2Polarity == TIM5_ICPolarity_Falling)
+  {
+    TIM5->CCER1 |= TIM_CCER1_CC2P ;
+  }
+  else
+  {
+    TIM5->CCER1 &= (uint8_t)(~TIM_CCER1_CC2P) ;
+  }
+
+  TIM5->SMCR = tmpsmcr;
+  TIM5->CCMR1 = tmpccmr1;
+  TIM5->CCMR2 = tmpccmr2;
+}
+
+/**
+  * @brief  Enables or Disables the TIM’s Hall sensor interface.
+  * @param  NewState: The new state of the TIM5 Hall sensor interface.
+  *          This parameter can be ENABLE or DISABLE
+  * @retval None
+  */
+void TIM5_SelectHallSensor(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Set or Reset the TI1S Bit */
+  if (NewState != DISABLE)
+  {
+    TIM5->CR2 |= TIM_CR2_TI1S;
+  }
+  else
+  {
+    TIM5->CR2 &= (uint8_t)(~TIM_CR2_TI1S);
+  }
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @brief  Configure the TI1 as Input.
+  * @param  TIM5_ICPolarity: Input Capture Polarity
+  *          This parameter can be one of the following values:
+  *            @arg TIM5_ICPolarity_Rising: Input Capture on Rising Edge
+  *            @arg TIM5_ICPolarity_Falling: Input Capture on Falling Edge  
+  * @param  TIM5_ICSelection: Specifies the input to be used.
+  *          This parameter can be one of the following values:
+  *            @arg TIM5_ICSelection_DirectTI: Input Capture mapped on the direct input
+  *            @arg TIM5_ICSelection_IndirectTI: Input Capture mapped on the indirect input
+  *            @arg TIM5_ICSelection_TRGI: Input Capture mapped on the Trigger Input   
+  * @param  TIM5_ICFilter: Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  */
+static void TI1_Config(TIM5_ICPolarity_TypeDef TIM5_ICPolarity, \
+                       TIM5_ICSelection_TypeDef TIM5_ICSelection, \
+                       uint8_t TIM5_ICFilter)
+{
+  uint8_t tmpccmr1 = 0;
+  uint8_t tmpicpolarity = TIM5_ICPolarity;
+  tmpccmr1 = TIM5->CCMR1;
+
+  /* Check the parameters */
+  assert_param(IS_TIM5_IC_POLARITY(TIM5_ICPolarity));
+  assert_param(IS_TIM5_IC_SELECTION(TIM5_ICSelection));
+  assert_param(IS_TIM5_IC_FILTER(TIM5_ICFilter));
+
+  /* Disable the Channel 1: Reset the CCE Bit */
+  TIM5->CCER1 &=  (uint8_t)(~TIM_CCER1_CC1E);
+
+  /* Select the Input and set the filter */
+  tmpccmr1 &= (uint8_t)(~TIM_CCMR_CCxS) & (uint8_t)(~TIM_CCMR_ICxF);
+  tmpccmr1 |= (uint8_t)(((uint8_t)(TIM5_ICSelection)) | ((uint8_t)(TIM5_ICFilter << 4)));
+
+  TIM5->CCMR1 = tmpccmr1;
+
+  /* Select the Polarity */
+  if (tmpicpolarity == (uint8_t)(TIM5_ICPolarity_Falling))
+  {
+    TIM5->CCER1 |= TIM_CCER1_CC1P;
+  }
+  else
+  {
+    TIM5->CCER1 &= (uint8_t)(~TIM_CCER1_CC1P);
+  }
+
+  /* Set the CCE Bit */
+  TIM5->CCER1 |=  TIM_CCER1_CC1E;
+}
+
+/**
+  * @brief  Configure the TI2 as Input.
+  * @param  TIM5_ICPolarity: Input Capture Polarity
+  *          This parameter can be one of the following values:
+  *            @arg TIM5_ICPolarity_Rising: Input Capture on Rising Edge
+  *            @arg TIM5_ICPolarity_Falling: Input Capture on Falling Edge  
+  * @param  TIM5_ICSelection: Specifies the input to be used.
+  *          This parameter can be one of the following values:
+  *            @arg TIM5_ICSelection_DirectTI: Input Capture mapped on the direct input
+  *            @arg TIM5_ICSelection_IndirectTI: Input Capture mapped on the indirect input
+  *            @arg TIM5_ICSelection_TRGI: Input Capture mapped on the Trigger Input   
+  * @param  TIM5_ICFilter: Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  */
+static void TI2_Config(TIM5_ICPolarity_TypeDef TIM5_ICPolarity,
+                       TIM5_ICSelection_TypeDef TIM5_ICSelection,
+                       uint8_t TIM5_ICFilter)
+{
+  uint8_t tmpccmr2 = 0;
+  uint8_t tmpicpolarity = TIM5_ICPolarity;
+
+  /* Check the parameters */
+  assert_param(IS_TIM5_IC_POLARITY(TIM5_ICPolarity));
+  assert_param(IS_TIM5_IC_SELECTION(TIM5_ICSelection));
+  assert_param(IS_TIM5_IC_FILTER(TIM5_ICFilter));
+
+  tmpccmr2 = TIM5->CCMR2;
+
+  /* Disable the Channel 2: Reset the CCE Bit */
+  TIM5->CCER1 &=  (uint8_t)(~TIM_CCER1_CC2E);
+
+  /* Select the Input and set the filter */
+  tmpccmr2 &= (uint8_t)(~TIM_CCMR_CCxS) & (uint8_t)(~TIM_CCMR_ICxF);
+  tmpccmr2 |= (uint8_t)(((uint8_t)(TIM5_ICSelection)) | ((uint8_t)(TIM5_ICFilter << 4)));
+
+  TIM5->CCMR2 = tmpccmr2;
+
+  /* Select the Polarity */
+  if (tmpicpolarity == TIM5_ICPolarity_Falling)
+  {
+    TIM5->CCER1 |= TIM_CCER1_CC2P ;
+  }
+  else
+  {
+    TIM5->CCER1 &= (uint8_t)(~TIM_CCER1_CC2P) ;
+  }
+
+  /* Set the CCE Bit */
+  TIM5->CCER1 |=  TIM_CCER1_CC2E;
+}
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+  
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_usart.c b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_usart.c
new file mode 100755
index 0000000..b12e368
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_usart.c
@@ -0,0 +1,1205 @@
+/**
+  ******************************************************************************
+  * @file    stm8l15x_usart.c
+  * @author  MCD Application Team
+  * @version V1.6.0
+  * @date    28-June-2013
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Universal synchronous asynchronous receiver
+  *          transmitter (USART):           
+  *           - Initialization and Configuration
+  *           - Data transfers
+  *           - Multi-Processor Communication
+  *           - Half-duplex mode
+  *           - Smartcard mode
+  *           - IrDA mode
+  *           - DMA transfers management
+  *           - Interrupts and flags management 
+  *           
+  *  @verbatim
+  *      
+  *          ===================================================================
+  *                                 How to use this driver
+  *          ===================================================================
+  *          1. Enable peripheral clock using CLK_PeripheralClockConfig(CLK_Peripheral_USARTx,
+  *             ENABLE) function (Refer to the product datasheet for the available USART
+  *           	peripherals)
+  *
+  *          2.  Enable the external Pull-up on the used USART Pins using the
+  *              GPIO_ExternalPullUpConfig() function or an external pull-up equivalent resistor
+	*              (RPU = 45 KOhm typical value). 
+	*
+  *          3. Program the Baud Rate, Word Length , Stop Bit, Parity and Mode (Receiver/Transmitter)
+  *           	using the USART_Init() function.
+  *
+  *          4. For synchronous mode, enable the clock and program the polarity,
+  *             phase and last bit using the USART_ClockInit() function.
+  *
+  *          5. Enable the corresponding interrupt using the function USART_ITConfig() if you need 
+	*             to use interrupt mode. 
+  *
+  *          6. When using the DMA mode 
+  *                   - Configure the DMA using DMA_Init() function
+  *                   - Activate the needed channel Request using USART_DMACmd() function
+  * 
+  *          7. Enable the USART using the USART_Cmd() function.
+  * 
+  *          8. Enable the DMA using the DMA_Cmd() function, when using DMA mode. 
+  *
+  *          Refer to Multi-Processor, half-duplex, Smartcard, IrDA sub-sections for more details.
+  *          
+  *  @endverbatim
+  *        
+  ******************************************************************************
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ****************************************************************************** 
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm8l15x_usart.h"
+
+/** @addtogroup STM8L15x_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup USART 
+  * @brief USART driver modules
+  * @{
+  */
+	
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup USART_Private_Functions
+  * @{
+  */
+
+/** @defgroup USART_Group1 Initialization and Configuration functions
+ *  @brief   Initialization and Configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+                  Initialization and Configuration functions
+ ===============================================================================  
+
+  This subsection provides a set of functions allowing to initialize the USART 
+  in asynchronous and in synchronous modes.
+   - For the asynchronous mode only these parameters can be configured: 
+        - Baud Rate
+        - Word Length 
+        - Stop Bit
+        - Parity: If the parity is enabled, then the MSB bit of the data written
+          in the data register is transmitted but is changed by the parity bit.
+          Depending on the frame length defined by the M bit (8-bits or 9-bits),
+          the possible USART frame formats are as listed in the following table:
+   +-------------------------------------------------------------+     
+   |   M bit |  PCE bit  |            USART frame                |
+   |---------------------|---------------------------------------|             
+   |    0    |    0      |    | SB | 8 bit data | STB |          |
+   |---------|-----------|---------------------------------------|  
+   |    0    |    1      |    | SB | 7 bit data | PB | STB |     |
+   |---------|-----------|---------------------------------------|  
+   |    1    |    0      |    | SB | 9 bit data | STB |          |
+   |---------|-----------|---------------------------------------|  
+   |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
+   +-------------------------------------------------------------+            
+        - Receiver/transmitter modes
+
+  The USART_Init() function follows the USART  asynchronous configuration procedure
+  (details for the procedure are available in reference manual (RM0031)).
+
+  - For the synchronous mode in addition to the asynchronous mode parameters these 
+    parameters should be also configured:
+        - USART Clock Enabled
+        - USART polarity
+        - USART phase
+        - USART LastBit
+  
+  These parameters can be configured using the USART_ClockInit() function.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief   Deinitializes the USART peripheral.
+  * @param  USARTx: where x can be 1, 2 or 3 to select the specified USART peripheral.
+  * @retval None
+  */
+void USART_DeInit(USART_TypeDef* USARTx)
+{
+
+  /* Clear the Idle Line Detected bit in the status register by a read
+      to the USART_SR register followed by a Read to the USART_DR register */
+  (void) USARTx->SR;
+  (void) USARTx->DR;
+
+  USARTx->BRR2 = USART_BRR2_RESET_VALUE;  /* Set USART_BRR2 to reset value 0x00 */
+  USARTx->BRR1 = USART_BRR1_RESET_VALUE;  /* Set USART_BRR1 to reset value 0x00 */
+
+  USARTx->CR1 = USART_CR1_RESET_VALUE;  /* Set USART_CR1 to reset value 0x00 */
+  USARTx->CR2 = USART_CR2_RESET_VALUE;  /* Set USART_CR2 to reset value 0x00 */
+  USARTx->CR3 = USART_CR3_RESET_VALUE;  /* Set USART_CR3 to reset value 0x00 */
+  USARTx->CR4 = USART_CR4_RESET_VALUE;  /* Set USART_CR4 to reset value 0x00 */
+}
+
+/**
+  * @brief  Initializes the USART according to the specified parameters.
+  * @note   Configure in Push Pull or Open Drain mode the Tx pin by setting the
+  *         correct I/O Port register according the product package and line
+  *         configuration
+  * @param  USARTx: where x can be 1 to select the specified USART peripheral.
+  * @param  BaudRate: The baudrate.
+  * @param  USART_WordLength: the word length
+  *           This parameter can be one of the following values:
+  *            @arg USART_WordLength_8b: 8 bits Data
+  *            @arg USART_WordLength_9b: 9 bits Data  
+  * @param  USART_StopBits: Stop Bit
+  *           This parameter can be one of the following values:
+  *            @arg USART_StopBits_1: One stop bit is transmitted at the end of frame
+  *            @arg USART_StopBits_2: Two stop bits are transmitted at the end of frame
+  *            @arg USART_StopBits_1_5: One and half stop bits
+  * @param  USART_Parity: Parity
+  *           This parameter can be one of the following values:
+  *            @arg USART_Parity_No: No Parity
+  *            @arg USART_Parity_Even: Even Parity
+  *            @arg USART_Parity_Odd: Odd Parity    
+  * @param  USART_Mode: Mode
+  *           This parameter can be one of the following values:
+  *            @arg USART_Mode_Rx: Receive Enable
+  *            @arg USART_Mode_Tx: Transmit Enable  
+  * @retval None
+  */
+void USART_Init(USART_TypeDef* USARTx, uint32_t BaudRate, USART_WordLength_TypeDef
+                USART_WordLength, USART_StopBits_TypeDef USART_StopBits,
+                USART_Parity_TypeDef USART_Parity,  USART_Mode_TypeDef USART_Mode)
+{
+  uint32_t BaudRate_Mantissa = 0;
+
+  /* Check the parameters */
+  assert_param(IS_USART_BAUDRATE(BaudRate));
+
+  assert_param(IS_USART_WORDLENGTH(USART_WordLength));
+
+  assert_param(IS_USART_STOPBITS(USART_StopBits));
+
+  assert_param(IS_USART_PARITY(USART_Parity));
+
+  assert_param(IS_USART_MODE(USART_Mode));
+
+  /* Clear the word length and Parity Control bits */
+  USARTx->CR1 &= (uint8_t)(~(USART_CR1_PCEN | USART_CR1_PS | USART_CR1_M));
+  /* Set the word length bit according to USART_WordLength value */
+  /* Set the Parity Control bit to USART_Parity value */
+  USARTx->CR1 |= (uint8_t)((uint8_t)USART_WordLength | (uint8_t)USART_Parity);
+
+  /* Clear the STOP bits */
+  USARTx->CR3 &= (uint8_t)(~USART_CR3_STOP);
+  /* Set the STOP bits number according to USART_StopBits value */
+  USARTx->CR3 |= (uint8_t)USART_StopBits;
+
+  /* Clear the LSB mantissa of USARTDIV */
+  USARTx->BRR1 &= (uint8_t)(~USART_BRR1_DIVM);
+  /* Clear the MSB mantissa of USARTDIV */
+  USARTx->BRR2 &= (uint8_t)(~USART_BRR2_DIVM);
+  /* Clear the Fraction bits of USARTDIV */
+  USARTx->BRR2 &= (uint8_t)(~USART_BRR2_DIVF);
+
+  BaudRate_Mantissa  = (uint32_t)(CLK_GetClockFreq() / BaudRate );
+  /* Set the fraction of USARTDIV */
+  USARTx->BRR2 = (uint8_t)((BaudRate_Mantissa >> (uint8_t)8) & (uint8_t)0xF0);
+  /* Set the MSB mantissa of USARTDIV */
+  USARTx->BRR2 |= (uint8_t)(BaudRate_Mantissa & (uint8_t)0x0F);
+  /* Set the LSB mantissa of USARTDIV */
+  USARTx->BRR1 = (uint8_t)(BaudRate_Mantissa >> (uint8_t)4);
+
+  /* Disable the Transmitter and Receiver */
+  USARTx->CR2 &= (uint8_t)~(USART_CR2_TEN | USART_CR2_REN);
+  /* Set TEN and REN bits according to USART_Mode value */
+  USARTx->CR2 |= (uint8_t)USART_Mode;
+}
+
+/**
+  * @brief  Initializes the USART Clock according to the specified parameters.
+  * @param  USARTx: where x can be 1 to select the specified USART peripheral.
+  * @param  USART_Clock: Clock
+  *           This parameter can be one of the following values:
+  *            @arg USART_Clock_Disable: CK pin disabled
+  *            @arg USART_Clock_Enable: CK pin enabled  
+  * @param  USART_CPOL: Clock Polarity
+  *           This parameter can be one of the following values:
+  *            @arg USART_CPOL_Low: CK to 0 when idle
+  *            @arg USART_CPOL_High: CK to 1 when idle
+  * @param  USART_CPHA: Clock Phase
+  *           This parameter can be one of the following values:
+  *            @arg USART_CPHA_1Edge: The first clock transition is the first data capture edge
+  *            @arg USART_CPHA_2Edge: The second clock transition is the first data capture edge
+  * @param  USART_LastBit: Last Bit
+  *           This parameter can be one of the following values:
+  *            @arg USART_LastBit_Disable: The clock pulse of the last data bit is 
+  *               not output to the SCLK pin
+  *            @arg USART_LastBit_Enable: The clock pulse of the last data bit is 
+  *               output to the SCLK pin
+  * @retval None
+  */
+void USART_ClockInit(USART_TypeDef* USARTx, USART_Clock_TypeDef USART_Clock,
+                     USART_CPOL_TypeDef USART_CPOL, USART_CPHA_TypeDef USART_CPHA,
+                     USART_LastBit_TypeDef USART_LastBit)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_CLOCK(USART_Clock));
+  assert_param(IS_USART_CPOL(USART_CPOL));
+  assert_param(IS_USART_CPHA(USART_CPHA));
+  assert_param(IS_USART_LASTBIT(USART_LastBit));
+
+  /* Clear the Clock Polarity, lock Phase, Last Bit Clock pulse */
+  USARTx->CR3 &= (uint8_t)~(USART_CR3_CPOL | USART_CR3_CPHA | USART_CR3_LBCL);
+  /* Set the Clock Polarity, lock Phase, Last Bit Clock pulse */
+  USARTx->CR3 |= (uint8_t)((uint8_t)((uint8_t)(USART_CPOL | (uint8_t)USART_CPHA ) | USART_LastBit));
+
+  if (USART_Clock != USART_Clock_Disable)
+  {
+    USARTx->CR3 |= (uint8_t)(USART_CR3_CLKEN); /* Set the Clock Enable bit */
+  }
+  else
+  {
+    USARTx->CR3 &= (uint8_t)(~USART_CR3_CLKEN); /* Clear the Clock Enable bit */
+  }
+}
+
+/**
+  * @brief  Enable the USART peripheral.
+  * @param  USARTx: where x can be 1 to select the specified USART peripheral.
+  * @param  NewState: The new state of the USART Communication.
+    *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  if (NewState != DISABLE)
+  {
+    USARTx->CR1 &= (uint8_t)(~USART_CR1_USARTD); /**< USART Enable */
+  }
+  else
+  {
+    USARTx->CR1 |= USART_CR1_USARTD;  /**< USART Disable (for low power consumption) */
+  }
+}
+
+/**
+  * @brief  Sets the system clock prescaler.
+  * @note   IrDA Low Power mode or smartcard mode should be enabled
+  * @note   This function is related to SmartCard and IrDa mode.
+  * @param  USARTx: Select the USARTx peripheral.
+  * @param  USART_Prescaler: specifies the prescaler clock.
+  * @note   In IrDA Low Power Mode the clock source is divided by the value given 
+  *         in the register (8 bits)
+  *         - 0000 0000 Reserved
+  *         - 0000 0001 divides the clock source by 1
+  *         - 0000 0010 divides the clock source by 2
+  *         - ...
+  * @note   In Smart Card Mode the clock source is divided by the value given in the register
+  *         (5 significant bits) multiplied by 2
+  *         - 0 0000 Reserved
+  *         - 0 0001 divides the clock source by 2
+  *         - 0 0010 divides the clock source by 4
+  *         - 0 0011 divides the clock source by 6
+  *         - ...
+  * @retval None
+  */
+void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler)
+{
+  /* Load the USART prescaler value*/
+  USARTx->PSCR = USART_Prescaler;
+}
+
+/**
+  * @brief  Transmits break characters.
+  * @param  USARTx: where x can be 1 to select the specified USART peripheral.
+  * @retval None
+  */
+void USART_SendBreak(USART_TypeDef* USARTx)
+{
+  USARTx->CR2 |= USART_CR2_SBK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_Group2 Data transfers functions
+ *  @brief   Data transfers functions 
+ *
+@verbatim   
+ ===============================================================================
+                            Data transfers functions
+ ===============================================================================  
+
+  This subsection provides a set of functions allowing to manage the USART data 
+  transfers.
+  
+  During an USART reception, data shifts in least significant bit first through 
+  the RX pin. In this mode, the USART_DR register is similar to a buffer (RDR) 
+  between the internal bus and the received shift register.
+
+  When a transmission is taking place, a write instruction to the USART_DR register 
+  stores the data in the TDR register which is copied in the shift register 
+  at the end of the current transmission.
+
+  The read access of the USART_DR register can be done using the USART_ReceiveData8()
+  or USART_ReceiveData9() functions and returns the RDR buffered value. Whereas a write
+	access to the USART_DR can be done using USART_SendData8() or USART_SendData9() 
+	functions and stores the written data into TDR buffer.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Returns the most recent received data by the USART peripheral.
+  * @param  USARTx: where x can be 1 to select the specified USART peripheral.
+  * @retval The received data.
+  */
+uint8_t USART_ReceiveData8(USART_TypeDef* USARTx)
+{
+  return USARTx->DR;
+}
+
+/**
+  * @brief  Returns the most recent received data by the USART peripheral.
+  * @param  USARTx: where x can be 1 to select the specified USART peripheral.
+  * @retval The received data.
+  */
+uint16_t USART_ReceiveData9(USART_TypeDef* USARTx)
+{
+  uint16_t temp = 0;
+
+  temp = ((uint16_t)(((uint16_t)((uint16_t)USARTx->CR1 & (uint16_t)USART_CR1_R8)) << 1));
+  return (uint16_t)( ((uint16_t)((uint16_t)USARTx->DR) | temp) & ((uint16_t)0x01FF));
+}
+
+/**
+  * @brief  Transmits 8 bit data through the USART peripheral.
+  * @param  Data: The data to transmit.
+  * @retval None
+  */
+void USART_SendData8(USART_TypeDef* USARTx, uint8_t Data)
+{
+  /* Transmit Data */
+  USARTx->DR = Data;
+}
+
+/**
+  * @brief  Transmits 9 bit data through the USART peripheral.
+  * @param  USARTx: Select the USARTx peripheral.
+  * @param  Data: The data to transmit.
+  *         This parameter should be lower than 0x1FF.
+  * @retval None
+  */
+void USART_SendData9(USART_TypeDef* USARTx, uint16_t Data)
+{
+  assert_param(IS_USART_DATA_9BITS(Data));
+
+  /* Clear the transmit data bit 8     */
+  USARTx->CR1 &= ((uint8_t)~USART_CR1_T8);
+
+  /* Write the transmit data bit [8]   */
+  USARTx->CR1 |= (uint8_t)(((uint8_t)(Data >> 2)) & USART_CR1_T8);
+
+  /* Write the transmit data bit [0:7] */
+  USARTx->DR   = (uint8_t)(Data);
+}
+/**
+  * @}
+  */
+
+/** @defgroup USART_Group3 MultiProcessor Communication functions
+ *  @brief   Multi-Processor Communication functions 
+ *
+@verbatim   
+ ===============================================================================
+                    Multi-Processor Communication functions
+ ===============================================================================  
+
+  This subsection provides a set of functions allowing to manage the USART 
+  multiprocessor communication.
+  
+  For instance one of the USARTs can be the master, its TX output is connected to 
+  the RX input of the other USART. The others are slaves, their respective TX outputs 
+  are logically ANDed together and connected to the RX input of the master.
+
+  USART multiprocessor communication is possible through the following procedure:
+     1. Program the Baud rate, Word length = 9 bits, Stop bits, Parity, Mode transmitter 
+        or Mode receiver and hardware flow control values using the USART_Init()
+        function.
+     2. Configures the USART address using the USART_SetAddress() function.
+     3. Configures the wake up method (USART_WakeUp_IdleLine or USART_WakeUp_AddressMark)
+        using USART_WakeUpConfig() function only for the slaves.
+     4. Enable the USART using the USART_Cmd() function.
+     5. Enter the USART slaves in mute mode using USART_ReceiverWakeUpCmd() function.
+
+  The USART Slave exit from mute mode when receiving the wake up condition.
+
+@endverbatim
+  * @{
+  */
+	
+/**
+  * @brief  Determines if the USART is in mute mode or not.
+  * @param  USARTx: where x can be 1 to select the specified USART peripheral.
+  * @param  NewState: The new state of the USART mode.
+    *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the mute mode USART by setting the RWU bit in the CR2 register */
+    USARTx->CR2 |= USART_CR2_RWU;
+  }
+  else
+  {
+    /* Disable the mute mode USART by clearing the RWU bit in the CR1 register */
+    USARTx->CR2 &= ((uint8_t)~USART_CR2_RWU);
+  }
+}
+
+/**
+  * @brief  Sets the address of the USART node.
+  * @param  USARTx: Select the USARTx peripheral.
+  * @param  Address: Indicates the address of the USART node.
+  *         This parameter should be lower than 16
+  * @retval None
+  */
+void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address)
+{
+  /* assert_param for USART_Address */
+  assert_param(IS_USART_ADDRESS(USART_Address));
+
+  /* Clear the USART address */
+  USARTx->CR4 &= ((uint8_t)~USART_CR4_ADD);
+  /* Set the USART address node */
+  USARTx->CR4 |= USART_Address;
+}
+
+/**
+  * @brief  Selects the USART WakeUp method.
+  * @param  USART_WakeUp: Specifies the USART wakeup method.
+  *           This parameter can be one of the following values:
+  *            @arg USART_WakeUp_IdleLine: 0x01 Idle Line wake up
+  *            @arg USART_WakeUp_AddressMark: 0x02 Address Mark wake up    
+  * @retval None
+  */
+void USART_WakeUpConfig(USART_TypeDef* USARTx, USART_WakeUp_TypeDef USART_WakeUp)
+{
+  assert_param(IS_USART_WAKEUP(USART_WakeUp));
+
+  USARTx->CR1 &= ((uint8_t)~USART_CR1_WAKE);
+  USARTx->CR1 |= (uint8_t)USART_WakeUp;
+}
+/**
+  * @}
+  */
+
+/** @defgroup USART_Group4 Halfduplex mode function
+ *  @brief   Half-duplex mode function 
+ *
+@verbatim   
+ ===============================================================================
+                         Half-duplex mode function
+ ===============================================================================  
+
+  This subsection provides a function allowing to manage the USART 
+  Half-duplex communication.
+  
+  The USART can be configured to follow a single-wire half-duplex protocol where 
+  the TX and RX lines are internally connected.
+
+  USART Half duplex communication is possible through the following procedure:
+     1. Program the Baud rate, Word length, Stop bits, Parity, Mode transmitter 
+        or Mode receiver and hardware flow control values using the USART_Init()
+        function.
+     2. Configures the USART address using the USART_SetAddress() function.
+     3. Enable the USART using the USART_Cmd() function.
+     4. Enable the half duplex mode using USART_HalfDuplexCmd() function.
+
+Note:
+----
+  1. The RX pin is no longer used
+  2. In Half-duplex mode the following bits must be kept cleared:
+       - CLKEN bits in the USART_CR3 register.
+       - SCEN and IREN bits in the USART_CR5 register.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the USART’s Half Duplex communication.
+  * @param  USARTx: where x can be 1 to select the specified USART peripheral.
+  * @param  NewState new state of the USART Communication.
+    *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    USARTx->CR5 |= USART_CR5_HDSEL;  /**< USART Half Duplex Enable  */
+  }
+  else
+  {
+    USARTx->CR5 &= (uint8_t)~USART_CR5_HDSEL; /**< USART Half Duplex Disable */
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_Group5 Smartcard mode functions
+ *  @brief   Smartcard mode functions 
+ *
+@verbatim   
+ ===============================================================================
+                               Smartcard mode functions
+ ===============================================================================  
+
+  This subsection provides a set of functions allowing to manage the USART 
+  Smartcard communication.
+  
+  The Smartcard interface is designed to support asynchronous protocol Smartcards as
+  defined in the ISO 7816-3 standard.
+
+  The USART can provide a clock to the smartcard through the SCLK output.
+  In smartcard mode, SCLK is not associated to the communication but is simply derived 
+  from the internal peripheral input clock through a 5-bit prescaler.
+
+  Smartcard communication is possible through the following procedure:
+     1. Configures the Smartcard Prsecaler using the USART_SetPrescaler() function.
+     2. Configures the Smartcard Guard Time using the USART_SetGuardTime() function.
+     3. Program the USART clock using the USART_ClockInit() function as following:
+        - USART Clock enabled
+        - USART CPOL Low
+        - USART CPHA on first edge
+        - USART Last Bit Clock Enabled
+     4. Program the Smartcard interface using the USART_Init() function as following:
+        - Word Length = 9 Bits
+        - 1.5 Stop Bit
+        - Even parity
+        - BaudRate = 12096 baud
+        - Hardware flow control disabled (RTS and CTS signals)
+        - Tx and Rx enabled
+     5. Optionally you can enable the parity error interrupt using the USART_ITConfig()
+        function
+     6. Enable the USART using the USART_Cmd() function.
+     7. Enable the Smartcard NACK using the USART_SmartCardNACKCmd() function.
+     8. Enable the Smartcard interface using the USART_SmartCardCmd() function.
+
+  Please refer to the ISO 7816-3 specification for more details.
+
+Note: 
+-----
+  1.  It is also possible to choose 0.5 stop bit for receiving but it is recommended 
+      to use 1.5 stop bits for both transmitting and receiving to avoid switching 
+      between the two configurations.
+  2. In smartcard mode, the following bits must be kept cleared:
+     - HDSEL and IREN bits in the USART_CR5 register.
+
+@endverbatim
+  * @{
+  */
+	
+/**
+  * @brief  Enables or disables the USART Smart Card mode.
+  * @param  USARTx: Select the USARTx peripheral.
+  * @param  NewState: new state of the Smart Card mode.
+    *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the SC mode by setting the SCEN bit in the CR5 register */
+    USARTx->CR5 |= USART_CR5_SCEN;
+  }
+  else
+  {
+    /* Disable the SC mode by clearing the SCEN bit in the CR5 register */
+    USARTx->CR5 &= ((uint8_t)(~USART_CR5_SCEN));
+  }
+}
+
+/**
+  * @brief  Enables or disables NACK transmission.
+  * @param  USARTx: where x can be 1 to select the specified USART peripheral.
+  * @param  NewState: new state of the Smart Card mode.
+    *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the NACK transmission by setting the NACK bit in the CR5 register */
+    USARTx->CR5 |= USART_CR5_NACK;
+  }
+  else
+  {
+    /* Disable the NACK transmission by clearing the NACK bit in the CR5 register */
+    USARTx->CR5 &= ((uint8_t)~(USART_CR5_NACK));
+  }
+}
+
+/**
+  * @brief  Sets the specified USART guard time.
+  * @note   SmartCard Mode should be Enabled
+  * @param  USARTx: where x can be 1 to select the specified USART peripheral.
+  * @param  USART_GuardTime: specifies the guard time.
+  * @retval None
+  */
+void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime)
+{
+  /* Set the USART guard time */
+  USARTx->GTR = USART_GuardTime;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_Group6 IrDA mode functions
+ *  @brief   IrDA mode functions 
+ *
+@verbatim   
+ ===============================================================================
+                                IrDA mode functions
+ ===============================================================================  
+
+  This subsection provides a set of functions allowing to manage the USART 
+  IrDA communication.
+  
+  IrDA is a half duplex communication protocol. If the Transmitter is busy, any data
+  on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver 
+  is busy, data on the TX from the USART to IrDA will not be encoded by IrDA.
+  While receiving data, transmission should be avoided as the data to be transmitted
+  could be corrupted.
+
+  IrDA communication is possible through the following procedure:
+     1. Program the Baud rate, Word length = 8 bits, Stop bits, Parity, Transmitter/Receiver 
+        modes and hardware flow control values using the USART_Init() function.
+     2. Enable the USART using the USART_Cmd() function.
+     3. Configures the IrDA pulse width by configuring the prescaler using  
+        the USART_SetPrescaler() function.
+     4. Configures the IrDA  USART_IrDAMode_LowPower or USART_IrDAMode_Normal mode
+        using the USART_IrDAConfig() function.
+     5. Enable the IrDA using the USART_IrDACmd() function.
+
+Note: 
+-----
+  1. A pulse of width less than two and greater than one PSC period(s) may or may
+     not be rejected.
+  2. The receiver set up time should be managed by software. The IrDA physical layer
+     specification specifies a minimum of 10 ms delay between transmission and 
+     reception (IrDA is a half duplex protocol).
+  3. In IrDA mode, the following bits must be kept cleared:
+    - STOP and CLKEN bits in the USART_CR3 register.
+    - SCEN and HDSEL bits in the USART_CR5 register.
+
+@endverbatim
+  * @{
+  */
+	
+/**
+  * @brief  Configures the USART’s IrDA interface.
+  * @param  USARTx: where x can be 1 to select the specified USART peripheral.
+  * @param  USART_IrDAMode specifies the IrDA mode.
+  *           This parameter can be one of the following values:
+  *            @arg USART_IrDAMode_Normal: IrDA Normal Mode
+  *            @arg USART_IrDAMode_LowPower: IrDA Low Power Mode 
+  * @retval None
+  */
+void USART_IrDAConfig(USART_TypeDef* USARTx, USART_IrDAMode_TypeDef USART_IrDAMode)
+{
+  assert_param(IS_USART_IRDAMODE(USART_IrDAMode));
+
+  if (USART_IrDAMode != USART_IrDAMode_Normal)
+  {
+    USARTx->CR5 |= USART_CR5_IRLP;
+  }
+  else
+  {
+    USARTx->CR5 &= ((uint8_t)~USART_CR5_IRLP);
+  }
+}
+
+/**
+  * @brief  Enables or disables the USART’s IrDA interface.
+  * @param  USARTx: where x can be 1 to select the specified USART peripheral.
+  * @param  NewState new state of the IrDA mode.
+    *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+
+  /* Check parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the IrDA mode by setting the IREN bit in the CR3 register */
+    USARTx->CR5 |= USART_CR5_IREN;
+  }
+  else
+  {
+    /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */
+    USARTx->CR5 &= ((uint8_t)~USART_CR5_IREN);
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_Group7 DMA transfers management functions
+ *  @brief   DMA transfers management functions
+ *
+@verbatim   
+ ===============================================================================
+                      DMA transfers management functions
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+
+/**
+  * @brief  Enables or disables the USART DMA interface.
+  * @param  USARTx: where x can be 1 to select the specified USART peripheral.
+  * @param  USART_DMAReq Specifies the USART DMA transfer request to be enabled or disabled.
+  *           This parameter can be one of the following values:
+  *            @arg USART_DMAReq_TX: Receive DMA request Enable
+  *            @arg USART_DMAReq_RX: Transmit DMA request Enable 
+  * @param  NewState Indicates the new state of the USART DMA request.
+    *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void USART_DMACmd(USART_TypeDef* USARTx, USART_DMAReq_TypeDef USART_DMAReq,
+                  FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_DMAREQ(USART_DMAReq));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the DMA transfer for selected requests by setting the DMAT and/or
+       DMAR bits in the USART CR5 register */
+    USARTx->CR5 |= (uint8_t) USART_DMAReq;
+  }
+  else
+  {
+    /* Disable the DMA transfer for selected requests by clearing the DMAT and/or
+       DMAR bits in the USART CR5 register */
+    USARTx->CR5 &= (uint8_t)~USART_DMAReq;
+  }
+}
+
+/**
+  * @}
+  */
+  
+/** @defgroup USART_Group8 Interrupts and flags management functions
+ *  @brief   Interrupts and flags management functions 
+ *
+@verbatim   
+ ===============================================================================
+                   Interrupts and flags management functions
+ ===============================================================================  
+
+  This subsection provides a set of functions allowing to configure the USART 
+  Interrupts sources, DMA channels requests and check or clear the flags or 
+  pending bits status.
+  The user should identify which mode will be used in his application to manage 
+  the communication: Polling mode, Interrupt mode or DMA mode. 
+    
+  Polling Mode
+  =============
+  In Polling Mode, the USART communication can be managed by 9 flags:
+     1. USART_FLAG_TXE: to indicate the status of the transmit buffer register
+     2. USART_FLAG_RXNE: to indicate the status of the receive buffer register
+     3. USART_FLAG_TC: to indicate the status of the transmit operation
+     4. USART_FLAG_IDLE: to indicate the status of the Idle Line             
+     5. USART_FLAG_SBK: to indicate the status of the Send Break characters
+     6. USART_FLAG_NE: to indicate if a noise error occur
+     7. USART_FLAG_FE: to indicate if a frame error occur
+     8. USART_FLAG_PE: to indicate if a parity error occur
+     9. USART_FLAG_ORE: to indicate if an Overrun error occur
+
+  In this Mode it is advised to use the following functions:
+      - FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, USART_FLAG_TypeDef USART_FLAG);
+      - void USART_ClearFlag(USART_TypeDef* USARTx, USART_FLAG_TypeDef USART_FLAG);
+
+  Interrupt Mode
+  ===============
+  In Interrupt Mode, the USART communication can be managed by 7 interrupt sources
+  and 6 pending bits: 
+
+  Pending Bits:
+  ------------- 
+     1. USART_IT_TXE: to indicate the status of the transmit buffer register
+     2. USART_IT_RXNE: to indicate the status of the receive buffer register
+     3. USART_IT_TC: to indicate the status of the transmit operation
+     4. USART_IT_IDLE: to indicate the status of the Idle Line             
+     5. USART_IT_PE: to indicate if a parity error occur
+     6. USART_IT_OR: to indicate if an Noise flag, overrun error and framing error in
+											multibuffer communication error occur
+
+  Interrupt Source:
+  -----------------
+     1. USART_IT_TXE: specifies the interrupt source for the Tx buffer empty 
+                       interrupt. 
+     2. USART_IT_RXNE: specifies the interrupt source for the Rx buffer not 
+                        empty interrupt.
+     3. USART_IT_TC: specifies the interrupt source for the Transmit complete 
+											interrupt. 
+     4. USART_IT_IDLE: specifies the interrupt source for the Idle Line interrupt.
+     5. USART_IT_PE: specifies the interrupt source for the parity error interrupt. 
+     6. USART_IT_ERR:  specifies the interrupt source for the errors interrupt.
+		 7. USART_IT_OR: specifies the interrupt source for the overrun error interrupt.
+
+    Note: Some parameters are coded in order to use them as interrupt source or 
+    ----  as pending bits.
+
+  In this Mode it is advised to use the following functions:
+     - void USART_ITConfig(USART_TypeDef* USARTx, USART_IT_TypeDef USART_IT, FunctionalState
+                      		 NewState);
+     - ITStatus USART_GetITStatus(USART_TypeDef* USARTx, USART_IT_TypeDef USART_IT);
+     - void USART_ClearITPendingBit(USART_TypeDef* USARTx, USART_IT_TypeDef USART_IT);
+
+  DMA Mode
+  ========
+  In DMA Mode, the USART communication can be managed by 2 DMA Channel requests:
+     1. USART_DMAReq_Tx: specifies the Tx buffer DMA transfer request
+     2. USART_DMAReq_Rx: specifies the Rx buffer DMA transfer request
+
+  In this Mode it is advised to use the following function:
+     - void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState);
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the specified USART interrupts.
+  * @param  USARTx: where x can be 1 to select the specified USART peripheral.
+  * @param  USART_IT specifies the USART interrupt sources to be enabled or disabled.
+  *         This parameter can be one of the following values:
+  *            @arg USART_IT_TXE: Transmit Data Register empty interrupt
+  *            @arg USART_IT_TC: Transmission complete interrupt
+  *            @arg USART_IT_RXNE: Receive Data register not empty interrupt
+  *            @arg USART_IT_OR: Overrun error interrupt
+  *            @arg USART_IT_IDLE: Idle line detection interrupt
+  *            @arg USART_IT_ERR: Error interrupt
+  * @param  NewState new state of the specified USART interrupts.
+    *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void USART_ITConfig(USART_TypeDef* USARTx, USART_IT_TypeDef USART_IT, FunctionalState NewState)
+{
+  uint8_t usartreg, itpos = 0x00;
+  assert_param(IS_USART_CONFIG_IT(USART_IT));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Get the USART register index */
+  usartreg = (uint8_t)((uint16_t)USART_IT >> 0x08);
+  /* Get the USART IT index */
+  itpos = (uint8_t)((uint8_t)1 << (uint8_t)((uint8_t)USART_IT & (uint8_t)0x0F));
+
+  if (NewState != DISABLE)
+  {
+    /**< Enable the Interrupt bits according to USART_IT mask */
+    if (usartreg == 0x01)
+    {
+      USARTx->CR1 |= itpos;
+    }
+    else if (usartreg == 0x05)
+    {
+      USARTx->CR5 |= itpos;
+    }
+    /*uartreg =0x02*/
+    else
+    {
+      USARTx->CR2 |= itpos;
+    }
+  }
+  else
+  {
+    /**< Disable the interrupt bits according to USART_IT mask */
+    if (usartreg == 0x01)
+    {
+      USARTx->CR1 &= (uint8_t)(~itpos);
+    }
+    else if (usartreg == 0x05)
+    {
+      USARTx->CR5 &= (uint8_t)(~itpos);
+    }
+    /*uartreg =0x02*/
+    else
+    {
+      USARTx->CR2 &= (uint8_t)(~itpos);
+    }
+  }
+}
+
+/**
+  * @brief  Checks whether the specified USART flag is set or not.
+  * @param  USARTx: Select the USARTx peripheral.
+  * @param  USART_FLAG specifies the flag to check.
+  *         This parameter can be one of the following values:
+  *            @arg USART_FLAG_TXE: Transmit Data Register empty
+  *            @arg USART_FLAG_TC: Transmission Complete 
+  *            @arg USART_FLAG_RXNE: Read Data Register Not Empty
+  *            @arg USART_FLAG_IDLE: Idle line detected
+  *            @arg USART_FLAG_OR: OverRun error
+  *            @arg USART_FLAG_NF: Noise error
+  *            @arg USART_FLAG_FE: Framing Error
+  *            @arg USART_FLAG_PE: Parity Error
+  *            @arg USART_FLAG_SBK: Send Break characters               
+  * @retval FlagStatus (SET or RESET)
+  */
+FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, USART_FLAG_TypeDef USART_FLAG)
+{
+  FlagStatus status = RESET;
+
+  /* Check parameters */
+  assert_param(IS_USART_FLAG(USART_FLAG));
+
+  if (USART_FLAG == USART_FLAG_SBK)
+  {
+    if ((USARTx->CR2 & (uint8_t)USART_FLAG) != (uint8_t)0x00)
+    {
+      /* USART_FLAG is set*/
+      status = SET;
+    }
+    else
+    {
+      /* USART_FLAG is reset*/
+      status = RESET;
+    }
+  }
+  else
+  {
+    if ((USARTx->SR & (uint8_t)USART_FLAG) != (uint8_t)0x00)
+    {
+      /* USART_FLAG is set*/
+      status = SET;
+    }
+    else
+    {
+      /* USART_FLAG is reset*/
+      status = RESET;
+    }
+  }
+  /* Return the USART_FLAG status*/
+  return status;
+}
+
+/**
+  * @brief  Clears the USARTx's pending flags.
+  * @param  USARTx: where x can be 1 to select the specified USART peripheral.
+  * @param  USART_FLAG: specifies the flag to clear.
+  *         This parameter can be any combination of the following values:
+  *            @arg USART_FLAG_TC:   Transmission Complete flag.
+  *            @arg USART_FLAG_RXNE: Receive data register not empty flag.
+  * @note   PE (Parity error), FE (Framing error), NE (Noise error), OR (OverRun error)
+  *         and IDLE (Idle line detected) flags are cleared by software sequence: a read
+  *         operation to USART_SR register (USART_GetFlagStatus())followed by a read
+  *         operation to USART_DR register(USART_ReceiveData8() or USART_ReceiveData9()).
+  * @note   RXNE flag can be also cleared by a read to the USART_DR register
+  *         (USART_ReceiveData8()or USART_ReceiveData9()).
+  * @note   TC flag can be also cleared by software sequence: a read operation to USART_SR
+  *         register (USART_GetFlagStatus()) followed by a write operation to USART_DR
+  *         register (USART_SendData8() or USART_SendData9()).
+  * @note    TXE flag is cleared only by a write to the USART_DR register
+  *         (USART_SendData8() or USART_SendData9()).
+  * @note   SBK flag is cleared during the stop bit of break.
+  * @retval None
+  */
+void USART_ClearFlag(USART_TypeDef* USARTx, USART_FLAG_TypeDef USART_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_CLEAR_FLAG(USART_FLAG));
+  /*< Clear RXNE or TC flags */
+  USARTx->SR = (uint8_t)((uint16_t)~((uint16_t)USART_FLAG));
+}
+
+/**
+  * @brief  Checks whether the specified USART interrupt has occurred or not.
+  * @param  USARTx: where x can be 1 to select the specified USART peripheral.
+  * @param  USART_IT: Specifies the USART interrupt pending bit to check.
+  *         This parameter can be one of the following values:
+  *            @arg USART_IT_TXE: Transmit Data Register empty interrupt
+  *            @arg USART_IT_TC: Transmission complete interrupt
+  *            @arg USART_IT_RXNE: Receive Data register not empty interrupt
+  *            @arg USART_IT_IDLE: Idle line detection interrupt
+  *            @arg USART_IT_OR: OverRun Error interrupt
+  *            @arg USART_IT_PE: Parity Error interrupt
+  *            @arg USART_IT_FE: Frame Error interrupt
+  *            @arg USART_IT_NF: Noise Flag Error interrupt
+  * @retval ITStatus The new state of USART_IT (SET or RESET).
+  */
+ITStatus USART_GetITStatus(USART_TypeDef* USARTx, USART_IT_TypeDef USART_IT)
+{
+  ITStatus pendingbitstatus = RESET;
+  uint8_t temp = 0;
+  uint8_t itpos = 0;
+  uint8_t itmask1 = 0;
+  uint8_t itmask2 = 0;
+  uint8_t enablestatus = 0;
+
+  /* Check parameters */
+  assert_param(IS_USART_GET_IT(USART_IT));
+
+  /* Get the USART IT index */
+  itpos = (uint8_t)((uint8_t)1 << (uint8_t)((uint8_t)USART_IT & (uint8_t)0x0F));
+  /* Get the USART IT index */
+  itmask1 = (uint8_t)((uint8_t)USART_IT >> (uint8_t)4);
+  /* Set the IT mask*/
+  itmask2 = (uint8_t)((uint8_t)1 << itmask1);
+
+  /* Check the status of the specified USART pending bit*/
+  if (USART_IT == USART_IT_PE)
+  {
+    /* Get the USART_IT enable bit status*/
+    enablestatus = (uint8_t)((uint8_t)USARTx->CR1 & itmask2);
+    /* Check the status of the specified USART interrupt*/
+
+    if (((USARTx->SR & itpos) != (uint8_t)0x00) && enablestatus)
+    {
+      /* Interrupt occurred*/
+      pendingbitstatus = SET;
+    }
+    else
+    {
+      /* Interrupt not occurred*/
+      pendingbitstatus = RESET;
+    }
+  }
+
+  else if (USART_IT == USART_IT_OR)
+  {
+    /* Get the USART_IT enable bit status*/
+    enablestatus = (uint8_t)((uint8_t)USARTx->CR2 & itmask2);
+    /* Check the status of the specified USART interrupt*/
+
+    temp = (uint8_t)(USARTx->CR5 & USART_CR5_EIE);
+
+    if (( (USARTx->SR & itpos) != 0x00) && ((enablestatus || temp)))
+    {
+      /* Interrupt occurred*/
+      pendingbitstatus = SET;
+    }
+    else
+    {
+      /* Interrupt not occurred*/
+      pendingbitstatus = RESET;
+    }
+  }
+
+  else
+  {
+    /* Get the USART_IT enable bit status*/
+    enablestatus = (uint8_t)((uint8_t)USARTx->CR2 & itmask2);
+    /* Check the status of the specified USART interrupt*/
+    if (((USARTx->SR & itpos) != (uint8_t)0x00) && enablestatus)
+    {
+      /* Interrupt occurred*/
+      pendingbitstatus = SET;
+    }
+    else
+    {
+      /* Interrupt not occurred*/
+      pendingbitstatus = RESET;
+    }
+  }
+
+  /* Return the USART_IT status*/
+  return  pendingbitstatus;
+}
+
+/**
+  * @brief  Clears the USARTx’s interrupt pending bits.
+  * @param  USARTx: where x can be 1 to select the specified USART peripheral.
+  * @param  USART_IT: specifies the interrupt pending bit to clear.
+  *         This parameter can be one of the following values:
+  *            @arg USART_IT_TC: Transmission complete interrupt.
+  * @note   PE (Parity error), FE (Framing error), NE (Noise error),
+  *         OR (OverRun error) and IDLE (Idle line detected) pending bits are
+  *         cleared by software sequence: a read operation to USART_SR register
+  *         (USART_GetITStatus()) followed by a read operation to USART_DR
+  *         register (USART_ReceiveData8() or USART_ReceiveData9()).
+  * @note   RXNE pending bit can be also cleared by a read to the USART_DR register
+  *         (USART_ReceiveData8() or USART_ReceiveData9()).
+  * @note   TC (Transmit complete) pending bit can be also cleared by software
+  *         sequence: a read operation to USART_SR register (USART_GetITStatus())
+  *         followed by a write operation to USART_DR register (USART_SendData8()
+  *         or USART_SendData9()).
+  * @note   TXE pending bit is cleared only by a write to the USART_DR register
+  *         (USART_SendData8() or USART_SendData9()).
+  * @retval None
+  */
+void USART_ClearITPendingBit(USART_TypeDef* USARTx, USART_IT_TypeDef USART_IT)
+{
+  assert_param(IS_USART_CLEAR_IT(USART_IT));
+
+  /*< Clear RXNE or TC pending bit */
+  USARTx->SR &= (uint8_t)(~USART_SR_TC);
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_wfe.c b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_wfe.c
new file mode 100755
index 0000000..fb27153
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_wfe.c
@@ -0,0 +1,345 @@
+/**
+  ******************************************************************************
+  * @file    stm8l15x_wfe.c
+  * @author  MCD Application Team
+  * @version V1.6.0
+  * @date    28-June-2013
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Wait for Event (WFE) peripheral:           
+  *           - WFE Source configuration and management
+  *             
+  *  @verbatim
+  *               
+  *          ===================================================================
+  *                               WFE specific features
+  *          ===================================================================
+  *
+  *           Wait for event mode (WFE) stops the CPU but allows the other peripherals
+  *           and interrupt controller to continue running.
+  *           This mode is entered from Run mode by executing a WFE instruction.
+  *           Peripheral events can be generated by the timers, serial interfaces, 
+  *           DMA controller, comparators and I/O ports. 
+  *           These are enabled by using the WFE_WakeUpSourceEventCmd() function.
+  *           
+  *           When a peripheral event is enabled, the corresponding interrupts are 
+  *           not served and you have to clear the corresponding flag status.
+  *           
+  *           There are two ways to wake up the CPU from WFE mode:
+  *            - Interrupts: When an interrupt occurs, the CPU wakes up from WFE mode
+  *              serves the interrupt then goes back to WFE mode.
+  *            - Wake up event: when a wake up event occurs, the CPU wakes up and 
+  *              resumes processing, in this case and to save time and power consumption
+  *              there is no context save/restore activity.            
+  *                          
+  *
+  *  @endverbatim
+  *                 
+  ******************************************************************************
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ****************************************************************************** 
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm8l15x_wfe.h"
+
+/** @addtogroup STM8L15x_StdPeriph_Driver
+  * @{
+  */
+  
+/** @defgroup WFE 
+  * @brief WFE driver modules
+  * @{
+  */
+   
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup WFE_Private_Functions
+  * @{
+  */
+
+/** @defgroup WFE_Group1 WFE Source configuration and management functions 
+ *  @brief   WFE Source configuration and management functions  
+ *
+@verbatim   
+ ===============================================================================
+               WFE Source configuration and management functions 
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+ 
+/**
+  * @brief  Deinitializes the WFE registers to their default reset value.
+  * @param  None
+  * @retval None
+  */
+void WFE_DeInit(void)
+{
+  WFE->CR1 = WFE_CRX_RESET_VALUE;
+  WFE->CR2 = WFE_CRX_RESET_VALUE;
+  WFE->CR3 = WFE_CRX_RESET_VALUE;
+  WFE->CR4 = WFE_CRX_RESET_VALUE;
+}
+
+/**
+  * @brief  Set the source that can generate the wake-up event.
+  * @param  WFE_Source: The wake-up event source .
+  *          This parameter can be one of the following values:
+  *            @arg WFE_Source_TIM2_EV0: TIM2 Update/Trigger and Break interrupt  
+  *            @arg WFE_Source_TIM2_EV1: TIM2 Capture/Compare interrupt 
+  *            @arg WFE_Source_TIM1_EV0: TIM1 Update/Trigger and Break interrupt
+  *            @arg WFE_Source_TIM1_EV1: TIM1 Capture/Compare interrupt 
+  *            @arg WFE_Source_EXTI_EV0: I/O port interrupt from Pins 0
+  *            @arg WFE_Source_EXTI_EV1: I/O port interrupt from Pins 1
+  *            @arg WFE_Source_EXTI_EV2: I/O port interrupt from Pins 2
+  *            @arg WFE_Source_EXTI_EV3: I/O port interrupt from Pins 3
+  *            @arg WFE_Source_EXTI_EV4: I/O port interrupt from Pins 4
+  *            @arg WFE_Source_EXTI_EV5: I/O port interrupt from Pins 5
+  *            @arg WFE_Source_EXTI_EV6: I/O port interrupt from Pins 6
+  *            @arg WFE_Source_EXTI_EV7: I/O port interrupt from Pins 7
+  *            @arg WFE_Source_EXTI_EVB_G: I/O port interrupt from port B and G
+  *            @arg WFE_Source_EXTI_EVD_H: I/O port interrupt from Port D and H
+  *            @arg WFE_Source_EXTI_EVE_F: I/O port interrupt from Port E and F 
+  *            @arg WFE_Source_ADC1_COMP_EV: ADC1, COMP1 and COMP2 interrupts
+  *            @arg WFE_Source_TIM3_EV0: TIM3 Update/Trigger and Break interrupt
+  *            @arg WFE_Source_TIM3_EV1: TIM3 Capture/Compare interrupt
+  *            @arg WFE_Source_TIM4_EV: TIM4 Update and Trigger interrupt
+  *            @arg WFE_Source_SPI1_EV: SPI1 Rx and Tx interrupt
+  *            @arg WFE_Source_I2C1_EV: I2C1 Rx and Tx interrupt
+  *            @arg WFE_Source_USART1_EV: USART1 Rx and Tx interrupt
+  *            @arg WFE_Source_DMA1CH01_EV: DMA1 channel 0 and  1 interrupt
+  *            @arg WFE_Source_DMA1CH23_EV: DMA1 channel 2 and  3  interrupt 
+  *            @arg WFE_Source_RTC_CSS_EV: RTC or CSS on LSE event
+  *            @arg WFE_Source_SPI2_EV: SPI2 Rx and Tx interrupt
+  *            @arg WFE_Source_USART2_EV: USART2 Rx and Tx interrupt
+  *            @arg WFE_Source_USART3_EV: USART3 Rx and Tx interrupt
+  *            @arg WFE_Source_TIM5_EV0: TIM5 Update/Trigger and Break interrupt
+  *            @arg WFE_Source_TIM5_EV1: TIM5 Capture/Compare interrupt                                                        
+  * @param  NewState : The wake-up new state.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void WFE_WakeUpSourceEventCmd(WFE_Source_TypeDef WFE_Source, FunctionalState NewState)
+{
+  uint8_t register_index = 0;
+  /* Check function parameters */
+  assert_param(IS_WFE_SOURCE(WFE_Source));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* The mask is reversed in order to  */
+  register_index = (uint8_t)((uint16_t)WFE_Source >> 0x08);
+
+  if (NewState != DISABLE)
+  {
+    switch (register_index)
+    {
+      case 1:
+        WFE->CR1 |= (uint8_t)WFE_Source;
+        break;
+
+      case 2:
+        WFE->CR2 |= (uint8_t)WFE_Source;
+        break;
+
+      case 3:
+        WFE->CR3 |= (uint8_t)WFE_Source;
+        break;
+
+      case 4:
+        WFE->CR4 |= (uint8_t)WFE_Source;
+        break;
+
+      default:
+        break;
+    }
+  }
+  else
+  {
+    switch (register_index)
+    {
+      case 1:
+        WFE->CR1 &= (uint8_t)(~(uint8_t)WFE_Source);
+        break;
+
+      case 2:
+        WFE->CR2 &= (uint8_t)(~ (uint8_t)WFE_Source);
+        break;
+
+      case 3:
+        WFE->CR3 &= (uint8_t)(~(uint8_t)WFE_Source);
+        break;
+
+      case 4:
+        WFE->CR4 &= (uint8_t)(~(uint8_t)WFE_Source);
+        break;
+
+      default:
+        break;
+    }
+  }
+}
+
+/**
+  * @brief  Gets the status of the specified source event.
+  * @param  WFE_Source: The wake-up event source.
+  *          This parameter can be one of the following values:
+  *            @arg WFE_Source_TIM2_EV0: TIM2 Update/Trigger and Break interrupt  
+  *            @arg WFE_Source_TIM2_EV1: TIM2 Capture/Compare interrupt 
+  *            @arg WFE_Source_TIM1_EV0: TIM1 Update/Trigger and Break interrupt
+  *            @arg WFE_Source_TIM1_EV1: TIM1 Capture/Compare interrupt 
+  *            @arg WFE_Source_EXTI_EV0: I/O port interrupt from Pins 0
+  *            @arg WFE_Source_EXTI_EV1: I/O port interrupt from Pins 1
+  *            @arg WFE_Source_EXTI_EV2: I/O port interrupt from Pins 2
+  *            @arg WFE_Source_EXTI_EV3: I/O port interrupt from Pins 3
+  *            @arg WFE_Source_EXTI_EV4: I/O port interrupt from Pins 4
+  *            @arg WFE_Source_EXTI_EV5: I/O port interrupt from Pins 5
+  *            @arg WFE_Source_EXTI_EV6: I/O port interrupt from Pins 6
+  *            @arg WFE_Source_EXTI_EV7: I/O port interrupt from Pins 7
+  *            @arg WFE_Source_EXTI_EVB_G: I/O port interrupt from port B and G
+  *            @arg WFE_Source_EXTI_EVD_H: I/O port interrupt from Port D and H
+  *            @arg WFE_Source_EXTI_EVE_F: I/O port interrupt from Port E and F 
+  *            @arg WFE_Source_ADC1_COMP_EV: ADC1, COMP1 and COMP2 interrupts
+  *            @arg WFE_Source_TIM3_EV0: TIM3 Update/Trigger and Break interrupt
+  *            @arg WFE_Source_TIM3_EV1: TIM3 Capture/Compare interrupt
+  *            @arg WFE_Source_TIM4_EV: TIM4 Update and Trigger interrupt
+  *            @arg WFE_Source_SPI1_EV: SPI1 Rx and Tx interrupt
+  *            @arg WFE_Source_I2C1_EV: I2C1 Rx and Tx interrupt
+  *            @arg WFE_Source_USART1_EV: USART1 Rx and Tx interrupt
+  *            @arg WFE_Source_DMA1CH01_EV: DMA1 channel 0 and  1 interrupt
+  *            @arg WFE_Source_DMA1CH23_EV: DMA1 channel 2 and  3  interrupt 
+  *            @arg WFE_Source_RTC_CSS_EV: RTC or CSS on LSE event
+  *            @arg WFE_Source_SPI2_EV: SPI2 Rx and Tx interrupt
+  *            @arg WFE_Source_USART2_EV: USART2 Rx and Tx interrupt
+  *            @arg WFE_Source_USART3_EV: USART3 Rx and Tx interrupt
+  *            @arg WFE_Source_TIM5_EV0: TIM5 Update/Trigger and Break interrupt
+  *            @arg WFE_Source_TIM5_EV1: TIM5 Capture/Compare interrupt  
+  * @retval Source Event state, ENABLE or DISABLE
+  */
+FunctionalState WFE_GetWakeUpSourceEventStatus(WFE_Source_TypeDef WFE_Source)
+{
+  FunctionalState status = DISABLE;
+  /* Check function parameters */
+  assert_param(IS_WFE_SOURCE(WFE_Source));
+
+  switch (WFE_Source)
+  {
+    case WFE_Source_TIM2_EV0:
+    case WFE_Source_TIM2_EV1:
+    case WFE_Source_TIM1_EV0:
+    case WFE_Source_TIM1_EV1:
+    case WFE_Source_EXTI_EV0:
+    case WFE_Source_EXTI_EV1:
+    case WFE_Source_EXTI_EV2:
+    case WFE_Source_EXTI_EV3:
+
+      if ((WFE->CR1 & (uint8_t)WFE_Source) != (uint8_t)0x00)
+      {
+        /* The wake-up event source is enabled*/
+        status = ENABLE;
+      }
+      else
+      {
+        /* The wake-up event source is disabled*/
+        status = DISABLE;
+      }
+      break;
+
+    case WFE_Source_EXTI_EV4:
+    case WFE_Source_EXTI_EV5:
+    case WFE_Source_EXTI_EV6:
+    case WFE_Source_EXTI_EV7:
+    case WFE_Source_EXTI_EVB_G:
+    case WFE_Source_EXTI_EVD_H:
+    case WFE_Source_EXTI_EVE_F:
+    case WFE_Source_ADC1_COMP_EV:
+
+      if ((WFE->CR2 & (uint8_t)WFE_Source) != (uint8_t)0x00)
+      {
+        /* The wake-up event source is enabled*/
+        status = ENABLE;
+      }
+      else
+      {
+        /* The wake-up event source is disabled*/
+        status = DISABLE;
+      }
+      break;
+    case WFE_Source_TIM3_EV0:
+    case WFE_Source_TIM3_EV1:
+    case WFE_Source_TIM4_EV:
+    case WFE_Source_SPI1_EV:
+    case WFE_Source_I2C1_EV:
+    case WFE_Source_USART1_EV:
+    case WFE_Source_DMA1CH01_EV:
+    case WFE_Source_DMA1CH23_EV:
+
+      if ((WFE->CR3 & (uint8_t)WFE_Source) != (uint8_t)0x00)
+      {
+        /* The wake-up event source is enabled*/
+        status = ENABLE;
+      }
+      else
+      {
+        /* The wake-up event source is disabled*/
+        status = DISABLE;
+      }
+      break;
+
+    case WFE_Source_TIM5_EV0:
+    case WFE_Source_TIM5_EV1:
+    case WFE_Source_AES_EV:
+    case WFE_Source_SPI2_EV:
+    case WFE_Source_USART2_EV:
+    case WFE_Source_USART3_EV:
+    case WFE_Source_RTC_CSS_EV:
+
+      if ((WFE->CR4 & (uint8_t)WFE_Source) != (uint8_t)0x00)
+      {
+        /* The wake-up event source is enabled*/
+        status = ENABLE;
+      }
+      else
+      {
+        /* The wake-up event source is disabled*/
+        status = DISABLE;
+      }
+      break;
+    default:
+      break;
+  }
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_wwdg.c b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_wwdg.c
new file mode 100755
index 0000000..aa4e6b1
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/src/stm8l15x_wwdg.c
@@ -0,0 +1,244 @@
+/**
+  ********************************************************************************
+  * @file    stm8l15x_wwdg.c
+  * @author  MCD Application Team
+  * @version V1.6.0
+  * @date    28-June-2013
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Window watchdog (WWDG) peripheral:           
+  *           - Refresh window and Counter configuration
+  *           - WWDG activation
+  *           - Couter and software reset management
+  *             
+  *  @verbatim
+  *    
+  *          ===================================================================
+  *                                     WWDG features
+  *          ===================================================================
+  *                                        
+  *          Once enabled the WWDG generates a system reset on expiry of a programmed
+  *          time period, unless the program refreshes the counter (downcounter) 
+  *          before to reach 0x3F value (i.e. a reset is generated when the counter
+  *          value rolls over from 0x40 to 0x3F). 
+  *          An MCU reset is also generated if the counter value is refreshed
+  *          before the counter has reached the refresh window value. This 
+  *          implies that the counter must be refreshed in a limited window.
+  *            
+  *          Once enabled the WWDG cannot be disabled except by a system reset.
+  *          
+  *          If the WWDG is activated and the watchdog reset on halt option is 
+  *          selected (Option byte), then the HALT instruction will generate a reset.                               
+  *          
+  *          WWDGF flag in RST_SR register can be used to inform when a WWDG
+  *          reset occurs.
+  *            
+  *          WWDG timeout = (WWDG counter clock) * 12288 * (T[5:0] + 1)
+  *                      
+  *          Min-max timeout value @16 MHz(PCLK1): ~0.768 ms / ~49.152 ms
+  *                            
+  *          ===================================================================
+  *                                 How to use this driver
+  *          =================================================================== 
+  *          1. Configure the WWDG refresh window using WWDG_SetWindowValue() function
+  *            
+  *          2. Set the WWDG counter value and start it using WWDG_Enable() function.
+  *             When the WWDG is enabled the counter value should be configured to 
+  *             a value greater than 0x40 to prevent generating an immediate reset.     
+  *            
+  *          3. Then the application program must refresh the WWDG counter at regular
+  *             intervals during normal operation to prevent an MCU reset, using
+  *             WWDG_SetCounter() function. This operation must occur only when
+  *             the counter value is lower than the refresh window value, 
+  *             programmed using WWDG_SetWindowValue().         
+  *
+  *  @endverbatim  
+  *                             
+  ******************************************************************************
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ****************************************************************************** 
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm8l15x_wwdg.h"
+
+/** @addtogroup STM8L15x_StdPeriph_Driver
+  * @{
+  */
+/** @defgroup WWDG 
+  * @brief WWDG driver modules
+  * @{
+  */
+  
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define BIT_MASK          ((uint8_t)0x7F)
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup WWDG_Private_Functions
+  * @{
+  */
+  
+/** @defgroup WWDG_Group1 Refresh window and Counter configuration functions
+ *  @brief   Refresh window and Counter configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+              Refresh window and Counter configuration functions
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Initializes the WWDG peripheral.
+  *         This function set Window Register = WindowValue, Counter Register
+  *         according to Counter and \b ENABLE \b WWDG
+  * @param  Counter : WWDG counter value
+  * @param  WindowValue : specifies the WWDG Window Register, range is 0x00 to 0x7F.
+  * @retval None
+  */
+void WWDG_Init(uint8_t Counter, uint8_t WindowValue)
+{
+  /* Check the parameters */
+  assert_param(IS_WWDG_WINDOW_LIMIT_VALUE(WindowValue));
+  
+  WWDG->WR = WWDG_WR_RESET_VALUE;
+  WWDG->CR = (uint8_t)(WWDG_CR_WDGA | Counter);
+  WWDG->WR = (uint8_t)((uint8_t)BIT_MASK & (uint8_t) WindowValue);
+}
+
+/**
+  * @brief  Sets the WWDG window value.
+  * @param  WindowValue: specifies the window value to be compared to the downcounter.
+  *         This parameter value must be lower than 0x80.
+  * @retval None
+  */
+void WWDG_SetWindowValue(uint8_t WindowValue)
+{
+  __IO uint8_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_WWDG_WINDOW_LIMIT_VALUE(WindowValue));
+
+  /* Set W[6:0] bits according to WindowValue value */
+  tmpreg |= (uint8_t) (WindowValue & (uint8_t) BIT_MASK);
+
+  /* Store the new value */
+  WWDG->WR = tmpreg;
+}
+
+/**
+  * @brief  Sets the WWDG counter value.
+  * @param  Counter: specifies the watchdog counter value.
+  *   This parameter must be a number between 0x40 and 0x7F (to prevent generating
+  *   an immediate reset) 
+  * @retval None
+  */
+void WWDG_SetCounter(uint8_t Counter)
+{
+  /* Check the parameters */
+  assert_param(IS_WWDG_COUNTER_VALUE(Counter));
+
+  /* Write to T[6:0] bits to configure the counter value, no need to do
+     a read-modify-write; writing a 0 to WDGA bit does nothing */
+  WWDG->CR = (uint8_t)(Counter & (uint8_t)BIT_MASK);
+}
+/**
+  * @}
+  */
+
+/** @defgroup WWDG_Group2 WWDG activation function 
+ *  @brief   WWDG activation function  
+ *
+@verbatim   
+ ===============================================================================
+                          WWDG activation function 
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Enables WWDG and load the counter value.
+  * @param  Counter: specifies the watchdog counter value.
+  *         This parameter must be a number between 0x40 and 0x7F.
+  * @retval None
+  */
+void WWDG_Enable(uint8_t Counter)
+{
+  /* Check the parameters */
+  assert_param(IS_WWDG_COUNTER_VALUE(Counter));
+  WWDG->CR = (uint8_t)(WWDG_CR_WDGA | Counter);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup WWDG_Group3 WWDG counter and software reset management 
+ *  @brief   WWDG counter and software reset management
+ *
+@verbatim   
+ ===============================================================================
+                   WWDG counter and software reset management 
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief Gets the WWDG Counter Value.
+  *        This value could be used to check if WWDG is in the window, where
+  *        refresh is allowed.
+  * @param  None
+  * @retval WWDG Counter Value
+  */
+uint8_t WWDG_GetCounter(void)
+{
+  return(WWDG->CR);
+}
+
+/**
+  * @brief Generates immediate WWDG RESET.
+  * @param  None
+  * @retval None
+  */
+void WWDG_SWReset(void)
+{
+  WWDG->CR = WWDG_CR_WDGA; /* Activate WWDG, with clearing T6 */
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/stm8l15x_conf.h b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/stm8l15x_conf.h
new file mode 100755
index 0000000..3eb9396
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/4_STM8_L15x_StdPeriph_Drivers/stm8l15x_conf.h
@@ -0,0 +1,88 @@
+/**
+  ******************************************************************************
+  * @file    ADC/ADC_IT/stm8l15x_conf.h
+  * @author  MCD Application Team
+  * @version V1.5.1
+  * @date    28-June-2013
+  * @brief   Library configuration file.
+  ******************************************************************************
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */  
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM8L15x_CONF_H
+#define __STM8L15x_CONF_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm8l15x.h"
+
+/* Uncomment the line below to enable peripheral header file inclusion */
+#include "stm8l15x_adc.h"
+#include "stm8l15x_aes.h"
+#include "stm8l15x_beep.h"
+#include "stm8l15x_clk.h"
+#include "stm8l15x_comp.h"
+#include "stm8l15x_dac.h"
+#include "stm8l15x_dma.h"
+#include "stm8l15x_exti.h"
+#include "stm8l15x_flash.h"
+#include "stm8l15x_gpio.h"
+#include "stm8l15x_i2c.h"
+#include "stm8l15x_irtim.h"
+#include "stm8l15x_itc.h"
+#include "stm8l15x_iwdg.h"
+#include "stm8l15x_lcd.h"
+#include "stm8l15x_pwr.h"
+#include "stm8l15x_rst.h"
+#include "stm8l15x_rtc.h"
+#include "stm8l15x_spi.h"
+#include "stm8l15x_syscfg.h"
+#include "stm8l15x_tim1.h"
+#include "stm8l15x_tim2.h"
+#include "stm8l15x_tim3.h"
+#include "stm8l15x_tim4.h"
+#include "stm8l15x_tim5.h"
+#include "stm8l15x_usart.h"
+#include "stm8l15x_wfe.h"
+#include "stm8l15x_wwdg.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Uncomment the line below to expanse the "assert_param" macro in the 
+   Standard Peripheral Library drivers code */
+/* #define USE_FULL_ASSERT    (1) */ 
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param expr: If expr is false, it calls assert_failed function
+  *   which reports the name of the source file and the source
+  *   line number of the call that failed. 
+  *   If expr is true, it returns no value.
+  * @retval : None
+  */
+  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+#endif /* __STM8L15x_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/NSPE/WIFI_IOT/bsp/drivers/readme.c b/NSPE/WIFI_IOT/bsp/drivers/readme.c
new file mode 100755
index 0000000..fb566b3
--- /dev/null
+++ b/NSPE/WIFI_IOT/bsp/drivers/readme.c
@@ -0,0 +1,21 @@
+
+
+|-E15-EVB02-E48-DEMO //Ö÷Îļþ¼Ð
+| |
+| |-0_Project
+|   |_IAR_for_Stm8   //¹¤³ÌÎļþ¼Ð£¬ÓÃIAR´ò¿ª  
+|
+| |-1_Middleware
+|   |¡ªKfifo          //ͨÓÃÊý×é¶ÓÁÐ    
+|   |_Produce        //PC²âÊÔ
+|
+| |-2_Ebyte_Board_Support
+|   |_E15-EVB02      //°åÔØ×ÊÔ´³õʼ»¯
+|
+| |-3_Ebyte_WirelessModule_Drivers
+|   |_E48xMx         //E48Çý¶¯
+|
+| |-4_STM8_L15x_StdPeriph_Drivers
+
+
+