From eacd045dfdaae71218cba6e11b88d36df2031d93 Mon Sep 17 00:00:00 2001 From: gaoyang3513 Date: Thu, 1 Aug 2024 10:17:12 +0800 Subject: [PATCH] =?UTF-8?q?[Mod]=20=E6=8C=89=E4=BC=98=E5=8C=96=E6=96=B9?= =?UTF-8?q?=E6=A1=88=E4=BF=AE=E6=94=B9=EF=BC=8C=E5=AE=8C=E6=95=B4=E5=88=9D?= =?UTF-8?q?=E5=A7=8B=E5=8C=96=E6=AD=A3=E5=B8=B8?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- NSPE/WIFI_IOT/app/main.c | 4 +- NSPE/WIFI_IOT/bsp/drivers/.editorconfig | 12 + .../E48xMx/CMT2310A_reg.h | 466 +++++++++--------- .../E48xMx/ebyte_e48x.c | 25 +- .../E48xMx/radio.c | 372 +++++++------- .../E48xMx/radio_hal.c | 44 +- .../E48xMx/radio_hal.h | 64 +-- 7 files changed, 528 insertions(+), 459 deletions(-) create mode 100644 NSPE/WIFI_IOT/bsp/drivers/.editorconfig diff --git a/NSPE/WIFI_IOT/app/main.c b/NSPE/WIFI_IOT/app/main.c index ccb6777..52d3e61 100644 --- a/NSPE/WIFI_IOT/app/main.c +++ b/NSPE/WIFI_IOT/app/main.c @@ -197,11 +197,11 @@ int main(void) } #endif // CONFIG_TASK_LED - if (NULL == sys_task_create(NULL, (const uint8_t *)"sub1g_task", NULL, START_TASK_STK_SIZE, 0, START_TASK_PRIO, sub1g_task, NULL)) { + if (NULL == sys_task_create(NULL, (const uint8_t *)"start_task", NULL, START_TASK_STK_SIZE, 0, START_TASK_PRIO, start_task, NULL)) { DEBUGPRINT("ERROR: create start task failed\r\n"); } - if (NULL == sys_task_create(NULL, (const uint8_t *)"start_task", NULL, START_TASK_STK_SIZE, 0, START_TASK_PRIO, start_task, NULL)) { + if (NULL == sys_task_create(NULL, (const uint8_t *)"sub1g_task", NULL, START_TASK_STK_SIZE, 0, START_TASK_PRIO, sub1g_task, NULL)) { DEBUGPRINT("ERROR: create start task failed\r\n"); } diff --git a/NSPE/WIFI_IOT/bsp/drivers/.editorconfig b/NSPE/WIFI_IOT/bsp/drivers/.editorconfig new file mode 100644 index 0000000..98ccd7f --- /dev/null +++ b/NSPE/WIFI_IOT/bsp/drivers/.editorconfig @@ -0,0 +1,12 @@ +# EditorConfig is awesome: https://EditorConfig.org + +# top-most EditorConfig file +root = true + +[*] +indent_style = tab +indent_size = 8 +end_of_line = lf +charset = utf-8 +trim_trailing_whitespace = true +insert_final_newline = false \ No newline at end of file diff --git a/NSPE/WIFI_IOT/bsp/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/CMT2310A_reg.h b/NSPE/WIFI_IOT/bsp/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/CMT2310A_reg.h index 905f9d7..c5a48ef 100755 --- a/NSPE/WIFI_IOT/bsp/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/CMT2310A_reg.h +++ b/NSPE/WIFI_IOT/bsp/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/CMT2310A_reg.h @@ -17,7 +17,7 @@ * @date Dec 7 2021 * @author CMOSTEK R&D */ - + #ifndef __CMT2310A_REG_H @@ -28,118 +28,118 @@ #define CMT2310A_PAGE2_SIZE (0x3f-0x00+1) //---------------------- CUS PAGE0 defines ------------------------------- -//------------------------------------------------------------------------ +//------------------------------------------------------------------------ #define CMT2310A_CTL_REG_00 0x00 // PU_BOOT<7:0> #define CMT2310A_REBOOT 0x03 - + #define CMT2310A_CTL_REG_01 0x01 // radio chip status switch #define CMT2310A_GO_SLEEP (1<<0) // radio go sleep #define CMT2310A_GO_READY (1<<1) // radio go ready #define CMT2310A_GO_TX (1<<2) // radio go tx - #define CMT2310A_GO_RX (1<<3) // radio go rx + #define CMT2310A_GO_RX (1<<3) // radio go rx #define CMT2310A_GO_TFS (1<<4) // radio go tfs #define CMT2310A_GO_RFS (1<<5) // radio go rfs - + #define CMT2310A_CTL_REG_02 0x02 // Antenna Diversity #define CMT2310A_ANT_DIV_MANU (1<<1) // 0=disable antenna diversity, 1=enable antenna diversity #define CMT2310A_ANT_SELECT (1<<0) // 0=select antenna_1, 1=select antenna_2, when antenna diversity manual active - + #define CMT2310A_CTL_REG_03 0x03 // frequencry channel value, by manual set - + #define CMT2310A_CTL_REG_04 0x04 // gpio ctrl 0 #define CMT2310A_TX_DIN_EN (1<<6) // 0=disable TX_DATA input to GPIO, 1=enable TX_DATA input to GPIO - + #define CMT2310A_GPIO1_SEL (7<<3) // masker #define CMT2310A_GPIO1_DCLK (0<<3) // gpio1 as DCLK #define CMT2310A_GPIO1_INT1 (1<<3) // gpio1 as INT1 #define CMT2310A_GPIO1_INT2 (2<<3) // gpio1 as INT2 - #define CMT2310A_GPIO1_DOUT (3<<3) // goio1 as DOUT - + #define CMT2310A_GPIO1_DOUT (3<<3) // goio1 as DOUT + #define CMT2310A_GPIO0_SEL (7<<0) // masker #define CMT2310A_GPIO0_DOUT (0<<0) // gpio0 as DOUT #define CMT2310A_GPIO0_INT1 (1<<0) // gpio0 as INT1 #define CMT2310A_GPIO0_INT2 (2<<0) // gpio0 as INT2 #define CMT2310A_GPIO0_DCLK (3<<0) // goio0 as DCLK #define CMT2310A_GPIO0_INT3 (6<<0) // gpio0 as INT3 - + #define CMT2310A_CTL_REG_05 0x05 // gpio ctrl 1 #define CMT2310A_TX_DIN_SEL (3<<6) // masker #define CMT2310A_TX_DIN_GPIO3 (0<<6) // TX_DIN from GPIO3 #define CMT2310A_TX_DIN_GPIO4 (1<<6) // TX_DIN from GPIO4 #define CMT2310A_TX_DIN_nIRQ (2<<6) // TX_DIN from nIRQ - + #define CMT2310A_GPIO3_SEL (7<<3) //masker #define CMT2310A_GPIO3_INT2 (0<<3) // gpio3 as INT2 - #define CMT2310A_GPIO3_INT1 (1<<3) // gpio3 as INT1 - #define CMT2310A_GPIO3_DCLK (2<<3) // gpio3 as DCLK + #define CMT2310A_GPIO3_INT1 (1<<3) // gpio3 as INT1 + #define CMT2310A_GPIO3_DCLK (2<<3) // gpio3 as DCLK #define CMT2310A_GPIO3_DOUT (3<<3) // gpio3 as DOUT #define CMT2310A_GPIO3_DIN (5<<3) // gpio3 as DIN (TX_DIN) - + #define CMT2310A_GPIO2_SEL (7<<0) //masker #define CMT2310A_GPIO2_INT1 (0<<0) // gpio2 as INT1 #define CMT2310A_GPIO2_INT2 (1<<0) // gpio2 as INT2 #define CMT2310A_GPIO2_DCLK (2<<0) // gpio2 as DCLK #define CMT2310A_GPIO2_DOUT (3<<0) // gpio2 as DOUT #define CMT2310A_GPIO2_INT3 (6<<0) // gpio2 as INT3 - + #define CMT2310A_CTL_REG_06 0x06 // gpio ctrl 2 #define CMT2310A_DIG_CLKOUT_EN (1<<6) // 0=bypass, 1=enable digital clock out to GPIO4 - + #define CMT2310A_GPIO5_SEL (7<<3) //masker #define CMT2310A_GPIO5_nRST (0<<3) // gpio5 as nRST #define CMT2310A_GPIO5_INT1 (1<<3) // goio5 as INT1 #define CMT2310A_GPIO5_INT2 (2<<3) // gpio5 as INT2 #define CMT2310A_GPIO5_DOUT (3<<3) // gpio5 as DOUT #define CMT2310A_GPIO5_DCLK (4<<3) // gpio5 as DCLK - + #define CMT2310A_GPIO4_SEL (7<<0) //masker #define CMT2310A_GPIO4_DOUT (0<<0) // gpio4 as DOUT #define CMT2310A_GPIO4_INT1 (1<<0) // gpio4 as INT1 #define CMT2310A_GPIO4_INT2 (2<<0) // gpio4 as INT2 #define CMT2310A_GPIO4_DCLK (3<<0) // gpio4 as DCLK #define CMT2310A_GPIO4_DIN (5<<0) // gpio4 as DIN (TX_DIN) - + #define CMT2310A_CTL_REG_07 0x07 // nIRQ select #define CMT2310A_CTL_REG_07_MASK (3<<6) #define CMT2310A_LFXO_PAD_EN (1<<5) // 0=disable, 1=enable GPIO2 & GPIO3 as 32.768kHz crystal pin #define CMT2310A_API_STOP (1<<4) // 0=API go on, 1=stop API #define CMT2310A_SPI_3W_EN (1<<3) // 0=select SPI-4, 1=select SPI-3 - + #define CMT2310A_nIRQ_SEL (7<<0) //masker #define CMT2310A_nIRQ_INT1 (0<<0) // nIRQ as INT1 #define CMT2310A_nIRQ_INT2 (1<<0) // nIRQ as INT2 #define CMT2310A_nIRQ_DCLK (2<<0) // nIRQ as DCLK #define CMT2310A_nIRQ_DOUT (3<<0) // nIRQ as DOUT #define CMT2310A_nIRQ_TCXO (4<<0) // nIRQ as TCXO control pin - #define CMT2310A_nIRQ_DIN (5<<0) // nIRQ as DIN (TX_DIN) - + #define CMT2310A_nIRQ_DIN (5<<0) // nIRQ as DIN (TX_DIN) + #define CMT2310A_CTL_REG_08 0x08 //API Command interface #define CMT2310A_API_CMD_REG 0x08 - + #define CMT2310A_CTL_REG_09 0x09 #define CMT2310A_API_CMD_FLAG (1<<7) //API Command flag #define CMT2310A_API_RESP_MASK 0x7F //API Respond value - + #define CMT2310A_CTL_REG_10 0x0A // radio status register (-RO) - #define CMT2310A_CHIP_MODE_STA_REG 0x0A // - #define CMT2310A_STATE_IS_IDLE 0x00 // radio is in idle - #define CMT2310A_STATE_IS_SLEEP 0x81 // radio is in sleep - #define CMT2310A_STATE_IS_READY 0x82 // radio is in ready - #define CMT2310A_STATE_IS_RFS 0x84 // radio is in RFS - #define CMT2310A_STATE_IS_TFS 0x88 // radio is in TFS - #define CMT2310A_STATE_IS_RX 0x90 // radio is in RX - #define CMT2310A_STATE_IS_TX 0xA0 // radio is in TX - - #define CMT2310A_CTL_REG_11 0x0B // auto frequencry hopping done times + #define CMT2310A_CHIP_MODE_STA_REG 0x0A // + #define CMT2310A_STATE_IS_IDLE 0x00 // radio is in idle + #define CMT2310A_STATE_IS_SLEEP 0x81 // radio is in sleep + #define CMT2310A_STATE_IS_READY 0x82 // radio is in ready + #define CMT2310A_STATE_IS_RFS 0x84 // radio is in RFS + #define CMT2310A_STATE_IS_TFS 0x88 // radio is in TFS + #define CMT2310A_STATE_IS_RX 0x90 // radio is in RX + #define CMT2310A_STATE_IS_TX 0xA0 // radio is in TX + + #define CMT2310A_CTL_REG_11 0x0B // auto frequencry hopping done times // range 0-63 - - #define CMT2310A_CTL_REG_12 0x0C // auto frequencry hopping channel space - #define CMT2310A_FREQ_SPACE_REG 0x0C - + + #define CMT2310A_CTL_REG_12 0x0C // auto frequencry hopping channel space + #define CMT2310A_FREQ_SPACE_REG 0x0C + #define CMT2310A_CTL_REG_13 0x0D // auto frequencry hopping times - #define CMT2310A_FREQ_TIMES_REG 0x0D // range 1-64(n+1) - - #define CMT2310A_CTL_REG_14 0x0E // fifo status interrupt control register + #define CMT2310A_FREQ_TIMES_REG 0x0D // range 1-64(n+1) + + #define CMT2310A_CTL_REG_14 0x0E // fifo status interrupt control register #define CMT2310A_RX_FIFO_FULL_EN (1<<7) // 0=disable, 1=enable rx fifo full interrupt #define CMT2310A_RX_FIFO_NMTY_EN (1<<6) // 0=disable, 1=enable rx fifo non-empty interrupt #define CMT2310A_RX_FIFO_TH_EN (1<<5) // 0=disable, 1=enable rx fifo threshold interrupt @@ -147,16 +147,16 @@ #define CMT2310A_TX_FIFO_FULL_EN (1<<2) // 0=disable, 1=enable tx fifo full interrupt #define CMT2310A_TX_FIFO_NMTY_EN (1<<1) // 0=disable, 1=enable tx fifo non-empty interrupt #define CMT2310A_TX_FIFO_TH_EN (1<<0) // 0=disable, 1=enable tx fifo threshold interrupt - + #define CMT2310A_CTL_REG_15 0x0F // antenna diversity indicate #define CMT2310A_ANT_INSTR (1<<0) // indicate antenna diversity lock which antenna - + #define CMT2310A_CTL_REG_16 0x10 // interrupt1 selection #define CMT2310A_INT1_SEL_REG 0x10 #define CMT2310A_INT1_SEL_MASK 0x3F - #define CMT2310A_CTL_REG_17 0x11 // interrupt2 selection + #define CMT2310A_CTL_REG_17 0x11 // interrupt2 selection #define CMT2310A_INT2_SEL_REG 0x11 #define CMT2310A_INT1_POLAR (1<<7) // int1 polar selection, 0=high acitve, 1=low acitve; #define CMT2310A_INT2_POLAR (1<<6) // int1 polar selection, 0=high acitve, 1=low acitve; @@ -168,7 +168,7 @@ #define CMT2310A_INT_PREAM_PASS (3<<0) // preamble detected #define CMT2310A_INT_SYNC_PASS (4<<0) // sync word detected #define CMT2310A_INT_ADDR_PASS (5<<0) // node address detected - #define CMT2310A_INT_CRC_PASS (6<<0) // crc ok detected + #define CMT2310A_INT_CRC_PASS (6<<0) // crc ok detected #define CMT2310A_INT_PKT_OK (7<<0) // packet received detected #define CMT2310A_INT_PKT_DONE (8<<0) // packet received detected, even wrong packet or collision #define CMT2310A_INT_SLEEP_TMO (9<<0) // sleep timer time-out @@ -196,13 +196,13 @@ #define CMT2310A_INT_SEQ_MATCH (31<<0) // sequence number match #define CMT2310A_INT_CSMA_DONE (32<<0) // CSMA done #define CMT2310A_INT_CCA_STATUS (33<<0) // CCA status match - + #define CMT2310A_CTL_REG_18 0x12 // interrupt enable control 1 - #define CMT2310A_INT_CTL1_REG 0x12 + #define CMT2310A_INT_CTL1_REG 0x12 #define CMT2310A_SLEEP_TMO_EN (1<<7) // 0=disable, 1=enable sleep timer time-out #define CMT2310A_RX_TMO_EN (1<<6) // 0=disable, 1=enable rx timer time-out - #define CMT2310A_TX_DONE_EN (1<<5) // 0=disable, 1=enable tx done + #define CMT2310A_TX_DONE_EN (1<<5) // 0=disable, 1=enable tx done #define CMT2310A_PREAM_PASS_EN (1<<4) // 0=disable, 1=enable preamble detect #define CMT2310A_SYNC_PASS_EN (1<<3) // 0=disable, 1=enable syncword detect #define CMT2310A_ADDR_PASS_EN (1<<2) // 0=disable, 1=enable node address detect @@ -210,28 +210,28 @@ #define CMT2310A_PKT_DONE_EN (1<<0) // 0=disable, 1=enable packet received done #define CMT2310A_CTL_REG_19 0x13 // interrupt enable control 2 - #define CMT2310A_INT3_POLAR (1<<7) // int1 polar selection, 0=high acitve, 1=low acitve; + #define CMT2310A_INT3_POLAR (1<<7) // int1 polar selection, 0=high acitve, 1=low acitve; #define CMT2310A_PD_FIFO (1<<6) // 0=retain fifo in sleep, 1=not retain fifo in sleep #define CMT2310A_FIFO_TH_BIT8 (1<<5) // fifo threshold bit8 #define CMT2310A_FIFO_AUTO_CLR_RX_EN (1<<4) // 0=not clear fifo, 1=clear fifo, when trigger go to rx - #define CMT2310A_FIFO_AUTO_RES_TX_EN (1<<3) // 0=auto restore tx fifo, 1=don't auto restore tx fifo, when tx done. (if TX_PKT_NUM is not 0, should be set this bit) + #define CMT2310A_FIFO_AUTO_RES_TX_EN (1<<3) // 0=auto restore tx fifo, 1=don't auto restore tx fifo, when tx done. (if TX_PKT_NUM is not 0, should be set this bit) #define CMT2310A_FIFO_TX_TEST_EN (1<<2) // 0=tx fifo only write, 1=tx fifo can be read. suggest only for testing, normal useage should be clear this bit - #define CMT2310A_FIFO_MERGE_EN (1<<1) // 0=split fifo to tx and rx, 1=fifo merge together + #define CMT2310A_FIFO_MERGE_EN (1<<1) // 0=split fifo to tx and rx, 1=fifo merge together #define CMT2310A_FIFO_TX_RX_SEL (1<<0) // 0=fifo for tx useage, 1=fifo for rx useage, when CMT2310A_FIFO_MERGE_EN=1 #define CMT2310A_CTL_REG_20 0x14 // fifo threshold value #define CMT2310A_FIFO_TH_REG 0x14 - - #define CMT2310A_CTL_REG_21 0x15 // interrupt enable control 3 + + #define CMT2310A_CTL_REG_21 0x15 // interrupt enable control 3 #define CMT2310A_RSSI_PJD_VALID_EN (1<<6) // 0=disable, 1=enable RSSI and/or PJD valid interrupt - #define CMT2310A_OP_CMD_FAILED_EN (1<<5) // 0=disable, 1=enable API Command failed interrupt + #define CMT2310A_OP_CMD_FAILED_EN (1<<5) // 0=disable, 1=enable API Command failed interrupt #define CMT2310A_RSSI_COLL_EN (1<<4) // 0=disable, 1=enable signal collision interrupt #define CMT2310A_PKT_ERR_EN (1<<3) // 0=disable, 1=enable packet recieve error interrupt #define CMT2310A_LBD_STATUS_EN (1<<2) // 0=disable, 1=enable LBD status interrupt #define CMT2310A_LBD_STOP_EN (1<<1) // 0=disable, 1=enable LBD stop interrupt #define CMT2310A_LD_STOP_EN (1<<0) // 0=disable, 1=enable PLL lock detect interrupt - #define CMT2310A_CTL_REG_22 0x16 // function enable config 0 + #define CMT2310A_CTL_REG_22 0x16 // function enable config 0 #define CMT2310A_FREQ_HOP_MANU_EN (1<<7) // 0=disable, 1=enable manual frequencry hopping #define CMT2310A_RX_HOP_PERSIST (1<<6) // 0=finish, 1=on going, Rx auto frequencry hopping #define CMT2310A_FREQ_SW_STATE (1<<5) // 0=return to READY, 1=return to RFS, for Rx auto frequencry hopping mode, every times after RX time-out state @@ -241,7 +241,7 @@ #define CMT2310A_TRX_SWT_EN (1<<1) // 0=disable, 1=enable TX/RX antenna switch #define CMT2310A_ANT_LOCK_EN (1<<0) // 0=disable, 1=enable antenna diversity lock interrupt - #define CMT2310A_CTL_REG_23 0x17 // interrupt enable control 4 + #define CMT2310A_CTL_REG_23 0x17 // interrupt enable control 4 #define CMT2310A_API_DONE_EN (1<<7) // 0=disable, 1=enable API done interrupt #define CMT2310A_CCA_STATUS_EN (1<<6) // 0=disable, 1=enable CCA status interrupt #define CMT2310A_CSMA_DONE_EN (1<<5) // 0=disable, 1=enable CSMA done interrupt @@ -250,47 +250,47 @@ #define CMT2310A_TX_RESEND_DONE_EN (1<<2) // 0=disable, 1=enable TX re-send done interrupt #define CMT2310A_NACK_RECV_EN (1<<1) // 0=disable, 1=enable no ACK received interrupt #define CMT2310A_SEQ_MATCH_EN (1<<0) // 0=disable, 1=enable sequence number match interrupt - + #define CMT2310A_CTL_REG_24 0x18 // interrupt flag & clear control 1 #define CMT2310A_SLEEP_TMO_FLG (1<<5) // sleep timer time-out flag #define CMT2310A_RX_TMO_FLG (1<<4) // rx timer time-out flag #define CMT2310A_TX_DONE_FLG (1<<3) // tx done flag - #define CMT2310A_SLEEP_TMO_CLR (1<<2) // set '1' to clear Sleep timer time-out flag + #define CMT2310A_SLEEP_TMO_CLR (1<<2) // set '1' to clear Sleep timer time-out flag #define CMT2310A_RX_TMO_CLR (1<<1) // set '1' to clear Rx timer time-out flag #define CMT2310A_TX_DONE_CLR (1<<0) // set '1' to clear TX done flag - + #define CMT2310A_CTL_REG_25 0x19 // interrupt flag & clear control 2 #define CMT2310A_PREAM_PASS_CLR (1<<4) // set '1' to clear PREAM_PASS flag #define CMT2310A_SYNC_PASS_CLR (1<<3) // set '1' to clear SYNC_PASS flag #define CMT2310A_ADDR_PASS_CLR (1<<2) // set '1' to clear ADDR_PASS flag #define CMT2310A_CRC_PASS_CLR (1<<1) // set '1' to clear CRC_PASS flag #define CMT2310A_PKT_DONE_CLR (1<<0) // set '1' to clear PKT_DONE flag - + #define CMT2310A_CTL_REG_26 0x1A // interrupt flag & clear control 3 (-RO) #define CMT2310A_SYNC1_PASS_FLG (1<<5) // sync-word1 match interrupt flag #define CMT2310A_PREAM_PASS_FLG (1<<4) // preamlbe pass interrupt flag #define CMT2310A_SYNC_PASS_FLG (1<<3) // sync-word match interrupt flag #define CMT2310A_ADDR_PASS_FLG (1<<2) // node address match interrupt flag #define CMT2310A_CRC_PASS_FLG (1<<1) // packet crc pass interrupt flag - #define CMT2310A_PKT_DONE_FLG (1<<0) // packet done interrupt flag + #define CMT2310A_PKT_DONE_FLG (1<<0) // packet done interrupt flag #define CMT2310A_CTL_REG_27 0x1B // fifo control 1, fifo clear - #define CMT2310A_TX_FIFO_RESTORE (1<<2) // 0=disable, 1=enable + #define CMT2310A_TX_FIFO_RESTORE (1<<2) // 0=disable, 1=enable #define CMT2310A_RX_FIFO_CLR (1<<1) // set '1' to clear Rx FIFO #define CMT2310A_TX_FIFO_CLR (1<<0) // set '1' to clear Tx FIFO - + #define CMT2310A_CTL_REG_28 0x1C // fifo control 2, fifo flag (-RO) - #define CMT2310A_RX_FIFO_FULL_FLG (1<<7) // + #define CMT2310A_RX_FIFO_FULL_FLG (1<<7) // #define CMT2310A_RX_FIFO_NMTY_FLG (1<<6) // #define CMT2310A_RX_FIFO_TH_FLG (1<<5) // #define CMT2310A_RX_FIFO_OVF_FLG (1<<3) // #define CMT2310A_TX_FIFO_FULL_FLG (1<<2) // #define CMT2310A_TX_FIFO_NMTY_FLG (1<<1) // #define CMT2310A_TX_FIFO_TH_FLG (1<<0) // - - #define CMT2310A_CTL_REG_29 0x1D // auxrl function clear control + + #define CMT2310A_CTL_REG_29 0x1D // auxrl function clear control #define CMT2310A_ANT_LOCK_CLR (1<<4) // set '1' to clear antenna lock - #define CMT2310A_OP_CMD_FAILED_CLR (1<<3) // set '1' to clear command operate failed + #define CMT2310A_OP_CMD_FAILED_CLR (1<<3) // set '1' to clear command operate failed #define CMT2310A_RSSI_COLL_CLR (1<<2) // set '1' to clear rssi collision #define CMT2310A_PKT_ERR_CLR (1<<1) // set '1' to clear packet receive error #define CMT2310A_LBD_STATUS_CLR (1<<0) // set '1' to clear LBD status @@ -309,11 +309,11 @@ #define CMT2310A_TX_DC_DONE_CLR (1<<4) // set '1' to clear TX_DC_DONE #define CMT2310A_ACK_RECV_FAILED_CLR (1<<3) // set '1' to clear ACK receive failed #define CMT2310A_TX_RESEND_DONE_CLR (1<<2) // set '1' to clear Tx resend done - #define CMT2310A_NACK_RECV_CLR (1<<1) // set '1' to clear NACK receive + #define CMT2310A_NACK_RECV_CLR (1<<1) // set '1' to clear NACK receive #define CMT2310A_SEQ_MATCH_CLR (1<<0) // set '1' to clear sequence number match - #define CMT2310A_CTL_REG_32 0x20 // mac function flag (-RO) - #define CMT2310A_API_DONE_FLG (1<<7) // + #define CMT2310A_CTL_REG_32 0x20 // mac function flag (-RO) + #define CMT2310A_API_DONE_FLG (1<<7) // #define CMT2310A_CCA_STATUS_FLG (1<<6) // #define CMT2310A_CSMA_DONE_FLG (1<<5) // #define CMT2310A_TX_DC_DONE_FLG (1<<4) // @@ -321,12 +321,12 @@ #define CMT2310A_TX_RESEND_DONE_FLG (1<<2) // #define CMT2310A_NACK_RECV_FLG (1<<1) // #define CMT2310A_SEQ_MATCH_FLG (1<<0) // - + #define CMT2310A_CTL_REG_33 0x21 // RSSI value minimum (-RO) #define CMT2310A_RSSI_MIN_REG 0x21 - - #define CMT2310A_CTL_REG_34 0x22 // RSSI value (-RO) - #define CMT2310A_RSSI_REG 0x22 + + #define CMT2310A_CTL_REG_34 0x22 // RSSI value (-RO) + #define CMT2310A_RSSI_REG 0x22 #define CMT2310A_CTL_REG_35 0x23 // LBD value (-RO) #define CMT2310A_LBD_REG 0x23 @@ -336,7 +336,7 @@ #define CMT2310A_CTL_REG_37 0x25 // frequence channel current active (-RO) #define CMT2310A_FREQ_CHANL_ACT_REG 0x25 - + #define CMT2310A_CTL_REG_38 0x26 // sequence number tx out[7:0] (-RO) #define CMT2310A_CTL_REG_39 0x27 // sequence number tx out[15:8] (-RO) #define CMT2310A_SEQNUM_TX_OUT_L_REG 0x26 @@ -345,7 +345,7 @@ #define CMT2310A_CTL_REG_40 0x28 // rx preamble size[4:0] + preamble length unit + data mode[1:0] #define CMT2310A_RX_PREAM_SIZE_MASK 0xF8 // rx preamble detect length, 0=don't detect #define CMT2310A_PREAM_LENG_UNIIT (1<<2) // 0=8bits/unit, 1=4bits/unit (nibble) - + #define CMT2310A_DATA_MODE_MASK (3<<0) #define CMT2310A_DIRECT_MODE (0<<0) // Direct mode #define CMT2310A_PACKET_MODE (2<<0) // Packet mode @@ -354,7 +354,7 @@ #define CMT2310A_CTL_REG_42 0x2A // tx preamble size[15:8] #define CMT2310A_TX_PREAM_SIZE_L_REG 0x29 // when TX_PREAM_SIZE=0, means do not send preamble #define CMT2310A_TX_PREAM_SIZE_H_REG 0x2A - + #define CMT2310A_CTL_REG_43 0x2B // preamble value #define CMT2310A_PREAM_VALUE_REG 0x2B // when PREAM_LENG_UNIIT = 0, 8bits active // when PREAM_LENG_UNIIT = 1, 4bits(LSB) active @@ -364,7 +364,7 @@ #define CMT2310A_SYNC_TOL_MASK (7<<4) #define CMT2310A_SYNC_SIZE_MASK (7<<1) // n+1 for SyncWord length #define CMT2310A_SYNC_MAN_EN (1<<0) // 0=disable, 1=enable SyncWord manchester encoding - + #define CMT2310A_CTL_REG_45 0x2D // sync value 0 [7:0] send last #define CMT2310A_SYNC_VALUE_7_REG 0x2D #define CMT2310A_CTL_REG_46 0x2E // sync value 1 [15:8] @@ -376,12 +376,12 @@ #define CMT2310A_CTL_REG_49 0x31 // sync value 4 [39:32] #define CMT2310A_SYNC_VALUE_3_REG 0x31 #define CMT2310A_CTL_REG_50 0x32 // sync value 5 [47:40] - #define CMT2310A_SYNC_VALUE_2_REG 0x32 + #define CMT2310A_SYNC_VALUE_2_REG 0x32 #define CMT2310A_CTL_REG_51 0x33 // sync value 6 [55:48] #define CMT2310A_SYNC_VALUE_1_REG 0x33 #define CMT2310A_CTL_REG_52 0x34 // sync value 7 [63:56] send first - #define CMT2310A_SYNC_VALUE_0_REG 0x34 - + #define CMT2310A_SYNC_VALUE_0_REG 0x34 + #define CMT2310A_CTL_REG_53 0x35 // sync fec value 0 [7:0] #define CMT2310A_FEC_SYNC_7_REG 0x35 #define CMT2310A_CTL_REG_54 0x36 // sync fec value 1 [15:8] @@ -397,16 +397,16 @@ #define CMT2310A_CTL_REG_59 0x3B // sync fec value 6 [55:48] #define CMT2310A_FEC_SYNC_1_REG 0x3B #define CMT2310A_CTL_REG_60 0x3C // sync fec value 7 [63:56] - #define CMT2310A_FEC_SYNC_0_REG 0x3C - + #define CMT2310A_FEC_SYNC_0_REG 0x3C + #define CMT2310A_CTL_REG_61 0x3D // payload length [7:0] #define CMT2310A_CTL_REG_62 0x3E // payload length [15:8] #define CMT2310A_PAYLOAD_LENGTH_L_REG 0x3D #define CMT2310A_PAYLOAD_LENGTH_H_REG 0x3E - + #define CMT2310A_CTL_REG_63 0x3F // packet config 1, interleave_en + x + length_size + piggybacking_en + x + addr_leng_conf + payload_bit_order + pkt_type #define CMT2310A_INTERLEAVE_EN (1<<7) // 0=disable, 1=enable interleave - #define CMT2310A_LENGTH_SIZE (1<<5) // 0=1Byte, for up to 255 bytes variable length packet， + #define CMT2310A_LENGTH_SIZE (1<<5) // 0=1Byte, for up to 255 bytes variable length packet， // 1=2Bytes, for up to 65535 bytes variable length packet #define CMT2310A_PAGGYBACKING_EN (1<<4) // 0=disable, 1=enable for auto paggy backing payload for auto-ack #define CMT2310A_ADDR_FIELD_EN (1<<3) // 0=disable, 1=enable for node address field @@ -416,23 +416,23 @@ #define CMT2310A_CTL_REG_64 0x40 // packet config 2, sync_value_sel + addr_split_mode + addr_free_en + addr_err_mask + addr_size[1:0] + addr_det_mode[1:0] #define CMT2310A_SYNC_VALUE_SEL (1<<7) // 0=select SYNC_VALUE, 1=select SYNC_FEC_VALUE, only for TX used - #define CMT2310A_ADDR_SPLIT_MODE (1<<6) // 0=only DEST_ADDR filed active, 1=DEST_ADDR+SRC_ADDR filed both active + #define CMT2310A_ADDR_SPLIT_MODE (1<<6) // 0=only DEST_ADDR filed active, 1=DEST_ADDR+SRC_ADDR filed both active #define CMT2310A_ADDR_FREE_EN (1<<5) // 0=disable, 1=enable ADDR detect stand-alone #define CMT2310A_ADDR_ERR_MASK (1<<4) // 0=allow, 1=not allow for reset decoding when ADDR mis-matching #define CMT2310A_ADDR_SIZE_MASK (3<<2) // - - #define CMT2310A_ADDR_DET_MODE_MASK (3<<0) + + #define CMT2310A_ADDR_DET_MODE_MASK (3<<0) #define CMT2310A_ADDR_DET_DISABLE (0<<0) // disable node address detect #define CMT2310A_ADDR_DET_MATCH (1<<0) // rx only detect ADDR_VALUE, tx send ADDR_VALUE #define CMT2310A_ADDR_DET_BOARDCAST_0 (2<<0) // rx detect ADDR_VALUE & all-0, tx send ADDR_VALUE #define CMT2310A_ADDR_DET_BOARDCAST_ALL (3<<0) // rx detect ADDR_VALUE & all-0 & all-1, tx send ADDR_VALUE - + #define CMT2310A_CTL_REG_65 0x41 // SRC_ADDR [7:0] #define CMT2310A_CTL_REG_66 0x42 // SRC_ADDR [15:8] #define CMT2310A_SRC_ADDR_L_REG 0x41 #define CMT2310A_SRC_ADDR_H_REG 0x42 - + #define CMT2310A_CTL_REG_67 0x43 // DEST_ADDR [7:0] #define CMT2310A_CTL_REG_68 0x44 // DEST_ADDR [15:8] #define CMT2310A_DEST_ADDR_L_REG 0x43 @@ -442,27 +442,27 @@ #define CMT2310A_CTL_REG_70 0x46 // SRC_BITMASK [15:8] #define CMT2310A_SRC_BITMASK_L_REG 0x45 #define CMT2310A_SRC_BITMASK_H_REG 0x46 - + #define CMT2310A_CTL_REG_71 0x47 // DEST_BITMASK [7:0] #define CMT2310A_CTL_REG_72 0x48 // DEST_BITMASK [15:8] #define CMT2310A_DEST_BITMASK_L_REG 0x47 #define CMT2310A_DEST_BITMASK_H_REG 0x48 - - #define CMT2310A_CTL_REG_73 0x49 // crc config, crc_size[1:0] + crc_byte_swap + crc_bit_inv + crc_range + crc_refin + crc_bit_order + crc_en + + #define CMT2310A_CTL_REG_73 0x49 // crc config, crc_size[1:0] + crc_byte_swap + crc_bit_inv + crc_range + crc_refin + crc_bit_order + crc_en #define CMT2310A_CRC_CFG_REG 0x49 #define CMT2310A_CRC_SIZE_MASK (3<<6) #define CMT2310A_CRC_SLE_CRC8 (0<<6) // select crc-8 #define CMT2310A_CRC_SLE_CRC16 (1<<6) // select crc-16 #define CMT2310A_CRC_SLE_CRC24 (2<<6) // select crc-24 #define CMT2310A_CRC_SLE_CRC32 (3<<6) // select crc-32 - - #define CMT2310A_CRC_BYTE_SWAP (1<<5) // crc16 for example, 0=[15:8]+[7:0], 1=[7:0]+[15:8], - #define CMT2310A_CRC_BIT_INV (1<<4) // 0=disable, 1=enable for crc result inver + + #define CMT2310A_CRC_BYTE_SWAP (1<<5) // crc16 for example, 0=[15:8]+[7:0], 1=[7:0]+[15:8], + #define CMT2310A_CRC_BIT_INV (1<<4) // 0=disable, 1=enable for crc result inver #define CMT2310A_CRC_RANGE (1<<3) // 0=whole payload, 1=only data #define CMT2310A_CRC_REFIN (1<<2) // 0=normal bit input flow, 1=inver bit input flow, for byte as unit #define CMT2310A_CRC_BIT_ORDER (1<<1) // 0=MSB send first, 1=LSB send first #define CMT2310A_CRC_EN (1<<0) // 0=disable, 1=enable CRC function - + #define CMT2310A_CTL_REG_74 0x4A // crc seed 0 [7:0] #define CMT2310A_CTL_REG_75 0x4B // crc seed 1 [15:8] #define CMT2310A_CTL_REG_76 0x4C // crc seed 2 [23:16] @@ -485,22 +485,22 @@ #define CMT2310A_CRC_REFOUT (1<<7) // 0=MSB->LSB, 1=LSB->MSB, crc result turn over, byte as unit #define CMT2310A_WHITEN_SEED_B8 (1<<6) // whiten_seed[8] #define CMT2310A_WHITEN_SEED_TYPE (1<<5) // 0=compatible A7139 PN7 seed, 1=PN7 seed by whien_seed - + #define CMT2310A_WHITEN_TYPE_MASK (3<<3) #define CMT2310A_WHITEN_PN9_CCITT (0<<3) // whiten type select PN9 CCITT #define CMT2310A_WHITEN_PN9_IBM (1<<3) // whiten type select PN9 IBM #define CMT2310A_WHITEN_PN7 (2<<3) // whiten type select PN7 - + #define CMT2310A_WHITEN_EN (1<<2) // 0=disable, 1=enable whien encoding/decoding - + #define CMT2310A_MANCH_TYPE (1<<1) // 0= 2'b01 as logic'1', 2'b10 as logic'0' - // 1= 2'b10 as logic'1', 2'b01 as logic'0' - + // 1= 2'b10 as logic'1', 2'b01 as logic'0' + #define CMT2310A_MANCH_EN (1<<0) // 0=disable, 1=enable manchester encoding/decoding #define CMT2310A_CTL_REG_83 0x53 // whiten seed [7:0] #define CMT2310A_WHITEN_SEED_REG 0x53 - + #define CMT2310A_CTL_REG_84 0x54 // packet config 3, crc_err_clr_fifo_en + fcs2_en + seqnum_match_en + seqnum_size + seqnum_auto_inc + seqnum_en + tx_prefix_type[1:0] #define CMT2310A_CRCERR_CLR_FIFO_EN (1<<7) // 0=not clear, 1=clear Rx FIFO, when receive packet with CRC mis-matching #define CMT2310A_FCS2_EN (1<<6) // 0=disable, 1=enable FCS2 filed @@ -517,28 +517,28 @@ #define CMT2310A_CTL_REG_85 0x55 // tx packet number [7:0] - #define CMT2310A_CTL_REG_86 0x56 // tx packet number [15:8] + #define CMT2310A_CTL_REG_86 0x56 // tx packet number [15:8] #define CMT2310A_TX_PKT_NUM_L_REG 0x55 - #define CMT2310A_TX_PKT_NUM_H_REG 0x56 - + #define CMT2310A_TX_PKT_NUM_H_REG 0x56 + #define CMT2310A_CTL_REG_87 0x57 // sequence number tx inital value [7:0] #define CMT2310A_CTL_REG_88 0x58 // sequence number tx inital value [15:8] #define CMT2310A_SEQNUM_TX_IN_L_REG 0x57 - #define CMT2310A_SEQNUM_TX_IN_H_REG 0x58 - + #define CMT2310A_SEQNUM_TX_IN_H_REG 0x58 + #define CMT2310A_CTL_REG_89 0x59 // tx packet gap [7:0] #define CMT2310A_TX_PKT_GAP_REG 0x59 #define CMT2310A_CTL_REG_90 0x5A // Rssi calibrate offset #define CMT2310A_RSSI_CAL_OFFSET_REG 0x5A - + #define CMT2310A_CTL_REG_91 0x5B // tx side FCS2 filed inital value [7:0] - #define CMT2310A_FCS2_TX_IN_REG 0x5B - + #define CMT2310A_FCS2_TX_IN_REG 0x5B + #define CMT2310A_CTL_REG_92 0x5C // rx side FCC2 filed receive value [7:0] (-RO) #define CMT2310A_FCS2_RX_OUT_REG 0x5C - - #define CMT2310A_CTL_REG_93 0x5D // fec config 1, FEC_TICC + fec_padding_code[12:8] + fec_rcs_nrnsc_sel + fec_en + + #define CMT2310A_CTL_REG_93 0x5D // fec config 1, FEC_TICC + fec_padding_code[12:8] + fec_rcs_nrnsc_sel + fec_en #define CMT2310A_FEC_TICC (1<<7) // 0=invert, 1=not invert, for FEC ui #define CMT2310A_FEC_PAD_CODE_H_MASK (0x1F<<2) // fec_padding_code[12:8] #define CMT2310A_FEC_RSC_NRNSC_SEL (1<<1) // 0=RSC mode, 1=NRNSC mode @@ -546,7 +546,7 @@ #define CMT2310A_CTL_REG_94 0x5E // fec config 2, fec_padding_code[7:0] #define CMT2310A_FEC_PAD_CODE_L_REG 0x5E - + #define CMT2310A_CTL_REG_95 0x5F // 4-FSK config, 4fsk_3_level[1:0] + 4fsk_2_level[1:0] + 4fsk_1_level[1:0] + 4fsk_0_level[1:0] #define CMT2310A_MAP_4FSK_LEVEL_REG 0x5F //--------------------------------- system control config -------------------------------- @@ -556,9 +556,9 @@ #define CMT2310A_TX_EXIT_TO_SLEEP (1<<4) // tx done exit to sleep #define CMT2310A_TX_EXIT_TO_READY (2<<4) // tx done exit to ready #define CMT2310A_TX_EXIT_TO_TFS (3<<4) // tx done exit to TFS - #define CMT2310A_TX_EXIT_TO_TX (4<<4) // tx done exit to TX + #define CMT2310A_TX_EXIT_TO_TX (4<<4) // tx done exit to TX #define CMT2310A_TX_EXIT_TO_RFS (5<<4) // tx done exit to RFS - #define CMT2310A_TX_EXIT_TO_RX (6<<4) // tx done exit to RX + #define CMT2310A_TX_EXIT_TO_RX (6<<4) // tx done exit to RX // others to sleep, & only for packet mode tx done #define CMT2310A_TX_AUTO_HOP_EN (1<<3) // 0=disable, 1=enable tx auto hopping #define CMT2310A_TX_ACK_EN (1<<2) // 0=disable, 1=enable tx ack function @@ -572,9 +572,9 @@ #define CMT2310A_RX_EXIT_TO_SLEEP (1<<4) // rx done exit to sleep #define CMT2310A_RX_EXIT_TO_READY (2<<4) // rx done exit to ready #define CMT2310A_RX_EXIT_TO_TFS (3<<4) // rx done exit to TFS - #define CMT2310A_RX_EXIT_TO_TX (4<<4) // rx done exit to TX + #define CMT2310A_RX_EXIT_TO_TX (4<<4) // rx done exit to TX #define CMT2310A_RX_EXIT_TO_RFS (5<<4) // rx done exit to RFS - #define CMT2310A_RX_EXIT_TO_RX (6<<4) // rx done exit to RX + #define CMT2310A_RX_EXIT_TO_RX (6<<4) // rx done exit to RX // others to sleep, & only for packet mode rx done #define CMT2310A_RX_TIMER_EN (1<<3) // 0=disable, 1=enable rx timer #define CMT2310A_RX_ACK_EN (1<<2) // 0=disable, 1=enable rx ack function @@ -585,33 +585,33 @@ #define CMT2310A_PKT_DONE_EXIT_EN (1<<7) // 0=keep current, 1=depends on RX_EXIT_STATE #define CMT2310A_RX_HOP_SLP_MODE_MASK (7<<4) // rx hopping supper low power mode selection #define CMT2310A_SLP_MODE_MASK (15<<0) // rx supper low power mode selection - + #define CMT2310A_CTL_REG_99 0x63 // sysctrl 4, timer_m_sleep [7:0] #define CMT2310A_CTL_REG_100 0x64 // sysctrl 5, timer_m_sleep [10:8] + timer_r_sleep [4:0] #define CMT2310A_SLEEP_TIMER_M_REG 0x63 // Tsleep = M*2^(R+1)*31.25us, R from 0 to 26 - #define CMT2310A_SLEEP_TIMER_R_REG 0x64 - #define CMT2310A_SLEEP_TIMER_M_H_MASK (7<<5) - - #define CMT2310A_CTL_REG_101 0x65 // sysctrl 6, timer_m_rx_T1 [7:0] + #define CMT2310A_SLEEP_TIMER_R_REG 0x64 + #define CMT2310A_SLEEP_TIMER_M_H_MASK (7<<5) + + #define CMT2310A_CTL_REG_101 0x65 // sysctrl 6, timer_m_rx_T1 [7:0] #define CMT2310A_CTL_REG_102 0x66 // sysctrl 7, timer_m_rx_T1 [10:8] + timer_r_rx_T1 [4:0] - #define CMT2310A_RX_TIMER_T1_M_REG 0x65 // Trx_t1 = M*2^(R+1)*20us, R from 0 to 21, - #define CMT2310A_RX_TIMER_T1_R_REG 0x66 + #define CMT2310A_RX_TIMER_T1_M_REG 0x65 // Trx_t1 = M*2^(R+1)*20us, R from 0 to 21, + #define CMT2310A_RX_TIMER_T1_R_REG 0x66 #define CMT2310A_RX_TIMER_T1_M_H_MASK (7<<5) - #define CMT2310A_CTL_REG_103 0x67 // sysctrl 8, timer_m_rx_T2 [7:0] + #define CMT2310A_CTL_REG_103 0x67 // sysctrl 8, timer_m_rx_T2 [7:0] #define CMT2310A_CTL_REG_104 0x68 // sysctrl 9, timer_m_rx_T2 [10:8] + timer_r_rx_T2 [4:0] - #define CMT2310A_RX_TIMER_T2_M_REG 0x67 // Trx_t1 = M*2^(R+1)*20us, R from 0 to 21, + #define CMT2310A_RX_TIMER_T2_M_REG 0x67 // Trx_t1 = M*2^(R+1)*20us, R from 0 to 21, #define CMT2310A_RX_TIMER_T2_R_REG 0x68 #define CMT2310A_RX_TIMER_T2_M_H_MASK (7<<5) #define CMT2310A_CTL_REG_105 0x69 // sysctrl 10, tx_allow_rx + pup_done_state + timer_random_mode[1:0] + timer_sleep_en + rx_allow_tx + lfclk_sel + lfclk_out_en(lfosc/lfxo) #define CMT2310A_TIMER_RAND_MODE_MASK (3<<4) // CSMA mode, CSMA sleep timer random selection: - #define CMT2310A_TIMER_RAND_R (0<<4) // select random R - #define CMT2310A_TIMER_RAND_M (1<<4) // select random M + #define CMT2310A_TIMER_RAND_R (0<<4) // select random R + #define CMT2310A_TIMER_RAND_M (1<<4) // select random M #define CMT2310A_TIMER_RAND_M_R (2<<4) // select random both R & M #define CMT2310A_TIMER_RAND_OFF (3<<4) // select random off, used fixed value - + #define CMT2310A_SLEEP_TIMER_EN (1<<3) // 0=disable, 1=enable sleep timer #define CMT2310A_LFCLK_SEL (1<<1) // 0=internal LFOSC, 1=LFXO (32768Hz) #define CMT2310A_LFCLK_OUT_EN (1<<0) // 0=disable, 1=enable GPIO4 for LFCLK out, priority lower than DIG_CLKOUT_EN, but higher than GPIO4_SEL @@ -626,44 +626,44 @@ #define CMT2310A_CSMA_CCA_SYNC_RSSI (5<<5) // 5= detected sync word, or active >=1 of 4 times detect window, by Rssi #define CMT2310A_CSMA_CCA_SYNC_PJD (6<<5) // 6= detected sync word, or active >=1 of 4 times detect window, by PJD #define CMT2310A_CSMA_CCA_SYNC_RSSI_PJD (7<<5) // 7= detected sync word, or active >=1 of 4 times detect window, by PJD or Rssi - - #define CMT2310A_CSMA_PERSIST_EN (1<<4) // 0=auto exit when reach max & channel still busy, 1=keep on work until send out - + + #define CMT2310A_CSMA_PERSIST_EN (1<<4) // 0=auto exit when reach max & channel still busy, 1=keep on work until send out + #define CMT2310A_CCA_INT_SEL_MASK (3<<2) #define CMT2310A_CCA_INT_BY_PJD (0<<2) // CSMA_CCA interrupt condition by PJD #define CMT2310A_CCA_INT_BY_RSSI (1<<2) // CSMA_CCA interrupt condition by RSSI #define CMT2310A_CCA_INT_BY_PJD_RSSI (2<<2) // CSMA_CCA interrupt condition by PJD & RSSI - + #define CMT2310A_CCA_WIN_SEL_MASK (3<<0) #define CMT2310A_CCA_WIN_32_SYMBOL (0<<0) // CSMA detect window select 32symbols #define CMT2310A_CCA_WIN_64_SYMBOL (1<<0) // CSMA detect window select 64symbols #define CMT2310A_CCA_WIN_128_SYMBOL (2<<0) // CSMA detect window select 128symbols #define CMT2310A_CCA_WIN_256_SYMBOL (3<<0) // CSMA detect window select 256symbols - - + + #define CMT2310A_CTL_REG_107 0x6B // sysctrl 12, timer_m_rx_csma [7:0] #define CMT2310A_CTL_REG_108 0x6C // sysctrl 13, timer_m_rx_csma [10:8] + timer_r_rx_csma [4:0] - #define CMT2310A_RX_TIMER_CSMA_M_REG 0x6B // Trx_csma = M*2^(R+1)*20us, R from 0 to 21, + #define CMT2310A_RX_TIMER_CSMA_M_REG 0x6B // Trx_csma = M*2^(R+1)*20us, R from 0 to 21, #define CMT2310A_RX_TIMER_CSMA_R_REG 0x6C - #define CMT2310A_RX_TIMER_CSMA_M_H_MASK (15<<4) - + #define CMT2310A_RX_TIMER_CSMA_M_H_MASK (15<<4) + #define CMT2310A_CTL_REG_109 0x6D // low battery detect threshold, lbd_th[7:0] #define CMT2310A_LBD_TH_REG 0x6D #define CMT2310A_CTL_REG_110 0x6E // sysctrl 14, tx_dc_timer [7:0] - #define CMT2310A_TX_DC_TIMES_REG 0x6E + #define CMT2310A_TX_DC_TIMES_REG 0x6E - #define CMT2310A_CTL_REG_111 0x6F // + #define CMT2310A_CTL_REG_111 0x6F // #define CMT2310A_LENGTH_MODE (1<<7) // 0=normal, length filed as payload length, 1=as Wi-SUN mode #define CMT2310A_WISUN_ALLIN (1<<6) #define CMT2310A_WHITEN_WISUN (1<<5) #define CMT2310A_WISUN_MS (1<<4) #define CMT2310A_WISUN_FCS (1<<1) #define CMT2310A_WISUN_DW (1<<0) - - #define CMT2310A_CTL_REG_112 0x70 // sysctrl 15, tx_dc_done_timer [7:0] (-RO) + + #define CMT2310A_CTL_REG_112 0x70 // sysctrl 15, tx_dc_done_timer [7:0] (-RO) #define CMT2310A_TX_DC_DONE_TIMES_REG 0x70 - + #define CMT2310A_CTL_REG_113 0x71 // sysctrl 16, tx_resend_timer [7:0] #define CMT2310A_TX_RS_TIMES_REG 0x71 @@ -672,11 +672,11 @@ #define CMT2310A_CTL_REG_115 0x73 // sysctrl 18, csma_timer [7:0] #define CMT2310A_CSMA_TIMES_REG 0x73 - + #define CMT2310A_CTL_REG_116 0x74 // sysctrl 19, csma_done_timer [7:0] (-RO) #define CMT2310A_CSMA_DONE_TIMES_REG 0x74 - #define CMT2310A_CTL_REG_117 0x75 + #define CMT2310A_CTL_REG_117 0x75 #define CMT2310A_CTL_REG_118 0x76 // sysctrl 20, timer_m_sleep_csma [7:0] #define CMT2310A_CTL_REG_119 0x77 // sysctrl 21, timer_m_sleep_csma [10:8] + timer_r_sleep_csma [4:0] @@ -685,8 +685,8 @@ #define CMT2310A_FIFO_RW_PORT_REG 0x7A // FIFO R/W interface #define CMT2310A_FIFO_RW_PORT 0x7A - - #define CMT2310A_CRW_PORT_REG 0x7B + + #define CMT2310A_CRW_PORT_REG 0x7B #define CMT2310A_CRW_PORT 0x7B #define CMT2310A_CLT_REG_126 0x7E @@ -797,22 +797,22 @@ #define CMT2310A_RX_OOK_REG_00 0x5E // export by RFPDK #define CMT2310A_RX_OOK_REG_01 0x5F // export by RFPDK #define CMT2310A_RX_OOK_REG_02 0x60 // export by RFPDK - #define CMT2310A_RX_OOK_REG_03 0x61 // export by RFPDK - + #define CMT2310A_RX_OOK_REG_03 0x61 // export by RFPDK + #define CMT2310A_RX_RSSI_REG_00 0x62 // rf_rssi_reg 0, coll_handle[1:0] + coll_step_sel[1:0] + rssi_update_sel[1:0] + nc + coll_det_en - #define CMT2310A_COLL_STEP_SEL_MASK (3<<4) + #define CMT2310A_COLL_STEP_SEL_MASK (3<<4) #define CMT2310A_COLL_STEP_SEL_6dB (0<<4) // collision select 6dB #define CMT2310A_COLL_STEP_SEL_10dB (1<<4) // collision select 10dB #define CMT2310A_COLL_STEP_SEL_16dB (2<<4) // collision select 16dB #define CMT2310A_COLL_STEP_SEL_20dB (3<<4) // collision select 20dB - + #define CMT2310A_RSSI_UPDATE_SEL_MASK (3<<2) #define CMT2310A_RSSI_UPDATE_ALWAYS (0<<2) // rssi update always on - #define CMT2310A_RSSI_UPDATE_PREAM_OK (1<<2) // rssi update by preamble detected + #define CMT2310A_RSSI_UPDATE_PREAM_OK (1<<2) // rssi update by preamble detected #define CMT2310A_RSSI_UPDATE_SYNC_OK (2<<2) // rssi update by syncword detected #define CMT2310A_RSSI_UPDATE_PKT_DONE (3<<2) // rssi update by packet done - + #define CMT2310A_COLL_DET_EN (1<<0) // 0=disable, 1=enable collision detect #define CMT2310A_RX_RSSI_REG_01 0x63 // rf_rssi_reg 1, rssi_absolute_th[7:0] @@ -822,16 +822,16 @@ #define CMT2310A_DOUT_ADJUST_SEL_MASK (7<<2) #define CMT2310A_DOUT_ADJUST_3_33 (0<<2) #define CMT2310A_DOUT_ADJUST_6_66 (1<<2) - #define CMT2310A_DOUT_ADJUST_9_99 (2<<2) + #define CMT2310A_DOUT_ADJUST_9_99 (2<<2) #define CMT2310A_DOUT_ADJUST_13_32 (3<<2) #define CMT2310A_DOUT_ADJUST_16_65 (4<<2) #define CMT2310A_DOUT_ADJUST_19_98 (5<<2) #define CMT2310A_DOUT_ADJUST_23_21 (6<<2) #define CMT2310A_DOUT_ADJUST_26_64 (7<<2) - + #define CMT2310A_DOUT_ADJUST_MODE (1<<1) // 0=+1 duty, 1=-1 duty #define CMT2310A_DOUT_ADJUST_EN (1<<0) // 0=disable, 1=enable dout adjust - + #define CMT2310A_RX_ANTD_REG_00 0x67 // rf_ant_reg nc + nc + nc + nc + ant_wait_pmb[1:0] + ant_sw_dis + ant_div_en #define CMT2310A_ANT_WAIT_PMB_MASK (3<<2) @@ -839,7 +839,7 @@ #define CMT2310A_ANT_WAIT_2_UNIT (1<<2) // wait preamble size *2, when antenna calibrate #define CMT2310A_ANT_WAIT_2_5_UNIT (2<<2) // wait preamble size *2.5, when antenna calibrate #define CMT2310A_ANT_WAIT_3_UNIT (3<<2) // wait preamble size *3, when antenna calibrate - + #define CMT2310A_ANT_SW_DIS (1<<1) // 0=enable, 1=bypass antenna switch #define CMT2310A_ANT_DIV_EN (1<<0) // 0=disable, 1=enable antenna diversity @@ -909,12 +909,12 @@ #define CMT2310A_FREQ_CHANL_61 0x3D #define CMT2310A_FREQ_CHANL_62 0x3E #define CMT2310A_FREQ_CHANL_63 0x3F - + #define CMT2310A_CHIP_VERSION_00 0x40 #define CMT2310A_CHIP_VERSION_01 0x41 #define CMT2310A_CHIP_VERSION_02 0x42 -// -------------------------------- Marco defines ----------------------------------------- +// -------------------------------- Marco defines ----------------------------------------- #define VAL_BIT0 0x01 #define VAL_BIT1 0x02 #define VAL_BIT2 0x04 @@ -923,7 +923,7 @@ #define VAL_BIT5 0x20 #define VAL_BIT6 0x40 #define VAL_BIT7 0x80 - + #define BIT0 0 #define BIT1 1 #define BIT2 2 @@ -931,7 +931,7 @@ #define BIT4 4 #define BIT5 5 #define BIT6 6 - #define BIT7 7 + #define BIT7 7 //## CMT2310A_CTL_REG_00 registers #define M_BOOT_MAIN VAL_BIT1 @@ -945,7 +945,7 @@ #define M_GO_READY VAL_BIT1 #define M_GO_SLEEP VAL_BIT0 - //## CMT2310A_CTL_REG_02 registers + //## CMT2310A_CTL_REG_02 registers #define M_MCU_GPIO_EN VAL_BIT2 #define M_ANT_DIV_MANU VAL_BIT1 #define M_ANT_SELECT VAL_BIT0 @@ -954,18 +954,18 @@ #define M_TX_DIN_EN VAL_BIT6 #define M_GPIO1_SEL (VAL_BIT5|VAL_BIT4|VAL_BIT3) #define M_GPIO0_SEL (VAL_BIT2|VAL_BIT1|VAL_BIT0) - + //## CMT2310A_CTL_REG_05 registers #define M_TX_DIN_SEL (VAL_BIT7|VAL_BIT6) #define M_GPIO3_SEL (VAL_BIT5|VAL_BIT4|VAL_BIT3) #define M_GPIO2_SEL (VAL_BIT2|VAL_BIT1|VAL_BIT0) - + //## CMT2310A_CTL_REG_06 registers #define M_DIG_CLKOUT_EN VAL_BIT6 #define M_GPIO5_SEL (VAL_BIT5|VAL_BIT4|VAL_BIT3) #define M_GPIO4_SEL (VAL_BIT2|VAL_BIT1|VAL_BIT0) - - //## CMT2310A_CTL_REG_07 registers + + //## CMT2310A_CTL_REG_07 registers #define M_LFXO_PAD_EN VAL_BIT5 #define M_API_STOP VAL_BIT4 #define M_SPI_3W_EN VAL_BIT3 @@ -974,7 +974,7 @@ //## CMT2310A_CTL_REG_09 registers #define M_API_CMD_FLAG VAL_BIT7 #define M_API_RESP (VAL_BIT6|VAL_BIT5|VAL_BIT4|VAL_BIT3|VAL_BIT2|VAL_BIT1|VAL_BIT0) - + //## CMT2310A_CTL_REG_10 registers #define M_STATE_IS_TX VAL_BIT5 #define M_STATE_IS_RX VAL_BIT4 @@ -982,7 +982,7 @@ #define M_STATE_IS_RFS VAL_BIT2 #define M_STATE_IS_READY VAL_BIT1 #define M_STATE_IS_SLEEP VAL_BIT0 - + //## CMT2310A_CTL_REG_14 registers #define M_RX_FIFO_FULL_RX_EN VAL_BIT7 #define M_RX_FIFO_NMTY_RX_EN VAL_BIT6 @@ -1002,7 +1002,7 @@ #define M_INT1_POLAR VAL_BIT7 #define M_INT2_POLAR VAL_BIT6 #define M_INT2_SEL (VAL_BIT5|VAL_BIT4|VAL_BIT3|VAL_BIT2|VAL_BIT1|VAL_BIT0) - + //## CMT2310A_CTL_REG_18 registers #define M_SLEEP_TMO_EN VAL_BIT7 #define M_RX_TMO_EN VAL_BIT6 @@ -1012,7 +1012,7 @@ #define M_ADDR_PASS_EN VAL_BIT2 #define M_CRC_PASS_EN VAL_BIT1 #define M_PKT_DONE_EN VAL_BIT0 - + //## CMT2310A_CTL_REG_19 registers #define M_PD_FIFO VAL_BIT6 #define M_FIFO_TH_8 VAL_BIT5 @@ -1021,7 +1021,7 @@ #define M_FIFO_TX_TEST_EN VAL_BIT2 #define M_FIFO_MERGE_EN VAL_BIT1 #define M_FIFO_TX_RX_SEL VAL_BIT0 - + //## CMT2310A_CTL_REG_21 registers #define M_RSSI_PJD_VALID_EN VAL_BIT6 #define M_OP_CMD_FAILED_EN VAL_BIT5 @@ -1030,8 +1030,8 @@ #define M_LBD_STATUS_EN VAL_BIT2 #define M_LBD_STOP_EN VAL_BIT1 #define M_LD_STOP_EN VAL_BIT0 - - //## CMT2310A_CTL_REG_22 registers + + //## CMT2310A_CTL_REG_22 registers #define M_FREQ_HOP_MANU_EN VAL_BIT7 #define M_RX_HOP_PERSIST VAL_BIT5 #define M_FREQ_SW_STATE VAL_BIT6 @@ -1040,7 +1040,7 @@ #define M_TRX_SWT_INV VAL_BIT2 #define M_TRX_SWT_EN VAL_BIT1 #define M_ANT_LOCK_EN VAL_BIT0 - + //## CMT2310A_CTL_REG_23 registers #define M_API_DONE_EN VAL_BIT7 #define M_CCA_STATUS_EN VAL_BIT6 @@ -1050,22 +1050,22 @@ #define M_TX_RESEND_DONE_EN VAL_BIT2 #define M_NACK_RECV_EN VAL_BIT1 #define M_SEQ_MATCH_EN VAL_BIT0 - - //## CMT2310A_CTL_REG_24 registers + + //## CMT2310A_CTL_REG_24 registers #define M_SLEEP_TMO_FLG VAL_BIT5 #define M_RX_TMO_FLG VAL_BIT4 #define M_TX_DONE_FLG VAL_BIT3 #define M_TX_DONE_CLR VAL_BIT2 #define M_RX_TMO_CLR VAL_BIT1 - #define M_SLEEP_TMO_CLR VAL_BIT0 - + #define M_SLEEP_TMO_CLR VAL_BIT0 + //## CMT2310A_CTL_REG_25 registers #define M_PREAM_PASS_CLR VAL_BIT4 #define M_SYNC_PASS_CLR VAL_BIT3 #define M_ADDR_PASS_CLR VAL_BIT2 #define M_CRC_PASS_CLR VAL_BIT1 #define M_PKT_DONE_CLR VAL_BIT0 - + //## CMT2310A_CTL_REG_26 registers #define M_SYNC1_PASS_FLG VAL_BIT5 #define M_PREAM_PASS_FLG VAL_BIT4 @@ -1073,12 +1073,12 @@ #define M_ADDR_PASS_FLG VAL_BIT2 #define M_CRC_PASS_FLG VAL_BIT1 #define M_PKT_DONE_FLG VAL_BIT0 - + //## CMT2310A_CTL_REG_27 registers #define M_TX_FIFO_RESTORE VAL_BIT2 #define M_RX_FIFO_CLR VAL_BIT1 #define M_TX_FIFO_CLR VAL_BIT0 - + //## CMT2310A_CTL_REG_28 registers #define M_RX_FIFO_FULL_FLG VAL_BIT7 #define M_RX_FIFO_NMTY_FLG VAL_BIT6 @@ -1087,14 +1087,14 @@ #define M_TX_FIFO_FULL_FLG VAL_BIT2 #define M_TX_FIFO_NMTY_FLG VAL_BIT1 #define M_TX_FIFO_TH_FLG VAL_BIT0 - - //## CMT2310A_CTL_REG_29 registers + + //## CMT2310A_CTL_REG_29 registers #define M_ANT_LOCK_CLR VAL_BIT4 #define M_OP_CMD_FAILED_CLR VAL_BIT3 #define M_RSSI_COLL_CLR VAL_BIT2 #define M_PKT_ERR_CLR VAL_BIT1 #define M_LBD_STATUS_CLR VAL_BIT0 - + //## CMT2310A_CTL_REG_30 registers #define M_ANT_LOCK_FLG VAL_BIT4 #define M_OP_CMD_FAILED_FLG VAL_BIT3 @@ -1102,7 +1102,7 @@ #define M_PKT_ERR_FLG VAL_BIT1 #define M_LBD_STATUS_FLG VAL_BIT0 - + //## CMT2310A_CTL_REG_31 registers #define M_API_DONE_CLR VAL_BIT7 #define M_CCA_STATUS_CLR VAL_BIT6 @@ -1112,7 +1112,7 @@ #define M_TX_RESEND_DONE_CLR VAL_BIT2 #define M_NACK_RECV_CLR VAL_BIT1 #define M_SEQ_MATCH_CLR VAL_BIT0 - + //## CMT2310A_CTL_REG_32 registers #define M_API_DONE_FLG VAL_BIT7 #define M_CCA_STATUS_FLG VAL_BIT6 @@ -1123,70 +1123,70 @@ #define M_NACK_RECV_FLG VAL_BIT1 #define M_SEQ_MATCH_FLG VAL_BIT0 - //## CMT2310A_CTL_REG_126 registers + //## CMT2310A_CTL_REG_126 registers #define M_HV_PAGE_SEL (VAL_BIT7|VAL_BIT6) - //## CMT2310A STATE - #define STATE_IS_IDLE 0x00 - #define STATE_IS_SLEEP 0x81 + //## CMT2310A STATE + #define STATE_IS_IDLE 0x00 + #define STATE_IS_SLEEP 0x81 #define STATE_IS_READY 0x82 #define STATE_IS_RFS 0x84 #define STATE_IS_TFS 0x88 #define STATE_IS_RX 0x90 #define STATE_IS_TX 0xA0 - - //## GPIO0_SEL + + //## GPIO0_SEL #define GPIO0_SEL_DOUT 0x00 - #define GPIO0_SEL_INT1 0x01 - #define GPIO0_SEL_INT2 0x02 - #define GPIO0_SEL_DCLK 0x03 - - //## GPIO1_SEL + #define GPIO0_SEL_INT1 0x01 + #define GPIO0_SEL_INT2 0x02 + #define GPIO0_SEL_DCLK 0x03 + + //## GPIO1_SEL #define GPIO1_SEL_DCLK 0x00 - #define GPIO1_SEL_INT1 0x01 - #define GPIO1_SEL_INT2 0x02 - #define GPIO1_SEL_DOUT 0x03 - - //## GPIO2_SEL + #define GPIO1_SEL_INT1 0x01 + #define GPIO1_SEL_INT2 0x02 + #define GPIO1_SEL_DOUT 0x03 + + //## GPIO2_SEL #define GPIO2_SEL_INT1 0x00 - #define GPIO2_SEL_INT2 0x01 - #define GPIO2_SEL_DCLK 0x02 - #define GPIO2_SEL_DOUT 0x03 - - //## GPIO3_SEL + #define GPIO2_SEL_INT2 0x01 + #define GPIO2_SEL_DCLK 0x02 + #define GPIO2_SEL_DOUT 0x03 + + //## GPIO3_SEL #define GPIO3_SEL_INT2 0x00 - #define GPIO3_SEL_INT1 0x01 - #define GPIO3_SEL_DCLK 0x02 - #define GPIO3_SEL_DOUT 0x03 - #define GPIO3_SEL_DIN 0x05 - - //## GPIO4_SEL + #define GPIO3_SEL_INT1 0x01 + #define GPIO3_SEL_DCLK 0x02 + #define GPIO3_SEL_DOUT 0x03 + #define GPIO3_SEL_DIN 0x05 + + //## GPIO4_SEL #define GPIO4_SEL_DOUT 0x00 - #define GPIO4_SEL_INT1 0x01 - #define GPIO4_SEL_INT2 0x02 - #define GPIO4_SEL_DCLK 0x03 - #define GPIO4_SEL_DIN 0x05 - - //## GPIO5_SEL + #define GPIO4_SEL_INT1 0x01 + #define GPIO4_SEL_INT2 0x02 + #define GPIO4_SEL_DCLK 0x03 + #define GPIO4_SEL_DIN 0x05 + + //## GPIO5_SEL #define GPIO5_SEL_RSTN 0x00 - #define GPIO5_SEL_INT1 0x01 - #define GPIO5_SEL_INT2 0x02 - #define GPIO5_SEL_DOUT 0x03 - #define GPIO5_SEL_DCLK 0x04 - - //## TX_DIN_SEL + #define GPIO5_SEL_INT1 0x01 + #define GPIO5_SEL_INT2 0x02 + #define GPIO5_SEL_DOUT 0x03 + #define GPIO5_SEL_DCLK 0x04 + + //## TX_DIN_SEL #define TX_DIN_SEL_GPIO3 0x00 - #define TX_DIN_SEL_GPIO4 0x01 + #define TX_DIN_SEL_GPIO4 0x01 #define TX_DIN_SEL_NIRQ 0x02 - + //## NIRQ_SEL #define NIRQ_SEL_INT1 0x00 - #define NIRQ_SEL_INT2 0x01 - #define NIRQ_SEL_DCLK 0x02 - #define NIRQ_SEL_DOUT 0x03 + #define NIRQ_SEL_INT2 0x01 + #define NIRQ_SEL_DCLK 0x02 + #define NIRQ_SEL_DOUT 0x03 #define NIRQ_SEL_DIN 0x04 - - //## INT1/2_SEL + + //## INT1/2_SEL #define INT_SRC_MIX 0x00 #define INT_SRC_ANT_LOCK 0x01 #define INT_SRC_RSSI_PJD_VALID 0x02 diff --git a/NSPE/WIFI_IOT/bsp/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/ebyte_e48x.c b/NSPE/WIFI_IOT/bsp/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/ebyte_e48x.c index e5dc08c..2384b57 100755 --- a/NSPE/WIFI_IOT/bsp/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/ebyte_e48x.c +++ b/NSPE/WIFI_IOT/bsp/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/ebyte_e48x.c @@ -25,11 +25,32 @@ uint8_t rf_rxbuffer[200]; uint8_t rf_rxsize; uint8_t radio_rece_data_flag; +extern uint32_t g_chip_id; void Ebyte_E48x_Init( void ) { - vRadioCheckLink(); - vRadioInit(); + /* Step1 */ + vRadioPowerUp(); // Release RST(GPIO5) + vRadioSetAntSwitch(FALSE, FALSE); // Disable GPIO0 & GPIO1 as antenna switch control + vRadioSpiModeSel(FALSE); // SPI 4-Wire mode + + /* Step2 */ + g_chip_id = lRadioChipVersion(); + if(0x00231000 != (g_chip_id & 0x00FFFF00)) { + DEBUGPRINT("[%s|%u] Error, dismatch Chip-ID[%#x](!=0x231000).\r\n", __FUNCTION__, __LINE__, g_chip_id); + return; + } + DEBUGPRINT("[%s|%u] Info, Link Device:E48-XXXM20S.\r\n", __FUNCTION__, __LINE__); + + /* Step3 */ + if (bRadioGetState() == CMT2310A_STATE_IS_READY) { + DEBUGPRINT("[%s|%u] Infor, CMT2310 already in State[READY], so skip initialization.\r\n", __FUNCTION__, __LINE__); + return; + } + DEBUGPRINT("[%s|%u] Info, goto initialize E48-XXXM20S.\r\n", __FUNCTION__, __LINE__); + + /* Step4 */ + vRadioInit(); } void Ebyte_E48x_SendPayload( uint8_t *payload, uint8_t size, uint32_t timeout ) diff --git a/NSPE/WIFI_IOT/bsp/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/radio.c b/NSPE/WIFI_IOT/bsp/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/radio.c index 0ee587c..d0c11a3 100755 --- a/NSPE/WIFI_IOT/bsp/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/radio.c +++ b/NSPE/WIFI_IOT/bsp/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/radio.c @@ -71,191 +71,201 @@ const uint8_t cmt2310a_power[55][7] = { ********************************/ void vRadioInit( void ) { - byte fw_rev; - vRadioSoftReset(); - vRadioConfigPageReg( 0, g_cmt2310a_page0, CMT2310A_PAGE0_SIZE ); //config page 0 - vRadioConfigPageReg( 1, g_cmt2310a_page1, CMT2310A_PAGE1_SIZE ); //config page 1 - vRadioSetNirq( CMT2310A_nIRQ_TCXO ); //for TCXO need cofig as nIRQ pin at first - vRadioTcxoDrvSel( 0 ); //drive power + byte fw_rev; - fw_rev = (byte)g_chip_id; //dealwith Xtal - switch(fw_rev) - { - case 0xC0: - vRadioXoWaitCfg(RADIO_CGU_DIV4); - break; - default: - break; - } + /* Step4 */ + vRadioHardReset(); - vRadioPowerUpBoot(); - delay1ms( 10 ); - bRadioGoStandby(); - delay1ms( 2 ); - bRadioApiCommand( 0x02 ); // - delay1ms( 10 ); - bRadioApiCommand( 0x01 ); //IR Calibration, need some times - vRadioCapLoad( 2 ); //Xo Cap - //GPIOn default setting - vRadioSetGpio0( CMT2310A_GPIO0_INT3 ); - vRadioSetGpio1( CMT2310A_GPIO1_INT2 ); - vRadioSetGpio2( CMT2310A_GPIO2_DCLK ); - vRadioSetGpio3( CMT2310A_GPIO3_DOUT ); - vRadioSetGpio4( CMT2310A_GPIO4_INT1 ); - vRadioSetGpio5( CMT2310A_GPIO5_nRST ); - //INT1 = RX_FIFO_WBYTE, INT2 = PKT_DONE - vRadioSetInt1Sel( INT_SRC_RX_FIFO_WBYTE ); - vRadioSetInt2Sel( INT_SRC_PKT_DONE ); - vRadioSetInt1Polar( FALSE ); - vRadioSetInt2Polar( FALSE ); - vRadioSetInt3Polar( FALSE ); - //interrupt source enable config - g_radio.int_src_en._BITS.PKT_DONE_EN = 1; - g_radio.int_src_en._BITS.CRC_PASS_EN = 1; - g_radio.int_src_en._BITS.ADDR_PASS_EN = 0; - g_radio.int_src_en._BITS.SYNC_PASS_EN = 1; - g_radio.int_src_en._BITS.PREAM_PASS_EN = 1; - g_radio.int_src_en._BITS.TX_DONE_EN = 1; - g_radio.int_src_en._BITS.RX_TOUT_EN = 1; - g_radio.int_src_en._BITS.LD_STOP_EN = 0; - g_radio.int_src_en._BITS.LBD_STOP_EN = 0; - g_radio.int_src_en._BITS.LBD_STAT_EN = 0; - g_radio.int_src_en._BITS.PKT_ERR_EN = 0; - g_radio.int_src_en._BITS.RSSI_COLL_EN = 0; - g_radio.int_src_en._BITS.OP_CMD_FAILED_EN = 0; - g_radio.int_src_en._BITS.RSSI_PJD_EN = 0; - g_radio.int_src_en._BITS.SEQ_MATCH_EN = 0; - g_radio.int_src_en._BITS.NACK_RECV_EN = 0; - g_radio.int_src_en._BITS.TX_RESEND_DONE_EN = 0; - g_radio.int_src_en._BITS.ACK_RECV_FAILED_EN = 0; - g_radio.int_src_en._BITS.TX_DC_DONE_EN = 0; - g_radio.int_src_en._BITS.CSMA_DONE_EN = 0; - g_radio.int_src_en._BITS.CCA_STAT_EN = 0; - g_radio.int_src_en._BITS.API_DONE_EN = 0; - g_radio.int_src_en._BITS.TX_FIFO_TH_EN = 1; - g_radio.int_src_en._BITS.TX_FIFO_NMTY_EN = 1; - g_radio.int_src_en._BITS.TX_FIFO_FULL_EN = 1; - g_radio.int_src_en._BITS.RX_FIFO_OVF_EN = 1; - g_radio.int_src_en._BITS.RX_FIFO_TH_EN = 1; - g_radio.int_src_en._BITS.RX_FIFO_NMTY_EN = 1; - g_radio.int_src_en._BITS.RX_FIFO_FULL_EN = 1; - vRadioInterruptSoucreCfg( &g_radio.int_src_en ); - //packet preamble config - g_radio.preamble_cfg.PREAM_LENG_UNIT = 0; //8-bits mode - g_radio.preamble_cfg.PREAM_VALUE = 0xAA; // - g_radio.preamble_cfg.RX_PREAM_SIZE = 2; // - g_radio.preamble_cfg.TX_PREAM_SIZE = 16; - vRadioCfgPreamble( &g_radio.preamble_cfg ); - //packet syncword config - g_radio.sync_cfg.SYN_CFG_u._BITS.SYNC_MAN_EN = 0; //disable syncword manchester coding - g_radio.sync_cfg.SYN_CFG_u._BITS.SYNC_SIZE = 2; //enable 3 bytes for syncword - g_radio.sync_cfg.SYN_CFG_u._BITS.SYNC_TOL = 0; - g_radio.sync_cfg.SYN_CFG_u._BITS.SYNC_MODE_SEL = 0; //normal packet - g_radio.sync_cfg.SYNC_VALUE[0] = 0xAA; - g_radio.sync_cfg.SYNC_VALUE[1] = 0x2D; - g_radio.sync_cfg.SYNC_VALUE[2] = 0xD4; - g_radio.sync_cfg.SYNC_VALUE_SEL = 0; //select SYN_VAL - vRadioCfgSyncWord( &g_radio.sync_cfg ); - //packet node address config - g_radio.addr_cfg.ADDR_CFG_u._BITS.ADDR_DET_MODE = 0; //disable Node Address - vRadioCfgNodeAddr( &g_radio.addr_cfg ); - //packet crc config - g_radio.crc_cfg.CRC_CFG_u._BITS.CRC_EN = 1; //enable crc - g_radio.crc_cfg.CRC_CFG_u._BITS.CRC_BIT_ORDER = 0; - g_radio.crc_cfg.CRC_CFG_u._BITS.CRC_REFIN = 0; - g_radio.crc_cfg.CRC_CFG_u._BITS.CRC_RANGE = 0; - g_radio.crc_cfg.CRC_CFG_u._BITS.CRC_BIT_INV = 0; - g_radio.crc_cfg.CRC_CFG_u._BITS.CRC_BYTE_SWAP = 0; - g_radio.crc_cfg.CRC_CFG_u._BITS.CRC_REFOUT = 0; //whole payload - g_radio.crc_cfg.CRC_CFG_u._BITS.CRCERR_CLR_FIFO_EN = 0; //note: need ative FIFO_AUTO_CLR_RX_EN = 1 or call vRadioFifoAutoClearGoRx(1) - g_radio.crc_cfg.CRC_CFG_u._BITS.CRC_SIZE = 1; //crc-16 mode - g_radio.crc_cfg.CRC_POLY_u.u32_POLY = 0x10210000; - g_radio.crc_cfg.CRC_SEED_u.u32_SEED = 0x00000000; - vRadioCfgCrc( &g_radio.crc_cfg ); - //packet coding format - g_radio.coding_format_cfg.CODING_FORMAT_CFG_u._BITS.MANCH_EN = 0; - g_radio.coding_format_cfg.CODING_FORMAT_CFG_u._BITS.MANCH_TYPE = 0; - g_radio.coding_format_cfg.CODING_FORMAT_CFG_u._BITS.WHITEN_EN = 0; - g_radio.coding_format_cfg.CODING_FORMAT_CFG_u._BITS.WHITEN_TYPE = 0; - g_radio.coding_format_cfg.CODING_FORMAT_CFG_u._BITS.WHITEN_SEED_TYP = 0; - g_radio.coding_format_cfg.CODING_FORMAT_CFG_u._BITS.FEC_EN = 0; - g_radio.coding_format_cfg.CODING_FORMAT_CFG_u._BITS.FEC_RSC_NRNSC_SEL = 0; - g_radio.coding_format_cfg.CODING_FORMAT_CFG_u._BITS.FEC_TICC = 0; - g_radio.coding_format_cfg.WHITEN_SEED = 0x01FF; - g_radio.coding_format_cfg.FEC_PAD_CODE = 0; - vRadioCfgCodeFormat( &g_radio.coding_format_cfg ); - //packet frame format - g_radio.frame_cfg.DATA_MODE = 2; //0=direct mode, 2=packet mode - g_radio.frame_cfg.FRAME_CFG1_u._BITS.PKT_TYPE = 1; //0=fixd-length packet mode 1=可变长 - g_radio.frame_cfg.FRAME_CFG1_u._BITS.PAYLOAD_BIT_ORDER = 0; //msb first - g_radio.frame_cfg.FRAME_CFG1_u._BITS.ADDR_LEN_CONF = 0; - g_radio.frame_cfg.FRAME_CFG1_u._BITS.PAGGYBACKING_EN = 0; - g_radio.frame_cfg.FRAME_CFG1_u._BITS.LENGTH_SIZE = 0; - g_radio.frame_cfg.FRAME_CFG1_u._BITS.INTERLEAVE_EN = 0; //note: when FEC enable, INTERLEAVE_EN should be set 1 - g_radio.frame_cfg.FRAME_CFG2_u._BITS.TX_PREFIX_TYPE = TX_PREFIX_SEL_PREAMBLE; //transmit preamble - g_radio.frame_cfg.FRAME_CFG2_u._BITS.SEQNUM_EN = 0; - g_radio.frame_cfg.FRAME_CFG2_u._BITS.SEQNUM_AUTO_INC = 0; - g_radio.frame_cfg.FRAME_CFG2_u._BITS.SEQNUM_SIZE = 0; - g_radio.frame_cfg.FRAME_CFG2_u._BITS.SEQNUM_MACH_EN = 0; - g_radio.frame_cfg.FRAME_CFG2_u._BITS.FCS2_EN = 0; - g_radio.frame_cfg.TX_PKT_NUM = 0; - g_radio.frame_cfg.TX_PKT_GAP = 0; - g_radio.frame_cfg.FCS2_TX_IN = 0; - g_radio.frame_cfg.PAYLOAD_LENGTH = UHF_LEN; - vRadioCfgFrameFormat( &g_radio.frame_cfg ); - //Run Mode Config - g_radio.word_mode_cfg.WORK_MODE_CFG1_u._BITS.TX_DC_EN = 0; - g_radio.word_mode_cfg.WORK_MODE_CFG1_u._BITS.TX_ACK_EN = 0; - g_radio.word_mode_cfg.WORK_MODE_CFG1_u._BITS.TX_DC_PERSIST_EN = 0; - g_radio.word_mode_cfg.WORK_MODE_CFG1_u._BITS.TX_AUTO_HOP_EN = 0; - g_radio.word_mode_cfg.WORK_MODE_CFG1_u._BITS.TX_EXIT_STATE = EXIT_TO_READY; - g_radio.word_mode_cfg.WORK_MODE_CFG2_u._BITS.RX_DC_EN = 0; - g_radio.word_mode_cfg.WORK_MODE_CFG2_u._BITS.RX_AUTO_HOP_EN = 0; - g_radio.word_mode_cfg.WORK_MODE_CFG2_u._BITS.RX_ACK_EN = 0; - g_radio.word_mode_cfg.WORK_MODE_CFG2_u._BITS.RX_TIMER_EN = 0; - g_radio.word_mode_cfg.WORK_MODE_CFG2_u._BITS.RX_EXIT_STATE = EXIT_TO_READY; - g_radio.word_mode_cfg.WORK_MODE_CFG2_u._BITS.CSMA_EN = 0; - g_radio.word_mode_cfg.WORK_MODE_CFG3_u._BITS.PKT_DONE_EXIT_EN = 0; //depend on RX_EXIT_STATE - g_radio.word_mode_cfg.WORK_MODE_CFG3_u._BITS.RX_HOP_SLP_MODE = 0; - g_radio.word_mode_cfg.WORK_MODE_CFG3_u._BITS.SLP_MODE = 0; - g_radio.word_mode_cfg.WORK_MODE_CFG4_u._BITS.LFCLK_OUT_EN = 0; - g_radio.word_mode_cfg.WORK_MODE_CFG4_u._BITS.LFCLK_SEL = 0; - g_radio.word_mode_cfg.WORK_MODE_CFG4_u._BITS.SLEEP_TIMER_EN = 0; - g_radio.word_mode_cfg.WORK_MODE_CFG4_u._BITS.TIMER_RAND_MODE = 0; - g_radio.word_mode_cfg.WORK_MODE_CFG5_u._BITS.CSMA_CCA_MODE = 0; - g_radio.word_mode_cfg.WORK_MODE_CFG5_u._BITS.CSMA_CCA_WIN_SEL = 0; - g_radio.word_mode_cfg.WORK_MODE_CFG5_u._BITS.CSMA_CCA_INT_SEL = 0; - g_radio.word_mode_cfg.WORK_MODE_CFG5_u._BITS.CSMA_PERSIST_EN = 0; + /* Step5 */ + vRadioConfigPageReg( 0, g_cmt2310a_page0, CMT2310A_PAGE0_SIZE ); //config page 0 + vRadioConfigPageReg( 1, g_cmt2310a_page1, CMT2310A_PAGE1_SIZE ); //config page 1 + vRadioSetNirq( CMT2310A_nIRQ_TCXO ); //for TCXO need cofig as nIRQ pin at first + vRadioTcxoDrvSel( 0 ); //drive power - g_radio.word_mode_cfg.WORK_MODE_CFG6_u._BITS.FREQ_HOP_MANU_EN = 1;//使能手动快速跳频，不使能手动跳频无法使用 + fw_rev = (byte)g_chip_id; //dealwith Xtal + switch(fw_rev) + { + case 0xC0: + vRadioXoWaitCfg(RADIO_CGU_DIV4); + break; + default: + break; + } - g_radio.word_mode_cfg.FREQ_CHANL_NANU = 92;//手动跳频信道0~255 - g_radio.word_mode_cfg.FREQ_DONE_TIMES = 0; - g_radio.word_mode_cfg.FREQ_SPACE = 250;//跳频信道间隔0~255 KHz - g_radio.word_mode_cfg.FREQ_TIMES = 0; - g_radio.word_mode_cfg.SLEEP_TIMER_M = 0; - g_radio.word_mode_cfg.SLEEP_TIMER_R = 0; - g_radio.word_mode_cfg.RX_TIMER_T1_M = 0; //M*2^(R+1)*5us=M*2^R*10us, - g_radio.word_mode_cfg.RX_TIMER_T1_R = 0; //R=7, unit=0.64ms - g_radio.word_mode_cfg.RX_TIMER_T2_M = 0; - g_radio.word_mode_cfg.RX_TIMER_T2_R = 0; - g_radio.word_mode_cfg.RX_TIMER_CSMA_M = 0; - g_radio.word_mode_cfg.RX_TIMER_CSMA_R = 0; - g_radio.word_mode_cfg.TX_DC_TIMES = 0; - g_radio.word_mode_cfg.TX_RS_TIMES = 0; - g_radio.word_mode_cfg.CSMA_TIMES = 0; - g_radio.word_mode_cfg.SLEEP_TIMER_CSMA_M = 0; - g_radio.word_mode_cfg.SLEEP_TIMER_CSMA_R = 0; - vRadioCfgWorkMode( &g_radio.word_mode_cfg ); - //FIFO Init - vRadioFifoMerge( FALSE ); - vRadioSetFifoTH( 30 ); - vRadioClearRxFifo(); //reset & clear fifo - vRadioClearTxFifo(); - vRadioFifoAutoClearGoRx( TRUE ); //when crc error, need to auto clear fifo, should enable - vRadioRssiUpdateSel( CMT2310A_RSSI_UPDATE_ALWAYS ); - vRadioSetAntSwitch( FALSE, FALSE ); // - vRadioDcdcCfg( TRUE ); //dc-dc off + /* Step6 */ + vRadioPowerUpBoot(); + delay1ms( 10 ); + + /* Step7 */ + bRadioGoStandby(); + delay1ms( 2 ); + bRadioApiCommand( 0x02 ); // + delay1ms( 10 ); + + /* Step8 */ + bRadioApiCommand( 0x01 ); //IR Calibration, need some times + vRadioCapLoad( 2 ); //Xo Cap + + /* Step9, GPIOn and interrupt setting */ + vRadioSetGpio0( CMT2310A_GPIO0_INT3 ); + vRadioSetGpio1( CMT2310A_GPIO1_INT2 ); + vRadioSetGpio2( CMT2310A_GPIO2_DCLK ); + vRadioSetGpio3( CMT2310A_GPIO3_DOUT ); + vRadioSetGpio4( CMT2310A_GPIO4_INT1 ); + vRadioSetGpio5( CMT2310A_GPIO5_nRST ); + //INT1 = RX_FIFO_WBYTE, INT2 = PKT_DONE + vRadioSetInt1Sel( INT_SRC_RX_FIFO_WBYTE ); + vRadioSetInt2Sel( INT_SRC_PKT_DONE ); + vRadioSetInt1Polar( FALSE ); + vRadioSetInt2Polar( FALSE ); + vRadioSetInt3Polar( FALSE ); + //interrupt source enable config + g_radio.int_src_en._BITS.PKT_DONE_EN = 1; + g_radio.int_src_en._BITS.CRC_PASS_EN = 1; + g_radio.int_src_en._BITS.ADDR_PASS_EN = 0; + g_radio.int_src_en._BITS.SYNC_PASS_EN = 1; + g_radio.int_src_en._BITS.PREAM_PASS_EN = 1; + g_radio.int_src_en._BITS.TX_DONE_EN = 1; + g_radio.int_src_en._BITS.RX_TOUT_EN = 1; + g_radio.int_src_en._BITS.LD_STOP_EN = 0; + g_radio.int_src_en._BITS.LBD_STOP_EN = 0; + g_radio.int_src_en._BITS.LBD_STAT_EN = 0; + g_radio.int_src_en._BITS.PKT_ERR_EN = 0; + g_radio.int_src_en._BITS.RSSI_COLL_EN = 0; + g_radio.int_src_en._BITS.OP_CMD_FAILED_EN = 0; + g_radio.int_src_en._BITS.RSSI_PJD_EN = 0; + g_radio.int_src_en._BITS.SEQ_MATCH_EN = 0; + g_radio.int_src_en._BITS.NACK_RECV_EN = 0; + g_radio.int_src_en._BITS.TX_RESEND_DONE_EN = 0; + g_radio.int_src_en._BITS.ACK_RECV_FAILED_EN = 0; + g_radio.int_src_en._BITS.TX_DC_DONE_EN = 0; + g_radio.int_src_en._BITS.CSMA_DONE_EN = 0; + g_radio.int_src_en._BITS.CCA_STAT_EN = 0; + g_radio.int_src_en._BITS.API_DONE_EN = 0; + g_radio.int_src_en._BITS.TX_FIFO_TH_EN = 1; + g_radio.int_src_en._BITS.TX_FIFO_NMTY_EN = 1; + g_radio.int_src_en._BITS.TX_FIFO_FULL_EN = 1; + g_radio.int_src_en._BITS.RX_FIFO_OVF_EN = 1; + g_radio.int_src_en._BITS.RX_FIFO_TH_EN = 1; + g_radio.int_src_en._BITS.RX_FIFO_NMTY_EN = 1; + g_radio.int_src_en._BITS.RX_FIFO_FULL_EN = 1; + vRadioInterruptSoucreCfg( &g_radio.int_src_en ); + //packet preamble config + g_radio.preamble_cfg.PREAM_LENG_UNIT = 0; //8-bits mode + g_radio.preamble_cfg.PREAM_VALUE = 0xAA; // + g_radio.preamble_cfg.RX_PREAM_SIZE = 2; // + g_radio.preamble_cfg.TX_PREAM_SIZE = 16; + vRadioCfgPreamble( &g_radio.preamble_cfg ); + //packet syncword config + g_radio.sync_cfg.SYN_CFG_u._BITS.SYNC_MAN_EN = 0; //disable syncword manchester coding + g_radio.sync_cfg.SYN_CFG_u._BITS.SYNC_SIZE = 2; //enable 3 bytes for syncword + g_radio.sync_cfg.SYN_CFG_u._BITS.SYNC_TOL = 0; + g_radio.sync_cfg.SYN_CFG_u._BITS.SYNC_MODE_SEL = 0; //normal packet + g_radio.sync_cfg.SYNC_VALUE[0] = 0xAA; + g_radio.sync_cfg.SYNC_VALUE[1] = 0x2D; + g_radio.sync_cfg.SYNC_VALUE[2] = 0xD4; + g_radio.sync_cfg.SYNC_VALUE_SEL = 0; //select SYN_VAL + vRadioCfgSyncWord( &g_radio.sync_cfg ); + //packet node address config + g_radio.addr_cfg.ADDR_CFG_u._BITS.ADDR_DET_MODE = 0; //disable Node Address + vRadioCfgNodeAddr( &g_radio.addr_cfg ); + //packet crc config + g_radio.crc_cfg.CRC_CFG_u._BITS.CRC_EN = 1; //enable crc + g_radio.crc_cfg.CRC_CFG_u._BITS.CRC_BIT_ORDER = 0; + g_radio.crc_cfg.CRC_CFG_u._BITS.CRC_REFIN = 0; + g_radio.crc_cfg.CRC_CFG_u._BITS.CRC_RANGE = 0; + g_radio.crc_cfg.CRC_CFG_u._BITS.CRC_BIT_INV = 0; + g_radio.crc_cfg.CRC_CFG_u._BITS.CRC_BYTE_SWAP = 0; + g_radio.crc_cfg.CRC_CFG_u._BITS.CRC_REFOUT = 0; //whole payload + g_radio.crc_cfg.CRC_CFG_u._BITS.CRCERR_CLR_FIFO_EN = 0; //note: need ative FIFO_AUTO_CLR_RX_EN = 1 or call vRadioFifoAutoClearGoRx(1) + g_radio.crc_cfg.CRC_CFG_u._BITS.CRC_SIZE = 1; //crc-16 mode + g_radio.crc_cfg.CRC_POLY_u.u32_POLY = 0x10210000; + g_radio.crc_cfg.CRC_SEED_u.u32_SEED = 0x00000000; + vRadioCfgCrc( &g_radio.crc_cfg ); + //packet coding format + g_radio.coding_format_cfg.CODING_FORMAT_CFG_u._BITS.MANCH_EN = 0; + g_radio.coding_format_cfg.CODING_FORMAT_CFG_u._BITS.MANCH_TYPE = 0; + g_radio.coding_format_cfg.CODING_FORMAT_CFG_u._BITS.WHITEN_EN = 0; + g_radio.coding_format_cfg.CODING_FORMAT_CFG_u._BITS.WHITEN_TYPE = 0; + g_radio.coding_format_cfg.CODING_FORMAT_CFG_u._BITS.WHITEN_SEED_TYP = 0; + g_radio.coding_format_cfg.CODING_FORMAT_CFG_u._BITS.FEC_EN = 0; + g_radio.coding_format_cfg.CODING_FORMAT_CFG_u._BITS.FEC_RSC_NRNSC_SEL = 0; + g_radio.coding_format_cfg.CODING_FORMAT_CFG_u._BITS.FEC_TICC = 0; + g_radio.coding_format_cfg.WHITEN_SEED = 0x01FF; + g_radio.coding_format_cfg.FEC_PAD_CODE = 0; + vRadioCfgCodeFormat( &g_radio.coding_format_cfg ); + //packet frame format + g_radio.frame_cfg.DATA_MODE = 2; //0=direct mode, 2=packet mode + g_radio.frame_cfg.FRAME_CFG1_u._BITS.PKT_TYPE = 1; //0=fixd-length packet mode 1=可变长 + g_radio.frame_cfg.FRAME_CFG1_u._BITS.PAYLOAD_BIT_ORDER = 0; //msb first + g_radio.frame_cfg.FRAME_CFG1_u._BITS.ADDR_LEN_CONF = 0; + g_radio.frame_cfg.FRAME_CFG1_u._BITS.PAGGYBACKING_EN = 0; + g_radio.frame_cfg.FRAME_CFG1_u._BITS.LENGTH_SIZE = 0; + g_radio.frame_cfg.FRAME_CFG1_u._BITS.INTERLEAVE_EN = 0; //note: when FEC enable, INTERLEAVE_EN should be set 1 + g_radio.frame_cfg.FRAME_CFG2_u._BITS.TX_PREFIX_TYPE = TX_PREFIX_SEL_PREAMBLE; //transmit preamble + g_radio.frame_cfg.FRAME_CFG2_u._BITS.SEQNUM_EN = 0; + g_radio.frame_cfg.FRAME_CFG2_u._BITS.SEQNUM_AUTO_INC = 0; + g_radio.frame_cfg.FRAME_CFG2_u._BITS.SEQNUM_SIZE = 0; + g_radio.frame_cfg.FRAME_CFG2_u._BITS.SEQNUM_MACH_EN = 0; + g_radio.frame_cfg.FRAME_CFG2_u._BITS.FCS2_EN = 0; + g_radio.frame_cfg.TX_PKT_NUM = 0; + g_radio.frame_cfg.TX_PKT_GAP = 0; + g_radio.frame_cfg.FCS2_TX_IN = 0; + g_radio.frame_cfg.PAYLOAD_LENGTH = UHF_LEN; + vRadioCfgFrameFormat( &g_radio.frame_cfg ); + //Run Mode Config + g_radio.word_mode_cfg.WORK_MODE_CFG1_u._BITS.TX_DC_EN = 0; + g_radio.word_mode_cfg.WORK_MODE_CFG1_u._BITS.TX_ACK_EN = 0; + g_radio.word_mode_cfg.WORK_MODE_CFG1_u._BITS.TX_DC_PERSIST_EN = 0; + g_radio.word_mode_cfg.WORK_MODE_CFG1_u._BITS.TX_AUTO_HOP_EN = 0; + g_radio.word_mode_cfg.WORK_MODE_CFG1_u._BITS.TX_EXIT_STATE = EXIT_TO_READY; + g_radio.word_mode_cfg.WORK_MODE_CFG2_u._BITS.RX_DC_EN = 0; + g_radio.word_mode_cfg.WORK_MODE_CFG2_u._BITS.RX_AUTO_HOP_EN = 0; + g_radio.word_mode_cfg.WORK_MODE_CFG2_u._BITS.RX_ACK_EN = 0; + g_radio.word_mode_cfg.WORK_MODE_CFG2_u._BITS.RX_TIMER_EN = 0; + g_radio.word_mode_cfg.WORK_MODE_CFG2_u._BITS.RX_EXIT_STATE = EXIT_TO_READY; + g_radio.word_mode_cfg.WORK_MODE_CFG2_u._BITS.CSMA_EN = 0; + g_radio.word_mode_cfg.WORK_MODE_CFG3_u._BITS.PKT_DONE_EXIT_EN = 0; //depend on RX_EXIT_STATE + g_radio.word_mode_cfg.WORK_MODE_CFG3_u._BITS.RX_HOP_SLP_MODE = 0; + g_radio.word_mode_cfg.WORK_MODE_CFG3_u._BITS.SLP_MODE = 0; + g_radio.word_mode_cfg.WORK_MODE_CFG4_u._BITS.LFCLK_OUT_EN = 0; + g_radio.word_mode_cfg.WORK_MODE_CFG4_u._BITS.LFCLK_SEL = 0; + g_radio.word_mode_cfg.WORK_MODE_CFG4_u._BITS.SLEEP_TIMER_EN = 0; + g_radio.word_mode_cfg.WORK_MODE_CFG4_u._BITS.TIMER_RAND_MODE = 0; + g_radio.word_mode_cfg.WORK_MODE_CFG5_u._BITS.CSMA_CCA_MODE = 0; + g_radio.word_mode_cfg.WORK_MODE_CFG5_u._BITS.CSMA_CCA_WIN_SEL = 0; + g_radio.word_mode_cfg.WORK_MODE_CFG5_u._BITS.CSMA_CCA_INT_SEL = 0; + g_radio.word_mode_cfg.WORK_MODE_CFG5_u._BITS.CSMA_PERSIST_EN = 0; + + g_radio.word_mode_cfg.WORK_MODE_CFG6_u._BITS.FREQ_HOP_MANU_EN = 1;//使能手动快速跳频，不使能手动跳频无法使用 + + g_radio.word_mode_cfg.FREQ_CHANL_NANU = 92;//手动跳频信道0~255 + g_radio.word_mode_cfg.FREQ_DONE_TIMES = 0; + g_radio.word_mode_cfg.FREQ_SPACE = 250;//跳频信道间隔0~255 KHz + g_radio.word_mode_cfg.FREQ_TIMES = 0; + g_radio.word_mode_cfg.SLEEP_TIMER_M = 0; + g_radio.word_mode_cfg.SLEEP_TIMER_R = 0; + g_radio.word_mode_cfg.RX_TIMER_T1_M = 0; //M*2^(R+1)*5us=M*2^R*10us, + g_radio.word_mode_cfg.RX_TIMER_T1_R = 0; //R=7, unit=0.64ms + g_radio.word_mode_cfg.RX_TIMER_T2_M = 0; + g_radio.word_mode_cfg.RX_TIMER_T2_R = 0; + g_radio.word_mode_cfg.RX_TIMER_CSMA_M = 0; + g_radio.word_mode_cfg.RX_TIMER_CSMA_R = 0; + g_radio.word_mode_cfg.TX_DC_TIMES = 0; + g_radio.word_mode_cfg.TX_RS_TIMES = 0; + g_radio.word_mode_cfg.CSMA_TIMES = 0; + g_radio.word_mode_cfg.SLEEP_TIMER_CSMA_M = 0; + g_radio.word_mode_cfg.SLEEP_TIMER_CSMA_R = 0; + vRadioCfgWorkMode( &g_radio.word_mode_cfg ); + //FIFO Init + vRadioFifoMerge( FALSE ); + vRadioSetFifoTH( 30 ); + vRadioClearRxFifo(); //reset & clear fifo + vRadioClearTxFifo(); + vRadioFifoAutoClearGoRx( TRUE ); //when crc error, need to auto clear fifo, should enable + vRadioRssiUpdateSel( CMT2310A_RSSI_UPDATE_ALWAYS ); + vRadioSetAntSwitch( FALSE, FALSE ); // + vRadioDcdcCfg( TRUE ); //dc-dc off } void vRadioClearInterrupt( void ) diff --git a/NSPE/WIFI_IOT/bsp/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/radio_hal.c b/NSPE/WIFI_IOT/bsp/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/radio_hal.c index 4f8e073..d24c790 100755 --- a/NSPE/WIFI_IOT/bsp/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/radio_hal.c +++ b/NSPE/WIFI_IOT/bsp/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/radio_hal.c @@ -1,4 +1,5 @@ #include "radio_hal.h" +#include "board.h" void delay1ms(uint16_t cnt) { @@ -440,6 +441,18 @@ void vRadioPowerUpBoot( void ) bSpiWriteByte( CMT2310A_CTL_REG_00, CMT2310A_REBOOT ); } +/****************************** +**Name: vRadioPowerUpBoot +**Func: Radio power up boot start +**Input: None +*Output: None +********************************/ +void vRadioPowerUp( void ) +{ + gpio_bit_write(BSP_GPIO_PORT_E48_GP5, BSP_GPIO_PIN_E48_GP5, RESET); + delay1ms(10); +} + /****************************** **Name: vRadioSoftReset **Func: Radio soft reset @@ -455,6 +468,20 @@ void vRadioSoftReset( void ) delay10us( 100 ); } +/****************************** +**Name: vRadioSoftReset +**Func: Radio soft reset +**Input: None +*Output: None +********************************/ +void vRadioHardReset( void ) +{ + gpio_bit_write(BSP_GPIO_PORT_E48_GP5, BSP_GPIO_PIN_E48_GP5, SET); + delay10us(10); + gpio_bit_write(BSP_GPIO_PORT_E48_GP5, BSP_GPIO_PIN_E48_GP5, RESET); + delay1ms(10); +} + /****************************** **Name: vRadioSetPaOutputMode **Func: Radio config PA output mode @@ -512,16 +539,13 @@ void vRadioSetTxDataInverse( boolean_t cfg_en ) ********************************/ void vRadioSetAntSwitch( boolean_t cfg_en, boolean_t cfg_polar ) { - uint8_t cfg_tmp = 0; - if( cfg_en ) - { - cfg_tmp |= CMT2310A_TRX_SWT_EN; - } - if( cfg_polar ) - { - cfg_tmp |= CMT2310A_TRX_SWT_INV; - } - bRadioSetReg( CMT2310A_CTL_REG_22, cfg_tmp, ( CMT2310A_TRX_SWT_EN | CMT2310A_TRX_SWT_INV ) ); + uint8_t cfg_tmp = 0; + + if( cfg_en ) + cfg_tmp |= CMT2310A_TRX_SWT_EN; + if( cfg_polar ) + cfg_tmp |= CMT2310A_TRX_SWT_INV; + bRadioSetReg( CMT2310A_CTL_REG_22, cfg_tmp, ( CMT2310A_TRX_SWT_EN | CMT2310A_TRX_SWT_INV ) ); } /****************************** diff --git a/NSPE/WIFI_IOT/bsp/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/radio_hal.h b/NSPE/WIFI_IOT/bsp/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/radio_hal.h index 01a8ede..d3a8ed3 100755 --- a/NSPE/WIFI_IOT/bsp/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/radio_hal.h +++ b/NSPE/WIFI_IOT/bsp/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/radio_hal.h @@ -43,44 +43,46 @@ extern uint8_t bRadioReadReg( uint8_t addr ); extern uint8_t bRadioWriteReg( uint8_t addr, uint8_t reg_dat ); extern uint8_t bRadioSetReg( uint8_t addr, uint8_t set_bits, uint8_t mask_bits ); -extern void vRadioLoadRegs( uint8_t sta_adr, uint8_t* ptr_buf, uint8_t length ); -extern void vRadioStoreRegs( uint8_t sta_adr, uint8_t* ptr_buf, uint8_t length ); +extern void vRadioLoadRegs( uint8_t sta_adr, uint8_t* ptr_buf, uint8_t length ); +extern void vRadioStoreRegs( uint8_t sta_adr, uint8_t* ptr_buf, uint8_t length ); -extern void vRadioBurstReadRegs( uint8_t* ptr_buf, uint8_t length ); -extern void vRadioBurstWriteRegs( uint8_t* ptr_buf, uint8_t length ); +extern void vRadioBurstReadRegs( uint8_t* ptr_buf, uint8_t length ); +extern void vRadioBurstWriteRegs( uint8_t* ptr_buf, uint8_t length ); -extern void vRadioReadFifo( uint8_t* ptr_fifo, uint8_t length ); -extern void vRadioWriteFifo( uint8_t* ptr_fifo, uint8_t length ); -extern void vRadioReadTxFifo( uint8_t* ptr_fifo, uint8_t length ); +extern void vRadioReadFifo( uint8_t* ptr_fifo, uint8_t length ); +extern void vRadioWriteFifo( uint8_t* ptr_fifo, uint8_t length ); +extern void vRadioReadTxFifo( uint8_t* ptr_fifo, uint8_t length ); -extern void vRadioSpiModeSel( boolean_t spi_mod ); -extern void vRadioSetTxDin( boolean_t cfg_din, uint8_t pin_sel ); -extern void vRadioSetDigClkOut( boolean_t cfg_out ); -extern void vRadioSetLfxoPad( boolean_t cfg_lfxo ); -extern void vRadioSetGpio0( uint8_t gpio0_sel ); -extern void vRadioSetGpio1( uint8_t gpio1_sel ); -extern void vRadioSetGpio2( uint8_t gpio2_sel ); -extern void vRadioSetGpio3( uint8_t gpio3_sel ); -extern void vRadioSetGpio4( uint8_t gpio4_sel ); -extern void vRadioSetGpio5( uint8_t gpio5_sel ); -extern void vRadioSetNirq( uint8_t nirq_sel ); -extern void vRadioTcxoDrvSel( uint8_t drv_sel ); +extern void vRadioSpiModeSel( boolean_t spi_mod ); +extern void vRadioSetTxDin( boolean_t cfg_din, uint8_t pin_sel ); +extern void vRadioSetDigClkOut( boolean_t cfg_out ); +extern void vRadioSetLfxoPad( boolean_t cfg_lfxo ); +extern void vRadioSetGpio0( uint8_t gpio0_sel ); +extern void vRadioSetGpio1( uint8_t gpio1_sel ); +extern void vRadioSetGpio2( uint8_t gpio2_sel ); +extern void vRadioSetGpio3( uint8_t gpio3_sel ); +extern void vRadioSetGpio4( uint8_t gpio4_sel ); +extern void vRadioSetGpio5( uint8_t gpio5_sel ); +extern void vRadioSetNirq( uint8_t nirq_sel ); +extern void vRadioTcxoDrvSel( uint8_t drv_sel ); -extern void vRadioRegPageSel( uint8_t page_sel ); -extern void vRadioPowerUpBoot( void ); -extern void vRadioSoftReset( void ); -extern void vRadioSetPaOutputMode( boolean_t cfg_en ); -extern void vRadioSetTxDataInverse( boolean_t cfg_en ); -extern void vRadioSetAntSwitch( boolean_t cfg_en, boolean_t cfg_polar ); +extern void vRadioRegPageSel( uint8_t page_sel ); +extern void vRadioPowerUp( void ); +extern void vRadioPowerUpBoot( void ); +extern void vRadioHardReset( void ); +extern void vRadioSoftReset( void ); +extern void vRadioSetPaOutputMode( boolean_t cfg_en ); +extern void vRadioSetTxDataInverse( boolean_t cfg_en ); +extern void vRadioSetAntSwitch( boolean_t cfg_en, boolean_t cfg_polar ); -extern void vRadioDcdcCfg( boolean_t on_off ); -extern void vRadioCapLoad( uint8_t cap_value ); -extern void vRadioLfoscCfg( boolean_t on_off ); -extern void vRadioXoWaitCfg( uint8_t div_sel ); +extern void vRadioDcdcCfg( boolean_t on_off ); +extern void vRadioCapLoad( uint8_t cap_value ); +extern void vRadioLfoscCfg( boolean_t on_off ); +extern void vRadioXoWaitCfg( uint8_t div_sel ); -extern void delay1ms(uint16_t cnt); -extern void delay10us(uint32_t cnt); +extern void delay1ms(uint16_t cnt); +extern void delay10us(uint32_t cnt); #endif