From f35fba223cfab5dbcec5fdb932d87d78f7680338 Mon Sep 17 00:00:00 2001 From: gaoyang3513 Date: Thu, 1 Aug 2024 11:44:58 +0800 Subject: [PATCH] =?UTF-8?q?[Add]=20NBL=20=E6=96=B0=E5=A2=9ECMT2310=20?= =?UTF-8?q?=E9=A9=B1=E5=8A=A8?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- MBL/source_ns/drivers/.editorconfig | 12 + .../Uart_PingPong/ebyte/ebyte_callback.c | 155 +++ .../Uart_PingPong/ebyte/ebyte_callback.h | 8 + .../Uart_PingPong/ebyte/ebyte_conf.h | 34 + .../Uart_PingPong/ebyte/ebyte_core.c | 48 + .../Uart_PingPong/ebyte/ebyte_core.h | 46 + .../Uart_PingPong/ebyte/ebyte_port.c | 97 ++ .../Uart_PingPong/ebyte/ebyte_port.h | 33 + .../0_Project/Uart_PingPong/ebyte_e48.h | 6 + .../0_Project/Uart_PingPong/irq_handle.c | 211 +++ .../0_Project/Uart_PingPong/irq_handle.h | 38 + .../CMT2310/0_Project/Uart_PingPong/main.c | 227 +++ .../CMT2310/1_Middleware/Kfifo/ebyte_kfifo.c | 107 ++ .../CMT2310/1_Middleware/Kfifo/ebyte_kfifo.h | 19 + .../1_Middleware/Produce/ebyte_debug.c | 122 ++ .../1_Middleware/Produce/ebyte_debug.h | 14 + .../2_Ebyte_Board_Support/E15-EVB02/board.c | 340 +++++ .../2_Ebyte_Board_Support/E15-EVB02/board.h | 181 +++ .../E15-EVB02/board_button.c | 147 ++ .../E15-EVB02/board_button.h | 6 + .../E15-EVB02/board_mini_printf.c | 203 +++ .../E15-EVB02/board_mini_printf.h | 6 + .../E48xMx/CMT2310A_def.h | 578 ++++++++ .../E48xMx/CMT2310A_def.h.orig | 578 ++++++++ .../E48xMx/CMT2310A_reg.h | 1229 +++++++++++++++++ .../E48xMx/cmt2310a_410mhz.c | 428 ++++++ .../E48xMx/cmt2310a_433mhz.c | 351 +++++ .../E48xMx/cmt2310a_868mhz.c | 352 +++++ .../E48xMx/cmt2310a_915mhz.c | 352 +++++ .../E48xMx/ebyte_e48x.c | 111 ++ .../E48xMx/ebyte_e48x.h | 23 + .../E48xMx/radio.c | 414 ++++++ .../E48xMx/radio.h | 40 + .../E48xMx/radio_hal.c | 626 +++++++++ .../E48xMx/radio_hal.h | 89 ++ .../E48xMx/radio_mac.c | 482 +++++++ .../E48xMx/radio_mac.h | 49 + .../E48xMx/radio_phy.c | 645 +++++++++ .../E48xMx/radio_phy.h | 65 + .../E48xMx/radio_spi.c | 108 ++ .../E48xMx/radio_spi.h | 17 + MBL/source_ns/drivers/CMT2310/CMakeLists.txt | 55 + MBL/source_ns/drivers/CMT2310/readme.md | 22 + 43 files changed, 8674 insertions(+) create mode 100644 MBL/source_ns/drivers/.editorconfig create mode 100755 MBL/source_ns/drivers/CMT2310/0_Project/Uart_PingPong/ebyte/ebyte_callback.c create mode 100755 MBL/source_ns/drivers/CMT2310/0_Project/Uart_PingPong/ebyte/ebyte_callback.h create mode 100755 MBL/source_ns/drivers/CMT2310/0_Project/Uart_PingPong/ebyte/ebyte_conf.h create mode 100755 MBL/source_ns/drivers/CMT2310/0_Project/Uart_PingPong/ebyte/ebyte_core.c create mode 100755 MBL/source_ns/drivers/CMT2310/0_Project/Uart_PingPong/ebyte/ebyte_core.h create mode 100755 MBL/source_ns/drivers/CMT2310/0_Project/Uart_PingPong/ebyte/ebyte_port.c create mode 100755 MBL/source_ns/drivers/CMT2310/0_Project/Uart_PingPong/ebyte/ebyte_port.h create mode 100644 MBL/source_ns/drivers/CMT2310/0_Project/Uart_PingPong/ebyte_e48.h create mode 100755 MBL/source_ns/drivers/CMT2310/0_Project/Uart_PingPong/irq_handle.c create mode 100755 MBL/source_ns/drivers/CMT2310/0_Project/Uart_PingPong/irq_handle.h create mode 100755 MBL/source_ns/drivers/CMT2310/0_Project/Uart_PingPong/main.c create mode 100755 MBL/source_ns/drivers/CMT2310/1_Middleware/Kfifo/ebyte_kfifo.c create mode 100755 MBL/source_ns/drivers/CMT2310/1_Middleware/Kfifo/ebyte_kfifo.h create mode 100755 MBL/source_ns/drivers/CMT2310/1_Middleware/Produce/ebyte_debug.c create mode 100755 MBL/source_ns/drivers/CMT2310/1_Middleware/Produce/ebyte_debug.h create mode 100755 MBL/source_ns/drivers/CMT2310/2_Ebyte_Board_Support/E15-EVB02/board.c create mode 100755 MBL/source_ns/drivers/CMT2310/2_Ebyte_Board_Support/E15-EVB02/board.h create mode 100755 MBL/source_ns/drivers/CMT2310/2_Ebyte_Board_Support/E15-EVB02/board_button.c create mode 100755 MBL/source_ns/drivers/CMT2310/2_Ebyte_Board_Support/E15-EVB02/board_button.h create mode 100755 MBL/source_ns/drivers/CMT2310/2_Ebyte_Board_Support/E15-EVB02/board_mini_printf.c create mode 100755 MBL/source_ns/drivers/CMT2310/2_Ebyte_Board_Support/E15-EVB02/board_mini_printf.h create mode 100755 MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/CMT2310A_def.h create mode 100755 MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/CMT2310A_def.h.orig create mode 100755 MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/CMT2310A_reg.h create mode 100755 MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/cmt2310a_410mhz.c create mode 100755 MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/cmt2310a_433mhz.c create mode 100755 MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/cmt2310a_868mhz.c create mode 100755 MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/cmt2310a_915mhz.c create mode 100755 MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/ebyte_e48x.c create mode 100755 MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/ebyte_e48x.h create mode 100755 MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/radio.c create mode 100755 MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/radio.h create mode 100755 MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/radio_hal.c create mode 100755 MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/radio_hal.h create mode 100755 MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/radio_mac.c create mode 100755 MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/radio_mac.h create mode 100755 MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/radio_phy.c create mode 100755 MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/radio_phy.h create mode 100755 MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/radio_spi.c create mode 100755 MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/radio_spi.h create mode 100644 MBL/source_ns/drivers/CMT2310/CMakeLists.txt create mode 100755 MBL/source_ns/drivers/CMT2310/readme.md diff --git a/MBL/source_ns/drivers/.editorconfig b/MBL/source_ns/drivers/.editorconfig new file mode 100644 index 0000000..98ccd7f --- /dev/null +++ b/MBL/source_ns/drivers/.editorconfig @@ -0,0 +1,12 @@ +# EditorConfig is awesome: https://EditorConfig.org + +# top-most EditorConfig file +root = true + +[*] +indent_style = tab +indent_size = 8 +end_of_line = lf +charset = utf-8 +trim_trailing_whitespace = true +insert_final_newline = false \ No newline at end of file diff --git a/MBL/source_ns/drivers/CMT2310/0_Project/Uart_PingPong/ebyte/ebyte_callback.c b/MBL/source_ns/drivers/CMT2310/0_Project/Uart_PingPong/ebyte/ebyte_callback.c new file mode 100755 index 0000000..85db472 --- /dev/null +++ b/MBL/source_ns/drivers/CMT2310/0_Project/Uart_PingPong/ebyte/ebyte_callback.c @@ -0,0 +1,155 @@ +/** + ********************************************************************************** + * @file ebyte_callback.h + * @brief EBYTE驱动库的收发完成回调函数 由客户实现自己的逻辑代码 + * @details 详情请参见 https://www.ebyte.com/ + * @author JiangHeng + * @date 2021-05-13 + * @version 1.0.0 + ********************************************************************************** + * @copyright BSD License + * 成都亿佰特电子科技有限公司 + * ______ ____ __ __ _______ ______ + * | ____| | _ \ \ \ / / |__ __| | ____| + * | |__ | |_) | \ \_/ / | | | |__ + * | __| | _ < \ / | | | __| + * | |____ | |_) | | | | | | |____ + * |______| |____/ |_| |_| |______| + * + ********************************************************************************** + */ +#include "ebyte_callback.h" + +/*= !!!配置目标硬件平台头文件 =======================================*/ +#include "board.h" //E15-EVB02 评估板 +#include "ebyte_debug.h" //E15-EVB02 评估板 +/*= !!!配置目标硬件变量 =======================================*/ +extern uint8_t RxBuffer[64]; +extern uint8_t BufferPing[5]; +extern uint8_t BufferPong[5]; +extern uint8_t Callback_isPingCheckReady; +extern uint8_t PC_isConnected; +extern uint8_t PcEchoBuffer[20]; +/*==================================================================*/ + + + +/* ! + * @brief 发送完成回调接口 由客户实现自己的发送完成逻辑 + * + * @param state 上层回调提供的状态码 客户请根据示例注释找到对应区域 + * + */ +void Ebyte_Port_TransmitCallback( uint16e_t state ) +{ + /* 发送: 正常完成 */ + if( state &= 0x0001 ) + { + //To-do 实现自己的逻辑 + } + /* 发送: 异常超时 */ + else if ( state &= 0x0200 ) + { + //To-do 实现自己的逻辑 + } + /* 发送: 未知错误 */ + else + { + /* 发送状态标识不正确，请检查软硬件 + 常见问题 1:SPI通信不正确 2:模块供电不足 */ + while(1); + } +} + +/* ! + * @brief 接收完成回调接口 由客户实现自己的发送完成逻辑 + * + * @param state 上层回调提供的状态码 客户请根据示例注释找到对应区域 + * + */ +void Ebyte_Port_ReceiveCallback( uint16_t state, uint8_t *buffer, uint8_t length ) +{ + uint8_t j, pcEchoLength; + uint8_t *p; + /* 接收: 正常 */ + if( state &= 0x0002 ) + { + //To-do 实现自己的逻辑 + + /* 通过长度判断是否是ping pong指令 */ + if( length == 4 || length == 5 ) + { + + p = buffer; + for( j = 0; j < 4; j++ ) + { + if( BufferPing[j] != *p++ ) + { + break; + } + + } + //比较到了末尾表示完全匹配ping + if( j == 4 ) + { + Callback_isPingCheckReady = 1;//通知回复Pong + if( length == 5 && PC_isConnected ) + { + BufferPong[4] = buffer[4];//第5字节为按键标识 + } + + } + + if( j!=4 && length == 5 && PC_isConnected ) + { + p = buffer; + + for( j = 0; j < 4; j++ ) + { + if( BufferPong[j] != *p++ ) + { + break; + } + + } + + if( j == 4 )//完全匹配pong + { + if( 0x01 == buffer[4] ) + { + Ebyte_DEBUG_CommandEcho( ( uint8_t* )SimulatedCommandsWireless1, EBYTE_CMD_PACKAGE_LENGTH, PcEchoBuffer, &pcEchoLength ); + } + else + { + Ebyte_DEBUG_CommandEcho( ( uint8_t* )SimulatedCommandsWireless2, EBYTE_CMD_PACKAGE_LENGTH, PcEchoBuffer, &pcEchoLength ); + } + Ebyte_BSP_UartTransmit( PcEchoBuffer, pcEchoLength ); + } + + } + } + + Ebyte_BSP_LedControl( BSP_LED_1, ON ); + + if( ! PC_isConnected ) + { + + DEBUGPRINT("\r\n Receive Data:"); + Ebyte_BSP_UartTransmit ( buffer, length ); + } + + Ebyte_BSP_LedControl( BSP_LED_1, OFF ); + } + /* 接收: 异常超时 */ + else if ( state &= 0x0200 ) + { + //To-do 实现自己的逻辑 + } + /* 接收: 未知错误 */ + else + { + /* 发送状态标识不正确，请检查软硬件 + 常见问题 1:SPI通信不正确 2:模块供电不足 */ + while(1); + } +} \ No newline at end of file diff --git a/MBL/source_ns/drivers/CMT2310/0_Project/Uart_PingPong/ebyte/ebyte_callback.h b/MBL/source_ns/drivers/CMT2310/0_Project/Uart_PingPong/ebyte/ebyte_callback.h new file mode 100755 index 0000000..0eb31e9 --- /dev/null +++ b/MBL/source_ns/drivers/CMT2310/0_Project/Uart_PingPong/ebyte/ebyte_callback.h @@ -0,0 +1,8 @@ +#ifndef _EBYTE_CALLBACK_H_ +#define _EBYTE_CALLBACK_H_ +#include "ebyte_port.h" + +void Ebyte_Port_TransmitCallback( uint16e_t state ); +void Ebyte_Port_ReceiveCallback( uint16e_t state ,uint8e_t *buffer, uint8e_t length); + +#endif \ No newline at end of file diff --git a/MBL/source_ns/drivers/CMT2310/0_Project/Uart_PingPong/ebyte/ebyte_conf.h b/MBL/source_ns/drivers/CMT2310/0_Project/Uart_PingPong/ebyte/ebyte_conf.h new file mode 100755 index 0000000..19335c4 --- /dev/null +++ b/MBL/source_ns/drivers/CMT2310/0_Project/Uart_PingPong/ebyte/ebyte_conf.h @@ -0,0 +1,34 @@ +/** + ********************************************************************************** + * @file ebyte_conf.h + * @brief EBYTE驱动库的通用配置文件 + * @details 详情请参见 https://www.ebyte.com/ + * @author JiangHeng + * @date 2021-05-13 + * @version 1.0.0 + ********************************************************************************** + * @copyright BSD License + * 成都亿佰特电子科技有限公司 + * ______ ____ __ __ _______ ______ + * | ____| | _ \ \ \ / / |__ __| | ____| + * | |__ | |_) | \ \_/ / | | | |__ + * | __| | _ < \ / | | | __| + * | |____ | |_) | | | | | | |____ + * |______| |____/ |_| |_| |______| + * + ********************************************************************************** + */ + +/*= !!!配置产品型号 单选 ============================================*/ +#define EBYTE_E48_433M20S +//#define EBYTE_E48_900M20S + +/*==================================================================*/ + +/* SPI通信 由软件控制CS(NSS)信号 0:禁用 1:启用 */ +#define EBYTE_PORT_SPI_CS_SOFTWARE 1 + +/* 如何检测模块发送时的状态 0:异步中断通知 1:同步阻塞 */ +#define EBYTE_RF_TRANSMIT_CHECK_MODE 1 + + diff --git a/MBL/source_ns/drivers/CMT2310/0_Project/Uart_PingPong/ebyte/ebyte_core.c b/MBL/source_ns/drivers/CMT2310/0_Project/Uart_PingPong/ebyte/ebyte_core.c new file mode 100755 index 0000000..4e0fb91 --- /dev/null +++ b/MBL/source_ns/drivers/CMT2310/0_Project/Uart_PingPong/ebyte/ebyte_core.c @@ -0,0 +1,48 @@ +/** + ********************************************************************************** + * @file ebyte_core.c + * @brief EBYTE驱动库的上层API封装层 帮助客户抽象底层逻辑 + * @details 详情请参见 https://www.ebyte.com/ + * @author JiangHeng + * @date 2021-05-13 + * @version 1.0.0 + ********************************************************************************** + * @copyright BSD License + * 成都亿佰特电子科技有限公司 + * ______ ____ __ __ _______ ______ + * | ____| | _ \ \ \ / / |__ __| | ____| + * | |__ | |_) | \ \_/ / | | | |__ + * | __| | _ < \ / | | | __| + * | |____ | |_) | | | | | | |____ + * |______| |____/ |_| |_| |______| + * + ********************************************************************************** + */ + + +#include "ebyte_core.h" + +/* 指向 E48x 底层驱动函数 */ + +#if defined(EBYTE_E48_433M20S)||defined(EBYTE_E48_900M20S) +const Ebyte_RF_t Ebyte_RF = +{ + Ebyte_E48x_Init, + Ebyte_E48x_SendPayload, + Ebyte_E48x_SetSleep, + Ebyte_E48x_SetRx, + Ebyte_E48x_IntOrPollTask, + Ebyte_E48x_InterruptTrigger, + Ebyte_E48x_GetName, + Ebyte_E48x_GetDriverVersion +}; +#else +/* ebyte_conf.h 宏配置选择的产品型号不正确 */ +#error No product selected ! +#endif + + + + + + diff --git a/MBL/source_ns/drivers/CMT2310/0_Project/Uart_PingPong/ebyte/ebyte_core.h b/MBL/source_ns/drivers/CMT2310/0_Project/Uart_PingPong/ebyte/ebyte_core.h new file mode 100755 index 0000000..5875798 --- /dev/null +++ b/MBL/source_ns/drivers/CMT2310/0_Project/Uart_PingPong/ebyte/ebyte_core.h @@ -0,0 +1,46 @@ +/** + ********************************************************************************** + * @file ebyte_core.h + * @brief EBYTE驱动库的上层API封装层 帮助客户抽象底层逻辑 + * @details 详情请参见 https://www.ebyte.com/ + * @author JiangHeng + * @date 2021-05-13 + * @version 1.0.0 + ********************************************************************************** + * @copyright BSD License + * 成都亿佰特电子科技有限公司 + * ______ ____ __ __ _______ ______ + * | ____| | _ \ \ \ / / |__ __| | ____| + * | |__ | |_) | \ \_/ / | | | |__ + * | __| | _ < \ / | | | __| + * | |____ | |_) | | | | | | |____ + * |______| |____/ |_| |_| |______| + * + ********************************************************************************** + */ + +#include +#include "ebyte_conf.h" + +#if defined(EBYTE_E48_433M20S)||defined(EBYTE_E48_900M20S) +#include "ebyte_e48x.h" +#else +#error No product selected ! +#endif + +typedef struct +{ + void ( *Init )( void ); + void ( *Send )( uint8e_t *buffer, uint8e_t size , uint32e_t timeout); + void ( *EnterSleepMode )( uint8e_t command); + void ( *EnterReceiveMode )( uint32e_t timeout ); + void ( *StartPollTask)( void ); + void ( *InterruptTrigger)( void ); + uint32e_t ( *GetName ) (void ); + uint8e_t ( *GetDriverVersion ) (void ); +}Ebyte_RF_t; + +extern const Ebyte_RF_t Ebyte_RF; + + + diff --git a/MBL/source_ns/drivers/CMT2310/0_Project/Uart_PingPong/ebyte/ebyte_port.c b/MBL/source_ns/drivers/CMT2310/0_Project/Uart_PingPong/ebyte/ebyte_port.c new file mode 100755 index 0000000..61f173f --- /dev/null +++ b/MBL/source_ns/drivers/CMT2310/0_Project/Uart_PingPong/ebyte/ebyte_port.c @@ -0,0 +1,97 @@ +/** + ********************************************************************************** + * @file ebyte_port.h + * @brief EBYTE驱动库的硬件接口层 由客户自己提供IO接口 + * @details 详情请参见 https://www.ebyte.com/ + * @author JiangHeng + * @date 2021-05-13 + * @version 1.0.0 + ********************************************************************************** + * @copyright BSD License + * 成都亿佰特电子科技有限公司 + * ______ ____ __ __ _______ ______ + * | ____| | _ \ \ \ / / |__ __| | ____| + * | |__ | |_) | \ \_/ / | | | |__ + * | __| | _ < \ / | | | __| + * | |____ | |_) | | | | | | |____ + * |______| |____/ |_| |_| |______| + * + ********************************************************************************** + */ +#include "ebyte_port.h" + + +/*= !!!配置目标硬件平台头文件 =======================================*/ +#include "board.h" //E15-EVB02 评估板 +#include "wrapper_os.h" +/*==================================================================*/ + +/* ! + * @brief 配置目标硬件平台SPI接口收发函数 + * + * @param send EBYTE驱动库上层调用需要传输的数据 1 Byte + * @return SPI接收的数据 1 Byte + * @note 当目标平台采用硬件SPI_NSS时，请配置 ebyte_conf.h文件 关闭驱动库的软件控制SPI_CS(NSS) + * 当目标平台采用软件SPI_NSS时，还需额外配置 Ebyte_Port_SpiCsIoControl() 具体请查阅函数说明 + */ +uint8e_t Ebyte_Port_SpiTransmitAndReceivce( uint8e_t send ) +{ + uint8e_t result = 0; + + /* !必须提供: SPI接口 */ + result = Ebyte_BSP_SpiTransAndRecv( send ); + + return result; +} + +/* ! + * @brief (可选)配置目标硬件平台SPI_CS(NSS)函数 + * + * @param cmd EBYTE驱动库上层期望的控制指令 + * @arg 0: 期望CS(NSS)引脚输出低电平逻辑信号 EBYTE模块SPI接口为低电平选中 + * @arg 1: 期望CS(NSS)引脚输出高电平逻辑信号 + * @note 当目标平台采用硬件SPI_NSS时，由配置文件定义 此函数将无效 + * 当目标平台采用软件SPI_NSS时，请配置此函数 + */ +void Ebyte_Port_SpiCsIoControl( uint8e_t cmd ) +{ + if ( cmd == 1 ) + { + /* !可选: SPI CS控制 高电平未选中 */ + Ebyte_BSP_RfSpiUnselected(); + } + else + { + /* !可选: SPI CS控制 低电平选中 */ + Ebyte_BSP_RfSpiSelected( ); + } +} + + + +/* ! + * @brief 配置目标硬件平台延时函数 + * + * @param time 期望延时毫秒 + * @note 请注意时序，模块初始化时将调用此函数，请注意中断是否会影响到此函数 + */ +void Ebyte_Port_DelayMs( uint16e_t time ) +{ + /* !必须提供: 延时函数 */ + sys_ms_sleep(time); +} + + +/* ! + * @brief 配置目标硬件平台延时函数 + * + * @param time 期望延时毫秒 + * @note 请注意时序，模块初始化时将调用此函数，请注意中断是否会影响到此函数 + */ +void Ebyte_Port_DelayUs( uint16e_t time ) +{ + /* !必须提供: 延时函数 */ + sys_us_delay(time); +} + + diff --git a/MBL/source_ns/drivers/CMT2310/0_Project/Uart_PingPong/ebyte/ebyte_port.h b/MBL/source_ns/drivers/CMT2310/0_Project/Uart_PingPong/ebyte/ebyte_port.h new file mode 100755 index 0000000..9b84257 --- /dev/null +++ b/MBL/source_ns/drivers/CMT2310/0_Project/Uart_PingPong/ebyte/ebyte_port.h @@ -0,0 +1,33 @@ +#ifndef __EBYTE_PORT_H +#define __EBYTE_PORT_H + +#include +#include "ebyte_conf.h" + +//#include "stm8l15x.h" +//typedef unsigned char uint8e_t; +//typedef unsigned short uint16e_t; +//typedef unsigned long uint32e_t; +// +//typedef signed char int8e_t; +//typedef signed short int16e_t; +//typedef signed long int32e_t; + +#define uint8e_t uint8_t +#define uint16e_t uint16_t +#define uint32e_t uint32_t +#define int8e_t int8_t +#define int16e_t int16_t +#define int32e_t int32_t + +void Ebyte_Port_RstIoControl( uint8e_t cmd ); +void Ebyte_Port_TxenIoControl( uint8e_t cmd ); +void Ebyte_Port_RxenIoControl( uint8e_t cmd ); +void Ebyte_Port_DelayMs( uint16e_t time ); +void Ebyte_Port_DelayUs( uint16e_t time ); +void Ebyte_Port_SpiCsIoControl( uint8e_t cmd ); + +uint8e_t Ebyte_Port_BusyIoRead( void ); +uint8e_t Ebyte_Port_SpiTransmitAndReceivce( uint8e_t send ); + +#endif /* __EBYTE_PORT_H */ diff --git a/MBL/source_ns/drivers/CMT2310/0_Project/Uart_PingPong/ebyte_e48.h b/MBL/source_ns/drivers/CMT2310/0_Project/Uart_PingPong/ebyte_e48.h new file mode 100644 index 0000000..e9847d4 --- /dev/null +++ b/MBL/source_ns/drivers/CMT2310/0_Project/Uart_PingPong/ebyte_e48.h @@ -0,0 +1,6 @@ +#ifndef __EBYTE_E48_H__ +#define __EBYTE_E48_H__ + +int ebyte_main( void ); + +#endif /* __EBYTE_E48_H__ */ diff --git a/MBL/source_ns/drivers/CMT2310/0_Project/Uart_PingPong/irq_handle.c b/MBL/source_ns/drivers/CMT2310/0_Project/Uart_PingPong/irq_handle.c new file mode 100755 index 0000000..64afbbf --- /dev/null +++ b/MBL/source_ns/drivers/CMT2310/0_Project/Uart_PingPong/irq_handle.c @@ -0,0 +1,211 @@ +/** + ****************************************************************************** + * @file stm8l15x_it.c + * @author MCD Application Team + * @version V1.0.0 + * @date 09/28/2010 + * @brief Main Interrupt Service Routines. + * This file provides template for all peripherals interrupt service routine. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "gd32_it.h" +#include "ebyte_kfifo.h" +#include "ebyte_core.h" +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +static uint8_t Uart_isInRecvState = 0; +static uint8_t Uart_isContinuousRecv = 0; +static uint32_t Uart_TickCounter = 0; +extern uint8_t Uart_isRecvReady; + +static uint16_t Button1_TickCounter = 0; +static uint16_t Button2_TickCounter = 0; + +extern Ebyte_FIFO_t hfifo; +extern uint8_t FIFO_isTimeCheckReady; +static uint32_t FIFO_TickCounter = 0; +/* Private function prototypes -----------------------------------------------*/ +void IT_Timer_ButtonCheck(void); +void IT_Timer_UartCheck(void); +/* Private functions ---------------------------------------------------------*/ + +/** @addtogroup IT_Functions + * @{ + */ + +#ifdef _COSMIC_ +/** + * @brief Dummy interrupt routine + * @par Parameters: + * None + * @retval + * None +*/ +INTERRUPT_HANDLER(NonHandledInterrupt, 0) +{ + /* In order to detect unexpected events during development, + it is recommended to set a breakpoint on the following instruction. + */ +} +#endif + +/*! + \brief This function handles TIMER2 interrupt request. + \param[in] none + \param[out] none + \retval none +*/ +void __TIMER2_IRQHandler(void) +{ + if(SET == timer_interrupt_flag_get(TIMER2, TIMER_INT_UP)){ + /* clear channel 0 interrupt bit */ + timer_interrupt_flag_clear(TIMER2, TIMER_INT_UP); + + /* 按键检测 */ + IT_Timer_ButtonCheck(); + + /* 串口状态检测 */ +// IT_Timer_UartCheck(); + + /* 定时器延时辅助计算 */ + Ebyte_BSP_TimerDecrement(); + } +} + +#if 0 // GY3513 +/** + * @brief USART1 RX / Timer5 Capture/Compare Interrupt routine. + * @param None + * @retval None + */ +INTERRUPT_HANDLER(USART1_RX_TIM5_CC_IRQHandler, 28) +{ + + /* 首帧判断 状态机 触发定时器计时 10ms后未收到下一字节则断帧 */ + if( !Uart_isInRecvState ) + { + Uart_isInRecvState = 1; + } + Uart_isContinuousRecv = 1; + + /* 接收串口数据 1 Byte */ + uint8_t temp = USART_ReceiveData8(USART1) ; + + /* 写入缓存队列 1 Byte */ + Ebyte_FIFO_Write( &hfifo, &temp, 1 ); + + /* 清除中断标识 */ + USART_ClearITPendingBit( USART1, USART_IT_RXNE ); +} + +/* ! + * @brief 定时器中断 状态机 辅助按键检测 + */ +void IT_Timer_ButtonCheck(void) +{ + /* 如果按键1被按下 */ + if( !Ebyte_BSP_ReadButton( BSP_BUTTON_1 ) ) + { + Button1_TickCounter++; + } + else + { + if( Button1_TickCounter > 1000 ) // 1秒 长按 + { + Ebyte_BTN_FIFO_Push( &BSP_BTN_FIFO, BTN_1_LONG); + } + else if( Button1_TickCounter > 50 ) //50毫秒 短按 + { + Ebyte_BTN_FIFO_Push( &BSP_BTN_FIFO, BTN_1_SHORT); + } + else {} //50毫秒以下 认为是抖动 不操作 + + Button1_TickCounter=0; + } + + /* 如果按键2被按下 */ + if( !Ebyte_BSP_ReadButton( BSP_BUTTON_2 ) ) + { + Button2_TickCounter++; + } + else + { + if( Button2_TickCounter > 1000 ) // 1秒 长按 + { + Ebyte_BTN_FIFO_Push( &BSP_BTN_FIFO, BTN_2_LONG); + } + else if( Button2_TickCounter > 50 ) //50毫秒 短按 + { + Ebyte_BTN_FIFO_Push( &BSP_BTN_FIFO, BTN_2_SHORT); + } + else {} //50毫秒以下 认为是抖动 不操作 + + Button2_TickCounter=0; + } +} + +/* ! + * @brief 定时器中断 状态机 辅助时间断帧 + */ +void IT_Timer_UartCheck(void) +{ + /* 串口接收到第一字节起就开始计时 */ + if( Uart_isInRecvState ) + { + Uart_TickCounter++; + + /* 超过10ms没有接收到第二字节 就认为断帧 */ + if( Uart_TickCounter > 10 ) + { + /* 通知主函数接收到一帧 */ + Uart_isRecvReady ++; + /* 停止计时 */ + Uart_isInRecvState = 0; + Uart_TickCounter = 0; + } + + /* 复位FIFO超时检测 */ + FIFO_TickCounter = 0; + } + else + { + /* 如果在串口没有接收数据时 还存在没有发送完的帧 500ms后超时检测成立 清算FIFO中的数据 */ + if( (!Uart_isInRecvState) && Uart_isRecvReady ) + { + FIFO_TickCounter++; + if( FIFO_TickCounter > 500) + { + FIFO_isTimeCheckReady=1; + Uart_isRecvReady = 0; + FIFO_TickCounter = 0; + } + } + } + + /* 串口每接收到1个字节就重新计数 */ + if( Uart_isInRecvState && Uart_isContinuousRecv ) + { + Uart_TickCounter = 0; + Uart_isContinuousRecv = 0; + } +} +#endif // GY3513 + +/** + * @} + */ +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/MBL/source_ns/drivers/CMT2310/0_Project/Uart_PingPong/irq_handle.h b/MBL/source_ns/drivers/CMT2310/0_Project/Uart_PingPong/irq_handle.h new file mode 100755 index 0000000..084f897 --- /dev/null +++ b/MBL/source_ns/drivers/CMT2310/0_Project/Uart_PingPong/irq_handle.h @@ -0,0 +1,38 @@ +/** + ****************************************************************************** + * @file stm8l15x_it.h + * @author MCD Application Team + * @version V1.0.0 + * @date 09/28/2010 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM8L15x_IT_H +#define __STM8L15x_IT_H + +/* Includes ------------------------------------------------------------------*/ +//#include "stm8l15x.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void __TIMER2_IRQHandler(void); + +#endif /* __STM8L15x_IT_H */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/MBL/source_ns/drivers/CMT2310/0_Project/Uart_PingPong/main.c b/MBL/source_ns/drivers/CMT2310/0_Project/Uart_PingPong/main.c new file mode 100755 index 0000000..508bf42 --- /dev/null +++ b/MBL/source_ns/drivers/CMT2310/0_Project/Uart_PingPong/main.c @@ -0,0 +1,227 @@ +/** + ********************************************************************************** + * @file main.c + * @brief E15-EVB02 评估板固件 + * @details 本例程为: 串口无线透传示例 详情请参见 https://www.ebyte.com/ + * @author yxw + * @date 2023-12-25 + * @version 1.0.0 + ********************************************************************************** + * @copyright BSD License + * 成都亿佰特电子科技有限公司 + * ______ ____ __ __ _______ ______ + * | ____| | _ \ \ \ / / |__ __| | ____| + * | |__ | |_) | \ \_/ / | | | |__ + * | __| | _ < \ / | | | __| + * | |____ | |_) | | | | | | |____ + * |______| |____/ |_| |_| |______| + * + ********************************************************************************** + */ + +#include "ebyte_core.h" +#include "ebyte_kfifo.h" +#include "ebyte_debug.h" +#include "wrapper_os.h" +#include "debug_print.h" + +void Task_Transmit( void ); +void Task_Button( void ); + +/* 串口 数据存储队列 */ +Ebyte_FIFO_t hfifo; + +/* 串口 帧接收完成标识 */ +uint8_t Uart_isRecvReady = 0; + +/* 串口 FIFO检查标识 */ +uint8_t FIFO_isTimeCheckReady = 0; + +/* 串口 自定义收/发缓存 */ +uint8_t TxBuffer[64] = {0}; +uint8_t RxBuffer[64] = {0}; +uint8_t PcEchoBuffer[20] = {0}; + +uint8_t BufferPing[5] = {'p', 'i', 'n', 'g'}; +uint8_t BufferPong[5] = {'p', 'o', 'n', 'g'}; + +/* 串口 FIFO检查标识 */ +uint8_t Callback_isPingCheckReady = 0; + +/* 自检模式 标识 */ +uint8_t PC_isConnected = 0; + +static BSP_BTN_EVENT_t BTN_Event; + +/* ! + * @brief 主函数 + */ +int ebyte_main( void ) +{ + /* 板载硬件资源 初始化 */ + Ebyte_BSP_Init(); + /* (可选) 串口中断接收FIFO 可根据需要自行处理 */ + Ebyte_FIFO_Init( &hfifo, EBYTE_FIFO_SIZE ); + /* EBYTE 无线模块初始化 */ + Ebyte_RF.Init(); + /* 启用无线模块接收 */ + Ebyte_RF.EnterReceiveMode( 0 ); + /* MCU 开全局中断 */ + Ebyte_BSP_GlobalIntEnable(); + + DEBUGPRINT( "Start PingPong.....\r\n" ); + DEBUGPRINT( "Please push button1 or button2.....\r\n" ); + + while( 1 ) { + /* 按键事件响应 */ + Task_Button(); + + /* 任务:检测串口数据并无线发送 客户请按需自定义 */ + Task_Transmit(); + + /* 任务:EBYTE驱动库必须的周期执行任务 客户无需修改 */ + Ebyte_RF.StartPollTask(); + + sys_ms_sleep(100); + } +} + +/* ! + * @brief 轮询任务 串口接收的数据通过模块发送 + * + * @note 建议客户将需要发送的数据进行组包处理，否则需要考虑额外的无线传输开销 + * 注意无线模块的模式切换，一般情况下可以处于接收/休眠/周期休眠 此示例过程为: 接收模式->发送模式->接收模式 + */ +void Task_Transmit( void ) +{ + uint16_t length = 0; + uint8_t pcEchoLength = 0; + uint8_t pongLength = 0; + + /* 是否有数据需要无线传输 (来自串口接收FIFO缓存) */ + Ebyte_FIFO_GetDataLength( &hfifo, &length ); + + /* 涉及到异步中断,这里简单示范 判断两种条件 + 1; 串口FIFO中有数据且已经有完整接收的帧，此时启用无线发送( 采用时间断帧方式,连续传输时低于判断时间会导致数据粘包 请根据具体项目自行考虑帧判断 ) + 2: 串口FIFO中有数据但串口已经退出了接收状态，超时检测条件成立 ( 会导致FIFO剩余未发送数据被打包无线发送 请根据具体项目自行考虑帧判断 )*/ + if( ( length != 0 && Uart_isRecvReady ) || ( length != 0 && FIFO_isTimeCheckReady ) ) + { + Ebyte_BSP_LedControl( BSP_LED_1, ON ); + + /* 读取FIFO 数据放入TxBuffer */ + Ebyte_FIFO_Read( &hfifo, TxBuffer, length ); + + /* PC特殊指令响应 */ + if( Ebyte_DEBUG_CommandEcho( TxBuffer,length, PcEchoBuffer, &pcEchoLength ) ) + { + Ebyte_BSP_UartTransmit( PcEchoBuffer , pcEchoLength); + } + /* 非特殊指令则无线透传 */ + else + { + /* 启用无线模块进行发送 */ + Ebyte_RF.Send( TxBuffer, length, 0 ); + + /* 启用无线模块继续接收 */ + Ebyte_RF.EnterReceiveMode( 0 ); + } + + /* 每发完一帧就减少帧计数 串口中断可能已经写入了多帧 */ + if( Uart_isRecvReady ) Uart_isRecvReady --; + if( FIFO_isTimeCheckReady ) FIFO_isTimeCheckReady = 0; + + Ebyte_BSP_LedControl( BSP_LED_1, OFF ); + } + + /* 接收完成回调函数检测到了 ping 命令 回复 pong */ + if( Callback_isPingCheckReady ) + { + if( PC_isConnected ) + { + pongLength = 5; + }else{ + DEBUGPRINT( "\r\n Echo : pong \r\n" ); + pongLength = 4; + } + + /* 启用无线模块进行发送 */ + Ebyte_RF.Send( BufferPong, pongLength, 0 ); + + /* 启用无线模块继续接收 */ + Ebyte_RF.EnterReceiveMode( 0 ); + + Callback_isPingCheckReady = 0; + } +} + +/* ! + * @brief 按键事件响应 + */ +void Task_Button( void ) +{ + uint8_t pcEchoLength = 0; + uint8_t pingLength = 0; + + if( ! Ebyte_BTN_FIFO_Pop( &BSP_BTN_FIFO, &BTN_Event ) ) + { + switch( BTN_Event ) + { + /* 按键1 短按 */ + case BTN_1_SHORT: + Ebyte_BSP_LedControl( BSP_LED_1, ON ); + + if( PC_isConnected ) + { + /* 通知PC */ + Ebyte_DEBUG_CommandEcho( (uint8_t*)SimulatedCommandsButton1, EBYTE_CMD_PACKAGE_LENGTH , PcEchoBuffer, &pcEchoLength ); + Ebyte_BSP_UartTransmit( PcEchoBuffer , pcEchoLength); + BufferPing[4] = 0x01; + pingLength = 5; + }else + { + DEBUGPRINT( "\r\n Send Command : ping \r\n" ); + pingLength = 4; + } + + /* 发送 ping */ + Ebyte_RF.Send( BufferPing, pingLength, 0 ); + Ebyte_RF.EnterReceiveMode( 0 ); + + Ebyte_BSP_LedControl( BSP_LED_1, OFF ); + break; + /* 按键1 长按 */ + case BTN_1_LONG: + Ebyte_BSP_LedControl( BSP_LED_1, TOGGLE ); + break; + /* 按键2 短按 */ + case BTN_2_SHORT: + Ebyte_BSP_LedControl( BSP_LED_2, ON ); + if( PC_isConnected ) + { + /* 通知PC */ + Ebyte_DEBUG_CommandEcho( (uint8_t*)SimulatedCommandsButton2, EBYTE_CMD_PACKAGE_LENGTH , PcEchoBuffer, &pcEchoLength ); + Ebyte_BSP_UartTransmit( PcEchoBuffer , pcEchoLength); + BufferPing[4] = 0x02; + pingLength = 5; + }else + { + DEBUGPRINT( "\r\n Send Command : ping \r\n" ); + pingLength = 4; + } + + /* 发送 ping */ + Ebyte_RF.Send( BufferPing, pingLength, 0 ); + Ebyte_RF.EnterReceiveMode( 0 ); + + Ebyte_BSP_LedControl( BSP_LED_2, OFF ); + break; + /* 按键2 长按 */ + case BTN_2_LONG: + Ebyte_BSP_LedControl( BSP_LED_2, TOGGLE ); + break; + default : + break; + } + } +} + diff --git a/MBL/source_ns/drivers/CMT2310/1_Middleware/Kfifo/ebyte_kfifo.c b/MBL/source_ns/drivers/CMT2310/1_Middleware/Kfifo/ebyte_kfifo.c new file mode 100755 index 0000000..97efa2d --- /dev/null +++ b/MBL/source_ns/drivers/CMT2310/1_Middleware/Kfifo/ebyte_kfifo.c @@ -0,0 +1,107 @@ + +/* Includes ------------------------------------------------------------------*/ +#include "ebyte_kfifo.h" + +uint8_t Ebyte_FIFO_Init( Ebyte_FIFO_t *fifo, uint16_t size ) +{ + uint8_t result = 0; + + if( ( size & ( size - 1 ) ) != 0 ) //Warning ! Size must be 2^n ! Please view linux kfifo + { + result = 1; + } + + fifo->size = size; + fifo->in = 0; + fifo->out = 0; + return result; +} + +uint8_t Ebyte_FIFO_Write( Ebyte_FIFO_t *fifo, uint8_t *pData, uint16_t length ) +{ + uint8_t result = 0; + + uint32_t i, j; + uint16_t endLength, orgLength; + uint8_t *pFifoBuffer; + + orgLength = length; + /* calculate the length of data that can be written */ + length = MIN( length, fifo->size - fifo->in + fifo->out ); + /* first put the data starting from fifo->in to buffer end */ + endLength = MIN( length, fifo->size - ( fifo->in & ( fifo->size - 1 ) ) ); + pFifoBuffer = fifo->buffer + ( fifo->in & ( fifo->size - 1 ) ); + for( i = 0; i < endLength; i++ ) + { + *( pFifoBuffer++ ) = *( pData++ ); + } + /* then put the rest (if any) at the beginning of the buffer */ + j = length - endLength; + if ( j > 0 ) + { + pFifoBuffer = fifo->buffer; + + for( i = 0; i < j; i++ ) + { + *( pFifoBuffer++ ) = *( pData++ ); + } + } + + fifo->in += length; + if( length < orgLength ) + { + result = 1; // Means fifo is full , some data can not be written in + } + return result; +} + +uint8_t Ebyte_FIFO_Read( Ebyte_FIFO_t *fifo, uint8_t *pData, uint16_t length ) +{ + uint8_t result = 0; + uint16_t i, j; + uint16_t endLength, orgLength; + uint8_t *pFifoBuffer; + + orgLength = length; + length = MIN( length, fifo->in - fifo->out ); + /* first get the data from fifo->out until the end of the buffer */ + endLength = MIN( length, fifo->size - ( fifo->out & ( fifo->size - 1 ) ) ); + pFifoBuffer = fifo->buffer + ( fifo->out & ( fifo->size - 1 ) ); + for( i = 0; i < endLength; i++ ) + { + *( pData++ ) = *( pFifoBuffer++ ); + } + /* then get the rest (if any) from the beginning of the buffer */ + j = length - endLength; + if ( j > 0 ) + { + pFifoBuffer = fifo->buffer; + + for( i = 0; i < j; i++ ) + { + *( pData++ ) = *( pFifoBuffer++ ) ; + } + } + fifo->out += length; + if( length < orgLength ) + { + result = 1; // not enough data + } + return result; +} + +uint8_t Ebyte_FIFO_GetDataLength( Ebyte_FIFO_t *fifo, uint16_t *pLength ) +{ + uint8_t result = 0; + *pLength = ( fifo->in - fifo->out ); + return result; +} + +uint8_t Ebyte_FIFO_Clear( Ebyte_FIFO_t *fifo ) +{ + uint8_t result = 0; + fifo->in = 0; + fifo->out = 0; + return result; +} + diff --git a/MBL/source_ns/drivers/CMT2310/1_Middleware/Kfifo/ebyte_kfifo.h b/MBL/source_ns/drivers/CMT2310/1_Middleware/Kfifo/ebyte_kfifo.h new file mode 100755 index 0000000..28ed230 --- /dev/null +++ b/MBL/source_ns/drivers/CMT2310/1_Middleware/Kfifo/ebyte_kfifo.h @@ -0,0 +1,19 @@ +#include "board.h" + +#define MIN(a, b) (((a) < (b)) ? (a) : (b)) +#define EBYTE_FIFO_SIZE 64 // Warning ! Size must be 2^n ! Please view linux kfifo + +typedef struct +{ + uint32_t in; + uint32_t out; + uint32_t size; + uint8_t buffer[EBYTE_FIFO_SIZE]; + +} Ebyte_FIFO_t; + +uint8_t Ebyte_FIFO_Init( Ebyte_FIFO_t *fifo, uint16_t size ); +uint8_t Ebyte_FIFO_Write( Ebyte_FIFO_t *fifo, uint8_t *pData, uint16_t length ); +uint8_t Ebyte_FIFO_GetDataLength( Ebyte_FIFO_t *fifo, uint16_t *pLength ); +uint8_t Ebyte_FIFO_Read( Ebyte_FIFO_t *fifo, uint8_t *pData, uint16_t length ); +uint8_t Ebyte_FIFO_Clear( Ebyte_FIFO_t *fifo ); diff --git a/MBL/source_ns/drivers/CMT2310/1_Middleware/Produce/ebyte_debug.c b/MBL/source_ns/drivers/CMT2310/1_Middleware/Produce/ebyte_debug.c new file mode 100755 index 0000000..17d503e --- /dev/null +++ b/MBL/source_ns/drivers/CMT2310/1_Middleware/Produce/ebyte_debug.c @@ -0,0 +1,122 @@ +/** + ********************************************************************************** + * @file board.c + * @brief E15-EVB02 检测模式 + * @details 详情请参见 https://www.ebyte.com/ + * @author JiangHeng + * @date 2021-05-20 + * @version 1.0.0 + ********************************************************************************** + * @copyright BSD License + * 成都亿佰特电子科技有限公司 + * ______ ____ __ __ _______ ______ + * | ____| | _ \ \ \ / / |__ __| | ____| + * | |__ | |_) | \ \_/ / | | | |__ + * | __| | _ < \ / | | | __| + * | |____ | |_) | | | | | | |____ + * |______| |____/ |_| |_| |______| + * + ********************************************************************************** + */ + +#include "ebyte_core.h" +#include "ebyte_debug.h" + +extern unsigned char PC_isConnected; + +const unsigned char SimulatedCommandsButton1[5] = { EBYTE_CMD_PACKAGE_START, + EBYTE_CMD_PACKAGE_START, + EBYTE_CMD_PACKAGE_START, + EBYTE_CMD_TEST_BUTTON, + 0x01 + }; + +const unsigned char SimulatedCommandsButton2[5] = { EBYTE_CMD_PACKAGE_START, + EBYTE_CMD_PACKAGE_START, + EBYTE_CMD_PACKAGE_START, + EBYTE_CMD_TEST_BUTTON, + 0x02 + }; +const unsigned char SimulatedCommandsWireless1[5] = { EBYTE_CMD_PACKAGE_START, + EBYTE_CMD_PACKAGE_START, + EBYTE_CMD_PACKAGE_START, + EBYTE_CMD_TEST_WIRELESS, + 0x01 + }; +const unsigned char SimulatedCommandsWireless2[5] = { EBYTE_CMD_PACKAGE_START, + EBYTE_CMD_PACKAGE_START, + EBYTE_CMD_PACKAGE_START, + EBYTE_CMD_TEST_WIRELESS, + 0x02 + }; + + +/* ! + * @brief 测试命令检查 + * + * @param rxBuffer 可能含有命令的数据包 + * @param length rxBuffer数据长度 + * @param txBuffer 响应数据包 长度>10 + * @param tLength 响应数据包长度 + * @return 0:未检测到命令 1:检测到了命令 + */ +unsigned char Ebyte_DEBUG_CommandEcho( unsigned char *rxBuffer , unsigned char length, unsigned char *txBuffer, unsigned char *tLength) +{ + unsigned char result = 0; + unsigned char *p; + unsigned char tmp,version; + unsigned long name; + + /* 只关心固定长度为10的数据帧 间隔时间长 粘包几率很小*/ + if( length == EBYTE_CMD_PACKAGE_LENGTH ) + { + p = rxBuffer; + + if( *p++== EBYTE_CMD_PACKAGE_START && *p++== EBYTE_CMD_PACKAGE_START && *p++== EBYTE_CMD_PACKAGE_START) + { + /* 数据体第一字节 指令码 */ + tmp = *p; + switch( tmp ) + { + case EBYTE_CMD_TEST_MODE: + + name = Ebyte_RF.GetName(); + version = Ebyte_RF.GetDriverVersion(); + + *txBuffer++ = EBYTE_CMD_PACKAGE_START; + *txBuffer++ = EBYTE_CMD_PACKAGE_START; + *txBuffer++ = EBYTE_CMD_PACKAGE_START; + *txBuffer++ = EBYTE_CMD_TEST_MODE; + *txBuffer++ = (unsigned char)(name>>24); + *txBuffer++ = (unsigned char)(name>>16); + *txBuffer++ = (unsigned char)(name>>8); + *txBuffer++ = (unsigned char)(name); + *txBuffer++ = version; + + *tLength = EBYTE_CMD_PACKAGE_LENGTH; + PC_isConnected = 1; //模式变更 + break; + case EBYTE_CMD_TEST_BUTTON: + *txBuffer++ = EBYTE_CMD_PACKAGE_START; + *txBuffer++ = EBYTE_CMD_PACKAGE_START; + *txBuffer++ = EBYTE_CMD_PACKAGE_START; + *txBuffer++ = EBYTE_CMD_TEST_BUTTON; + *txBuffer = *++p; + *tLength = EBYTE_CMD_PACKAGE_LENGTH; + break; + case EBYTE_CMD_TEST_WIRELESS: + *txBuffer++ = EBYTE_CMD_PACKAGE_START; + *txBuffer++ = EBYTE_CMD_PACKAGE_START; + *txBuffer++ = EBYTE_CMD_PACKAGE_START; + *txBuffer++ = EBYTE_CMD_TEST_WIRELESS; + *txBuffer = *++p; + *tLength = EBYTE_CMD_PACKAGE_LENGTH; + break; + } + + result = 1; + } + } + + return result; +} \ No newline at end of file diff --git a/MBL/source_ns/drivers/CMT2310/1_Middleware/Produce/ebyte_debug.h b/MBL/source_ns/drivers/CMT2310/1_Middleware/Produce/ebyte_debug.h new file mode 100755 index 0000000..2252798 --- /dev/null +++ b/MBL/source_ns/drivers/CMT2310/1_Middleware/Produce/ebyte_debug.h @@ -0,0 +1,14 @@ + + +#define EBYTE_CMD_PACKAGE_START 0xC5 +#define EBYTE_CMD_PACKAGE_LENGTH 0x0A +#define EBYTE_CMD_TEST_MODE 0x01 +#define EBYTE_CMD_TEST_BUTTON 0x02 +#define EBYTE_CMD_TEST_WIRELESS 0x03 + +extern const unsigned char SimulatedCommandsButton1[5]; +extern const unsigned char SimulatedCommandsButton2[5]; +extern const unsigned char SimulatedCommandsWireless1[5]; +extern const unsigned char SimulatedCommandsWireless2[5]; + +unsigned char Ebyte_DEBUG_CommandEcho( unsigned char *rxBuffer , unsigned char length, unsigned char *txBuffer, unsigned char *tLength); \ No newline at end of file diff --git a/MBL/source_ns/drivers/CMT2310/2_Ebyte_Board_Support/E15-EVB02/board.c b/MBL/source_ns/drivers/CMT2310/2_Ebyte_Board_Support/E15-EVB02/board.c new file mode 100755 index 0000000..236e595 --- /dev/null +++ b/MBL/source_ns/drivers/CMT2310/2_Ebyte_Board_Support/E15-EVB02/board.c @@ -0,0 +1,340 @@ +/** + ********************************************************************************** + * @file board.c + * @brief E15-EVB02 板级软件驱动层 + * @details 详情请参见 https://www.ebyte.com/ + * @author JiangHeng + * @date 2021-05-06 + * @version 1.0.0 + ********************************************************************************** + * @copyright BSD License + * 成都亿佰特电子科技有限公司 + * ______ ____ __ __ _______ ______ + * | ____| | _ \ \ \ / / |__ __| | ____| + * | |__ | |_) | \ \_/ / | | | |__ + * | __| | _ < \ / | | | __| + * | |____ | |_) | | | | | | |____ + * |______| |____/ |_| |_| |______| + * + ********************************************************************************** + */ + +#include "board.h" +#include "ebyte_port.h" +#include "ebyte_conf.h" +#include "gd32w51x_gpio.h" +#include "platform_def.h" + +BSP_BTN_FIFO_t BSP_BTN_FIFO; + + +/*!< @brief 辅助延时计算 用于定时器中断 递减 */ +volatile uint32_t Ebyte_TimerDelayCounter = 0; + +/* ! + * @brief 内部时钟初始化 + */ +void Ebyte_BSP_HSI_Init(void) +{ +// /* 内部 16M HSI 时钟 */ +// CLK_SYSCLKSourceConfig( CLK_SYSCLKSource_HSI ); +// +// /* 1分频 16M/1 */ +// CLK_SYSCLKDivConfig( CLK_SYSCLKDiv_1 ); +} + + +void Ebyte_BSP_E48xGPIO_Init(void) +{ + rcu_periph_clock_enable(BSP_GPIO_RCU_E48_GPIO); + + gpio_mode_set( BSP_GPIO_PORT_E48_GP0, GPIO_MODE_INPUT, GPIO_PUPD_PULLUP, BSP_GPIO_PIN_E48_GP0); + gpio_mode_set( BSP_GPIO_PORT_E48_NIRQ, GPIO_MODE_INPUT, GPIO_PUPD_PULLUP, BSP_GPIO_PIN_E48_NIRQ); + gpio_mode_set( BSP_GPIO_PORT_E48_GP3, GPIO_MODE_INPUT, GPIO_PUPD_PULLUP, BSP_GPIO_PIN_E48_GP3); + gpio_mode_set( BSP_GPIO_PORT_E48_GP4, GPIO_MODE_INPUT, GPIO_PUPD_NONE, BSP_GPIO_PIN_E48_GP4); + gpio_mode_set( BSP_GPIO_PORT_E48_GP5, GPIO_MODE_INPUT, GPIO_PUPD_PULLUP, BSP_GPIO_PIN_E48_GP5); +} +/* ! + * @brief 初始化所有IO + * + * @note 目标硬件: EBYTE E15-EVB02 + */ +void Ebyte_BSP_GPIO_Init(void) +{ + /* 无线模块状态控制 */ + Ebyte_BSP_E48xGPIO_Init(); + + /* LED */ + rcu_periph_clock_enable(BSP_GPIO_RCU_E48_LED); + gpio_mode_set( BSP_GPIO_PORT_LED_1, GPIO_MODE_OUTPUT, GPIO_PUPD_PULLUP, BSP_GPIO_PIN_LED_1 ); + gpio_mode_set( BSP_GPIO_PORT_LED_2, GPIO_MODE_OUTPUT, GPIO_PUPD_PULLUP, BSP_GPIO_PIN_LED_2 ); + gpio_output_options_set(BSP_GPIO_PORT_LED_1, GPIO_OTYPE_PP, GPIO_OSPEED_25MHZ, BSP_GPIO_PIN_LED_1); + gpio_output_options_set(BSP_GPIO_PORT_LED_2, GPIO_OTYPE_PP, GPIO_OSPEED_25MHZ, BSP_GPIO_PIN_LED_2); + + /* Button */ + rcu_periph_clock_enable(BSP_GPIO_RCU_E48_BUTTON); + gpio_mode_set( BSP_GPIO_PORT_BUTTON_1, GPIO_MODE_INPUT, GPIO_PUPD_PULLUP, BSP_GPIO_PIN_BUTTON_1); +// GPIO_Init( BSP_GPIO_PORT_BUTTON_2, BSP_GPIO_PIN_BUTTON_2, GPIO_Mode_In_PU_No_IT ); +} + +/* ! + * @brief 通信串口初始化 + * + * @note 请注意，不同的MCU可能无需端口映射 + */ +void Ebyte_BSP_UART_Init( void ) +{ +// /* 时钟 */ +// CLK_PeripheralClockConfig( BSP_USER_UART_CLOCK, ENABLE); +// +// /* GPIO */ +// GPIO_ExternalPullUpConfig( BSP_GPIO_PORT_UART_TX, BSP_GPIO_PIN_UART_TX, ENABLE ); +// GPIO_ExternalPullUpConfig( BSP_GPIO_PORT_UART_RX, BSP_GPIO_PIN_UART_RX, ENABLE ); +// +// /* 端口重映射 */ +// SYSCFG_REMAPPinConfig( REMAP_Pin_USART1TxRxPortA, ENABLE ); +// +// /* 基础参数配置 E15-EVB02默认波特率9600 8N1 */ +// USART_Init( BSP_USER_UART, BSP_USER_UART_BAUDRATE, USART_WordLength_8b, USART_StopBits_1, BSP_USER_UART_PARITY, (USART_Mode_TypeDef)(USART_Mode_Rx | USART_Mode_Tx ));//允许接收和发送 +// +// /* 打开接收中断 */; +// USART_ITConfig( BSP_USER_UART, USART_IT_RXNE, ENABLE ); +// +// /* 串口 使能 */ +// USART_Cmd( BSP_USER_UART, ENABLE); +} + +void Ebyte_BSP_ThreeLinesSPI_Init() +{ + /* 合并到了E49 GPIO初始化中 */ +} + +/* ! + * @brief 无线模块通信SPI接口初始化函数 + */ +void Ebyte_BSP_SPI_Init( void ) +{ + spi_parameter_struct spi_init_struct; + + /* 时钟 */ + rcu_periph_clock_enable(BSP_RF_SPI_CLOCK); + rcu_periph_clock_enable(BSP_GPIO_RCU_E48_SPI); + + /* SPI1 GPIO config: SCK/PB13, MISO/PB14, MOSI/PB15 */ + gpio_af_set(BSP_GPIO_PORT_SPI, GPIO_AF_5, GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15); + gpio_mode_set(BSP_GPIO_PORT_SPI, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15); + gpio_output_options_set(BSP_GPIO_PORT_SPI, GPIO_OTYPE_PP, GPIO_OSPEED_10MHZ, GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15); + + /* SPI0_NSS */ + gpio_mode_set(BSP_GPIO_PORT_SPI, GPIO_MODE_OUTPUT, GPIO_PUPD_PULLUP, BSP_GPIO_PIN_SPI_NSS); //片选 CS + gpio_output_options_set(BSP_GPIO_PORT_SPI, GPIO_OTYPE_PP, GPIO_OSPEED_25MHZ, BSP_GPIO_PIN_SPI_NSS); + +// GPIO_ExternalPullUpConfig( BSP_GPIO_PORT_SPI_SCK, BSP_GPIO_PIN_SPI_MOSI | BSP_GPIO_PIN_SPI_MISO | BSP_GPIO_PIN_SPI_SCK, ENABLE); // MOSI MISO SCK + + /* 参数配置 */ + spi_init_struct.trans_mode = SPI_TRANSMODE_FULLDUPLEX; + spi_init_struct.device_mode = SPI_MASTER; //主机模式 + spi_init_struct.frame_size = SPI_FRAMESIZE_8BIT; + spi_init_struct.clock_polarity_phase = SPI_CK_PL_LOW_PH_1EDGE; // Mode0 {CPOL=0, CPHA=0} + spi_init_struct.nss = SPI_NSS_SOFT; //软件控制从机CS片选 + spi_init_struct.prescale = SPI_PSC_8; //16M/2 SCK速率 + spi_init_struct.endian = SPI_ENDIAN_MSB; //从高位开始传输 + spi_init(BSP_RF_SPI, &spi_init_struct); + + /* 使能 */ + /* SPI enable */ + spi_enable(BSP_RF_SPI); +} + +/* ! + * @brief RF模块SPI通信收/发函数 + * + * @param data 发送数据 + * @return 接收数据 + * @note stm8l SPI库函数中的SPI_SendData()/SPI_ReceiveData() 不能直接使用 + */ +uint8_t Ebyte_BSP_SpiTransAndRecv( uint8_t data ) +{ + while(RESET == spi_i2s_flag_get(BSP_RF_SPI, SPI_FLAG_TBE)); + spi_i2s_data_transmit(BSP_RF_SPI, data); + + while(RESET == spi_i2s_flag_get(BSP_RF_SPI, SPI_FLAG_RBNE)); + return spi_i2s_data_receive(BSP_RF_SPI); + +// BSP_RF_SPI->DR = data; +// while ((BSP_RF_SPI->SR & SPI_FLAG_TXE) == RESET); +// +// while ((BSP_RF_SPI->SR & SPI_FLAG_RXNE) == RESET); +// return BSP_RF_SPI->DR; +} + +/* ! + * @brief 定时器初始化 + * + * @note 使用了TIM3产生1ms周期性中断 + * TIM3的主时钟为HSI 16MHz, 128分频即为 16 MHz / 128 = 125 000 Hz + * 目标定时1ms 计数周期即为 ( 0.001 x 125000 - 1) = 124 + */ +void Ebyte_BSP_TIMER_Init( void ) +{ + timer_parameter_struct timer_initpara; + /** + TIMER2 Configuration: + TIMER2CLK = SystemCoreClock/180 = 1MHz. + TIMER2 configuration is timing mode, and the timing is 1ms(1000/1 = 1ms). + */ + + /* enable the peripherals clock */ + rcu_timer_clock_prescaler_config(RCU_TIMER_PSC_MUL4); + rcu_periph_clock_enable(BSP_RF_TIMER_RCU); + + /* deinit a TIMER */ + timer_deinit(BSP_RF_TIMER); + /* initialize TIMER init parameter struct */ + timer_struct_para_init(&timer_initpara); + /* TIMER2 configuration */ + timer_initpara.prescaler = 179; + timer_initpara.alignedmode = TIMER_COUNTER_EDGE; + timer_initpara.counterdirection = TIMER_COUNTER_UP; + timer_initpara.period = 1000; + timer_initpara.clockdivision = TIMER_CKDIV_DIV1; + timer_init(BSP_RF_TIMER, &timer_initpara); + + /* clear interrupt bit */ + timer_interrupt_flag_clear(BSP_RF_TIMER, TIMER_INT_FLAG_UP); + /* enable the TIMER interrupt */ + timer_interrupt_enable(BSP_RF_TIMER, TIMER_INT_UP); + /* enable a TIMER */ + timer_enable(BSP_RF_TIMER); + + nvic_irq_enable(TIMER2_IRQn, 0, 0); +} + +/* ! + * @brief E15-EVB02 板载资源初始化 + * + * @note 内部时钟HSI x 16MHz + * 用户通信串口 x USART1 + * 无线模块通信接口 x SPI1 + * 定时器 x TIM3 + * 按键 x 2 + * 指示灯 x 2 + */ +void Ebyte_BSP_Init( void ) +{ + /* 时钟 初始化 */ +// Ebyte_BSP_HSI_Init(); + + /* IO 初始化 */ + Ebyte_BSP_GPIO_Init(); + + /* 串口 初始化 */ +// Ebyte_BSP_UART_Init(); + + /* SPI接口 初始化 */ + Ebyte_BSP_SPI_Init(); + + /* 定时器 初始化 */ + Ebyte_BSP_TIMER_Init(); + + /* 按键事件队列 初始化 */ + Ebyte_BTN_FIFO_Init( &BSP_BTN_FIFO ); +} + +/* ! + * @brief 控制LED 开/关/翻转 + * + * @param LEDx 板载两颗发光二极管 + * @arg BSP_LED_1 : LED1 + * @arg BSP_LED_2 : LED2 + * + * @param ctl 开 / 关 + * @arg OFF : 关 + * @arg ON : 开 + * @arg TOGGLE : 翻转 + */ +void Ebyte_BSP_LedControl( BSP_LED_t LEDx , BSP_LED_Ctl_t ctl) +{ + if( TOGGLE == ctl ) + { + switch( LEDx ) + { + case BSP_LED_1 : gpio_bit_toggle( BSP_GPIO_PORT_LED_1, BSP_GPIO_PIN_LED_1); break; + case BSP_LED_2 : gpio_bit_toggle( BSP_GPIO_PORT_LED_2, BSP_GPIO_PIN_LED_2); break; + default: break; + } + } + else + { + switch( LEDx ) + { + case BSP_LED_1 : gpio_bit_write( BSP_GPIO_PORT_LED_1, BSP_GPIO_PIN_LED_1, (BitAction)ctl); break; + case BSP_LED_2 : gpio_bit_write( BSP_GPIO_PORT_LED_2, BSP_GPIO_PIN_LED_2, (BitAction)ctl); break; + default: break; + } + } + +} + + +/* ! + * @brief 基于定时器的毫秒延时函数 + * + * @param nTime 单位:毫秒 + */ +void Ebyte_BSP_DelayMs( volatile uint32_t nTime ) +{ + Ebyte_TimerDelayCounter = nTime; + + while( Ebyte_TimerDelayCounter !=0 ); +} + +/* ! + * @brief 辅助毫秒延时计算 定时器中断调用 + */ +void Ebyte_BSP_TimerDecrement(void) +{ + if( Ebyte_TimerDelayCounter != 0 ) + { + Ebyte_TimerDelayCounter--; + } +} + + +/* ! + * @brief 读取按键状态 + * + * @param btn 对应的按键编号 + * @arg BSP_BUTTON_1 :按键1 + * @arg BSP_BUTTON_2 :按键2 + * @return 0:按键被按下 非0:按键未按下 + * @note 板载按键未按下时 IO处于上拉状态 即为1；按下后IO接地 即为0 + */ +uint8_t Ebyte_BSP_ReadButton( BSP_BUTTON_t btn ) +{ + BitStatus result = RESET; + + switch ( btn ) + { + case BSP_BUTTON_1: result = gpio_input_bit_get( BSP_GPIO_PORT_BUTTON_1 , BSP_GPIO_PIN_BUTTON_1); break; +// case BSP_BUTTON_2: result = GPIO_ReadInputDataBit( BSP_GPIO_PORT_BUTTON_2 , BSP_GPIO_PIN_BUTTON_2); break; + default : break; + } + + return result; +} + + +/* ! + * @brief 串口发送函数 + */ +void Ebyte_BSP_UartTransmit( uint8_t *buffer , uint16_t length ) +{ + uint8_t i; + + for( i = 0; i < length; i++ ) { + while(RESET == usart_flag_get(LOG_UART, USART_FLAG_TBE)); + usart_data_transmit(LOG_UART, *buffer); + } +} + diff --git a/MBL/source_ns/drivers/CMT2310/2_Ebyte_Board_Support/E15-EVB02/board.h b/MBL/source_ns/drivers/CMT2310/2_Ebyte_Board_Support/E15-EVB02/board.h new file mode 100755 index 0000000..5996f33 --- /dev/null +++ b/MBL/source_ns/drivers/CMT2310/2_Ebyte_Board_Support/E15-EVB02/board.h @@ -0,0 +1,181 @@ +/** + ********************************************************************************** + * @file board.h + * @brief E15-EVB02 板级软件驱动层 + * @details 详情请参见 https://www.ebyte.com/ + * @author JiangHeng + * @date 2021-05-06 + * @version 1.0.0 + ********************************************************************************** + * @copyright BSD License + * 成都亿佰特电子科技有限公司 + * ______ ____ __ __ _______ ______ + * | ____| | _ \ \ \ / / |__ __| | ____| + * | |__ | |_) | \ \_/ / | | | |__ + * | __| | _ < \ / | | | __| + * | |____ | |_) | | | | | | |____ + * |______| |____/ |_| |_| |______| + * + ********************************************************************************** + */ +#ifndef __EBYTE_BOARD_H__ +#define __EBYTE_BOARD_H__ + +#include +//#include "stm8l15x_conf.h" +#include "gd32w51x.h" +#include "debug_print.h" +#include "board_mini_printf.h" + +/* 引脚配置 LED */ +#define BSP_GPIO_RCU_E48_LED RCU_GPIOB +#define BSP_GPIO_PORT_LED_1 GPIOB +#define BSP_GPIO_PIN_LED_1 GPIO_PIN_6 + +#define BSP_GPIO_PORT_LED_2 GPIOA +#define BSP_GPIO_PIN_LED_2 GPIO_PIN_15 + +/* 引脚配置 按键 */ +#define BSP_GPIO_RCU_E48_BUTTON RCU_GPIOA +#define BSP_GPIO_PORT_BUTTON_1 GPIOA +#define BSP_GPIO_PIN_BUTTON_1 GPIO_PIN_2 + +//#define BSP_GPIO_PORT_BUTTON_2 GPIOA +//#define BSP_GPIO_PIN_BUTTON_2 GPIO_PIN_5 + +/* 引脚配置 SPI通信接口 */ +#define BSP_GPIO_RCU_E48_SPI RCU_GPIOB + +#define BSP_GPIO_PORT_SPI GPIOB +#define BSP_GPIO_PIN_SPI_NSS GPIO_PIN_12 +#define BSP_GPIO_PIN_SPI_SCK GPIO_PIN_13 +#define BSP_GPIO_PIN_SPI_MISO GPIO_PIN_14 +#define BSP_GPIO_PIN_SPI_MOSI GPIO_PIN_15 + +/* 引脚配置 通信串口 */ +#define BSP_GPIO_PORT_UART_TX GPIOA +#define BSP_GPIO_PIN_UART_TX GPIO_PIN_2 + +#define BSP_GPIO_PORT_UART_RX GPIOA +#define BSP_GPIO_PIN_UART_RX GPIO_PIN_3 + +/* 引脚配置 EBYTE无线模块控制 */ + + +/* E48 */ +#define BSP_GPIO_RCU_E48_GPIO RCU_GPIOC + +#define BSP_GPIO_PORT_E48_GP0 GPIOC +#define BSP_GPIO_PIN_E48_GP0 GPIO_PIN_0 +#define BSP_GPIO_PORT_E48_NIRQ GPIOC +#define BSP_GPIO_PIN_E48_NIRQ GPIO_PIN_1 +#define BSP_GPIO_PORT_E48_GP3 GPIOC +#define BSP_GPIO_PIN_E48_GP3 GPIO_PIN_3 +#define BSP_GPIO_PORT_E48_GP4 GPIOC +#define BSP_GPIO_PIN_E48_GP4 GPIO_PIN_4 +#define BSP_GPIO_PORT_E48_GP5 GPIOC +#define BSP_GPIO_PIN_E48_GP5 GPIO_PIN_5 + +/* 参数配置 SPI */ +#define BSP_RF_SPI SPI1 +#define BSP_RF_SPI_CLOCK RCU_SPI1 +#define Ebyte_BSP_RfSpiSelected() gpio_bit_write( BSP_GPIO_PORT_SPI, BSP_GPIO_PIN_SPI_NSS, RESET ) +#define Ebyte_BSP_RfSpiUnselected() gpio_bit_write( BSP_GPIO_PORT_SPI, BSP_GPIO_PIN_SPI_NSS, SET ) + +/* 配置 Timer */ +#define BSP_RF_TIMER TIMER2 +#define BSP_RF_TIMER_RCU RCU_TIMER2 + +/* 参数配置 无线模块控制IO */ + +///* E07 */ +//#define Ebyte_BSP_RfBusyIoRead() gpio_input_bit_get( BSP_GPIO_PORT_BUSY , BSP_GPIO_PIN_BUSY) +//#define Ebyte_BSP_RfGdo0IoRead() gpio_input_bit_get( BSP_GPIO_PORT_E07_GDO0 , BSP_GPIO_PIN_E07_GDO0) +//#define Ebyte_BSP_RfGdo1IoRead() gpio_input_bit_get( BSP_GPIO_PORT_E07_GDO1 , BSP_GPIO_PIN_E07_GDO1) +///* E10 */ +//#define Ebyte_BSP_E10IrqIoRead() gpio_input_bit_get( BSP_GPIO_PORT_E10_IRQ , BSP_GPIO_PIN_E10_IRQ) +//#define Ebyte_BSP_E10Dio2Read() gpio_input_bit_get( BSP_GPIO_PORT_E10_DIO2 , BSP_GPIO_PIN_E10_DIO2) +//#define Ebyte_BSP_E10Dio3Read() gpio_input_bit_get( BSP_GPIO_PORT_E10_DIO3 , BSP_GPIO_PIN_E10_DIO3) +//#define Ebyte_BSP_E10SdnIoLow() gpio_bit_write( BSP_GPIO_PORT_E10_SDN , BSP_GPIO_PIN_E10_SDN, RESET ) +//#define Ebyte_BSP_E10SdnIoHigh() gpio_bit_write( BSP_GPIO_PORT_E10_SDN , BSP_GPIO_PIN_E10_SDN, SET ) +///* E49 */ +//#define Ebyte_BSP_E49Dio1IoRead() gpio_input_bit_get( BSP_GPIO_PORT_E49_DIO1 , BSP_GPIO_PIN_E49_DIO1) +//#define Ebyte_BSP_E49Dio2IoRead() gpio_input_bit_get( BSP_GPIO_PORT_E49_DIO2 , BSP_GPIO_PIN_E49_DIO2) +//#define Ebyte_BSP_E49FcsbIoLow() gpio_bit_write( BSP_GPIO_PORT_E49_FCSB , BSP_GPIO_PIN_E49_FCSB, RESET ) +//#define Ebyte_BSP_E49FcsbIoHigh() gpio_bit_write( BSP_GPIO_PORT_E49_FCSB , BSP_GPIO_PIN_E49_FCSB, SET ) +//#define Ebyte_BSP_E49CsbIoLow() gpio_bit_write( BSP_GPIO_PORT_E49_CSB , BSP_GPIO_PIN_E49_CSB, RESET ) +//#define Ebyte_BSP_E49CsbIoHigh() gpio_bit_write( BSP_GPIO_PORT_E49_CSB , BSP_GPIO_PIN_E49_CSB, SET ) +//#define Ebyte_BSP_E49SlckIoLow() gpio_bit_write( BSP_GPIO_PORT_E49_SLCK , BSP_GPIO_PIN_E49_SLCK, RESET ) +//#define Ebyte_BSP_E49SlckIoHigh() gpio_bit_write( BSP_GPIO_PORT_E49_SLCK , BSP_GPIO_PIN_E49_SLCK, SET ) +//#define Ebyte_BSP_E49SdioIoLow() gpio_bit_write( BSP_GPIO_PORT_E49_SDIO , BSP_GPIO_PIN_E49_SDIO, RESET ) +//#define Ebyte_BSP_E49SdioIoHigh() gpio_bit_write( BSP_GPIO_PORT_E49_SDIO , BSP_GPIO_PIN_E49_SDIO, SET ) +//#define Ebyte_BSP_E49SdioIoOutput() gpio_mode_set( BSP_GPIO_PORT_E49_SDIO, BSP_GPIO_PIN_E49_SDIO, GPIO_Mode_Out_PP_High_Fast ) +//#define Ebyte_BSP_E49SdioIoInput() GPIO_Init( BSP_GPIO_PORT_E49_SDIO, BSP_GPIO_PIN_E49_SDIO, GPIO_Mode_In_FL_No_IT ) +//#define Ebyte_BSP_E49SdioIoRead() GPIO_ReadInputDataBit( BSP_GPIO_PORT_E49_SDIO , BSP_GPIO_PIN_E49_SDIO) + +/* E48 */ +#define Ebyte_BSP_E48GPIO4Read() gpio_input_bit_get( BSP_GPIO_PORT_E48_GP4 , BSP_GPIO_PIN_E48_GP4) + +/* 全局中断 */ +#define Ebyte_BSP_GlobalIntEnable() __enable_irq() +#define Ebyte_BSP_GlobalIntDisable() __disable_irq() + +/* 参数配置 UART */ +#define BSP_USER_UART USART1 +#define BSP_USER_UART_CLOCK CLK_Peripheral_USART1 +#define BSP_USER_UART_BAUDRATE 9600 //波特率 +#define BSP_USER_UART_PARITY USART_Parity_No //USART_Parity_No:无校验 USART_Parity_Even:奇校验 USART_Parity_Odd:偶校验 +#define BSP_USER_UART_IRQ USART1_RX_IRQn //中断类型 +#define BSP_USER_UART_IRQ_LEVEL ITC_PriorityLevel_2 //优先级 + + +/* 参数配置 按键事件队列 */ +#define BSP_BTN_FIFO_LENGTH 16 + +/* 参数配置 调试打印信息 关闭打印需要注释掉宏定义 EBYTE_DEBUG */ +#define EBYTE_DEBUG + +#ifdef EBYTE_DEBUG +#define DEBUG(format, ...) mprintf(format, ##__VA_ARGS__) +#else +#define DEBUG(...) +#endif + +typedef enum { BSP_LED_1 = 0, BSP_LED_2 } BSP_LED_t; +typedef enum { OFF = 0, ON , TOGGLE} BSP_LED_Ctl_t; +typedef enum { UART_8N1 = 0, UART_8O1, UART_8E1 } BSP_UART_Parity_t; + +typedef enum { BSP_BUTTON_1 = 0, BSP_BUTTON_2 } BSP_BUTTON_t; +typedef enum +{ + BTN_1_SHORT, //按键1 短按 + BTN_1_LONG, //按键1 长按 + BTN_2_SHORT, //按键2 短按 + BTN_2_LONG, //按键2 长按 +}BSP_BTN_EVENT_t; + +typedef struct +{ + uint8_t fifoLen ; + uint8_t fifoRead ; + uint8_t fifoWrite ; + uint8_t buff[BSP_BTN_FIFO_LENGTH]; +}BSP_BTN_FIFO_t; + +extern BSP_BTN_FIFO_t BSP_BTN_FIFO; + +void Ebyte_BSP_Init( void ); +void Ebyte_BTN_FIFO_Init(BSP_BTN_FIFO_t *fifo); +void Ebyte_BSP_DelayMs( volatile uint32_t nTime ); +void Ebyte_BSP_TimerDecrement(void); +void Ebyte_BSP_LedControl( BSP_LED_t LEDx , BSP_LED_Ctl_t ctl); +void Ebyte_BSP_UartTransmit( uint8_t *buffer , uint16_t length ); + +uint8_t Ebyte_BSP_ReadButton( BSP_BUTTON_t btn ); +uint8_t Ebyte_BSP_SpiTransAndRecv( uint8_t data ); + +uint8_t Ebyte_BTN_FIFO_Push(BSP_BTN_FIFO_t *fifo, BSP_BTN_EVENT_t event); +uint8_t Ebyte_BTN_FIFO_Pop(BSP_BTN_FIFO_t *fifo, BSP_BTN_EVENT_t *event); +uint32_t Ebyte_BSP_TimerGetTick(void); + +#endif // !__EBYTE_BOARD_H__ \ No newline at end of file diff --git a/MBL/source_ns/drivers/CMT2310/2_Ebyte_Board_Support/E15-EVB02/board_button.c b/MBL/source_ns/drivers/CMT2310/2_Ebyte_Board_Support/E15-EVB02/board_button.c new file mode 100755 index 0000000..6cfa8e4 --- /dev/null +++ b/MBL/source_ns/drivers/CMT2310/2_Ebyte_Board_Support/E15-EVB02/board_button.c @@ -0,0 +1,147 @@ +/** + ********************************************************************************** + * @file board_button.c + * @brief 通用 按键队列驱动库 + * @author JiangHeng + * @date 2021-05-06 + * @version 1.0.0 + ********************************************************************************** + * @copyright BSD License + * 成都亿佰特电子科技有限公司 + * ______ ____ __ __ _______ ______ + * | ____| | _ \ \ \ / / |__ __| | ____| + * | |__ | |_) | \ \_/ / | | | |__ + * | __| | _ < \ / | | | __| + * | |____ | |_) | | | | | | |____ + * |______| |____/ |_| |_| |______| + * + ********************************************************************************** + */ + +#include "board.h" +#include "ebyte_kfifo.h" +#include "ebyte_core.h" + +static uint16_t Button1_TickCounter = 0; +static uint16_t Button2_TickCounter = 0; + +extern Ebyte_FIFO_t hfifo; +extern uint8_t FIFO_isTimeCheckReady; +static uint32_t FIFO_TickCounter = 0; + +/* Private function prototypes -----------------------------------------------*/ +void IT_Timer_ButtonCheck(void); + + +/* ! + * @brief 按键队列初始化 + * + * @param fifo 指向按键事件队列结构体的指针 + */ +void Ebyte_BTN_FIFO_Init(BSP_BTN_FIFO_t *fifo) +{ + fifo->fifoLen = 0; + fifo->fifoRead = 0; + fifo->fifoWrite = 0; +} + +/* ! + * @brief 按键队列入队 + * + * @param fifo 指向按键事件队列结构体的指针 + * @param event 按键的事件 主要为各按键的短按/长按 + * @return 0:正常 1:队列溢出 + * @note 入队位置可循环但不会覆盖已入队数据，队满时会导致数据丢失！ + */ +uint8_t Ebyte_BTN_FIFO_Push(BSP_BTN_FIFO_t *fifo, BSP_BTN_EVENT_t event) +{ + /* 入队数据包长度预先自增 */ + fifo->fifoLen++; + + /* 如果入队长度大于了设定长度 */ + if(fifo->fifoLen > BSP_BTN_FIFO_LENGTH) + { + fifo->fifoLen = BSP_BTN_FIFO_LENGTH;//入队长度不再增加 + return 1; + } + + /* 正常入队 */ + fifo->buff[fifo->fifoWrite] = event; + + /* 如果入队位置已经到了队尾 */ + if(++fifo->fifoWrite >= BSP_BTN_FIFO_LENGTH) + { + fifo->fifoWrite = 0; //那么下一个入队数据将回到队首开始入队 + } + + return 0; + +} + +/* ! + * @brief 按键队列出队 + * + * @param fifo 指向按键事件队列结构体的指针 + * @param event 按键的事件 主要为各按键的短按/长按 + * @return 0:正常 1:队列为空 + */ +uint8_t Ebyte_BTN_FIFO_Pop(BSP_BTN_FIFO_t *fifo, BSP_BTN_EVENT_t *event) +{ + /* 如果入队长度为0 即空队列 */ + if(fifo->fifoLen == 0) + { + return 1; + } + + /* 入队数据长度自减 */ + fifo->fifoLen--; + + /* 正常出队 */ + *event = (BSP_BTN_EVENT_t )(fifo->buff[fifo->fifoRead]); + + /* 如果出队位置已经到了队尾 */ + if(++fifo->fifoRead >= BSP_BTN_FIFO_LENGTH) + { + fifo->fifoRead = 0;//那么下一次将从队首开始出队 + } + + return 0; +} + +/* ! + * @brief 定时器中断 状态机 辅助按键检测 + */ +void IT_Timer_ButtonCheck(void) +{ + /* 如果按键1被按下 */ + if (!Ebyte_BSP_ReadButton(BSP_BUTTON_1)) { + Button1_TickCounter++; + } else { + if (Button1_TickCounter > 1000) // 1秒 长按 + { + Ebyte_BTN_FIFO_Push(&BSP_BTN_FIFO, BTN_1_LONG); + } else if (Button1_TickCounter > 50) // 50毫秒 短按 + { + Ebyte_BTN_FIFO_Push(&BSP_BTN_FIFO, BTN_1_SHORT); + } else { + } // 50毫秒以下 认为是抖动 不操作 + + Button1_TickCounter = 0; + } + + /* 如果按键2被按下 */ + if (!Ebyte_BSP_ReadButton(BSP_BUTTON_2)) { + Button2_TickCounter++; + } else { + if (Button2_TickCounter > 1000) // 1秒 长按 + { + Ebyte_BTN_FIFO_Push(&BSP_BTN_FIFO, BTN_2_LONG); + } else if (Button2_TickCounter > 50) // 50毫秒 短按 + { + Ebyte_BTN_FIFO_Push(&BSP_BTN_FIFO, BTN_2_SHORT); + } else { + } // 50毫秒以下 认为是抖动 不操作 + + Button2_TickCounter = 0; + } +} diff --git a/MBL/source_ns/drivers/CMT2310/2_Ebyte_Board_Support/E15-EVB02/board_button.h b/MBL/source_ns/drivers/CMT2310/2_Ebyte_Board_Support/E15-EVB02/board_button.h new file mode 100755 index 0000000..53e4b43 --- /dev/null +++ b/MBL/source_ns/drivers/CMT2310/2_Ebyte_Board_Support/E15-EVB02/board_button.h @@ -0,0 +1,6 @@ +#ifndef __BOARD_BUTTON_H__ +#define __BOARD_BUTTON_H__ + +void IT_Timer_ButtonCheck(void); + +#endif // !__BOARD_BUTTON_H__ \ No newline at end of file diff --git a/MBL/source_ns/drivers/CMT2310/2_Ebyte_Board_Support/E15-EVB02/board_mini_printf.c b/MBL/source_ns/drivers/CMT2310/2_Ebyte_Board_Support/E15-EVB02/board_mini_printf.c new file mode 100755 index 0000000..f5e83ae --- /dev/null +++ b/MBL/source_ns/drivers/CMT2310/2_Ebyte_Board_Support/E15-EVB02/board_mini_printf.c @@ -0,0 +1,203 @@ +#include +#include "stdarg.h" +#include "gd32w51x.h" +//#include "stm8l15x_usart.h" +#include "board_mini_printf.h" +#include "platform_def.h" + +/* ! + * @brief 目标硬件串口通信接口 + * + * @param data 写入的数据 1 Byte + */ +static void send_uart_data(uint8_t data) +{ + while(RESET == usart_flag_get(LOG_UART, USART_FLAG_TBE)); + usart_data_transmit(LOG_UART, data); +} + +/* + 功能：将int型数据转为2，8，10，16进制字符串 + 参数：value --- 输入的int整型数 + str --- 存储转换的字符串 + radix --- 进制类型选择 + 注意：8位单片机int字节只占2个字节 +*/ +static char *sky_itoa(int value, char *str, unsigned int radix) +{ + char list[] = "0123456789ABCDEF"; + unsigned int tmp_value; + int i = 0, j, k = 0; +// if (NULL == str) { + if (0 == str) { +// return NULL; + return 0; + } + if (2 != radix && 8 != radix && 10 != radix && 16 != radix) { +// return NULL; + return 0; + } + if (radix == 10 && value < 0) { + //十进制且为负数 + tmp_value = (unsigned int)(0 - value); + str[i++] = '-'; + k = 1; + } else { + tmp_value = (unsigned int)value; + } + //数据转换为字符串，逆序存储 + do { + str[i ++] = list[tmp_value%radix]; + tmp_value /= radix; + } while(tmp_value); + str[i] = '\0'; + //将逆序字符串转换为正序 + char tmp; + for (j = k; j < (i+k)/2; j++) { + tmp = str[j]; + str[j] = str[i-j-1+k]; + str[i-j-1+k] = tmp; + } + return str; +} + +/* + 功能：将double型数据转为字符串 + 参数：value --- 输入的double浮点数 + str --- 存储转换的字符串 + eps --- 保留小数位选择，至少保留一个小数位,至多保留4个小数位 + 注意：8位单片机int字节只占2个字节 +*/ +static void sky_ftoa(double value, char *str, unsigned int eps) +{ + unsigned int integer; + double decimal; + char list[] = "0123456789"; + int i = 0, j, k = 0; + //将整数及小数部分提取出来 + if (value < 0) { + decimal = (double)(((int)value) - value); + integer = (unsigned int)(0 - value); + str[i ++] = '-'; + k = 1; + } else { + integer = (unsigned int)(value); + decimal = (double)(value - integer); + } + //整数部分数据转换为字符串，逆序存储 + do { + str[i ++] = list[integer%10]; + integer /= 10; + } while(integer); + str[i] = '\0'; + //将逆序字符串转换为正序 + char tmp; + for (j = k; j < (i+k)/2; j++) { + tmp = str[j]; + str[j] = str[i-j-1+k]; + str[i-j-1+k] = tmp; + } + //处理小数部分 + if (eps < 1 || eps > 4) { + eps = 4; + } + + //精度问题，防止输入1.2输出1.19等情况 + double pp = 0.1; + for (j = 0; j <= eps; j++) { + pp *= 0.1; + } + decimal += pp; + while (eps) { + decimal *= 10; + eps --; + } + int tmp_decimal = (int)decimal; + str[i ++] = '.'; + k = i; + //整数部分数据转换为字符串，逆序存储 + do { + str[i ++] = list[tmp_decimal%10]; + tmp_decimal /= 10; + } while(tmp_decimal); + str[i] = '\0'; + //将逆序字符串转换为正序 + for (j = k; j < (i+k)/2; j++) { + tmp = str[j]; + str[j] = str[i-j-1+k]; + str[i-j-1+k] = tmp; + } + str[i] = '\0'; +} + + +void mprintf(char * Data, ...) +{ + const char *s; + int d; + char buf[16]; + uint8_t txdata; + va_list ap; + va_start(ap, Data); + while ( * Data != 0 ) { + if ( * Data == 0x5c ) { + switch ( *++Data ) { + case 'r': + txdata = 0x0d; + send_uart_data(txdata); + Data ++; + break; + case 'n': + txdata = 0x0a; + send_uart_data(txdata); + Data ++; + break; + default: + Data ++; + break; + } + } else if ( * Data == '%') { + switch ( *++Data ) { + case 's': + s = va_arg(ap, const char *); + for ( ; *s; s++) { + send_uart_data(*((uint8_t *)s)); + } + Data++; + break; + case 'd': + d = va_arg(ap, int); + sky_itoa(d, buf, 10); + for (s = buf; *s; s++) { + send_uart_data(*((uint8_t *)s)); + } + Data++; + break; + case 'x': { + d = va_arg(ap, int); + sky_itoa(d, buf, 16); + for (s = buf; *s; s++) { + send_uart_data(*((uint8_t *)s)); + } + Data++; + break; + } + case 'f': { + double num = va_arg(ap, double); + sky_ftoa(num, buf, 4); + for (s = buf; *s; s++) { + send_uart_data(*((uint8_t *)s)); + } + Data++; + break; + } + default: + Data++; + break; + } + } else { + send_uart_data(*((uint8_t *)Data)); + Data++; + } + } +} \ No newline at end of file diff --git a/MBL/source_ns/drivers/CMT2310/2_Ebyte_Board_Support/E15-EVB02/board_mini_printf.h b/MBL/source_ns/drivers/CMT2310/2_Ebyte_Board_Support/E15-EVB02/board_mini_printf.h new file mode 100755 index 0000000..5dc11b5 --- /dev/null +++ b/MBL/source_ns/drivers/CMT2310/2_Ebyte_Board_Support/E15-EVB02/board_mini_printf.h @@ -0,0 +1,6 @@ +#ifndef __BOARD_PRINTF_H__ +#define __BOARD_PRINTF_H__ + +void mprintf(char * Data, ...); + +#endif // !__BOARD_PRINTF_H__ diff --git a/MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/CMT2310A_def.h b/MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/CMT2310A_def.h new file mode 100755 index 0000000..a4359e6 --- /dev/null +++ b/MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/CMT2310A_def.h @@ -0,0 +1,578 @@ +/* + * THE FOLLOWING FIRMWARE IS PROVIDED: (1) "AS IS" WITH NO WARRANTY; AND + * (2)TO ENABLE ACCESS TO CODING INFORMATION TO GUIDE AND FACILITATE CUSTOMER. + * CONSEQUENTLY, CMOSTEK SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR + * CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT + * OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + * CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + * Copyright (C) CMOSTEK SZ. + */ + +/*! + * @file CMT2310A_def.h + * @brief CMT2310A transceiver RF chip driver + * + * @version 1.0 + * @date Dec 7 2021 + * @author CMOSTEK R&D + */ + + +#ifndef __CMT2310A_DEF_H + +#define __CMT2310A_DEF_H + +//Exit State +#define EXIT_TO_SLEEP 1 +#define EXIT_TO_READY 2 +#define EXIT_TO_TFS 3 +#define EXIT_TO_TX 4 +#define EXIT_TO_RFS 5 +#define EXIT_TO_RX 6 + +//Prefxi select +#define TX_PREFIX_SEL_0 0 +#define TX_PREFIX_SEL_1 1 +#define TX_PREFIX_SEL_PREAMBLE 2 + +//## interrupt source config +typedef union +{ + struct + { + uint8_t PKT_DONE_EN: 1; //pkt_done_en //bit0 + uint8_t CRC_PASS_EN: 1; //crc_pass_en //bit1 + uint8_t ADDR_PASS_EN: 1; //node_address_pass_en //bit2 + uint8_t SYNC_PASS_EN: 1; //sync_pass_en //bit3 + uint8_t PREAM_PASS_EN: 1; //preamble_pass_en //bit4 + uint8_t TX_DONE_EN: 1; //tx_done_en //bit5 + uint8_t RX_TOUT_EN: 1; //rx_timeout_en //bit6 + uint8_t SLP_TOUT_EN: 1; //sleep_timeout_en //bit7 + + uint8_t LD_STOP_EN: 1; //ld_stop_en(PLL lock detect)//bit0 + uint8_t LBD_STOP_EN: 1; //lbd_stop_en //bit1 + uint8_t LBD_STAT_EN: 1; //lbd_status_en //bit2 + uint8_t PKT_ERR_EN: 1; //pkt_err_en //bit3 + uint8_t RSSI_COLL_EN: 1; //rssi_collision_en //bit4 + uint8_t OP_CMD_FAILED_EN: 1; //op_cmd_failed_en //bit5 + uint8_t RSSI_PJD_EN: 1; //rssi_pjd_valid_en //bit6 + uint8_t RESV_2_1: 1; //reserve, don't used //bit7 + + uint8_t SEQ_MATCH_EN: 1; //seq_match_en //bit0 + uint8_t NACK_RECV_EN: 1; //nack_recv_en //bit1 + uint8_t TX_RESEND_DONE_EN: 1; //tx_resend_done_en //bit2 + uint8_t ACK_RECV_FAILED_EN: 1; //ack_recv_failed_en //bit3 + uint8_t TX_DC_DONE_EN: 1; //tx_dc_done_en //bit4 + uint8_t CSMA_DONE_EN: 1; //csma_max_en //bit5 + uint8_t CCA_STAT_EN: 1; //cca_status_en //bit6 + uint8_t API_DONE_EN: 1; //api_done_en //bit7 + + uint8_t TX_FIFO_TH_EN: 1; //tx_fifo_threshold_en //bit0 + uint8_t TX_FIFO_NMTY_EN: 1; //tx_fifo_non_empty_en //bit1 + uint8_t TX_FIFO_FULL_EN: 1; //tx_fifo_full_en //bit2 + uint8_t RX_FIFO_OVF_EN: 1; //rx_fifo_overflow_en //bit3 + uint8_t RESV_4_1: 1; //reserve, don't used //bit4 + uint8_t RX_FIFO_TH_EN: 1; //rx_fifo_threshold_en //bit5 + uint8_t RX_FIFO_NMTY_EN: 1; //rx_fifo_non_empty_en //bit6 + uint8_t RX_FIFO_FULL_EN: 1; //rx_fifo_full_en //bit7 + } _BITS; + struct + { + uint8_t INT_CTL1_REG; //CTL_REG_18, 0x12 + uint8_t INT_CTL2_REG; //CTL_REG_21, 0x15 + uint8_t INT_CTL3_REG; //CTL_REG_23, 0x17 + uint8_t INT_CTL4_REG; //CTL_REG_14, 0x0E + } _BYTE; +} INT_SRC_CFG; + +//## interrupt flag +typedef union +{ + struct + { + uint8_t RESV_3: 3; //reserve, don't used //bit0/1/2 + uint8_t TX_DONE_FLG: 1; //tx_done_flag //bit3 + uint8_t RX_TMO_FLG: 1; //rx_timer_timeout_flag //bit4 + uint8_t SLEEP_TMO_FLG: 1; //sleep_timer_timeout_flag //bit5 + uint8_t RESV_2: 2; //reserve, don't used //bit6/7 + + uint8_t PKT_DONE_FLG: 1; //pkt_done_flag //bit0 + uint8_t CRC_PASS_FLG: 1; //crc_pass_flag //bit1 + uint8_t ADDR_PASS_FLG: 1; //addr_pass_flag //bit2 + uint8_t SYNC_PASS_FLG: 1; //sync_pass_flag //bit3 + uint8_t PREAM_PASS_FLG: 1; //preamble_pass_flag //bit4 + uint8_t SYNC1_PASS_FLG: 1; //sync1_pass_flag //bit5 + uint8_t RESV_2_2: 2; //reserve, don't used //bit6/7 + + uint8_t LBD_STATUS_FLG: 1; //lbd_status_flag //bit0 + uint8_t PKT_ERR_FLG: 1; //pkt_err_flag //bit1 + uint8_t RSSI_COLL_FLG: 1; //rssi_collision_flag //bit2 + uint8_t OP_CMD_FAILED_FLG: 1; //op_cmd_failed_flag //bit3 + uint8_t ANT_LOCK_FLG: 1; //ant_lock_flag //bit4 + uint8_t RESV_3_3: 3; //reserve, don't used //bit5/6/7 + + uint8_t SEQ_MATCH_FLG: 1; //seq_match_flag //bit0 + uint8_t NACK_RECV_FLG: 1; //nack_recv_flag //bit1 + uint8_t TX_RESEND_DONE_FLG: 1; //tx_resend_max_flag //bit2 + uint8_t ACK_RECV_FAILED_FLG: 1; //ack_recv_failed_flag //bit3 + uint8_t TX_DC_DONE_FLG: 1; //tx_dc_done_flag //bit4 + uint8_t CSMA_DONE_FLG: 1; //csma_done_flag //bit5 + uint8_t CCA_STATUS_FLG: 1; //cca_status_flag //bit6 + uint8_t API_DONE_FLG: 1; //api_done_flag //bit7 + } _BITS; + struct + { + uint8_t INT_FLAG1_REG; //CTL_REG_24, 0x18 + uint8_t INT_FLAG2_REG; //CTL_REG_26, 0x1A + uint8_t INT_FLAG3_REG; //CTL_REG_30, 0x1E + uint8_t INT_FLAG4_REG; //CTL_REG_32, 0x20 + } _BYTE; +} INT_SRC_FLG; + +//## interrupt clear +typedef union +{ + struct + { + uint8_t TX_DONE_CLR: 1; //tx_done_clr //bit0 + uint8_t RX_TMO_CLR: 1; //rx_timer_timeout_clr //bit1 + uint8_t SLEEP_TMO_CLR: 1; //sleep_timer_timeout_clr //bit2 + uint8_t RESV_5: 5; //reserve, don't used //bit3-7 + + uint8_t PKT_DONE_CLR: 1; //pkt_done_clr //bit0 + uint8_t CRC_PASS_CLR: 1; //crc_pass_clr //bit1 + uint8_t ADDR_PASS_CLR: 1; //addr_pass_clr //bit2 + uint8_t SYNC_PASS_CLR: 1; //sync_pass_clr //bit3 + uint8_t PREAM_PASS_CLR: 1; //preamble_pass_clr //bit4 + uint8_t RESV_3: 3; //reserve, don't used //bit5/6/7 + + uint8_t LBD_STAT_CLR: 1; //lbd_status_clr //bit0 + uint8_t PKT_ERR_CLR: 1; //packet_err_clr //bit1 + uint8_t RSSI_COLL_CLR: 1; //rssi_collision_clr //bit2 + uint8_t OP_CMD_FAILED_CLR: 1; //op_cmd_failed_clr //bit3 + uint8_t ANT_LOCK_CLR: 1; //antenna_lock_clr //bit4 + uint8_t RESV_2_3: 3; //reserve, don't used //bit5/6/7 + + uint8_t SEQ_MATCH_CLR: 1; //seq_match_clr //bit0 + uint8_t NACK_RECV_CLR: 1; //nack_recv_clr //bit1 + uint8_t TX_RESEND_DONE_CLR: 1; //tx_resend_done_clr //bit2 + uint8_t ACK_RECV_FAILED_CLR: 1; //ack_recv_failed_clr //bit3 + uint8_t TX_DC_DONE_CLR: 1; //tx_dc_done_clr //bit4 + uint8_t CSMA_DONE_CLR: 1; //csma_done_clr //bit5 + uint8_t CCA_STATUS_CLR: 1; //cca_status_clr //bit6 + uint8_t API_DONE_CLR: 1; //api_done_clr //bit7 + } _BITS; + struct + { + uint8_t INT_CLR1_REG; //CTL_REG_24, 0x18 + uint8_t INT_CLR2_REG; //CTL_REG_25, 0x19 + uint8_t INT_CLR3_REG; //CTL_REG_29, 0x1D + uint8_t INT_CLR4_REG; //CTL_REG_31, 0x1F + } _BYTE; +} INT_SRC_CLR; + +//## fifo status flag +typedef union +{ + struct + { + uint8_t TX_FIFO_TH_FLG: 1; //tx_fifo_threshold_flag //bit0 + uint8_t TX_FIFO_NMTY_FLG: 1; //tx_fifo_non_empty_flag //bit1 + uint8_t TX_FIFO_FULL_FLG: 1; //tx_fifo_full_flag //bit2 + uint8_t RX_FIFO_OVF_FLG: 1; //rx_fifo_overflow_flag //bit3 + uint8_t RESV_1: 1; //reserve, don't used //bit4 + uint8_t RX_FIFO_TH_FLG: 1; //rx_fifo_threshold_flag //bit5 + uint8_t RX_FIFO_NMTY_FLG: 1; //rx_fifo_non_empty_flag //bit6 + uint8_t RX_FIFO_FULL_FLG: 1; //rx_fifo_full_flag //bit7 + } _BITS; + uint8_t FIFO_FLG_REG; //CTL_REG_28, 0x1c +} FIFO_STATUS_FLG; + + +//## packet preamble config +typedef struct //Packet Preamble +{ + uint8_t PREAM_LENG_UNIT; //0=preamble unit as 8bits, !0=preamble unit as 4bits (nibble mode) + uint8_t PREAM_VALUE; //preamble value + uint8_t RX_PREAM_SIZE; //rx preamble length, range: 0-31, 0==disable rx preamble detect + uint16_t TX_PREAM_SIZE; //tx preamble length //## note: for arm mcu uint16_t is 16bits +} PREAMBLE_CFG; + +//## packet syncword config +typedef struct +{ + union + { + struct + { + uint8_t SYNC_MAN_EN: 1; //sync word manchester coding enable + uint8_t SYNC_SIZE: 3; // n+1 bytes + uint8_t SYNC_TOL: 3; // n bits tolerence error + uint8_t SYNC_MODE_SEL: 1; // 0: compatible S2LP; 1: compatible 802.15.4 + } _BITS; + uint8_t SYNC_CFG_REG; //CTL_REG_44, 0x2c + } SYN_CFG_u; + uint8_t SYNC_VALUE[8]; //CTL_REG_45-CTL_REG_53, 0x2D-0x34 + uint8_t SYNC_FEC_VALUE[8]; //CTL_REG_53-CTL_REG_60, 0x35-0x3C + uint8_t SYNC_VALUE_SEL; // 0: select SYN_VAL; !0: select SYN_FEC_VAL +} SYNC_CFG; + +//## packet node address config +typedef struct +{ + union + { + struct + { + uint8_t ADDR_DET_MODE: 2; //node address mode: 0,disable; 1,only match; 2,add all 0; 3,add all 1 & 0 + uint8_t ADDR_SIZE: 2; // n+1 bytes + uint8_t ADDR_ERR_MASK: 1; // 0: trigger PKT_ERR flag, when node address not match, and reset decode; 1: non-reset decode, when node address not match + uint8_t ADDR_FREE_EN: 1; // 0: disable; 1: enable node address match as stand-alone working + uint8_t ADDR_SPLIT_MODE: 1; // 0: disable, dest_addr==node_addr; 1: enable, node_addr==src_addr+des_addr + uint8_t RESV_1: 1; + } _BITS; + uint8_t ADDR_CFG_REG; //CTL_REG_64, 0x40 + } ADDR_CFG_u; + uint8_t SRC_ADDR[2]; //CTL_REG_65, CTL_REG_66 + uint8_t DEST_ADDR[2]; //CTL_REG_67, CTL_REG_68 + uint8_t SRC_BITMASK[2]; //CTL_REG_69, CTL_REG_70 + uint8_t DEST_BITMASK[2]; //CTL_REG_71, CTL_REG_72 +} ADDR_CFG; + +//## packet crc config +typedef struct +{ + union + { + struct + { + uint8_t CRC_EN: 1; // 0:disable CRC; 1:enable CRC + uint8_t CRC_BIT_ORDER: 1; // 0:crc result MSB output first; 1:crc result LSB output first; active unit is byte + uint8_t CRC_REFIN: 1; // 0:normal input; 1:inverse input; + uint8_t CRC_RANGE: 1; // 0:whole payload; 1:only data + uint8_t CRC_BIT_INV: 1; // 0:crc result non-invert; 1:crc result all bits invert + uint8_t CRC_BYTE_SWAP: 1; // 0:crc result HighByte output first; 1:crc result LowByte output first + uint8_t CRC_SIZE: 2; // 0:crc8; 1:crc16; 2:crc24; 3:crc32 + uint8_t CRC_REFOUT: 1; // 0:result whole bit MSB->LSB 1:result whole bit LSB->MSB + uint8_t CRCERR_CLR_FIFO_EN: 1; // 0:disable 1:enable when crc error, clear fifo function + uint8_t RESV_6: 6; + } _BITS; + uint16_t CRC_CFG_REG; //CTL_REG_73, 0x49 & CTL_REG_82[7] & CTL_REG_84[7] + } CRC_CFG_u; + union //CTL_REG_74-CTL_REG_77, 0x4A-0x4D //## note: for arm mcu uint32_t is 32bits + { + uint8_t u8_SEED[4]; + uint32_t u32_SEED; + } CRC_SEED_u; + union //CTL_REG_78-CTL_REG_81, 0x4E-0x51 //## note: for arm mcu uint32_t is 32bits + { + uint8_t u8_POLY[4]; + uint32_t u32_POLY; + } CRC_POLY_u; +} CRC_CFG; + +//## packet encode/decode format config +typedef struct +{ + union + { + struct + { + uint8_t MANCH_EN: 1; // 0:disable manchester coding; 1:enable manchester coding + uint8_t MANCH_TYPE: 1; // 0: 2'b01=1, 2'b10=0; 1: 2'b01=0, 2'b10=1 + uint8_t WHITEN_EN: 1; // 0:disable whiten coding; 1:enable whiten coding + uint8_t WHITEN_TYPE: 2; // 0:PN9-CCITT, 1:PN9-IBM, 2:PN7, 3:NA + uint8_t WHITEN_SEED_TYP: 1; // 0:compatible A7139; 1:customer seed; note: when select PN7 active + uint8_t RESV_2: 2; + uint8_t FEC_EN: 1; // 0:disable FEC Coding; 1:enable FEC Coding + uint8_t FEC_RSC_NRNSC_SEL: 1; // 0:RSC Mode; 1:NRNSC Mode + uint8_t RESV_5: 5; + uint8_t FEC_TICC: 1; // 0:ui invert ouput in FEC calucate; 1:ui non-invert ouput in FEC calucate + } _BITS; + uint16_t CODING_CFG_REG; // CTL_REG_82, 0x52 & CTL_REG_93, 0x5D + } CODING_FORMAT_CFG_u; + uint16_t WHITEN_SEED; // CTL_REG_83, 0x53 & CTL_REG_82[6] + uint16_t FEC_PAD_CODE; // CTL_REG_94, 0x5E & CTL_REG_93[6:2], 0x5D +} CODING_FORMAT_CFG; + +//## frame struct config +typedef struct +{ + uint8_t DATA_MODE; //0: direct mode; 2: packet mode; 1&3: na + union + { + struct + { + uint8_t PKT_TYPE: 1; //0: fixed length; 1: variable length + uint8_t PAYLOAD_BIT_ORDER: 1; //0: MSB output first; 1: LSB output first + uint8_t ADDR_LEN_CONF: 1; //0: node_addr+length; 1: length+node_addr + uint8_t ADDR_FIELD_EN: 1; //0: disable; 1: enable address field + uint8_t PAGGYBACKING_EN: 1; //0: disable 1: enable + uint8_t LENGTH_SIZE: 1; //0: length range 1 byte; 1: length range 2 bytes + uint8_t RESV_1_2: 1; + uint8_t INTERLEAVE_EN: 1; //0: disable interleave 1: enable interleave + } _BITS; + uint8_t FRAME_CFG1_REG; //CTL_REG_63, 0x3F + } FRAME_CFG1_u; + union + { + struct + { + uint8_t TX_PREFIX_TYPE: 2; //0:transmit_0; 1:transmit_1; 2:transmit_preamble 3:NA + uint8_t SEQNUM_EN: 1; //0:disable; 1:enable; note: SEQ_NUM is the same with FCS1 + uint8_t SEQNUM_AUTO_INC: 1; //0:disable SEQNUM increase; 1:enable + uint8_t SEQNUM_SIZE: 1; //0:1byte for SEQNUM; 1:2bytes for SEQNUM + uint8_t SEQNUM_MACH_EN: 1; //0:disable; 1:enable compare with local SEQNUM, when TX_ACK enable + uint8_t FCS2_EN: 1; //0:not include FCS2 filed; 1:include FCS2 filed + uint8_t RESV_1: 1; + } _BITS; + uint8_t FRAME_CFG2_REG; //CTL_REG_84, 0x54 + } FRAME_CFG2_u; + + uint16_t TX_PKT_NUM; //CTL_REG_85, 0x55[7:0] & CTL_REG_86, 0x56[15:8] + uint16_t SEQNUM_TX_IN; //CTL_REG_88/87, 0x58[15:8], 0x57[7:0] + uint16_t SEQNUM_TX_CURRENT_OUT; //CTL_REG_39/38, 0x27[15:8]/0x26[7:0] + uint8_t TX_PKT_GAP; //CTL_REG_89, 0x59 + uint8_t FCS2_TX_IN; //CTL_REG_91, 0x5B + uint8_t FCS2_RX_OUT; //CTL_REG_92, 0x5C + uint16_t PAYLOAD_LENGTH; //CTL_REG_62/61, 0x3E[15:8], 0x3D[7:0] +} FRAME_CFG; + +//## Wi-SUN V1.0 packet format compatible +typedef union +{ + struct + { + uint8_t WISUN_DW: 1; // 0:not whiten, 1: whiten + uint8_t WISUN_FCS: 1; // 0:CRC-32 for PSDU, 1: CRC-16 for PSDU + uint8_t RESV_2: 2; // + uint8_t WISUN_MS: 1; // default for 0 + uint8_t WHITEN_WISUN: 1; // 0: for normal used, 1: for Wi-SUN whitenning + uint8_t WISUN_ALLIN: 1; // 0: WISUN_FCS & WISUN_DW not active, 1: FCS & DW depend on WISUN_FCS & WISUN_DW, + uint8_t LENGTH_MODE: 1; // 0: for normal used, 1: for Wi-SUN used, PSDU length filed is 11bits + } _BITS; + uint8_t WI_SUN_REG; //CTL_REG_111, 0x6F +} WI_SUN_CFG; + +//## working mode +typedef struct +{ + union + { + struct + { + uint8_t TX_DC_EN: 1; //0:disable TxDutyCycle; 1:enable + uint8_t TX_DC_PERSIST_EN: 1; //0:run TX_DC_TIMES; 1:always run until this bit set 0 + uint8_t TX_ACK_EN: 1; //0:disable 1:enable + uint8_t TX_AUTO_HOP_EN: 1; //0:disable 1:enable tx frequency auto hopping + uint8_t TX_EXIT_STATE: 3; //1:Sleep, 2:Ready, 3:TFS, 4:TX, 5:RFS, 6:RX, other Sleep + uint8_t RESV: 1; + } _BITS; + uint8_t WORK_MODE_CFG1_REG; //CTL_REG_96, 0x60 + } WORK_MODE_CFG1_u; + + union + { + struct + { + uint8_t RX_DC_EN: 1; //0:disable RxDutyCycle; 1:enable + uint8_t RX_AUTO_HOP_EN: 1; //0:disable RxAutoHop; 1:enable + uint8_t RX_ACK_EN: 1; //0:disable 1:enable + uint8_t RX_TIMER_EN: 1; //0:disable 1:enable + uint8_t RX_EXIT_STATE: 3; //1:Sleep, 2:Ready, 3:TFS, 4:TX, 5:RFS, 6:RX, other Sleep + uint8_t CSMA_EN: 1; //0:disable 1:enable + } _BITS; + uint8_t WORK_MODE_CFG2_REG; //CTL_REG_97, 0x61 + } WORK_MODE_CFG2_u; + + union + { + struct + { + uint8_t SLP_MODE: 4; //14 items for select + uint8_t RX_HOP_SLP_MODE: 3; //7 items for select + uint8_t PKT_DONE_EXIT_EN: 1; //0:keep on current state; 1:depends on RX_EXIT_STATE + } _BITS; + uint8_t WORK_MODE_CFG3_REG; //CTL_REG_98, 0x62 + } WORK_MODE_CFG3_u; + + union + { + struct + { + uint8_t LFCLK_OUT_EN: 1; //0:disable; 1:enable LFCLK output to GPIO4 + uint8_t LFCLK_SEL: 1; //0:LFOSC; 1:LFXO (32768Hz) + uint8_t RESV_1: 1; // + uint8_t SLEEP_TIMER_EN: 1; //0:disable 1:enable + uint8_t TIMER_RAND_MODE: 2; //00:random R, 01:random M, 10:both M&R random, 11:depends on config value + uint8_t RESV_2: 2; + } _BITS; + uint8_t WORK_MODE_CFG4_REG; //CTL_REG_105, 0x69 + } WORK_MODE_CFG4_u; + + union + { + struct + { + uint8_t CSMA_CCA_WIN_SEL: 2; //00:32symbol, 01:64symbol, 10:128symbol, 11:256symbol + uint8_t CSMA_CCA_INT_SEL: 2; //00:PJD, 01:RSSI, 10:PJD & RSSI, 11:NA + uint8_t CSMA_PERSIST_EN: 1; //0:auto exit when reach max & channel still busy, 1:keep on work until send out + uint8_t CSMA_CCA_MODE: 3; //000:idle, 001:>=1 RSSI, 010:>=1 PJD, 011:>=1 RSSI or PJD, + //100:>=1 SYNC, 101:>=1 SYNC or RSSI, 110:>=1 SYNC or PJD, 111:>=1 SYNC or PJD or RSSI + } _BITS; + uint8_t WORK_MODE_CFG5_REG; //CTL_REG_106, 0x6A + } WORK_MODE_CFG5_u; + + union + { + struct + { + uint8_t RESV_5: 5; + uint8_t FREQ_SW_STATE: 1; //0:switch to RFS/TFS, and then to the next channel; 1:switch to RDY, and then to the next channel; + uint8_t RX_HOP_PERSIST: 1; //0:depend on TX/RX_EXIT_STATE, 1:go on next cycle from 0 label + uint8_t FREQ_HOP_MANU_EN: 1; //0:auto hopping mode; 1:hopping by manual + + } _BITS; + uint8_t WORK_MODE_CFG6_REG; + } WORK_MODE_CFG6_u; //CTL_REG_22, 0x16 + + uint8_t FREQ_CHANL_NANU; //CTL_REG_3, 0x03, frequency hopping by manual, set channel number + uint8_t FREQ_DONE_TIMES; //CTL_REG_11, 0x0B, auto frequency hopping times have done + uint8_t FREQ_SPACE; //CTL_REG_12, 0x0C, auto frequency channel interval + uint8_t FREQ_TIMES; //CTL_REG_13, 0x0D, auto frequency hopping set range, 1-64 + + uint16_t SLEEP_TIMER_M; //CTL_REG_100[7:5]|CLT_REG_99, 11bits, 0x64,0x63 + uint8_t SLEEP_TIMER_R; //CTL_REG_100[4:0], 0x64 + uint16_t RX_TIMER_T1_M; //CTL_REG_102[7:5]|CLT_REG_101, 11bits, 0x66, 0x65 + uint8_t RX_TIMER_T1_R; //CTL_REG_102[4:0], 0x66 + uint16_t RX_TIMER_T2_M; //CTL_REG_104[7:5]|CLT_REG_103, 11bits, 0x68, 0x67 + uint8_t RX_TIMER_T2_R; //CTL_REG_104[4:0], 0x68 + uint16_t RX_TIMER_CSMA_M; //CTL_REG_108[7:5]|CLT_REG_107, 11bits, 0x6C,0x6B + uint8_t RX_TIMER_CSMA_R; //CTL_REG_108[4:0], 0x6C + uint8_t TX_DC_TIMES; //CTL_REG_110, 0x6E, tx duty cycle, set maximum times + uint8_t TX_DC_DONE_TIMES; //CTL_REG_112, 0x70, tx duty cycle, times have done + uint8_t TX_RS_TIMES; //CTL_REG_113, 0x71, tx ack mode, set maximum times + uint8_t TX_RS_DONE_TIMES; //CLT_REG_114, 0x72, tx ack mode, times have done + uint8_t CSMA_TIMES; //CTL_REG_115, 0x73, csma, set maximum times + uint8_t CSMA_DONE_TIMES; //CTL_REG_116, 0x74, csma, times have done + uint16_t SLEEP_TIMER_CSMA_M; //CTL_REG_119[7:5]|CTL_REG_118, 11bits + uint8_t SLEEP_TIMER_CSMA_R; //CTL_REG_119, 0x77[4:0] +} WORK_MODE_CFG; + +//## RSSI config (in page1) +typedef struct +{ + union + { + struct + { + uint8_t COLL_DET_EN: 1; //0: disable, 1: enable collision detect; + uint8_t RESV_1: 1; + uint8_t RSSI_UPDATE_SEL: 2; //0:always update, 1:when PREAM_OK, 2:when SYNC_OK, 3:when PKT_DONE + uint8_t COLL_STEP_SEL: 2; //0:6dB, 1:10dB, 2:16dB 3:20dB + uint8_t RESV_2: 2; + } _BITS; + uint8_t RSSI_CFG_REG; //RX_RSSI_REG_00, 0x62, page1 + } FRAME_CFG1_u; + uint8_t RSSI_ABS_TH; //RX_RSSI_REG_01, 0x63, page1 +} RSSI_CFG; + + +//## Antenna config (in page0 & page1) +typedef struct +{ + union + { + struct + { + uint8_t ANT_SELECT: 1; //0: antenna1, 1: antenna2, for antenna diversity manual mode + uint8_t ANT_DIV_MANU: 1; //0: auto antenna diversity, 1: manual antenna diversity + uint8_t RESV_6: 6; + } _BITS; + uint8_t ANT_CFG1_REG; // CTL_REG_02, 0x02, page0 + } ANT_CFG1_u; + + union + { + struct + { + uint8_t ANT_INSTR: 1; //0: antenna1 was used, 1: antenna2 was used, for indicate which antenna was used in antenna diversity auto mode + uint8_t RESV_7: 6; + } _BITS; + uint8_t ANT_CFG2_REG; // CTL_REG_14, 0x0E, page0 + } ANT_CFG2_u; + + union + { + struct + { + uint8_t ANT_DIV_EN: 1; //0: disable, 1: enable antenna diversity + uint8_t ANT_SW_DIS: 1; //0: enable, 1: disable antenna diversity switch + uint8_t ANT_WAIT_PMB: 2; //0: RX_PREAM_SIZE x1.5, 1: RX_PREAM_SIZE x2, 2: RX_PREAM_SIZE x2.5, 3: RX_PREAM_SIZE x3 + uint8_t RESV_4: 4; + } _BITS; + uint8_t RX_ANTD_REG; //RX_ANTD_REG_00, 0x67, page1 + } ANT_CFG3_u; +} ANT_DIV_CFG; + +//## CDR Tracing (in page1) +typedef struct +{ + union + { + struct + { + uint8_t CDR_MODE: 2; //0:tracing, 1:counting, 2:manchester, 3:no_cdr + uint8_t CDR_RANGE_SEL: 2; //0:+/-6.3%, 1:+/-9.4%, 2:+/-12.5%, 3:+/-15.6% + uint8_t CDR_AVG_SEL: 3; //0:48/64, 1:32/64 2:24/64 3:16/64, 4:11/64 5:8/64 6:6/64 7:4/64 + uint8_t CDR_DET_SEL: 1; //0:mode0, 1:mode1(recommand) + } _BITS; + uint8_t CDR_CFG0_REG; //RX_CDR_REG_00, 0x44, page1 + } CDR_CFG0_u; + union + { + struct + { + uint8_t RESV_3: 3; //CDR_BR_TH<18:16> + uint8_t CDR_3RD_EN: 1; //0:disable, 1:enable + uint8_t CDR_4TH_EN: 1; //0:disable, 1:enable + uint8_t RESV_3_2: 3; //0:mode0, 1:mode1(recommend) + } _BITS; + uint8_t CDR_CFG1_REG; //RX_CDR_REG_00, 0x44, page1 + } CDR_CFG1_u; + uint32_t CDR_BR_TH; //RX_CDR_REG_03<18:16> & RX_CDR_REG_02<15:8> & RX_CDR_REG_01<7:0>, page1(0x47,0x45,0x46) +} CDR_TRACING_CFG; + +enum CDR_MODE +{ + CDR_SEL_TRACING = 0, + CDR_SEL_COUNTING = 1, + CDR_SEL_MANCHESTER = 2, + CDR_SEL_RAW = 3, +}; + +typedef struct +{ + INT_SRC_CFG int_src_en; + INT_SRC_FLG int_src_flag; + INT_SRC_CLR int_src_clear; + FIFO_STATUS_FLG fifo_status_flag; + PREAMBLE_CFG preamble_cfg; + SYNC_CFG sync_cfg; + ADDR_CFG addr_cfg; + CRC_CFG crc_cfg; + CODING_FORMAT_CFG coding_format_cfg; + FRAME_CFG frame_cfg; + WI_SUN_CFG wi_sun_cfg; + WORK_MODE_CFG word_mode_cfg; + RSSI_CFG rssi_cfg; + ANT_DIV_CFG antenna_cfg; + CDR_TRACING_CFG cdr_tracing_cfg; +} CMT2310A_CFG; + +#endif + +//****************************************************************************** +//* EOF (not truncated) +//****************************************************************************** diff --git a/MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/CMT2310A_def.h.orig b/MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/CMT2310A_def.h.orig new file mode 100755 index 0000000..7ed4b25 --- /dev/null +++ b/MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/CMT2310A_def.h.orig @@ -0,0 +1,578 @@ +/* + * THE FOLLOWING FIRMWARE IS PROVIDED: (1) "AS IS" WITH NO WARRANTY; AND + * (2)TO ENABLE ACCESS TO CODING INFORMATION TO GUIDE AND FACILITATE CUSTOMER. + * CONSEQUENTLY, CMOSTEK SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR + * CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT + * OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + * CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + * Copyright (C) CMOSTEK SZ. + */ + +/*! + * @file CMT2310A_def.h + * @brief CMT2310A transceiver RF chip driver + * + * @version 1.0 + * @date Dec 7 2021 + * @author CMOSTEK R&D + */ + + +#ifndef __CMT2310A_DEF_H + + #define __CMT2310A_DEF_H + + //Exit State + #define EXIT_TO_SLEEP 1 + #define EXIT_TO_READY 2 + #define EXIT_TO_TFS 3 + #define EXIT_TO_TX 4 + #define EXIT_TO_RFS 5 + #define EXIT_TO_RX 6 + + //Prefxi select + #define TX_PREFIX_SEL_0 0 + #define TX_PREFIX_SEL_1 1 + #define TX_PREFIX_SEL_PREAMBLE 2 + + //## interrupt source config + typedef union + { + struct + { + uint8_t PKT_DONE_EN: 1; //pkt_done_en //bit0 + uint8_t CRC_PASS_EN: 1; //crc_pass_en //bit1 + uint8_t ADDR_PASS_EN: 1; //node_address_pass_en //bit2 + uint8_t SYNC_PASS_EN: 1; //sync_pass_en //bit3 + uint8_t PREAM_PASS_EN: 1; //preamble_pass_en //bit4 + uint8_t TX_DONE_EN: 1; //tx_done_en //bit5 + uint8_t RX_TOUT_EN: 1; //rx_timeout_en //bit6 + uint8_t SLP_TOUT_EN: 1; //sleep_timeout_en //bit7 + + uint8_t LD_STOP_EN: 1; //ld_stop_en(PLL lock detect)//bit0 + uint8_t LBD_STOP_EN: 1; //lbd_stop_en //bit1 + uint8_t LBD_STAT_EN: 1; //lbd_status_en //bit2 + uint8_t PKT_ERR_EN: 1; //pkt_err_en //bit3 + uint8_t RSSI_COLL_EN: 1; //rssi_collision_en //bit4 + uint8_t OP_CMD_FAILED_EN: 1; //op_cmd_failed_en //bit5 + uint8_t RSSI_PJD_EN: 1; //rssi_pjd_valid_en //bit6 + uint8_t RESV_2_1: 1; //reserve, don't used //bit7 + + uint8_t SEQ_MATCH_EN: 1; //seq_match_en //bit0 + uint8_t NACK_RECV_EN: 1; //nack_recv_en //bit1 + uint8_t TX_RESEND_DONE_EN: 1; //tx_resend_done_en //bit2 + uint8_t ACK_RECV_FAILED_EN: 1; //ack_recv_failed_en //bit3 + uint8_t TX_DC_DONE_EN: 1; //tx_dc_done_en //bit4 + uint8_t CSMA_DONE_EN: 1; //csma_max_en //bit5 + uint8_t CCA_STAT_EN: 1; //cca_status_en //bit6 + uint8_t API_DONE_EN: 1; //api_done_en //bit7 + + uint8_t TX_FIFO_TH_EN: 1; //tx_fifo_threshold_en //bit0 + uint8_t TX_FIFO_NMTY_EN: 1; //tx_fifo_non_empty_en //bit1 + uint8_t TX_FIFO_FULL_EN: 1; //tx_fifo_full_en //bit2 + uint8_t RX_FIFO_OVF_EN: 1; //rx_fifo_overflow_en //bit3 + uint8_t RESV_4_1: 1; //reserve, don't used //bit4 + uint8_t RX_FIFO_TH_EN: 1; //rx_fifo_threshold_en //bit5 + uint8_t RX_FIFO_NMTY_EN: 1; //rx_fifo_non_empty_en //bit6 + uint8_t RX_FIFO_FULL_EN: 1; //rx_fifo_full_en //bit7 + }_BITS; + struct + { + uint8_t INT_CTL1_REG; //CTL_REG_18, 0x12 + uint8_t INT_CTL2_REG; //CTL_REG_21, 0x15 + uint8_t INT_CTL3_REG; //CTL_REG_23, 0x17 + uint8_t INT_CTL4_REG; //CTL_REG_14, 0x0E + }_BYTE; + }INT_SRC_CFG; + + //## interrupt flag + typedef union + { + struct + { + uint8_t RESV_3: 3; //reserve, don't used //bit0/1/2 + uint8_t TX_DONE_FLG: 1; //tx_done_flag //bit3 + uint8_t RX_TMO_FLG: 1; //rx_timer_timeout_flag //bit4 + uint8_t SLEEP_TMO_FLG: 1; //sleep_timer_timeout_flag //bit5 + uint8_t RESV_2: 2; //reserve, don't used //bit6/7 + + uint8_t PKT_DONE_FLG: 1; //pkt_done_flag //bit0 + uint8_t CRC_PASS_FLG: 1; //crc_pass_flag //bit1 + uint8_t ADDR_PASS_FLG: 1; //addr_pass_flag //bit2 + uint8_t SYNC_PASS_FLG: 1; //sync_pass_flag //bit3 + uint8_t PREAM_PASS_FLG: 1; //preamble_pass_flag //bit4 + uint8_t SYNC1_PASS_FLG: 1; //sync1_pass_flag //bit5 + uint8_t RESV_2_2: 2; //reserve, don't used //bit6/7 + + uint8_t LBD_STATUS_FLG: 1; //lbd_status_flag //bit0 + uint8_t PKT_ERR_FLG: 1; //pkt_err_flag //bit1 + uint8_t RSSI_COLL_FLG: 1; //rssi_collision_flag //bit2 + uint8_t OP_CMD_FAILED_FLG: 1; //op_cmd_failed_flag //bit3 + uint8_t ANT_LOCK_FLG: 1; //ant_lock_flag //bit4 + uint8_t RESV_3_3: 3; //reserve, don't used //bit5/6/7 + + uint8_t SEQ_MATCH_FLG: 1; //seq_match_flag //bit0 + uint8_t NACK_RECV_FLG: 1; //nack_recv_flag //bit1 + uint8_t TX_RESEND_DONE_FLG: 1; //tx_resend_max_flag //bit2 + uint8_t ACK_RECV_FAILED_FLG: 1; //ack_recv_failed_flag //bit3 + uint8_t TX_DC_DONE_FLG: 1; //tx_dc_done_flag //bit4 + uint8_t CSMA_DONE_FLG: 1; //csma_done_flag //bit5 + uint8_t CCA_STATUS_FLG: 1; //cca_status_flag //bit6 + uint8_t API_DONE_FLG: 1; //api_done_flag //bit7 + }_BITS; + struct + { + uint8_t INT_FLAG1_REG; //CTL_REG_24, 0x18 + uint8_t INT_FLAG2_REG; //CTL_REG_26, 0x1A + uint8_t INT_FLAG3_REG; //CTL_REG_30, 0x1E + uint8_t INT_FLAG4_REG; //CTL_REG_32, 0x20 + }_BYTE; + }INT_SRC_FLG; + + //## interrupt clear + typedef union + { + struct + { + uint8_t TX_DONE_CLR: 1; //tx_done_clr //bit0 + uint8_t RX_TMO_CLR: 1; //rx_timer_timeout_clr //bit1 + uint8_t SLEEP_TMO_CLR: 1; //sleep_timer_timeout_clr //bit2 + uint8_t RESV_5: 5; //reserve, don't used //bit3-7 + + uint8_t PKT_DONE_CLR: 1; //pkt_done_clr //bit0 + uint8_t CRC_PASS_CLR: 1; //crc_pass_clr //bit1 + uint8_t ADDR_PASS_CLR: 1; //addr_pass_clr //bit2 + uint8_t SYNC_PASS_CLR: 1; //sync_pass_clr //bit3 + uint8_t PREAM_PASS_CLR: 1; //preamble_pass_clr //bit4 + uint8_t RESV_3: 3; //reserve, don't used //bit5/6/7 + + uint8_t LBD_STAT_CLR: 1; //lbd_status_clr //bit0 + uint8_t PKT_ERR_CLR: 1; //packet_err_clr //bit1 + uint8_t RSSI_COLL_CLR: 1; //rssi_collision_clr //bit2 + uint8_t OP_CMD_FAILED_CLR: 1; //op_cmd_failed_clr //bit3 + uint8_t ANT_LOCK_CLR: 1; //antenna_lock_clr //bit4 + uint8_t RESV_2_3: 3; //reserve, don't used //bit5/6/7 + + uint8_t SEQ_MATCH_CLR: 1; //seq_match_clr //bit0 + uint8_t NACK_RECV_CLR: 1; //nack_recv_clr //bit1 + uint8_t TX_RESEND_DONE_CLR: 1; //tx_resend_done_clr //bit2 + uint8_t ACK_RECV_FAILED_CLR: 1; //ack_recv_failed_clr //bit3 + uint8_t TX_DC_DONE_CLR: 1; //tx_dc_done_clr //bit4 + uint8_t CSMA_DONE_CLR: 1; //csma_done_clr //bit5 + uint8_t CCA_STATUS_CLR: 1; //cca_status_clr //bit6 + uint8_t API_DONE_CLR: 1; //api_done_clr //bit7 + }_BITS; + struct + { + uint8_t INT_CLR1_REG; //CTL_REG_24, 0x18 + uint8_t INT_CLR2_REG; //CTL_REG_25, 0x19 + uint8_t INT_CLR3_REG; //CTL_REG_29, 0x1D + uint8_t INT_CLR4_REG; //CTL_REG_31, 0x1F + }_BYTE; + }INT_SRC_CLR; + + //## fifo status flag + typedef union + { + struct + { + uint8_t TX_FIFO_TH_FLG: 1; //tx_fifo_threshold_flag //bit0 + uint8_t TX_FIFO_NMTY_FLG: 1; //tx_fifo_non_empty_flag //bit1 + uint8_t TX_FIFO_FULL_FLG: 1; //tx_fifo_full_flag //bit2 + uint8_t RX_FIFO_OVF_FLG: 1; //rx_fifo_overflow_flag //bit3 + uint8_t RESV_1: 1; //reserve, don't used //bit4 + uint8_t RX_FIFO_TH_FLG: 1; //rx_fifo_threshold_flag //bit5 + uint8_t RX_FIFO_NMTY_FLG: 1; //rx_fifo_non_empty_flag //bit6 + uint8_t RX_FIFO_FULL_FLG: 1; //rx_fifo_full_flag //bit7 + }_BITS; + uint8_t FIFO_FLG_REG; //CTL_REG_28, 0x1c + }FIFO_STATUS_FLG; + + + //## packet preamble config + typedef struct //Packet Preamble + { + uint8_t PREAM_LENG_UNIT; //0=preamble unit as 8bits, !0=preamble unit as 4bits (nibble mode) + uint8_t PREAM_VALUE; //preamble value + uint8_t RX_PREAM_SIZE; //rx preamble length, range: 0-31, 0==disable rx preamble detect + uint16_t TX_PREAM_SIZE; //tx preamble length //## note: for arm mcu uint16_t is 16bits + }PREAMBLE_CFG; + + //## packet syncword config + typedef struct + { + union + { + struct + { + uint8_t SYNC_MAN_EN: 1; //sync word manchester coding enable + uint8_t SYNC_SIZE: 3; // n+1 bytes + uint8_t SYNC_TOL: 3; // n bits tolerence error + uint8_t SYNC_MODE_SEL: 1; // 0: compatible S2LP; 1: compatible 802.15.4 + }_BITS; + uint8_t SYNC_CFG_REG; //CTL_REG_44, 0x2c + }SYN_CFG_u; + uint8_t SYNC_VALUE[8]; //CTL_REG_45-CTL_REG_53, 0x2D-0x34 + uint8_t SYNC_FEC_VALUE[8]; //CTL_REG_53-CTL_REG_60, 0x35-0x3C + uint8_t SYNC_VALUE_SEL; // 0: select SYN_VAL; !0: select SYN_FEC_VAL + }SYNC_CFG; + + //## packet node address config + typedef struct + { + union + { + struct + { + uint8_t ADDR_DET_MODE: 2; //node address mode: 0,disable; 1,only match; 2,add all 0; 3,add all 1 & 0 + uint8_t ADDR_SIZE: 2; // n+1 bytes + uint8_t ADDR_ERR_MASK: 1; // 0: trigger PKT_ERR flag, when node address not match, and reset decode; 1: non-reset decode, when node address not match + uint8_t ADDR_FREE_EN: 1; // 0: disable; 1: enable node address match as stand-alone working + uint8_t ADDR_SPLIT_MODE: 1; // 0: disable, dest_addr==node_addr; 1: enable, node_addr==src_addr+des_addr + uint8_t RESV_1: 1; + }_BITS; + uint8_t ADDR_CFG_REG; //CTL_REG_64, 0x40 + }ADDR_CFG_u; + uint8_t SRC_ADDR[2]; //CTL_REG_65, CTL_REG_66 + uint8_t DEST_ADDR[2]; //CTL_REG_67, CTL_REG_68 + uint8_t SRC_BITMASK[2]; //CTL_REG_69, CTL_REG_70 + uint8_t DEST_BITMASK[2]; //CTL_REG_71, CTL_REG_72 + }ADDR_CFG; + + //## packet crc config + typedef struct + { + union + { + struct + { + uint8_t CRC_EN: 1; // 0:disable CRC; 1:enable CRC + uint8_t CRC_BIT_ORDER: 1; // 0:crc result MSB output first; 1:crc result LSB output first; active unit is byte + uint8_t CRC_REFIN: 1; // 0:normal input; 1:inverse input; + uint8_t CRC_RANGE: 1; // 0:whole payload; 1:only data + uint8_t CRC_BIT_INV: 1; // 0:crc result non-invert; 1:crc result all bits invert + uint8_t CRC_BYTE_SWAP: 1; // 0:crc result HighByte output first; 1:crc result LowByte output first + uint8_t CRC_SIZE: 2; // 0:crc8; 1:crc16; 2:crc24; 3:crc32 + uint8_t CRC_REFOUT: 1; // 0:result whole bit MSB->LSB 1:result whole bit LSB->MSB + uint8_t CRCERR_CLR_FIFO_EN: 1; // 0:disable 1:enable when crc error, clear fifo function + uint8_t RESV_6: 6; + }_BITS; + uint16_t CRC_CFG_REG; //CTL_REG_73, 0x49 & CTL_REG_82[7] & CTL_REG_84[7] + }CRC_CFG_u; + union //CTL_REG_74-CTL_REG_77, 0x4A-0x4D //## note: for arm mcu uint32_t is 32bits + { + uint8_t u8_SEED[4]; + uint32_t u32_SEED; + }CRC_SEED_u; + union //CTL_REG_78-CTL_REG_81, 0x4E-0x51 //## note: for arm mcu uint32_t is 32bits + { + uint8_t u8_POLY[4]; + uint32_t u32_POLY; + }CRC_POLY_u; + }CRC_CFG; + + //## packet encode/decode format config + typedef struct + { + union + { + struct + { + uint8_t MANCH_EN: 1; // 0:disable manchester coding; 1:enable manchester coding + uint8_t MANCH_TYPE: 1; // 0: 2'b01=1, 2'b10=0; 1: 2'b01=0, 2'b10=1 + uint8_t WHITEN_EN: 1; // 0:disable whiten coding; 1:enable whiten coding + uint8_t WHITEN_TYPE: 2; // 0:PN9-CCITT, 1:PN9-IBM, 2:PN7, 3:NA + uint8_t WHITEN_SEED_TYP: 1; // 0:compatible A7139; 1:customer seed; note: when select PN7 active + uint8_t RESV_2: 2; + uint8_t FEC_EN: 1; // 0:disable FEC Coding; 1:enable FEC Coding + uint8_t FEC_RSC_NRNSC_SEL: 1; // 0:RSC Mode; 1:NRNSC Mode + uint8_t RESV_5: 5; + uint8_t FEC_TICC: 1; // 0:ui invert ouput in FEC calucate; 1:ui non-invert ouput in FEC calucate + }_BITS; + uint16_t CODING_CFG_REG; // CTL_REG_82, 0x52 & CTL_REG_93, 0x5D + }CODING_FORMAT_CFG_u; + uint16_t WHITEN_SEED; // CTL_REG_83, 0x53 & CTL_REG_82[6] + uint16_t FEC_PAD_CODE; // CTL_REG_94, 0x5E & CTL_REG_93[6:2], 0x5D + }CODING_FORMAT_CFG; + + //## frame struct config + typedef struct + { + uint8_t DATA_MODE; //0: direct mode; 2: packet mode; 1&3: na + union + { + struct + { + uint8_t PKT_TYPE: 1; //0: fixed length; 1: variable length + uint8_t PAYLOAD_BIT_ORDER: 1; //0: MSB output first; 1: LSB output first + uint8_t ADDR_LEN_CONF: 1; //0: node_addr+length; 1: length+node_addr + uint8_t ADDR_FIELD_EN: 1; //0: disable; 1: enable address field + uint8_t PAGGYBACKING_EN: 1; //0: disable 1: enable + uint8_t LENGTH_SIZE: 1; //0: length range 1 byte; 1: length range 2 bytes + uint8_t RESV_1_2: 1; + uint8_t INTERLEAVE_EN: 1; //0: disable interleave 1: enable interleave + }_BITS; + uint8_t FRAME_CFG1_REG; //CTL_REG_63, 0x3F + }FRAME_CFG1_u; + union + { + struct + { + uint8_t TX_PREFIX_TYPE: 2; //0:transmit_0; 1:transmit_1; 2:transmit_preamble 3:NA + uint8_t SEQNUM_EN: 1; //0:disable; 1:enable; note: SEQ_NUM is the same with FCS1 + uint8_t SEQNUM_AUTO_INC: 1; //0:disable SEQNUM increase; 1:enable + uint8_t SEQNUM_SIZE: 1; //0:1byte for SEQNUM; 1:2bytes for SEQNUM + uint8_t SEQNUM_MACH_EN: 1; //0:disable; 1:enable compare with local SEQNUM, when TX_ACK enable + uint8_t FCS2_EN: 1; //0:not include FCS2 filed; 1:include FCS2 filed + uint8_t RESV_1: 1; + }_BITS; + uint8_t FRAME_CFG2_REG; //CTL_REG_84, 0x54 + }FRAME_CFG2_u; + + uint16_t TX_PKT_NUM; //CTL_REG_85, 0x55[7:0] & CTL_REG_86, 0x56[15:8] + uint16_t SEQNUM_TX_IN; //CTL_REG_88/87, 0x58[15:8], 0x57[7:0] + uint16_t SEQNUM_TX_CURRENT_OUT; //CTL_REG_39/38, 0x27[15:8]/0x26[7:0] + uint8_t TX_PKT_GAP; //CTL_REG_89, 0x59 + uint8_t FCS2_TX_IN; //CTL_REG_91, 0x5B + uint8_t FCS2_RX_OUT; //CTL_REG_92, 0x5C + uint16_t PAYLOAD_LENGTH; //CTL_REG_62/61, 0x3E[15:8], 0x3D[7:0] + }FRAME_CFG; + + //## Wi-SUN V1.0 packet format compatible + typedef union + { + struct + { + uint8_t WISUN_DW: 1; // 0:not whiten, 1: whiten + uint8_t WISUN_FCS: 1; // 0:CRC-32 for PSDU, 1: CRC-16 for PSDU + uint8_t RESV_2: 2; // + uint8_t WISUN_MS: 1; // default for 0 + uint8_t WHITEN_WISUN: 1; // 0: for normal used, 1: for Wi-SUN whitenning + uint8_t WISUN_ALLIN: 1; // 0: WISUN_FCS & WISUN_DW not active, 1: FCS & DW depend on WISUN_FCS & WISUN_DW, + uint8_t LENGTH_MODE: 1; // 0: for normal used, 1: for Wi-SUN used, PSDU length filed is 11bits + }_BITS; + uint8_t WI_SUN_REG; //CTL_REG_111, 0x6F + }WI_SUN_CFG; + + //## working mode + typedef struct + { + union + { + struct + { + uint8_t TX_DC_EN: 1; //0:disable TxDutyCycle; 1:enable + uint8_t TX_DC_PERSIST_EN: 1; //0:run TX_DC_TIMES; 1:always run until this bit set 0 + uint8_t TX_ACK_EN: 1; //0:disable 1:enable + uint8_t TX_AUTO_HOP_EN: 1; //0:disable 1:enable tx frequency auto hopping + uint8_t TX_EXIT_STATE: 3; //1:Sleep, 2:Ready, 3:TFS, 4:TX, 5:RFS, 6:RX, other Sleep + uint8_t RESV: 1; + }_BITS; + uint8_t WORK_MODE_CFG1_REG; //CTL_REG_96, 0x60 + }WORK_MODE_CFG1_u; + + union + { + struct + { + uint8_t RX_DC_EN: 1; //0:disable RxDutyCycle; 1:enable + uint8_t RX_AUTO_HOP_EN: 1; //0:disable RxAutoHop; 1:enable + uint8_t RX_ACK_EN: 1; //0:disable 1:enable + uint8_t RX_TIMER_EN: 1; //0:disable 1:enable + uint8_t RX_EXIT_STATE: 3; //1:Sleep, 2:Ready, 3:TFS, 4:TX, 5:RFS, 6:RX, other Sleep + uint8_t CSMA_EN: 1; //0:disable 1:enable + }_BITS; + uint8_t WORK_MODE_CFG2_REG; //CTL_REG_97, 0x61 + }WORK_MODE_CFG2_u; + + union + { + struct + { + uint8_t SLP_MODE: 4; //14 items for select + uint8_t RX_HOP_SLP_MODE: 3; //7 items for select + uint8_t PKT_DONE_EXIT_EN: 1; //0:keep on current state; 1:depends on RX_EXIT_STATE + }_BITS; + uint8_t WORK_MODE_CFG3_REG; //CTL_REG_98, 0x62 + }WORK_MODE_CFG3_u; + + union + { + struct + { + uint8_t LFCLK_OUT_EN: 1; //0:disable; 1:enable LFCLK output to GPIO4 + uint8_t LFCLK_SEL: 1; //0:LFOSC; 1:LFXO (32768Hz) + uint8_t RESV_1: 1; // + uint8_t SLEEP_TIMER_EN: 1; //0:disable 1:enable + uint8_t TIMER_RAND_MODE: 2; //00:random R, 01:random M, 10:both M&R random, 11:depends on config value + uint8_t RESV_2: 2; + }_BITS; + uint8_t WORK_MODE_CFG4_REG; //CTL_REG_105, 0x69 + }WORK_MODE_CFG4_u; + + union + { + struct + { + uint8_t CSMA_CCA_WIN_SEL: 2; //00:32symbol, 01:64symbol, 10:128symbol, 11:256symbol + uint8_t CSMA_CCA_INT_SEL: 2; //00:PJD, 01:RSSI, 10:PJD & RSSI, 11:NA + uint8_t CSMA_PERSIST_EN: 1; //0:auto exit when reach max & channel still busy, 1:keep on work until send out + uint8_t CSMA_CCA_MODE: 3; //000:idle, 001:>=1 RSSI, 010:>=1 PJD, 011:>=1 RSSI or PJD, + //100:>=1 SYNC, 101:>=1 SYNC or RSSI, 110:>=1 SYNC or PJD, 111:>=1 SYNC or PJD or RSSI + }_BITS; + uint8_t WORK_MODE_CFG5_REG; //CTL_REG_106, 0x6A + }WORK_MODE_CFG5_u; + + union + { + struct + { + uint8_t RESV_5: 5; + uint8_t FREQ_SW_STATE: 1; //0:switch to RFS/TFS, and then to the next channel; 1:switch to RDY, and then to the next channel; + uint8_t RX_HOP_PERSIST: 1; //0:depend on TX/RX_EXIT_STATE, 1:go on next cycle from 0 label + uint8_t FREQ_HOP_MANU_EN: 1; //0:auto hopping mode; 1:hopping by manual + + }_BITS; + uint8_t WORK_MODE_CFG6_REG; + }WORK_MODE_CFG6_u; //CTL_REG_22, 0x16 + + uint8_t FREQ_CHANL_NANU; //CTL_REG_3, 0x03, frequency hopping by manual, set channel number + uint8_t FREQ_DONE_TIMES; //CTL_REG_11, 0x0B, auto frequency hopping times have done + uint8_t FREQ_SPACE; //CTL_REG_12, 0x0C, auto frequency channel interval + uint8_t FREQ_TIMES; //CTL_REG_13, 0x0D, auto frequency hopping set range, 1-64 + + uint16_t SLEEP_TIMER_M; //CTL_REG_100[7:5]|CLT_REG_99, 11bits, 0x64,0x63 + uint8_t SLEEP_TIMER_R; //CTL_REG_100[4:0], 0x64 + uint16_t RX_TIMER_T1_M; //CTL_REG_102[7:5]|CLT_REG_101, 11bits, 0x66, 0x65 + uint8_t RX_TIMER_T1_R; //CTL_REG_102[4:0], 0x66 + uint16_t RX_TIMER_T2_M; //CTL_REG_104[7:5]|CLT_REG_103, 11bits, 0x68, 0x67 + uint8_t RX_TIMER_T2_R; //CTL_REG_104[4:0], 0x68 + uint16_t RX_TIMER_CSMA_M; //CTL_REG_108[7:5]|CLT_REG_107, 11bits, 0x6C,0x6B + uint8_t RX_TIMER_CSMA_R; //CTL_REG_108[4:0], 0x6C + uint8_t TX_DC_TIMES; //CTL_REG_110, 0x6E, tx duty cycle, set maximum times + uint8_t TX_DC_DONE_TIMES; //CTL_REG_112, 0x70, tx duty cycle, times have done + uint8_t TX_RS_TIMES; //CTL_REG_113, 0x71, tx ack mode, set maximum times + uint8_t TX_RS_DONE_TIMES; //CLT_REG_114, 0x72, tx ack mode, times have done + uint8_t CSMA_TIMES; //CTL_REG_115, 0x73, csma, set maximum times + uint8_t CSMA_DONE_TIMES; //CTL_REG_116, 0x74, csma, times have done + uint16_t SLEEP_TIMER_CSMA_M; //CTL_REG_119[7:5]|CTL_REG_118, 11bits + uint8_t SLEEP_TIMER_CSMA_R; //CTL_REG_119, 0x77[4:0] + }WORK_MODE_CFG; + + //## RSSI config (in page1) + typedef struct + { + union + { + struct + { + uint8_t COLL_DET_EN: 1; //0: disable, 1: enable collision detect; + uint8_t RESV_1: 1; + uint8_t RSSI_UPDATE_SEL: 2; //0:always update, 1:when PREAM_OK, 2:when SYNC_OK, 3:when PKT_DONE + uint8_t COLL_STEP_SEL: 2; //0:6dB, 1:10dB, 2:16dB 3:20dB + uint8_t RESV_2: 2; + }_BITS; + uint8_t RSSI_CFG_REG; //RX_RSSI_REG_00, 0x62, page1 + }FRAME_CFG1_u; + uint8_t RSSI_ABS_TH; //RX_RSSI_REG_01, 0x63, page1 + }RSSI_CFG; + + + //## Antenna config (in page0 & page1) + typedef struct + { + union + { + struct + { + uint8_t ANT_SELECT: 1; //0: antenna1, 1: antenna2, for antenna diversity manual mode + uint8_t ANT_DIV_MANU: 1; //0: auto antenna diversity, 1: manual antenna diversity + uint8_t RESV_6: 6; + }_BITS; + uint8_t ANT_CFG1_REG; // CTL_REG_02, 0x02, page0 + }ANT_CFG1_u; + + union + { + struct + { + uint8_t ANT_INSTR: 1; //0: antenna1 was used, 1: antenna2 was used, for indicate which antenna was used in antenna diversity auto mode + uint8_t RESV_7: 6; + }_BITS; + uint8_t ANT_CFG2_REG; // CTL_REG_14, 0x0E, page0 + }ANT_CFG2_u; + + union + { + struct + { + uint8_t ANT_DIV_EN: 1; //0: disable, 1: enable antenna diversity + uint8_t ANT_SW_DIS: 1; //0: enable, 1: disable antenna diversity switch + uint8_t ANT_WAIT_PMB: 2; //0: RX_PREAM_SIZE x1.5, 1: RX_PREAM_SIZE x2, 2: RX_PREAM_SIZE x2.5, 3: RX_PREAM_SIZE x3 + uint8_t RESV_4: 4; + }_BITS; + uint8_t RX_ANTD_REG; //RX_ANTD_REG_00, 0x67, page1 + }ANT_CFG3_u; + }ANT_DIV_CFG; + + //## CDR Tracing (in page1) + typedef struct + { + union + { + struct + { + uint8_t CDR_MODE: 2; //0:tracing, 1:counting, 2:manchester, 3:no_cdr + uint8_t CDR_RANGE_SEL: 2; //0:+/-6.3%, 1:+/-9.4%, 2:+/-12.5%, 3:+/-15.6% + uint8_t CDR_AVG_SEL: 3; //0:48/64, 1:32/64 2:24/64 3:16/64, 4:11/64 5:8/64 6:6/64 7:4/64 + uint8_t CDR_DET_SEL: 1; //0:mode0, 1:mode1(recommand) + }_BITS; + uint8_t CDR_CFG0_REG; //RX_CDR_REG_00, 0x44, page1 + }CDR_CFG0_u; + union + { + struct + { + uint8_t RESV_3: 3; //CDR_BR_TH<18:16> + uint8_t CDR_3RD_EN: 1; //0:disable, 1:enable + uint8_t CDR_4TH_EN: 1; //0:disable, 1:enable + uint8_t RESV_3_2: 3; //0:mode0, 1:mode1(recommend) + }_BITS; + uint8_t CDR_CFG1_REG; //RX_CDR_REG_00, 0x44, page1 + }CDR_CFG1_u; + uint32_t CDR_BR_TH; //RX_CDR_REG_03<18:16> & RX_CDR_REG_02<15:8> & RX_CDR_REG_01<7:0>, page1(0x47,0x45,0x46) + }CDR_TRACING_CFG; + + enum CDR_MODE + { + CDR_SEL_TRACING = 0, + CDR_SEL_COUNTING = 1, + CDR_SEL_MANCHESTER = 2, + CDR_SEL_RAW = 3, + }; + + typedef struct + { + INT_SRC_CFG int_src_en; + INT_SRC_FLG int_src_flag; + INT_SRC_CLR int_src_clear; + FIFO_STATUS_FLG fifo_status_flag; + PREAMBLE_CFG preamble_cfg; + SYNC_CFG sync_cfg; + ADDR_CFG addr_cfg; + CRC_CFG crc_cfg; + CODING_FORMAT_CFG coding_format_cfg; + FRAME_CFG frame_cfg; + WI_SUN_CFG wi_sun_cfg; + WORK_MODE_CFG word_mode_cfg; + RSSI_CFG rssi_cfg; + ANT_DIV_CFG antenna_cfg; + CDR_TRACING_CFG cdr_tracing_cfg; + }CMT2310A_CFG; + +#endif + +//****************************************************************************** +//* EOF (not truncated) +//****************************************************************************** diff --git a/MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/CMT2310A_reg.h b/MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/CMT2310A_reg.h new file mode 100755 index 0000000..c5a48ef --- /dev/null +++ b/MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/CMT2310A_reg.h @@ -0,0 +1,1229 @@ +/* + * THE FOLLOWING FIRMWARE IS PROVIDED: (1) "AS IS" WITH NO WARRANTY; AND + * (2)TO ENABLE ACCESS TO CODING INFORMATION TO GUIDE AND FACILITATE CUSTOMER. + * CONSEQUENTLY, CMOSTEK SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR + * CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT + * OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + * CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + * Copyright (C) CMOSTEK SZ. + */ + +/*! + * @file CMT2310A_reg.h + * @brief CMT2310A transceiver RF chip driver + * + * @version 1.0 + * @date Dec 7 2021 + * @author CMOSTEK R&D + */ + + +#ifndef __CMT2310A_REG_H + + #define __CMT2310A_REG_H + + #define CMT2310A_PAGE0_SIZE (0x77-0x28+1) + #define CMT2310A_PAGE1_SIZE (0xef-0x80+1) + #define CMT2310A_PAGE2_SIZE (0x3f-0x00+1) + +//---------------------- CUS PAGE0 defines ------------------------------- +//------------------------------------------------------------------------ + #define CMT2310A_CTL_REG_00 0x00 // PU_BOOT<7:0> + #define CMT2310A_REBOOT 0x03 + + #define CMT2310A_CTL_REG_01 0x01 // radio chip status switch + #define CMT2310A_GO_SLEEP (1<<0) // radio go sleep + #define CMT2310A_GO_READY (1<<1) // radio go ready + #define CMT2310A_GO_TX (1<<2) // radio go tx + #define CMT2310A_GO_RX (1<<3) // radio go rx + #define CMT2310A_GO_TFS (1<<4) // radio go tfs + #define CMT2310A_GO_RFS (1<<5) // radio go rfs + + #define CMT2310A_CTL_REG_02 0x02 // Antenna Diversity + #define CMT2310A_ANT_DIV_MANU (1<<1) // 0=disable antenna diversity, 1=enable antenna diversity + #define CMT2310A_ANT_SELECT (1<<0) // 0=select antenna_1, 1=select antenna_2, when antenna diversity manual active + + #define CMT2310A_CTL_REG_03 0x03 // frequencry channel value, by manual set + + #define CMT2310A_CTL_REG_04 0x04 // gpio ctrl 0 + #define CMT2310A_TX_DIN_EN (1<<6) // 0=disable TX_DATA input to GPIO, 1=enable TX_DATA input to GPIO + + #define CMT2310A_GPIO1_SEL (7<<3) // masker + #define CMT2310A_GPIO1_DCLK (0<<3) // gpio1 as DCLK + #define CMT2310A_GPIO1_INT1 (1<<3) // gpio1 as INT1 + #define CMT2310A_GPIO1_INT2 (2<<3) // gpio1 as INT2 + #define CMT2310A_GPIO1_DOUT (3<<3) // goio1 as DOUT + + #define CMT2310A_GPIO0_SEL (7<<0) // masker + #define CMT2310A_GPIO0_DOUT (0<<0) // gpio0 as DOUT + #define CMT2310A_GPIO0_INT1 (1<<0) // gpio0 as INT1 + #define CMT2310A_GPIO0_INT2 (2<<0) // gpio0 as INT2 + #define CMT2310A_GPIO0_DCLK (3<<0) // goio0 as DCLK + #define CMT2310A_GPIO0_INT3 (6<<0) // gpio0 as INT3 + + #define CMT2310A_CTL_REG_05 0x05 // gpio ctrl 1 + #define CMT2310A_TX_DIN_SEL (3<<6) // masker + #define CMT2310A_TX_DIN_GPIO3 (0<<6) // TX_DIN from GPIO3 + #define CMT2310A_TX_DIN_GPIO4 (1<<6) // TX_DIN from GPIO4 + #define CMT2310A_TX_DIN_nIRQ (2<<6) // TX_DIN from nIRQ + + #define CMT2310A_GPIO3_SEL (7<<3) //masker + #define CMT2310A_GPIO3_INT2 (0<<3) // gpio3 as INT2 + #define CMT2310A_GPIO3_INT1 (1<<3) // gpio3 as INT1 + #define CMT2310A_GPIO3_DCLK (2<<3) // gpio3 as DCLK + #define CMT2310A_GPIO3_DOUT (3<<3) // gpio3 as DOUT + #define CMT2310A_GPIO3_DIN (5<<3) // gpio3 as DIN (TX_DIN) + + #define CMT2310A_GPIO2_SEL (7<<0) //masker + #define CMT2310A_GPIO2_INT1 (0<<0) // gpio2 as INT1 + #define CMT2310A_GPIO2_INT2 (1<<0) // gpio2 as INT2 + #define CMT2310A_GPIO2_DCLK (2<<0) // gpio2 as DCLK + #define CMT2310A_GPIO2_DOUT (3<<0) // gpio2 as DOUT + #define CMT2310A_GPIO2_INT3 (6<<0) // gpio2 as INT3 + + #define CMT2310A_CTL_REG_06 0x06 // gpio ctrl 2 + #define CMT2310A_DIG_CLKOUT_EN (1<<6) // 0=bypass, 1=enable digital clock out to GPIO4 + + #define CMT2310A_GPIO5_SEL (7<<3) //masker + #define CMT2310A_GPIO5_nRST (0<<3) // gpio5 as nRST + #define CMT2310A_GPIO5_INT1 (1<<3) // goio5 as INT1 + #define CMT2310A_GPIO5_INT2 (2<<3) // gpio5 as INT2 + #define CMT2310A_GPIO5_DOUT (3<<3) // gpio5 as DOUT + #define CMT2310A_GPIO5_DCLK (4<<3) // gpio5 as DCLK + + #define CMT2310A_GPIO4_SEL (7<<0) //masker + #define CMT2310A_GPIO4_DOUT (0<<0) // gpio4 as DOUT + #define CMT2310A_GPIO4_INT1 (1<<0) // gpio4 as INT1 + #define CMT2310A_GPIO4_INT2 (2<<0) // gpio4 as INT2 + #define CMT2310A_GPIO4_DCLK (3<<0) // gpio4 as DCLK + #define CMT2310A_GPIO4_DIN (5<<0) // gpio4 as DIN (TX_DIN) + + #define CMT2310A_CTL_REG_07 0x07 // nIRQ select + #define CMT2310A_CTL_REG_07_MASK (3<<6) + #define CMT2310A_LFXO_PAD_EN (1<<5) // 0=disable, 1=enable GPIO2 & GPIO3 as 32.768kHz crystal pin + #define CMT2310A_API_STOP (1<<4) // 0=API go on, 1=stop API + #define CMT2310A_SPI_3W_EN (1<<3) // 0=select SPI-4, 1=select SPI-3 + + #define CMT2310A_nIRQ_SEL (7<<0) //masker + #define CMT2310A_nIRQ_INT1 (0<<0) // nIRQ as INT1 + #define CMT2310A_nIRQ_INT2 (1<<0) // nIRQ as INT2 + #define CMT2310A_nIRQ_DCLK (2<<0) // nIRQ as DCLK + #define CMT2310A_nIRQ_DOUT (3<<0) // nIRQ as DOUT + #define CMT2310A_nIRQ_TCXO (4<<0) // nIRQ as TCXO control pin + #define CMT2310A_nIRQ_DIN (5<<0) // nIRQ as DIN (TX_DIN) + + #define CMT2310A_CTL_REG_08 0x08 //API Command interface + #define CMT2310A_API_CMD_REG 0x08 + + #define CMT2310A_CTL_REG_09 0x09 + #define CMT2310A_API_CMD_FLAG (1<<7) //API Command flag + #define CMT2310A_API_RESP_MASK 0x7F //API Respond value + + #define CMT2310A_CTL_REG_10 0x0A // radio status register (-RO) + #define CMT2310A_CHIP_MODE_STA_REG 0x0A // + #define CMT2310A_STATE_IS_IDLE 0x00 // radio is in idle + #define CMT2310A_STATE_IS_SLEEP 0x81 // radio is in sleep + #define CMT2310A_STATE_IS_READY 0x82 // radio is in ready + #define CMT2310A_STATE_IS_RFS 0x84 // radio is in RFS + #define CMT2310A_STATE_IS_TFS 0x88 // radio is in TFS + #define CMT2310A_STATE_IS_RX 0x90 // radio is in RX + #define CMT2310A_STATE_IS_TX 0xA0 // radio is in TX + + #define CMT2310A_CTL_REG_11 0x0B // auto frequencry hopping done times + // range 0-63 + + #define CMT2310A_CTL_REG_12 0x0C // auto frequencry hopping channel space + #define CMT2310A_FREQ_SPACE_REG 0x0C + + #define CMT2310A_CTL_REG_13 0x0D // auto frequencry hopping times + #define CMT2310A_FREQ_TIMES_REG 0x0D // range 1-64(n+1) + + #define CMT2310A_CTL_REG_14 0x0E // fifo status interrupt control register + #define CMT2310A_RX_FIFO_FULL_EN (1<<7) // 0=disable, 1=enable rx fifo full interrupt + #define CMT2310A_RX_FIFO_NMTY_EN (1<<6) // 0=disable, 1=enable rx fifo non-empty interrupt + #define CMT2310A_RX_FIFO_TH_EN (1<<5) // 0=disable, 1=enable rx fifo threshold interrupt + #define CMT2310A_RX_FIFO_OVF_EN (1<<3) // 0=disable, 1=enable rx fifo overflow interrupt + #define CMT2310A_TX_FIFO_FULL_EN (1<<2) // 0=disable, 1=enable tx fifo full interrupt + #define CMT2310A_TX_FIFO_NMTY_EN (1<<1) // 0=disable, 1=enable tx fifo non-empty interrupt + #define CMT2310A_TX_FIFO_TH_EN (1<<0) // 0=disable, 1=enable tx fifo threshold interrupt + + #define CMT2310A_CTL_REG_15 0x0F // antenna diversity indicate + #define CMT2310A_ANT_INSTR (1<<0) // indicate antenna diversity lock which antenna + + + #define CMT2310A_CTL_REG_16 0x10 // interrupt1 selection + #define CMT2310A_INT1_SEL_REG 0x10 + #define CMT2310A_INT1_SEL_MASK 0x3F + + #define CMT2310A_CTL_REG_17 0x11 // interrupt2 selection + #define CMT2310A_INT2_SEL_REG 0x11 + #define CMT2310A_INT1_POLAR (1<<7) // int1 polar selection, 0=high acitve, 1=low acitve; + #define CMT2310A_INT2_POLAR (1<<6) // int1 polar selection, 0=high acitve, 1=low acitve; + #define CMT2310A_INT2_SEL_MASK 0x3F + + #define CMT2310A_INT_MIX (0<<0) // all interrupt mixed together + #define CMT2310A_INT_ANT_LOCK (1<<0) // antenna locked + #define CMT2310A_INT_RSSI_PJD_VALID (2<<0) // rssi and/or pjd valid + #define CMT2310A_INT_PREAM_PASS (3<<0) // preamble detected + #define CMT2310A_INT_SYNC_PASS (4<<0) // sync word detected + #define CMT2310A_INT_ADDR_PASS (5<<0) // node address detected + #define CMT2310A_INT_CRC_PASS (6<<0) // crc ok detected + #define CMT2310A_INT_PKT_OK (7<<0) // packet received detected + #define CMT2310A_INT_PKT_DONE (8<<0) // packet received detected, even wrong packet or collision + #define CMT2310A_INT_SLEEP_TMO (9<<0) // sleep timer time-out + #define CMT2310A_INT_RX_TMO (10<<0) // rx timer time-out + #define CMT2310A_INT_RX_FIFO_NMTY (11<<0) // rx fifo non-empty + #define CMT2310A_INT_RX_FIFO_TH (12<<0) // rx fifo threshold + #define CMT2310A_INT_RX_FIFO_FULL (13<<0) // rx fifo full + #define CMT2310A_INT_RX_FIFO_WBYTE (14<<0) // rx fifo write byte trigger + #define CMT2310A_INT_RX_FIFO_OVF (15<<0) // rx fifo overflow + #define CMT2310A_INT_TX_DONE (16<<0) // tx done + #define CMT2310A_INT_TX_FIFO_NMTY (17<<0) // tx fifo non-empty + #define CMT2310A_INT_TX_FIFO_TH (18<<0) // tx fifo threshold + #define CMT2310A_INT_TX_FIFO_FULL (19<<0) // tx fifo full + #define CMT2310A_INT_STATE_IS_READY (20<<0) // state is ready + #define CMT2310A_INT_STATE_IS_FS (21<<0) // state is FS + #define CMT2310A_INT_STATE_IS_RX (22<<0) // state is rx + #define CMT2310A_INT_STATE_IS_TX (23<<0) // state is tx + #define CMT2310A_INT_LBD_STATUS (24<<0) // LBD status + #define CMT2310A_INT_API_CMD_FAILED (25<<0) // API Command failed + #define CMT2310A_INT_API_DONE (26<<0) // API execute finish + #define CMT2310A_INT_TX_DC_DONE (27<<0) // ?? + #define CMT2310A_INT_ACK_RECV_FAILED (28<<0) // ack recieve failed + #define CMT2310A_INT_TX_RESEND_DONE (29<<0) // tx re-send done + #define CMT2310A_INT_NACK_RECV (30<<0) // non-ack received + #define CMT2310A_INT_SEQ_MATCH (31<<0) // sequence number match + #define CMT2310A_INT_CSMA_DONE (32<<0) // CSMA done + #define CMT2310A_INT_CCA_STATUS (33<<0) // CCA status match + + + #define CMT2310A_CTL_REG_18 0x12 // interrupt enable control 1 + #define CMT2310A_INT_CTL1_REG 0x12 + #define CMT2310A_SLEEP_TMO_EN (1<<7) // 0=disable, 1=enable sleep timer time-out + #define CMT2310A_RX_TMO_EN (1<<6) // 0=disable, 1=enable rx timer time-out + #define CMT2310A_TX_DONE_EN (1<<5) // 0=disable, 1=enable tx done + #define CMT2310A_PREAM_PASS_EN (1<<4) // 0=disable, 1=enable preamble detect + #define CMT2310A_SYNC_PASS_EN (1<<3) // 0=disable, 1=enable syncword detect + #define CMT2310A_ADDR_PASS_EN (1<<2) // 0=disable, 1=enable node address detect + #define CMT2310A_CRC_PASS_EN (1<<1) // 0=disable, 1=enable packet crc detect + #define CMT2310A_PKT_DONE_EN (1<<0) // 0=disable, 1=enable packet received done + + #define CMT2310A_CTL_REG_19 0x13 // interrupt enable control 2 + #define CMT2310A_INT3_POLAR (1<<7) // int1 polar selection, 0=high acitve, 1=low acitve; + #define CMT2310A_PD_FIFO (1<<6) // 0=retain fifo in sleep, 1=not retain fifo in sleep + #define CMT2310A_FIFO_TH_BIT8 (1<<5) // fifo threshold bit8 + #define CMT2310A_FIFO_AUTO_CLR_RX_EN (1<<4) // 0=not clear fifo, 1=clear fifo, when trigger go to rx + #define CMT2310A_FIFO_AUTO_RES_TX_EN (1<<3) // 0=auto restore tx fifo, 1=don't auto restore tx fifo, when tx done. (if TX_PKT_NUM is not 0, should be set this bit) + #define CMT2310A_FIFO_TX_TEST_EN (1<<2) // 0=tx fifo only write, 1=tx fifo can be read. suggest only for testing, normal useage should be clear this bit + #define CMT2310A_FIFO_MERGE_EN (1<<1) // 0=split fifo to tx and rx, 1=fifo merge together + #define CMT2310A_FIFO_TX_RX_SEL (1<<0) // 0=fifo for tx useage, 1=fifo for rx useage, when CMT2310A_FIFO_MERGE_EN=1 + + #define CMT2310A_CTL_REG_20 0x14 // fifo threshold value + #define CMT2310A_FIFO_TH_REG 0x14 + + #define CMT2310A_CTL_REG_21 0x15 // interrupt enable control 3 + #define CMT2310A_RSSI_PJD_VALID_EN (1<<6) // 0=disable, 1=enable RSSI and/or PJD valid interrupt + #define CMT2310A_OP_CMD_FAILED_EN (1<<5) // 0=disable, 1=enable API Command failed interrupt + #define CMT2310A_RSSI_COLL_EN (1<<4) // 0=disable, 1=enable signal collision interrupt + #define CMT2310A_PKT_ERR_EN (1<<3) // 0=disable, 1=enable packet recieve error interrupt + #define CMT2310A_LBD_STATUS_EN (1<<2) // 0=disable, 1=enable LBD status interrupt + #define CMT2310A_LBD_STOP_EN (1<<1) // 0=disable, 1=enable LBD stop interrupt + #define CMT2310A_LD_STOP_EN (1<<0) // 0=disable, 1=enable PLL lock detect interrupt + + #define CMT2310A_CTL_REG_22 0x16 // function enable config 0 + #define CMT2310A_FREQ_HOP_MANU_EN (1<<7) // 0=disable, 1=enable manual frequencry hopping + #define CMT2310A_RX_HOP_PERSIST (1<<6) // 0=finish, 1=on going, Rx auto frequencry hopping + #define CMT2310A_FREQ_SW_STATE (1<<5) // 0=return to READY, 1=return to RFS, for Rx auto frequencry hopping mode, every times after RX time-out state + #define CMT2310A_TX_DATA_INV (1<<4) // 0=don't invert, 1=invert, for TX data input from GPIO + #define CMT2310A_PA_DIFF_SEL (1<<3) // 0=single-end PA, 1=differential-end PA, for CMT2310A need select single-end PA + #define CMT2310A_TRX_SWT_INV (1<<2) // 0=don't invert, 1=invert for TX/RX antenna switch + #define CMT2310A_TRX_SWT_EN (1<<1) // 0=disable, 1=enable TX/RX antenna switch + #define CMT2310A_ANT_LOCK_EN (1<<0) // 0=disable, 1=enable antenna diversity lock interrupt + + #define CMT2310A_CTL_REG_23 0x17 // interrupt enable control 4 + #define CMT2310A_API_DONE_EN (1<<7) // 0=disable, 1=enable API done interrupt + #define CMT2310A_CCA_STATUS_EN (1<<6) // 0=disable, 1=enable CCA status interrupt + #define CMT2310A_CSMA_DONE_EN (1<<5) // 0=disable, 1=enable CSMA done interrupt + #define CMT2310A_TX_DC_DONE_EN (1<<4) // 0=disable, 1=enable TX DutyCycle done interrupt + #define CMT2310A_ACK_RECV_FAILED_EN (1<<3) // 0=disable, 1=enable ACK received failed interrupt + #define CMT2310A_TX_RESEND_DONE_EN (1<<2) // 0=disable, 1=enable TX re-send done interrupt + #define CMT2310A_NACK_RECV_EN (1<<1) // 0=disable, 1=enable no ACK received interrupt + #define CMT2310A_SEQ_MATCH_EN (1<<0) // 0=disable, 1=enable sequence number match interrupt + + #define CMT2310A_CTL_REG_24 0x18 // interrupt flag & clear control 1 + #define CMT2310A_SLEEP_TMO_FLG (1<<5) // sleep timer time-out flag + #define CMT2310A_RX_TMO_FLG (1<<4) // rx timer time-out flag + #define CMT2310A_TX_DONE_FLG (1<<3) // tx done flag + #define CMT2310A_SLEEP_TMO_CLR (1<<2) // set '1' to clear Sleep timer time-out flag + #define CMT2310A_RX_TMO_CLR (1<<1) // set '1' to clear Rx timer time-out flag + #define CMT2310A_TX_DONE_CLR (1<<0) // set '1' to clear TX done flag + + #define CMT2310A_CTL_REG_25 0x19 // interrupt flag & clear control 2 + #define CMT2310A_PREAM_PASS_CLR (1<<4) // set '1' to clear PREAM_PASS flag + #define CMT2310A_SYNC_PASS_CLR (1<<3) // set '1' to clear SYNC_PASS flag + #define CMT2310A_ADDR_PASS_CLR (1<<2) // set '1' to clear ADDR_PASS flag + #define CMT2310A_CRC_PASS_CLR (1<<1) // set '1' to clear CRC_PASS flag + #define CMT2310A_PKT_DONE_CLR (1<<0) // set '1' to clear PKT_DONE flag + + #define CMT2310A_CTL_REG_26 0x1A // interrupt flag & clear control 3 (-RO) + #define CMT2310A_SYNC1_PASS_FLG (1<<5) // sync-word1 match interrupt flag + #define CMT2310A_PREAM_PASS_FLG (1<<4) // preamlbe pass interrupt flag + #define CMT2310A_SYNC_PASS_FLG (1<<3) // sync-word match interrupt flag + #define CMT2310A_ADDR_PASS_FLG (1<<2) // node address match interrupt flag + #define CMT2310A_CRC_PASS_FLG (1<<1) // packet crc pass interrupt flag + #define CMT2310A_PKT_DONE_FLG (1<<0) // packet done interrupt flag + + #define CMT2310A_CTL_REG_27 0x1B // fifo control 1, fifo clear + #define CMT2310A_TX_FIFO_RESTORE (1<<2) // 0=disable, 1=enable + #define CMT2310A_RX_FIFO_CLR (1<<1) // set '1' to clear Rx FIFO + #define CMT2310A_TX_FIFO_CLR (1<<0) // set '1' to clear Tx FIFO + + #define CMT2310A_CTL_REG_28 0x1C // fifo control 2, fifo flag (-RO) + #define CMT2310A_RX_FIFO_FULL_FLG (1<<7) // + #define CMT2310A_RX_FIFO_NMTY_FLG (1<<6) // + #define CMT2310A_RX_FIFO_TH_FLG (1<<5) // + #define CMT2310A_RX_FIFO_OVF_FLG (1<<3) // + #define CMT2310A_TX_FIFO_FULL_FLG (1<<2) // + #define CMT2310A_TX_FIFO_NMTY_FLG (1<<1) // + #define CMT2310A_TX_FIFO_TH_FLG (1<<0) // + + #define CMT2310A_CTL_REG_29 0x1D // auxrl function clear control + #define CMT2310A_ANT_LOCK_CLR (1<<4) // set '1' to clear antenna lock + #define CMT2310A_OP_CMD_FAILED_CLR (1<<3) // set '1' to clear command operate failed + #define CMT2310A_RSSI_COLL_CLR (1<<2) // set '1' to clear rssi collision + #define CMT2310A_PKT_ERR_CLR (1<<1) // set '1' to clear packet receive error + #define CMT2310A_LBD_STATUS_CLR (1<<0) // set '1' to clear LBD status + + #define CMT2310A_CTL_REG_30 0x1E // auxrl function flag (-RO) + #define CMT2310A_ANT_LOCK_FLG (1<<4) // + #define CMT2310A_OP_CMD_FAILED_FLG (1<<3) // + #define CMT2310A_RSSI_COLL_FLG (1<<2) // + #define CMT2310A_PKT_ERR_FLG (1<<1) // + #define CMT2310A_LBD_STATUS_FLG (1<<0) // + + #define CMT2310A_CTL_REG_31 0x1F // mac function clear control + #define CMT2310A_API_DONE_CLR (1<<7) // set '1' to clear API done + #define CMT2310A_CCA_STATUS_CLR (1<<6) // set '1' to clear CCA status + #define CMT2310A_CSMA_DONE_CLR (1<<5) // set '1' to clear CSMA done + #define CMT2310A_TX_DC_DONE_CLR (1<<4) // set '1' to clear TX_DC_DONE + #define CMT2310A_ACK_RECV_FAILED_CLR (1<<3) // set '1' to clear ACK receive failed + #define CMT2310A_TX_RESEND_DONE_CLR (1<<2) // set '1' to clear Tx resend done + #define CMT2310A_NACK_RECV_CLR (1<<1) // set '1' to clear NACK receive + #define CMT2310A_SEQ_MATCH_CLR (1<<0) // set '1' to clear sequence number match + + #define CMT2310A_CTL_REG_32 0x20 // mac function flag (-RO) + #define CMT2310A_API_DONE_FLG (1<<7) // + #define CMT2310A_CCA_STATUS_FLG (1<<6) // + #define CMT2310A_CSMA_DONE_FLG (1<<5) // + #define CMT2310A_TX_DC_DONE_FLG (1<<4) // + #define CMT2310A_ACK_RECV_FAILED_FLG (1<<3) // + #define CMT2310A_TX_RESEND_DONE_FLG (1<<2) // + #define CMT2310A_NACK_RECV_FLG (1<<1) // + #define CMT2310A_SEQ_MATCH_FLG (1<<0) // + + #define CMT2310A_CTL_REG_33 0x21 // RSSI value minimum (-RO) + #define CMT2310A_RSSI_MIN_REG 0x21 + + #define CMT2310A_CTL_REG_34 0x22 // RSSI value (-RO) + #define CMT2310A_RSSI_REG 0x22 + + #define CMT2310A_CTL_REG_35 0x23 // LBD value (-RO) + #define CMT2310A_LBD_REG 0x23 + + #define CMT2310A_CTL_REG_36 0x24 // temperature value (-RO) + #define CMT2310A_TEMP_REG 0x24 + + #define CMT2310A_CTL_REG_37 0x25 // frequence channel current active (-RO) + #define CMT2310A_FREQ_CHANL_ACT_REG 0x25 + + #define CMT2310A_CTL_REG_38 0x26 // sequence number tx out[7:0] (-RO) + #define CMT2310A_CTL_REG_39 0x27 // sequence number tx out[15:8] (-RO) + #define CMT2310A_SEQNUM_TX_OUT_L_REG 0x26 + #define CMT2310A_SEQNUM_TX_OUT_H_REG 0x27 +//--------------------------------- packet config ----------------------------- + #define CMT2310A_CTL_REG_40 0x28 // rx preamble size[4:0] + preamble length unit + data mode[1:0] + #define CMT2310A_RX_PREAM_SIZE_MASK 0xF8 // rx preamble detect length, 0=don't detect + #define CMT2310A_PREAM_LENG_UNIIT (1<<2) // 0=8bits/unit, 1=4bits/unit (nibble) + + #define CMT2310A_DATA_MODE_MASK (3<<0) + #define CMT2310A_DIRECT_MODE (0<<0) // Direct mode + #define CMT2310A_PACKET_MODE (2<<0) // Packet mode + + #define CMT2310A_CTL_REG_41 0x29 // tx preamble size[7:0] + #define CMT2310A_CTL_REG_42 0x2A // tx preamble size[15:8] + #define CMT2310A_TX_PREAM_SIZE_L_REG 0x29 // when TX_PREAM_SIZE=0, means do not send preamble + #define CMT2310A_TX_PREAM_SIZE_H_REG 0x2A + + #define CMT2310A_CTL_REG_43 0x2B // preamble value + #define CMT2310A_PREAM_VALUE_REG 0x2B // when PREAM_LENG_UNIIT = 0, 8bits active + // when PREAM_LENG_UNIIT = 1, 4bits(LSB) active + #define CMT2310A_CTL_REG_44 0x2C // sync control, sync_mode_sel + sync_tolerance[2:0] + sync_size[2:0] + sync_man_en + #define CMT2310A_SYNC_CTL_REG 0x2C + #define CMT2310A_SYNC_MODE_SEL (1<<7) // 0=compatible S2LP, 1=compatible 802.15.4 + #define CMT2310A_SYNC_TOL_MASK (7<<4) + #define CMT2310A_SYNC_SIZE_MASK (7<<1) // n+1 for SyncWord length + #define CMT2310A_SYNC_MAN_EN (1<<0) // 0=disable, 1=enable SyncWord manchester encoding + + #define CMT2310A_CTL_REG_45 0x2D // sync value 0 [7:0] send last + #define CMT2310A_SYNC_VALUE_7_REG 0x2D + #define CMT2310A_CTL_REG_46 0x2E // sync value 1 [15:8] + #define CMT2310A_SYNC_VALUE_6_REG 0x2E + #define CMT2310A_CTL_REG_47 0x2F // sync value 2 [23:16] + #define CMT2310A_SYNC_VALUE_5_REG 0x2F + #define CMT2310A_CTL_REG_48 0x30 // sync value 3 [31:24] + #define CMT2310A_SYNC_VALUE_4_REG 0x30 + #define CMT2310A_CTL_REG_49 0x31 // sync value 4 [39:32] + #define CMT2310A_SYNC_VALUE_3_REG 0x31 + #define CMT2310A_CTL_REG_50 0x32 // sync value 5 [47:40] + #define CMT2310A_SYNC_VALUE_2_REG 0x32 + #define CMT2310A_CTL_REG_51 0x33 // sync value 6 [55:48] + #define CMT2310A_SYNC_VALUE_1_REG 0x33 + #define CMT2310A_CTL_REG_52 0x34 // sync value 7 [63:56] send first + #define CMT2310A_SYNC_VALUE_0_REG 0x34 + + #define CMT2310A_CTL_REG_53 0x35 // sync fec value 0 [7:0] + #define CMT2310A_FEC_SYNC_7_REG 0x35 + #define CMT2310A_CTL_REG_54 0x36 // sync fec value 1 [15:8] + #define CMT2310A_FEC_SYNC_6_REG 0x36 + #define CMT2310A_CTL_REG_55 0x37 // sync fec value 2 [23:16] + #define CMT2310A_FEC_SYNC_5_REG 0x37 + #define CMT2310A_CTL_REG_56 0x38 // sync fec value 3 [31:24] + #define CMT2310A_FEC_SYNC_4_REG 0x38 + #define CMT2310A_CTL_REG_57 0x39 // sync fec value 4 [39:32] + #define CMT2310A_FEC_SYNC_3_REG 0x39 + #define CMT2310A_CTL_REG_58 0x3A // sync fec value 5 [47:40] + #define CMT2310A_FEC_SYNC_2_REG 0x3A + #define CMT2310A_CTL_REG_59 0x3B // sync fec value 6 [55:48] + #define CMT2310A_FEC_SYNC_1_REG 0x3B + #define CMT2310A_CTL_REG_60 0x3C // sync fec value 7 [63:56] + #define CMT2310A_FEC_SYNC_0_REG 0x3C + + #define CMT2310A_CTL_REG_61 0x3D // payload length [7:0] + #define CMT2310A_CTL_REG_62 0x3E // payload length [15:8] + #define CMT2310A_PAYLOAD_LENGTH_L_REG 0x3D + #define CMT2310A_PAYLOAD_LENGTH_H_REG 0x3E + + #define CMT2310A_CTL_REG_63 0x3F // packet config 1, interleave_en + x + length_size + piggybacking_en + x + addr_leng_conf + payload_bit_order + pkt_type + #define CMT2310A_INTERLEAVE_EN (1<<7) // 0=disable, 1=enable interleave + #define CMT2310A_LENGTH_SIZE (1<<5) // 0=1Byte, for up to 255 bytes variable length packet， + // 1=2Bytes, for up to 65535 bytes variable length packet + #define CMT2310A_PAGGYBACKING_EN (1<<4) // 0=disable, 1=enable for auto paggy backing payload for auto-ack + #define CMT2310A_ADDR_FIELD_EN (1<<3) // 0=disable, 1=enable for node address field + #define CMT2310A_ADDR_LEN_CONF (1<<2) // 0=node address before length filed, 1=node address after length filed. Note! It is affect payload length + #define CMT2310A_PAYLOAD_BIT_ORDER (1<<1) // 0=MSB first, 1=LSB first for decode (payload+crc filed) + #define CMT2310A_PKT_TYPE (1<<0) // 0=fixed length packet, 1=variable length packet + + #define CMT2310A_CTL_REG_64 0x40 // packet config 2, sync_value_sel + addr_split_mode + addr_free_en + addr_err_mask + addr_size[1:0] + addr_det_mode[1:0] + #define CMT2310A_SYNC_VALUE_SEL (1<<7) // 0=select SYNC_VALUE, 1=select SYNC_FEC_VALUE, only for TX used + #define CMT2310A_ADDR_SPLIT_MODE (1<<6) // 0=only DEST_ADDR filed active, 1=DEST_ADDR+SRC_ADDR filed both active + #define CMT2310A_ADDR_FREE_EN (1<<5) // 0=disable, 1=enable ADDR detect stand-alone + #define CMT2310A_ADDR_ERR_MASK (1<<4) // 0=allow, 1=not allow for reset decoding when ADDR mis-matching + #define CMT2310A_ADDR_SIZE_MASK (3<<2) // + + #define CMT2310A_ADDR_DET_MODE_MASK (3<<0) + #define CMT2310A_ADDR_DET_DISABLE (0<<0) // disable node address detect + #define CMT2310A_ADDR_DET_MATCH (1<<0) // rx only detect ADDR_VALUE, tx send ADDR_VALUE + #define CMT2310A_ADDR_DET_BOARDCAST_0 (2<<0) // rx detect ADDR_VALUE & all-0, tx send ADDR_VALUE + #define CMT2310A_ADDR_DET_BOARDCAST_ALL (3<<0) // rx detect ADDR_VALUE & all-0 & all-1, tx send ADDR_VALUE + + + #define CMT2310A_CTL_REG_65 0x41 // SRC_ADDR [7:0] + #define CMT2310A_CTL_REG_66 0x42 // SRC_ADDR [15:8] + #define CMT2310A_SRC_ADDR_L_REG 0x41 + #define CMT2310A_SRC_ADDR_H_REG 0x42 + + #define CMT2310A_CTL_REG_67 0x43 // DEST_ADDR [7:0] + #define CMT2310A_CTL_REG_68 0x44 // DEST_ADDR [15:8] + #define CMT2310A_DEST_ADDR_L_REG 0x43 + #define CMT2310A_DEST_ADDR_H_REG 0x44 + + #define CMT2310A_CTL_REG_69 0x45 // SRC_BITMASK [7:0] + #define CMT2310A_CTL_REG_70 0x46 // SRC_BITMASK [15:8] + #define CMT2310A_SRC_BITMASK_L_REG 0x45 + #define CMT2310A_SRC_BITMASK_H_REG 0x46 + + #define CMT2310A_CTL_REG_71 0x47 // DEST_BITMASK [7:0] + #define CMT2310A_CTL_REG_72 0x48 // DEST_BITMASK [15:8] + #define CMT2310A_DEST_BITMASK_L_REG 0x47 + #define CMT2310A_DEST_BITMASK_H_REG 0x48 + + #define CMT2310A_CTL_REG_73 0x49 // crc config, crc_size[1:0] + crc_byte_swap + crc_bit_inv + crc_range + crc_refin + crc_bit_order + crc_en + #define CMT2310A_CRC_CFG_REG 0x49 + #define CMT2310A_CRC_SIZE_MASK (3<<6) + #define CMT2310A_CRC_SLE_CRC8 (0<<6) // select crc-8 + #define CMT2310A_CRC_SLE_CRC16 (1<<6) // select crc-16 + #define CMT2310A_CRC_SLE_CRC24 (2<<6) // select crc-24 + #define CMT2310A_CRC_SLE_CRC32 (3<<6) // select crc-32 + + #define CMT2310A_CRC_BYTE_SWAP (1<<5) // crc16 for example, 0=[15:8]+[7:0], 1=[7:0]+[15:8], + #define CMT2310A_CRC_BIT_INV (1<<4) // 0=disable, 1=enable for crc result inver + #define CMT2310A_CRC_RANGE (1<<3) // 0=whole payload, 1=only data + #define CMT2310A_CRC_REFIN (1<<2) // 0=normal bit input flow, 1=inver bit input flow, for byte as unit + #define CMT2310A_CRC_BIT_ORDER (1<<1) // 0=MSB send first, 1=LSB send first + #define CMT2310A_CRC_EN (1<<0) // 0=disable, 1=enable CRC function + + #define CMT2310A_CTL_REG_74 0x4A // crc seed 0 [7:0] + #define CMT2310A_CTL_REG_75 0x4B // crc seed 1 [15:8] + #define CMT2310A_CTL_REG_76 0x4C // crc seed 2 [23:16] + #define CMT2310A_CTL_REG_77 0x4D // crc seed 3 [31:24] + #define CMT2310A_CRC_SEED_0_REG 0x4A + #define CMT2310A_CRC_SEED_1_REG 0x4B + #define CMT2310A_CRC_SEED_2_REG 0x4C + #define CMT2310A_CRC_SEED_3_REG 0x4D + + #define CMT2310A_CTL_REG_78 0x4E // crc polynomial 0 [7:0] + #define CMT2310A_CTL_REG_79 0x4F // crc polynomial 1 [15:8] + #define CMT2310A_CTL_REG_80 0x50 // crc polynomial 2 [23:16] + #define CMT2310A_CTL_REG_81 0x51 // crc polynomial 3 [31:24] + #define CMT2310A_CRC_POLY_0_REG 0x4E + #define CMT2310A_CRC_POLY_1_REG 0x4F + #define CMT2310A_CRC_POLY_2_REG 0x50 + #define CMT2310A_CRC_POLY_3_REG 0x51 + + #define CMT2310A_CTL_REG_82 0x52 // coding config, crc_refout + whiten_seed[8] + whiten_seed_type + whiten_type[1:0] + whiten_en + manch_type + manch_en + #define CMT2310A_CRC_REFOUT (1<<7) // 0=MSB->LSB, 1=LSB->MSB, crc result turn over, byte as unit + #define CMT2310A_WHITEN_SEED_B8 (1<<6) // whiten_seed[8] + #define CMT2310A_WHITEN_SEED_TYPE (1<<5) // 0=compatible A7139 PN7 seed, 1=PN7 seed by whien_seed + + #define CMT2310A_WHITEN_TYPE_MASK (3<<3) + #define CMT2310A_WHITEN_PN9_CCITT (0<<3) // whiten type select PN9 CCITT + #define CMT2310A_WHITEN_PN9_IBM (1<<3) // whiten type select PN9 IBM + #define CMT2310A_WHITEN_PN7 (2<<3) // whiten type select PN7 + + #define CMT2310A_WHITEN_EN (1<<2) // 0=disable, 1=enable whien encoding/decoding + + #define CMT2310A_MANCH_TYPE (1<<1) // 0= 2'b01 as logic'1', 2'b10 as logic'0' + // 1= 2'b10 as logic'1', 2'b01 as logic'0' + + #define CMT2310A_MANCH_EN (1<<0) // 0=disable, 1=enable manchester encoding/decoding + + #define CMT2310A_CTL_REG_83 0x53 // whiten seed [7:0] + #define CMT2310A_WHITEN_SEED_REG 0x53 + + #define CMT2310A_CTL_REG_84 0x54 // packet config 3, crc_err_clr_fifo_en + fcs2_en + seqnum_match_en + seqnum_size + seqnum_auto_inc + seqnum_en + tx_prefix_type[1:0] + #define CMT2310A_CRCERR_CLR_FIFO_EN (1<<7) // 0=not clear, 1=clear Rx FIFO, when receive packet with CRC mis-matching + #define CMT2310A_FCS2_EN (1<<6) // 0=disable, 1=enable FCS2 filed + #define CMT2310A_SEQNUM_MATCH_EN (1<<5) // 0=disable, 1=enable matching for TX_ACK used, receive ack packet matching seqnum number which sent by local + #define CMT2310A_SEQNUM_SIZE (1<<4) // 0=1Byte, 1=2Byte for sequence number filed + #define CMT2310A_SEQNUM_AUTO_INC (1<<3) // 0=disable, 1=enable sequence number auto increase in TX, step=1 + #define CMT2310A_SEQNUM_EN (1<<2) // 0=disable, 1=enable sequence number filed (FCS1) + + #define CMT2310A_TX_PREFIX_TYPE_MASK (3<<0) + #define CMT2310A_TX_PREFIX_IS_0 (0<<0) // tx prefix = 0 + #define CMT2310A_TX_PREFIX_IS_1 (1<<0) // tx prefix = 1 + #define CMT2310A_TX_PREFIX_IS_PREAM (2<<0) // tx prefix = preamble + + + + #define CMT2310A_CTL_REG_85 0x55 // tx packet number [7:0] + #define CMT2310A_CTL_REG_86 0x56 // tx packet number [15:8] + #define CMT2310A_TX_PKT_NUM_L_REG 0x55 + #define CMT2310A_TX_PKT_NUM_H_REG 0x56 + + #define CMT2310A_CTL_REG_87 0x57 // sequence number tx inital value [7:0] + #define CMT2310A_CTL_REG_88 0x58 // sequence number tx inital value [15:8] + #define CMT2310A_SEQNUM_TX_IN_L_REG 0x57 + #define CMT2310A_SEQNUM_TX_IN_H_REG 0x58 + + #define CMT2310A_CTL_REG_89 0x59 // tx packet gap [7:0] + #define CMT2310A_TX_PKT_GAP_REG 0x59 + + #define CMT2310A_CTL_REG_90 0x5A // Rssi calibrate offset + #define CMT2310A_RSSI_CAL_OFFSET_REG 0x5A + + #define CMT2310A_CTL_REG_91 0x5B // tx side FCS2 filed inital value [7:0] + #define CMT2310A_FCS2_TX_IN_REG 0x5B + + #define CMT2310A_CTL_REG_92 0x5C // rx side FCC2 filed receive value [7:0] (-RO) + #define CMT2310A_FCS2_RX_OUT_REG 0x5C + + #define CMT2310A_CTL_REG_93 0x5D // fec config 1, FEC_TICC + fec_padding_code[12:8] + fec_rcs_nrnsc_sel + fec_en + #define CMT2310A_FEC_TICC (1<<7) // 0=invert, 1=not invert, for FEC ui + #define CMT2310A_FEC_PAD_CODE_H_MASK (0x1F<<2) // fec_padding_code[12:8] + #define CMT2310A_FEC_RSC_NRNSC_SEL (1<<1) // 0=RSC mode, 1=NRNSC mode + #define CMT2310A_FEC_EN (1<<0) // 0=disable, 1=enable FEC encoding/decoding + + #define CMT2310A_CTL_REG_94 0x5E // fec config 2, fec_padding_code[7:0] + #define CMT2310A_FEC_PAD_CODE_L_REG 0x5E + + #define CMT2310A_CTL_REG_95 0x5F // 4-FSK config, 4fsk_3_level[1:0] + 4fsk_2_level[1:0] + 4fsk_1_level[1:0] + 4fsk_0_level[1:0] + #define CMT2310A_MAP_4FSK_LEVEL_REG 0x5F +//--------------------------------- system control config -------------------------------- + #define CMT2310A_CTL_REG_96 0x60 // sysctrl 1, fw_nk_sel + tx_exit_state[2:0] + x + tx_ack_en + tx_dc_persist_en + tx_dc_en + + #define CMT2310A_TX_EXIT_STATE_MASK (7<<4) // tx done exit state masker + #define CMT2310A_TX_EXIT_TO_SLEEP (1<<4) // tx done exit to sleep + #define CMT2310A_TX_EXIT_TO_READY (2<<4) // tx done exit to ready + #define CMT2310A_TX_EXIT_TO_TFS (3<<4) // tx done exit to TFS + #define CMT2310A_TX_EXIT_TO_TX (4<<4) // tx done exit to TX + #define CMT2310A_TX_EXIT_TO_RFS (5<<4) // tx done exit to RFS + #define CMT2310A_TX_EXIT_TO_RX (6<<4) // tx done exit to RX + // others to sleep, & only for packet mode tx done + #define CMT2310A_TX_AUTO_HOP_EN (1<<3) // 0=disable, 1=enable tx auto hopping + #define CMT2310A_TX_ACK_EN (1<<2) // 0=disable, 1=enable tx ack function + #define CMT2310A_TX_DC_PERSIST_EN (1<<1) // 0=auto exit tx duty-cycle when reach TX_DC_TIMES, 1=hold on until set this bit to '0' + #define CMT2310A_TX_DC_EN (1<<0) // 0=disable, 1=enable tx duty-cycle function + + #define CMT2310A_CTL_REG_97 0x61 // sysctrl 2, csma_en + rx_exit_state[2:0] + timer_rx_en + rx_ack_en + rx_auto_hop_en + rx_dc_en + #define CMT2310A_CSMA_EN (1<<7) // 0=disable, 1=enable CSMA + + #define CMT2310A_RX_EXIT_STATE_MASK (7<<4) // rx done exit state masker + #define CMT2310A_RX_EXIT_TO_SLEEP (1<<4) // rx done exit to sleep + #define CMT2310A_RX_EXIT_TO_READY (2<<4) // rx done exit to ready + #define CMT2310A_RX_EXIT_TO_TFS (3<<4) // rx done exit to TFS + #define CMT2310A_RX_EXIT_TO_TX (4<<4) // rx done exit to TX + #define CMT2310A_RX_EXIT_TO_RFS (5<<4) // rx done exit to RFS + #define CMT2310A_RX_EXIT_TO_RX (6<<4) // rx done exit to RX + // others to sleep, & only for packet mode rx done + #define CMT2310A_RX_TIMER_EN (1<<3) // 0=disable, 1=enable rx timer + #define CMT2310A_RX_ACK_EN (1<<2) // 0=disable, 1=enable rx ack function + #define CMT2310A_RX_AUTO_HOP_EN (1<<1) // 0=disable, 1=enable rx auto hopping function + #define CMT2310A_RX_DC_EN (1<<0) // 0=disable, 1=enable rx duty-cycle function + + #define CMT2310A_CTL_REG_98 0x62 // sysctrl 3, pkt_done_exit_en + rx_hop_slp_mode[2:0] + slp_mode[3:0] + #define CMT2310A_PKT_DONE_EXIT_EN (1<<7) // 0=keep current, 1=depends on RX_EXIT_STATE + #define CMT2310A_RX_HOP_SLP_MODE_MASK (7<<4) // rx hopping supper low power mode selection + #define CMT2310A_SLP_MODE_MASK (15<<0) // rx supper low power mode selection + + #define CMT2310A_CTL_REG_99 0x63 // sysctrl 4, timer_m_sleep [7:0] + #define CMT2310A_CTL_REG_100 0x64 // sysctrl 5, timer_m_sleep [10:8] + timer_r_sleep [4:0] + #define CMT2310A_SLEEP_TIMER_M_REG 0x63 // Tsleep = M*2^(R+1)*31.25us, R from 0 to 26 + #define CMT2310A_SLEEP_TIMER_R_REG 0x64 + #define CMT2310A_SLEEP_TIMER_M_H_MASK (7<<5) + + #define CMT2310A_CTL_REG_101 0x65 // sysctrl 6, timer_m_rx_T1 [7:0] + #define CMT2310A_CTL_REG_102 0x66 // sysctrl 7, timer_m_rx_T1 [10:8] + timer_r_rx_T1 [4:0] + #define CMT2310A_RX_TIMER_T1_M_REG 0x65 // Trx_t1 = M*2^(R+1)*20us, R from 0 to 21, + #define CMT2310A_RX_TIMER_T1_R_REG 0x66 + #define CMT2310A_RX_TIMER_T1_M_H_MASK (7<<5) + + #define CMT2310A_CTL_REG_103 0x67 // sysctrl 8, timer_m_rx_T2 [7:0] + #define CMT2310A_CTL_REG_104 0x68 // sysctrl 9, timer_m_rx_T2 [10:8] + timer_r_rx_T2 [4:0] + #define CMT2310A_RX_TIMER_T2_M_REG 0x67 // Trx_t1 = M*2^(R+1)*20us, R from 0 to 21, + #define CMT2310A_RX_TIMER_T2_R_REG 0x68 + #define CMT2310A_RX_TIMER_T2_M_H_MASK (7<<5) + + #define CMT2310A_CTL_REG_105 0x69 // sysctrl 10, tx_allow_rx + pup_done_state + timer_random_mode[1:0] + timer_sleep_en + rx_allow_tx + lfclk_sel + lfclk_out_en(lfosc/lfxo) + + #define CMT2310A_TIMER_RAND_MODE_MASK (3<<4) // CSMA mode, CSMA sleep timer random selection: + #define CMT2310A_TIMER_RAND_R (0<<4) // select random R + #define CMT2310A_TIMER_RAND_M (1<<4) // select random M + #define CMT2310A_TIMER_RAND_M_R (2<<4) // select random both R & M + #define CMT2310A_TIMER_RAND_OFF (3<<4) // select random off, used fixed value + + #define CMT2310A_SLEEP_TIMER_EN (1<<3) // 0=disable, 1=enable sleep timer + #define CMT2310A_LFCLK_SEL (1<<1) // 0=internal LFOSC, 1=LFXO (32768Hz) + #define CMT2310A_LFCLK_OUT_EN (1<<0) // 0=disable, 1=enable GPIO4 for LFCLK out, priority lower than DIG_CLKOUT_EN, but higher than GPIO4_SEL + + #define CMT2310A_CTL_REG_106 0x6A // sysctrl 11, cca_mode[2:0] + csma_persist_en + cca_int_sel[1:0] + cca_win_sel[1:0] + #define CMT2310A_CSMA_CCA_MODE_MASK (7<<5) + #define CMT2310A_CSMA_CCA_DISABLE (0<<5) // 0= channel is always idle + #define CMT2310A_CSMA_CCA_RSSI (1<<5) // 1= active >=1 of 4 times detect window, by Rssi + #define CMT2310A_CSMA_CCA_PJD (2<<5) // 2= active >=1 of 4 times detect window, by PJD + #define CMT2310A_CSMA_CCA_RSSI_PJD (3<<5) // 3= active >=1 of 4 times detect window, by PJD or Rssi + #define CMT2310A_CSMA_CCA_SYNC (4<<5) // 4= detected sync word + #define CMT2310A_CSMA_CCA_SYNC_RSSI (5<<5) // 5= detected sync word, or active >=1 of 4 times detect window, by Rssi + #define CMT2310A_CSMA_CCA_SYNC_PJD (6<<5) // 6= detected sync word, or active >=1 of 4 times detect window, by PJD + #define CMT2310A_CSMA_CCA_SYNC_RSSI_PJD (7<<5) // 7= detected sync word, or active >=1 of 4 times detect window, by PJD or Rssi + + #define CMT2310A_CSMA_PERSIST_EN (1<<4) // 0=auto exit when reach max & channel still busy, 1=keep on work until send out + + #define CMT2310A_CCA_INT_SEL_MASK (3<<2) + #define CMT2310A_CCA_INT_BY_PJD (0<<2) // CSMA_CCA interrupt condition by PJD + #define CMT2310A_CCA_INT_BY_RSSI (1<<2) // CSMA_CCA interrupt condition by RSSI + #define CMT2310A_CCA_INT_BY_PJD_RSSI (2<<2) // CSMA_CCA interrupt condition by PJD & RSSI + + #define CMT2310A_CCA_WIN_SEL_MASK (3<<0) + #define CMT2310A_CCA_WIN_32_SYMBOL (0<<0) // CSMA detect window select 32symbols + #define CMT2310A_CCA_WIN_64_SYMBOL (1<<0) // CSMA detect window select 64symbols + #define CMT2310A_CCA_WIN_128_SYMBOL (2<<0) // CSMA detect window select 128symbols + #define CMT2310A_CCA_WIN_256_SYMBOL (3<<0) // CSMA detect window select 256symbols + + + #define CMT2310A_CTL_REG_107 0x6B // sysctrl 12, timer_m_rx_csma [7:0] + #define CMT2310A_CTL_REG_108 0x6C // sysctrl 13, timer_m_rx_csma [10:8] + timer_r_rx_csma [4:0] + #define CMT2310A_RX_TIMER_CSMA_M_REG 0x6B // Trx_csma = M*2^(R+1)*20us, R from 0 to 21, + #define CMT2310A_RX_TIMER_CSMA_R_REG 0x6C + #define CMT2310A_RX_TIMER_CSMA_M_H_MASK (15<<4) + + #define CMT2310A_CTL_REG_109 0x6D // low battery detect threshold, lbd_th[7:0] + #define CMT2310A_LBD_TH_REG 0x6D + + #define CMT2310A_CTL_REG_110 0x6E // sysctrl 14, tx_dc_timer [7:0] + #define CMT2310A_TX_DC_TIMES_REG 0x6E + + #define CMT2310A_CTL_REG_111 0x6F // + #define CMT2310A_LENGTH_MODE (1<<7) // 0=normal, length filed as payload length, 1=as Wi-SUN mode + #define CMT2310A_WISUN_ALLIN (1<<6) + #define CMT2310A_WHITEN_WISUN (1<<5) + #define CMT2310A_WISUN_MS (1<<4) + #define CMT2310A_WISUN_FCS (1<<1) + #define CMT2310A_WISUN_DW (1<<0) + + #define CMT2310A_CTL_REG_112 0x70 // sysctrl 15, tx_dc_done_timer [7:0] (-RO) + #define CMT2310A_TX_DC_DONE_TIMES_REG 0x70 + + #define CMT2310A_CTL_REG_113 0x71 // sysctrl 16, tx_resend_timer [7:0] + #define CMT2310A_TX_RS_TIMES_REG 0x71 + + #define CMT2310A_CTL_REG_114 0x72 // sysctrl 17, tx_resend_done_timer [7:0] (-RO) + #define CMT2310A_TX_RS_DONE_TIMES_REG 0x72 + + #define CMT2310A_CTL_REG_115 0x73 // sysctrl 18, csma_timer [7:0] + #define CMT2310A_CSMA_TIMES_REG 0x73 + + #define CMT2310A_CTL_REG_116 0x74 // sysctrl 19, csma_done_timer [7:0] (-RO) + #define CMT2310A_CSMA_DONE_TIMES_REG 0x74 + + #define CMT2310A_CTL_REG_117 0x75 + + #define CMT2310A_CTL_REG_118 0x76 // sysctrl 20, timer_m_sleep_csma [7:0] + #define CMT2310A_CTL_REG_119 0x77 // sysctrl 21, timer_m_sleep_csma [10:8] + timer_r_sleep_csma [4:0] + #define CMT2310A_SLEEP_TIMER_CSMA_M_REG 0x76 // Tsleep_timer_csma = M*2^(R+1)*31.25us, R from 0 to 26, + #define CMT2310A_SLEEP_TIMER_CSMA_R_REG 0x77 + + #define CMT2310A_FIFO_RW_PORT_REG 0x7A // FIFO R/W interface + #define CMT2310A_FIFO_RW_PORT 0x7A + + #define CMT2310A_CRW_PORT_REG 0x7B + #define CMT2310A_CRW_PORT 0x7B + + #define CMT2310A_CLT_REG_126 0x7E + #define CMT2310A_PAGE_CTL_REG 0x7E // hv_page_sel + #define CMT2310A_PAGE_SEL_MASK (3<<6) + #define CMT2310A_PAGE_0 (0<<6) // 0=page 0 + #define CMT2310A_PAGE_1 (1<<6) // 1=page 1 + #define CMT2310A_PAGE_2 (2<<6) // 2=page 2 + + #define CMT2310A_SOFT_RST 0x7F // soft_reset + + +// --------------------------- CUS PAGE1 defines ----------------------------------------- + #define CMT2310A_CMT_REG_00 0x00 // export by RFPDK + #define CMT2310A_CMT_REG_01 0x01 // export by RFPDK + #define CMT2310A_CMT_REG_02 0x02 // export by RFPDK + #define CMT2310A_CMT_REG_03 0x03 // export by RFPDK + #define CMT2310A_CMT_REG_04 0x04 // export by RFPDK + #define CMT2310A_CMT_REG_05 0x05 // export by RFPDK + #define CMT2310A_CMT_REG_06 0x06 // export by RFPDK + #define CMT2310A_CMT_REG_07 0x07 // export by RFPDK + #define CMT2310A_CMT_REG_08 0x08 // export by RFPDK + #define CMT2310A_CMT_REG_09 0x09 // export by RFPDK + #define CMT2310A_CMT_REG_10 0x0A // export by RFPDK + #define CMT2310A_CMT_REG_11 0x0B // export by RFPDK + #define CMT2310A_CMT_REG_12 0x0C // export by RFPDK + #define CMT2310A_CMT_REG_13 0x0D // export by RFPDK + #define CMT2310A_CMT_REG_14 0x0E // export by RFPDK + #define CMT2310A_CMT_REG_15 0x0F // export by RFPDK + #define CMT2310A_TX_FREQ_REG_00 0x10 // export by RFPDK + #define CMT2310A_TX_FREQ_REG_01 0x11 // export by RFPDK + #define CMT2310A_TX_FREQ_REG_02 0x12 // export by RFPDK + #define CMT2310A_TX_FREQ_REG_03 0x13 // export by RFPDK + #define CMT2310A_TX_MODE_REG_00 0x14 // export by RFPDK + #define CMT2310A_TX_DR_REG_00 0x15 // export by RFPDK + #define CMT2310A_TX_DR_REG_01 0x16 // export by RFPDK + #define CMT2310A_TX_DR_REG_02 0x17 // export by RFPDK + #define CMT2310A_TX_DR_REG_03 0x18 // export by RFPDK + #define CMT2310A_TX_DR_REG_04 0x19 // export by RFPDK + #define CMT2310A_TX_DR_REG_05 0x1A // export by RFPDK + #define CMT2310A_TX_DEV_REG_00 0x1B // export by RFPDK + #define CMT2310A_TX_DEV_REG_01 0x1C // export by RFPDK + #define CMT2310A_TX_DEV_REG_02 0x1D // export by RFPDK + #define CMT2310A_TX_PWR_REG_00 0x1E // export by RFPDK + #define CMT2310A_TX_PWR_REG_01 0x1F // export by RFPDK + #define CMT2310A_TX_PWR_REG_02 0x20 // export by RFPDK + #define CMT2310A_TX_PWR_REG_03 0x21 // export by RFPDK + #define CMT2310A_TX_PWR_REG_04 0x22 // export by RFPDK + #define CMT2310A_TX_PWR_REG_05 0x23 // export by RFPDK + #define CMT2310A_TX_PWR_REG_06 0x24 // export by RFPDK + #define CMT2310A_TX_MISC_REG_00 0x25 // export by RFPDK + #define CMT2310A_TX_MISC_REG_01 0x26 // export by RFPDK + #define CMT2310A_TX_MISC_REG_02 0x27 // export by RFPDK + #define CMT2310A_TX_RESEV_00 0x28 // export by RFPDK + #define CMT2310A_TX_RESEV_01 0x29 // export by RFPDK + #define CMT2310A_TX_RESEV_02 0x2A // export by RFPDK + #define CMT2310A_TX_RESEV_03 0x2B // export by RFPDK + #define CMT2310A_TX_RESEV_04 0x2C // export by RFPDK + #define CMT2310A_TX_RESEV_05 0x2D // export by RFPDK + #define CMT2310A_TX_RESEV_06 0x2E // export by RFPDK + #define CMT2310A_TX_RESEV_07 0x2F // export by RFPDK + #define CMT2310A_RX_FREQ_REG_00 0x30 // export by RFPDK + #define CMT2310A_RX_FREQ_REG_01 0x31 // export by RFPDK + #define CMT2310A_RX_FREQ_REG_02 0x32 // export by RFPDK + #define CMT2310A_RX_FREQ_REG_03 0x33 // export by RFPDK + #define CMT2310A_RX_FREQ_REG_04 0x34 // export by RFPDK + #define CMT2310A_RX_IRF_REG_00 0x35 // export by RFPDK + #define CMT2310A_RX_IRF_REG_01 0x36 // export by RFPDK + #define CMT2310A_RX_IRF_REG_02 0x37 // export by RFPDK + #define CMT2310A_RX_IRF_REG_03 0x38 // export by RFPDK + #define CMT2310A_RX_PWR_REG_00 0x39 // export by RFPDK + #define CMT2310A_RX_PWR_REG_01 0x3A // export by RFPDK + #define CMT2310A_RX_PWR_REG_02 0x3B // export by RFPDK + #define CMT2310A_RX_DR_REG_00 0x3C // export by RFPDK + #define CMT2310A_RX_DR_REG_01 0x3D // export by RFPDK + #define CMT2310A_RX_DR_REG_02 0x3E // export by RFPDK + #define CMT2310A_RX_DR_REG_03 0x3F // export by RFPDK + #define CMT2310A_RX_DR_REG_04 0x40 // export by RFPDK + #define CMT2310A_RX_DR_REG_05 0x41 // export by RFPDK + #define CMT2310A_RX_DR_REG_06 0x42 // export by RFPDK + #define CMT2310A_RX_DR_REG_07 0x43 // export by RFPDK + #define CMT2310A_RX_CDR_REG_00 0x44 // export by RFPDK + #define CMT2310A_RX_CDR_REG_01 0x45 // export by RFPDK + #define CMT2310A_RX_CDR_REG_02 0x46 // export by RFPDK + #define CMT2310A_RX_CDR_REG_03 0x47 // export by RFPDK + #define CMT2310A_RX_CHNL_REG_00 0x48 // export by RFPDK + #define CMT2310A_RX_CHNL_REG_01 0x49 // export by RFPDK + #define CMT2310A_RX_CHNL_REG_02 0x4A // export by RFPDK + #define CMT2310A_RX_AGC_REG_00 0x4B // export by RFPDK + #define CMT2310A_RX_AGC_REG_01 0x4C // export by RFPDK + #define CMT2310A_RX_AGC_REG_02 0x4D // export by RFPDK + #define CMT2310A_RX_AGC_REG_03 0x4E // export by RFPDK + #define CMT2310A_RX_AGC_REG_04 0x4F // export by RFPDK + #define CMT2310A_RX_AGC_REG_05 0x50 // export by RFPDK + #define CMT2310A_RX_AGC_REG_06 0x51 // export by RFPDK + #define CMT2310A_RX_2FSK_REG_00 0x52 // export by RFPDK + #define CMT2310A_RX_2FSK_REG_01 0x53 // export by RFPDK + #define CMT2310A_RX_2FSK_REG_02 0x54 // export by RFPDK + #define CMT2310A_RX_2FSK_REG_03 0x55 // export by RFPDK + #define CMT2310A_RX_AFC_REG_00 0x56 // export by RFPDK + #define CMT2310A_RX_AFC_REG_01 0x57 // export by RFPDK + #define CMT2310A_RX_AFC_REG_02 0x58 // export by RFPDK + #define CMT2310A_RX_AFC_REG_03 0x59 // export by RFPDK + #define CMT2310A_RX_4FSK_REG_00 0x5A // export by RFPDK + #define CMT2310A_RX_4FSK_REG_01 0x5B // export by RFPDK + #define CMT2310A_RX_4FSK_REG_02 0x5C // export by RFPDK + #define CMT2310A_RX_4FSK_REG_03 0x5D // export by RFPDK + #define CMT2310A_RX_OOK_REG_00 0x5E // export by RFPDK + #define CMT2310A_RX_OOK_REG_01 0x5F // export by RFPDK + #define CMT2310A_RX_OOK_REG_02 0x60 // export by RFPDK + #define CMT2310A_RX_OOK_REG_03 0x61 // export by RFPDK + + #define CMT2310A_RX_RSSI_REG_00 0x62 // rf_rssi_reg 0, coll_handle[1:0] + coll_step_sel[1:0] + rssi_update_sel[1:0] + nc + coll_det_en + + #define CMT2310A_COLL_STEP_SEL_MASK (3<<4) + #define CMT2310A_COLL_STEP_SEL_6dB (0<<4) // collision select 6dB + #define CMT2310A_COLL_STEP_SEL_10dB (1<<4) // collision select 10dB + #define CMT2310A_COLL_STEP_SEL_16dB (2<<4) // collision select 16dB + #define CMT2310A_COLL_STEP_SEL_20dB (3<<4) // collision select 20dB + + #define CMT2310A_RSSI_UPDATE_SEL_MASK (3<<2) + #define CMT2310A_RSSI_UPDATE_ALWAYS (0<<2) // rssi update always on + #define CMT2310A_RSSI_UPDATE_PREAM_OK (1<<2) // rssi update by preamble detected + #define CMT2310A_RSSI_UPDATE_SYNC_OK (2<<2) // rssi update by syncword detected + #define CMT2310A_RSSI_UPDATE_PKT_DONE (3<<2) // rssi update by packet done + + #define CMT2310A_COLL_DET_EN (1<<0) // 0=disable, 1=enable collision detect + + #define CMT2310A_RX_RSSI_REG_01 0x63 // rf_rssi_reg 1, rssi_absolute_th[7:0] + #define CMT2310A_RSSI_ABS_TH_REG 0x63 + + #define CMT2310A_RX_DOUT_REG_00 0x64 // rf_dout_reg, nc + nc + nc + dout_adjust_sel[2:0] + dout_adjust_mode + dout_adjust_en + #define CMT2310A_DOUT_ADJUST_SEL_MASK (7<<2) + #define CMT2310A_DOUT_ADJUST_3_33 (0<<2) + #define CMT2310A_DOUT_ADJUST_6_66 (1<<2) + #define CMT2310A_DOUT_ADJUST_9_99 (2<<2) + #define CMT2310A_DOUT_ADJUST_13_32 (3<<2) + #define CMT2310A_DOUT_ADJUST_16_65 (4<<2) + #define CMT2310A_DOUT_ADJUST_19_98 (5<<2) + #define CMT2310A_DOUT_ADJUST_23_21 (6<<2) + #define CMT2310A_DOUT_ADJUST_26_64 (7<<2) + + #define CMT2310A_DOUT_ADJUST_MODE (1<<1) // 0=+1 duty, 1=-1 duty + #define CMT2310A_DOUT_ADJUST_EN (1<<0) // 0=disable, 1=enable dout adjust + + + #define CMT2310A_RX_ANTD_REG_00 0x67 // rf_ant_reg nc + nc + nc + nc + ant_wait_pmb[1:0] + ant_sw_dis + ant_div_en + #define CMT2310A_ANT_WAIT_PMB_MASK (3<<2) + #define CMT2310A_ANT_WAIT_1_5_UNIT (0<<2) // wait preamble size *1.5, when antenna calibrate + #define CMT2310A_ANT_WAIT_2_UNIT (1<<2) // wait preamble size *2, when antenna calibrate + #define CMT2310A_ANT_WAIT_2_5_UNIT (2<<2) // wait preamble size *2.5, when antenna calibrate + #define CMT2310A_ANT_WAIT_3_UNIT (3<<2) // wait preamble size *3, when antenna calibrate + + #define CMT2310A_ANT_SW_DIS (1<<1) // 0=enable, 1=bypass antenna switch + #define CMT2310A_ANT_DIV_EN (1<<0) // 0=disable, 1=enable antenna diversity + +// --------------------------- CUS PAGE2 defines ----------------------------------------- + + #define CMT2310A_FREQ_CHANL_00 0x00 + #define CMT2310A_FREQ_CHANL_01 0x01 + #define CMT2310A_FREQ_CHANL_02 0x02 + #define CMT2310A_FREQ_CHANL_03 0x03 + #define CMT2310A_FREQ_CHANL_04 0x04 + #define CMT2310A_FREQ_CHANL_05 0x05 + #define CMT2310A_FREQ_CHANL_06 0x06 + #define CMT2310A_FREQ_CHANL_07 0x07 + #define CMT2310A_FREQ_CHANL_08 0x08 + #define CMT2310A_FREQ_CHANL_09 0x09 + #define CMT2310A_FREQ_CHANL_10 0x0A + #define CMT2310A_FREQ_CHANL_11 0x0B + #define CMT2310A_FREQ_CHANL_12 0x0C + #define CMT2310A_FREQ_CHANL_13 0x0D + #define CMT2310A_FREQ_CHANL_14 0x0E + #define CMT2310A_FREQ_CHANL_15 0x0F + #define CMT2310A_FREQ_CHANL_16 0x10 + #define CMT2310A_FREQ_CHANL_17 0x11 + #define CMT2310A_FREQ_CHANL_18 0x12 + #define CMT2310A_FREQ_CHANL_19 0x13 + #define CMT2310A_FREQ_CHANL_20 0x14 + #define CMT2310A_FREQ_CHANL_21 0x15 + #define CMT2310A_FREQ_CHANL_22 0x16 + #define CMT2310A_FREQ_CHANL_23 0x17 + #define CMT2310A_FREQ_CHANL_24 0x18 + #define CMT2310A_FREQ_CHANL_25 0x19 + #define CMT2310A_FREQ_CHANL_26 0x1A + #define CMT2310A_FREQ_CHANL_27 0x1B + #define CMT2310A_FREQ_CHANL_28 0x1C + #define CMT2310A_FREQ_CHANL_29 0x1D + #define CMT2310A_FREQ_CHANL_30 0x1E + #define CMT2310A_FREQ_CHANL_31 0x1F + #define CMT2310A_FREQ_CHANL_32 0x20 + #define CMT2310A_FREQ_CHANL_33 0x21 + #define CMT2310A_FREQ_CHANL_34 0x22 + #define CMT2310A_FREQ_CHANL_35 0x23 + #define CMT2310A_FREQ_CHANL_36 0x24 + #define CMT2310A_FREQ_CHANL_37 0x25 + #define CMT2310A_FREQ_CHANL_38 0x26 + #define CMT2310A_FREQ_CHANL_39 0x27 + #define CMT2310A_FREQ_CHANL_40 0x28 + #define CMT2310A_FREQ_CHANL_41 0x29 + #define CMT2310A_FREQ_CHANL_42 0x2A + #define CMT2310A_FREQ_CHANL_43 0x2B + #define CMT2310A_FREQ_CHANL_44 0x2C + #define CMT2310A_FREQ_CHANL_45 0x2D + #define CMT2310A_FREQ_CHANL_46 0x2E + #define CMT2310A_FREQ_CHANL_47 0x2F + #define CMT2310A_FREQ_CHANL_48 0x30 + #define CMT2310A_FREQ_CHANL_49 0x31 + #define CMT2310A_FREQ_CHANL_50 0x32 + #define CMT2310A_FREQ_CHANL_51 0x33 + #define CMT2310A_FREQ_CHANL_52 0x34 + #define CMT2310A_FREQ_CHANL_53 0x35 + #define CMT2310A_FREQ_CHANL_54 0x36 + #define CMT2310A_FREQ_CHANL_55 0x37 + #define CMT2310A_FREQ_CHANL_56 0x38 + #define CMT2310A_FREQ_CHANL_57 0x39 + #define CMT2310A_FREQ_CHANL_58 0x3A + #define CMT2310A_FREQ_CHANL_59 0x3B + #define CMT2310A_FREQ_CHANL_60 0x3C + #define CMT2310A_FREQ_CHANL_61 0x3D + #define CMT2310A_FREQ_CHANL_62 0x3E + #define CMT2310A_FREQ_CHANL_63 0x3F + + #define CMT2310A_CHIP_VERSION_00 0x40 + #define CMT2310A_CHIP_VERSION_01 0x41 + #define CMT2310A_CHIP_VERSION_02 0x42 + +// -------------------------------- Marco defines ----------------------------------------- + #define VAL_BIT0 0x01 + #define VAL_BIT1 0x02 + #define VAL_BIT2 0x04 + #define VAL_BIT3 0x08 + #define VAL_BIT4 0x10 + #define VAL_BIT5 0x20 + #define VAL_BIT6 0x40 + #define VAL_BIT7 0x80 + + #define BIT0 0 + #define BIT1 1 + #define BIT2 2 + #define BIT3 3 + #define BIT4 4 + #define BIT5 5 + #define BIT6 6 + #define BIT7 7 + + //## CMT2310A_CTL_REG_00 registers + #define M_BOOT_MAIN VAL_BIT1 + #define M_POWERUP VAL_BIT0 + + //## CMT2310A_CTL_REG_01 registers + #define M_GO_RXFS VAL_BIT5 + #define M_GO_TXFS VAL_BIT4 + #define M_GO_RX VAL_BIT3 + #define M_GO_TX VAL_BIT2 + #define M_GO_READY VAL_BIT1 + #define M_GO_SLEEP VAL_BIT0 + + //## CMT2310A_CTL_REG_02 registers + #define M_MCU_GPIO_EN VAL_BIT2 + #define M_ANT_DIV_MANU VAL_BIT1 + #define M_ANT_SELECT VAL_BIT0 + + //## CMT2310A_CTL_REG_04 registers + #define M_TX_DIN_EN VAL_BIT6 + #define M_GPIO1_SEL (VAL_BIT5|VAL_BIT4|VAL_BIT3) + #define M_GPIO0_SEL (VAL_BIT2|VAL_BIT1|VAL_BIT0) + + //## CMT2310A_CTL_REG_05 registers + #define M_TX_DIN_SEL (VAL_BIT7|VAL_BIT6) + #define M_GPIO3_SEL (VAL_BIT5|VAL_BIT4|VAL_BIT3) + #define M_GPIO2_SEL (VAL_BIT2|VAL_BIT1|VAL_BIT0) + + //## CMT2310A_CTL_REG_06 registers + #define M_DIG_CLKOUT_EN VAL_BIT6 + #define M_GPIO5_SEL (VAL_BIT5|VAL_BIT4|VAL_BIT3) + #define M_GPIO4_SEL (VAL_BIT2|VAL_BIT1|VAL_BIT0) + + //## CMT2310A_CTL_REG_07 registers + #define M_LFXO_PAD_EN VAL_BIT5 + #define M_API_STOP VAL_BIT4 + #define M_SPI_3W_EN VAL_BIT3 + #define M_NIRQ_SEL (VAL_BIT2|VAL_BIT1|VAL_BIT0) + + //## CMT2310A_CTL_REG_09 registers + #define M_API_CMD_FLAG VAL_BIT7 + #define M_API_RESP (VAL_BIT6|VAL_BIT5|VAL_BIT4|VAL_BIT3|VAL_BIT2|VAL_BIT1|VAL_BIT0) + + //## CMT2310A_CTL_REG_10 registers + #define M_STATE_IS_TX VAL_BIT5 + #define M_STATE_IS_RX VAL_BIT4 + #define M_STATE_IS_TFS VAL_BIT3 + #define M_STATE_IS_RFS VAL_BIT2 + #define M_STATE_IS_READY VAL_BIT1 + #define M_STATE_IS_SLEEP VAL_BIT0 + + //## CMT2310A_CTL_REG_14 registers + #define M_RX_FIFO_FULL_RX_EN VAL_BIT7 + #define M_RX_FIFO_NMTY_RX_EN VAL_BIT6 + #define M_RX_FIFO_TH_RX_EN VAL_BIT5 + #define M_RX_FIFO_OVF_EN VAL_BIT3 + #define M_TX_FIFO_FULL_EN VAL_BIT2 + #define M_TX_FIFO_NMTY_EN VAL_BIT1 + #define M_TX_FIFO_TH_EN VAL_BIT0 + + //## CMT2310A_CTL_REG_15 registers + #define M_ANT_INSTR VAL_BIT0 + + //## CMT2310A_CTL_REG_16 registers + #define M_INT1_SEL (VAL_BIT5|VAL_BIT4|VAL_BIT3|VAL_BIT2|VAL_BIT1|VAL_BIT0) + + //## CMT2310A_CTL_REG_17 registers + #define M_INT1_POLAR VAL_BIT7 + #define M_INT2_POLAR VAL_BIT6 + #define M_INT2_SEL (VAL_BIT5|VAL_BIT4|VAL_BIT3|VAL_BIT2|VAL_BIT1|VAL_BIT0) + + //## CMT2310A_CTL_REG_18 registers + #define M_SLEEP_TMO_EN VAL_BIT7 + #define M_RX_TMO_EN VAL_BIT6 + #define M_TX_DONE_EN VAL_BIT5 + #define M_PREAM_PASS_EN VAL_BIT4 + #define M_SYNC_PASS_EN VAL_BIT3 + #define M_ADDR_PASS_EN VAL_BIT2 + #define M_CRC_PASS_EN VAL_BIT1 + #define M_PKT_DONE_EN VAL_BIT0 + + //## CMT2310A_CTL_REG_19 registers + #define M_PD_FIFO VAL_BIT6 + #define M_FIFO_TH_8 VAL_BIT5 + #define M_FIFO_AUTO_CLR_RX_EN VAL_BIT4 + #define M_FIFO_AUTO_RES_TX_EN VAL_BIT3 + #define M_FIFO_TX_TEST_EN VAL_BIT2 + #define M_FIFO_MERGE_EN VAL_BIT1 + #define M_FIFO_TX_RX_SEL VAL_BIT0 + + //## CMT2310A_CTL_REG_21 registers + #define M_RSSI_PJD_VALID_EN VAL_BIT6 + #define M_OP_CMD_FAILED_EN VAL_BIT5 + #define M_RSSI_COLL_EN VAL_BIT4 + #define M_PKT_ERR_EN VAL_BIT3 + #define M_LBD_STATUS_EN VAL_BIT2 + #define M_LBD_STOP_EN VAL_BIT1 + #define M_LD_STOP_EN VAL_BIT0 + + //## CMT2310A_CTL_REG_22 registers + #define M_FREQ_HOP_MANU_EN VAL_BIT7 + #define M_RX_HOP_PERSIST VAL_BIT5 + #define M_FREQ_SW_STATE VAL_BIT6 + #define M_TX_DATA_INV VAL_BIT4 + #define M_PA_DIFF_SEL VAL_BIT3 + #define M_TRX_SWT_INV VAL_BIT2 + #define M_TRX_SWT_EN VAL_BIT1 + #define M_ANT_LOCK_EN VAL_BIT0 + + //## CMT2310A_CTL_REG_23 registers + #define M_API_DONE_EN VAL_BIT7 + #define M_CCA_STATUS_EN VAL_BIT6 + #define M_CSMA_DONE_EN VAL_BIT5 + #define M_TX_DC_DONE_EN VAL_BIT4 + #define M_ACK_RECV_FAILED_EN VAL_BIT3 + #define M_TX_RESEND_DONE_EN VAL_BIT2 + #define M_NACK_RECV_EN VAL_BIT1 + #define M_SEQ_MATCH_EN VAL_BIT0 + + //## CMT2310A_CTL_REG_24 registers + #define M_SLEEP_TMO_FLG VAL_BIT5 + #define M_RX_TMO_FLG VAL_BIT4 + #define M_TX_DONE_FLG VAL_BIT3 + #define M_TX_DONE_CLR VAL_BIT2 + #define M_RX_TMO_CLR VAL_BIT1 + #define M_SLEEP_TMO_CLR VAL_BIT0 + + //## CMT2310A_CTL_REG_25 registers + #define M_PREAM_PASS_CLR VAL_BIT4 + #define M_SYNC_PASS_CLR VAL_BIT3 + #define M_ADDR_PASS_CLR VAL_BIT2 + #define M_CRC_PASS_CLR VAL_BIT1 + #define M_PKT_DONE_CLR VAL_BIT0 + + //## CMT2310A_CTL_REG_26 registers + #define M_SYNC1_PASS_FLG VAL_BIT5 + #define M_PREAM_PASS_FLG VAL_BIT4 + #define M_SYNC_PASS_FLG VAL_BIT3 + #define M_ADDR_PASS_FLG VAL_BIT2 + #define M_CRC_PASS_FLG VAL_BIT1 + #define M_PKT_DONE_FLG VAL_BIT0 + + //## CMT2310A_CTL_REG_27 registers + #define M_TX_FIFO_RESTORE VAL_BIT2 + #define M_RX_FIFO_CLR VAL_BIT1 + #define M_TX_FIFO_CLR VAL_BIT0 + + //## CMT2310A_CTL_REG_28 registers + #define M_RX_FIFO_FULL_FLG VAL_BIT7 + #define M_RX_FIFO_NMTY_FLG VAL_BIT6 + #define M_RX_FIFO_TH_FLG VAL_BIT5 + #define M_RX_FIFO_OVF_FLG VAL_BIT3 + #define M_TX_FIFO_FULL_FLG VAL_BIT2 + #define M_TX_FIFO_NMTY_FLG VAL_BIT1 + #define M_TX_FIFO_TH_FLG VAL_BIT0 + + //## CMT2310A_CTL_REG_29 registers + #define M_ANT_LOCK_CLR VAL_BIT4 + #define M_OP_CMD_FAILED_CLR VAL_BIT3 + #define M_RSSI_COLL_CLR VAL_BIT2 + #define M_PKT_ERR_CLR VAL_BIT1 + #define M_LBD_STATUS_CLR VAL_BIT0 + + //## CMT2310A_CTL_REG_30 registers + #define M_ANT_LOCK_FLG VAL_BIT4 + #define M_OP_CMD_FAILED_FLG VAL_BIT3 + #define M_RSSI_COLL_FLG VAL_BIT2 + #define M_PKT_ERR_FLG VAL_BIT1 + #define M_LBD_STATUS_FLG VAL_BIT0 + + + //## CMT2310A_CTL_REG_31 registers + #define M_API_DONE_CLR VAL_BIT7 + #define M_CCA_STATUS_CLR VAL_BIT6 + #define M_CSMA_DONE_CLR VAL_BIT5 + #define M_TX_DC_DONE_CLR VAL_BIT4 + #define M_ACK_RECV_FAILED_CLR VAL_BIT3 + #define M_TX_RESEND_DONE_CLR VAL_BIT2 + #define M_NACK_RECV_CLR VAL_BIT1 + #define M_SEQ_MATCH_CLR VAL_BIT0 + + //## CMT2310A_CTL_REG_32 registers + #define M_API_DONE_FLG VAL_BIT7 + #define M_CCA_STATUS_FLG VAL_BIT6 + #define M_CSMA_DONE_FLG VAL_BIT5 + #define M_TX_DC_DONE_FLG VAL_BIT4 + #define M_ACK_RECV_FAILED_FLG VAL_BIT3 + #define M_TX_RESEND_DONE_FLG VAL_BIT2 + #define M_NACK_RECV_FLG VAL_BIT1 + #define M_SEQ_MATCH_FLG VAL_BIT0 + + //## CMT2310A_CTL_REG_126 registers + #define M_HV_PAGE_SEL (VAL_BIT7|VAL_BIT6) + + //## CMT2310A STATE + #define STATE_IS_IDLE 0x00 + #define STATE_IS_SLEEP 0x81 + #define STATE_IS_READY 0x82 + #define STATE_IS_RFS 0x84 + #define STATE_IS_TFS 0x88 + #define STATE_IS_RX 0x90 + #define STATE_IS_TX 0xA0 + + //## GPIO0_SEL + #define GPIO0_SEL_DOUT 0x00 + #define GPIO0_SEL_INT1 0x01 + #define GPIO0_SEL_INT2 0x02 + #define GPIO0_SEL_DCLK 0x03 + + //## GPIO1_SEL + #define GPIO1_SEL_DCLK 0x00 + #define GPIO1_SEL_INT1 0x01 + #define GPIO1_SEL_INT2 0x02 + #define GPIO1_SEL_DOUT 0x03 + + //## GPIO2_SEL + #define GPIO2_SEL_INT1 0x00 + #define GPIO2_SEL_INT2 0x01 + #define GPIO2_SEL_DCLK 0x02 + #define GPIO2_SEL_DOUT 0x03 + + //## GPIO3_SEL + #define GPIO3_SEL_INT2 0x00 + #define GPIO3_SEL_INT1 0x01 + #define GPIO3_SEL_DCLK 0x02 + #define GPIO3_SEL_DOUT 0x03 + #define GPIO3_SEL_DIN 0x05 + + //## GPIO4_SEL + #define GPIO4_SEL_DOUT 0x00 + #define GPIO4_SEL_INT1 0x01 + #define GPIO4_SEL_INT2 0x02 + #define GPIO4_SEL_DCLK 0x03 + #define GPIO4_SEL_DIN 0x05 + + //## GPIO5_SEL + #define GPIO5_SEL_RSTN 0x00 + #define GPIO5_SEL_INT1 0x01 + #define GPIO5_SEL_INT2 0x02 + #define GPIO5_SEL_DOUT 0x03 + #define GPIO5_SEL_DCLK 0x04 + + //## TX_DIN_SEL + #define TX_DIN_SEL_GPIO3 0x00 + #define TX_DIN_SEL_GPIO4 0x01 + #define TX_DIN_SEL_NIRQ 0x02 + + //## NIRQ_SEL + #define NIRQ_SEL_INT1 0x00 + #define NIRQ_SEL_INT2 0x01 + #define NIRQ_SEL_DCLK 0x02 + #define NIRQ_SEL_DOUT 0x03 + #define NIRQ_SEL_DIN 0x04 + + //## INT1/2_SEL + #define INT_SRC_MIX 0x00 + #define INT_SRC_ANT_LOCK 0x01 + #define INT_SRC_RSSI_PJD_VALID 0x02 + #define INT_SRC_PREAM_PASS 0x03 + #define INT_SRC_SYNC_PASS 0x04 + #define INT_SRC_ADDR_PASS 0x05 + #define INT_SRC_CRC_PASS 0x06 + #define INT_SRC_PKT_OK 0x07 + #define INT_SRC_PKT_DONE 0x08 + #define INT_SRC_SLEEP_TMO 0x09 + #define INT_SRC_RX_TMO 0x0A + #define INT_SRC_RX_FIFO_NMTY 0x0B + #define INT_SRC_RX_FIFO_TH 0x0C + #define INT_SRC_RX_FIFO_FULL 0x0D + #define INT_SRC_RX_FIFO_WBYTE 0x0E + #define INT_SRC_RX_FIFO_OVF 0x0F + #define INT_SRC_TX_DONE 0x10 + #define INT_SRC_TX_FIFO_NMTY 0x11 + #define INT_SRC_TX_FIFO_TH 0x12 + #define INT_SRC_TX_FIFO_FULL 0x13 + #define INT_SRC_STATE_IS_READY 0x14 + #define INT_SRC_STATE_IS_FS 0x15 + #define INT_SRC_STATE_IS_RX 0x16 + #define INT_SRC_STATE_IS_TX 0x17 + #define INT_SRC_LBD_STATUS 0x18 + #define INT_SRC_API_CMD_FAILED 0x19 + #define INT_SRC_API_DONE 0x1A + #define INT_SRC_TX_DC_DONE 0x1B + #define INT_SRC_ACK_RECV_FAILED 0x1C + #define INT_SRC_TX_RESEND_DONE 0x1D + #define INT_SRC_NACK_RECV 0x1E + #define INT_SRC_SEQ_MATCH 0x1F + #define INT_SRC_CSMA_DONE 0x20 + #define INT_SRC_CCA_STATUS 0x21 + +#endif + +//****************************************************************************** +//* EOF (not truncated) +//****************************************************************************** diff --git a/MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/cmt2310a_410mhz.c b/MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/cmt2310a_410mhz.c new file mode 100755 index 0000000..f77cb60 --- /dev/null +++ b/MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/cmt2310a_410mhz.c @@ -0,0 +1,428 @@ +#include "radio_hal.h" +#include "CMT2310A_reg.h" +#include "CMT2310A_def.h" + +/**************************************************************************** +;--------------------------------------- +; CMT2310A Configuration File +; Generated by CMOSTEK RFPDK 1.54 +; 2023.12.07 13:35 +;--------------------------------------- +; Mode = Advanced +; Part Number = CMT2310A +; Frequency = 410.000 MHz +; DC-DC = Off +; Demodulation = GFSK +; Xtal Cap Load = 2 +; Data Rate = 2.400 kbps +; Deviation = 4.800 kHz +; Tx Xtal Tol. = 10 ppm +; Rx Xtal Tol. = 10 ppm +; TRx Matching Network Type = 20 dBm +; Tx Power = +20 dBm +; Gaussian BT = 0.5 +; PA Ramp = On-Autosel Rampstep +; PA Ramp Step = NA +; RF Performance = NA +; Output Drive Capability = 0.5mA +; Rx Duty-Cycle = Off +; Tx Duty-Cycle = Off +; Sleep Timer = Off +; Sleep Time = NA +; Rx Timer = Off +; Rx Time T1 = NA +; Rx Time T2 = NA +; Rx Exit State = STBY +; Tx Exit State = STBY +; TX Duty Cycle Persist = Off +; Packet Done Exit = Off +; TX Duty-Cycle Times = 0 +; SLP Mode = Mode 0 +; RSSI Valid Source = RSSI Compare +; PJD Window = NA +; RSSI Compare TH = -127 dBm +; CDR Type = Counting +; AFC = autosel +; FSK2 Data Map = 0:F-low 1:F-high +; FSK4 Data Map = NA +; FSK4 RX Data Map = NA +; CDR Type = Counting +; CDR Range Sel FSK = NA +; Channel BW = autosel +; Baseband BW FSK = autosel +; Data Mode = Packet +; Packet Mode = Normal +; PiggyBacking = Disable +; Manchester = Disable +; Manchester Type = NA +; Whitening = Disable +; Whiten Type = NA +; Whiten Seed Type = NA +; Whiten Seed = NA +; FEC = Disable +; FEC Type = NA +; FEC Padding Code = NA +; crc err clear fifo = Not Clear +; Tx Packet Gap = 32 symbol(s) +; Tx Packet Number = 1 packet(s) +; Tx Prefix Type = 0 +; Packet Type = Fixed Length +; Address-Length Position = NA +; Length Size = 1-byte +; Payload Bit Order = Start from msb +; Address Field = Disable +; Preamble Rx Size = 2 +; Preamble Tx Size = 8 +; Preamble Value = 170 +; Preamble Unit = 8-bit +; Sync Size = 3-byte +; Sync Format = S2LP +; Sync Value = 3003605 +; Sync Manchester = Disable +; Sync Value Selection = Sync Value +; Sync FEC Value = 3003605 +; Sync Tolerance = None +; Address Detect Mode = None +; Address Split Mode = NA +; Address Size = NA +; Address Err Mask = NA +; Address Free = NA +; Dest Addr Value = NA +; Src Addr Value = NA +; Dest Addr Bit Mask = NA +; Src Addr Bit Mask = NA +; Sequence Num = None +; Sequence Num Match = off +; Sequence Num Mode = NA +; Sequence Num Value = NA +; FCS2 = None +; FCS2 Value = NA +; Payload Length = 32 +; CRC Options = None +; CRC Swap = NA +; CRC Seed = NA +; CRC Bit Invert = NA +; CRC Range = NA +; CRC Polynomial = NA +; CRC Bit Order = NA +; CRC Refin = NA +; CRC_Refout = NA +; Frequency Hopping Mode = Mode 2 +; Freq Hopping Space = 10 kHz +; Hopping Channels = 10 +; CSMA Mode = Disable +; CSMA RSSI Detection = NA +; Hopping Persist = Disable +; Hopping Intermediate State = TRFS +; CSMA Sleep Timer Random = NA +; CSMA Rx Time = NA +; CSMA Sleep Time M = NA +; CSMA Sleep Time R = NA +; CSMA Persist = NA +; CSMA Detect Times = NA +; Tx Auto Hopping = Disable +; Rx Auto Hopping = Disable +; Auto Acknowledge = off +; Auto Resend = off +; Maximum Resend Times = 1 +; RSSI Detect Mode = always +; LFOSC LFXO Sel = LFOSC(32kHz) +; LF Clock Out = off +; Dout Mute = disable +; Dout Mute Sel = NA +; dout adjust mode = disable +; Dout Adjust Percentage = NA +; LBD Threshold = 2.4 v +; Antenna Diversity = off +; Antenna Switch Mode = NA +; Collision Detect = off +; Collision Step = NA +; RSSI Offset dB = NA +; RSSI Offset Sel = autosel +; i_fir_bb_bw_for_cal_freq = 1 + +;--------------------------------------- +; The following are the Register contents +;--------------------------------------- + +*****************************************************************************/ + +#if (PRODUCT_FREQUENCY == CM2310A_410MHZ) + +/* [CMT page0] */ +const uint8_t g_cmt2310a_page0[CMT2310A_PAGE0_SIZE] = { + 0x12, + 0x08, + 0x00, + 0xAA, + 0x04, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0xD5, + 0xD4, + 0x2D, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0xD5, + 0xD4, + 0x2D, + 0x1F, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x2D, + 0x00, + 0x00, + 0x00, + 0x2D, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x45, + 0x1F, + 0x00, + 0x00, + 0x00, + 0x00, + 0x08, + 0x00, + 0x00, + 0x00, + 0x00, + 0x1F, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0xE4, + 0x20, + 0x20, + 0x20, + 0x01, + 0x00, + 0xD0, + 0xE0, + 0xE2, + 0x84, + 0x30, + 0x04, + 0xD0, + 0xE0, + 0x80, + 0x00, + 0x41, + 0x00, + 0x01, + 0x00, + 0x02, + 0x00, + 0x00, + 0x03, + 0x04, +}; + +/* [CMT page1] */ +const uint8_t g_cmt2310a_page1[CMT2310A_PAGE1_SIZE] = { + 0x10, + 0x06, + 0x00, + 0xFF, + 0x00, + 0xCD, + 0x02, + 0x28, + 0x50, + 0x87, + 0x31, + 0x5B, + 0x08, + 0x00, + 0xFF, + 0x00, + 0x66, + 0x00, + 0x00, + 0x08, + 0xB4, + 0xEA, + 0x04, + 0xE0, + 0x20, + 0x08, + 0x05, + 0x8D, + 0x06, + 0x00, + 0xA0, + 0x7F, + 0x00, + 0x18, + 0x00, + 0x00, + 0x1F, + 0xE4, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0xCA, + 0x66, + 0x00, + 0x80, + 0xD8, + 0x63, + 0x00, + 0x80, + 0x0F, + 0x64, + 0x06, + 0x02, + 0xEA, + 0x04, + 0x00, + 0x36, + 0x01, + 0x20, + 0xC8, + 0x63, + 0xA1, + 0x15, + 0x34, + 0x58, + 0x40, + 0xD2, + 0x74, + 0xF0, + 0x0F, + 0x01, + 0x17, + 0xE6, + 0x54, + 0x08, + 0x39, + 0xE6, + 0x27, + 0x0C, + 0x01, + 0xB4, + 0x06, + 0x0F, + 0x00, + 0x4C, + 0x00, + 0x00, + 0xF6, + 0x00, + 0x00, + 0x00, + 0x10, + 0x81, + 0x00, + 0x00, + 0x47, + 0x12, + 0x25, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, +}; + +//#define CMT2310A_AUTO_HOP_ENABLE +#ifdef CMT2310A_AUTO_HOP_ENABLE +#define freq_space_val 0x0A +#define freq_times_val 0x0A +#define freq_switch_state_val 0x01 +#define freq_hop_persist_val 0x00 + +/* [CMT page2] */ +const uint8_t g_cmt2310a_page2[CMT2310A_PAGE2_SIZE] = { + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, +}; +#endif + +#endif diff --git a/MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/cmt2310a_433mhz.c b/MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/cmt2310a_433mhz.c new file mode 100755 index 0000000..bae1d8d --- /dev/null +++ b/MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/cmt2310a_433mhz.c @@ -0,0 +1,351 @@ +#include "radio_hal.h" +#include "CMT2310A_reg.h" +#include "CMT2310A_def.h" + + +/**************************************************************************** +;--------------------------------------- +; CMT2310A Configuration File +; Generated by CMOSTEK RFPDK 1.53_Update4 +; 2023.01.14 10:34 +;--------------------------------------- +; Mode = Advanced +; Part Number = CMT2310A +; Frequency = 433.920 MHz +; DC-DC = Off +; Demodulation = GFSK +; Xtal Cap Load = 2 +; Data Rate = 2.400 kbps +; Deviation = 4.800 kHz +; Tx Xtal Tol. = 10 ppm +; Rx Xtal Tol. = 10 ppm +; TRx Matching Network Type = 20 dBm +; Tx Power = +20 dBm +; Gaussian BT = 0.5 +; PA Ramp = On-Autosel Rampstep +; PA Ramp Step = NA +; RF Performance = NA +; Output Drive Capability = 0.5mA +; Rx Duty-Cycle = Off +; Tx Duty-Cycle = Off +; Sleep Timer = Off +; Sleep Time = NA +; Rx Timer = Off +; Rx Time T1 = NA +; Rx Time T2 = NA +; Rx Exit State = STBY +; Tx Exit State = STBY +; TX Duty Cycle Persist = Off +; Packet Done Exit = Off +; TX Duty-Cycle Times = 0 +; SLP Mode = Mode 0 +; RSSI Valid Source = RSSI Compare +; PJD Window = NA +; RSSI Compare TH = -127 dBm +; CDR Type = Counting +; AFC = autosel +; FSK2 Data Map = 0:F-low 1:F-high +; FSK4 Data Map = NA +; FSK4 RX Data Map = NA +; CDR Type = Counting +; CDR Range Sel FSK = NA +; Channel BW = autosel +; Baseband BW FSK = autosel +; Data Mode = Packet +; Packet Mode = Normal +; PiggyBacking = Disable +; Manchester = Disable +; Manchester Type = NA +; Whitening = Disable +; Whiten Type = NA +; Whiten Seed Type = NA +; Whiten Seed = NA +; FEC = Disable +; FEC Type = NA +; FEC Padding Code = NA +; crc err clear fifo = Not Clear +; Tx Packet Gap = 32 symbol(s) +; Tx Packet Number = 1 packet(s) +; Tx Prefix Type = 0 +; Packet Type = Fixed Length +; Address-Length Position = NA +; Length Size = 1-byte +; Payload Bit Order = Start from msb +; Address Field = Disable +; Preamble Rx Size = 2 +; Preamble Tx Size = 8 +; Preamble Value = 170 +; Preamble Unit = 8-bit +; Sync Size = 3-byte +; Sync Format = S2LP +; Sync Value = 3003605 +; Sync Manchester = Disable +; Sync Value Selection = Sync Value +; Sync FEC Value = 3003605 +; Sync Tolerance = None +; Address Detect Mode = None +; Address Split Mode = NA +; Address Size = NA +; Address Err Mask = NA +; Address Free = NA +; Dest Addr Value = NA +; Src Addr Value = NA +; Dest Addr Bit Mask = NA +; Src Addr Bit Mask = NA +; Sequence Num = None +; Sequence Num Match = off +; Sequence Num Mode = NA +; Sequence Num Value = NA +; FCS2 = None +; FCS2 Value = NA +; Payload Length = 32 +; CRC Options = None +; CRC Swap = NA +; CRC Seed = NA +; CRC Bit Invert = NA +; CRC Range = NA +; CRC Polynomial = NA +; CRC Bit Order = NA +; CRC Refin = NA +; CRC_Refout = NA +; Frequency Hopping Mode = Mode 2 +; Freq Hopping Space = 10 kHz +; Hopping Channels = 10 +; CSMA Mode = Disable +; CSMA RSSI Detection = NA +; Hopping Persist = Disable +; Hopping Intermediate State = TRFS +; CSMA Sleep Timer Random = NA +; CSMA Rx Time = NA +; CSMA Sleep Time M = NA +; CSMA Sleep Time R = NA +; CSMA Persist = NA +; CSMA Detect Times = NA +; Tx Auto Hopping = Disable +; Rx Auto Hopping = Disable +; Auto Acknowledge = off +; Auto Resend = off +; Maximum Resend Times = 1 +; RSSI Detect Mode = always +; LFOSC LFXO Sel = LFOSC(32kHz) +; LF Clock Out = off +; Dout Mute = disable +; Dout Mute Sel = NA +; dout adjust mode = disable +; Dout Adjust Percentage = NA +; LBD Threshold = 2.4 v +; Antenna Diversity = off +; Antenna Switch Mode = NA +; Collision Detect = off +; Collision Step = NA +; RSSI Offset dB = NA +; RSSI Offset Sel = autosel + +;--------------------------------------- +; The following are the Register contents +;--------------------------------------- + +*****************************************************************************/ + +#if (PRODUCT_FREQUENCY == CM2310A_433MHZ) +/* [CMT page0] */ +const uint8_t g_cmt2310a_page0[CMT2310A_PAGE0_SIZE] = { + 0x12, + 0x08, + 0x00, + 0xAA, + 0x04, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0xD5, + 0xD4, + 0x2D, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0xD5, + 0xD4, + 0x2D, + 0x1F, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x2D, + 0x00, + 0x00, + 0x00, + 0x2D, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x45, + 0x1F, + 0x00, + 0x00, + 0x00, + 0x00, + 0x08, + 0x00, + 0x00, + 0x00, + 0x00, + 0x1F, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0xE4, + 0x20, + 0x20, + 0x20, + 0x01, + 0x00, + 0xD0, + 0xE0, + 0xE2, + 0x84, + 0x30, + 0x04, + 0xD0, + 0xE0, + 0x80, + 0x00, + 0x41, + 0x00, + 0x01, + 0x00, + 0x02, + 0x00, + 0x00, + 0x03, + 0x04, +}; + +/* [CMT page1] */ +const uint8_t g_cmt2310a_page1[CMT2310A_PAGE1_SIZE] = { + 0x10, + 0x06, + 0x00, + 0xFF, + 0x00, + 0xCD, + 0x02, + 0x28, + 0x50, + 0x87, + 0x31, + 0x5B, + 0x08, + 0x00, + 0xFF, + 0x00, + 0x6C, + 0x14, + 0xAE, + 0x07, + 0xB4, + 0xEA, + 0x04, + 0xE0, + 0x20, + 0x08, + 0x05, + 0x8D, + 0x06, + 0x00, + 0xA0, + 0x7F, + 0x00, + 0x18, + 0x00, + 0x00, + 0x1F, + 0xE4, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0xCA, + 0x6C, + 0x14, + 0x2E, + 0xD8, + 0x6B, + 0x00, + 0x80, + 0x0F, + 0x64, + 0x06, + 0x02, + 0xEA, + 0x04, + 0x00, + 0x36, + 0x01, + 0x20, + 0xC8, + 0x63, + 0xA1, + 0x15, + 0x34, + 0x58, + 0x40, + 0xD2, + 0x74, + 0xF0, + 0x0F, + 0x01, + 0x17, + 0xE6, + 0x54, + 0x08, + 0x39, + 0xE2, + 0x27, + 0x0C, + 0x01, + 0xB4, + 0x06, + 0x0F, + 0x0E, + 0x4C, + 0x00, + 0x00, + 0xF6, + 0x00, + 0x00, + 0x00, + 0x10, + 0x81, + 0x00, + 0x00, + 0x47, + 0x12, + 0x25, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, +}; + +#endif diff --git a/MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/cmt2310a_868mhz.c b/MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/cmt2310a_868mhz.c new file mode 100755 index 0000000..b455f7e --- /dev/null +++ b/MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/cmt2310a_868mhz.c @@ -0,0 +1,352 @@ +#include "radio_hal.h" +#include "CMT2310A_reg.h" +#include "CMT2310A_def.h" + + + +/**************************************************************************** +;--------------------------------------- +; CMT2310A Configuration File +; Generated by CMOSTEK RFPDK 1.53_Update4 +; 2023.01.14 10:34 +;--------------------------------------- +; Mode = Advanced +; Part Number = CMT2310A +; Frequency = 868.000 MHz +; DC-DC = Off +; Demodulation = GFSK +; Xtal Cap Load = 2 +; Data Rate = 2.400 kbps +; Deviation = 4.800 kHz +; Tx Xtal Tol. = 10 ppm +; Rx Xtal Tol. = 10 ppm +; TRx Matching Network Type = 20 dBm +; Tx Power = +20 dBm +; Gaussian BT = 0.5 +; PA Ramp = On-Autosel Rampstep +; PA Ramp Step = NA +; RF Performance = NA +; Output Drive Capability = 0.5mA +; Rx Duty-Cycle = Off +; Tx Duty-Cycle = Off +; Sleep Timer = Off +; Sleep Time = NA +; Rx Timer = Off +; Rx Time T1 = NA +; Rx Time T2 = NA +; Rx Exit State = STBY +; Tx Exit State = STBY +; TX Duty Cycle Persist = Off +; Packet Done Exit = Off +; TX Duty-Cycle Times = 0 +; SLP Mode = Mode 0 +; RSSI Valid Source = RSSI Compare +; PJD Window = NA +; RSSI Compare TH = -127 dBm +; CDR Type = Counting +; AFC = autosel +; FSK2 Data Map = 0:F-low 1:F-high +; FSK4 Data Map = NA +; FSK4 RX Data Map = NA +; CDR Type = Counting +; CDR Range Sel FSK = NA +; Channel BW = autosel +; Baseband BW FSK = autosel +; Data Mode = Packet +; Packet Mode = Normal +; PiggyBacking = Disable +; Manchester = Disable +; Manchester Type = NA +; Whitening = Disable +; Whiten Type = NA +; Whiten Seed Type = NA +; Whiten Seed = NA +; FEC = Disable +; FEC Type = NA +; FEC Padding Code = NA +; crc err clear fifo = Not Clear +; Tx Packet Gap = 32 symbol(s) +; Tx Packet Number = 1 packet(s) +; Tx Prefix Type = 0 +; Packet Type = Fixed Length +; Address-Length Position = NA +; Length Size = 1-byte +; Payload Bit Order = Start from msb +; Address Field = Disable +; Preamble Rx Size = 2 +; Preamble Tx Size = 8 +; Preamble Value = 170 +; Preamble Unit = 8-bit +; Sync Size = 3-byte +; Sync Format = S2LP +; Sync Value = 3003605 +; Sync Manchester = Disable +; Sync Value Selection = Sync Value +; Sync FEC Value = 3003605 +; Sync Tolerance = None +; Address Detect Mode = None +; Address Split Mode = NA +; Address Size = NA +; Address Err Mask = NA +; Address Free = NA +; Dest Addr Value = NA +; Src Addr Value = NA +; Dest Addr Bit Mask = NA +; Src Addr Bit Mask = NA +; Sequence Num = None +; Sequence Num Match = off +; Sequence Num Mode = NA +; Sequence Num Value = NA +; FCS2 = None +; FCS2 Value = NA +; Payload Length = 32 +; CRC Options = None +; CRC Swap = NA +; CRC Seed = NA +; CRC Bit Invert = NA +; CRC Range = NA +; CRC Polynomial = NA +; CRC Bit Order = NA +; CRC Refin = NA +; CRC_Refout = NA +; Frequency Hopping Mode = Mode 2 +; Freq Hopping Space = 10 kHz +; Hopping Channels = 10 +; CSMA Mode = Disable +; CSMA RSSI Detection = NA +; Hopping Persist = Disable +; Hopping Intermediate State = TRFS +; CSMA Sleep Timer Random = NA +; CSMA Rx Time = NA +; CSMA Sleep Time M = NA +; CSMA Sleep Time R = NA +; CSMA Persist = NA +; CSMA Detect Times = NA +; Tx Auto Hopping = Disable +; Rx Auto Hopping = Disable +; Auto Acknowledge = off +; Auto Resend = off +; Maximum Resend Times = 1 +; RSSI Detect Mode = always +; LFOSC LFXO Sel = LFOSC(32kHz) +; LF Clock Out = off +; Dout Mute = disable +; Dout Mute Sel = NA +; dout adjust mode = disable +; Dout Adjust Percentage = NA +; LBD Threshold = 2.4 v +; Antenna Diversity = off +; Antenna Switch Mode = NA +; Collision Detect = off +; Collision Step = NA +; RSSI Offset dB = NA +; RSSI Offset Sel = autosel + +;--------------------------------------- +; The following are the Register contents +;--------------------------------------- + +*****************************************************************************/ + +#if ( PRODUCT_FREQUENCY == CM2310A_868MHZ) +/* [CMT page0] */ +const uint8_t g_cmt2310a_page0[CMT2310A_PAGE0_SIZE] = { + 0x12, + 0x08, + 0x00, + 0xAA, + 0x04, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0xD5, + 0xD4, + 0x2D, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0xD5, + 0xD4, + 0x2D, + 0x1F, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x2D, + 0x00, + 0x00, + 0x00, + 0x2D, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x45, + 0x1F, + 0x00, + 0x00, + 0x00, + 0x00, + 0x08, + 0x00, + 0x00, + 0x00, + 0x00, + 0x1F, + 0x04, + 0x00, + 0x00, + 0x00, + 0x00, + 0xE4, + 0x20, + 0x20, + 0x20, + 0x01, + 0x00, + 0xD0, + 0xE0, + 0xE2, + 0x84, + 0x30, + 0x04, + 0xD0, + 0xE0, + 0x80, + 0x00, + 0x41, + 0x00, + 0x01, + 0x00, + 0x02, + 0x00, + 0x00, + 0x03, + 0x04, +}; + +/* [CMT page1] */ +const uint8_t g_cmt2310a_page1[CMT2310A_PAGE1_SIZE] = { + 0x10, + 0x06, + 0x00, + 0xFF, + 0x00, + 0xCD, + 0x02, + 0x20, + 0x50, + 0x87, + 0x31, + 0x5B, + 0x08, + 0x00, + 0xFF, + 0x00, + 0x6C, + 0x00, + 0x00, + 0x08, + 0xB4, + 0xEA, + 0x04, + 0xE0, + 0x20, + 0x08, + 0x05, + 0x47, + 0x03, + 0x00, + 0x91, + 0x7F, + 0x00, + 0x18, + 0x00, + 0x00, + 0x1F, + 0xE4, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0xC0, + 0x6C, + 0x00, + 0x40, + 0xD8, + 0x6B, + 0x00, + 0xC0, + 0x0F, + 0x64, + 0x06, + 0x02, + 0xEA, + 0x04, + 0x00, + 0x36, + 0x01, + 0x20, + 0xC8, + 0x63, + 0xA1, + 0x15, + 0x34, + 0x58, + 0x40, + 0xC3, + 0x74, + 0xF0, + 0x0F, + 0x01, + 0x17, + 0xE6, + 0x54, + 0x08, + 0x39, + 0xE2, + 0x14, + 0x18, + 0x01, + 0xB4, + 0x06, + 0x0F, + 0x07, + 0x4C, + 0x00, + 0x00, + 0xF6, + 0x00, + 0x00, + 0x00, + 0x10, + 0x81, + 0x00, + 0x00, + 0x47, + 0x12, + 0x25, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, +}; + +#endif \ No newline at end of file diff --git a/MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/cmt2310a_915mhz.c b/MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/cmt2310a_915mhz.c new file mode 100755 index 0000000..6ef82f6 --- /dev/null +++ b/MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/cmt2310a_915mhz.c @@ -0,0 +1,352 @@ +#include "radio_hal.h" +#include "CMT2310A_reg.h" +#include "CMT2310A_def.h" + + + +/**************************************************************************** +;--------------------------------------- +; CMT2310A Configuration File +; Generated by CMOSTEK RFPDK 1.53_Update4 +; 2023.01.14 10:34 +;--------------------------------------- +; Mode = Advanced +; Part Number = CMT2310A +; Frequency = 915.000 MHz +; DC-DC = Off +; Demodulation = GFSK +; Xtal Cap Load = 2 +; Data Rate = 2.400 kbps +; Deviation = 4.800 kHz +; Tx Xtal Tol. = 10 ppm +; Rx Xtal Tol. = 10 ppm +; TRx Matching Network Type = 20 dBm +; Tx Power = +20 dBm +; Gaussian BT = 0.5 +; PA Ramp = On-Autosel Rampstep +; PA Ramp Step = NA +; RF Performance = NA +; Output Drive Capability = 0.5mA +; Rx Duty-Cycle = Off +; Tx Duty-Cycle = Off +; Sleep Timer = Off +; Sleep Time = NA +; Rx Timer = Off +; Rx Time T1 = NA +; Rx Time T2 = NA +; Rx Exit State = STBY +; Tx Exit State = STBY +; TX Duty Cycle Persist = Off +; Packet Done Exit = Off +; TX Duty-Cycle Times = 0 +; SLP Mode = Mode 0 +; RSSI Valid Source = RSSI Compare +; PJD Window = NA +; RSSI Compare TH = -127 dBm +; CDR Type = Counting +; AFC = autosel +; FSK2 Data Map = 0:F-low 1:F-high +; FSK4 Data Map = NA +; FSK4 RX Data Map = NA +; CDR Type = Counting +; CDR Range Sel FSK = NA +; Channel BW = autosel +; Baseband BW FSK = autosel +; Data Mode = Packet +; Packet Mode = Normal +; PiggyBacking = Disable +; Manchester = Disable +; Manchester Type = NA +; Whitening = Disable +; Whiten Type = NA +; Whiten Seed Type = NA +; Whiten Seed = NA +; FEC = Disable +; FEC Type = NA +; FEC Padding Code = NA +; crc err clear fifo = Not Clear +; Tx Packet Gap = 32 symbol(s) +; Tx Packet Number = 1 packet(s) +; Tx Prefix Type = 0 +; Packet Type = Fixed Length +; Address-Length Position = NA +; Length Size = 1-byte +; Payload Bit Order = Start from msb +; Address Field = Disable +; Preamble Rx Size = 2 +; Preamble Tx Size = 8 +; Preamble Value = 170 +; Preamble Unit = 8-bit +; Sync Size = 3-byte +; Sync Format = S2LP +; Sync Value = 3003605 +; Sync Manchester = Disable +; Sync Value Selection = Sync Value +; Sync FEC Value = 3003605 +; Sync Tolerance = None +; Address Detect Mode = None +; Address Split Mode = NA +; Address Size = NA +; Address Err Mask = NA +; Address Free = NA +; Dest Addr Value = NA +; Src Addr Value = NA +; Dest Addr Bit Mask = NA +; Src Addr Bit Mask = NA +; Sequence Num = None +; Sequence Num Match = off +; Sequence Num Mode = NA +; Sequence Num Value = NA +; FCS2 = None +; FCS2 Value = NA +; Payload Length = 32 +; CRC Options = None +; CRC Swap = NA +; CRC Seed = NA +; CRC Bit Invert = NA +; CRC Range = NA +; CRC Polynomial = NA +; CRC Bit Order = NA +; CRC Refin = NA +; CRC_Refout = NA +; Frequency Hopping Mode = Mode 2 +; Freq Hopping Space = 10 kHz +; Hopping Channels = 10 +; CSMA Mode = Disable +; CSMA RSSI Detection = NA +; Hopping Persist = Disable +; Hopping Intermediate State = TRFS +; CSMA Sleep Timer Random = NA +; CSMA Rx Time = NA +; CSMA Sleep Time M = NA +; CSMA Sleep Time R = NA +; CSMA Persist = NA +; CSMA Detect Times = NA +; Tx Auto Hopping = Disable +; Rx Auto Hopping = Disable +; Auto Acknowledge = off +; Auto Resend = off +; Maximum Resend Times = 1 +; RSSI Detect Mode = always +; LFOSC LFXO Sel = LFOSC(32kHz) +; LF Clock Out = off +; Dout Mute = disable +; Dout Mute Sel = NA +; dout adjust mode = disable +; Dout Adjust Percentage = NA +; LBD Threshold = 2.4 v +; Antenna Diversity = off +; Antenna Switch Mode = NA +; Collision Detect = off +; Collision Step = NA +; RSSI Offset dB = NA +; RSSI Offset Sel = autosel + +;--------------------------------------- +; The following are the Register contents +;--------------------------------------- + +*****************************************************************************/ + +#if (PRODUCT_FREQUENCY == CM2310A_915MHZ) +/* [CMT page0] */ +const uint8_t g_cmt2310a_page0[CMT2310A_PAGE0_SIZE] = { + 0x12, + 0x08, + 0x00, + 0xAA, + 0x04, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0xD5, + 0xD4, + 0x2D, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0xD5, + 0xD4, + 0x2D, + 0x1F, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x2D, + 0x00, + 0x00, + 0x00, + 0x2D, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x45, + 0x1F, + 0x00, + 0x00, + 0x00, + 0x00, + 0x08, + 0x00, + 0x00, + 0x00, + 0x00, + 0x1F, + 0x04, + 0x00, + 0x00, + 0x00, + 0x00, + 0xE4, + 0x20, + 0x20, + 0x20, + 0x01, + 0x00, + 0xD0, + 0xE0, + 0xE2, + 0x84, + 0x30, + 0x04, + 0xD0, + 0xE0, + 0x80, + 0x00, + 0x41, + 0x00, + 0x01, + 0x00, + 0x02, + 0x00, + 0x00, + 0x03, + 0x04, +}; + +/* [CMT page1] */ +const uint8_t g_cmt2310a_page1[CMT2310A_PAGE1_SIZE] = { + 0x10, + 0x06, + 0x00, + 0xFF, + 0x00, + 0xCD, + 0x02, + 0x20, + 0x50, + 0x87, + 0x31, + 0x5B, + 0x08, + 0x00, + 0xFF, + 0x00, + 0x72, + 0x00, + 0x00, + 0x06, + 0xB4, + 0xEA, + 0x04, + 0xE0, + 0x20, + 0x08, + 0x05, + 0x47, + 0x03, + 0x00, + 0x88, + 0x7F, + 0x00, + 0x18, + 0x00, + 0x00, + 0x14, + 0xE4, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0xC0, + 0x72, + 0x00, + 0x40, + 0xD6, + 0x73, + 0x00, + 0xC0, + 0x0F, + 0x64, + 0x06, + 0x02, + 0xEA, + 0x04, + 0x00, + 0x36, + 0x01, + 0x20, + 0xC8, + 0x63, + 0xA1, + 0x15, + 0x34, + 0x58, + 0x40, + 0xC3, + 0x74, + 0xF0, + 0x0F, + 0x01, + 0x17, + 0xE6, + 0x54, + 0x08, + 0x39, + 0xE2, + 0x14, + 0x18, + 0x01, + 0xB4, + 0x06, + 0x0F, + 0x07, + 0x4C, + 0x00, + 0x00, + 0xF6, + 0x00, + 0x00, + 0x00, + 0x10, + 0x81, + 0x00, + 0x00, + 0x47, + 0x12, + 0x25, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, +}; + +#endif \ No newline at end of file diff --git a/MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/ebyte_e48x.c b/MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/ebyte_e48x.c new file mode 100755 index 0000000..2384b57 --- /dev/null +++ b/MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/ebyte_e48x.c @@ -0,0 +1,111 @@ +#include "ebyte_e48x.h" +#include "ebyte_callback.h" + + +/* 辅助识别模块类别 */ +#define EBYTE_E48_NAME_TYPE 0x00000048 + +/* 辅助识别模块频段 */ +#if defined(EBYTE_E48_433M20S) + + #define EBYTE_E48_FREQUENCY_TYPE 0x00000433 + +#elif defined(EBYTE_E48_900M20S) + + #define EBYTE_E48_FREQUENCY_TYPE 0x00000900 + +#endif + +/* 辅助识别驱动程序版本号 */ +#define EBYTE_E48_PROGRAM_TYPE 0x10 + +#include "board.h" + +uint8_t rf_rxbuffer[200]; +uint8_t rf_rxsize; +uint8_t radio_rece_data_flag; + +extern uint32_t g_chip_id; + +void Ebyte_E48x_Init( void ) +{ + /* Step1 */ + vRadioPowerUp(); // Release RST(GPIO5) + vRadioSetAntSwitch(FALSE, FALSE); // Disable GPIO0 & GPIO1 as antenna switch control + vRadioSpiModeSel(FALSE); // SPI 4-Wire mode + + /* Step2 */ + g_chip_id = lRadioChipVersion(); + if(0x00231000 != (g_chip_id & 0x00FFFF00)) { + DEBUGPRINT("[%s|%u] Error, dismatch Chip-ID[%#x](!=0x231000).\r\n", __FUNCTION__, __LINE__, g_chip_id); + return; + } + DEBUGPRINT("[%s|%u] Info, Link Device:E48-XXXM20S.\r\n", __FUNCTION__, __LINE__); + + /* Step3 */ + if (bRadioGetState() == CMT2310A_STATE_IS_READY) { + DEBUGPRINT("[%s|%u] Infor, CMT2310 already in State[READY], so skip initialization.\r\n", __FUNCTION__, __LINE__); + return; + } + DEBUGPRINT("[%s|%u] Info, goto initialize E48-XXXM20S.\r\n", __FUNCTION__, __LINE__); + + /* Step4 */ + vRadioInit(); +} + +void Ebyte_E48x_SendPayload( uint8_t *payload, uint8_t size, uint32_t timeout ) +{ + vRadioTransmit( payload, size ); +} + + +void Ebyte_E48x_SetRx( uint32_t timeout ) +{ + vRadioReceive(); +} + +void Ebyte_E48x_SetSleep( uint8_t cmd ) +{ + return; +} + + +void Ebyte_E48x_IntOrPollTask( void ) +{ + radio_rece_data_flag = gpio_input_bit_get( BSP_GPIO_PORT_E48_GP4 , BSP_GPIO_PIN_E48_GP4); + /* 有接收数据 */ + if( radio_rece_data_flag != RESET ) { + vRadioGetPacket(rf_rxbuffer,&rf_rxsize); + Ebyte_Port_ReceiveCallback(0x0002,rf_rxbuffer,rf_rxsize); + } +} + + +void Ebyte_E48x_InterruptTrigger( void ) +{ + + +} + +/* ! + * @brief 获取模块类型 + * + * @return 32位的编码 + * @note 高16位代表模块名 例如0x0220 代表E22模块 + * 低16位代表频段名 例如0x0400 代表400频段 + */ +uint32_t Ebyte_E48x_GetName(void) +{ + return ( ( (uint32_t)EBYTE_E48_NAME_TYPE << 16 ) | (uint32_t)EBYTE_E48_FREQUENCY_TYPE); +} + +/* ! + * @brief 获取模块程序版本 + * + * @return 8位的编码 + * @note 例如0x10 代表V1.0 + */ +uint8_t Ebyte_E48x_GetDriverVersion(void) +{ + return EBYTE_E48_PROGRAM_TYPE; +} \ No newline at end of file diff --git a/MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/ebyte_e48x.h b/MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/ebyte_e48x.h new file mode 100755 index 0000000..4f4e886 --- /dev/null +++ b/MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/ebyte_e48x.h @@ -0,0 +1,23 @@ +#ifndef _EBYTE_E48X_H_ +#define _EBYTE_E48X_H_ + + +#include "radio.h" +#include "radio_hal.h" +#include "radio_mac.h" +#include "radio_phy.h" +#include "radio_spi.h" + +#include "ebyte_conf.h" + +void Ebyte_E48x_Init( void ); +void Ebyte_E48x_SendPayload( uint8_t *payload, uint8_t size, uint32_t timeout ); +void Ebyte_E48x_SetRx( uint32_t timeout ); +void Ebyte_E48x_SetSleep( uint8_t cmd ); +void Ebyte_E48x_IntOrPollTask( void ); +void Ebyte_E48x_InterruptTrigger( void ); +uint32_t Ebyte_E48x_GetName(void); +uint8_t Ebyte_E48x_GetDriverVersion(void); + + +#endif \ No newline at end of file diff --git a/MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/radio.c b/MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/radio.c new file mode 100755 index 0000000..d0c11a3 --- /dev/null +++ b/MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/radio.c @@ -0,0 +1,414 @@ +#include "radio.h" +#include "board.h" +CMT2310A_CFG g_radio; // + +uint8_t g_reg_read_buf[128]; +uint32_t g_chip_id = 0; + +//生成的配置文件的270~276行，对应的7个功率配置寄存器 +const uint8_t cmt2310a_power[55][7] = { + {0x20,0x1B,0x00,0x3A,0x00,0x00,0x01 }, /* cmt2310a_params13-0.h */ + {0x25,0x1B,0x00,0x3A,0x00,0x00,0x01 }, /* cmt2310a_params13-1.h */ + {0x68,0x1B,0x00,0x3A,0x00,0x00,0x05 }, /* cmt2310a_params13-10.h */ + {0x36,0x2D,0x00,0x22,0x00,0x00,0x07 }, /* cmt2310a_params13-11.h */ + {0x40,0x2D,0x00,0x22,0x00,0x00,0x08 }, /* cmt2310a_params13-12.h */ + {0x4D,0x2D,0x00,0x22,0x00,0x00,0x0C }, /* cmt2310a_params13-13.h */ + {0x2A,0x1B,0x00,0x3A,0x00,0x00,0x01 }, /* cmt2310a_params13-2.h */ + {0x30,0x1B,0x00,0x3A,0x00,0x00,0x01 }, /* cmt2310a_params13-3.h */ + {0x35,0x1B,0x00,0x3A,0x00,0x00,0x01 }, /* cmt2310a_params13-4.h */ + {0x3A,0x1B,0x00,0x3A,0x00,0x00,0x02 }, /* cmt2310a_params13-5.h */ + {0x41,0x1B,0x00,0x3A,0x00,0x00,0x02 }, /* cmt2310a_params13-6.h */ + {0x48,0x1B,0x00,0x3A,0x00,0x00,0x02 }, /* cmt2310a_params13-7.h */ + {0x50,0x1B,0x00,0x3A,0x00,0x00,0x03 }, /* cmt2310a_params13-8.h */ + {0x5B,0x1B,0x00,0x3A,0x00,0x00,0x04 }, /* cmt2310a_params13-9.h */ + {0x1C,0x1B,0x00,0x3A,0x00,0x00,0x01 }, /* cmt2310a_params13-N1.h */ + {0x19,0x12,0x00,0x57,0x00,0x00,0x01 }, /* cmt2310a_params13-N10.h */ + {0x19,0x1B,0x00,0x3A,0x00,0x00,0x01 }, /* cmt2310a_params13-N2.h */ + {0x16,0x1B,0x00,0x3A,0x00,0x00,0x01 }, /* cmt2310a_params13-N3.h */ + {0x35,0x12,0x00,0x57,0x00,0x00,0x02 }, /* cmt2310a_params13-N4.h */ + {0x2F,0x12,0x00,0x57,0x00,0x00,0x02 }, /* cmt2310a_params13-N5.h */ + {0x29,0x12,0x00,0x57,0x00,0x00,0x02 }, /* cmt2310a_params13-N6.h */ + {0x25,0x12,0x00,0x57,0x00,0x00,0x01 }, /* cmt2310a_params13-N7.h */ + {0x20,0x12,0x00,0x57,0x00,0x00,0x01 }, /* cmt2310a_params13-N8.h */ + {0x1C,0x12,0x00,0x57,0x00,0x00,0x01 }, /* cmt2310a_params13-N9.h */ + {0x2A,0x1F,0x00,0x32,0x00,0x00,0x01 }, /* cmt2310a_params20-0.h */ + {0x2F,0x1F,0x00,0x32,0x00,0x00,0x01 }, /* cmt2310a_params20-1.h */ + {0x39,0x3F,0x00,0x18,0x00,0x00,0x06 }, /* cmt2310a_params20-10.h */ + {0x40,0x3F,0x00,0x18,0x00,0x00,0x07 }, /* cmt2310a_params20-11.h */ + {0x49,0x3F,0x00,0x18,0x00,0x00,0x08 }, /* cmt2310a_params20-12.h */ + {0x53,0x3F,0x00,0x18,0x00,0x00,0x0A }, /* cmt2310a_params20-13.h */ + {0x5F,0x3F,0x00,0x18,0x00,0x00,0x0C }, /* cmt2310a_params20-14.h */ + {0x70,0x3F,0x00,0x18,0x00,0x00,0x0F }, /* cmt2310a_params20-15.h */ + {0x85,0x3F,0x00,0x18,0x00,0x00,0x14 }, /* cmt2310a_params20-16.h */ + {0x50,0x7F,0x00,0x18,0x00,0x00,0x12 }, /* cmt2310a_params20-17.h */ + {0x69,0x7F,0x00,0x18,0x00,0x00,0x18 }, /* cmt2310a_params20-18.h */ + {0x80,0x7F,0x00,0x18,0x00,0x00,0x1C }, /* cmt2310a_params20-19.h */ + {0x35,0x1F,0x00,0x32,0x00,0x00,0x01 }, /* cmt2310a_params20-2.h */ + {0xA0,0x7F,0x00,0x18,0x00,0x00,0x1F }, /* cmt2310a_params20-20.h */ + {0x3C,0x1F,0x00,0x32,0x00,0x00,0x01 }, /* cmt2310a_params20-3.h */ + {0x42,0x1F,0x00,0x32,0x00,0x00,0x01 }, /* cmt2310a_params20-4.h */ + {0x49,0x1F,0x00,0x32,0x00,0x00,0x02 }, /* cmt2310a_params20-5.h */ + {0x54,0x1F,0x00,0x32,0x00,0x00,0x02 }, /* cmt2310a_params20-6.h */ + {0x5F,0x1F,0x00,0x32,0x00,0x00,0x03 }, /* cmt2310a_params20-7.h */ + {0x6B,0x1F,0x00,0x32,0x00,0x00,0x03 }, /* cmt2310a_params20-8.h */ + {0x33,0x3F,0x00,0x18,0x00,0x00,0x05 }, /* cmt2310a_params20-9.h */ + {0x25,0x1F,0x00,0x32,0x00,0x00,0x01 }, /* cmt2310a_params20-N1.h */ + {0x1A,0x16,0x00,0x47,0x00,0x00,0x01 }, /* cmt2310a_params20-N10.h */ + {0x21,0x1F,0x00,0x32,0x00,0x00,0x01 }, /* cmt2310a_params20-N2.h */ + {0x1D,0x1F,0x00,0x32,0x00,0x00,0x01 }, /* cmt2310a_params20-N3.h */ + {0x36,0x16,0x00,0x47,0x00,0x00,0x01 }, /* cmt2310a_params20-N4.h */ + {0x30,0x16,0x00,0x47,0x00,0x00,0x01 }, /* cmt2310a_params20-N5.h */ + {0x2A,0x16,0x00,0x47,0x00,0x00,0x01 }, /* cmt2310a_params20-N6.h */ + {0x25,0x16,0x00,0x47,0x00,0x00,0x01 }, /* cmt2310a_params20-N7.h */ + {0x21,0x16,0x00,0x47,0x00,0x00,0x01 }, /* cmt2310a_params20-N8.h */ + {0x1D,0x16,0x00,0x47,0x00,0x00,0x01 } /* cmt2310a_params20-N9.h */ +}; +/****************************** +**Name: vRadioInit +**Func: Radio config spi & reset +**Input: None +*Output: None +********************************/ +void vRadioInit( void ) +{ + byte fw_rev; + + /* Step4 */ + vRadioHardReset(); + + /* Step5 */ + vRadioConfigPageReg( 0, g_cmt2310a_page0, CMT2310A_PAGE0_SIZE ); //config page 0 + vRadioConfigPageReg( 1, g_cmt2310a_page1, CMT2310A_PAGE1_SIZE ); //config page 1 + vRadioSetNirq( CMT2310A_nIRQ_TCXO ); //for TCXO need cofig as nIRQ pin at first + vRadioTcxoDrvSel( 0 ); //drive power + + fw_rev = (byte)g_chip_id; //dealwith Xtal + switch(fw_rev) + { + case 0xC0: + vRadioXoWaitCfg(RADIO_CGU_DIV4); + break; + default: + break; + } + + /* Step6 */ + vRadioPowerUpBoot(); + delay1ms( 10 ); + + /* Step7 */ + bRadioGoStandby(); + delay1ms( 2 ); + bRadioApiCommand( 0x02 ); // + delay1ms( 10 ); + + /* Step8 */ + bRadioApiCommand( 0x01 ); //IR Calibration, need some times + vRadioCapLoad( 2 ); //Xo Cap + + /* Step9, GPIOn and interrupt setting */ + vRadioSetGpio0( CMT2310A_GPIO0_INT3 ); + vRadioSetGpio1( CMT2310A_GPIO1_INT2 ); + vRadioSetGpio2( CMT2310A_GPIO2_DCLK ); + vRadioSetGpio3( CMT2310A_GPIO3_DOUT ); + vRadioSetGpio4( CMT2310A_GPIO4_INT1 ); + vRadioSetGpio5( CMT2310A_GPIO5_nRST ); + //INT1 = RX_FIFO_WBYTE, INT2 = PKT_DONE + vRadioSetInt1Sel( INT_SRC_RX_FIFO_WBYTE ); + vRadioSetInt2Sel( INT_SRC_PKT_DONE ); + vRadioSetInt1Polar( FALSE ); + vRadioSetInt2Polar( FALSE ); + vRadioSetInt3Polar( FALSE ); + //interrupt source enable config + g_radio.int_src_en._BITS.PKT_DONE_EN = 1; + g_radio.int_src_en._BITS.CRC_PASS_EN = 1; + g_radio.int_src_en._BITS.ADDR_PASS_EN = 0; + g_radio.int_src_en._BITS.SYNC_PASS_EN = 1; + g_radio.int_src_en._BITS.PREAM_PASS_EN = 1; + g_radio.int_src_en._BITS.TX_DONE_EN = 1; + g_radio.int_src_en._BITS.RX_TOUT_EN = 1; + g_radio.int_src_en._BITS.LD_STOP_EN = 0; + g_radio.int_src_en._BITS.LBD_STOP_EN = 0; + g_radio.int_src_en._BITS.LBD_STAT_EN = 0; + g_radio.int_src_en._BITS.PKT_ERR_EN = 0; + g_radio.int_src_en._BITS.RSSI_COLL_EN = 0; + g_radio.int_src_en._BITS.OP_CMD_FAILED_EN = 0; + g_radio.int_src_en._BITS.RSSI_PJD_EN = 0; + g_radio.int_src_en._BITS.SEQ_MATCH_EN = 0; + g_radio.int_src_en._BITS.NACK_RECV_EN = 0; + g_radio.int_src_en._BITS.TX_RESEND_DONE_EN = 0; + g_radio.int_src_en._BITS.ACK_RECV_FAILED_EN = 0; + g_radio.int_src_en._BITS.TX_DC_DONE_EN = 0; + g_radio.int_src_en._BITS.CSMA_DONE_EN = 0; + g_radio.int_src_en._BITS.CCA_STAT_EN = 0; + g_radio.int_src_en._BITS.API_DONE_EN = 0; + g_radio.int_src_en._BITS.TX_FIFO_TH_EN = 1; + g_radio.int_src_en._BITS.TX_FIFO_NMTY_EN = 1; + g_radio.int_src_en._BITS.TX_FIFO_FULL_EN = 1; + g_radio.int_src_en._BITS.RX_FIFO_OVF_EN = 1; + g_radio.int_src_en._BITS.RX_FIFO_TH_EN = 1; + g_radio.int_src_en._BITS.RX_FIFO_NMTY_EN = 1; + g_radio.int_src_en._BITS.RX_FIFO_FULL_EN = 1; + vRadioInterruptSoucreCfg( &g_radio.int_src_en ); + //packet preamble config + g_radio.preamble_cfg.PREAM_LENG_UNIT = 0; //8-bits mode + g_radio.preamble_cfg.PREAM_VALUE = 0xAA; // + g_radio.preamble_cfg.RX_PREAM_SIZE = 2; // + g_radio.preamble_cfg.TX_PREAM_SIZE = 16; + vRadioCfgPreamble( &g_radio.preamble_cfg ); + //packet syncword config + g_radio.sync_cfg.SYN_CFG_u._BITS.SYNC_MAN_EN = 0; //disable syncword manchester coding + g_radio.sync_cfg.SYN_CFG_u._BITS.SYNC_SIZE = 2; //enable 3 bytes for syncword + g_radio.sync_cfg.SYN_CFG_u._BITS.SYNC_TOL = 0; + g_radio.sync_cfg.SYN_CFG_u._BITS.SYNC_MODE_SEL = 0; //normal packet + g_radio.sync_cfg.SYNC_VALUE[0] = 0xAA; + g_radio.sync_cfg.SYNC_VALUE[1] = 0x2D; + g_radio.sync_cfg.SYNC_VALUE[2] = 0xD4; + g_radio.sync_cfg.SYNC_VALUE_SEL = 0; //select SYN_VAL + vRadioCfgSyncWord( &g_radio.sync_cfg ); + //packet node address config + g_radio.addr_cfg.ADDR_CFG_u._BITS.ADDR_DET_MODE = 0; //disable Node Address + vRadioCfgNodeAddr( &g_radio.addr_cfg ); + //packet crc config + g_radio.crc_cfg.CRC_CFG_u._BITS.CRC_EN = 1; //enable crc + g_radio.crc_cfg.CRC_CFG_u._BITS.CRC_BIT_ORDER = 0; + g_radio.crc_cfg.CRC_CFG_u._BITS.CRC_REFIN = 0; + g_radio.crc_cfg.CRC_CFG_u._BITS.CRC_RANGE = 0; + g_radio.crc_cfg.CRC_CFG_u._BITS.CRC_BIT_INV = 0; + g_radio.crc_cfg.CRC_CFG_u._BITS.CRC_BYTE_SWAP = 0; + g_radio.crc_cfg.CRC_CFG_u._BITS.CRC_REFOUT = 0; //whole payload + g_radio.crc_cfg.CRC_CFG_u._BITS.CRCERR_CLR_FIFO_EN = 0; //note: need ative FIFO_AUTO_CLR_RX_EN = 1 or call vRadioFifoAutoClearGoRx(1) + g_radio.crc_cfg.CRC_CFG_u._BITS.CRC_SIZE = 1; //crc-16 mode + g_radio.crc_cfg.CRC_POLY_u.u32_POLY = 0x10210000; + g_radio.crc_cfg.CRC_SEED_u.u32_SEED = 0x00000000; + vRadioCfgCrc( &g_radio.crc_cfg ); + //packet coding format + g_radio.coding_format_cfg.CODING_FORMAT_CFG_u._BITS.MANCH_EN = 0; + g_radio.coding_format_cfg.CODING_FORMAT_CFG_u._BITS.MANCH_TYPE = 0; + g_radio.coding_format_cfg.CODING_FORMAT_CFG_u._BITS.WHITEN_EN = 0; + g_radio.coding_format_cfg.CODING_FORMAT_CFG_u._BITS.WHITEN_TYPE = 0; + g_radio.coding_format_cfg.CODING_FORMAT_CFG_u._BITS.WHITEN_SEED_TYP = 0; + g_radio.coding_format_cfg.CODING_FORMAT_CFG_u._BITS.FEC_EN = 0; + g_radio.coding_format_cfg.CODING_FORMAT_CFG_u._BITS.FEC_RSC_NRNSC_SEL = 0; + g_radio.coding_format_cfg.CODING_FORMAT_CFG_u._BITS.FEC_TICC = 0; + g_radio.coding_format_cfg.WHITEN_SEED = 0x01FF; + g_radio.coding_format_cfg.FEC_PAD_CODE = 0; + vRadioCfgCodeFormat( &g_radio.coding_format_cfg ); + //packet frame format + g_radio.frame_cfg.DATA_MODE = 2; //0=direct mode, 2=packet mode + g_radio.frame_cfg.FRAME_CFG1_u._BITS.PKT_TYPE = 1; //0=fixd-length packet mode 1=可变长 + g_radio.frame_cfg.FRAME_CFG1_u._BITS.PAYLOAD_BIT_ORDER = 0; //msb first + g_radio.frame_cfg.FRAME_CFG1_u._BITS.ADDR_LEN_CONF = 0; + g_radio.frame_cfg.FRAME_CFG1_u._BITS.PAGGYBACKING_EN = 0; + g_radio.frame_cfg.FRAME_CFG1_u._BITS.LENGTH_SIZE = 0; + g_radio.frame_cfg.FRAME_CFG1_u._BITS.INTERLEAVE_EN = 0; //note: when FEC enable, INTERLEAVE_EN should be set 1 + g_radio.frame_cfg.FRAME_CFG2_u._BITS.TX_PREFIX_TYPE = TX_PREFIX_SEL_PREAMBLE; //transmit preamble + g_radio.frame_cfg.FRAME_CFG2_u._BITS.SEQNUM_EN = 0; + g_radio.frame_cfg.FRAME_CFG2_u._BITS.SEQNUM_AUTO_INC = 0; + g_radio.frame_cfg.FRAME_CFG2_u._BITS.SEQNUM_SIZE = 0; + g_radio.frame_cfg.FRAME_CFG2_u._BITS.SEQNUM_MACH_EN = 0; + g_radio.frame_cfg.FRAME_CFG2_u._BITS.FCS2_EN = 0; + g_radio.frame_cfg.TX_PKT_NUM = 0; + g_radio.frame_cfg.TX_PKT_GAP = 0; + g_radio.frame_cfg.FCS2_TX_IN = 0; + g_radio.frame_cfg.PAYLOAD_LENGTH = UHF_LEN; + vRadioCfgFrameFormat( &g_radio.frame_cfg ); + //Run Mode Config + g_radio.word_mode_cfg.WORK_MODE_CFG1_u._BITS.TX_DC_EN = 0; + g_radio.word_mode_cfg.WORK_MODE_CFG1_u._BITS.TX_ACK_EN = 0; + g_radio.word_mode_cfg.WORK_MODE_CFG1_u._BITS.TX_DC_PERSIST_EN = 0; + g_radio.word_mode_cfg.WORK_MODE_CFG1_u._BITS.TX_AUTO_HOP_EN = 0; + g_radio.word_mode_cfg.WORK_MODE_CFG1_u._BITS.TX_EXIT_STATE = EXIT_TO_READY; + g_radio.word_mode_cfg.WORK_MODE_CFG2_u._BITS.RX_DC_EN = 0; + g_radio.word_mode_cfg.WORK_MODE_CFG2_u._BITS.RX_AUTO_HOP_EN = 0; + g_radio.word_mode_cfg.WORK_MODE_CFG2_u._BITS.RX_ACK_EN = 0; + g_radio.word_mode_cfg.WORK_MODE_CFG2_u._BITS.RX_TIMER_EN = 0; + g_radio.word_mode_cfg.WORK_MODE_CFG2_u._BITS.RX_EXIT_STATE = EXIT_TO_READY; + g_radio.word_mode_cfg.WORK_MODE_CFG2_u._BITS.CSMA_EN = 0; + g_radio.word_mode_cfg.WORK_MODE_CFG3_u._BITS.PKT_DONE_EXIT_EN = 0; //depend on RX_EXIT_STATE + g_radio.word_mode_cfg.WORK_MODE_CFG3_u._BITS.RX_HOP_SLP_MODE = 0; + g_radio.word_mode_cfg.WORK_MODE_CFG3_u._BITS.SLP_MODE = 0; + g_radio.word_mode_cfg.WORK_MODE_CFG4_u._BITS.LFCLK_OUT_EN = 0; + g_radio.word_mode_cfg.WORK_MODE_CFG4_u._BITS.LFCLK_SEL = 0; + g_radio.word_mode_cfg.WORK_MODE_CFG4_u._BITS.SLEEP_TIMER_EN = 0; + g_radio.word_mode_cfg.WORK_MODE_CFG4_u._BITS.TIMER_RAND_MODE = 0; + g_radio.word_mode_cfg.WORK_MODE_CFG5_u._BITS.CSMA_CCA_MODE = 0; + g_radio.word_mode_cfg.WORK_MODE_CFG5_u._BITS.CSMA_CCA_WIN_SEL = 0; + g_radio.word_mode_cfg.WORK_MODE_CFG5_u._BITS.CSMA_CCA_INT_SEL = 0; + g_radio.word_mode_cfg.WORK_MODE_CFG5_u._BITS.CSMA_PERSIST_EN = 0; + + g_radio.word_mode_cfg.WORK_MODE_CFG6_u._BITS.FREQ_HOP_MANU_EN = 1;//使能手动快速跳频，不使能手动跳频无法使用 + + g_radio.word_mode_cfg.FREQ_CHANL_NANU = 92;//手动跳频信道0~255 + g_radio.word_mode_cfg.FREQ_DONE_TIMES = 0; + g_radio.word_mode_cfg.FREQ_SPACE = 250;//跳频信道间隔0~255 KHz + g_radio.word_mode_cfg.FREQ_TIMES = 0; + g_radio.word_mode_cfg.SLEEP_TIMER_M = 0; + g_radio.word_mode_cfg.SLEEP_TIMER_R = 0; + g_radio.word_mode_cfg.RX_TIMER_T1_M = 0; //M*2^(R+1)*5us=M*2^R*10us, + g_radio.word_mode_cfg.RX_TIMER_T1_R = 0; //R=7, unit=0.64ms + g_radio.word_mode_cfg.RX_TIMER_T2_M = 0; + g_radio.word_mode_cfg.RX_TIMER_T2_R = 0; + g_radio.word_mode_cfg.RX_TIMER_CSMA_M = 0; + g_radio.word_mode_cfg.RX_TIMER_CSMA_R = 0; + g_radio.word_mode_cfg.TX_DC_TIMES = 0; + g_radio.word_mode_cfg.TX_RS_TIMES = 0; + g_radio.word_mode_cfg.CSMA_TIMES = 0; + g_radio.word_mode_cfg.SLEEP_TIMER_CSMA_M = 0; + g_radio.word_mode_cfg.SLEEP_TIMER_CSMA_R = 0; + vRadioCfgWorkMode( &g_radio.word_mode_cfg ); + //FIFO Init + vRadioFifoMerge( FALSE ); + vRadioSetFifoTH( 30 ); + vRadioClearRxFifo(); //reset & clear fifo + vRadioClearTxFifo(); + vRadioFifoAutoClearGoRx( TRUE ); //when crc error, need to auto clear fifo, should enable + vRadioRssiUpdateSel( CMT2310A_RSSI_UPDATE_ALWAYS ); + vRadioSetAntSwitch( FALSE, FALSE ); // + vRadioDcdcCfg( TRUE ); //dc-dc off +} + +void vRadioClearInterrupt( void ) +{ + vRadioInterruptSoucreFlag( &g_radio.int_src_flag ); + g_radio.int_src_clear._BITS.SLEEP_TMO_CLR = g_radio.int_src_flag._BITS.SLEEP_TMO_FLG; + g_radio.int_src_clear._BITS.RX_TMO_CLR = g_radio.int_src_flag._BITS.RX_TMO_FLG; + g_radio.int_src_clear._BITS.TX_DONE_CLR = g_radio.int_src_flag._BITS.TX_DONE_FLG; + g_radio.int_src_clear._BITS.PKT_DONE_CLR = g_radio.int_src_flag._BITS.PKT_DONE_FLG; + g_radio.int_src_clear._BITS.CRC_PASS_CLR = g_radio.int_src_flag._BITS.CRC_PASS_FLG; + g_radio.int_src_clear._BITS.ADDR_PASS_CLR = g_radio.int_src_flag._BITS.ADDR_PASS_FLG; + g_radio.int_src_clear._BITS.SYNC_PASS_CLR = g_radio.int_src_flag._BITS.SYNC_PASS_FLG | g_radio.int_src_flag._BITS.SYNC1_PASS_FLG; + g_radio.int_src_clear._BITS.PREAM_PASS_CLR = g_radio.int_src_flag._BITS.PREAM_PASS_FLG; + g_radio.int_src_clear._BITS.LBD_STAT_CLR = g_radio.int_src_flag._BITS.LBD_STATUS_FLG; + g_radio.int_src_clear._BITS.PKT_ERR_CLR = g_radio.int_src_flag._BITS.PKT_ERR_FLG; + g_radio.int_src_clear._BITS.RSSI_COLL_CLR = g_radio.int_src_flag._BITS.RSSI_COLL_FLG; + g_radio.int_src_clear._BITS.OP_CMD_FAILED_CLR = g_radio.int_src_flag._BITS.OP_CMD_FAILED_FLG; + g_radio.int_src_clear._BITS.ANT_LOCK_CLR = g_radio.int_src_flag._BITS.ANT_LOCK_FLG; + g_radio.int_src_clear._BITS.SEQ_MATCH_CLR = g_radio.int_src_flag._BITS.SEQ_MATCH_FLG; + g_radio.int_src_clear._BITS.NACK_RECV_CLR = g_radio.int_src_flag._BITS.NACK_RECV_FLG; + g_radio.int_src_clear._BITS.TX_RESEND_DONE_CLR = g_radio.int_src_flag._BITS.TX_RESEND_DONE_FLG ; + g_radio.int_src_clear._BITS.ACK_RECV_FAILED_CLR = g_radio.int_src_flag._BITS.ACK_RECV_FAILED_FLG; + g_radio.int_src_clear._BITS.TX_DC_DONE_CLR = g_radio.int_src_flag._BITS.TX_DC_DONE_FLG; + g_radio.int_src_clear._BITS.CSMA_DONE_CLR = g_radio.int_src_flag._BITS.CSMA_DONE_FLG; + g_radio.int_src_clear._BITS.CCA_STATUS_CLR = g_radio.int_src_flag._BITS.CCA_STATUS_FLG; + g_radio.int_src_clear._BITS.API_DONE_CLR = g_radio.int_src_flag._BITS.API_DONE_FLG; + vRadioInterruptSoucreClear( &g_radio.int_src_clear ); +} + +void vRadioReadAllStatus( void ) +{ + bRadioGetState(); //read work status + vRadioFifoGetStatus( &g_radio.fifo_status_flag ); //read fifo status + vRadioInterruptSoucreFlag( &g_radio.int_src_flag ); //read interrupt flag + bRadioReadReg( CMT2310A_CTL_REG_04 ); //get GPIO1/GPIO0 selection + bRadioReadReg( CMT2310A_CTL_REG_05 ); //get GPIO3/GPIO2 selection + bRadioReadReg( CMT2310A_CTL_REG_06 ); //get GPIO5/GPIO4 selection + bRadioReadReg( CMT2310A_CTL_REG_16 ); //get INT1 selection + bRadioReadReg( CMT2310A_CTL_REG_17 ); //get INT2 selection +} + +void vRadioCmpReg( byte const wr_ptr[], byte rd_ptr[], byte cmp_ptr[], byte length ) +{ + byte i; + for( i = 0; i < length; i++ ) + { + if( wr_ptr[i] != rd_ptr[i] ) + { + cmp_ptr[i] = 0xFF; + } + else + { + cmp_ptr[i] = 0x00; + } + } +} + +void vRadioGoTxInit( void ) +{ +} + +void vRadioGoRxInit( void ) +{ +} + +void vRadioReceive(void) +{ + g_radio.frame_cfg.PAYLOAD_LENGTH = UHF_LEN; + vRadioSetPayloadLength(&g_radio.frame_cfg); + vRadioSetInt1Sel(CMT2310A_INT_PKT_DONE); + vRadioSetInt2Sel(CMT2310A_INT_RX_FIFO_WBYTE); + bRadioGoRx(); +} + +void vRadioTransmit(uint8_t* buffer, uint8_t length ) +{ + vRadioSetInt1Sel( CMT2310A_INT_TX_DONE ); + vRadioSetInt2Sel( CMT2310A_INT_TX_FIFO_NMTY ); + g_radio.frame_cfg.PAYLOAD_LENGTH = length; + vRadioSetPayloadLength( &g_radio.frame_cfg ); + vRadioWriteFifo( buffer, length ); + // vRadioReadTxFifo(radio_rx_buf, 20); + // vRadioManualResetTxFifoPointer(); + bRadioGoTx(); + + while ( gpio_input_bit_get( BSP_GPIO_PORT_E48_GP4 , BSP_GPIO_PIN_E48_GP4) == RESET); + bRadioGoStandby(); + vRadioClearTxFifo(); + vRadioClearInterrupt(); + + vRadioReceive(); +} + +uint8_t vRadioGetPacket(uint8_t *buffer,uint8_t *length) +{ + uint8_t rx_length; + + if( g_radio.crc_cfg.CRC_CFG_u._BITS.CRC_EN == 1 ) + { + vRadioInterruptSoucreFlag( &g_radio.int_src_flag ); + if( g_radio.int_src_flag._BITS.CRC_PASS_FLG == 1 ) + { +// g_rx_count++; + } + } + else + { +// g_rx_count++; + } + + vRadioReadFifo(&rx_length, 1); + + vRadioReadFifo(buffer, rx_length); + *length = rx_length; + vRadioClearRxFifo(); + vRadioClearInterrupt(); + bRadioGoRx(); + + return 0; +} + + +void vRadioCheckLink(void) +{ + uint8_t i = 0; + + while(1) { + vRadioSoftReset(); + vRadioPowerUpBoot(); + delay1ms(10); + g_chip_id = lRadioChipVersion(); + if(0x00231000==(g_chip_id&0x00FFFF00)) break; + + DEBUGPRINT( "Link Error.....\r\n" ); + delay1ms(500); + i++; + if(i >= 20) while(1); + } + DEBUGPRINT( "Link Device:E48-XXXM20S....\r\n" ); +} + +void vRadioSetFreqChannel(uint8_t channel) +{ + bRadioGoStandby(); + bRadioWriteReg( CMT2310A_CTL_REG_03, channel); +} \ No newline at end of file diff --git a/MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/radio.h b/MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/radio.h new file mode 100755 index 0000000..5d05cbe --- /dev/null +++ b/MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/radio.h @@ -0,0 +1,40 @@ + + +#ifndef __RADIO_H + +#define __RADIO_H + +#include +#include "radio_phy.h" +#include "radio_mac.h" +#include "CMT2310A_def.h" +#include "CMT2310A_reg.h" + +#define UHF_LEN 30 // + + +extern const uint8_t g_cmt2310a_page0[CMT2310A_PAGE0_SIZE]; +extern const uint8_t g_cmt2310a_page1[CMT2310A_PAGE1_SIZE]; +extern const uint8_t g_cmt2310a_page2[CMT2310A_PAGE2_SIZE]; + +extern void vRadioInit( void ); +extern void vRadioClearInterrupt( void ); +extern void vRadioReadAllStatus( void ); +extern void vRadioCmpReg( byte const wr_ptr[], byte rd_ptr[], byte cmp_ptr[], byte length ); +extern void vRadioGoTxInit( void ); +extern void vRadioGoRxInit( void ); + +extern void vRadioTransmit(uint8_t* buffer, uint8_t length ); +extern void vRadioReceive(void); +extern uint8_t vRadioGetPacket(uint8_t *buffer,uint8_t *length); + + +extern void vRadioCheckLink(void); + +extern void vRadioSetFreqChannel(uint8_t channel); + +#endif + + + + diff --git a/MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/radio_hal.c b/MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/radio_hal.c new file mode 100755 index 0000000..d24c790 --- /dev/null +++ b/MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/radio_hal.c @@ -0,0 +1,626 @@ +#include "radio_hal.h" +#include "board.h" + +void delay1ms(uint16_t cnt) +{ + Ebyte_Port_DelayMs(cnt); +} + +void delay10us(uint32_t cnt) +{ + Ebyte_Port_DelayUs(cnt * 10); +} + +/****************************** +**Name: vRadioGpioInit +**Func: Radio SPI-4 and GPIO config +**Input: None +*Output: None +********************************/ +void vRadioGpioInit( void ) +{ + vSpiMasterInit(); //init spi-4 gpio +} + + +/****************************** +**Name: bRadioReadReg +**Func: radio read one register +**Input: None +*Output: read out data +********************************/ +uint8_t bRadioReadReg( uint8_t addr ) +{ + return( bSpiReadByte( addr ) ); +} + +/****************************** +**Name: bRadioWriteReg +**Func: radio write one register +**Input: None +*Output: old data +********************************/ +uint8_t bRadioWriteReg( uint8_t addr, uint8_t reg_dat ) +{ + return( bSpiWriteByte( addr, reg_dat ) ); +} + +/****************************** +**Name: bRadioSetReg +**Func: radio set some bits of register +**Input: None +*Output: old data +********************************/ +uint8_t bRadioSetReg( uint8_t addr, uint8_t set_bits, uint8_t mask_bits ) +{ + uint8_t tmp_dat; + tmp_dat = bSpiReadByte( addr ); + tmp_dat &= ( ~mask_bits ); + tmp_dat |= ( set_bits & mask_bits ); + return( bSpiWriteByte( addr, tmp_dat ) ); +} + +/****************************** +**Name: vRadioLoadRegs +**Func: radio read some registers +**Input: None +*Output: None +********************************/ +void vRadioLoadRegs( uint8_t sta_adr, uint8_t* ptr_buf, uint8_t length ) +{ + uint8_t i; + for( i = 0; i < length; i++ ) + { + ptr_buf[i] = bSpiReadByte( sta_adr++ ); + } +} + +/****************************** +**Name: vRadioStoreRegs +**Func: radio write some registers +**Input: None +*Output: None +********************************/ +void vRadioStoreRegs( uint8_t sta_adr, uint8_t* ptr_buf, uint8_t length ) +{ + uint8_t i; + for( i = 0; i < length; i++ ) + { + bSpiWriteByte( sta_adr++, ptr_buf[i] ); + } +} + +/****************************** +**Name: vRadioBurstReadRegs +**Func: radio read some registers, just for +** Page0, start from 0x28, Packet Config Area & System Config Area, bank 5~15 +** Page1, start from 0x00 +**Input: None +*Output: None +********************************/ +void vRadioBurstReadRegs( uint8_t* ptr_buf, uint8_t length ) +{ + vSpiBurstRead( CMT2310A_CRW_PORT, ptr_buf, length ); +} + +/****************************** +**Name: vRadioBurstWriteRegs +**Func: radio write some registers, just for +** Page0, start from 0x28, Packet Config Area & System Config Area, bank 5~15 +** Page1, start from 0x00 +**Input: None +*Output: None +********************************/ +void vRadioBurstWriteRegs( uint8_t* ptr_buf, uint8_t length ) +{ + vSpiBurstWrite( CMT2310A_CRW_PORT, ptr_buf, length ); +} + +/****************************** +**Name: vRadioReadFifo +**Func: radio read FIFO +**Input: None +*Output: None +********************************/ +void vRadioReadFifo( uint8_t* ptr_fifo, uint8_t length ) +{ + uint8_t tmp; + tmp = bRadioReadReg( CMT2310A_CTL_REG_19 ); + if( tmp & M_FIFO_MERGE_EN ) //when fifo merge + { + tmp &= ( ~M_FIFO_TX_RX_SEL ); + bRadioWriteReg( CMT2310A_CTL_REG_19, tmp ); + } + vSpiBurstRead( CMT2310A_FIFO_RW_PORT, ptr_fifo, length ); +} + + +/****************************** +**Name: vRadioWriteFifo +**Func: radio write FIFO +**Input: None +*Output: None +********************************/ +void vRadioWriteFifo( uint8_t* ptr_fifo, uint8_t length ) +{ + uint8_t tmp; + tmp = bRadioReadReg( CMT2310A_CTL_REG_19 ); + if( tmp & M_FIFO_MERGE_EN ) //when fifo merge + { + tmp &= ( ~M_FIFO_TX_RX_SEL ); + bRadioWriteReg( CMT2310A_CTL_REG_19, tmp ); //TX FIFO + } + vSpiBurstWrite( CMT2310A_FIFO_RW_PORT, ptr_fifo, length ); +} + +/****************************** +**Name: vRadioReadTxFifo +**Func: radio read FIFO +**Input: None +*Output: None +********************************/ +void vRadioReadTxFifo( uint8_t* ptr_fifo, uint8_t length ) +{ + uint8_t tmp; + tmp = bRadioReadReg( CMT2310A_CTL_REG_19 ); + if( tmp & M_FIFO_MERGE_EN ) //when fifo merge + { + tmp &= ( ~M_FIFO_TX_RX_SEL ); + } + tmp |= M_FIFO_TX_TEST_EN; + bRadioWriteReg( CMT2310A_CTL_REG_19, tmp ); + vSpiBurstRead( CMT2310A_FIFO_RW_PORT, ptr_fifo, length ); + tmp &= ( ~M_FIFO_TX_TEST_EN ); + bRadioWriteReg( CMT2310A_CTL_REG_19, tmp ); +} + +//###################################################################### +// GPIO +//###################################################################### +/****************************** +**Name: vRadioSpiModeSel +**Func: Radio SPI-4 or SPI-3 Select +**Input: FALSE: select SPI-4 +* TRUE: select SPI-3 +*Output: None +**note: should be point to page0 +********************************/ +void vRadioSpiModeSel( boolean_t spi_mod ) +{ + if( spi_mod ) + { + bRadioSetReg( CMT2310A_CTL_REG_07, M_SPI_3W_EN, VAL_BIT3 ); + } + else + { + bRadioSetReg( CMT2310A_CTL_REG_07, 0, VAL_BIT3 ); + } +} + +/****************************** +**Name: vRadioSetTxDin +**Func: Radio tx_din enable or disable +**Input: cfg_din, FALSE: disable +* TRUE: enable +* pin_sel, CMT2310A_TX_DIN_GPIO3: GPIO3 as Tx Din +* CMT2310A_TX_DIN_GPIO4: GPIO4 as Tx Din +* CMT2310A_TX_DIN_nIRQ: NIRQ as Tx Din +*Output: None +********************************/ +void vRadioSetTxDin( boolean_t cfg_din, uint8_t pin_sel ) +{ + bRadioSetReg( CMT2310A_CTL_REG_05, pin_sel, CMT2310A_TX_DIN_SEL ); + if( cfg_din ) + { + bRadioSetReg( CMT2310A_CTL_REG_04, CMT2310A_TX_DIN_EN, CMT2310A_TX_DIN_EN ); + vRadioRegPageSel( 1 ); + bRadioSetReg( CMT2310A_TX_DR_REG_02, ( 0 << 7 ), ( 1 << 7 ) ); + vRadioRegPageSel( 0 ); + } + else + { + bRadioSetReg( CMT2310A_CTL_REG_04, 0, CMT2310A_TX_DIN_EN ); + vRadioRegPageSel( 1 ); + bRadioSetReg( CMT2310A_TX_DR_REG_02, ( 1 << 7 ), ( 1 << 7 ) ); + vRadioRegPageSel( 0 ); + } +} + +/****************************** +**Name: vRadioSetDclk +**Func: Radio digital clkout enable or disable +**Input: FALSE: disable +* TRUE: enable +*Output: None +* note: only active on GPIO4, and priority high over than other function on GPIO4 +********************************/ +void vRadioSetDigClkOut( boolean_t cfg_out ) +{ + if( cfg_out ) + { + bRadioSetReg( CMT2310A_CTL_REG_06, CMT2310A_DIG_CLKOUT_EN, CMT2310A_DIG_CLKOUT_EN ); + } + else + { + bRadioSetReg( CMT2310A_CTL_REG_06, 0, CMT2310A_DIG_CLKOUT_EN ); + } +} + +/****************************** +**Name: vRadioSetLfxoPad +**Func: Radio enable or disable exteral 32768Hz xo connect +** when enable this functiong, GPIO2 & GPIO3 as lfxo connect pin +**Input: FALSE: disable +* TRUE: enable +*Output: None +* note: only active on GPIO2 & GPIO3, and priority high over than other function on GPIO2 & GPIO3 +********************************/ +void vRadioSetLfxoPad( boolean_t cfg_lfxo ) +{ + if( cfg_lfxo ) + { + bRadioSetReg( CMT2310A_CTL_REG_07, CMT2310A_LFXO_PAD_EN, CMT2310A_LFXO_PAD_EN ); + } + else + { + bRadioSetReg( CMT2310A_CTL_REG_07, 0, CMT2310A_LFXO_PAD_EN ); + } +} + +/****************************** +**Name: vRadioSetGpio0 +**Func: Radio config GPIO0 +**Input: CMT2310A_GPIO0_DOUT +* CMT2310A_GPIO0_INT1 +* CMT2310A_GPIO0_INT2 +* CMT2310A_GPIO0_DCLK +* CMT2310A_GPIO0_INT3 +*Output: None +********************************/ +void vRadioSetGpio0( uint8_t gpio0_sel ) +{ + bRadioSetReg( CMT2310A_CTL_REG_04, gpio0_sel, CMT2310A_GPIO0_SEL ); +} + +/****************************** +**Name: vRadioSetGpio1 +**Func: Radio config GPIO1 +**Input: CMT2310A_GPIO1_DCLK +* CMT2310A_GPIO1_INT1 +* CMT2310A_GPIO1_INT2 +* CMT2310A_GPIO1_DOUT +*Output: None +********************************/ +void vRadioSetGpio1( uint8_t gpio1_sel ) +{ + bRadioSetReg( CMT2310A_CTL_REG_04, gpio1_sel, CMT2310A_GPIO1_SEL ); +} + +/****************************** +**Name: vRadioSetGpio2 +**Func: Radio config GPIO2 +**Input: CMT2310A_GPIO2_INT1 +* CMT2310A_GPIO2_INT2 +* CMT2310A_GPIO2_DCLK +* CMT2310A_GPIO2_DOUT +* CMT2310A_GPIO2_INT3 +*Output: None +********************************/ +void vRadioSetGpio2( uint8_t gpio2_sel ) +{ + bRadioSetReg( CMT2310A_CTL_REG_05, gpio2_sel, CMT2310A_GPIO2_SEL ); +} + +/****************************** +**Name: vRadioSetGpio3 +**Func: Radio config GPIO3 +**Input: CMT2310A_GPIO3_INT2 +* CMT2310A_GPIO3_INT1 +* CMT2310A_GPIO3_DCLK +* CMT2310A_GPIO3_DOUT +* CMT2310A_GPIO3_DIN +*Output: None +********************************/ +void vRadioSetGpio3( uint8_t gpio3_sel ) +{ + bRadioSetReg( CMT2310A_CTL_REG_05, gpio3_sel, CMT2310A_GPIO3_SEL ); +} + +/****************************** +**Name: vRadioSetGpio4 +**Func: Radio config GPIO4 +**Input: CMT2310A_GPIO4_DOUT +* CMT2310A_GPIO4_INT1 +* CMT2310A_GPIO4_INT2 +* CMT2310A_GPIO4_DCLK +* CMT2310A_GPIO4_DIN +*Output: None +********************************/ +void vRadioSetGpio4( uint8_t gpio4_sel ) +{ + bRadioSetReg( CMT2310A_CTL_REG_06, gpio4_sel, CMT2310A_GPIO4_SEL ); +} + +/****************************** +**Name: vRadioSetGpio5 +**Func: Radio config GPIO5 +**Input: CMT2310A_GPIO5_nRST +* CMT2310A_GPIO5_INT1 +* CMT2310A_GPIO5_INT2 +* CMT2310A_GPIO5_DOUT +* CMT2310A_GPIO5_DCLK +*Output: None +********************************/ +void vRadioSetGpio5( uint8_t gpio5_sel ) +{ + bRadioSetReg( CMT2310A_CTL_REG_06, gpio5_sel, CMT2310A_GPIO5_SEL ); +} + +/****************************** +**Name: vRadioSetNirq +**Func: Radio config NIRQ pin +**Input: CMT2310A_nIRQ_INT1 +* CMT2310A_nIRQ_INT2 +* CMT2310A_nIRQ_DCLK +* CMT2310A_nIRQ_DOUT +* CMT2310A_nIRQ_DIN +*Output: None +********************************/ +void vRadioSetNirq( uint8_t nirq_sel ) +{ + bRadioSetReg( CMT2310A_CTL_REG_07, nirq_sel, CMT2310A_nIRQ_SEL ); +} + +/****************************** +**Name: vRadioTcxoDrvSel +**Func: Radio set TCXO drive power, nIRQ pin +**Input: 0=strengh + 3=week +*Output: None +********************************/ +void vRadioTcxoDrvSel( uint8_t drv_sel ) +{ + vRadioRegPageSel( 1 ); + switch( drv_sel & 0x03 ) + { + case 0: + bRadioSetReg( CMT2310A_CMT_REG_05, ( 0 << 6 ), ( 3 << 6 ) ); + break; + case 1: + bRadioSetReg( CMT2310A_CMT_REG_05, ( 1 << 6 ), ( 3 << 6 ) ); + break; + case 2: + bRadioSetReg( CMT2310A_CMT_REG_05, ( 2 << 6 ), ( 3 << 6 ) ); + break; + default: + bRadioSetReg( CMT2310A_CMT_REG_05, ( 3 << 6 ), ( 3 << 6 ) ); + break; + } + vRadioRegPageSel( 0 ); +} + + +//###################################################################### +// Auxrl +//###################################################################### + +/****************************** +**Name: vRadioRegPageSel +**Func: Radio register page select(page0, page1, page2) +**Input: 1: select page 1 +* 0: select page 0 +* 2: select page 2 +*Output: None +********************************/ +void vRadioRegPageSel( uint8_t page_sel ) +{ + page_sel &= 0x03; + switch( page_sel ) + { + case 2: + bRadioSetReg( CMT2310A_PAGE_CTL_REG, CMT2310A_PAGE_2, CMT2310A_PAGE_SEL_MASK ); + break; + case 1: + bRadioSetReg( CMT2310A_PAGE_CTL_REG, CMT2310A_PAGE_1, CMT2310A_PAGE_SEL_MASK ); + break; + case 0: + default: + bRadioSetReg( CMT2310A_PAGE_CTL_REG, CMT2310A_PAGE_0, CMT2310A_PAGE_SEL_MASK ); + break; + } +} + +/****************************** +**Name: vRadioPowerUpBoot +**Func: Radio power up boot start +**Input: None +*Output: None +********************************/ +void vRadioPowerUpBoot( void ) +{ + bSpiWriteByte( CMT2310A_CTL_REG_00, CMT2310A_REBOOT ); +} + +/****************************** +**Name: vRadioPowerUpBoot +**Func: Radio power up boot start +**Input: None +*Output: None +********************************/ +void vRadioPowerUp( void ) +{ + gpio_bit_write(BSP_GPIO_PORT_E48_GP5, BSP_GPIO_PIN_E48_GP5, RESET); + delay1ms(10); +} + +/****************************** +**Name: vRadioSoftReset +**Func: Radio soft reset +**Input: None +*Output: None +********************************/ +void vRadioSoftReset( void ) +{ + uint8_t i; + + bRadioWriteReg( CMT2310A_SOFT_RST, 0xFF ); + for( i = 0; i < 20; i++ ) + delay10us( 100 ); +} + +/****************************** +**Name: vRadioSoftReset +**Func: Radio soft reset +**Input: None +*Output: None +********************************/ +void vRadioHardReset( void ) +{ + gpio_bit_write(BSP_GPIO_PORT_E48_GP5, BSP_GPIO_PIN_E48_GP5, SET); + delay10us(10); + gpio_bit_write(BSP_GPIO_PORT_E48_GP5, BSP_GPIO_PIN_E48_GP5, RESET); + delay1ms(10); +} + +/****************************** +**Name: vRadioSetPaOutputMode +**Func: Radio config PA output mode +**Input: cfg_en +* FALSE: single ended PA output mode +* TRUE: differential PA output mode +*Output: None +********************************/ +void vRadioSetPaOutputMode( boolean_t cfg_en ) +{ + if( cfg_en ) + { + bRadioSetReg( CMT2310A_CTL_REG_22, CMT2310A_PA_DIFF_SEL, CMT2310A_PA_DIFF_SEL ); + } + else + { + bRadioSetReg( CMT2310A_CTL_REG_22, 0, CMT2310A_PA_DIFF_SEL ); + } +} + +/****************************** +**Name: vRadioSetTxDataInverse +**Func: Radio config Tx Data inverse +**Input: cfg_en +* FALSE: normal +* TRUE: inverse +*Output: None +********************************/ +void vRadioSetTxDataInverse( boolean_t cfg_en ) +{ + if( cfg_en ) + { + bRadioSetReg( CMT2310A_CTL_REG_22, CMT2310A_TX_DATA_INV, CMT2310A_TX_DATA_INV ); + } + else + { + bRadioSetReg( CMT2310A_CTL_REG_22, 0, CMT2310A_TX_DATA_INV ); + } +} + +/****************************** +**Name: vRadioSetAntSwitch +**Func: Radio config GPIO0 & GPIO1 as antenna switch control +**Input: cfg_en, FALSE: disable antenna switch function +* TRUE: enable antenna switch function +* +* GPIO0 GPIO1 +* cfg_polar, FALSE: RX_STATE 1 0 +* TX_STATE 0 1 +* +* TRUE: RX_STATE 0 1 +* TX_STATE 1 0 +*Output: None +* note: priority high over than other function on GPIO0 & GPIO1 +********************************/ +void vRadioSetAntSwitch( boolean_t cfg_en, boolean_t cfg_polar ) +{ + uint8_t cfg_tmp = 0; + + if( cfg_en ) + cfg_tmp |= CMT2310A_TRX_SWT_EN; + if( cfg_polar ) + cfg_tmp |= CMT2310A_TRX_SWT_INV; + bRadioSetReg( CMT2310A_CTL_REG_22, cfg_tmp, ( CMT2310A_TRX_SWT_EN | CMT2310A_TRX_SWT_INV ) ); +} + +/****************************** +**Name: vRadioDcdcCfg +**Func: Radio DC-DC config +**Input: cfg_en +* FALSE: normal +* TRUE: inverse +*Output: None +********************************/ +void vRadioDcdcCfg( boolean_t on_off ) +{ + vRadioRegPageSel( 1 ); + if( on_off ) //Buck_sel = 1; + { + bRadioSetReg( CMT2310A_CMT_REG_01, 0x10, 0x10 ); + } + else + { + bRadioSetReg( CMT2310A_CMT_REG_01, 0x00, 0x10 ); + } + vRadioRegPageSel( 0 ); +} + +/****************************** +**Name: vRadioCapLoad +**Func: Radio Set Cap load value +**Input: cap value, range 0-31 +*Output: None +********************************/ +void vRadioCapLoad( uint8_t cap_value ) +{ + cap_value &= 0x1F; + vRadioRegPageSel( 1 ); + bRadioSetReg( CMT2310A_CMT_REG_06, cap_value, 0x1F ); + vRadioRegPageSel( 0 ); +} + +/****************************** +**Name: vRadioLfoscCfg +**Func: Radio Set LFOSC +**Input: TRUE: enable +** FALSE: disable +*Output: None +********************************/ +void vRadioLfoscCfg( boolean_t on_off ) +{ + vRadioRegPageSel( 1 ); + if( on_off ) + { + bRadioSetReg( CMT2310A_CMT_REG_13, 0x38, 0x38 ); + } + else + { + bRadioSetReg( CMT2310A_CMT_REG_13, 0x00, 0x38 ); + } + vRadioRegPageSel( 0 ); +} + +/****************************** +**Name: vRadioXoWaitCfg +**Func: Radio Set xtal wait for pu_boot +**Input: + pu_boot(us) slp2rdy(us) + RADIO_CGU_DIV1-> 1344 584 + RADIO_CGU_DIV4-> 3972 1013 + RADIO_CGU_DIV8-> 6624 1586 +*Output: None +********************************/ +void vRadioXoWaitCfg( uint8_t div_sel ) +{ + div_sel &= 0x03; + div_sel <<= 6; + vRadioRegPageSel( 0 ); + bRadioSetReg( CMT2310A_CTL_REG_07, div_sel, CMT2310A_CTL_REG_07_MASK ); + vRadioRegPageSel( 0 ); +} + diff --git a/MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/radio_hal.h b/MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/radio_hal.h new file mode 100755 index 0000000..d3a8ed3 --- /dev/null +++ b/MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/radio_hal.h @@ -0,0 +1,89 @@ + + +#ifndef __RADIO_HAL_H + +#define __RADIO_HAL_H + +//#include "stm8l15x.h" +#include "gd32w51x.h" +#include "ebyte_port.h" + + +//基础频点只能从以下选择 +#define CM2310A_410MHZ 0 +#define CM2310A_433MHZ 1 +#define CM2310A_868MHZ 2 +#define CM2310A_915MHZ 3 + +#define PRODUCT_FREQUENCY CM2310A_410MHZ//选择基础频点 + +#include "radio_spi.h" +#include "CMT2310A_def.h" +#include "CMT2310A_reg.h" + +#define RADIO_CGU_DIV1 0 +#define RADIO_CGU_DIV4 1 +#define RADIO_CGU_DIV8 2 + +#ifndef TRUE +/** Value is true (boolean_t type) */ +#define TRUE ((boolean_t) 1u) +#endif + +#ifndef FALSE +/** Value is false (boolean_t type) */ +#define FALSE ((boolean_t) 0u) +#endif +typedef uint8_t boolean_t; +typedef uint8_t byte; + +extern void vRadioGpioInit( void ); + +extern uint8_t bRadioReadReg( uint8_t addr ); +extern uint8_t bRadioWriteReg( uint8_t addr, uint8_t reg_dat ); +extern uint8_t bRadioSetReg( uint8_t addr, uint8_t set_bits, uint8_t mask_bits ); + +extern void vRadioLoadRegs( uint8_t sta_adr, uint8_t* ptr_buf, uint8_t length ); +extern void vRadioStoreRegs( uint8_t sta_adr, uint8_t* ptr_buf, uint8_t length ); + +extern void vRadioBurstReadRegs( uint8_t* ptr_buf, uint8_t length ); +extern void vRadioBurstWriteRegs( uint8_t* ptr_buf, uint8_t length ); + +extern void vRadioReadFifo( uint8_t* ptr_fifo, uint8_t length ); +extern void vRadioWriteFifo( uint8_t* ptr_fifo, uint8_t length ); +extern void vRadioReadTxFifo( uint8_t* ptr_fifo, uint8_t length ); + + +extern void vRadioSpiModeSel( boolean_t spi_mod ); +extern void vRadioSetTxDin( boolean_t cfg_din, uint8_t pin_sel ); +extern void vRadioSetDigClkOut( boolean_t cfg_out ); +extern void vRadioSetLfxoPad( boolean_t cfg_lfxo ); +extern void vRadioSetGpio0( uint8_t gpio0_sel ); +extern void vRadioSetGpio1( uint8_t gpio1_sel ); +extern void vRadioSetGpio2( uint8_t gpio2_sel ); +extern void vRadioSetGpio3( uint8_t gpio3_sel ); +extern void vRadioSetGpio4( uint8_t gpio4_sel ); +extern void vRadioSetGpio5( uint8_t gpio5_sel ); +extern void vRadioSetNirq( uint8_t nirq_sel ); +extern void vRadioTcxoDrvSel( uint8_t drv_sel ); + +extern void vRadioRegPageSel( uint8_t page_sel ); +extern void vRadioPowerUp( void ); +extern void vRadioPowerUpBoot( void ); +extern void vRadioHardReset( void ); +extern void vRadioSoftReset( void ); +extern void vRadioSetPaOutputMode( boolean_t cfg_en ); +extern void vRadioSetTxDataInverse( boolean_t cfg_en ); +extern void vRadioSetAntSwitch( boolean_t cfg_en, boolean_t cfg_polar ); + +extern void vRadioDcdcCfg( boolean_t on_off ); +extern void vRadioCapLoad( uint8_t cap_value ); +extern void vRadioLfoscCfg( boolean_t on_off ); +extern void vRadioXoWaitCfg( uint8_t div_sel ); + +extern void delay1ms(uint16_t cnt); +extern void delay10us(uint32_t cnt); +#endif + + + diff --git a/MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/radio_mac.c b/MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/radio_mac.c new file mode 100755 index 0000000..c4971b3 --- /dev/null +++ b/MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/radio_mac.c @@ -0,0 +1,482 @@ +#include "radio_mac.h" + +/****************************** +**Name: bRadioGetCurrentChannl +**Func: Radio get current active channl number +**Input: None +*Output: channl number +********************************/ +uint8_t bRadioGetCurrentChannl( void ) +{ + return( bRadioReadReg( CMT2310A_FREQ_CHANL_ACT_REG ) ); +} + +/****************************** +**Name: vRadioSetTxSeqNumber +**Func: Radio set transmit sequence number +**Input: transmit init sequence number +*Output: None +********************************/ +void vRadioSetTxSeqNumberInitValue( FRAME_CFG* frm_cfg ) +{ + bRadioWriteReg( CMT2310A_SEQNUM_TX_IN_L_REG, ( uint8_t )( ( *frm_cfg ).SEQNUM_TX_IN ) ); + bRadioWriteReg( CMT2310A_SEQNUM_TX_IN_H_REG, ( uint8_t )( ( ( *frm_cfg ).SEQNUM_TX_IN ) >> 8 ) ); +} + +/****************************** +**Name: wRadioGetTxSeqNumber +**Func: Radio get current transmit sequence number +**Input: None +*Output: current transmit sequence number +********************************/ +uint16_t wRadioGetTxSeqNumberCurrent( FRAME_CFG* frm_cfg ) +{ + uint16_t seq_num = 0; + seq_num = bRadioReadReg( CMT2310A_SEQNUM_TX_OUT_H_REG ); + seq_num <<= 8; + seq_num |= bRadioReadReg( CMT2310A_SEQNUM_TX_OUT_L_REG ); + ( *frm_cfg ).SEQNUM_TX_CURRENT_OUT = seq_num; + return( ( *frm_cfg ).SEQNUM_TX_CURRENT_OUT = seq_num ); +} + + +/****************************** +**Name: vRadioSetTxFCS2 +**Func: Radio set transmit packet FCS2 value +**Input: transmit FCS2 +*Output: None +********************************/ +void vRadioSetTxFCS2( FRAME_CFG* frm_cfg ) +{ + bRadioWriteReg( CMT2310A_FCS2_TX_IN_REG, ( *frm_cfg ).FCS2_TX_IN ); +} + +/****************************** +**Name: vRadioGetRxFCS2 +**Func: Radio get receive packet FCS2 value +**Input: None +*Output: receive FCS2 +********************************/ +uint8_t bRadioGetRxFCS2( FRAME_CFG* frm_cfg ) +{ + ( *frm_cfg ).FCS2_RX_OUT = bRadioReadReg( CMT2310A_FCS2_RX_OUT_REG ); + return( ( *frm_cfg ).FCS2_RX_OUT ); +} + +/****************************** +**Name: vRadioSetPayloadLength +**Func: Radio config payload length +**Input: length +*Output: None +********************************/ +void vRadioSetPayloadLength( FRAME_CFG* frm_cfg ) +{ + uint16_t len; + if( ( *frm_cfg ).PAYLOAD_LENGTH != 0 ) + { + len = ( *frm_cfg ).PAYLOAD_LENGTH - 1; + bRadioWriteReg( CMT2310A_PAYLOAD_LENGTH_L_REG, ( byte )len ); + bRadioWriteReg( CMT2310A_PAYLOAD_LENGTH_H_REG, ( byte )( len >> 8 ) ); + } +} + +/****************************** +**Name: wRadioGetPayloadLength +**Func: Radio get payload length +**Input: None +*Output: payload length +********************************/ +uint16_t vRadioGetPayloadLength( FRAME_CFG* frm_cfg ) +{ + uint16_t length = 0; + length = bRadioReadReg( CMT2310A_PAYLOAD_LENGTH_H_REG ); + length <<= 8; + length |= bRadioReadReg( CMT2310A_PAYLOAD_LENGTH_L_REG ); + ( *frm_cfg ).PAYLOAD_LENGTH = length + 1; + return( length ); +} + +//###################################################################### +// Packet config +//###################################################################### +/****************************** +**Name: vRadioCfgPreamble +**Func: Radio config preamble +**Input: preamble struct +*Output: None +********************************/ +void vRadioCfgPreamble( PREAMBLE_CFG* prm_ptr ) +{ + uint8_t cfg_tmp; + cfg_tmp = bRadioReadReg( CMT2310A_CTL_REG_40 ); + if( ( *prm_ptr ).PREAM_LENG_UNIT == 0 ) + { + cfg_tmp &= ( ~CMT2310A_PREAM_LENG_UNIIT ); + } + else + { + cfg_tmp |= CMT2310A_PREAM_LENG_UNIIT; + } + cfg_tmp &= ( ~CMT2310A_RX_PREAM_SIZE_MASK ); + cfg_tmp |= ( ( ( ( *prm_ptr ).RX_PREAM_SIZE ) << 3 )&CMT2310A_RX_PREAM_SIZE_MASK ); + bRadioWriteReg( CMT2310A_CTL_REG_40, cfg_tmp ); + bRadioWriteReg( CMT2310A_CTL_REG_41, ( uint8_t )( ( *prm_ptr ).TX_PREAM_SIZE ) ); + bRadioWriteReg( CMT2310A_CTL_REG_42, ( uint8_t )( ( *prm_ptr ).TX_PREAM_SIZE >> 8 ) ); + bRadioWriteReg( CMT2310A_CTL_REG_43, ( *prm_ptr ).PREAM_VALUE ); +} + +/****************************** +**Name: vRadioCfgSyncWord +**Func: Radio config sync word +**Input: sync word struct +*Output: None +********************************/ +void vRadioCfgSyncWord( SYNC_CFG* sync_ptr ) +{ + uint8_t i; + uint8_t adr; + bRadioWriteReg( CMT2310A_CTL_REG_44, ( *sync_ptr ).SYN_CFG_u.SYNC_CFG_REG ); + for( i = 0, adr = CMT2310A_CTL_REG_52; i < 8; i++, adr-- ) + { + bRadioWriteReg( adr, ( *sync_ptr ).SYNC_VALUE[i] ); + bRadioWriteReg( ( adr + 8 ), ( *sync_ptr ).SYNC_FEC_VALUE[i] ); + } + if( ( *sync_ptr ).SYNC_VALUE_SEL == 0 ) + { + bRadioSetReg( CMT2310A_CTL_REG_64, 0, CMT2310A_SYNC_VALUE_SEL ); + } + else + { + bRadioSetReg( CMT2310A_CTL_REG_64, CMT2310A_SYNC_VALUE_SEL, CMT2310A_SYNC_VALUE_SEL ); + } +} + +/****************************** +**Name: vRadioCfgNodeAddr +**Func: Radio config node address +**Input: node address struct +*Output: None +********************************/ +void vRadioCfgNodeAddr( ADDR_CFG* node_addr_ptr ) +{ + uint8_t cfg_tmp; + cfg_tmp = bRadioReadReg( CMT2310A_CTL_REG_64 ); + cfg_tmp &= 0x80; + cfg_tmp |= ( ( *node_addr_ptr ).ADDR_CFG_u.ADDR_CFG_REG & 0x7F ); + bRadioWriteReg( CMT2310A_CTL_REG_64, cfg_tmp ); + bRadioWriteReg( CMT2310A_SRC_ADDR_L_REG, ( *node_addr_ptr ).SRC_ADDR[0] ); + bRadioWriteReg( CMT2310A_SRC_ADDR_H_REG, ( *node_addr_ptr ).SRC_ADDR[1] ); + bRadioWriteReg( CMT2310A_DEST_ADDR_L_REG, ( *node_addr_ptr ).DEST_ADDR[0] ); + bRadioWriteReg( CMT2310A_DEST_ADDR_H_REG, ( *node_addr_ptr ).DEST_ADDR[1] ); + bRadioWriteReg( CMT2310A_SRC_BITMASK_L_REG, ( *node_addr_ptr ).SRC_BITMASK[0] ); + bRadioWriteReg( CMT2310A_SRC_BITMASK_H_REG, ( *node_addr_ptr ).SRC_BITMASK[1] ); + bRadioWriteReg( CMT2310A_DEST_BITMASK_L_REG, ( *node_addr_ptr ).DEST_BITMASK[0] ); + bRadioWriteReg( CMT2310A_DEST_BITMASK_H_REG, ( *node_addr_ptr ).DEST_BITMASK[1] ); +} + +/****************************** +**Name: vRadioCfgCrc +**Func: Radio config crc +**Input: crc struct +*Output: None +********************************/ +void vRadioCfgCrc( CRC_CFG* crc_ptr ) +{ + uint8_t i, adr; + bRadioWriteReg( CMT2310A_CTL_REG_73, ( uint8_t )( ( *crc_ptr ).CRC_CFG_u.CRC_CFG_REG ) ); + for( i = 0, adr = CMT2310A_CTL_REG_74; i < 4; i++, adr++ ) + { + bRadioWriteReg( adr, ( *crc_ptr ).CRC_SEED_u.u8_SEED[i] ); + bRadioWriteReg( ( adr + 4 ), ( *crc_ptr ).CRC_POLY_u.u8_POLY[i] ); + } + if( ( *crc_ptr ).CRC_CFG_u._BITS.CRC_REFOUT ) + { + bRadioSetReg( CMT2310A_CTL_REG_82, CMT2310A_CRC_REFOUT, CMT2310A_CRC_REFOUT ); + } + else + { + bRadioSetReg( CMT2310A_CTL_REG_82, 0, CMT2310A_CRC_REFOUT ); + } + if( ( *crc_ptr ).CRC_CFG_u._BITS.CRCERR_CLR_FIFO_EN ) + { + bRadioSetReg( CMT2310A_CTL_REG_84, CMT2310A_CRCERR_CLR_FIFO_EN, CMT2310A_CRCERR_CLR_FIFO_EN ); + } + else + { + bRadioSetReg( CMT2310A_CTL_REG_84, 0, CMT2310A_CRCERR_CLR_FIFO_EN ); + } +} + +/****************************** +**Name: vRadioCfgCodeFormat +**Func: Radio config code format +**Input: code format struct +*Output: None +********************************/ +void vRadioCfgCodeFormat( CODING_FORMAT_CFG* code_format_ptr ) +{ + uint8_t cfg_tmp; + cfg_tmp = bRadioReadReg( CMT2310A_CTL_REG_82 ); + cfg_tmp &= 0x80; + cfg_tmp |= ( ( *code_format_ptr ).CODING_FORMAT_CFG_u.CODING_CFG_REG & 0x3F ); + if( ( *code_format_ptr ).WHITEN_SEED & 0x0100 ) + { + cfg_tmp |= CMT2310A_WHITEN_SEED_B8; + } + bRadioWriteReg( CMT2310A_CTL_REG_82, cfg_tmp ); + bRadioWriteReg( CMT2310A_CTL_REG_83, ( uint8_t )( ( *code_format_ptr ).WHITEN_SEED ) ); + cfg_tmp = ( ( *code_format_ptr ).CODING_FORMAT_CFG_u.CODING_CFG_REG >> 8 ); + cfg_tmp &= ( ~CMT2310A_FEC_PAD_CODE_H_MASK ); + cfg_tmp |= ( ( uint8_t )( ( ( *code_format_ptr ).FEC_PAD_CODE ) >> 6 )&CMT2310A_FEC_PAD_CODE_H_MASK ); + bRadioWriteReg( CMT2310A_CTL_REG_93, cfg_tmp ); + bRadioWriteReg( CMT2310A_CTL_REG_94, ( uint8_t )( ( *code_format_ptr ).FEC_PAD_CODE ) ); +} + +/****************************** +**Name: vRadioCfgFrameFormat +**Func: Radio config frame format +**Input: frame format struct +*Output: None +********************************/ +void vRadioCfgFrameFormat( FRAME_CFG* frame_format_ptr ) +{ + uint8_t cfg_tmp; + bRadioSetReg( CMT2310A_CTL_REG_40, ( *frame_format_ptr ).DATA_MODE, CMT2310A_DATA_MODE_MASK ); + bRadioWriteReg( CMT2310A_CTL_REG_63, ( *frame_format_ptr ).FRAME_CFG1_u.FRAME_CFG1_REG ); + cfg_tmp = bRadioReadReg( CMT2310A_CTL_REG_84 ); + cfg_tmp &= 0x80; + cfg_tmp |= ( ( *frame_format_ptr ).FRAME_CFG2_u.FRAME_CFG2_REG & 0x7F ); + bRadioWriteReg( CMT2310A_CTL_REG_84, cfg_tmp ); + bRadioWriteReg( CMT2310A_TX_PKT_NUM_L_REG, ( uint8_t )( *frame_format_ptr ).TX_PKT_NUM ); + bRadioWriteReg( CMT2310A_TX_PKT_NUM_H_REG, ( uint8_t )( ( *frame_format_ptr ).TX_PKT_NUM >> 8 ) ); + bRadioWriteReg( CMT2310A_SEQNUM_TX_IN_L_REG, ( uint8_t )( *frame_format_ptr ).SEQNUM_TX_IN ); + bRadioWriteReg( CMT2310A_SEQNUM_TX_IN_H_REG, ( uint8_t )( ( *frame_format_ptr ).SEQNUM_TX_IN >> 8 ) ); + bRadioWriteReg( CMT2310A_TX_PKT_GAP_REG, ( *frame_format_ptr ).TX_PKT_GAP ); + bRadioWriteReg( CMT2310A_FCS2_TX_IN_REG, ( *frame_format_ptr ).FCS2_TX_IN ); + bRadioWriteReg( CMT2310A_FCS2_RX_OUT_REG, ( *frame_format_ptr ).FCS2_RX_OUT ); +} + +/****************************** +**Name: vRadioCfgFrameFormat +**Func: Radio config frame format +**Input: frame format struct +*Output: None +********************************/ +void vRadioCfgWiSunFormat( WI_SUN_CFG* wi_sun_ptr ) +{ + bRadioWriteReg( CMT2310A_CTL_REG_111, ( *wi_sun_ptr ).WI_SUN_REG ); +} + +/****************************** +**Name: vRadioCdrTracingModeCfg +**Func: Radio config cdr tracing config +**Input: cdr tracing +*Output: None +********************************/ +void vRadioCdrTracingModeCfg( CDR_TRACING_CFG* cdr_ptr ) +{ + vRadioRegPageSel( 1 ); + bRadioWriteReg( CMT2310A_RX_CDR_REG_00, ( *cdr_ptr ).CDR_CFG0_u.CDR_CFG0_REG ); + ( *cdr_ptr ).CDR_CFG1_u.CDR_CFG1_REG &= 0xF8; + ( *cdr_ptr ).CDR_CFG1_u.CDR_CFG1_REG |= ( ( uint8_t )( ( *cdr_ptr ).CDR_BR_TH >> 16 ) & 0x07 ); + bRadioSetReg( CMT2310A_RX_CDR_REG_03, ( *cdr_ptr ).CDR_CFG1_u.CDR_CFG1_REG, 0x1F ); + bRadioWriteReg( CMT2310A_RX_CDR_REG_01, ( uint8_t )( *cdr_ptr ).CDR_BR_TH ); + bRadioWriteReg( CMT2310A_RX_CDR_REG_02, ( uint8_t )( ( *cdr_ptr ).CDR_BR_TH >> 8 ) ); + vRadioRegPageSel( 0 ); +} + + +//###################################################################### +// System control +//###################################################################### +void vRadioCfgWorkMode( WORK_MODE_CFG* run_mode_ptr ) +{ + bRadioWriteReg( CMT2310A_CTL_REG_03, ( *run_mode_ptr ).FREQ_CHANL_NANU ); + bRadioWriteReg( CMT2310A_CTL_REG_12, ( *run_mode_ptr ).FREQ_SPACE ); + bRadioWriteReg( CMT2310A_CTL_REG_13, ( *run_mode_ptr ).FREQ_TIMES ); + bRadioWriteReg( CMT2310A_CTL_REG_96, ( *run_mode_ptr ).WORK_MODE_CFG1_u.WORK_MODE_CFG1_REG ); + bRadioWriteReg( CMT2310A_CTL_REG_97, ( *run_mode_ptr ).WORK_MODE_CFG2_u.WORK_MODE_CFG2_REG ); + bRadioWriteReg( CMT2310A_CTL_REG_98, ( *run_mode_ptr ).WORK_MODE_CFG3_u.WORK_MODE_CFG3_REG ); + bRadioWriteReg( CMT2310A_CTL_REG_105, ( *run_mode_ptr ).WORK_MODE_CFG4_u.WORK_MODE_CFG4_REG ); + bRadioWriteReg( CMT2310A_CTL_REG_106, ( *run_mode_ptr ).WORK_MODE_CFG5_u.WORK_MODE_CFG5_REG ); + bRadioSetReg( CMT2310A_CTL_REG_22, ( *run_mode_ptr ).WORK_MODE_CFG6_u.WORK_MODE_CFG6_REG, 0xC0 ); + bRadioWriteReg( CMT2310A_CTL_REG_99, ( uint8_t )( ( *run_mode_ptr ).SLEEP_TIMER_M ) ); + bRadioWriteReg( CMT2310A_CTL_REG_100, ( ( ( uint8_t )( ( *run_mode_ptr ).SLEEP_TIMER_M >> 3 ) ) & 0xE0 ) | ( ( *run_mode_ptr ).SLEEP_TIMER_R & 0x1F ) ); + bRadioWriteReg( CMT2310A_CTL_REG_101, ( uint8_t )( ( *run_mode_ptr ).RX_TIMER_T1_M ) ); + bRadioWriteReg( CMT2310A_CTL_REG_102, ( ( ( uint8_t )( ( *run_mode_ptr ).RX_TIMER_T1_M >> 3 ) ) & 0xE0 ) | ( ( *run_mode_ptr ).RX_TIMER_T1_R & 0x1F ) ); + bRadioWriteReg( CMT2310A_CTL_REG_103, ( uint8_t )( ( *run_mode_ptr ).RX_TIMER_T2_M ) ); + bRadioWriteReg( CMT2310A_CTL_REG_104, ( ( ( uint8_t )( ( *run_mode_ptr ).RX_TIMER_T2_M >> 3 ) ) & 0xE0 ) | ( ( *run_mode_ptr ).RX_TIMER_T2_R & 0x1F ) ); + bRadioWriteReg( CMT2310A_CTL_REG_107, ( uint8_t )( ( *run_mode_ptr ).RX_TIMER_CSMA_M ) ); + bRadioWriteReg( CMT2310A_CTL_REG_108, ( ( ( uint8_t )( ( *run_mode_ptr ).RX_TIMER_CSMA_M >> 3 ) ) & 0xE0 ) | ( ( *run_mode_ptr ).RX_TIMER_CSMA_R & 0x1F ) ); + bRadioWriteReg( CMT2310A_CTL_REG_110, ( *run_mode_ptr ).TX_DC_TIMES ); + bRadioWriteReg( CMT2310A_CTL_REG_113, ( *run_mode_ptr ).TX_RS_TIMES ); + bRadioWriteReg( CMT2310A_CTL_REG_115, ( *run_mode_ptr ).CSMA_TIMES ); + bRadioWriteReg( CMT2310A_CTL_REG_118, ( uint8_t )( ( *run_mode_ptr ).SLEEP_TIMER_CSMA_M ) ); + bRadioWriteReg( CMT2310A_CTL_REG_119, ( ( ( uint8_t )( ( *run_mode_ptr ).SLEEP_TIMER_CSMA_M >> 3 ) ) & 0xE0 ) | ( ( *run_mode_ptr ).SLEEP_TIMER_CSMA_R & 0x1F ) ); +} + +void vRadioReadRunModeCfg( void ) +{ + bRadioReadReg( CMT2310A_CTL_REG_11 ); + bRadioReadReg( CMT2310A_CTL_REG_12 ); + bRadioReadReg( CMT2310A_CTL_REG_13 ); + bRadioReadReg( CMT2310A_CTL_REG_96 ); + bRadioReadReg( CMT2310A_CTL_REG_97 ); + bRadioReadReg( CMT2310A_CTL_REG_98 ); + bRadioReadReg( CMT2310A_CTL_REG_105 ); + bRadioReadReg( CMT2310A_CTL_REG_106 ); + bRadioReadReg( CMT2310A_CTL_REG_99 ); + bRadioReadReg( CMT2310A_CTL_REG_100 ); + bRadioReadReg( CMT2310A_CTL_REG_101 ); + bRadioReadReg( CMT2310A_CTL_REG_102 ); + bRadioReadReg( CMT2310A_CTL_REG_103 ); + bRadioReadReg( CMT2310A_CTL_REG_104 ); + bRadioReadReg( CMT2310A_CTL_REG_107 ); + bRadioReadReg( CMT2310A_CTL_REG_108 ); + bRadioReadReg( CMT2310A_CTL_REG_110 ); + bRadioReadReg( CMT2310A_CTL_REG_113 ); + bRadioReadReg( CMT2310A_CTL_REG_115 ); + bRadioReadReg( CMT2310A_CTL_REG_118 ); + bRadioReadReg( CMT2310A_CTL_REG_119 ); +} + +uint8_t bRadioGetTxDutyCycleDoneTimes( WORK_MODE_CFG* run_mode_ptr ) +{ + ( *run_mode_ptr ).TX_DC_DONE_TIMES = bRadioReadReg( CMT2310A_CTL_REG_112 ); + return( ( *run_mode_ptr ).TX_DC_DONE_TIMES ); +} + +uint8_t bRadioGetTxResendDoneTimes( WORK_MODE_CFG* run_mode_ptr ) +{ + ( *run_mode_ptr ).TX_RS_DONE_TIMES = bRadioReadReg( CMT2310A_CTL_REG_114 ); + return( ( *run_mode_ptr ).TX_RS_DONE_TIMES ); +} + +uint8_t bRadioGetCMSADoneTimes( WORK_MODE_CFG* run_mode_ptr ) +{ + ( *run_mode_ptr ).CSMA_DONE_TIMES = bRadioReadReg( CMT2310A_CTL_REG_116 ); + return( ( *run_mode_ptr ).CSMA_DONE_TIMES ); +} + +void vRadioSendWithAck( boolean_t w_ack, FRAME_CFG* frame_format_ptr ) +{ + uint8_t tmp; + tmp = bRadioReadReg( CMT2310A_FCS2_TX_IN_REG ); + if( w_ack ) + { + ( *frame_format_ptr ).FCS2_TX_IN = tmp | 0x80; + } + else + { + ( ( *frame_format_ptr ) ).FCS2_TX_IN = tmp & 0x7F; + } + bRadioWriteReg( CMT2310A_FCS2_TX_IN_REG, ( ( *frame_format_ptr ) ).FCS2_TX_IN ); +} + + + +void vRadioEnableTxAck( boolean_t en_flg, WORK_MODE_CFG* run_mode_ptr ) +{ + if( en_flg ) + { + ( *run_mode_ptr ).WORK_MODE_CFG1_u._BITS.TX_ACK_EN = 1; //enable TX_ACK + ( *run_mode_ptr ).WORK_MODE_CFG2_u._BITS.RX_TIMER_EN = 1; + } + else + { + ( *run_mode_ptr ).WORK_MODE_CFG1_u._BITS.TX_ACK_EN = 0; //disable TX_ACK + ( *run_mode_ptr ).WORK_MODE_CFG2_u._BITS.RX_TIMER_EN = 0; + } + vRadioCfgWorkMode( run_mode_ptr ); +} + + +void vRadioEnableRxAck( boolean_t en_flg, WORK_MODE_CFG* run_mode_ptr ) +{ + if( en_flg ) + { + ( *run_mode_ptr ).WORK_MODE_CFG2_u._BITS.RX_ACK_EN = 1; //enable RX_ACK + } + else + { + ( *run_mode_ptr ).WORK_MODE_CFG2_u._BITS.RX_ACK_EN = 0; //disable RX_ACK + } + vRadioCfgWorkMode( run_mode_ptr ); +} + + +uint8_t bRadioGetFreqChanl( void ) +{ + return( bRadioReadReg( CMT2310A_FREQ_CHANL_ACT_REG ) ); +} + +uint8_t bRadioGetHopDoneTimes( void ) +{ + return( bRadioReadReg( CMT2310A_CTL_REG_11 ) ); +} + + +void vRadioCsmaEnable( boolean_t on_off, WORK_MODE_CFG* run_mode_ptr ) +{ + if( on_off ) + { + ( *run_mode_ptr ).WORK_MODE_CFG2_u._BITS.RX_TIMER_EN = 1; + if( ( *run_mode_ptr ).CSMA_TIMES != 0 ) + { + ( *run_mode_ptr ).WORK_MODE_CFG4_u._BITS.SLEEP_TIMER_EN = 1; + } + ( *run_mode_ptr ).WORK_MODE_CFG2_u._BITS.CSMA_EN = 1; + } + else + { + ( *run_mode_ptr ).WORK_MODE_CFG2_u._BITS.RX_TIMER_EN = 0; + ( *run_mode_ptr ).WORK_MODE_CFG4_u._BITS.SLEEP_TIMER_EN = 0; + ( *run_mode_ptr ).WORK_MODE_CFG2_u._BITS.CSMA_EN = 0; + } + vRadioCfgWorkMode( run_mode_ptr ); +} + +void vRadioSetRssiAbsThValue( int8_t rssi ) +{ + vRadioRegPageSel( 1 ); + bRadioWriteReg( CMT2310A_RSSI_ABS_TH_REG, ( uint8_t )rssi ); + vRadioRegPageSel( 0 ); +} + +void vRadioSetPjdDetWin( uint8_t pjd_win ) //0:4-jump, 1:6-jump, 2:8-jump, 3:10-jump +{ + pjd_win &= 0x03; + pjd_win <<= 4; + vRadioRegPageSel( 1 ); //CMT2310A_RX_2FSK_REG_01 is in bank1 + bRadioSetReg( CMT2310A_RX_2FSK_REG_01, pjd_win, 0x30 ); + vRadioRegPageSel( 0 ); +} + + + + + + + + + +// +//void vRadioSetFreq(const byte *ptr) +//{ +// byte i; +// byte adr; +// vRadioRegPageSel(1); +// adr = CMT2310A_TX_FREQ_REG_00; +// for(i=0; i<4; i++) +// bSpiWriteByte(adr++, ptr[i]); +// +// adr = CMT2310A_RX_FREQ_REG_01; +// for( ; i<8; i++) +// bSpiWriteByte(adr++, ptr[i]); +// vRadioRegPageSel(0); +//} +// + + + + diff --git a/MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/radio_mac.h b/MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/radio_mac.h new file mode 100755 index 0000000..7268562 --- /dev/null +++ b/MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/radio_mac.h @@ -0,0 +1,49 @@ +#ifndef __RADIO_MAC_H + +#define __RADIO_MAC_H + +#include "radio_hal.h" +#include "CMT2310A_def.h" +#include "CMT2310A_reg.h" + + +extern uint8_t bRadioGetCurrentChannl(void); + +extern void vRadioSetTxSeqNumberInitValue(FRAME_CFG *frm_cfg); +extern uint16_t wRadioGetTxSeqNumberCurrent(FRAME_CFG *frm_cfg); +extern void vRadioSetTxFCS2(FRAME_CFG *frm_cfg); +extern uint8_t bRadioGetRxFCS2(FRAME_CFG *frm_cfg); +extern void vRadioSetPayloadLength(FRAME_CFG *frm_cfg); +extern uint16_t vRadioGetPayloadLength(FRAME_CFG *frm_cfg); + + +extern void vRadioCfgPreamble(PREAMBLE_CFG *prm_ptr); +extern void vRadioCfgSyncWord(SYNC_CFG *sync_ptr); +extern void vRadioCfgNodeAddr(ADDR_CFG *node_addr_ptr); +extern void vRadioCfgCrc(CRC_CFG *crc_ptr); +extern void vRadioCfgCodeFormat(CODING_FORMAT_CFG *code_format_ptr); +extern void vRadioCfgFrameFormat(FRAME_CFG *frame_format_ptr); +extern void vRadioCfgWiSunFormat(WI_SUN_CFG *wi_sun_ptr); +extern void vRadioCdrTracingModeCfg(CDR_TRACING_CFG *cdr_ptr); + +extern void vRadioCfgWorkMode(WORK_MODE_CFG *run_mode_ptr); +extern void vRadioReadRunModeCfg(void); +extern uint8_t bRadioGetTxDutyCycleDoneTimes(WORK_MODE_CFG *run_mode_ptr); +extern uint8_t bRadioGetTxResendDoneTimes(WORK_MODE_CFG *run_mode_ptr); +extern uint8_t bRadioGetCMSADoneTimes(WORK_MODE_CFG *run_mode_ptr); + + +extern void vRadioSendWithAck(boolean_t w_ack, FRAME_CFG *frame_format_ptr); +extern void vRadioEnableTxAck(boolean_t en_flg, WORK_MODE_CFG *run_mode_ptr); +extern void vRadioEnableRxAck(boolean_t en_flg, WORK_MODE_CFG *run_mode_ptr); +extern uint8_t bRadioGetFreqChanl(void); +extern uint8_t bRadioGetHopDoneTimes(void); +extern void vRadioCsmaEnable(boolean_t on_off, WORK_MODE_CFG *run_mode_ptr); +extern void vRadioSetRssiAbsThValue(int8_t rssi); +extern void vRadioSetPjdDetWin(uint8_t pjd_win); + + + +#endif + + diff --git a/MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/radio_phy.c b/MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/radio_phy.c new file mode 100755 index 0000000..9fbbcf6 --- /dev/null +++ b/MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/radio_phy.c @@ -0,0 +1,645 @@ +#include "radio_phy.h" + +/****************************** +**Name: vRadioSetInterruptSel +**Func: Radio config INT1 & INT2 pin seleciton +**Input: int1_sel, int2_sel, +** +** CMT2310A_INT_MIX (0<<0) // all interrupt mixed together +** CMT2310A_INT_ANT_LOCK (1<<0) // antenna locked +** CMT2310A_INT_RSSI_PJD_VALID (2<<0) // rssi and/or pjd valid +** CMT2310A_INT_PREAM_PASS (3<<0) // preamble detected +** CMT2310A_INT_SYNC_PASS (4<<0) // sync word detected +** CMT2310A_INT_ADDR_PASS (5<<0) // node address detected +** CMT2310A_INT_CRC_PASS (6<<0) // crc ok detected +** CMT2310A_INT_PKT_OK (7<<0) // packet received detected +** CMT2310A_INT_PKT_DONE (8<<0) // packet received detected, even wrong packet or collision +** CMT2310A_INT_SLEEP_TMO (9<<0) // sleep timer time-out +** CMT2310A_INT_RX_TMO (10<<0) // rx timer time-out +** CMT2310A_INT_RX_FIFO_NMTY (11<<0) // rx fifo non-empty +** CMT2310A_INT_RX_FIFO_TH (12<<0) // rx fifo threshold +** CMT2310A_INT_RX_FIFO_FULL (13<<0) // rx fifo full +** CMT2310A_INT_RX_FIFO_WBYTE (14<<0) // rx fifo write byte trigger +** CMT2310A_INT_RX_FIFO_OVF (15<<0) // rx fifo overflow +** CMT2310A_INT_TX_DONE (16<<0) // tx done +** CMT2310A_INT_TX_FIFO_NMTY (17<<0) // tx fifo non-empty +** CMT2310A_INT_TX_FIFO_TH (18<<0) // tx fifo threshold +** CMT2310A_INT_TX_FIFO_FULL (19<<0) // tx fifo full +** CMT2310A_INT_STATE_IS_READY (20<<0) // state is ready +** CMT2310A_INT_STATE_IS_FS (21<<0) // state is FS +** CMT2310A_INT_STATE_IS_RX (22<<0) // state is rx +** CMT2310A_INT_STATE_IS_TX (23<<0) // state is tx +** CMT2310A_INT_LBD_STATUS (24<<0) // LBD status +** CMT2310A_INT_API_CMD_FAILED (25<<0) // API Command failed +** CMT2310A_INT_API_DONE (26<<0) // API execute finish +** CMT2310A_INT_TX_DC_DONE (27<<0) // ?? +** CMT2310A_INT_ACK_RECV_FAILED (28<<0) // ack recieve failed +** CMT2310A_INT_TX_RESEND_DONE (29<<0) // tx re-send done +** CMT2310A_INT_NACK_RECV (30<<0) // non-ack received +** CMT2310A_INT_SEQ_MATCH (31<<0) // sequence number match +** CMT2310A_INT_CSMA_DONE (32<<0) // CSMA done +** CMT2310A_INT_CCA_STATUS (33<<0) // CCA status match +** +*Output: None +********************************/ +void vRadioSetInt1Sel( uint8_t int1_sel ) +{ + bRadioSetReg( CMT2310A_INT1_SEL_REG, int1_sel, CMT2310A_INT1_SEL_MASK ); +} + +void vRadioSetInt2Sel( uint8_t int2_sel ) +{ + bRadioSetReg( CMT2310A_INT2_SEL_REG, int2_sel, CMT2310A_INT2_SEL_MASK ); +} + +/****************************** +**Name: vRadioSetInterruptPolar +**Func: Radio config INT pin out polar mode +**Input: int1_polar, FALSE: ative-high, normal-low +* TRUE: ative-low, normal-high +* int2_polar, FALSE: ative-high, normal-low +* TRUE: ative-low, normal-high +* int3_polar, FALSE: ative-high, normal-low +* TRUE: ative-low, normal-high +*Output: None +********************************/ +void vRadioSetInt1Polar( boolean_t int1_polar ) +{ + if( int1_polar ) + { + bRadioSetReg( CMT2310A_CTL_REG_17, CMT2310A_INT1_POLAR, CMT2310A_INT1_POLAR ); + } + else + { + bRadioSetReg( CMT2310A_CTL_REG_17, 0, CMT2310A_INT1_POLAR ); + } +} + +void vRadioSetInt2Polar( boolean_t int2_polar ) +{ + if( int2_polar ) + { + bRadioSetReg( CMT2310A_CTL_REG_17, CMT2310A_INT2_POLAR, CMT2310A_INT2_POLAR ); + } + else + { + bRadioSetReg( CMT2310A_CTL_REG_17, 0, CMT2310A_INT2_POLAR ); + } +} + +void vRadioSetInt3Polar( boolean_t int3_polar ) +{ + if( int3_polar ) + { + bRadioSetReg( CMT2310A_CTL_REG_19, CMT2310A_INT3_POLAR, CMT2310A_INT3_POLAR ); + } + else + { + bRadioSetReg( CMT2310A_CTL_REG_19, 0, CMT2310A_INT3_POLAR ); + } +} + +//###################################################################### +// RSSI +//###################################################################### + +/****************************** +**Name: vRadioRssiUpdateSel +**Func: Radio rssi update select +**Input: CMT2310A_RSSI_UPDATE_ALWAYS ---- always +** CMT2310A_RSSI_UPDATE_PREAM_OK ---- when preamble ok +** CMT2310A_RSSI_UPDATE_SYNC_OK ---- when sync ok +** CMT2310A_RSSI_UPDATE_PKT_DONE ---- when pkt done +*Output: None +********************************/ +void vRadioRssiUpdateSel( uint8_t sel ) +{ + vRadioRegPageSel( 1 ); //CMT2310A_RX_RSSI_REG_00 is in page1 + bRadioSetReg( CMT2310A_RX_RSSI_REG_00, sel, CMT2310A_RSSI_UPDATE_SEL_MASK ); + vRadioRegPageSel( 0 ); +} + + +/****************************** +**Name: bRadioGetRssi +**Func: Radio get rssi value +**Input: None +*Output: rssi with sign +********************************/ +uint8_t bRadioGetRssi( void ) +{ + return( bRadioReadReg( CMT2310A_CTL_REG_34 ) ); +} + +/****************************** +**Name: vRadioRssiConfig +**Func: Radio config Rssi +**Input: None +*Output: None +********************************/ +void vRadioRssiConfig( RSSI_CFG rssi_cfg ) +{ + vRadioRegPageSel( 1 ); + bRadioSetReg( CMT2310A_RX_RSSI_REG_00, rssi_cfg.FRAME_CFG1_u.RSSI_CFG_REG, ( CMT2310A_COLL_STEP_SEL_MASK | CMT2310A_RSSI_UPDATE_SEL_MASK | CMT2310A_COLL_DET_EN ) ); + bRadioWriteReg( CMT2310A_RSSI_ABS_TH_REG, rssi_cfg.RSSI_ABS_TH ); + vRadioRegPageSel( 0 ); +} + +/****************************** +**Name: vRadioRssiCalOffset +**Func: Radio config Rssi calibrate offset +**Input: None +*Output: None +********************************/ +void vRadioRssiCalOffset( uint8_t cal_offset ) +{ + vRadioRegPageSel( 0 ); + bRadioWriteReg( CMT2310A_RSSI_CAL_OFFSET_REG, cal_offset ); +} + + + +//###################################################################### +// Misc +//###################################################################### +/****************************** +**Name: bRadioGetLbdValue +**Func: Radio get LBD value +**Input: None +*Output: LBD value +********************************/ +uint8_t bRadioGetLbdValue( void ) +{ + return( bRadioReadReg( CMT2310A_LBD_REG ) ); +} + +/****************************** +**Name: vRadioSetLbdTH +**Func: Radio get LBD threshold value +**Input: LBD threshold value +*Output: None +********************************/ +void vRadioSetLbdTH( uint8_t lbd_th ) +{ + bRadioWriteReg( CMT2310A_LBD_TH_REG, lbd_th ); +} + +/****************************** +**Name: bRadioGetTemperature +**Func: Radio get Temperature value +**Input: None +*Output: +********************************/ +uint8_t bRadioGetTemperature( void ) +{ + return( bRadioReadReg( CMT2310A_TEMP_REG ) ); +} + +/****************************** +**Name: bRadioApiCommand +**Func: Radio get Temperature value +**Input: api_cmd, API command code +*Output: +* note: only support 0x01 command code +********************************/ +boolean_t bRadioApiCommand( uint8_t api_cmd ) +{ + uint16_t i; + bRadioWriteReg( CMT2310A_API_CMD_REG, api_cmd ); + api_cmd |= CMT2310A_API_CMD_FLAG; + for( i = 0; i < 500; i++ ) + { + delay1ms( 2 ); + if( bRadioReadReg( CMT2310A_CTL_REG_09 ) == api_cmd ) + { + return( TRUE ); + } + } + return( FALSE ); +} + +/****************************** +**Name: vRadioCdrModeCfg +**Func: Radio set CDR mode +**Input: enum CDR_MODE +*Output: +********************************/ +void vRadioCdrModeCfg( enum CDR_MODE cdr_mode ) +{ + vRadioRegPageSel( 1 ); + bRadioSetReg( CMT2310A_RX_CDR_REG_00, cdr_mode, 0x03 ); + vRadioRegPageSel( 0 ); +} + +/****************************** +**Name: vRadioTxRampCfg +**Func: Radio set tx ramp +**Input: +** tx_ramp_en: TRUE = enable; FALSE = disable +** tx_ramp_step: ramp value, about 1.9us/step +*Output: +********************************/ +void vRadioTxRampCfg( boolean_t tx_ramp_en, uint16_t tx_ramp_step ) +{ + vRadioRegPageSel( 1 ); + if( tx_ramp_en ) + { + bRadioSetReg( CMT2310A_TX_MODE_REG_00, ( 1 << 2 ), ( 1 << 2 ) ); + bRadioWriteReg( CMT2310A_TX_PWR_REG_03, ( uint8_t )tx_ramp_step ); + bRadioSetReg( CMT2310A_TX_PWR_REG_05, ( uint8_t )( ( tx_ramp_step >> 4 ) & 0xF0 ), 0xF0 ); + } + else + { + bRadioSetReg( CMT2310A_TX_MODE_REG_00, ( 0 << 2 ), ( 1 << 2 ) ); + } + vRadioRegPageSel( 0 ); +} + +/****************************** +**Name: vRadioTxGaussianCfg +**Func: Radio set tx with Gaussian +**Input: +** tx_gaus_en: TRUE = enable; FALSE = disable +** tx_gaus_bt: 0=0.3, 1=0.5, 2=0.8, 3=1.0 +*Output: +********************************/ +void vRadioTxGaussianCfg( boolean_t tx_gaus_en, uint8_t tx_gaus_bt ) +{ + uint8_t tmp = 0; + tmp = ( tx_gaus_bt & 0x03 ); + tmp <<= 5; + if( tx_gaus_en ) + { + tmp |= 0x10; + } + vRadioRegPageSel( 1 ); + bRadioSetReg( CMT2310A_TX_MODE_REG_00, tmp, 0x70 ); + vRadioRegPageSel( 0 ); +} + +/****************************** +**Name: vRadioAfcCfg +**Func: Radio set afc +**Input: +** afc_en: TRUE = enable; FALSE = disable +*Output: +********************************/ +void vRadioAfcCfg( boolean_t afc_en ) +{ + vRadioRegPageSel( 1 ); + if( afc_en ) + { + bRadioSetReg( CMT2310A_RX_AFC_REG_00, 0x01, 0x01 ); + } + else + { + bRadioSetReg( CMT2310A_RX_AFC_REG_00, 0x00, 0x01 ); + } + vRadioRegPageSel( 0 ); +} + + +//###################################################################### +// Work State +//###################################################################### +/****************************** +**Name: bRadioGetState +**Func: Radio state +**Input: None +*Output: Radio State +* CMT2310A_STATE_IS_IDLE | CMT2310A_STATE_IS_SLEEP | CMT2310A_STATE_IS_READY | CMT2310A_STATE_IS_RFS | CMT2310A_STATE_IS_TFS | CMT2310A_STATE_IS_RX | CMT2310A_STATE_IS_TX +* note: page0 +********************************/ +uint8_t bRadioGetState( void ) +{ + return( bRadioReadReg( CMT2310A_CHIP_MODE_STA_REG ) ); +} + +uint8_t bRadioSwitchWaiting( uint8_t targ_state ) +{ + uint8_t i = 0; + do + { + delay10us( 2 ); //约26us，加上SPI访问约8us，合计33us查询一次 + if( bRadioGetState() == targ_state ) + { + break; + } + i++; + } + while( i < 60 ); + return( i ); +} + +uint8_t bRadioGoSleep( void ) +{ + bRadioWriteReg( CMT2310A_CTL_REG_01, CMT2310A_GO_SLEEP ); + return( bRadioSwitchWaiting( CMT2310A_STATE_IS_SLEEP ) ); +} + +uint8_t bRadioGoStandby( void ) +{ + bRadioWriteReg( CMT2310A_CTL_REG_01, CMT2310A_GO_READY ); + delay10us( 3 ); + bRadioWriteReg( CMT2310A_CTL_REG_01, CMT2310A_GO_READY ); + return( bRadioSwitchWaiting( CMT2310A_STATE_IS_READY ) ); +} + +uint8_t bRadioGoTx( void ) +{ + bRadioWriteReg( CMT2310A_CTL_REG_01, CMT2310A_GO_TX ); + return( bRadioSwitchWaiting( CMT2310A_STATE_IS_TX ) ); +} + +uint8_t bRadioGoRx( void ) +{ + bRadioWriteReg( CMT2310A_CTL_REG_01, CMT2310A_GO_RX ); + return( bRadioSwitchWaiting( CMT2310A_STATE_IS_RX ) ); +} + +uint8_t bRadioGoTxFS( void ) +{ + bRadioWriteReg( CMT2310A_CTL_REG_01, CMT2310A_GO_TFS ); + return( bRadioSwitchWaiting( CMT2310A_STATE_IS_TFS ) ); +} + +uint8_t bRadioGoRxFS( void ) +{ + bRadioWriteReg( CMT2310A_CTL_REG_01, CMT2310A_GO_RFS ); + return( bRadioSwitchWaiting( CMT2310A_STATE_IS_RFS ) ); +} + +//###################################################################### +// FIFO Control +//###################################################################### +/****************************** +**Name: vRadioSetFifoTH +**Func: Radio set fifo threshold value +**Input: fifo_th +*Output: None +********************************/ +void vRadioSetFifoTH( uint16_t fifo_th ) +{ + if( fifo_th >= 256 ) + { + bRadioSetReg( CMT2310A_CTL_REG_19, CMT2310A_FIFO_TH_BIT8, CMT2310A_FIFO_TH_BIT8 ); + } + else + { + bRadioSetReg( CMT2310A_CTL_REG_19, 0, CMT2310A_FIFO_TH_BIT8 ); + } + bRadioWriteReg( CMT2310A_CTL_REG_20, ( uint8_t )fifo_th ); +} + +/****************************** +**Name: vRadioFifoRetent +**Func: Radio set fifo retent +**Input: cfg_en, FALSE: disable fifo retention +* TRUE: enable fifo retention +*Output: None +* note: fifo retention function active in sleep +********************************/ +void vRadioFifoRetent( boolean_t cfg_en ) +{ + if( cfg_en ) + { + bRadioSetReg( CMT2310A_CTL_REG_19, 0, CMT2310A_PD_FIFO ); + } + else + { + bRadioSetReg( CMT2310A_CTL_REG_19, CMT2310A_PD_FIFO, CMT2310A_PD_FIFO ); + } +} + +/****************************** +**Name: vRadioFifoAutoClearBeforeRx +**Func: Radio set fifo auto clear when entry to Rx +**Input: cfg_en, FALSE: disable fifo auto clear +* TRUE: enable fifo auto clear +*Output: None +********************************/ +void vRadioFifoAutoClearGoRx( boolean_t cfg_en ) +{ + if( cfg_en ) + { + bRadioSetReg( CMT2310A_CTL_REG_19, CMT2310A_FIFO_AUTO_CLR_RX_EN, CMT2310A_FIFO_AUTO_CLR_RX_EN ); + } + else + { + bRadioSetReg( CMT2310A_CTL_REG_19, 0, CMT2310A_FIFO_AUTO_CLR_RX_EN ); + } +} + +/****************************** +**Name: vRadioFifoAutoRestoreWhenTxDone +**Func: Radio set fifo auto re-store when after Tx +**Input: cfg_en, FALSE: disable fifo auto re-store +* TRUE: enable fifo auto re-store +*Output: None +* none: if need repeat send packet, this function should be enable +********************************/ +void vRadioFifoAutoRestoreWhenTxDone( boolean_t cfg_en ) +{ + if( cfg_en ) + { + bRadioSetReg( CMT2310A_CTL_REG_19, CMT2310A_FIFO_AUTO_RES_TX_EN, CMT2310A_FIFO_AUTO_RES_TX_EN ); + } + else + { + bRadioSetReg( CMT2310A_CTL_REG_19, 0, CMT2310A_FIFO_AUTO_RES_TX_EN ); + } +} + +/****************************** +**Name: vRadioFifoMerge +**Func: Radio set fifo merge together +**Input: cfg_en, FALSE: disable fifo merge, 128B for Tx, and 128B for Rx +* TRUE: enable fifo merge, 256B for Tx or Rx +*Output: None +********************************/ +void vRadioFifoMerge( boolean_t cfg_en ) +{ + if( cfg_en ) + { + bRadioSetReg( CMT2310A_CTL_REG_19, CMT2310A_FIFO_MERGE_EN, CMT2310A_FIFO_MERGE_EN ); + } + else + { + bRadioSetReg( CMT2310A_CTL_REG_19, 0, CMT2310A_FIFO_MERGE_EN ); + } +} + +/****************************** +**Name: vRadioFifoTRxUsageSel +**Func: Radio set fifo used for Tx or Rx +**Input: cfg_tx, FALSE: used for Rx +* TRUE: used for Tx +*Output: None +* note: when FIFO merge together active +********************************/ +void vRadioFifoTRxUsageSel( boolean_t cfg_tx ) +{ + if( cfg_tx ) + { + bRadioSetReg( CMT2310A_CTL_REG_19, CMT2310A_FIFO_TX_RX_SEL, CMT2310A_FIFO_TX_RX_SEL ); //for rx + } + else + { + bRadioSetReg( CMT2310A_CTL_REG_19, 0, CMT2310A_FIFO_TX_RX_SEL ); //for tx + } +} + + +/****************************** +**Name: vRadioFifoGetStatus +**Func: Radio get fifo status +**Input: fifo_status +*Output: None +********************************/ +void vRadioFifoGetStatus( FIFO_STATUS_FLG* fifo_status ) +{ + ( *fifo_status ).FIFO_FLG_REG = bRadioReadReg( CMT2310A_CTL_REG_28 ); +} + +/****************************** +**Name: vRadioClearTxFifo +**Func: Radio clear tx fifo +**Input: None +*Output: None +********************************/ +void vRadioClearTxFifo( void ) +{ + bRadioSetReg( CMT2310A_CTL_REG_27, CMT2310A_TX_FIFO_CLR, CMT2310A_TX_FIFO_CLR ); +} + +/****************************** +**Name: vRadioClearRxFifo +**Func: Radio clear rx fifo +**Input: None +*Output: None +********************************/ +void vRadioClearRxFifo( void ) +{ + bRadioSetReg( CMT2310A_CTL_REG_27, CMT2310A_RX_FIFO_CLR, CMT2310A_RX_FIFO_CLR ); +} + +/****************************** +**Name: vRadioManualResetTxFifoPointer +**Func: Radio manual store tx fifo, tx fifo pointer reset +* can be resend the same message +**Input: None +*Output: None +********************************/ +void vRadioManualResetTxFifoPointer( void ) +{ + bRadioSetReg( CMT2310A_CTL_REG_27, CMT2310A_TX_FIFO_RESTORE, CMT2310A_TX_FIFO_RESTORE ); +} + +//###################################################################### +// Interrupt Control +//###################################################################### +/****************************** +**Name: vRadioInterruptSoucreCfg +**Func: Radio set interrupt source config +**Input: int_src_ctrl +*Output: None +********************************/ +void vRadioInterruptSoucreCfg( INT_SRC_CFG* int_src_ctrl ) +{ + bRadioWriteReg( CMT2310A_CTL_REG_18, ( *int_src_ctrl )._BYTE.INT_CTL1_REG ); + bRadioWriteReg( CMT2310A_CTL_REG_21, ( *int_src_ctrl )._BYTE.INT_CTL2_REG ); + bRadioWriteReg( CMT2310A_CTL_REG_23, ( *int_src_ctrl )._BYTE.INT_CTL3_REG ); + bRadioWriteReg( CMT2310A_CTL_REG_14, ( *int_src_ctrl )._BYTE.INT_CTL4_REG ); +} + +/****************************** +**Name: vRadioInterruptSoucreFlag +**Func: Radio get interrupt source flag +**Input: int_src_flag +*Output: None +********************************/ +void vRadioInterruptSoucreFlag( INT_SRC_FLG* int_src_flag ) +{ + ( *int_src_flag )._BYTE.INT_FLAG1_REG = bRadioReadReg( CMT2310A_CTL_REG_24 ); + ( *int_src_flag )._BYTE.INT_FLAG2_REG = bRadioReadReg( CMT2310A_CTL_REG_26 ); + ( *int_src_flag )._BYTE.INT_FLAG3_REG = bRadioReadReg( CMT2310A_CTL_REG_30 ); + ( *int_src_flag )._BYTE.INT_FLAG4_REG = bRadioReadReg( CMT2310A_CTL_REG_32 ); +} + +/****************************** +**Name: vRadioInterruptSoucreClear +**Func: Radio clear interrupt source +**Input: int_src_clr +*Output: None +********************************/ +void vRadioInterruptSoucreClear( INT_SRC_CLR* int_src_clr ) +{ + bRadioWriteReg( CMT2310A_CTL_REG_24, ( *int_src_clr )._BYTE.INT_CLR1_REG ); + bRadioWriteReg( CMT2310A_CTL_REG_25, ( *int_src_clr )._BYTE.INT_CLR2_REG ); + bRadioWriteReg( CMT2310A_CTL_REG_29, ( *int_src_clr )._BYTE.INT_CLR3_REG ); + bRadioWriteReg( CMT2310A_CTL_REG_31, ( *int_src_clr )._BYTE.INT_CLR4_REG ); +} + + + + +//###################################################################### +// Config +//###################################################################### + +/****************************** +**Name: vRadioConfigPageReg +**Func: Radio config page 0/1 regsisters +* page0, start address from 0x28 +* page1, start address from 0x00 +**Input: page_sel: Page0, Page1 +* reg_ptr: +* reg_len: +*Output: None +* note: Page2 is not support burst mode +********************************/ +void vRadioConfigPageReg( byte page_sel, uint8_t const reg_ptr[], uint8_t reg_len ) +{ + vRadioRegPageSel( page_sel ); + vRadioBurstWriteRegs( ( byte* )reg_ptr, reg_len ); + vRadioRegPageSel( 0 ); +} + +void vRadioReadPageReg( byte page_sel, uint8_t reg_ptr[], uint8_t reg_len ) +{ + vRadioRegPageSel( page_sel ); + vRadioBurstReadRegs( reg_ptr, reg_len ); + vRadioRegPageSel( 0 ); +} + + +boolean_t bRadioIsExist( void ) +{ + uint8_t back, dat; + back = bRadioReadReg( CMT2310A_CTL_REG_12 ); + bRadioWriteReg( CMT2310A_CTL_REG_12, 0xAA ); + dat = bRadioReadReg( CMT2310A_CTL_REG_12 ); + bRadioWriteReg( CMT2310A_CTL_REG_12, back ); + if( 0xAA == dat ) + { + return( TRUE ); + } + else + { + return( FALSE ); + } +} +//0x00231000 +uint32_t lRadioChipVersion( void ) +{ + uint32_t chip_ver = 0; + vRadioRegPageSel( 2 ); + chip_ver = bRadioReadReg( CMT2310A_CHIP_VERSION_00 ); + chip_ver <<= 8; + chip_ver |= bRadioReadReg( CMT2310A_CHIP_VERSION_01 ); + chip_ver <<= 8; + chip_ver |= bRadioReadReg( CMT2310A_CHIP_VERSION_02 ); + vRadioRegPageSel( 0 ); + return( chip_ver ); +} + diff --git a/MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/radio_phy.h b/MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/radio_phy.h new file mode 100755 index 0000000..dd00f76 --- /dev/null +++ b/MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/radio_phy.h @@ -0,0 +1,65 @@ +#ifndef __RADIO_PHY_H + +#define __RADIO_PHY_H +//#include "stm8l15x.h" +#include "gd32w51x.h" +#include "radio_hal.h" +#include "CMT2310A_def.h" +#include "CMT2310A_reg.h" + + +extern void vRadioSetInt1Sel( uint8_t int1_sel ); +extern void vRadioSetInt2Sel( uint8_t int2_sel ); +extern void vRadioSetInt1Polar( boolean_t int1_polar ); +extern void vRadioSetInt2Polar( boolean_t int2_polar ); +extern void vRadioSetInt3Polar( boolean_t int3_polar ); + + +extern void vRadioRssiUpdateSel( uint8_t sel ); +extern uint8_t bRadioGetRssi( void ); +extern void vRadioRssiConfig( RSSI_CFG rssi_cfg ); +extern void vRadioRssiCalOffset( uint8_t cal_offset ); + +extern uint8_t bRadioGetLbdValue( void ); +extern void vRadioSetLbdTH( uint8_t lbd_th ); +extern uint8_t bRadioGetTemperature( void ); +extern boolean_t bRadioApiCommand( uint8_t api_cmd ); +extern void vRadioCdrModeCfg( enum CDR_MODE cdr_mode ); +extern void vRadioTxRampCfg( boolean_t tx_ramp_en, uint16_t tx_ramp_step ); +extern void vRadioTxGaussianCfg( boolean_t tx_gaus_en, uint8_t tx_gaus_bt ); +extern void vRadioAfcCfg( boolean_t afc_en ); + +extern uint8_t bRadioGetState( void ); +extern uint8_t bRadioGoSleep( void ); +extern uint8_t bRadioGoStandby( void ); +extern uint8_t bRadioGoTx( void ); +extern uint8_t bRadioGoRx( void ); +extern uint8_t bRadioGoTxFS( void ); +extern uint8_t bRadioGoRxFS( void ); + + +extern void vRadioSetFifoTH( uint16_t fifo_th ); +extern void vRadioFifoRetent( boolean_t cfg_en ); +extern void vRadioFifoAutoClearGoRx( boolean_t cfg_en ); +extern void vRadioFifoAutoRestoreWhenTxDone( boolean_t cfg_en ); +extern void vRadioFifoMerge( boolean_t cfg_en ); +extern void vRadioFifoTRxUsageSel( boolean_t cfg_tx ); +extern void vRadioFifoGetStatus( FIFO_STATUS_FLG* fifo_status ); +extern void vRadioClearTxFifo( void ); +extern void vRadioClearRxFifo( void ); +extern void vRadioManualResetTxFifoPointer( void ); + +extern void vRadioInterruptSoucreCfg( INT_SRC_CFG* int_src_ctrl ); +extern void vRadioInterruptSoucreFlag( INT_SRC_FLG* int_src_flag ); +extern void vRadioInterruptSoucreClear( INT_SRC_CLR* int_src_clr ); + + +extern void vRadioConfigPageReg( byte page_sel, uint8_t const reg_ptr[], uint8_t reg_len ); +extern void vRadioReadPageReg( byte page_sel, uint8_t reg_ptr[], uint8_t reg_len ); +extern boolean_t bRadioIsExist( void ); +extern uint32_t lRadioChipVersion( void ); + +#endif + + + diff --git a/MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/radio_spi.c b/MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/radio_spi.c new file mode 100755 index 0000000..842f63f --- /dev/null +++ b/MBL/source_ns/drivers/CMT2310/3_Ebyte_WirelessModule_Drivers/E48xMx/radio_spi.c @@ -0,0 +1,108 @@ +#include "radio_spi.h" + +/****************************** +**Name: vSpiMasterInit +**Func: SPI Master +**Input: None +*Output: None +********************************/ +void vSpiMasterInit( void ) +{ + /* 已经初始化了SPI 这里跳过*/ +} + + +uint8_t bSpiWriteByte( uint8_t spi_adr, uint8_t spi_dat ) +{ + uint8_t ret; + + spi_adr &= 0x7F; + + /* SPI 片选 CS */ +#if EBYTE_PORT_SPI_CS_SOFTWARE + Ebyte_Port_SpiCsIoControl( 0 ); +#endif + + Ebyte_Port_SpiTransmitAndReceivce(spi_adr); + + ret = Ebyte_Port_SpiTransmitAndReceivce(spi_dat); + + /* SPI 片选 CS */ +#if EBYTE_PORT_SPI_CS_SOFTWARE + Ebyte_Port_SpiCsIoControl( 1 ); +#endif + + return ret; +} + +uint8_t bSpiReadByte( uint8_t spi_adr ) +{ + uint8_t ret; + + spi_adr |= 0x80; + + /* SPI 片选 CS */ +#if EBYTE_PORT_SPI_CS_SOFTWARE + Ebyte_Port_SpiCsIoControl( 0 ); +#endif + + Ebyte_Port_SpiTransmitAndReceivce(spi_adr); + + ret = Ebyte_Port_SpiTransmitAndReceivce(0x00); + + /* SPI 片选 CS */ +#if EBYTE_PORT_SPI_CS_SOFTWARE + Ebyte_Port_SpiCsIoControl( 1 ); +#endif + + return ret; +} + +void vSpiBurstWrite( uint8_t spi_adr, uint8_t spi_dat[], uint8_t spi_length ) +{ + uint8_t i; + + spi_adr &= 0x7F; + + /* SPI 片选 CS */ +#if EBYTE_PORT_SPI_CS_SOFTWARE + Ebyte_Port_SpiCsIoControl( 0 ); +#endif + + Ebyte_Port_SpiTransmitAndReceivce(spi_adr); + + for(i=0; i