350 lines
12 KiB
C
350 lines
12 KiB
C
/*!
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\file mbl.c
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\brief Main boot loader for GD32W51x WiFi SDK
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\version 2021-10-30, V1.0.0, firmware for GD32W51x
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*/
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/*
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Copyright (c) 2021, GigaDevice Semiconductor Inc.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors
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may be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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*/
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#include "mbl_includes.h"
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#include "rom_export_mbedtls.h"
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#include "mbl_nsc_api.h"
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#include "mbl_dummy.c"
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#if defined (__ICCARM__)
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extern uint32_t MBL_CMSE_VENEER$$Base;
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extern uint32_t MBL_CMSE_VENEER$$Limit;
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extern uint32_t MBL_BUF$$Base;
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extern uint32_t HEAP$$Limit;
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#else
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REGION_DECLARE(Image$$, MBL_CMSE_VENEER, $$Base);
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REGION_DECLARE(Image$$, MBL_CMSE_VENEER, $$Limit);
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REGION_DECLARE(Image$$, MBL_BUF, $$ZI$$Base);
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#endif
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typedef void (*nsfptr_t) (void) __attribute__((cmse_nonsecure_call));
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struct rom_api_s_t *p_rom_api_s = (struct rom_api_s_t *)ROM_API_ARRAY_BASE;
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static uint8_t alloc_buf[MBL_BUF_SIZE];
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/*!
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\brief initialize usart
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\param[in] none
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\param[out] none
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\retval none
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*/
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static void log_uart_init(void)
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{
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rcu_periph_clock_enable(RCU_USART1);
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rcu_periph_clock_enable(RCU_GPIOB);
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rcu_periph_clock_enable(RCU_GPIOA);
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gpio_af_set(GPIOB, GPIO_AF_7, GPIO_PIN_15);
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gpio_af_set(GPIOA, GPIO_AF_3, GPIO_PIN_8);
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gpio_mode_set(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_15);
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gpio_output_options_set(GPIOB, GPIO_OTYPE_PP, GPIO_OSPEED_25MHZ, GPIO_PIN_15);
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gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_8);
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gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_25MHZ, GPIO_PIN_8);
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usart_deinit(USART1);
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usart_baudrate_set(USART1, 115200U);
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usart_receive_config(USART1, USART_RECEIVE_ENABLE);
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usart_transmit_config(USART1, USART_TRANSMIT_ENABLE);
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usart_enable(USART1);
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usart_interrupt_enable(USART1, USART_INT_RBNE);
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}
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/*!
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\brief wait usart transmit complete
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\param[in] none
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\param[out] none
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\retval none
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*/
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void log_uart_idle_wait(void)
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{
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while (RESET == usart_flag_get(USART1, USART_FLAG_TC));
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}
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/*!
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\brief deinitialize mbedtls
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\param[in] none
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\param[out] none
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\retval none
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*/
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static void mbedtls_deinit(void)
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{
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mbedtls_platform_set_calloc_free(NULL, NULL);
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mbedtls_platform_set_snprintf(NULL);
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mbedtls_platform_set_printf(NULL);
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}
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#if defined (__ICCARM__)
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/*!
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\brief clear ram data
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\param[in] none
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\param[out] none
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\retval none
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*/
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__attribute__((naked))
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void ram_data_clear(void)
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{
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__ASM volatile(
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"mov r0, #0 \n"
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"ldr r1, =MBL_BUF$$Base \n"
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"ldr r2, =HEAP$$Limit \n"
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"subs r2, r2, r1 \n"
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"Loop: \n"
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"subs r2, #4 \n"
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"itt ge \n"
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"strge r0, [r1, r2] \n"
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"bge Loop \n"
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"bx lr \n"
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: : : "r0" , "r1" , "r2" , "memory"
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);
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}
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#else
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/*!
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\brief clear ram data
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\param[in] none
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\param[out] none
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\retval none
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*/
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__attribute__((naked))
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void ram_data_clear(void)
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{
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__ASM volatile(
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"mov r0, #0 \n"
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"ldr r1, =Image$$MBL_BUF$$ZI$$Base \n"
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"ldr r2, =Image$$ARM_LIB_STACKHEAP$$ZI$$Limit \n"
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"subs r2, r2, r1 \n"
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"Loop: \n"
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"subs r2, #4 \n"
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"itt ge \n"
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"strge r0, [r1, r2] \n"
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"bge Loop \n"
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"bx lr \n"
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: : : "r0" , "r1" , "r2" , "memory"
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);
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}
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#endif
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// ".syntax unified \n"
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/*!
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\brief jump to PSA root
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\param[in] reset_handler_addr: reset handler adress
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\param[out] none
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\retval none
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*/
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__attribute__((naked))
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void jump_to_prot_asm(uint32_t reset_handler_addr)
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{
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__ASM volatile(
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"mov r7, r0 \n"
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"bl ram_data_clear \n" /* Clear ram data before jump to Main Image including the data rom uesed */
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"movs r0, #0 \n" /* Clear registers: R0-R12, */
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"mov r1, r0 \n" /* except R7 */
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"mov r2, r0 \n"
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"mov r3, r0 \n"
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"mov r4, r0 \n"
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"mov r5, r0 \n"
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"mov r6, r0 \n"
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"mov r8, r0 \n"
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"mov r9, r0 \n"
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"mov r10, r0 \n"
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"mov r11, r0 \n"
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"mov r12, r0 \n"
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"mov lr, r0 \n"
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"bx r7 \n" /* Jump to Reset_handler */
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);
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}
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/*!
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\brief jump to main image
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\param[in] to_nsec: decide jujmp to non-secure or secure
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\param[in] msp: main stack pointer
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\param[in] reset: reset handler
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\param[out] none
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\retval none
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*/
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static void jump_to_main_image(IN uint32_t to_nsec, IN uint32_t msp, IN uint32_t reset)
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{
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static uint32_t prot_reset;
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static nsfptr_t nspe_reset;
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if (to_nsec) {
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nspe_reset = (nsfptr_t)cmse_nsfptr_create(reset);
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#if defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8M_BASE__)
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__TZ_set_MSPLIM_NS(0);
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#endif
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__TZ_set_MSP_NS(msp);
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__DSB();
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__ISB();
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nspe_reset();
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} else {
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prot_reset = reset;
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#if defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8M_BASE__)
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/* Restore the Main Stack Pointer Limit register's reset value
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* before passing execution to runtime firmware to make the
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* bootloader transparent to it.
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*/
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__set_MSPLIM(0);
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#endif
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__set_MSP(msp);
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__DSB();
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__ISB();
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jump_to_prot_asm(prot_reset);
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}
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}
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/*!
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\brief main function
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\param[in] none
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\param[out] none
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\retval none
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*/
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int main(void)
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{
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struct ibl_state_t ibl_state;
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uint32_t boot_idx = 0, image_addr = 0;
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uint8_t boot_seed[BOOT_SEED_SIZE];
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uint8_t impl_id[IMPLEMENTATION_ID_MAX_SIZE];
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uint8_t inst_id[INSTANCE_ID_MAX_SIZE];
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uint32_t arm_vector[2];
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uint32_t bonly_nspe = 0;
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uint32_t nsc_start, nsc_end;
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int ret;
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#if defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8M_BASE__)
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#if defined (__ICCARM__)
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uint32_t msp_stack_bottom = (uint32_t)&MBL_BUF$$Base + 0x1000;
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#else
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uint32_t msp_stack_bottom = (uint32_t)®ION_NAME(Image$$, MBL_BUF, $$ZI$$Base) + 0x1000;
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#endif
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__set_MSPLIM(msp_stack_bottom);
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#endif
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/* Set all flash pages as secure */
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mbl_flash_wm_init();
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/* Reinitialize uart since system clock source changed from IRC16M to HXTAL40M */
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log_uart_init();
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/* Read Initial boot state from shared SRAM */
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memcpy(&ibl_state, (void *)IBL_SHARED_DATA_START, sizeof(struct ibl_state_t));
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/* Re-initialize shared SRAM */
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mbl_status_init();
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mbl_status_sw_info_add(&ibl_state.mbl_info);
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mbedtls_memory_buffer_alloc_init(alloc_buf, sizeof(alloc_buf));
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/* Find the correct image to boot, Image 0 or Image 1 */
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ret = boot_image_find(&boot_idx, &image_addr);
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if (ret < 0) {
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rom_trace_ex(ROM_ERR, "No image to boot (ret = %d).\r\n", ret);
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goto BootFailed;
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} else {
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rom_trace_ex(ROM_ALWAYS, "MBL: Boot from Image %d.\r\n", boot_idx);
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}
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/* If boot from Image 1, config offset mapping */
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if (boot_idx == IMAGE_1) {
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flash_offset_mapping();
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}
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/* Verify Image */
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ret = image_x_validate(image_addr, ibl_state.mbl_pk, ibl_state.ibl_opt, &bonly_nspe);
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if (ret < 0) {
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rom_trace_ex(ROM_ERR, "Validate Image %d failed (ret = %d).\r\n", boot_idx, ret);
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rom_sys_set_img_flag(boot_idx, IMG_FLAG_VERIFY_MASK, IMG_FLAG_VERIFY_FAIL);
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goto BootFailed;
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} else {
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rom_trace_ex(ROM_ALWAYS, "MBL: Validate Image %d OK.\r\n", boot_idx);
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}
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/* Update Image status and Running Image flag */
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rom_sys_set_img_flag(boot_idx, IMG_FLAG_VERIFY_MASK, IMG_FLAG_VERIFY_OK);
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rom_sys_set_running_img(boot_idx);
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/* Generate boot seed, Instance ID, Implementation ID */
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boot_seed_gen(boot_seed);
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memcpy(impl_id, ibl_state.impl_id, sizeof(impl_id));
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instance_id_gen(inst_id);
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/* Save General info to MBL status */
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mbl_status_boot_seed_add(boot_seed);
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mbl_status_impl_id_add(impl_id);
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mbl_status_inst_id_add(inst_id);
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mbl_status_running_img_add((uint8_t *)&boot_idx);
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#if defined (__ICCARM__)
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nsc_start = (uint32_t)&MBL_CMSE_VENEER$$Base;
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nsc_end = (uint32_t)&MBL_CMSE_VENEER$$Limit;
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#else
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nsc_start = (uint32_t)®ION_NAME(Image$$, MBL_CMSE_VENEER, $$Base);
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nsc_end = (uint32_t)®ION_NAME(Image$$, MBL_CMSE_VENEER, $$Limit);
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#endif
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mbl_status_sau_entry_add((uint8_t *)&nsc_start, (uint8_t *)&nsc_end);
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mbl_status_rom_version_add((uint8_t *)&ibl_state.rom_ver);
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/* Clear the pointers of mbedtls platform APIs */
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if (!bonly_nspe)
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mbedtls_deinit();
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/*####### Test #######*/
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//mbl_status_show();
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/* Jump to PROT or AROT or NSPE */
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rom_flash_read((image_addr + sizeof(struct image_header)), arm_vector, 8);
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if (!rom_is_valid_flash_addr(arm_vector[1])) {
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rom_trace_ex(ROM_ERR, "Image vector reset is invalid (%08x).\r\n", arm_vector[1]);
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goto BootFailed;
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}
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rom_trace_ex(ROM_ALWAYS, "MBL: Jump to Main Image.\r\n");
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/* Setup security related settings for NSPE if no PROT or AROT */
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if (bonly_nspe) {
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if (mbl_sec_for_nspe_setup(boot_idx)< 0) {
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rom_trace_ex(ROM_ERR, "Setup security settings for NSPE failed. \r\n");
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goto BootFailed;
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}
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SCB_NS->VTOR = FLASH_BASE_NS + image_addr + sizeof(struct image_header);
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}
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log_uart_idle_wait();
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jump_to_main_image(bonly_nspe, arm_vector[0], arm_vector[1]);
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BootFailed:
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while(1);
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}
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