55 lines
2.6 KiB
Plaintext
55 lines
2.6 KiB
Plaintext
/*!
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\file readme.txt
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\brief description of the DBG demo
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\version 2021-10-30, V1.0.0, firmware for GD32W51x
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*/
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/*
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Copyright (c) 2021, GigaDevice Semiconductor Inc.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors
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may be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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*/
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This demo is based on the GD32W515P-EVAL-V1.0 board, it shows that, when the
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DBG_CTL0_TM1_HOLD bit in DBG control register(DBG_CTL0) is set and the core halted,
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the TIMER0 counter stop counting and the PWM outputs of all channels are stopped as
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well.It's benefit for debugging.
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The TIMER0 counter clock used is 2MHz.
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The Three Duty cycles are computed as the following description:
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The channel 1 duty cycle is set to 25%
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The channel 2 duty cycle is set to 50%
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The channel 3 duty cycle is set to 75%
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Connect the TIMER0 pins to an oscilloscope and monitor the different waveforms:
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- TIMER0_CH1 pin (PA9)
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- TIMER0_CH2 pin (PA10)
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- TIMER0_CH3 pin (PA11)
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For Keil,in debug mode,when the core is stopped,update the register window for TIMER0,
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you will see that the count value will not change. And at the same time,the PWM outputs of
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all the channels of TIMER0 will be stopped.
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