401 lines
13 KiB
C
401 lines
13 KiB
C
/*!
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\file mbl_target_config.c
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\brief MBL target configuration for GD32W51x WiFi SDK
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\version 2021-10-30, V1.0.0, firmware for GD32W51x
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*/
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/*
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Copyright (c) 2021, GigaDevice Semiconductor Inc.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors
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may be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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*/
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#include "mbl_includes.h"
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#include "rom_flash.h"
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#if defined PLATFORM_GDM32
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#if 0
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enum {
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NS_REGION_CODE_1 = 0,
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NS_REGION_CODE_2,
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NS_REGION_DATA,
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NS_REGION_CMSE_1, /* NSC */
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NS_REGION_CMSE_2, /* NSC */
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NS_REGION_PERIPH,
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NS_REGION_USER,
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};
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/*!
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\brief configure sau and idau
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\param[in] none
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\param[out] none
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\retval none
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*/
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static void sau_and_idau_cfg(void)
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{
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SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) |
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((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk));
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FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) |
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((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos) & FPU_FPCCR_TS_Msk) |
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((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) |
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((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos) & FPU_FPCCR_CLRONRET_Msk);
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/* Disable SAU */
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TZ_SAU_Disable();
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#ifdef CODE_FROM_FLASH
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/* Configures SAU regions to be non-secure */
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/* CODE */
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SAU->RNR = NS_REGION_CODE_1;
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SAU->RBAR = ((FLASH_BASE_NS + FLASH_AREA_1_OFFSET)
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& SAU_RBAR_BADDR_Msk);
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SAU->RLAR = ((FLASH_BASE_NS + FLASH_AREA_1_OFFSET + FLASH_AREA_1_SIZE - 1)
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& SAU_RLAR_LADDR_Msk)
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| SAU_RLAR_ENABLE_Msk;
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SAU->RNR = NS_REGION_CODE_2;
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SAU->RBAR = ((FLASH_BASE_NS + FLASH_AREA_3_OFFSET)
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& SAU_RBAR_BADDR_Msk);
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SAU->RLAR = ((FLASH_BASE_NS + FLASH_AREA_3_OFFSET + FLASH_AREA_3_SIZE - 1)
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& SAU_RLAR_LADDR_Msk)
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| SAU_RLAR_ENABLE_Msk;
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/* DATA */
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SAU->RNR = NS_REGION_DATA;
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SAU->RBAR = ((RAM_BASE_NS + RAM_BANK3_OFFSET)
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& SAU_RBAR_BADDR_Msk);
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SAU->RLAR = ((RAM_BASE_NS + RAM_BANK3_OFFSET + RAM_BANK3_SIZE + RAM_BANK4_SIZE - 1)
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& SAU_RLAR_LADDR_Msk)
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| SAU_RLAR_ENABLE_Msk;
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/* Configures veneers region to be non-secure callable */
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SAU->RNR = NS_REGION_CMSE_1;
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SAU->RBAR = ((FLASH_BASE_S + FLASH_AREA_0_CMSE_OFFSET)
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& SAU_RBAR_BADDR_Msk);
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SAU->RLAR = ((FLASH_BASE_S + FLASH_AREA_0_CMSE_OFFSET + FLASH_AREA_0_CMSE_SIZE - 1)
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& SAU_RLAR_LADDR_Msk)
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| SAU_RLAR_ENABLE_Msk
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| SAU_RLAR_NSC_Msk;
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SAU->RNR = NS_REGION_CMSE_2;
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SAU->RBAR = ((FLASH_BASE_S + FLASH_AREA_2_CMSE_OFFSET)
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& SAU_RBAR_BADDR_Msk);
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SAU->RLAR = ((FLASH_BASE_S + FLASH_AREA_2_CMSE_OFFSET + FLASH_AREA_2_CMSE_SIZE - 1)
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& SAU_RLAR_LADDR_Msk)
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| SAU_RLAR_ENABLE_Msk
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| SAU_RLAR_NSC_Msk;
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#elif defined (CODE_FROM_SRAM)
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/* Configures SAU regions to be non-secure */
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/* CODE */
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SAU->RNR = NS_REGION_CODE_1;
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SAU->RBAR = ((RAM_BASE_NS + RAM_BANK4_OFFSET)
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& SAU_RBAR_BADDR_Msk);
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SAU->RLAR = ((RAM_BASE_NS + RAM_BANK4_OFFSET + RAM_BANK4_SIZE - 1)
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& SAU_RLAR_LADDR_Msk)
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| SAU_RLAR_ENABLE_Msk;
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/* DATA */
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SAU->RNR = NS_REGION_DATA;
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SAU->RBAR = ((RAM_BASE_NS + RAM_BANK2_OFFSET)
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& SAU_RBAR_BADDR_Msk);
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SAU->RLAR = ((RAM_BASE_NS + RAM_BANK2_OFFSET + RAM_BANK2_SIZE - 1)
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& SAU_RLAR_LADDR_Msk)
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| SAU_RLAR_ENABLE_Msk;
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/* Configures veneers region to be non-secure callable */
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SAU->RNR = NS_REGION_CMSE_1;
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SAU->RBAR = ((RAM_BASE_S + RAM_BANK1_CMSE_OFFSET)
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& SAU_RBAR_BADDR_Msk);
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SAU->RLAR = ((RAM_BASE_S + RAM_BANK1_CMSE_OFFSET + RAM_BANK1_CMSE_SIZE - 1)
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& SAU_RLAR_LADDR_Msk)
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| SAU_RLAR_ENABLE_Msk
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| SAU_RLAR_NSC_Msk;
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#endif
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/* Configure the peripherals space */
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SAU->RNR = NS_REGION_PERIPH;
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SAU->RBAR = (PERIPH_BASE_NS & SAU_RBAR_BADDR_Msk);
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SAU->RLAR = ((PERIPH_BASE_NS + 0xFFFFFFF) & SAU_RLAR_LADDR_Msk)
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| SAU_RLAR_ENABLE_Msk;
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/* Force memory writes before continuing */
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__DSB();
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/* Flush and refill pipeline with updated permissions */
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__ISB();
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/* Enable SAU */
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TZ_SAU_Enable();
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/* Lock SAU config */
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//FIXME
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//__HAL_RCC_SYSCFG_CLK_ENABLE();
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//SYSCFG->CSLCKR |= SYSCFG_CSLCKR_LOCKSAU;
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}
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#endif
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/* NVIC interrupt target state configuration */
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/*!
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\brief configure nvic interrupts
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\param[in] none
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\param[out] none
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\retval none
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*/
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void mbl_nvic_its_config(void)
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{
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uint32_t sz;
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int i;
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sz = sizeof(NVIC->ITNS)/sizeof(NVIC->ITNS[0]);
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for (i = 0; i < sz; i++) {
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NVIC->ITNS[i] = 0xFFFFFFFF;
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}
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}
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/*!
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\brief configure gpio attribute
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\param[in] none
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\param[out] none
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\retval none
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*/
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void mbl_gpio_attr_config(void)
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{
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/* RFIO pins */
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gpio_bit_reset_sec_cfg(GPIOA, GPIO_PIN_9);
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gpio_bit_reset_sec_cfg(GPIOA, GPIO_PIN_10);
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gpio_bit_reset_sec_cfg(GPIOA, GPIO_PIN_11);
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gpio_bit_reset_sec_cfg(GPIOA, GPIO_PIN_12);
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/* USART pins */
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gpio_bit_reset_sec_cfg(GPIOA, GPIO_PIN_8);
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gpio_bit_reset_sec_cfg(GPIOB, GPIO_PIN_15);
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}
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/*!
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\brief configure sram block secure access mode
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\param[in] none
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\param[out] none
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\retval none
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*/
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void mbl_sram_mpcbb_config(void)
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{
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#ifndef ROM_SELF_TEST
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static const uint32_t groups[] = {TZBMPC0, TZBMPC1, TZBMPC2, TZBMPC3};
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static const uint32_t sizes[] = {0, 0x10000, 0x20000, 0x40000, 0x70000}; /* Start addresses of 4 SRAMs */
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const uint32_t address = RE_NSPE_DATA_START;
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uint32_t start_block, end_block, array_sz;
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int32_t i;
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array_sz = (sizeof(groups)/sizeof(groups[0]));
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for (i = array_sz - 1; i >= 0; i--) {
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if (address >= sizes[i + 1]) {
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continue;
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}
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start_block = address > sizes[i] ? (address - sizes[i]) >> 8 : 0;
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end_block = (sizes[i + 1] - sizes[i]) >> 8;
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for (uint32_t j = start_block; j < end_block; j++) {
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tzpcu_tzbmpc_block_secure_access_mode_config(groups[i], j, BLOCK_SECURE_ACCESS_MODE_NSEC);
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}
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}
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#else
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int32_t i;
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uint32_t blk_num = (RE_NSPE_DATA_START >> 8);
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for (i = blk_num; i < 768; i++) { /* SRAM4: 192K */
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tzpcu_tzbmpc_block_secure_access_mode_config(TZBMPC3, i, BLOCK_SECURE_ACCESS_MODE_NSEC);
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}
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tzgpc_tzbmpc_secure_illegal_access_disable_config(TZBMPC3, SECURE_ILLEGAL_ACCESS_DISABLE);
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#endif
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}
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/*!
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\brief initialize flash water mark secure pages
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\param[in] none
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\param[out] none
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\retval none
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*/
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void mbl_flash_wm_init(void)
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{
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if (IS_SIP_FLASH()) {
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if (OBSTAT_FMCOB()) {
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/* unlock the flash program erase controller */
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fmc_unlock();
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ob_unlock();
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/* clear pending flags */
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fmc_flag_clear(FMC_FLAG_END | FMC_FLAG_SECERR | FMC_FLAG_WPERR);
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/* Set MBL region as secure */
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ob_secmark_config(0, 0x3FF, SECM_INDEX2);
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/* lock the flash program erase controller */
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ob_lock();
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fmc_lock();
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}
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}
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}
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/*!
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\brief configure flash water secure pages
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\param[in] none
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\param[out] none
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\retval none
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*/
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void mbl_flash_wm_config(uint8_t boot_idx)
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{
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if (IS_SIP_FLASH()) {
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uint32_t ota_spage, ota_epage;
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if (boot_idx == IMAGE_0) {
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ota_spage = (RE_IMG_1_PROT_OFFSET >> 12);
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ota_epage = (RE_IMG_1_END_OFFSET >> 12) - 1;
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} else {
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ota_spage = (RE_IMG_0_PROT_OFFSET >> 12);
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ota_epage = (RE_IMG_1_PROT_OFFSET >> 12) - 1;
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}
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/* unlock the flash program erase controller */
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fmc_unlock();
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ob_unlock();
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/* clear pending flags */
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fmc_flag_clear(FMC_FLAG_END | FMC_FLAG_SECERR | FMC_FLAG_WPERR);
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if (OBSTAT_FMCOB()) {
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/* Set MBL region as secure */
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ob_secmark_config(0, ((RE_IMG_0_NSPE_OFFSET >> 12) - 1), SECM_INDEX2);
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/* Set IMAGE-not-running region as secure */
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ob_secmark_config(ota_spage, ota_epage, SECM_INDEX3);
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} else {
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/* Set MBL region as secure */
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ob_secmark_config(0, ((RE_IMG_0_NSPE_OFFSET >> 12) - 1), SECM_INDEX0);
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/* Set IMAGE-not-running region as secure */
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ob_secmark_config(ota_spage, ota_epage, SECM_INDEX1);
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ob_secmark_config(0x3FF, 0, SECM_INDEX2);
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ob_secmark_config(0x3FF, 0, SECM_INDEX3);
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}
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/* lock the flash program erase controller */
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ob_lock();
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fmc_lock();
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} else {
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tzpcu_non_secure_mark_struct wm;
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wm.memory_type = QSPI_FLASH_MEM;
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wm.region_number = NON_SECURE_MARK_REGION0;
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if (boot_idx == IMAGE_0) {
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wm.start_address = RE_IMG_0_NSPE_OFFSET;
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wm.length = RE_IMG_1_PROT_OFFSET - RE_IMG_0_NSPE_OFFSET;
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} else {
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wm.start_address = RE_IMG_1_NSPE_OFFSET;
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wm.length = RE_IMG_1_END_OFFSET - RE_IMG_1_NSPE_OFFSET;
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}
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tzpcu_tzspc_emnsm_config(&wm);
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}
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}
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/*!
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\brief configure system reset
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\param[in] none
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\param[out] none
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\retval none
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*/
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void mbl_system_reset_config(void)
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{
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uint32_t reg_value;
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//struct sysctrl_t *sysctrl = (struct sysctrl_t *)CMSDK_SYSCTRL_BASE_S;
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reg_value = SCB->AIRCR;
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/* Enable system reset request for CPU 0, to be triggered via
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* NVIC_SystemReset function.
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*/
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//sysctrl->resetmask |= ENABLE_CPU0_SYSTEM_RESET_REQUEST;
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/* Clear SCB_AIRCR_VECTKEY value */
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reg_value &= ~(uint32_t)(SCB_AIRCR_VECTKEY_Msk);
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/* Enable system reset request only to the secure world */
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//reg_value |= (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB_AIRCR_SYSRESETREQS_Msk | SCB_AIRCR_PRIS_Msk);
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reg_value &= ~(uint32_t)(SCB_AIRCR_SYSRESETREQS_Msk);
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reg_value |= (uint32_t)(0x5FAUL << SCB_AIRCR_VECTKEY_Pos);
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SCB->AIRCR = reg_value;
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}
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/*!
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\brief setup secure for non-secure processing environment
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\param[in] boot_idx: boot index
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\param[out] none
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\retval result of setup secure for nspe
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*/
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int mbl_sec_for_nspe_setup(uint8_t boot_idx)
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{
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/* System reset options */
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mbl_system_reset_config();
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//__enable_irq();
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/* GPIO: set gpios used by WIFI to non-secure */
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mbl_gpio_attr_config();
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/* Flash: only first ten pages(40KB) are secure */
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mbl_flash_wm_config(boot_idx);
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/* SRAM: only first ten blocks(0xA00 Bytes) are secure */
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mbl_sram_mpcbb_config();
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/* Target every interrupt to NS; unimplemented interrupts will be WI */
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mbl_nvic_its_config();
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rom_trace_ex(ROM_ALWAYS, "Setup security settings for NSPE OK. \r\n");
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return 0;
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}
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/*!
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\brief mapping flash offset
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\param[in] none
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\param[out] none
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\retval none
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*/
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void flash_offset_mapping(void)
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{
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fmc_unlock();
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ob_unlock();
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fmc_offset_region_config(RE_IMG_0_PROT_OFFSET >> 12, (RE_IMG_1_PROT_OFFSET >> 12) - 1);
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fmc_offset_value_config((RE_IMG_1_PROT_OFFSET - RE_IMG_0_PROT_OFFSET) >> 12);
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ob_lock();
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fmc_lock();
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}
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#else
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int mbl_sec_for_nspe_setup(void)
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{
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}
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/*!
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\brief mapping flash offset
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\param[in] none
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\param[out] none
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\retval none
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*/
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void flash_offset_mapping(void)
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{
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}
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#endif
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