1460 lines
56 KiB
C
1460 lines
56 KiB
C
/*!
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\file gd32w51x_rtc.c
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\brief RTC driver
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\version 2021-10-30, V1.0.0, firmware for GD32W51x
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*/
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/*
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Copyright (c) 2021, GigaDevice Semiconductor Inc.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors
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may be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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*/
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#include "gd32w51x_rtc.h"
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/* RTC timeout value */
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#define RTC_WTWF_TIMEOUT ((uint32_t)0x00004000U) /*!< wakeup timer can be written flag timeout */
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#define RTC_INITM_TIMEOUT ((uint32_t)0x00004000U) /*!< initialization state flag timeout */
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#define RTC_RSYNF_TIMEOUT ((uint32_t)0x00008000U) /*!< register synchronization flag timeout */
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#define RTC_HRFC_TIMEOUT ((uint32_t)0x20000000U) /*!< recalibration pending flag timeout */
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#define RTC_SHIFTCTL_TIMEOUT ((uint32_t)0x00001000U) /*!< shift function operation pending flag timeout */
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#define RTC_ALRMXWF_TIMEOUT ((uint32_t)0x00008000U) /*!< alarm configuration can be written flag timeout */
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/*!
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\brief reset most of the RTC registers
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\param[in] none
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\param[out] none
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\retval ErrStatus: ERROR or SUCCESS
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*/
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ErrStatus rtc_deinit(void)
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{
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/* After Backup domain reset, some of the RTC registers are write-protected: RTC_TIME, RTC_DATE, RTC_PSC,
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RTC_HRFC, RTC_COSC, RTC_SHIFTCTL, the bit INITM in RTC_ICS and the bits CS, S1H, A1H, REFEN in RTC_CTL. */
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ErrStatus error_status = ERROR;
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volatile uint32_t time_index = RTC_WTWF_TIMEOUT;
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uint32_t flag_status = RESET;
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/* RTC_TAMP register is not under write protection */
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RTC_TAMP = RTC_REGISTER_RESET;
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/* rtc alarmx related registers are not under the protection of RTC_WPK, different from former GD32MCU */
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RTC_CTL &= ((uint32_t)~(RTC_CTL_ALRM0EN | RTC_CTL_ALRM1EN));
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/* to write RTC_ALRMxTD and RTC_ALRMxSS register, 1 ALRMxEN bit in RTC_CTL register should be reset as the condition
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2 or in INIT mode */
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RTC_ALRM0TD = RTC_REGISTER_RESET;
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RTC_ALRM1TD = RTC_REGISTER_RESET;
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RTC_ALRM0SS = RTC_REGISTER_RESET;
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RTC_ALRM1SS = RTC_REGISTER_RESET;
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/* 1 only when RTC_CTL_WTEN=0 and RTC_ICS_WTWF=1 can write RTC_CTL[2:0]
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2 or configure the wakeup timer in INIT mode*/
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RTC_CTL &= ((uint32_t)~RTC_CTL_WTEN);
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/* wait until the WTWF flag to be set */
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do{
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flag_status = RTC_ICS & RTC_ICS_WTWF;
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}while((--time_index > 0U) && ((uint32_t)RESET == flag_status));
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if ((uint32_t)RESET == flag_status){
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error_status = ERROR;
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}else{
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RTC_CTL &= ((uint32_t)~RTC_CTL_WTCS);
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RTC_WUT = RTC_WUT_RESET;
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/* disable the write protection */
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RTC_WPK = RTC_UNLOCK_KEY1;
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RTC_WPK = RTC_UNLOCK_KEY2;
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/* enter init mode */
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error_status = rtc_init_mode_enter();
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/* RTC_TIME, RTC_DATE, RTC_PSC registers, plus INITM in RTC_ICS, plus CS control bits in RTC_CTL */
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RTC_CTL = RTC_REGISTER_RESET;
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/* before reset RTC_TIME and RTC_DATE, BPSHAD bit in RTC_CTL should be reset as the condition.
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in order to read calendar from shadow register, not the real registers being reset */
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RTC_TIME = RTC_REGISTER_RESET;
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RTC_DATE = RTC_DATE_RESET;
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RTC_PSC = RTC_PSC_RESET;
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/* write protected and can only be written in initialization state */
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RTC_COSC = RTC_REGISTER_RESET;
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/* reset RTC_ICS register, also exit init mode.
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at the same time, RTC_ICS_SOPF bit is reset, as the condition to reset RTC_SHIFTCTL register later */
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RTC_ICS = RTC_ICS_RESET;
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/* reset RTC_SHIFTCTL and RTC_HRFC register, and the bits S1H, A1H, REFEN in RTC_CTL, these can be done without the init mode */
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RTC_SHIFTCTL = RTC_REGISTER_RESET;
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RTC_HRFC = RTC_REGISTER_RESET;
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error_status = rtc_register_sync_wait();
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/* enable the write protection */
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RTC_WPK = RTC_LOCK_KEY;
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RTC_PPM_CTL = RTC_REGISTER_RESET;
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RTC_SPM_CTL = RTC_SPM_CTL_RESET;
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RTC_STATC = (RTC_STATC_ALRM0FC | RTC_STATC_ALRM1FC | RTC_STATC_WTFC | RTC_STATC_TSFC | RTC_STATC_TSOVRFC | RTC_STATC_TP0FC | RTC_STATC_TP1FC);
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}
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return error_status;
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}
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/*!
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\brief initialize RTC registers
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\param[in] rtc_initpara_struct: pointer to a rtc_parameter_struct structure which contains
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parameters for initialization of the rtc peripheral
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members of the structure and the member values are shown as below:
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year: 0x0 - 0x99(BCD format)
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month: RTC_JAN, RTC_FEB, RTC_MAR, RTC_APR, RTC_MAY, RTC_JUN,
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RTC_JUL, RTC_AUG, RTC_SEP, RTC_OCT, RTC_NOV, RTC_DEC
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date: 0x1 - 0x31(BCD format)
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day_of_week: RTC_MONDAY, RTC_TUESDAY, RTC_WEDNESDAY, RTC_THURSDAY
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RTC_FRIDAY, RTC_SATURDAY, RTC_SUNDAY
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hour: 0x0 - 0x12(BCD format) or 0x0 - 0x23(BCD format) depending on the rtc display_format chose
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minute: 0x0 - 0x59(BCD format)
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second: 0x0 - 0x59(BCD format)
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factor_asyn: 0x0 - 0x7F
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factor_syn: 0x0 - 0x7FFF
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am_pm: RTC_AM, RTC_PM
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display_format: RTC_24HOUR, RTC_12HOUR
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\param[out] none
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\retval ErrStatus: ERROR or SUCCESS
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*/
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ErrStatus rtc_init(rtc_parameter_struct* rtc_initpara_struct)
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{
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ErrStatus error_status = ERROR;
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uint32_t reg_time = 0U, reg_date = 0U;
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reg_date = (DATE_YR(rtc_initpara_struct->year) | \
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DATE_DOW(rtc_initpara_struct->day_of_week) | \
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DATE_MON(rtc_initpara_struct->month) | \
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DATE_DAY(rtc_initpara_struct->date));
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reg_time = (rtc_initpara_struct->am_pm| \
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TIME_HR(rtc_initpara_struct->hour) | \
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TIME_MN(rtc_initpara_struct->minute) | \
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TIME_SC(rtc_initpara_struct->second));
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/* 1st: disable the write protection */
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RTC_WPK = RTC_UNLOCK_KEY1;
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RTC_WPK = RTC_UNLOCK_KEY2;
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/* 2nd: enter init mode */
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error_status = rtc_init_mode_enter();
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if(ERROR != error_status){
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RTC_PSC = (uint32_t)(PSC_FACTOR_A(rtc_initpara_struct->factor_asyn)| \
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PSC_FACTOR_S(rtc_initpara_struct->factor_syn));
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RTC_TIME = (uint32_t)reg_time;
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RTC_DATE = (uint32_t)reg_date;
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RTC_CTL &= (uint32_t)(~RTC_CTL_CS);
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RTC_CTL |= rtc_initpara_struct->display_format;
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/* 3rd: exit init mode */
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rtc_init_mode_exit();
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/* 4th: wait the RSYNF flag to set */
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error_status = rtc_register_sync_wait();
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}
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/* 5th: enable the write protection */
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RTC_WPK = RTC_LOCK_KEY;
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return error_status;
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}
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/*!
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\brief enter RTC init mode
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\param[in] none
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\param[out] none
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\retval ErrStatus: ERROR or SUCCESS
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*/
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ErrStatus rtc_init_mode_enter(void)
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{
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volatile uint32_t time_index = RTC_INITM_TIMEOUT;
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uint32_t flag_status = RESET;
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ErrStatus error_status = ERROR;
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/* check whether it has been in init mode */
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if ((uint32_t)RESET == (RTC_ICS & RTC_ICS_INITF)){
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RTC_ICS |= RTC_ICS_INITM;
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/* wait until the INITF flag to be set */
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do{
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flag_status = RTC_ICS & RTC_ICS_INITF;
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}while((--time_index > 0U) && ((uint32_t)RESET == flag_status));
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if ((uint32_t)RESET != flag_status){
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error_status = SUCCESS;
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}
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}else{
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error_status = SUCCESS;
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}
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return error_status;
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}
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/*!
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\brief exit RTC init mode
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\param[in] none
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\param[out] none
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\retval none
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*/
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void rtc_init_mode_exit(void)
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{
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RTC_ICS &= (uint32_t)(~RTC_ICS_INITM);
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}
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/*!
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\brief wait until RTC_TIME and RTC_DATE registers are synchronized with APB clock, and the shadow
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registers are updated
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\param[in] none
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\param[out] none
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\retval ErrStatus: ERROR or SUCCESS
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*/
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ErrStatus rtc_register_sync_wait(void)
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{
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volatile uint32_t time_index = RTC_RSYNF_TIMEOUT;
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uint32_t flag_status = RESET;
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ErrStatus error_status = ERROR;
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if ((uint32_t)RESET == (RTC_CTL & RTC_CTL_BPSHAD)){
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/* disable the write protection */
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RTC_WPK = RTC_UNLOCK_KEY1;
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RTC_WPK = RTC_UNLOCK_KEY2;
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/* firstly clear RSYNF flag */
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RTC_ICS &= (uint32_t)(~RTC_ICS_RSYNF);
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/* wait until RSYNF flag to be set */
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do{
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flag_status = RTC_ICS & RTC_ICS_RSYNF;
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}while((--time_index > 0U) && ((uint32_t)RESET == flag_status));
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if ((uint32_t)RESET != flag_status){
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error_status = SUCCESS;
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}
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/* enable the write protection */
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RTC_WPK = RTC_LOCK_KEY;
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}else{
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error_status = SUCCESS;
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}
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return error_status;
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}
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/*!
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\brief get current time and date
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\param[in] none
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\param[out] rtc_initpara_struct: pointer to a rtc_parameter_struct structure which contains
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parameters for initialization of the rtc peripheral
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members of the structure and the member values are shown as below:
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year: 0x0 - 0x99(BCD format)
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month: RTC_JAN, RTC_FEB, RTC_MAR, RTC_APR, RTC_MAY, RTC_JUN,
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RTC_JUL, RTC_AUG, RTC_SEP, RTC_OCT, RTC_NOV, RTC_DEC
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date: 0x1 - 0x31(BCD format)
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day_of_week: RTC_MONDAY, RTC_TUESDAY, RTC_WEDNESDAY, RTC_THURSDAY
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RTC_FRIDAY, RTC_SATURDAY, RTC_SUNDAY
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hour: 0x0 - 0x12(BCD format) or 0x0 - 0x23(BCD format) depending on the rtc display_format chose
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minute: 0x0 - 0x59(BCD format)
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second: 0x0 - 0x59(BCD format)
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factor_asyn: 0x0 - 0x7F
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factor_syn: 0x0 - 0x7FFF
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am_pm: RTC_AM, RTC_PM
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display_format: RTC_24HOUR, RTC_12HOUR
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\retval none
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*/
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void rtc_current_time_get(rtc_parameter_struct* rtc_initpara_struct)
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{
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uint32_t temp_tr = 0U, temp_dr = 0U, temp_pscr = 0U, temp_ctlr = 0U;
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temp_tr = (uint32_t)RTC_TIME;
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temp_dr = (uint32_t)RTC_DATE;
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temp_pscr = (uint32_t)RTC_PSC;
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temp_ctlr = (uint32_t)RTC_CTL;
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/* get current time and construct rtc_parameter_struct structure */
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rtc_initpara_struct->year = (uint8_t)GET_DATE_YR(temp_dr);
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rtc_initpara_struct->month = (uint8_t)GET_DATE_MON(temp_dr);
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rtc_initpara_struct->date = (uint8_t)GET_DATE_DAY(temp_dr);
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rtc_initpara_struct->day_of_week = (uint8_t)GET_DATE_DOW(temp_dr);
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rtc_initpara_struct->hour = (uint8_t)GET_TIME_HR(temp_tr);
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rtc_initpara_struct->minute = (uint8_t)GET_TIME_MN(temp_tr);
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rtc_initpara_struct->second = (uint8_t)GET_TIME_SC(temp_tr);
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rtc_initpara_struct->factor_asyn = (uint16_t)GET_PSC_FACTOR_A(temp_pscr);
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rtc_initpara_struct->factor_syn = (uint16_t)GET_PSC_FACTOR_S(temp_pscr);
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rtc_initpara_struct->am_pm = (uint32_t)(temp_tr & RTC_TIME_PM);
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rtc_initpara_struct->display_format = (uint32_t)(temp_ctlr & RTC_CTL_CS);
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}
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/*!
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\brief get current subsecond value
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\param[in] none
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\param[out] none
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\retval current subsecond value
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*/
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uint32_t rtc_subsecond_get(void)
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{
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uint32_t reg = 0U;
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/* if BPSHAD bit is reset, reading RTC_SS will lock RTC_TIME and RTC_DATE automatically */
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reg = (uint32_t)RTC_SS;
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/* read RTC_DATE to unlock the 3 shadow registers */
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(void) (RTC_DATE);
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return reg;
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}
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/*!
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\brief configure RTC alarm
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\param[in] rtc_alarm: RTC_ALARM0 or RTC_ALARM1
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\param[in] rtc_alarm_time: pointer to a rtc_alarm_struct structure which contains
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parameters for RTC alarm configuration
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members of the structure and the member values are shown as below:
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alarm_mask: RTC_ALARM_NONE_MASK, RTC_ALARM_DATE_MASK, RTC_ALARM_HOUR_MASK
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RTC_ALARM_MINUTE_MASK, RTC_ALARM_SECOND_MASK, RTC_ALARM_ALL_MASK
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weekday_or_date: RTC_ALARM_DATE_SELECTED, RTC_ALARM_WEEKDAY_SELECTED
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alarm_day: 1) 0x1 - 0x31(BCD format) if RTC_ALARM_DATE_SELECTED is set
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2) RTC_MONDAY, RTC_TUESDAY, RTC_WEDNESDAY, RTC_THURSDAY, RTC_FRIDAY,
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RTC_SATURDAY, RTC_SUNDAY if RTC_ALARM_WEEKDAY_SELECTED is set
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alarm_hour: 0x0 - 0x12(BCD format) or 0x0 - 0x23(BCD format) depending on the rtc display_format
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alarm_minute: 0x0 - 0x59(BCD format)
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alarm_second: 0x0 - 0x59(BCD format)
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am_pm: RTC_AM, RTC_PM
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\param[out] none
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\retval none
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*/
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void rtc_alarm_config(uint8_t rtc_alarm, rtc_alarm_struct* rtc_alarm_time)
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{
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uint32_t reg_alrmtd = 0U;
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reg_alrmtd =(rtc_alarm_time->alarm_mask | \
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rtc_alarm_time->weekday_or_date | \
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rtc_alarm_time->am_pm | \
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ALRMTD_DAY(rtc_alarm_time->alarm_day) | \
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ALRMTD_HR(rtc_alarm_time->alarm_hour) | \
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ALRMTD_MN(rtc_alarm_time->alarm_minute) | \
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ALRMTD_SC(rtc_alarm_time->alarm_second));
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if(RTC_ALARM0 == rtc_alarm){
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RTC_ALRM0TD = (uint32_t)reg_alrmtd;
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}else{
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RTC_ALRM1TD = (uint32_t)reg_alrmtd;
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}
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}
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/*!
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\brief configure subsecond of RTC alarm
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\param[in] rtc_alarm: RTC_ALARM0 or RTC_ALARM1
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\param[in] mask_subsecond: alarm subsecond mask
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\arg RTC_MSKSSC_0_14: mask alarm subsecond configuration
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\arg RTC_MSKSSC_1_14: mask RTC_ALRMXSS_SSC[14:1], and RTC_ALRMXSS_SSC[0] is to be compared
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\arg RTC_MSKSSC_2_14: mask RTC_ALRMXSS_SSC[14:2], and RTC_ALRMXSS_SSC[1:0] is to be compared
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\arg RTC_MSKSSC_3_14: mask RTC_ALRMXSS_SSC[14:3], and RTC_ALRMXSS_SSC[2:0] is to be compared
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\arg RTC_MSKSSC_4_14: mask RTC_ALRMXSS_SSC[14:4]], and RTC_ALRMXSS_SSC[3:0] is to be compared
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\arg RTC_MSKSSC_5_14: mask RTC_ALRMXSS_SSC[14:5], and RTC_ALRMXSS_SSC[4:0] is to be compared
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\arg RTC_MSKSSC_6_14: mask RTC_ALRMXSS_SSC[14:6], and RTC_ALRMXSS_SSC[5:0] is to be compared
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\arg RTC_MSKSSC_7_14: mask RTC_ALRMXSS_SSC[14:7], and RTC_ALRMXSS_SSC[6:0] is to be compared
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\arg RTC_MSKSSC_8_14: mask RTC_ALRMXSS_SSC[14:8], and RTC_ALRMXSS_SSC[7:0] is to be compared
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\arg RTC_MSKSSC_9_14: mask RTC_ALRMXSS_SSC[14:9], and RTC_ALRMXSS_SSC[8:0] is to be compared
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\arg RTC_MSKSSC_10_14: mask RTC_ALRMXSS_SSC[14:10], and RTC_ALRMXSS_SSC[9:0] is to be compared
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\arg RTC_MSKSSC_11_14: mask RTC_ALRMXSS_SSC[14:11], and RTC_ALRMXSS_SSC[10:0] is to be compared
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\arg RTC_MSKSSC_12_14: mask RTC_ALRMXSS_SSC[14:12], and RTC_ALRMXSS_SSC[11:0] is to be compared
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\arg RTC_MSKSSC_13_14: mask RTC_ALRMXSS_SSC[14:13], and RTC_ALRMXSS_SSC[12:0] is to be compared
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\arg RTC_MSKSSC_14: mask RTC_ALRMXSS_SSC[14], and RTC_ALRMXSS_SSC[13:0] is to be compared
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\arg RTC_MSKSSC_NONE: mask none, and RTC_ALRMXSS_SSC[14:0] is to be compared
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\param[in] subsecond: alarm subsecond value(0x000 - 0x7FFF)
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\param[out] none
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\retval none
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*/
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void rtc_alarm_subsecond_config(uint8_t rtc_alarm, uint32_t mask_subsecond, uint32_t subsecond)
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{
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if(RTC_ALARM0 == rtc_alarm){
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RTC_ALRM0SS = mask_subsecond | subsecond;
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}else{
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RTC_ALRM1SS = mask_subsecond | subsecond;
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}
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}
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/*!
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\brief get RTC alarm
|
|
\param[in] rtc_alarm: RTC_ALARM0 or RTC_ALARM1
|
|
\param[out] rtc_alarm_time: pointer to a rtc_alarm_struct structure which contains
|
|
parameters for RTC alarm configuration
|
|
members of the structure and the member values are shown as below:
|
|
alarm_mask: RTC_ALARM_NONE_MASK, RTC_ALARM_DATE_MASK, RTC_ALARM_HOUR_MASK
|
|
RTC_ALARM_MINUTE_MASK, RTC_ALARM_SECOND_MASK, RTC_ALARM_ALL_MASK
|
|
weekday_or_date: RTC_ALARM_DATE_SELECTED, RTC_ALARM_WEEKDAY_SELECTED
|
|
alarm_day: 1) 0x1 - 0x31(BCD format) if RTC_ALARM_DATE_SELECTED is set
|
|
2) RTC_MONDAY, RTC_TUESDAY, RTC_WEDNESDAY, RTC_THURSDAY, RTC_FRIDAY,
|
|
RTC_SATURDAY, RTC_SUNDAY if RTC_ALARM_WEEKDAY_SELECTED is set
|
|
alarm_hour: 0x0 - 0x12(BCD format) or 0x0 - 0x23(BCD format) depending on the rtc display_format
|
|
alarm_minute: 0x0 - 0x59(BCD format)
|
|
alarm_second: 0x0 - 0x59(BCD format)
|
|
am_pm: RTC_AM, RTC_PM
|
|
\retval none
|
|
*/
|
|
void rtc_alarm_get(uint8_t rtc_alarm, rtc_alarm_struct* rtc_alarm_time)
|
|
{
|
|
uint32_t reg_alrmtd = 0U;
|
|
|
|
/* get the value of RTC_ALRM0TD register */
|
|
if(RTC_ALARM0 == rtc_alarm){
|
|
reg_alrmtd = RTC_ALRM0TD;
|
|
}else{
|
|
reg_alrmtd = RTC_ALRM1TD;
|
|
}
|
|
/* get alarm parameters and construct the rtc_alarm_struct structure */
|
|
rtc_alarm_time->alarm_mask = reg_alrmtd & RTC_ALARM_ALL_MASK;
|
|
rtc_alarm_time->am_pm = (uint32_t)(reg_alrmtd & RTC_ALRMXTD_PM);
|
|
rtc_alarm_time->weekday_or_date = (uint32_t)(reg_alrmtd & RTC_ALRMXTD_DOWS);
|
|
rtc_alarm_time->alarm_day = (uint8_t)GET_ALRMTD_DAY(reg_alrmtd);
|
|
rtc_alarm_time->alarm_hour = (uint8_t)GET_ALRMTD_HR(reg_alrmtd);
|
|
rtc_alarm_time->alarm_minute = (uint8_t)GET_ALRMTD_MN(reg_alrmtd);
|
|
rtc_alarm_time->alarm_second = (uint8_t)GET_ALRMTD_SC(reg_alrmtd);
|
|
}
|
|
|
|
/*!
|
|
\brief get RTC alarm subsecond
|
|
\param[in] rtc_alarm: RTC_ALARM0 or RTC_ALARM1
|
|
\param[out] none
|
|
\retval RTC alarm subsecond value
|
|
*/
|
|
uint32_t rtc_alarm_subsecond_get(uint8_t rtc_alarm)
|
|
{
|
|
if(RTC_ALARM0 == rtc_alarm){
|
|
return ((uint32_t)(RTC_ALRM0SS & RTC_ALRM0SS_SSC));
|
|
}else{
|
|
return ((uint32_t)(RTC_ALRM1SS & RTC_ALRM1SS_SSC));
|
|
}
|
|
}
|
|
|
|
/*!
|
|
\brief enable RTC alarm
|
|
\param[in] rtc_alarm: RTC_ALARM0 or RTC_ALARM1
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void rtc_alarm_enable(uint8_t rtc_alarm)
|
|
{
|
|
if(RTC_ALARM0 == rtc_alarm){
|
|
RTC_CTL |= RTC_CTL_ALRM0EN;
|
|
}else{
|
|
RTC_CTL |= RTC_CTL_ALRM1EN;
|
|
}
|
|
|
|
}
|
|
|
|
/*!
|
|
\brief disable RTC alarm
|
|
\param[in] rtc_alarm: RTC_ALARM0 or RTC_ALARM1
|
|
\param[out] none
|
|
\retval ErrStatus: ERROR or SUCCESS
|
|
*/
|
|
ErrStatus rtc_alarm_disable(uint8_t rtc_alarm)
|
|
{
|
|
volatile uint32_t time_index = RTC_ALRMXWF_TIMEOUT;
|
|
ErrStatus error_status = ERROR;
|
|
uint32_t flag_status = RESET;
|
|
|
|
/* clear the state of alarm */
|
|
if(RTC_ALARM0 == rtc_alarm){
|
|
RTC_CTL &= (uint32_t)(~RTC_CTL_ALRM0EN);
|
|
/* wait until ALRM0WF flag to be set after the alarm is disabled */
|
|
do{
|
|
flag_status = RTC_ICS & RTC_ICS_ALRM0WF;
|
|
}while((--time_index > 0U) && ((uint32_t)RESET == flag_status));
|
|
}else{
|
|
RTC_CTL &= (uint32_t)(~RTC_CTL_ALRM1EN);
|
|
/* wait until ALRM1WF flag to be set after the alarm is disabled */
|
|
do{
|
|
flag_status = RTC_ICS & RTC_ICS_ALRM1WF;
|
|
}while((--time_index > 0U) && ((uint32_t)RESET == flag_status));
|
|
}
|
|
|
|
if ((uint32_t)RESET != flag_status){
|
|
error_status = SUCCESS;
|
|
}
|
|
return error_status;
|
|
}
|
|
|
|
/*!
|
|
\brief enable RTC time-stamp
|
|
\param[in] edge: specify which edge to detect of time-stamp
|
|
\arg RTC_TIMESTAMP_RISING_EDGE: rising edge is valid event edge for timestamp event
|
|
\arg RTC_TIMESTAMP_FALLING_EDGE: falling edge is valid event edge for timestamp event
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void rtc_timestamp_enable(uint32_t edge)
|
|
{
|
|
uint32_t reg_ctl = 0U;
|
|
|
|
/* clear the bits to be configured in RTC_CTL */
|
|
reg_ctl = (uint32_t)(RTC_CTL & (uint32_t)(~(RTC_CTL_TSEG | RTC_CTL_TSEN)));
|
|
|
|
/* new configuration */
|
|
reg_ctl |= (uint32_t)(edge | RTC_CTL_TSEN);
|
|
/* disable the write protection */
|
|
RTC_WPK = RTC_UNLOCK_KEY1;
|
|
RTC_WPK = RTC_UNLOCK_KEY2;
|
|
|
|
RTC_CTL = (uint32_t)reg_ctl;
|
|
/* enable the write protection */
|
|
RTC_WPK = RTC_LOCK_KEY;
|
|
}
|
|
|
|
/*!
|
|
\brief disable RTC time-stamp
|
|
\param[in] none
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void rtc_timestamp_disable(void)
|
|
{
|
|
/* clear the TSEN bit */
|
|
RTC_CTL &= (uint32_t)(~ RTC_CTL_TSEN);
|
|
}
|
|
|
|
/*!
|
|
\brief get RTC timestamp time and date
|
|
\param[in] none
|
|
\param[out] rtc_timestamp: pointer to a rtc_timestamp_struct structure which contains
|
|
parameters for RTC time-stamp configuration
|
|
members of the structure and the member values are shown as below:
|
|
timestamp_month: RTC_JAN, RTC_FEB, RTC_MAR, RTC_APR, RTC_MAY, RTC_JUN,
|
|
RTC_JUL, RTC_AUG, RTC_SEP, RTC_OCT, RTC_NOV, RTC_DEC
|
|
timestamp_date: 0x1 - 0x31(BCD format)
|
|
timestamp_day: RTC_MONDAY, RTC_TUESDAY, RTC_WEDNESDAY, RTC_THURSDAY, RTC_FRIDAY,
|
|
RTC_SATURDAY, RTC_SUNDAY
|
|
timestamp_hour: 0x0 - 0x12(BCD format) or 0x0 - 0x23(BCD format) depending on the rtc display_format
|
|
timestamp_minute: 0x0 - 0x59(BCD format)
|
|
timestamp_second: 0x0 - 0x59(BCD format)
|
|
am_pm: RTC_AM, RTC_PM
|
|
\retval none
|
|
*/
|
|
void rtc_timestamp_get(rtc_timestamp_struct* rtc_timestamp)
|
|
{
|
|
uint32_t temp_tts = 0U, temp_dts = 0U;
|
|
|
|
/* get the value of time_stamp registers */
|
|
temp_tts = (uint32_t)RTC_TTS;
|
|
temp_dts = (uint32_t)RTC_DTS;
|
|
|
|
/* get timestamp time and construct the rtc_timestamp_struct structure */
|
|
rtc_timestamp->am_pm = (uint32_t)(temp_tts & RTC_TTS_PM);
|
|
rtc_timestamp->timestamp_month = (uint8_t)GET_DTS_MON(temp_dts);
|
|
rtc_timestamp->timestamp_date = (uint8_t)GET_DTS_DAY(temp_dts);
|
|
rtc_timestamp->timestamp_day = (uint8_t)GET_DTS_DOW(temp_dts);
|
|
rtc_timestamp->timestamp_hour = (uint8_t)GET_TTS_HR(temp_tts);
|
|
rtc_timestamp->timestamp_minute = (uint8_t)GET_TTS_MN(temp_tts);
|
|
rtc_timestamp->timestamp_second = (uint8_t)GET_TTS_SC(temp_tts);
|
|
}
|
|
|
|
/*!
|
|
\brief get RTC time-stamp subsecond
|
|
\param[in] none
|
|
\param[out] none
|
|
\retval RTC time-stamp subsecond value
|
|
*/
|
|
uint32_t rtc_timestamp_subsecond_get(void)
|
|
{
|
|
return ((uint32_t)RTC_SSTS);
|
|
}
|
|
|
|
/*!
|
|
\brief enable RTC tamper
|
|
\param[in] rtc_tamper: pointer to a rtc_tamper_struct structure which contains
|
|
parameters for RTC tamper configuration
|
|
members of the structure and the member values are shown as below:
|
|
detecting tamper event can using edge mode or level mode
|
|
(1) using edge mode configuration:
|
|
tamper_source: RTC_TAMPER0, RTC_TAMPER1
|
|
tamper_trigger: RTC_TAMPER_TRIGGER_EDGE_RISING, RTC_TAMPER_TRIGGER_EDGE_FALLING
|
|
tamper_filter: RTC_FLT_EDGE
|
|
tamper_with_timestamp: DISABLE, ENABLE
|
|
(2) using level mode configuration:
|
|
tamper_source: RTC_TAMPER0, RTC_TAMPER1
|
|
tamper_trigger:RTC_TAMPER_TRIGGER_LEVEL_LOW, RTC_TAMPER_TRIGGER_LEVEL_HIGH
|
|
tamper_filter: RTC_FLT_2S, RTC_FLT_4S, RTC_FLT_8S
|
|
tamper_sample_frequency: RTC_FREQ_DIV32768, RTC_FREQ_DIV16384, RTC_FREQ_DIV8192,
|
|
RTC_FREQ_DIV4096, RTC_FREQ_DIV2048, RTC_FREQ_DIV1024,
|
|
RTC_FREQ_DIV512, RTC_FREQ_DIV256
|
|
tamper_precharge_enable: DISABLE, ENABLE
|
|
tamper_precharge_time: RTC_PRCH_1C, RTC_PRCH_2C, RTC_PRCH_4C, RTC_PRCH_8C
|
|
tamper_with_timestamp: DISABLE, ENABLE
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void rtc_tamper_enable(rtc_tamper_struct* rtc_tamper)
|
|
{
|
|
/* disable tamper */
|
|
RTC_TAMP &= (uint32_t)~(rtc_tamper->tamper_source);
|
|
|
|
/* tamper filter must be used when the tamper source is voltage level detection */
|
|
RTC_TAMP &= (uint32_t)~RTC_TAMP_FLT;
|
|
|
|
/* the tamper source is voltage level detection */
|
|
if((uint32_t)(rtc_tamper->tamper_filter) != RTC_FLT_EDGE ){
|
|
RTC_TAMP &= (uint32_t)~(RTC_TAMP_DISPU | RTC_TAMP_PRCH | RTC_TAMP_FREQ | RTC_TAMP_FLT);
|
|
|
|
/* check if the tamper pin need precharge, if need, then configure the precharge time */
|
|
if(DISABLE == rtc_tamper->tamper_precharge_enable){
|
|
RTC_TAMP |= (uint32_t)RTC_TAMP_DISPU;
|
|
}else{
|
|
RTC_TAMP |= (uint32_t)(rtc_tamper->tamper_precharge_time);
|
|
}
|
|
|
|
RTC_TAMP |= (uint32_t)(rtc_tamper->tamper_sample_frequency);
|
|
RTC_TAMP |= (uint32_t)(rtc_tamper->tamper_filter);
|
|
|
|
/* configure the tamper trigger */
|
|
RTC_TAMP &= ((uint32_t)~((rtc_tamper->tamper_source) << RTC_TAMPER_TRIGGER_POS));
|
|
if(RTC_TAMPER_TRIGGER_LEVEL_LOW != rtc_tamper->tamper_trigger){
|
|
RTC_TAMP |= (uint32_t)((rtc_tamper->tamper_source)<< RTC_TAMPER_TRIGGER_POS);
|
|
}
|
|
}else{
|
|
/* configure the tamper trigger */
|
|
RTC_TAMP &= ((uint32_t)~((rtc_tamper->tamper_source) << RTC_TAMPER_TRIGGER_POS));
|
|
if(RTC_TAMPER_TRIGGER_EDGE_RISING != rtc_tamper->tamper_trigger){
|
|
RTC_TAMP |= (uint32_t)((rtc_tamper->tamper_source)<< RTC_TAMPER_TRIGGER_POS);
|
|
}
|
|
}
|
|
RTC_TAMP &= (uint32_t)~RTC_TAMP_TPTS;
|
|
if(DISABLE != rtc_tamper->tamper_with_timestamp){
|
|
/* the tamper event also cause a time-stamp event */
|
|
RTC_TAMP |= (uint32_t)RTC_TAMP_TPTS;
|
|
}
|
|
/* enable tamper */
|
|
RTC_TAMP |= (uint32_t)(rtc_tamper->tamper_source);
|
|
}
|
|
|
|
/*!
|
|
\brief disable RTC tamper
|
|
\param[in] source: specify which tamper source to be disabled
|
|
\arg RTC_TAMPER0
|
|
\arg RTC_TAMPER1
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void rtc_tamper_disable(uint32_t source)
|
|
{
|
|
/* disable tamper */
|
|
RTC_TAMP &= (uint32_t)~source;
|
|
|
|
}
|
|
|
|
/*!
|
|
\brief reset the RTC_BKP registers by sofware
|
|
\param[in] none
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void rtc_software_bkp_reset(void)
|
|
{
|
|
RTC_TAMP |= RTC_TAMP_BKERASE;
|
|
}
|
|
|
|
/*!
|
|
\brief tamperx event does not erase the RTC_BKP registers
|
|
\param[in] ne_source: specify which tamper source will not trigger the RTC_BKP registers reset
|
|
\arg RTC_TAMPXNOER_NONE: both tamper0 and tamper1 event will trigger RTC_BKP registers reset
|
|
\arg RTC_TAMPXNOER_TP0: tamper0 event will not trigger RTC_BKP registers reset
|
|
\arg RTC_TAMPXNOER_TP1: tamper1 event will not trigger RTC_BKP registers reset
|
|
\arg RTC_TAMPXNOER_TP0_TP1: Neither tamper0 nor tamepr1 event will trigger RTC_BKP registers reset
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void rtc_tamper_without_bkp_seset(uint32_t ne_source)
|
|
{
|
|
RTC_TAMP &= (uint32_t)~(RTC_TAMP_TP0NOER | RTC_TAMP_TP1NOER );
|
|
RTC_TAMP |= ne_source;
|
|
}
|
|
|
|
/*!
|
|
\brief enable specified RTC interrupt
|
|
\param[in] interrupt: specify which interrupt source to be enabled
|
|
\arg RTC_INT_TIMESTAMP: timestamp interrupt
|
|
\arg RTC_INT_ALARM0: alarm0 interrupt
|
|
\arg RTC_INT_ALARM1: alarm1 interrupt
|
|
\arg RTC_INT_TAMP: tamper detection interrupt
|
|
\arg RTC_INT_WAKEUP: wakeup timer interrupt
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void rtc_interrupt_enable(uint32_t interrupt)
|
|
{
|
|
/* disable the write protection */
|
|
RTC_WPK = RTC_UNLOCK_KEY1;
|
|
RTC_WPK = RTC_UNLOCK_KEY2;
|
|
/* enable the interrupts in RTC_CTL register */
|
|
RTC_CTL |= (uint32_t)(interrupt & (uint32_t)~RTC_TAMP_TPIE);
|
|
/* enable the interrupts in RTC_TAMP register */
|
|
RTC_TAMP |= (uint32_t)(interrupt & RTC_TAMP_TPIE);
|
|
/* enable the write protection */
|
|
RTC_WPK = RTC_LOCK_KEY;
|
|
}
|
|
|
|
/*!
|
|
\brief disble specified RTC interrupt
|
|
\param[in] interrupt: specify which interrupt source to be disabled
|
|
\arg RTC_INT_TIMESTAMP: timestamp interrupt
|
|
\arg RTC_INT_ALARM0: alarm0 interrupt
|
|
\arg RTC_INT_ALARM1: alarm1 interrupt
|
|
\arg RTC_INT_TAMP: tamper detection interrupt
|
|
\arg RTC_INT_WAKEUP: wakeup timer interrupt
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void rtc_interrupt_disable(uint32_t interrupt)
|
|
{
|
|
/* disable the interrupts in RTC_CTL register */
|
|
RTC_CTL &= (uint32_t)~(interrupt & (uint32_t)~RTC_TAMP_TPIE);
|
|
/* disable the interrupts in RTC_TAMP register */
|
|
RTC_TAMP &= (uint32_t)~(interrupt & RTC_TAMP_TPIE);
|
|
}
|
|
|
|
/*!
|
|
\brief check specified flag
|
|
\param[in] flag: specify which flag to check
|
|
\arg RTC_FLAG_SCP: smooth calibration pending flag
|
|
\arg RTC_FLAG_TP1: RTC tamper 1 detected flag
|
|
\arg RTC_FLAG_TP0: RTC tamper 0 detected flag
|
|
\arg RTC_FLAG_TSOVR: time-stamp overflow flag
|
|
\arg RTC_FLAG_TS: time-stamp flag
|
|
\arg RTC_FLAG_ALARM0: alarm0 occurs flag
|
|
\arg RTC_FLAG_ALARM1: alarm1 occurs flag
|
|
\arg RTC_FLAG_WT: wakeup timer occurs flag
|
|
\arg RTC_FLAG_INIT: initialization state flag
|
|
\arg RTC_FLAG_RSYN: register synchronization flag
|
|
\arg RTC_FLAG_YCM: year configuration mark status flag
|
|
\arg RTC_FLAG_SOP: shift function operation pending flag
|
|
\arg RTC_FLAG_ALARM0W: alarm0 configuration can be written flag
|
|
\arg RTC_FLAG_ALARM1W: alarm1 configuration can be written flag
|
|
\arg RTC_FLAG_WTW: wakeup timer can be written flag
|
|
\param[out] none
|
|
\retval FlagStatus: SET or RESET
|
|
*/
|
|
FlagStatus rtc_flag_get(uint32_t flag)
|
|
{
|
|
FlagStatus flag_state = RESET;
|
|
if((flag & RTC_FLAG_ICSRM) == RTC_FLAG_ICSRM){
|
|
if ((uint32_t)RESET != (RTC_ICS & flag)){
|
|
flag_state = SET;
|
|
}
|
|
}else{
|
|
if ((uint32_t)RESET != (RTC_STAT & flag)){
|
|
flag_state = SET;
|
|
}
|
|
}
|
|
return flag_state;
|
|
}
|
|
|
|
/*!
|
|
\brief clear specified flag
|
|
\param[in] flag: specify which flag to clear
|
|
\arg RTC_FLAG_TP1: RTC tamper 1 detected flag
|
|
\arg RTC_FLAG_TP0: RTC tamper 0 detected flag
|
|
\arg RTC_FLAG_TSOVR: time-stamp overflow flag
|
|
\arg RTC_FLAG_TS: time-stamp flag
|
|
\arg RTC_FLAG_WT: wakeup timer occurs flag
|
|
\arg RTC_FLAG_ALARM0: alarm0 occurs flag
|
|
\arg RTC_FLAG_ALARM1: alarm1 occurs flag
|
|
\arg RTC_FLAG_RSYN: register synchronization flag
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void rtc_flag_clear(uint32_t flag)
|
|
{
|
|
if((flag & RTC_FLAG_ICSRM) == RTC_FLAG_ICSRM){
|
|
/* RSYNF bit is also can be cleared by software writing 0 */
|
|
RTC_ICS &= (uint32_t)(~flag);
|
|
}else{
|
|
/* Writing 1 in a bit clears the corresponding bit in the RTC_STAT register. */
|
|
RTC_STATC |= flag;
|
|
}
|
|
}
|
|
|
|
/*!
|
|
\brief get specified non-secure interrupt flag
|
|
\param[in] int_flag: specify which flag to check
|
|
\arg RTC_NSMI_STAT_ALRM0NSMF: alarm0 non-secure interrupt masked flag
|
|
\arg RTC_NSMI_STAT_ALRM1NSMF: alarm1 non-secure interrupt masked flag
|
|
\arg RTC_NSMI_STAT_WTNSMF: wakeup timer non-secure interrupt masked flag
|
|
\arg RTC_NSMI_STAT_TSNSMF: time-stamp non-secure interrupt masked flag
|
|
\arg RTC_NSMI_STAT_TSOVRNSMF: Time-stamp overflow non-secure interrupt masked flag
|
|
\arg RTC_NSMI_STAT_TP0NSMF: RTC_TAMP0 non-secure interrupt masked flag
|
|
\arg RTC_NSMI_STAT_TP1NSMF: RTC_TAMP1 non-secure interrupt masked flag
|
|
\param[out] none
|
|
\retval FlagStatus: SET or RESET
|
|
*/
|
|
FlagStatus rtc_nsec_interrupt_flag_get(uint32_t int_flag)
|
|
{
|
|
FlagStatus flag_state = RESET;
|
|
if ((uint32_t)RESET != (RTC_NSMI_STAT & int_flag)){
|
|
flag_state = SET;
|
|
}
|
|
return flag_state;
|
|
}
|
|
|
|
/*!
|
|
\brief clear specified non-secure interrupt flag
|
|
\param[in] int_flag: specify which flag to clear
|
|
\arg RTC_NSMI_STAT_ALRM0NSMF: alarm0 non-secure interrupt masked flag
|
|
\arg RTC_NSMI_STAT_ALRM1NSMF: alarm1 non-secure interrupt masked flag
|
|
\arg RTC_NSMI_STAT_WTNSMF: wakeup timer non-secure interrupt masked flag
|
|
\arg RTC_NSMI_STAT_TSNSMF: time-stamp non-secure interrupt masked flag
|
|
\arg RTC_NSMI_STAT_TSOVRNSMF: Time-stamp overflow non-secure interrupt masked flag
|
|
\arg RTC_NSMI_STAT_TP0NSMF: RTC_TAMP0 non-secure interrupt masked flag
|
|
\arg RTC_NSMI_STAT_TP1NSMF: RTC_TAMP1 non-secure interrupt masked flag
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void rtc_nsec_interrupt_flag_clear(uint32_t int_flag)
|
|
{
|
|
/* Writing 1 in a bit clears the corresponding bit in the RTC_NSMI_STAT register. */
|
|
RTC_STATC |= int_flag;
|
|
}
|
|
|
|
/*!
|
|
\brief get specified secure interrupt flag
|
|
\param[in] int_flag: specify which flag to check
|
|
\arg RTC_SMI_STAT_ALRM0SMF: alarm0 secure interrupt masked flag
|
|
\arg RTC_SMI_STAT_ALRM1SMF: alarm1 secure interrupt masked flag
|
|
\arg RTC_SMI_STAT_WTSMF: wakeup timer secure interrupt masked flag
|
|
\arg RTC_SMI_STAT_TSSMF: time-stamp secure interrupt masked flag
|
|
\arg RTC_SMI_STAT_TSOVRSMF: Time-stamp overflow secure interrupt masked flag
|
|
\arg RTC_SMI_STAT_TP0SMF: RTC_TAMP0 secure interrupt masked flag
|
|
\arg RTC_SMI_STAT_TP1SMF: RTC_TAMP1 secure interrupt masked flag
|
|
\param[out] none
|
|
\retval FlagStatus: SET or RESET
|
|
*/
|
|
FlagStatus rtc_sec_interrupt_flag_get(uint32_t int_flag)
|
|
{
|
|
FlagStatus flag_state = RESET;
|
|
if ((uint32_t)RESET != (RTC_SMI_STAT & int_flag)){
|
|
flag_state = SET;
|
|
}
|
|
return flag_state;
|
|
}
|
|
|
|
/*!
|
|
\brief clear specified secure interrupt flag
|
|
\param[in] int_flag: specify which flag to clear
|
|
\arg RTC_SMI_STAT_ALRM0SMF: alarm0 secure interrupt masked flag
|
|
\arg RTC_SMI_STAT_ALRM1SMF: alarm1 secure interrupt masked flag
|
|
\arg RTC_SMI_STAT_WTSMF: wakeup timer secure interrupt masked flag
|
|
\arg RTC_SMI_STAT_TSSMF: time-stamp secure interrupt masked flag
|
|
\arg RTC_SMI_STAT_TSOVRSMF: Time-stamp overflow secure interrupt masked flag
|
|
\arg RTC_SMI_STAT_TP0SMF: RTC_TAMP0 secure interrupt masked flag
|
|
\arg RTC_SMI_STAT_TP1SMF: RTC_TAMP1 secure interrupt masked flag
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void rtc_sec_interrupt_flag_clear(uint32_t int_flag)
|
|
{
|
|
/* Writing 1 in a bit clears the corresponding bit in the RTC_SMI_STAT register. */
|
|
RTC_STATC |= int_flag;
|
|
}
|
|
|
|
/*!
|
|
\brief select the RTC output pin pad
|
|
\param[in] pad: specify the rt output pad is PC15 or not
|
|
\arg RTC_OUT_PC15: the rtc output pad is PC15
|
|
\arg RTC_OUT_PA3_PA8: the rtc output pad is PA3 or PA8 according to the AFIO configuration
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void rtc_output_pad_select(uint32_t pad)
|
|
{
|
|
RTC_CTL &= (uint32_t)~(RTC_CTL_OUT2EN);
|
|
RTC_CTL |= (uint32_t)(pad);
|
|
}
|
|
|
|
/*!
|
|
\brief configure rtc alarm output source
|
|
\param[in] source: specify signal to output
|
|
\arg RTC_ALARM0_HIGH: when the alarm0 flag is set, the output pin is high
|
|
\arg RTC_ALARM0_LOW: when the alarm0 flag is set, the output pin is low
|
|
\arg RTC_ALARM1_HIGH: when the alarm1 flag is set, the output pin is high
|
|
\arg RTC_ALARM1_LOW: when the alarm1 flag is set, the output pin is low
|
|
\arg RTC_WAKEUP_HIGH: when the wakeup flag is set, the output pin is high
|
|
\arg RTC_WAKEUP_LOW: when the wakeup flag is set, the output pin is low
|
|
\param[in] mode: specify the output pin mode when output alarm signal or auto wakeup signal
|
|
\arg RTC_ALARM_OUTPUT_OD: open drain mode
|
|
\arg RTC_ALARM_OUTPUT_PP: push pull mode
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void rtc_alarm_output_config(uint32_t source, uint32_t mode)
|
|
{
|
|
RTC_CTL &= ~(RTC_CTL_OS | RTC_CTL_OPOL);
|
|
RTC_TAMP &= ~RTC_TAMP_AOT;
|
|
|
|
RTC_CTL |= (uint32_t)(source);
|
|
/* alarm output */
|
|
RTC_TAMP |= (uint32_t)(mode);
|
|
}
|
|
|
|
/*!
|
|
\brief configure rtc calibration output source
|
|
\param[in] source: specify signal to output
|
|
\arg RTC_CALIBRATION_512HZ: when the LSE freqency is 32768Hz and the RTC_PSC
|
|
is the default value, output 512Hz signal
|
|
\arg RTC_CALIBRATION_1HZ: when the LSE freqency is 32768Hz and the RTC_PSC
|
|
is the default value, output 1Hz signal
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void rtc_calibration_output_config(uint32_t source)
|
|
{
|
|
/* disable the write protection */
|
|
RTC_WPK = RTC_UNLOCK_KEY1;
|
|
RTC_WPK = RTC_UNLOCK_KEY2;
|
|
|
|
RTC_CTL &= (uint32_t)~(RTC_CTL_COEN | RTC_CTL_COS);
|
|
|
|
RTC_CTL |= (uint32_t)(source);
|
|
/* enable the write protection */
|
|
RTC_WPK = RTC_LOCK_KEY;
|
|
}
|
|
|
|
/*!
|
|
\brief adjust the daylight saving time by adding or substracting one hour from the current time
|
|
\param[in] operation: hour adjustment operation
|
|
\arg RTC_CTL_A1H: add one hour
|
|
\arg RTC_CTL_S1H: substract one hour
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void rtc_hour_adjust(uint32_t operation)
|
|
{
|
|
/* disable the write protection */
|
|
RTC_WPK = RTC_UNLOCK_KEY1;
|
|
RTC_WPK = RTC_UNLOCK_KEY2;
|
|
|
|
RTC_CTL |= (uint32_t)(operation);
|
|
|
|
/* enable the write protection */
|
|
RTC_WPK = RTC_LOCK_KEY;
|
|
}
|
|
|
|
/*!
|
|
\brief adjust RTC second or subsecond value of current time
|
|
\param[in] add: add 1s to current time or not
|
|
\arg RTC_SHIFT_ADD1S_RESET: no effect
|
|
\arg RTC_SHIFT_ADD1S_SET: add 1s to current time
|
|
\param[in] minus: number of subsecond to minus from current time(0x0 - 0x7FFF)
|
|
\param[out] none
|
|
\retval ErrStatus: ERROR or SUCCESS
|
|
*/
|
|
ErrStatus rtc_second_adjust(uint32_t add, uint32_t minus)
|
|
{
|
|
volatile uint32_t time_index = RTC_SHIFTCTL_TIMEOUT;
|
|
ErrStatus error_status = ERROR;
|
|
uint32_t flag_status = RESET;
|
|
uint32_t temp=0U;
|
|
/* disable the write protection */
|
|
RTC_WPK = RTC_UNLOCK_KEY1;
|
|
RTC_WPK = RTC_UNLOCK_KEY2;
|
|
|
|
/* check if a shift operation is ongoing */
|
|
do{
|
|
flag_status = RTC_ICS & RTC_ICS_SOPF;
|
|
}while((--time_index > 0U) && ((uint32_t)RESET != flag_status));
|
|
|
|
/* check if the function of reference clock detection is disabled */
|
|
temp = RTC_CTL & RTC_CTL_REFEN;
|
|
if((RESET == flag_status) && (RESET == temp)){
|
|
RTC_SHIFTCTL = (uint32_t)(add | SHIFTCTL_SFS(minus));
|
|
error_status = rtc_register_sync_wait();
|
|
}
|
|
/* enable the write protection */
|
|
RTC_WPK = RTC_LOCK_KEY;
|
|
return error_status;
|
|
}
|
|
|
|
/*!
|
|
\brief enable RTC bypass shadow registers function
|
|
\param[in] none
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void rtc_bypass_shadow_enable(void)
|
|
{
|
|
RTC_CTL |= RTC_CTL_BPSHAD;
|
|
}
|
|
|
|
/*!
|
|
\brief disable RTC bypass shadow registers function
|
|
\param[in] none
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void rtc_bypass_shadow_disable(void)
|
|
{
|
|
RTC_CTL &= ~RTC_CTL_BPSHAD;
|
|
}
|
|
|
|
/*!
|
|
\brief enable RTC reference clock detection function
|
|
\param[in] none
|
|
\param[out] none
|
|
\retval ErrStatus: ERROR or SUCCESS
|
|
*/
|
|
ErrStatus rtc_refclock_detection_enable(void)
|
|
{
|
|
ErrStatus error_status = ERROR;
|
|
|
|
/* disable the write protection */
|
|
RTC_WPK = RTC_UNLOCK_KEY1;
|
|
RTC_WPK = RTC_UNLOCK_KEY2;
|
|
|
|
/* enter init mode */
|
|
error_status = rtc_init_mode_enter();
|
|
|
|
if(ERROR != error_status){
|
|
RTC_CTL |= (uint32_t)RTC_CTL_REFEN;
|
|
/* exit init mode */
|
|
rtc_init_mode_exit();
|
|
}
|
|
/* enable the write protection */
|
|
RTC_WPK = RTC_LOCK_KEY;
|
|
return error_status;
|
|
}
|
|
|
|
/*!
|
|
\brief disable RTC reference clock detection function
|
|
\param[in] none
|
|
\param[out] none
|
|
\retval ErrStatus: ERROR or SUCCESS
|
|
*/
|
|
ErrStatus rtc_refclock_detection_disable(void)
|
|
{
|
|
ErrStatus error_status = ERROR;
|
|
|
|
/* disable the write protection */
|
|
RTC_WPK = RTC_UNLOCK_KEY1;
|
|
RTC_WPK = RTC_UNLOCK_KEY2;
|
|
|
|
/* enter init mode */
|
|
error_status = rtc_init_mode_enter();
|
|
|
|
if(ERROR != error_status){
|
|
RTC_CTL &= (uint32_t)~RTC_CTL_REFEN;
|
|
/* exit init mode */
|
|
rtc_init_mode_exit();
|
|
}
|
|
|
|
/* enable the write protection */
|
|
RTC_WPK = RTC_LOCK_KEY;
|
|
|
|
return error_status;
|
|
}
|
|
|
|
/*!
|
|
\brief enable RTC auto wakeup function
|
|
\param[in] none
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void rtc_wakeup_enable(void)
|
|
{
|
|
RTC_CTL |= RTC_CTL_WTEN;
|
|
}
|
|
|
|
/*!
|
|
\brief disable RTC auto wakeup function
|
|
\param[in] none
|
|
\param[out] none
|
|
\retval ErrStatus: ERROR or SUCCESS
|
|
*/
|
|
ErrStatus rtc_wakeup_disable(void)
|
|
{
|
|
ErrStatus error_status = ERROR;
|
|
volatile uint32_t time_index = RTC_WTWF_TIMEOUT;
|
|
uint32_t flag_status = RESET;
|
|
|
|
RTC_CTL &= ~RTC_CTL_WTEN;
|
|
/* wait until the WTWF flag to be set */
|
|
do{
|
|
flag_status = RTC_ICS & RTC_ICS_WTWF;
|
|
}while((--time_index > 0U) && ((uint32_t)RESET == flag_status));
|
|
|
|
if ((uint32_t)RESET == flag_status){
|
|
error_status = ERROR;
|
|
}else{
|
|
error_status = SUCCESS;
|
|
}
|
|
|
|
return error_status;
|
|
}
|
|
|
|
/*!
|
|
\brief set RTC auto wakeup timer clock
|
|
\param[in] wakeup_clock:
|
|
\arg WAKEUP_RTCCK_DIV16: RTC auto wakeup timer clock is RTC clock divided by 16
|
|
\arg WAKEUP_RTCCK_DIV8: RTC auto wakeup timer clock is RTC clock divided by 8
|
|
\arg WAKEUP_RTCCK_DIV4: RTC auto wakeup timer clock is RTC clock divided by 4
|
|
\arg WAKEUP_RTCCK_DIV2: RTC auto wakeup timer clock is RTC clock divided by 2
|
|
\arg WAKEUP_CKSPRE: RTC auto wakeup timer clock is ckspre
|
|
\arg WAKEUP_CKSPRE_2EXP16: RTC auto wakeup timer clock is ckspre and wakeup timer add 2exp16
|
|
\param[out] none
|
|
\retval ErrStatus: ERROR or SUCCESS
|
|
*/
|
|
ErrStatus rtc_wakeup_clock_set(uint8_t wakeup_clock)
|
|
{
|
|
ErrStatus error_status = ERROR;
|
|
volatile uint32_t time_index = RTC_WTWF_TIMEOUT;
|
|
uint32_t flag_status = RESET;
|
|
|
|
/* only when RTC_CTL_WTEN=0 and RTC_ICS_WTWF=1 can write RTC_CTL[2:0] */
|
|
/* wait until the WTWF flag to be set */
|
|
do{
|
|
flag_status = RTC_ICS & RTC_ICS_WTWF;
|
|
}while((--time_index > 0U) && ((uint32_t)RESET == flag_status));
|
|
|
|
if ((uint32_t)RESET == flag_status){
|
|
error_status = ERROR;
|
|
}else{
|
|
RTC_CTL &= (uint32_t)~ RTC_CTL_WTCS;
|
|
RTC_CTL |= (uint32_t)wakeup_clock;
|
|
error_status = SUCCESS;
|
|
}
|
|
|
|
return error_status;
|
|
}
|
|
|
|
/*!
|
|
\brief set wakeup timer value
|
|
\param[in] wakeup_timer: 0x0000-0xffff
|
|
\param[out] none
|
|
\retval ErrStatus: ERROR or SUCCESS
|
|
*/
|
|
ErrStatus rtc_wakeup_timer_set(uint16_t wakeup_timer)
|
|
{
|
|
ErrStatus error_status = ERROR;
|
|
volatile uint32_t time_index = RTC_WTWF_TIMEOUT;
|
|
uint32_t flag_status = RESET;
|
|
|
|
/* wait until the WTWF flag to be set */
|
|
do{
|
|
flag_status = RTC_ICS & RTC_ICS_WTWF;
|
|
}while((--time_index > 0U) && ((uint32_t)RESET == flag_status));
|
|
|
|
if ((uint32_t)RESET == flag_status){
|
|
error_status = ERROR;
|
|
}else{
|
|
RTC_WUT = (uint32_t)wakeup_timer;
|
|
error_status = SUCCESS;
|
|
}
|
|
|
|
return error_status;
|
|
}
|
|
|
|
/*!
|
|
\brief get wakeup timer value
|
|
\param[in] none
|
|
\param[out] none
|
|
\retval wakeup timer value
|
|
*/
|
|
uint16_t rtc_wakeup_timer_get(void)
|
|
{
|
|
return (uint16_t)RTC_WUT;
|
|
}
|
|
|
|
/*!
|
|
\brief configure RTC smooth calibration
|
|
\param[in] window: select calibration window
|
|
\arg RTC_CALIBRATION_WINDOW_32S: 2exp20 RTCCLK cycles, 32s if RTCCLK = 32768 Hz
|
|
\arg RTC_CALIBRATION_WINDOW_16S: 2exp19 RTCCLK cycles, 16s if RTCCLK = 32768 Hz
|
|
\arg RTC_CALIBRATION_WINDOW_8S: 2exp18 RTCCLK cycles, 8s if RTCCLK = 32768 Hz
|
|
\param[in] plus: add RTC clock or not
|
|
\arg RTC_CALIBRATION_PLUS_SET: add one RTC clock every 2048 rtc clock
|
|
\arg RTC_CALIBRATION_PLUS_RESET: no effect
|
|
\param[in] minus: the RTC clock to minus during the calibration window(0x0 - 0x1FF)
|
|
\param[out] none
|
|
\retval ErrStatus: ERROR or SUCCESS
|
|
*/
|
|
ErrStatus rtc_smooth_calibration_config(uint32_t window, uint32_t plus, uint32_t minus)
|
|
{
|
|
volatile uint32_t time_index = RTC_HRFC_TIMEOUT;
|
|
ErrStatus error_status = ERROR;
|
|
uint32_t flag_status = RESET;
|
|
|
|
/* disable the write protection */
|
|
RTC_WPK = RTC_UNLOCK_KEY1;
|
|
RTC_WPK = RTC_UNLOCK_KEY2;
|
|
|
|
/* check if a smooth calibration operation is ongoing */
|
|
do{
|
|
flag_status = RTC_ICS & RTC_ICS_SCPF;
|
|
}while((--time_index > 0U) && ((uint32_t)RESET != flag_status));
|
|
|
|
if((uint32_t)RESET == flag_status){
|
|
RTC_HRFC = (uint32_t)(window | plus | HRFC_CMSK(minus));
|
|
error_status = SUCCESS;
|
|
}
|
|
|
|
/* enable the write protection */
|
|
RTC_WPK = RTC_LOCK_KEY;
|
|
|
|
return error_status;
|
|
}
|
|
|
|
/*!
|
|
\brief enable RTC coarse calibration
|
|
\param[in] none
|
|
\param[out] none
|
|
\retval ErrStatus: ERROR or SUCCESS
|
|
*/
|
|
ErrStatus rtc_coarse_calibration_enable(void)
|
|
{
|
|
ErrStatus error_status = ERROR;
|
|
/* disable the write protection */
|
|
RTC_WPK = RTC_UNLOCK_KEY1;
|
|
RTC_WPK = RTC_UNLOCK_KEY2;
|
|
/* enter init mode */
|
|
error_status = rtc_init_mode_enter();
|
|
|
|
if(ERROR != error_status){
|
|
RTC_CTL |= (uint32_t)RTC_CTL_CCEN;
|
|
/* exit init mode */
|
|
rtc_init_mode_exit();
|
|
}
|
|
/* enable the write protection */
|
|
RTC_WPK = RTC_LOCK_KEY;
|
|
return error_status;
|
|
}
|
|
|
|
/*!
|
|
\brief disable RTC coarse calibration
|
|
\param[in] none
|
|
\param[out] none
|
|
\retval ErrStatus: ERROR or SUCCESS
|
|
*/
|
|
ErrStatus rtc_coarse_calibration_disable(void)
|
|
{
|
|
ErrStatus error_status = ERROR;
|
|
/* disable the write protection */
|
|
RTC_WPK = RTC_UNLOCK_KEY1;
|
|
RTC_WPK = RTC_UNLOCK_KEY2;
|
|
/* enter init mode */
|
|
error_status = rtc_init_mode_enter();
|
|
|
|
if(ERROR != error_status){
|
|
RTC_CTL &= (uint32_t)~RTC_CTL_CCEN;
|
|
/* exit init mode */
|
|
rtc_init_mode_exit();
|
|
}
|
|
|
|
/* enable the write protection */
|
|
RTC_WPK = RTC_LOCK_KEY;
|
|
return error_status;
|
|
}
|
|
|
|
/*!
|
|
\brief config coarse calibration direction and step
|
|
\param[in] direction: CALIB_INCREASE or CALIB_DECREASE
|
|
\param[in] step: 0x00-0x1F
|
|
COSD=0:
|
|
0x00:+0 PPM
|
|
0x01:+4 PPM
|
|
0x02:+8 PPM
|
|
....
|
|
0x1F:+126 PPM
|
|
COSD=1:
|
|
0x00:-0 PPM
|
|
0x01:-2 PPM
|
|
0x02:-4 PPM
|
|
....
|
|
0x1F:-63 PPM
|
|
\param[out] none
|
|
\retval ErrStatus: ERROR or SUCCESS
|
|
*/
|
|
ErrStatus rtc_coarse_calibration_config(uint8_t direction, uint8_t step)
|
|
{
|
|
ErrStatus error_status = ERROR;
|
|
/* disable the write protection */
|
|
RTC_WPK = RTC_UNLOCK_KEY1;
|
|
RTC_WPK = RTC_UNLOCK_KEY2;
|
|
|
|
/* enter init mode */
|
|
error_status = rtc_init_mode_enter();
|
|
|
|
if(ERROR != error_status){
|
|
if(CALIB_DECREASE == direction){
|
|
RTC_COSC |= (uint32_t)RTC_COSC_COSD;
|
|
}else{
|
|
RTC_COSC &= (uint32_t)~RTC_COSC_COSD;
|
|
}
|
|
RTC_COSC &= ~RTC_COSC_COSS;
|
|
RTC_COSC |= (uint32_t)((uint32_t)step & 0x1FU);
|
|
/* exit init mode */
|
|
rtc_init_mode_exit();
|
|
}
|
|
/* enable the write protection */
|
|
RTC_WPK = RTC_LOCK_KEY;
|
|
return error_status;
|
|
}
|
|
|
|
/*!
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|
\brief enable RTC privilege protection mode
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|
\param[in] sub_area: specify which sub area of the RTC module to be protected by the privilege mode
|
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\arg RTC_PPM_CTL_ALRM0PRIP: Alarm 0 privilege protection
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|
\arg RTC_PPM_CTL_ALRM1PRIP: Alarm 1 privilege protection
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|
\arg RTC_PPM_CTL_WUTPRIP: Wakeup timer privilege protection
|
|
\arg RTC_PPM_CTL_TSPRIP: Timestamp privilege protection
|
|
\arg RTC_PPM_CTL_TAMPPRIP: Tamper privilege protection (excluding backup registers)
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|
\arg RTC_PPM_CTL_CALCPRIP: Shift register, daylight saving, calibration and reference clock privilege protection
|
|
\arg RTC_PPM_CTL_INITPRIP: Initialization privilege protection
|
|
\arg RTC_PPM_CTL_RTCPRIP: RTC privilege protection
|
|
\arg RTC_PPM_CTL_BKPRWPRIP: backup registers zone a privilege protection
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|
\arg RTC_PPM_CTL_BKPWPRIP: backup registers zone b privilege protection
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|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void rtc_pri_pro_enable(uint32_t sub_area)
|
|
{
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|
RTC_PPM_CTL |= sub_area;
|
|
}
|
|
|
|
/*!
|
|
\brief disable RTC privilege protection mode
|
|
\param[in] sub_area: specify which sub area of the RTC module to be removed from the protection of the privilege mode
|
|
\arg RTC_PPM_CTL_ALRM0PRIP: Alarm 0 privilege protection
|
|
\arg RTC_PPM_CTL_ALRM1PRIP: Alarm 1 privilege protection
|
|
\arg RTC_PPM_CTL_WUTPRIP: Wakeup timer privilege protection
|
|
\arg RTC_PPM_CTL_TSPRIP: Timestamp privilege protection
|
|
\arg RTC_PPM_CTL_TAMPPRIP: Tamper privilege protection (excluding backup registers)
|
|
\arg RTC_PPM_CTL_CALCPRIP: Shift register, daylight saving, calibration and reference clock privilege protection
|
|
\arg RTC_PPM_CTL_INITPRIP: Initialization privilege protection
|
|
\arg RTC_PPM_CTL_RTCPRIP: RTC privilege protection
|
|
\arg RTC_PPM_CTL_BKPRWPRIP: backup registers zone a privilege protection
|
|
\arg RTC_PPM_CTL_BKPWPRIP: backup registers zone b privilege protection
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void rtc_pri_pro_disable(uint32_t sub_area)
|
|
{
|
|
RTC_PPM_CTL &= (uint32_t)~sub_area;
|
|
}
|
|
|
|
/*!
|
|
\brief enable RTC secure protection mode
|
|
\param[in] sub_area: specify which sub area of the RTC module to be protected by the secure mode
|
|
\arg RTC_SPM_CTL_ALRM0SECP: Alarm 0 secure protection
|
|
\arg RTC_SPM_CTL_ALRM1SECP: Alarm 1 secure protection
|
|
\arg RTC_SPM_CTL_WUTSECP: Wakeup timer secure protection
|
|
\arg RTC_SPM_CTL_TSSECP: Timestamp secure protection
|
|
\arg RTC_SPM_CTL_TAMPSECP: Tamper secure protection (excluding backup registers)
|
|
\arg RTC_SPM_CTL_CALCSECP: Shift register, daylight saving, calibration and reference clock secure protection
|
|
\arg RTC_SPM_CTL_INITSECP: Initialization secure protection
|
|
\arg RTC_SPM_CTL_RTCSECP: RTC global secure protection
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void rtc_sec_pro_enable(uint32_t sub_area)
|
|
{
|
|
RTC_SPM_CTL |= sub_area;
|
|
}
|
|
|
|
/*!
|
|
\brief disable RTC secure protection mode
|
|
\param[in] sub_area: specify which sub area of the RTC module to be removed from the protection of the secure mode
|
|
\arg RTC_SPM_CTL_ALRM0SECP: Alarm 0 protection
|
|
\arg RTC_SPM_CTL_ALRM1SECP: Alarm 1 protection
|
|
\arg RTC_SPM_CTL_WUTSECP: Wakeup timer protection
|
|
\arg RTC_SPM_CTL_TSSECP: Timestamp protection
|
|
\arg RTC_SPM_CTL_TAMPSECP: Tamper protection (excluding backup registers)
|
|
\arg RTC_SPM_CTL_CALCSECP: Shift register, daylight saving, calibration and reference clock protection
|
|
\arg RTC_SPM_CTL_INITSECP: Initialization protection
|
|
\arg RTC_SPM_CTL_RTCSECP: RTC global protection
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void rtc_sec_pro_disable(uint32_t sub_area)
|
|
{
|
|
RTC_SPM_CTL &= (uint32_t)~sub_area;
|
|
}
|
|
|
|
/*!
|
|
\brief set the RTC_BKP secure protection zonea tail value
|
|
\param[in] zonea_tail:RTC_BKP registers secure protection zonea
|
|
\arg RTC_BKP_PRO_ZONEA_TAIL_NONE: there is no RTC_BKP registers secure protection zonea
|
|
\arg RTC_BKP_PRO_ZONEA_TAIL_x(x = 0,1,2,...19):RTC_BKP registers secure protection zonea is from RTC_BKP0 to RTC_BKPx,\
|
|
which can be read and written only when the APB is in secure mode
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void rtc_bkp_zonea_sec_pro_set(uint32_t zonea_tail)
|
|
{
|
|
RTC_SPM_CTL &= (uint32_t)~ RTC_SPM_CTL_BKPRWSECP;
|
|
RTC_SPM_CTL |= zonea_tail;
|
|
}
|
|
|
|
/*!
|
|
\brief set the RTC_BKP secure protection zoneb tail value
|
|
\param[in] zoneb_tail:RTC_BKP registers secure protection zoneb
|
|
\arg RTC_BKP_PRO_ZONEB_TAIL_NONE: there is no RTC_BKP registers secure protection zoneb
|
|
\arg RTC_BKP_PRO_ZONEB_TAIL_x(x = 0,1,2,...19):the last RTC_BKP register of secure protection zoneb is RTC_BKPx,
|
|
if there is no RTC_BKP registers secure protection zoneb
|
|
\param[out] none
|
|
\retval ErrStatus: ERROR or SUCCESS
|
|
*/
|
|
ErrStatus rtc_bkp_zoneb_sec_pro_set(uint32_t zoneb_tail)
|
|
{
|
|
ErrStatus error_status = ERROR;
|
|
uint32_t zonea_tail = 0U;
|
|
|
|
RTC_SPM_CTL &= (uint32_t)~ RTC_SPM_CTL_BKPWSECP;
|
|
RTC_SPM_CTL |= zoneb_tail;
|
|
|
|
zonea_tail = GET_SPM_CTL_BKPRWSECP(RTC_SPM_CTL);
|
|
/* if zonea tail value is larger than or equal to the zoneb tail value, there is no zoneb.*/
|
|
if(zonea_tail < zoneb_tail){
|
|
error_status = SUCCESS;
|
|
}
|
|
|
|
return error_status;
|
|
}
|
|
|
|
/*!
|
|
\brief check the RTC_BKP secure protection zoneb is valid or not
|
|
\param[in] none
|
|
\param[out] none
|
|
\retval ErrStatus: ERROR or SUCCESS
|
|
*/
|
|
ErrStatus rtc_bkp_zoneb_sec_pro_check(void)
|
|
{
|
|
ErrStatus error_status = ERROR;
|
|
uint32_t zonea_tail = 0U;
|
|
uint32_t zoneb_tail = 0U;
|
|
|
|
zonea_tail = GET_SPM_CTL_BKPRWSECP(RTC_SPM_CTL);
|
|
zoneb_tail = GET_SPM_CTL_BKPWSECP(RTC_SPM_CTL);
|
|
/* if zonea tail value is larger than or equal to the zoneb tail value, there is no zoneb.*/
|
|
if(zonea_tail < zoneb_tail){
|
|
error_status = SUCCESS;
|
|
}
|
|
return error_status;
|
|
}
|