938 lines
32 KiB
C
938 lines
32 KiB
C
/*!
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\file gd32w51x_spi.c
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\brief SPI driver
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\version 2021-10-30, V1.0.0, firmware for GD32W51x
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*/
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/*
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Copyright (c) 2021, GigaDevice Semiconductor Inc.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors
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may be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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*/
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#include "gd32w51x_spi.h"
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#define SPI_ERROR_HANDLE(s) do{}while(1)
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/* SPI/I2S parameter initialization mask */
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#define SPI_INIT_MASK ((uint32_t)0x00003040U)
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#define I2S_INIT_MASK ((uint32_t)0x0000F047U)
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#define I2S_FULL_DUPLEX_MASK ((uint32_t)0x0000F040U)
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/* default value */
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#define SPI_I2SPSC_DEFAULT_VALUE ((uint32_t)0x00000002U) /*!< default value of SPI_I2SPSC register */
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/* I2S clock source selection, multiplication and division mask */
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#define I2S1_CLOCK_SEL ((uint32_t)0x00003000U) /*!< I2S1 clock source selection */
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#define PLL_I2S_DIV_MASK ((uint32_t)0x3F000000U) /*!< PLL I2S clock division mask */
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#define PLL2_I2S_PSC_MASK ((uint32_t)0x00070000U) /*!< PLL2 I2S clock multiplication mask */
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#define PLL2_I2S_MUL_MASK ((uint32_t)0x00007F00U) /*!< PLL2 I2S clock multiplication mask */
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#define PLL2_I2S_DIV_MASK ((uint32_t)0x0000003FU) /*!< PLL2 I2S clock division mask */
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/*!
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\brief reset SPI and I2S
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\param[in] spi_periph: SPIx(x=0,1)
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\param[out] none
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\retval none
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*/
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void spi_i2s_deinit(uint32_t spi_periph)
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{
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switch(spi_periph){
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case SPI0:
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/* reset SPI0 */
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rcu_periph_reset_enable(RCU_SPI0RST);
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rcu_periph_reset_disable(RCU_SPI0RST);
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break;
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case SPI1:
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/* reset SPI1 and I2S1 */
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rcu_periph_reset_enable(RCU_SPI1RST);
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rcu_periph_reset_disable(RCU_SPI1RST);
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break;
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default :
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break;
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}
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}
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/*!
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\brief initialize the parameters of SPI struct with default values
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\param[in] none
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\param[out] spi_parameter_struct: the initialized struct spi_parameter_struct pointer
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\retval none
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*/
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void spi_struct_para_init(spi_parameter_struct *spi_struct)
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{
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/* configure the structure with default value */
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spi_struct->device_mode = SPI_SLAVE;
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spi_struct->trans_mode = SPI_TRANSMODE_FULLDUPLEX;
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spi_struct->frame_size = SPI_FRAMESIZE_8BIT;
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spi_struct->nss = SPI_NSS_HARD;
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spi_struct->clock_polarity_phase = SPI_CK_PL_LOW_PH_1EDGE;
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spi_struct->prescale = SPI_PSC_2;
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spi_struct->endian = SPI_ENDIAN_MSB;
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}
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/*!
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\brief initialize SPI parameter
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\param[in] spi_periph: SPIx(x=0,1)
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\param[in] spi_struct: SPI parameter initialization stuct members of the structure
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and the member values are shown as below:
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device_mode: SPI_MASTER, SPI_SLAVE
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trans_mode: SPI_TRANSMODE_FULLDUPLEX, SPI_TRANSMODE_RECEIVEONLY,
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SPI_TRANSMODE_BDRECEIVE, SPI_TRANSMODE_BDTRANSMIT
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frame_size: SPI_FRAMESIZE_16BIT, SPI_FRAMESIZE_8BIT
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nss: SPI_NSS_SOFT, SPI_NSS_HARD
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endian: SPI_ENDIAN_MSB, SPI_ENDIAN_LSB
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clock_polarity_phase: SPI_CK_PL_LOW_PH_1EDGE, SPI_CK_PL_HIGH_PH_1EDGE
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SPI_CK_PL_LOW_PH_2EDGE, SPI_CK_PL_HIGH_PH_2EDGE
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prescale: SPI_PSC_n (n=2,4,8,16,32,64,128,256)
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\param[out] none
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\retval none
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*/
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void spi_init(uint32_t spi_periph, spi_parameter_struct* spi_struct)
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{
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uint32_t reg = 0U;
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reg = SPI_CTL0(spi_periph);
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reg &= SPI_INIT_MASK;
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/* select SPI as master or slave */
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reg |= spi_struct->device_mode;
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/* select SPI transfer mode */
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reg |= spi_struct->trans_mode;
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/* select SPI frame size */
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reg |= spi_struct->frame_size;
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/* select SPI NSS use hardware or software */
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reg |= spi_struct->nss;
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/* select SPI LSB or MSB */
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reg |= spi_struct->endian;
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/* select SPI polarity and phase */
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reg |= spi_struct->clock_polarity_phase;
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/* select SPI prescale to adjust transmit speed */
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reg |= spi_struct->prescale;
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/* write to SPI_CTL0 register */
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SPI_CTL0(spi_periph) = (uint32_t)reg;
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SPI_I2SCTL(spi_periph) &= (uint32_t)(~SPI_I2SCTL_I2SSEL);
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}
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/*!
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\brief enable SPI
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\param[in] spi_periph: SPIx(x=0,1)
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\param[out] none
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\retval none
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*/
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void spi_enable(uint32_t spi_periph)
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{
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SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SPIEN;
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}
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/*!
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\brief disable SPI
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\param[in] spi_periph: SPIx(x=0,1)
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\param[out] none
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\retval none
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*/
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void spi_disable(uint32_t spi_periph)
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{
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SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SPIEN);
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}
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/*!
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\brief initialize I2S parameter
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\param[in] spi_periph: SPIx(x=1)
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\param[in] i2s_mode: I2S operation mode
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only one parameter can be selected which is shown as below:
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\arg I2S_MODE_SLAVETX: I2S1/I2S1_ADD slave transmit mode
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\arg I2S_MODE_SLAVERX: I2S1/I2S1_ADD slave receive mode
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\arg I2S_MODE_MASTERTX: I2S1 master transmit mode
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\arg I2S_MODE_MASTERRX: I2S1 master receive mode
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\param[in] i2s_standard: I2S standard
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only one parameter can be selected which is shown as below:
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\arg I2S_STD_PHILLIPS: I2S phillips standard
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\arg I2S_STD_MSB: I2S MSB standard
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\arg I2S_STD_LSB: I2S LSB standard
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\arg I2S_STD_PCMSHORT: I2S PCM short standard
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\arg I2S_STD_PCMLONG: I2S PCM long standard
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\param[in] i2s_ckpl: I2S idle state clock polarity
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only one parameter can be selected which is shown as below:
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\arg I2S_CKPL_LOW: I2S clock polarity low level
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\arg I2S_CKPL_HIGH: I2S clock polarity high level
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\param[out] none
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\retval none
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*/
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void i2s_init(uint32_t spi_periph, uint32_t i2s_mode, uint32_t i2s_standard, uint32_t i2s_ckpl)
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{
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uint32_t reg= 0U;
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reg = SPI_I2SCTL(spi_periph);
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reg &= I2S_INIT_MASK;
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/* enable I2S mode */
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reg |= (uint32_t)SPI_I2SCTL_I2SSEL;
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/* select I2S mode */
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reg |= (uint32_t)i2s_mode;
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/* select I2S standard */
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reg |= (uint32_t)i2s_standard;
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/* select I2S polarity */
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reg |= (uint32_t)i2s_ckpl;
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/* write to SPI_I2SCTL register */
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SPI_I2SCTL(spi_periph) = (uint32_t)reg;
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}
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/*!
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\brief configure I2S prescaler
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\param[in] spi_periph: SPIx(x=1)
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\param[in] i2s_audiosample: I2S audio sample rate
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only one parameter can be selected which is shown as below:
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\arg I2S_AUDIOSAMPLE_8K: audio sample rate is 8KHz
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\arg I2S_AUDIOSAMPLE_11K: audio sample rate is 11KHz
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\arg I2S_AUDIOSAMPLE_16K: audio sample rate is 16KHz
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\arg I2S_AUDIOSAMPLE_22K: audio sample rate is 22KHz
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\arg I2S_AUDIOSAMPLE_32K: audio sample rate is 32KHz
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\arg I2S_AUDIOSAMPLE_44K: audio sample rate is 44KHz
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\arg I2S_AUDIOSAMPLE_48K: audio sample rate is 48KHz
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\arg I2S_AUDIOSAMPLE_96K: audio sample rate is 96KHz
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\arg I2S_AUDIOSAMPLE_192K: audio sample rate is 192KHz
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\param[in] i2s_frameformat: I2S data length and channel length
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only one parameter can be selected which is shown as below:
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\arg I2S_FRAMEFORMAT_DT16B_CH16B: I2S data length is 16 bit and channel length is 16 bit
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\arg I2S_FRAMEFORMAT_DT16B_CH32B: I2S data length is 16 bit and channel length is 32 bit
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\arg I2S_FRAMEFORMAT_DT24B_CH32B: I2S data length is 24 bit and channel length is 32 bit
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\arg I2S_FRAMEFORMAT_DT32B_CH32B: I2S data length is 32 bit and channel length is 32 bit
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\param[in] i2s_mckout: I2S master clock output
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only one parameter can be selected which is shown as below:
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\arg I2S_MCKOUT_ENABLE: I2S master clock output enable
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\arg I2S_MCKOUT_DISABLE: I2S master clock output disable
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\param[out] none
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\retval none
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*/
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void i2s_psc_config(uint32_t spi_periph, uint32_t i2s_audiosample, uint32_t i2s_frameformat, uint32_t i2s_mckout)
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{
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uint32_t i2sdiv = 2U, i2sof = 0U, clks = 0U, i2sclock = 0U;
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uint32_t pll2psc = 0U, pll2n = 0U, pll2div = 0U, pll2clks = 0U;
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uint32_t sysclock = 0U, pllp = 0U, pllfdiv = 0U;
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/* judge whether the audiosample is 0 */
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if(0U == i2s_audiosample){
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SPI_ERROR_HANDLE("the parameter can not be 0 \r\n");
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}
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/* deinit SPI_I2SPSC register */
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SPI_I2SPSC(spi_periph) = SPI_I2SPSC_DEFAULT_VALUE;
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if(0U == ((RCU_ADDCTL & I2S1_CLOCK_SEL) >> 12)){
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/* get the I2S1 source clock prescaler */
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pll2psc = (uint32_t)((RCU_PLLCFG & PLL2_I2S_PSC_MASK) >> 16U);
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/* get RCU PLL2 clock multiplication factor */
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pll2n = (uint32_t)((RCU_PLLCFG & PLL2_I2S_MUL_MASK) >> 8U);
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/* get RCU PLL2 clock division */
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pll2div = (uint32_t)((RCU_PLLCFG & PLL2_I2S_DIV_MASK));
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if(pll2n < 8U){
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/* multiplier is between 8 and 127 */
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pll2n = 8U;
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}
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/* calculate PLL2 clock */
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pll2clks = (uint32_t)((((HXTAL_VALUE / (pll2psc + 1U)) * pll2n) / pll2div) * 2U);
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/* get the I2S1 clock */
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i2sclock = pll2clks;
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}else if(2U == ((RCU_ADDCTL & I2S1_CLOCK_SEL) >> 12U)){
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/* get system clock */
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sysclock = rcu_clock_freq_get(CK_SYS);
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pllp = (GET_BITS(RCU_PLL, 16U, 17U) + 1U) * 2U;
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/* get RCU PLL I2S1 clock division */
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pllfdiv = (uint32_t)((RCU_ADDCTL & PLL_I2S_DIV_MASK) >> 24U);
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/* get the I2S1 clock */
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i2sclock = (uint32_t)((sysclock * pllp) / (pllfdiv + 1U));
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}else{
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SPI_ERROR_HANDLE(" i2s use external clock \r\n");
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}
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/* config the prescaler depending on the mclk output state, the frame format and audio sample rate */
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if(I2S_MCKOUT_ENABLE == i2s_mckout){
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clks = (uint32_t)(((i2sclock / 256U) * 10U) / i2s_audiosample);
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}else{
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if(I2S_FRAMEFORMAT_DT16B_CH16B == i2s_frameformat){
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clks = (uint32_t)(((i2sclock / 32U) *10U ) / i2s_audiosample);
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}else{
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clks = (uint32_t)(((i2sclock / 64U) *10U ) / i2s_audiosample);
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}
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}
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/* remove the floating point */
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clks = (clks + 5U) / 10U;
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i2sof = (clks & 0x00000001U);
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i2sdiv = ((clks - i2sof) / 2U);
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i2sof = (i2sof << 8U);
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/* set the default values */
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if((i2sdiv < 2U) || (i2sdiv > 255U)){
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i2sdiv = 2U;
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i2sof = 0U;
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}
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/* configure SPI_I2SPSC */
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SPI_I2SPSC(spi_periph) = (uint32_t)(i2sdiv | i2sof | i2s_mckout);
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/* clear SPI_I2SCTL_DTLEN and SPI_I2SCTL_CHLEN bits */
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SPI_I2SCTL(spi_periph) &= (uint32_t)(~(SPI_I2SCTL_DTLEN | SPI_I2SCTL_CHLEN));
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/* configure data frame format */
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SPI_I2SCTL(spi_periph) |= (uint32_t)i2s_frameformat;
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}
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/*!
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\brief configure I2S input clock prescaler
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\param[in] input_clock: I2S1 external input clock frequency
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\param[in] i2s_audiosample: I2S audio sample rate
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only one parameter can be selected which is shown as below:
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\arg I2S_AUDIOSAMPLE_8K: audio sample rate is 8KHz
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\arg I2S_AUDIOSAMPLE_11K: audio sample rate is 11KHz
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\arg I2S_AUDIOSAMPLE_16K: audio sample rate is 16KHz
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\arg I2S_AUDIOSAMPLE_22K: audio sample rate is 22KHz
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\arg I2S_AUDIOSAMPLE_32K: audio sample rate is 32KHz
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\arg I2S_AUDIOSAMPLE_44K: audio sample rate is 44KHz
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\arg I2S_AUDIOSAMPLE_48K: audio sample rate is 48KHz
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\arg I2S_AUDIOSAMPLE_96K: audio sample rate is 96KHz
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\arg I2S_AUDIOSAMPLE_192K: audio sample rate is 192KHz
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\param[in] i2s_frameformat: I2S data length and channel length
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only one parameter can be selected which is shown as below:
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\arg I2S_FRAMEFORMAT_DT16B_CH16B: I2S data length is 16 bit and channel length is 16 bit
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\arg I2S_FRAMEFORMAT_DT16B_CH32B: I2S data length is 16 bit and channel length is 32 bit
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\arg I2S_FRAMEFORMAT_DT24B_CH32B: I2S data length is 24 bit and channel length is 32 bit
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\arg I2S_FRAMEFORMAT_DT32B_CH32B: I2S data length is 32 bit and channel length is 32 bit
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\param[in] i2s_mckout: I2S master clock output
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only one parameter can be selected which is shown as below:
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\arg I2S_MCKOUT_ENABLE: I2S master clock output enable
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\arg I2S_MCKOUT_DISABLE: I2S master clock output disable
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\param[out] none
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\retval none
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*/
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void i2s_ckin_psc_config(uint32_t input_clock, uint32_t i2s_audiosample, uint32_t i2s_frameformat, uint32_t i2s_mckout)
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{
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uint32_t i2sdiv = 2U, i2sof = 0U, clks = 0U, i2sclock = 0U;
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/* judge whether the audiosample is 0 */
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if(0U == i2s_audiosample){
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SPI_ERROR_HANDLE("the parameter can not be 0 \r\n");
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}
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/* deinit SPI_I2SPSC register */
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SPI_I2SPSC(SPI1) = SPI_I2SPSC_DEFAULT_VALUE;
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if(1U == ((RCU_ADDCTL & I2S1_CLOCK_SEL) >> 12)){
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/* get the I2S1 clock */
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i2sclock = input_clock;
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}else{
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SPI_ERROR_HANDLE(" i2s use internal clock \r\n");
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}
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/* config the prescaler depending on the mclk output state, the frame format and audio sample rate */
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if(I2S_MCKOUT_ENABLE == i2s_mckout){
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clks = (uint32_t)(((i2sclock / 256U) * 10U) / i2s_audiosample);
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}else{
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if(I2S_FRAMEFORMAT_DT16B_CH16B == i2s_frameformat){
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clks = (uint32_t)(((i2sclock / 32U) *10U ) / i2s_audiosample);
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}else{
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clks = (uint32_t)(((i2sclock / 64U) *10U ) / i2s_audiosample);
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}
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}
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/* remove the floating point */
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clks = (clks + 5U) / 10U;
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i2sof = (clks & 0x00000001U);
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i2sdiv = ((clks - i2sof) / 2U);
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i2sof = (i2sof << 8U);
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/* set the default values */
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if((i2sdiv < 2U) || (i2sdiv > 255U)){
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i2sdiv = 2U;
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i2sof = 0U;
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}
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/* configure SPI_I2SPSC */
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SPI_I2SPSC(SPI1) = (uint32_t)(i2sdiv | i2sof | i2s_mckout);
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/* clear SPI_I2SCTL_DTLEN and SPI_I2SCTL_CHLEN bits */
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SPI_I2SCTL(SPI1) &= (uint32_t)(~(SPI_I2SCTL_DTLEN | SPI_I2SCTL_CHLEN));
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/* configure data frame format */
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SPI_I2SCTL(SPI1) |= (uint32_t)i2s_frameformat;
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}
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/*!
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\brief enable I2S
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\param[in] spi_periph: SPI1, I2S1_ADD
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\param[out] none
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\retval none
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*/
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void i2s_enable(uint32_t spi_periph)
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{
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SPI_I2SCTL(spi_periph) |= (uint32_t)SPI_I2SCTL_I2SEN;
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}
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/*!
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\brief disable I2S
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\param[in] spi_periph: SPI1, I2S1_ADD
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\param[out] none
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|
\retval none
|
|
*/
|
|
void i2s_disable(uint32_t spi_periph)
|
|
{
|
|
SPI_I2SCTL(spi_periph) &= (uint32_t)(~SPI_I2SCTL_I2SEN);
|
|
}
|
|
|
|
/*!
|
|
\brief enable SPI NSS output
|
|
\param[in] spi_periph: SPIx(x=0,1)
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void spi_nss_output_enable(uint32_t spi_periph)
|
|
{
|
|
SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSDRV;
|
|
}
|
|
|
|
/*!
|
|
\brief disable SPI NSS output
|
|
\param[in] spi_periph: SPIx(x=0,1)
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void spi_nss_output_disable(uint32_t spi_periph)
|
|
{
|
|
SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSDRV);
|
|
}
|
|
|
|
/*!
|
|
\brief SPI NSS pin high level in software mode
|
|
\param[in] spi_periph: SPIx(x=0,1)
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void spi_nss_internal_high(uint32_t spi_periph)
|
|
{
|
|
SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SWNSS;
|
|
}
|
|
|
|
/*!
|
|
\brief SPI NSS pin low level in software mode
|
|
\param[in] spi_periph: SPIx(x=0,1)
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void spi_nss_internal_low(uint32_t spi_periph)
|
|
{
|
|
SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SWNSS);
|
|
}
|
|
|
|
/*!
|
|
\brief enable SPI DMA send or receive
|
|
\param[in] spi_periph: SPIx(x=0,1) or I2Sx_ADD(x=1)
|
|
\param[in] spi_dma: SPI DMA mode
|
|
only one parameter can be selected which is shown as below:
|
|
\arg SPI_DMA_TRANSMIT: SPI transmit data use DMA
|
|
\arg SPI_DMA_RECEIVE: SPI receive data use DMA
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void spi_dma_enable(uint32_t spi_periph, uint8_t spi_dma)
|
|
{
|
|
if(SPI_DMA_TRANSMIT == spi_dma){
|
|
SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMATEN;
|
|
}else{
|
|
SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMAREN;
|
|
}
|
|
}
|
|
|
|
/*!
|
|
\brief disable SPI DMA send or receive
|
|
\param[in] spi_periph: SPIx(x=0,1) or I2Sx_ADD(x=1)
|
|
\param[in] spi_dma: SPI DMA mode
|
|
only one parameter can be selected which is shown as below:
|
|
\arg SPI_DMA_TRANSMIT: SPI transmit data use DMA
|
|
\arg SPI_DMA_RECEIVE: SPI receive data use DMA
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void spi_dma_disable(uint32_t spi_periph, uint8_t spi_dma)
|
|
{
|
|
if(SPI_DMA_TRANSMIT == spi_dma){
|
|
SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMATEN);
|
|
}else{
|
|
SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMAREN);
|
|
}
|
|
}
|
|
|
|
/*!
|
|
\brief configure SPI/I2S data frame format
|
|
\param[in] spi_periph: SPIx(x=0,1)
|
|
\param[in] frame_format: SPI frame size
|
|
only one parameter can be selected which is shown as below:
|
|
\arg SPI_FRAMESIZE_16BIT: SPI frame size is 16 bits
|
|
\arg SPI_FRAMESIZE_8BIT: SPI frame size is 8 bits
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format)
|
|
{
|
|
/* clear SPI_CTL0_FF16 bit */
|
|
SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_FF16);
|
|
/* confige SPI_CTL0_FF16 bit */
|
|
SPI_CTL0(spi_periph) |= (uint32_t)frame_format;
|
|
}
|
|
|
|
/*!
|
|
\brief SPI transmit data
|
|
\param[in] spi_periph: SPIx(x=0,1)
|
|
\param[in] data: 16-bit data
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data)
|
|
{
|
|
SPI_DATA(spi_periph) = (uint32_t)data;
|
|
}
|
|
|
|
/*!
|
|
\brief SPI receive data
|
|
\param[in] spi_periph: SPIx(x=0,1)
|
|
\param[out] none
|
|
\retval 16-bit data
|
|
*/
|
|
uint16_t spi_i2s_data_receive(uint32_t spi_periph)
|
|
{
|
|
return ((uint16_t)SPI_DATA(spi_periph));
|
|
}
|
|
|
|
/*!
|
|
\brief configure SPI bidirectional transfer direction
|
|
\param[in] spi_periph: SPIx(x=0,1)
|
|
\param[in] transfer_direction: SPI transfer direction
|
|
only one parameter can be selected which is shown as below:
|
|
\arg SPI_BIDIRECTIONAL_TRANSMIT: SPI work in transmit-only mode
|
|
\arg SPI_BIDIRECTIONAL_RECEIVE: SPI work in receive-only mode
|
|
\retval none
|
|
*/
|
|
void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction)
|
|
{
|
|
if(SPI_BIDIRECTIONAL_TRANSMIT == transfer_direction){
|
|
/* set the transmit only mode */
|
|
SPI_CTL0(spi_periph) |= (uint32_t)SPI_BIDIRECTIONAL_TRANSMIT;
|
|
}else{
|
|
/* set the receive only mode */
|
|
SPI_CTL0(spi_periph) &= SPI_BIDIRECTIONAL_RECEIVE;
|
|
}
|
|
}
|
|
|
|
/*!
|
|
\brief set SPI CRC polynomial
|
|
\param[in] spi_periph: SPIx(x=0,1)
|
|
\param[in] crc_poly: CRC polynomial value
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void spi_crc_polynomial_set(uint32_t spi_periph,uint16_t crc_poly)
|
|
{
|
|
/* set SPI CRC polynomial */
|
|
SPI_CRCPOLY(spi_periph) = (uint32_t)crc_poly;
|
|
}
|
|
|
|
/*!
|
|
\brief get SPI CRC polynomial
|
|
\param[in] spi_periph: SPIx(x=0,1)
|
|
\param[out] none
|
|
\retval 16-bit CRC polynomial
|
|
*/
|
|
uint16_t spi_crc_polynomial_get(uint32_t spi_periph)
|
|
{
|
|
return ((uint16_t)SPI_CRCPOLY(spi_periph));
|
|
}
|
|
|
|
/*!
|
|
\brief turn on CRC function
|
|
\param[in] spi_periph: SPIx(x=0,1)
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void spi_crc_on(uint32_t spi_periph)
|
|
{
|
|
SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCEN;
|
|
}
|
|
|
|
/*!
|
|
\brief turn off CRC function
|
|
\param[in] spi_periph: SPIx(x=0,1)
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void spi_crc_off(uint32_t spi_periph)
|
|
{
|
|
SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_CRCEN);
|
|
}
|
|
|
|
/*!
|
|
\brief SPI next data is CRC value
|
|
\param[in] spi_periph: SPIx(x=0,1)
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void spi_crc_next(uint32_t spi_periph)
|
|
{
|
|
SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCNT;
|
|
}
|
|
|
|
/*!
|
|
\brief get SPI CRC send value or receive value
|
|
\param[in] spi_periph: SPIx(x=0,1)
|
|
\param[in] crc: SPI crc value
|
|
only one parameter can be selected which is shown as below:
|
|
\arg SPI_CRC_TX: get transmit crc value
|
|
\arg SPI_CRC_RX: get receive crc value
|
|
\param[out] none
|
|
\retval 16-bit CRC value
|
|
*/
|
|
uint16_t spi_crc_get(uint32_t spi_periph,uint8_t crc)
|
|
{
|
|
if(SPI_CRC_TX == crc){
|
|
return ((uint16_t)(SPI_TCRC(spi_periph)));
|
|
}else{
|
|
return ((uint16_t)(SPI_RCRC(spi_periph)));
|
|
}
|
|
}
|
|
|
|
/*!
|
|
\brief enable SPI TI mode
|
|
\param[in] spi_periph: SPIx(x=0,1)
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void spi_ti_mode_enable(uint32_t spi_periph)
|
|
{
|
|
SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TMOD;
|
|
}
|
|
|
|
/*!
|
|
\brief disable SPI TI mode
|
|
\param[in] spi_periph: SPIx(x=0,1)
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void spi_ti_mode_disable(uint32_t spi_periph)
|
|
{
|
|
SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TMOD);
|
|
}
|
|
|
|
/*!
|
|
\brief configure i2s full duplex mode
|
|
\param[in] i2s_add_periph: I2Sx_ADD(x=1)
|
|
\param[in] i2s_mode:
|
|
\arg I2S_MODE_SLAVETX : I2S slave transmit mode
|
|
\arg I2S_MODE_SLAVERX : I2S slave receive mode
|
|
\param[in] i2s_standard:
|
|
\arg I2S_STD_PHILLIPS : I2S phillips standard
|
|
\arg I2S_STD_MSB : I2S MSB standard
|
|
\arg I2S_STD_LSB : I2S LSB standard
|
|
\arg I2S_STD_PCMSHORT : I2S PCM short standard
|
|
\arg I2S_STD_PCMLONG : I2S PCM long standard
|
|
\param[in] i2s_ckpl:
|
|
\arg I2S_CKPL_LOW : I2S clock polarity low level
|
|
\arg I2S_CKPL_HIGH : I2S clock polarity high level
|
|
\param[in] i2s_frameformat:
|
|
\arg I2S_FRAMEFORMAT_DT16B_CH16B: I2S data length is 16 bit and channel length is 16 bit
|
|
\arg I2S_FRAMEFORMAT_DT16B_CH32B: I2S data length is 16 bit and channel length is 32 bit
|
|
\arg I2S_FRAMEFORMAT_DT24B_CH32B: I2S data length is 24 bit and channel length is 32 bit
|
|
\arg I2S_FRAMEFORMAT_DT32B_CH32B: I2S data length is 32 bit and channel length is 32 bit
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void i2s_full_duplex_mode_config(uint32_t i2s_add_periph, uint32_t i2s_mode, uint32_t i2s_standard,
|
|
uint32_t i2s_ckpl, uint32_t i2s_frameformat)
|
|
{
|
|
uint32_t reg = 0U, tmp = 0U;
|
|
|
|
reg = I2S_ADD_I2SCTL(i2s_add_periph);
|
|
reg &= I2S_FULL_DUPLEX_MASK;
|
|
|
|
/* get the mode of the extra I2S module I2Sx_ADD */
|
|
if((I2S_MODE_MASTERTX == i2s_mode) || (I2S_MODE_SLAVETX == i2s_mode)){
|
|
tmp = I2S_MODE_SLAVERX;
|
|
}else{
|
|
tmp = I2S_MODE_SLAVETX;
|
|
}
|
|
|
|
/* enable I2S mode */
|
|
reg |= (uint32_t)SPI_I2SCTL_I2SSEL;
|
|
/* select I2S mode */
|
|
reg |= (uint32_t)tmp;
|
|
/* select I2S standard */
|
|
reg |= (uint32_t)i2s_standard;
|
|
/* select I2S polarity */
|
|
reg |= (uint32_t)i2s_ckpl;
|
|
/* configure data frame format */
|
|
reg |= (uint32_t)i2s_frameformat;
|
|
|
|
/* write to SPI_I2SCTL register */
|
|
I2S_ADD_I2SCTL(i2s_add_periph) = (uint32_t)reg;
|
|
}
|
|
|
|
/*!
|
|
\brief enable quad wire SPI
|
|
\param[in] spi_periph: SPIx(only x=0)
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void qspi_enable(uint32_t spi_periph)
|
|
{
|
|
SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_QMOD;
|
|
}
|
|
|
|
/*!
|
|
\brief disable quad wire SPI
|
|
\param[in] spi_periph: SPIx(only x=0)
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void qspi_disable(uint32_t spi_periph)
|
|
{
|
|
SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_QMOD);
|
|
}
|
|
|
|
/*!
|
|
\brief enable quad wire SPI write
|
|
\param[in] spi_periph: SPIx(only x=0)
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void qspi_write_enable(uint32_t spi_periph)
|
|
{
|
|
SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_QRD);
|
|
}
|
|
|
|
/*!
|
|
\brief enable quad wire SPI read
|
|
\param[in] spi_periph: SPIx(only x=0)
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void qspi_read_enable(uint32_t spi_periph)
|
|
{
|
|
SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_QRD;
|
|
}
|
|
|
|
/*!
|
|
\brief enable SPI_IO2 and SPI_IO3 pin output
|
|
\param[in] spi_periph: SPIx(only x=0)
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void qspi_io23_output_enable(uint32_t spi_periph)
|
|
{
|
|
SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_IO23_DRV;
|
|
}
|
|
|
|
/*!
|
|
\brief disable SPI_IO2 and SPI_IO3 pin output
|
|
\param[in] spi_periph: SPIx(only x=0)
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void qspi_io23_output_disable(uint32_t spi_periph)
|
|
{
|
|
SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_IO23_DRV);
|
|
}
|
|
|
|
/*!
|
|
\brief enable SPI and I2S interrupt
|
|
\param[in] spi_periph: SPIx(x=0,1)
|
|
\param[in] interrupt: SPI/I2S interrupt
|
|
only one parameter can be selected which is shown as below:
|
|
\arg SPI_I2S_INT_TBE: transmit buffer empty interrupt
|
|
\arg SPI_I2S_INT_RBNE: receive buffer not empty interrupt
|
|
\arg SPI_I2S_INT_ERR: CRC error,configuration error,reception overrun error,
|
|
transmission underrun error and format error interrupt
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt)
|
|
{
|
|
switch(interrupt){
|
|
/* SPI/I2S transmit buffer empty interrupt */
|
|
case SPI_I2S_INT_TBE:
|
|
SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TBEIE;
|
|
break;
|
|
/* SPI/I2S receive buffer not empty interrupt */
|
|
case SPI_I2S_INT_RBNE:
|
|
SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_RBNEIE;
|
|
break;
|
|
/* SPI/I2S error */
|
|
case SPI_I2S_INT_ERR:
|
|
SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_ERRIE;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
/*!
|
|
\brief disable SPI and I2S interrupt
|
|
\param[in] spi_periph: SPIx(x=0,1)
|
|
\param[in] interrupt: SPI/I2S interrupt
|
|
only one parameter can be selected which is shown as below:
|
|
\arg SPI_I2S_INT_TBE: transmit buffer empty interrupt
|
|
\arg SPI_I2S_INT_RBNE: receive buffer not empty interrupt
|
|
\arg SPI_I2S_INT_ERR: CRC error,configuration error,reception overrun error,
|
|
transmission underrun error and format error interrupt
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt)
|
|
{
|
|
switch(interrupt){
|
|
/* SPI/I2S transmit buffer empty interrupt */
|
|
case SPI_I2S_INT_TBE:
|
|
SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TBEIE);
|
|
break;
|
|
/* SPI/I2S receive buffer not empty interrupt */
|
|
case SPI_I2S_INT_RBNE:
|
|
SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_RBNEIE);
|
|
break;
|
|
/* SPI/I2S error */
|
|
case SPI_I2S_INT_ERR:
|
|
SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_ERRIE);
|
|
break;
|
|
default :
|
|
break;
|
|
}
|
|
}
|
|
|
|
/*!
|
|
\brief get SPI and I2S interrupt flag status
|
|
\param[in] spi_periph: SPIx(x=0,1)
|
|
\param[in] interrupt: SPI/I2S interrupt flag status
|
|
only one parameter can be selected which is shown as below:
|
|
\arg SPI_I2S_INT_FLAG_TBE: transmit buffer empty interrupt flag
|
|
\arg SPI_I2S_INT_FLAG_RBNE: receive buffer not empty interrupt flag
|
|
\arg SPI_I2S_INT_FLAG_RXORERR: overrun interrupt flag
|
|
\arg SPI_INT_FLAG_CONFERR: config error interrupt flag
|
|
\arg SPI_INT_FLAG_CRCERR: CRC error interrupt flag
|
|
\arg I2S_INT_FLAG_TXURERR: underrun error interrupt flag
|
|
\arg SPI_I2S_INT_FLAG_FERR: format error interrupt flag
|
|
\param[out] none
|
|
\retval FlagStatus: SET or RESET
|
|
*/
|
|
FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt)
|
|
{
|
|
uint32_t reg1 = SPI_STAT(spi_periph);
|
|
uint32_t reg2 = SPI_CTL1(spi_periph);
|
|
|
|
switch(interrupt){
|
|
/* SPI/I2S transmit buffer empty interrupt */
|
|
case SPI_I2S_INT_FLAG_TBE:
|
|
reg1 = reg1 & SPI_STAT_TBE;
|
|
reg2 = reg2 & SPI_CTL1_TBEIE;
|
|
break;
|
|
/* SPI/I2S receive buffer not empty interrupt */
|
|
case SPI_I2S_INT_FLAG_RBNE:
|
|
reg1 = reg1 & SPI_STAT_RBNE;
|
|
reg2 = reg2 & SPI_CTL1_RBNEIE;
|
|
break;
|
|
/* SPI/I2S overrun interrupt */
|
|
case SPI_I2S_INT_FLAG_RXORERR:
|
|
reg1 = reg1 & SPI_STAT_RXORERR;
|
|
reg2 = reg2 & SPI_CTL1_ERRIE;
|
|
break;
|
|
/* SPI config error interrupt */
|
|
case SPI_INT_FLAG_CONFERR:
|
|
reg1 = reg1 & SPI_STAT_CONFERR;
|
|
reg2 = reg2 & SPI_CTL1_ERRIE;
|
|
break;
|
|
/* SPI CRC error interrupt */
|
|
case SPI_INT_FLAG_CRCERR:
|
|
reg1 = reg1 & SPI_STAT_CRCERR;
|
|
reg2 = reg2 & SPI_CTL1_ERRIE;
|
|
break;
|
|
/* I2S underrun error interrupt */
|
|
case I2S_INT_FLAG_TXURERR:
|
|
reg1 = reg1 & SPI_STAT_TXURERR;
|
|
reg2 = reg2 & SPI_CTL1_ERRIE;
|
|
break;
|
|
/* SPI/I2S format error interrupt */
|
|
case SPI_I2S_INT_FLAG_FERR:
|
|
reg1 = reg1 & SPI_STAT_FERR;
|
|
reg2 = reg2 & SPI_CTL1_ERRIE;
|
|
break;
|
|
default :
|
|
break;
|
|
}
|
|
/*get SPI/I2S interrupt flag status */
|
|
if(reg1 && reg2){
|
|
return SET;
|
|
}else{
|
|
return RESET;
|
|
}
|
|
}
|
|
|
|
/*!
|
|
\brief get SPI and I2S flag status
|
|
\param[in] spi_periph: SPIx(x=0,1)
|
|
\param[in] flag: SPI/I2S flag status
|
|
only one parameter can be selected which is shown as below:
|
|
\arg SPI_FLAG_TBE: transmit buffer empty flag
|
|
\arg SPI_FLAG_RBNE: receive buffer not empty flag
|
|
\arg SPI_FLAG_TRANS: transmit on-going flag
|
|
\arg SPI_FLAG_RXORERR: receive overrun error flag
|
|
\arg SPI_FLAG_CONFERR: mode config error flag
|
|
\arg SPI_FLAG_CRCERR: CRC error flag
|
|
\arg SPI_FLAG_FERR: format error flag
|
|
\arg I2S_FLAG_TBE: transmit buffer empty flag
|
|
\arg I2S_FLAG_RBNE: receive buffer not empty flag
|
|
\arg I2S_FLAG_TRANS: transmit on-going flag
|
|
\arg I2S_FLAG_RXORERR: overrun error flag
|
|
\arg I2S_FLAG_TXURERR: underrun error flag
|
|
\arg I2S_FLAG_CH: channel side flag
|
|
\arg I2S_FLAG_FERR: format error flag
|
|
\param[out] none
|
|
\retval FlagStatus: SET or RESET
|
|
*/
|
|
FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag)
|
|
{
|
|
if(SPI_STAT(spi_periph) & flag){
|
|
return SET;
|
|
}else{
|
|
return RESET;
|
|
}
|
|
}
|
|
|
|
/*!
|
|
\brief clear SPI CRC error flag status
|
|
\param[in] spi_periph: SPIx(x=0,1)
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void spi_crc_error_clear(uint32_t spi_periph)
|
|
{
|
|
SPI_STAT(spi_periph) &= (uint32_t)(~SPI_FLAG_CRCERR);
|
|
}
|