[修改] 增加freeRTOS

1. 版本FreeRTOSv202212.01，命名为kernel；

kernel/FreeRTOS/Demo/NEC_V850ES_IAR/LowLevelInit/LowLevelInit.c

@@ -0,0 +1,76 @@
+/*
+ * FreeRTOS V202212.01
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#include "FreeRTOS.h"
+
+/*-----------------------------------------------------------*/
+
+/* Called by the startup code to initialise the run time system. */
+unsigned char __low_level_init(void);
+
+/*-----------------------------------------------------------*/
+
+unsigned char __low_level_init(void)
+{
+unsigned char resetflag = RESF;
+unsigned char psval = 0;
+unsigned portBASE_TYPE i = 0;
+
+	/* Setup provided by NEC. */
+
+	portDISABLE_INTERRUPTS();         /* disable global interrupts */
+
+	PRCMD = 0x00;                     /* On-chip debug mode */
+	OCDM = 0x00;
+	VSWC = 0x00;                      /* set system wait control register */
+	WDTM2 = 0x00;                     /* WDT2 setting */
+	PLLON = 0;                        /* PLL stop mode */
+	psval = 0x0A | 0x00;
+	PRCMD = psval;                    /* set Command Register */
+	CKC = psval;                      /* set Clock Control Register */
+	PLLS = 0x03;
+	psval = 0x80;                     /* Set fXX and fCPU */
+	PRCMD = psval;
+	PCC = psval;
+	PLLON = 1;                        /* activate PLL */
+	for( i = 0; i <= 2000; i++ )      /* Wait for stabilisation */
+	{
+	portNOP();
+	}
+	while( LOCK )                     /* Wait for PLL frequency stabiliasation */
+	{
+	;
+	}
+	SELPLL = 1;                       /* Set PLL mode active */
+	RSTOP = 0;                        /* Set fR (enable) */
+	BGCE0 = 0;                        /* Set fBRG(disable) */
+	psval = 0x00;                     /* Stand-by setting */
+	PRCMD = psval;                    /* set Command Register */
+	PSC = psval;                      /* set Power Save Control Register */
+
+	return pdTRUE;
+}
+/*-----------------------------------------------------------*/