[修改] 增加freeRTOS

1. 版本FreeRTOSv202212.01，命名为kernel；

kernel/FreeRTOS/Demo/WizNET_DEMO_GCC_ARM7/TCPISR.c

@@ -0,0 +1,89 @@
+/*
+ * FreeRTOS V202212.01
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* Scheduler include files. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+
+/* Constants required for interrupt management. */
+#define tcpCLEAR_VIC_INTERRUPT	( 0 )
+#define tcpEINT0_VIC_CHANNEL_BIT	( ( unsigned long ) 0x4000 )
+
+/* EINT0 interrupt handler.  This processes interrupts from the WIZnet device. */
+void vEINT0_ISR_Wrapper( void ) __attribute__((naked));
+
+/* The handler that goes with the EINT0 wrapper. */
+void vEINT0_ISR_Handler( void );
+
+/* Variable is required for its address, but does not otherwise get used. */
+static long lDummyVariable;
+
+/*
+ * When the WIZnet device asserts an interrupt we send an (empty) message to
+ * the TCP task.  This wakes the task so the interrupt can be processed.  The
+ * source of the interrupt has to be ascertained by the TCP task as this
+ * requires an I2C transaction which cannot be performed from this ISR.
+ * Note this code predates the introduction of semaphores, a semaphore should
+ * be used in place of the empty queue message.
+ */
+void vEINT0_ISR_Handler( void )
+{
+extern QueueHandle_t xTCPISRQueue;
+portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;
+
+	/* Just wake the TCP task so it knows an ISR has occurred. */
+	xQueueSendFromISR( xTCPISRQueue, ( void * ) &lDummyVariable, &xHigherPriorityTaskWoken );
+
+	/* We cannot carry on processing interrupts until the TCP task has
+	processed this one - so for now interrupts are disabled.  The TCP task will
+	re-enable it. */
+	VICIntEnClear |= tcpEINT0_VIC_CHANNEL_BIT;
+
+	/* Clear the interrupt bit. */
+	VICVectAddr = tcpCLEAR_VIC_INTERRUPT;
+
+	if( xHigherPriorityTaskWoken )
+	{
+		portYIELD_FROM_ISR();
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vEINT0_ISR_Wrapper( void )
+{
+	/* Save the context of the interrupted task. */
+	portSAVE_CONTEXT();
+
+	/* The handler must be a separate function from the wrapper to
+	ensure the correct stack frame is set up. */
+	vEINT0_ISR_Handler();
+
+	/* Restore the context of whichever task is going to run next. */
+	portRESTORE_CONTEXT();
+}
+
+