[修改] 增加freeRTOS
1. 版本FreeRTOSv202212.01，命名为kernel；
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kernel/FreeRTOS/Demo/WizNET_DEMO_GCC_ARM7/i2c.c
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kernel/FreeRTOS/Demo/WizNET_DEMO_GCC_ARM7/i2c.c
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/*
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* FreeRTOS V202212.01
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* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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* the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* https://www.FreeRTOS.org
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* https://github.com/FreeRTOS
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*
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*/
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/* Standard includes. */
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#include <stdlib.h>
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/* Scheduler include files. */
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#include "FreeRTOS.h"
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#include "queue.h"
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#include "semphr.h"
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/* Application includes. */
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#include "i2c.h"
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/*-----------------------------------------------------------*/
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/* Constants to setup the microcontroller IO. */
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#define mainSDA_ENABLE ( ( unsigned long ) 0x0040 )
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#define mainSCL_ENABLE ( ( unsigned long ) 0x0010 )
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/* Bit definitions within the I2CONCLR register. */
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#define i2cSTA_BIT ( ( unsigned char ) 0x20 )
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#define i2cSI_BIT ( ( unsigned char ) 0x08 )
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#define i2cSTO_BIT ( ( unsigned char ) 0x10 )
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/* Constants required to setup the VIC. */
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#define i2cI2C_VIC_CHANNEL ( ( unsigned long ) 0x0009 )
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#define i2cI2C_VIC_CHANNEL_BIT ( ( unsigned long ) 0x0200 )
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#define i2cI2C_VIC_ENABLE ( ( unsigned long ) 0x0020 )
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/* Misc constants. */
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#define i2cNO_BLOCK ( ( TickType_t ) 0 )
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#define i2cQUEUE_LENGTH ( ( unsigned char ) 5 )
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#define i2cEXTRA_MESSAGES ( ( unsigned char ) 2 )
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#define i2cREAD_TX_LEN ( ( unsigned long ) 2 )
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#define i2cACTIVE_MASTER_MODE ( ( unsigned char ) 0x40 )
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#define i2cTIMERL ( 200 )
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#define i2cTIMERH ( 200 )
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/* Array of message definitions. See the header file for more information
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on the structure members. There are two more places in the queue than as
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defined by i2cQUEUE_LENGTH. This is to ensure that there is always a free
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message available - one can be in the process of being transmitted and one
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can be left free. */
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static xI2CMessage xTxMessages[ i2cQUEUE_LENGTH + i2cEXTRA_MESSAGES ];
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/* Function in the ARM part of the code used to create the queues. */
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extern void vI2CISRCreateQueues( unsigned portBASE_TYPE uxQueueLength, QueueHandle_t *pxTxMessages, unsigned long **ppulBusFree );
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/* Index to the next free message in the xTxMessages array. */
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unsigned long ulNextFreeMessage = ( unsigned long ) 0;
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/* Queue of messages that are waiting transmission. */
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static QueueHandle_t xMessagesForTx;
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/* Flag to indicate the state of the I2C ISR state machine. */
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static unsigned long *pulBusFree;
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/*-----------------------------------------------------------*/
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void i2cMessage( const unsigned char * const pucMessage, long lMessageLength, unsigned char ucSlaveAddress, unsigned short usBufferAddress, unsigned long ulDirection, SemaphoreHandle_t xMessageCompleteSemaphore, TickType_t xBlockTime )
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{
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extern volatile xI2CMessage *pxCurrentMessage;
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xI2CMessage *pxNextFreeMessage;
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signed portBASE_TYPE xReturn;
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portENTER_CRITICAL();
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{
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/* This message is guaranteed to be free as there are two more messages
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than spaces in the queue allowing for one message to be in process of
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being transmitted and one to be left free. */
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pxNextFreeMessage = &( xTxMessages[ ulNextFreeMessage ] );
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/* Fill the message with the data to be sent. */
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/* Pointer to the actual data. Only a pointer is stored (i.e. the
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actual data is not copied, so the data being pointed to must still
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be valid when the message eventually gets sent (it may be queued for
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a while. */
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pxNextFreeMessage->pucBuffer = ( unsigned char * ) pucMessage;
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/* This is the address of the I2C device we are going to transmit this
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message to. */
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pxNextFreeMessage->ucSlaveAddress = ucSlaveAddress | ( unsigned char ) ulDirection;
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/* A semaphore can be used to allow the I2C ISR to indicate that the
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message has been sent. This can be NULL if you don't want to wait for
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the message transmission to complete. */
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pxNextFreeMessage->xMessageCompleteSemaphore = xMessageCompleteSemaphore;
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/* How many bytes are to be sent? */
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pxNextFreeMessage->lMessageLength = lMessageLength;
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/* The address within the WIZnet device to which the data will be
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written. This could be the address of a register, or alternatively
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a location within the WIZnet Tx buffer. */
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pxNextFreeMessage->ucBufferAddressLowByte = ( unsigned char ) ( usBufferAddress & 0xff );
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/* Second byte of the address. */
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usBufferAddress >>= 8;
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pxNextFreeMessage->ucBufferAddressHighByte = ( unsigned char ) ( usBufferAddress & 0xff );
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/* Increment to the next message in the array - with a wrap around check. */
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ulNextFreeMessage++;
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if( ulNextFreeMessage >= ( i2cQUEUE_LENGTH + i2cEXTRA_MESSAGES ) )
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{
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ulNextFreeMessage = ( unsigned long ) 0;
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}
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/* Is the I2C interrupt in the middle of transmitting a message? */
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if( *pulBusFree == ( unsigned long ) pdTRUE )
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{
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/* No message is currently being sent or queued to be sent. We
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can start the ISR sending this message immediately. */
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pxCurrentMessage = pxNextFreeMessage;
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I2C_I2CONCLR = i2cSI_BIT;
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I2C_I2CONSET = i2cSTA_BIT;
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*pulBusFree = ( unsigned long ) pdFALSE;
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}
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else
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{
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/* The I2C interrupt routine is mid sending a message. Queue
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this message ready to be sent. */
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xReturn = xQueueSend( xMessagesForTx, &pxNextFreeMessage, xBlockTime );
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/* We may have blocked while trying to queue the message. If this
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was the case then the interrupt would have been enabled and we may
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now find that the I2C interrupt routine is no longer sending a
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message. */
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if( ( *pulBusFree == ( unsigned long ) pdTRUE ) && ( xReturn == pdPASS ) )
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{
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/* Get the next message in the queue (this should be the
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message we just posted) and start off the transmission
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again. */
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xQueueReceive( xMessagesForTx, &pxNextFreeMessage, i2cNO_BLOCK );
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pxCurrentMessage = pxNextFreeMessage;
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I2C_I2CONCLR = i2cSI_BIT;
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I2C_I2CONSET = i2cSTA_BIT;
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*pulBusFree = ( unsigned long ) pdFALSE;
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}
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}
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}
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portEXIT_CRITICAL();
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}
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/*-----------------------------------------------------------*/
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void i2cInit( void )
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{
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extern void ( vI2C_ISR_Wrapper )( void );
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/* Create the queue used to send messages to the ISR. */
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vI2CISRCreateQueues( i2cQUEUE_LENGTH, &xMessagesForTx, &pulBusFree );
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/* Configure the I2C hardware. */
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I2C_I2CONCLR = 0xff;
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PCB_PINSEL0 |= mainSDA_ENABLE;
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PCB_PINSEL0 |= mainSCL_ENABLE;
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I2C_I2SCLL = i2cTIMERL;
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I2C_I2SCLH = i2cTIMERH;
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I2C_I2CONSET = i2cACTIVE_MASTER_MODE;
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portENTER_CRITICAL();
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{
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/* Setup the VIC for the i2c interrupt. */
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VICIntSelect &= ~( i2cI2C_VIC_CHANNEL_BIT );
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VICIntEnable |= i2cI2C_VIC_CHANNEL_BIT;
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VICVectAddr2 = ( long ) vI2C_ISR_Wrapper;
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VICVectCntl2 = i2cI2C_VIC_CHANNEL | i2cI2C_VIC_ENABLE;
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}
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portEXIT_CRITICAL();
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}
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