[修改] 增加freeRTOS

1. 版本FreeRTOSv202212.01，命名为kernel；

kernel/FreeRTOS/Source/portable/ThirdParty/CDK/T-HEAD_CK802/port.c

@@ -0,0 +1,151 @@
+/*
+ * Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+/* Kernel includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+extern void vPortStartTask(void);
+
+/* Used to keep track of the number of nested calls to taskENTER_CRITICAL().  This
+will be set to 0 prior to the first task being started. */
+portLONG ulCriticalNesting = 0x9999UL;
+
+/* Used to record one tack want to swtich task after enter critical area, we need know it
+ * and implement task switch after exit critical area */
+portLONG pendsvflag = 0;
+
+StackType_t *pxPortInitialiseStack( StackType_t * pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+    StackType_t *stk  = NULL;
+
+    stk = pxTopOfStack;
+
+    *(--stk)  = (uint32_t)pxCode;            /* Entry Point                                         */
+    *(--stk)  = (uint32_t)0xE0000140L;       /* PSR                                                 */
+    *(--stk)  = (uint32_t)0xFFFFFFFEL;       /* R15 (LR) (init value will cause fault if ever used) */
+    *(--stk)  = (uint32_t)0x13131313L;       /* R13                                                 */
+    *(--stk)  = (uint32_t)0x12121212L;       /* R12                                                 */
+    *(--stk)  = (uint32_t)0x11111111L;       /* R11                                                 */
+    *(--stk)  = (uint32_t)0x10101010L;       /* R10                                                 */
+    *(--stk)  = (uint32_t)0x09090909L;       /* R9                                                  */
+    *(--stk)  = (uint32_t)0x08080808L;       /* R8                                                  */
+    *(--stk)  = (uint32_t)0x07070707L;       /* R7                                                  */
+    *(--stk)  = (uint32_t)0x06060606L;       /* R6                                                  */
+    *(--stk)  = (uint32_t)0x05050505L;       /* R5                                                  */
+    *(--stk)  = (uint32_t)0x04040404L;       /* R4                                                  */
+    *(--stk)  = (uint32_t)0x03030303L;       /* R3                                                  */
+    *(--stk)  = (uint32_t)0x02020202L;       /* R2                                                  */
+    *(--stk)  = (uint32_t)0x01010101L;       /* R1                                                  */
+    *(--stk)  = (uint32_t)pvParameters;      /* R0 : argument                                       */
+
+    return stk;
+}
+
+BaseType_t xPortStartScheduler( void )
+{
+    ulCriticalNesting = 0UL;
+
+    vPortStartTask();
+
+    return pdFALSE;
+}
+
+
+void vPortEndScheduler( void )
+{
+    /* Not implemented as there is nothing to return to. */
+}
+
+void vPortEnterCritical( void )
+{
+    portDISABLE_INTERRUPTS();
+    ulCriticalNesting ++;
+}
+
+void vPortExitCritical( void )
+{
+    if (ulCriticalNesting == 0) {
+        while(1);
+    }
+
+    ulCriticalNesting --;
+    if (ulCriticalNesting == 0)
+    {
+        portENABLE_INTERRUPTS();
+
+        if (pendsvflag)
+        {
+            pendsvflag = 0;
+            portYIELD();
+        }
+    }
+}
+
+#if configUSE_PREEMPTION == 0
+void xPortSysTickHandler( void )
+{
+    portLONG ulDummy;
+
+    ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();
+    xTaskIncrementTick();
+    portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );
+}
+
+#else
+void xPortSysTickHandler( void )
+{
+    portLONG ulDummy;
+
+    ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();
+    {
+        if (xTaskIncrementTick() != pdFALSE)
+        {
+            portYIELD_FROM_ISR(pdTRUE);
+        }
+    }
+    portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );
+}
+#endif
+
+void vPortYieldHandler( void )
+{
+    uint32_t ulSavedInterruptMask;
+
+    ulSavedInterruptMask = portSET_INTERRUPT_MASK_FROM_ISR();
+
+    vTaskSwitchContext();
+
+    portCLEAR_INTERRUPT_MASK_FROM_ISR( ulSavedInterruptMask );
+}
+
+__attribute__((weak)) void vApplicationStackOverflowHook( xTaskHandle *pxTask, signed portCHAR *pcTaskName )
+{
+    for(;;);
+}
+
+__attribute__((weak)) void vApplicationMallocFailedHook( void )
+{
+    for(;;);
+}

kernel/FreeRTOS/Source/portable/ThirdParty/CDK/T-HEAD_CK802/portasm.S

@@ -0,0 +1,127 @@
+/*
+ * Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+//#include <csi_config.h>
+
+/********************************************************************
+ * Functions: vPortStartTask
+ *
+ ********************************************************************/
+.global vPortStartTask
+.type   vPortStartTask, %function
+vPortStartTask:
+    psrclr   ie
+    lrw      r4, pxCurrentTCB
+    ld.w     r4, (r4)                // the current task stack pointer is the first member
+    ld.w     sp, (r4)
+
+    ldw      r0, (sp, 64)
+    mtcr     r0, epc
+    ldw      r0, (sp, 60)
+    mtcr     r0, epsr
+    ldw      r15, (sp, 56)
+    ldm      r0-r13, (sp)
+    addi     sp, 68
+    rte
+
+/********************************************************************
+ * Functions: vPortYield
+ *
+ ********************************************************************/
+.global vPortYield
+.type   vPortYield, %function
+vPortYield:
+    psrclr  ee
+    subi    sp, 68
+    stm     r0-r13, (sp)
+    stw     r15, (sp, 56)
+    mfcr    r0, psr
+    bseti   r0, 8
+    stw     r0, (sp, 60)
+    stw     r15, (sp, 64)
+
+    lrw     r2, pxCurrentTCB
+    ld.w    r3, (r2)
+    st.w    sp, (r3)
+
+    jbsr    vTaskSwitchContext
+    lrw     r4, pxCurrentTCB
+    ld.w    r4, (r4)
+    ld.w    sp, (r4)
+
+    ldw     r0, (sp, 64)
+    mtcr    r0, epc
+    ldw     r0, (sp, 60)
+    mtcr    r0, epsr
+    ldw     r15, (sp, 56)
+    ldm     r0-r13, (sp)
+    addi    sp, 68
+
+    rte
+
+/********************************************************************
+ * Functions: NOVIC_IRQ_Default_Handler
+ *
+ ********************************************************************/
+.global NOVIC_IRQ_Default_Handler
+.type   NOVIC_IRQ_Default_Handler, %function
+NOVIC_IRQ_Default_Handler:
+    psrset  ee
+    subi    sp, 68
+    stm     r0-r13, (sp)
+    stw     r15, (sp, 56)
+    mfcr    r0, epsr
+    stw     r0, (sp, 60)
+    mfcr    r0, epc
+    stw     r0, (sp, 64)
+	
+    lrw     r7, pxCurrentTCB
+    ldw     r7, (r7)
+    stw     sp, (r7)
+
+    lrw     sp, g_top_irqstack
+
+    lrw     r1, g_irqvector
+    mfcr    r0, psr
+    lsri    r0, 16
+    sextb   r0
+    subi    r0, 32
+    lsli    r0, 2
+    add     r1, r0
+    ldw     r1, (r1)
+    lsri    r0, 2
+    jsr     r1
+
+    lrw     r7, pxCurrentTCB
+    ldw     r7, (r7)
+    ldw     sp, (r7)
+
+    ldw     r0, (sp, 64)
+    mtcr    r0, epc
+    ldw     r0, (sp, 60)
+    mtcr    r0, epsr
+    ldm     r0-r13, (sp)
+    ldw     r15, (sp, 56)
+    addi    sp, 68
+    rte

kernel/FreeRTOS/Source/portable/ThirdParty/CDK/T-HEAD_CK802/portmacro.h

@@ -0,0 +1,160 @@
+/*
+ * Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#include <stdlib.h>
+#include <stdint.h>
+#include <csi_core.h>
+
+extern void vPortYield(void);
+#ifdef __cplusplus
+class vPortYield;
+extern "C" {
+#endif
+
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR        char
+#define portFLOAT       float
+#define portDOUBLE      double
+#define portLONG        long
+#define portSHORT       short
+#define portSTACK_TYPE  uint32_t
+#define portBASE_TYPE   long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+typedef void (*portvectorfunc)(void);
+
+#if( configUSE_16_BIT_TICKS == 1 )
+    typedef uint16_t  TickType_t;
+    #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+    typedef uint32_t  TickType_t;
+    #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT          8
+#define portSTACK_GROWTH            -1
+#define portMS_PERIOD_TICK          10
+#define portTICK_PERIOD_MS	        ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+
+
+static inline void vPortEnableInterrupt( void )
+{
+    __enable_irq();
+}
+
+static inline void vPortDisableInterrupt( void )
+{
+    __disable_irq();
+}
+
+static inline portLONG GetCurrentPSR (void)
+{
+    return __get_PSR();
+}
+
+static inline portLONG SaveLocalPSR (void)
+{
+    portLONG flags = __get_PSR();
+    __disable_irq();
+    return flags;
+}
+
+static inline void RestoreLocalPSR (portLONG newMask)
+{
+    __asm__ __volatile__(
+    "mtcr   %0, psr \n"
+    :
+    :"r" (newMask)
+    :"memory"
+    );
+}
+
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+extern __attribute__((naked)) void cpu_yeild(void);
+
+#define portDISABLE_INTERRUPTS()                vPortDisableInterrupt()
+#define portENABLE_INTERRUPTS()                 vPortEnableInterrupt()
+#define portENTER_CRITICAL()                    vPortEnterCritical()
+#define portEXIT_CRITICAL()                     vPortExitCritical()
+#define portSET_INTERRUPT_MASK_FROM_ISR()       SaveLocalPSR()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(a)    RestoreLocalPSR(a)
+
+#define portNOP()                   asm("nop")
+
+extern portLONG ulCriticalNesting;
+extern portLONG pendsvflag;
+
+#define portYIELD()                 if (ulCriticalNesting == 0) \
+                                    {   \
+                                        vPortYield();   \
+                                    }   \
+                                    else \
+                                    {   \
+                                        pendsvflag = 1; \
+                                    }   \
+                                    portNOP();portNOP()
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) __attribute__((noreturn))
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+#define portEND_SWITCHING_ISR( xSwitchRequired )    do {    \
+                                                            if( xSwitchRequired != pdFALSE )    \
+                                                            {   \
+                                                                portYIELD();    \
+                                                            }   \
+                                                    }while(0)
+
+#define portYIELD_FROM_ISR( a )     vTaskSwitchContext()
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+

kernel/FreeRTOS/Source/portable/ThirdParty/Community-Supported-Ports/.github/CODE_OF_CONDUCT.md

@@ -0,0 +1,4 @@
+## Code of Conduct
+This project has adopted the [Amazon Open Source Code of Conduct](https://aws.github.io/code-of-conduct).
+For more information see the [Code of Conduct FAQ](https://aws.github.io/code-of-conduct-faq) or contact
+opensource-codeofconduct@amazon.com with any additional questions or comments.

kernel/FreeRTOS/Source/portable/ThirdParty/Community-Supported-Ports/.github/CONTRIBUTING.md

@@ -0,0 +1,70 @@
+# Contribution guidelines
+
+Thank you for your interest in contributing to our project. Whether it's a bug report, new feature, code, or
+documentation, we welcome our community to be involved in this project.
+
+Please read through this document before submitting any issues or pull requests to ensure we are able to help you and all members of the community as effectively as possible.
+
+## Code of conduct
+This project has adopted the [Amazon Open Source Code of Conduct](https://aws.github.io/code-of-conduct).
+For more information see the [Code of Conduct FAQ](https://aws.github.io/code-of-conduct-faq) or contact
+opensource-codeofconduct@amazon.com with any additional questions or comments.
+
+
+## Security issue notifications
+If you discover a potential security issue in this project we ask that you notify AWS/Amazon Security via our [vulnerability reporting page](http://aws.amazon.com/security/vulnerability-reporting/). Please do **not** create a public github issue.
+
+
+## Submitting a bugs/feature request
+Have a bug to report or feature to request? Follow these steps:
+1. Search on the [FreeRTOS Community Support Forums](https://forums.freertos.org/) and [GitHub issue tracker](https://github.com/FreeRTOS/FreeRTOS/issues?utf8=%E2%9C%93&q=is%3Aissue) to be sure this hasn't been already reported or discussed.
+2. If your search turns up empty, create a new topic in the [forums](https://forums.freertos.org/) and work with the community to help clarify issues or refine the idea. Include as many of the details listed below.
+3. Once the community has had time to discuss and digest, we welcome you to create an [issue](https://github.com/FreeRTOS/FreeRTOS/issues) to report bugs or suggest features.
+
+When creating a new topic on the forums or filing an issue, please include as many relevant details as possible. Examples include:
+
+* A clear description of the situation — what you observe, what you expect, and your view on how the two differ.
+* A reproducible test case or sequence of steps.
+* The version of our code being used.
+* Any modifications you've made relevant to the bug.
+* Details of your environment or deployment. Highlight anything unusual.
+
+
+## Contributing via pull request
+Contributions via pull requests are much appreciated. Before sending us a pull request, please ensure that:
+
+1. You are working against the latest source on the *master* branch.
+2. You check existing open, and recently merged, pull requests to make sure someone else hasn't addressed the problem already.
+3. You open an issue to discuss any significant work - we would hate for your time to be wasted.
+
+To send us a pull request, please:
+
+1. Fork the repository.
+2. Modify the source; focus on the specific change you are contributing. If you also reformat all the code, it will be hard for us to focus on your change.
+3. Follow the [coding style guide](https://www.freertos.org/FreeRTOS-Coding-Standard-and-Style-Guide.html).
+4. Commit to your fork using clear commit messages.
+5. Send us a pull request, answering any default questions in the pull request interface.
+   NOTE: Please make sure the default option (Allow edits from maintainers) is left checked.
+6. Pay attention to any automated CI failures reported in the pull request, and stay involved in the conversation.
+
+GitHub provides additional document on [forking a repository](https://help.github.com/articles/fork-a-repo/) and
+[creating a pull request](https://help.github.com/articles/creating-a-pull-request/).
+
+## Coding style
+* Please ensure that your code complies to the [FreeRTOS coding style guidelines](https://www.freertos.org/FreeRTOS-Coding-Standard-and-Style-Guide.html).
+
+
+## Getting your pull request merged
+All pull requests must be approved by our review team before it can be merged in. We appreciate your patience while pull requests are reviewed. The time it takes to review will depend on complexity and consideration of wider implications.
+
+
+## Finding contributions to work on
+Looking at the existing issues is a great way to find something to contribute on. As our projects, by default, use the default GitHub issue labels (enhancement/bug/duplicate/help wanted/invalid/question/wontfix), tackling open 'help wanted' issues is a great place to start.
+
+
+## Licensing
+The FreeRTOS kernel is released under the MIT open source license, the text of which can be found [here](https://github.com/FreeRTOS/FreeRTOS/blob/master/FreeRTOS/License/license.txt)
+
+Additional license files can be found in the folders containing any supplementary libraries licensed by their respective copyright owners where applicable.
+
+We may ask you to sign a [Contributor License Agreement (CLA)](http://en.wikipedia.org/wiki/Contributor_License_Agreement) for larger changes.

kernel/FreeRTOS/Source/portable/ThirdParty/Community-Supported-Ports/.github/SECURITY.md

@@ -0,0 +1,5 @@
+## Reporting a Vulnerability
+
+If you discover a potential security issue in this project we ask that you notify AWS/Amazon Security
+via our [vulnerability reporting page](http://aws.amazon.com/security/vulnerability-reporting/) or directly via email to aws-security@amazon.com.
+Please do **not** create a public github issue.

kernel/FreeRTOS/Source/portable/ThirdParty/Community-Supported-Ports/.github/pull_request_template.md

@@ -0,0 +1,16 @@
+<!--- Title -->
+
+Description
+-----------
+<!--- Describe your changes in detail. -->
+
+Test Steps
+-----------
+<!-- Describe the steps to reproduce. -->
+
+Related Issue
+-----------
+<!-- If any, please provide issue ID. -->
+
+
+By submitting this pull request, I confirm that you can use, modify, copy, and redistribute this contribution, under the terms of your choice.

kernel/FreeRTOS/Source/portable/ThirdParty/Community-Supported-Ports/CCS/C2000_C28x/README.md

@@ -0,0 +1,19 @@
+
+OVERVIEW
+
+This directory contains FreeRTOS port for Texas Instruments C28x based microcontrollers.
+
+The standard demo project to test this port is added at following location:
+FreeRTOS-Community-Supported-Demos\C2000_F2838x_C28x_CCS\freertos_ex1_c28x_port_val
+
+This port is distributed under MIT open source license.
+
+KNOWN ISSUES:
+Support for "fpu64" is not added yet to the port. The examples should specify "fpu32" as option for floating point.
+
+TOOL CHAIN SUPPORT:
+Code Composer Studio™ IDE (CCS) v11.1.0 or newer
+C2000 Compiler v20.2.1.LTS or newer
+C2000Ware_3_01_00_00 or newer
+FreeRTOSv202112.00
+

kernel/FreeRTOS/Source/portable/ThirdParty/Community-Supported-Ports/CCS/C2000_C28x/port.c

@@ -0,0 +1,172 @@
+//-------------------------------------------------------------------------------------------------
+// Author: Ivan Zaitsev, ivan.zaitsev@gmail.com
+//
+// This file follows the FreeRTOS distribution license.
+//
+// FreeRTOS is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License (version 2) as published by the
+// Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
+//
+// ***************************************************************************
+// >>!   NOTE: The modification to the GPL is included to allow you to     !<<
+// >>!   distribute a combined work that includes FreeRTOS without being   !<<
+// >>!   obliged to provide the source code for proprietary components     !<<
+// >>!   outside of the FreeRTOS kernel.                                   !<<
+// ***************************************************************************
+//
+// FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+// FOR A PARTICULAR PURPOSE.  Full license text is available on the following
+// link: http://www.freertos.org/a00114.html
+//-------------------------------------------------------------------------------------------------
+
+//-------------------------------------------------------------------------------------------------
+// Scheduler includes.
+//-------------------------------------------------------------------------------------------------
+#include "FreeRTOS.h"
+#include "task.h"
+
+//-------------------------------------------------------------------------------------------------
+// Implementation of functions defined in portable.h for the C28x port.
+//-------------------------------------------------------------------------------------------------
+
+// Constants required for hardware setup.
+#define portINITIAL_CRITICAL_NESTING  ( ( uint16_t ) 10 )
+#define portFLAGS_INT_ENABLED         ( ( StackType_t ) 0x08 )
+#if defined(__TMS320C28XX_FPU32__)
+# define AUX_REGISTERS_TO_SAVE        19 // XAR + FPU registers
+# define XAR4_REGISTER_POSITION       6  // XAR4 position in AUX registers array
+# define STF_REGISTER_POSITION        10 // STF position in AUX registers array
+#else
+# define AUX_REGISTERS_TO_SAVE        9  // XAR registers only
+# define XAR4_REGISTER_POSITION       5  // XAR4 position in AUX registers array
+#endif
+
+extern uint32_t getSTF( void );
+extern void vApplicationSetupTimerInterrupt( void );
+
+// Each task maintains a count of the critical section nesting depth.  Each
+// time a critical section is entered the count is incremented.  Each time a
+// critical section is exited the count is decremented - with interrupts only
+// being re-enabled if the count is zero.
+//
+// ulCriticalNesting will get set to zero when the scheduler starts, but must
+// not be initialised to zero as this will cause problems during the startup
+// sequence.
+// ulCriticalNesting should be 32 bit value to keep stack alignment unchanged.
+volatile uint32_t ulCriticalNesting = portINITIAL_CRITICAL_NESTING;
+volatile uint16_t bYield = 0;
+volatile uint16_t bPreemptive = 0;
+
+//-------------------------------------------------------------------------------------------------
+// Initialise the stack of a task to look exactly as if
+// timer interrupt was executed.
+//-------------------------------------------------------------------------------------------------
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+  uint16_t i;
+  uint16_t base = 0;
+
+  pxTopOfStack[base++]  = 0x0080;  // ST0. PSM = 0(No shift)
+  pxTopOfStack[base++]  = 0x0000;  // T
+  pxTopOfStack[base++]  = 0x0000;  // AL
+  pxTopOfStack[base++]  = 0x0000;  // AH
+  pxTopOfStack[base++]  = 0xFFFF;  // PL
+  pxTopOfStack[base++]  = 0xFFFF;  // PH
+  pxTopOfStack[base++]  = 0xFFFF;  // AR0
+  pxTopOfStack[base++]  = 0xFFFF;  // AR1
+  pxTopOfStack[base++]  = 0x8A08;  // ST1
+  pxTopOfStack[base++]  = 0x0000;  // DP
+  pxTopOfStack[base++] = 0x0000;  // IER
+  pxTopOfStack[base++] = 0x0000;  // DBGSTAT
+  pxTopOfStack[base++] = ((uint32_t)pxCode) & 0xFFFFU;       // PCL
+  pxTopOfStack[base++] = ((uint32_t)pxCode >> 16) & 0x00FFU; // PCH
+  pxTopOfStack[base++] = 0xAAAA;  // Alignment
+  pxTopOfStack[base++] = 0xBBBB;  // Alignment
+
+  // Fill the rest of the registers with dummy values.
+  for(i = 0; i < (2 * AUX_REGISTERS_TO_SAVE); i++)
+  {
+    uint16_t low  = 0x0000;
+    uint16_t high = 0x0000;
+
+    if(i == (2 * XAR4_REGISTER_POSITION))
+    {
+      low  = ((uint32_t)pvParameters) & 0xFFFFU;
+      high = ((uint32_t)pvParameters >> 16) & 0xFFFFU;
+    }
+
+#if defined(__TMS320C28XX_FPU32__)
+    if(i == (2 * STF_REGISTER_POSITION))
+    {
+      uint32_t stf = getSTF();
+
+      low  = stf & 0xFFFFU;
+      high = (stf >> 16) & 0xFFFFU;
+    }
+#endif
+
+    pxTopOfStack[base + i] = low;
+    i++;
+    pxTopOfStack[base + i] = high;
+  }
+
+  base += i;
+
+  // Reserve place for ST1 which will be used in context switch
+  // to set correct SPA bit ASAP.
+  pxTopOfStack[base++] = 0x8A18;  // ST1 with SPA bit set
+  pxTopOfStack[base++] = 0x0000;  // DP
+  pxTopOfStack[base++] = 0x0000;  // placeholder for 32 bit ulCriticalNesting
+  pxTopOfStack[base++] = 0x0000;
+
+  // Return a pointer to the top of the stack we have generated so this can
+  // be stored in the task control block for the task.
+  return pxTopOfStack + base;
+}
+
+//-------------------------------------------------------------------------------------------------
+void vPortEndScheduler( void )
+{
+  // It is unlikely that the TMS320 port will get stopped.
+  // If required simply disable the tick interrupt here.
+}
+
+//-------------------------------------------------------------------------------------------------
+// See header file for description.
+//-------------------------------------------------------------------------------------------------
+BaseType_t xPortStartScheduler(void)
+{
+  vApplicationSetupTimerInterrupt();
+
+  ulCriticalNesting = 0;
+
+#if(configUSE_PREEMPTION == 1)
+  bPreemptive = 1;
+#else
+  bPreemptive = 0;
+#endif
+
+  portENABLE_INTERRUPTS();
+  portRESTORE_FIRST_CONTEXT();
+
+  // Should not get here!
+  return pdFAIL;
+}
+
+//-------------------------------------------------------------------------------------------------
+void vPortEnterCritical( void )
+{
+  portDISABLE_INTERRUPTS();
+  ulCriticalNesting++;
+}
+
+//-------------------------------------------------------------------------------------------------
+void vPortExitCritical( void )
+{
+  ulCriticalNesting--;
+  if( ulCriticalNesting == 0 )
+  {
+    portENABLE_INTERRUPTS();
+  }
+}

kernel/FreeRTOS/Source/portable/ThirdParty/Community-Supported-Ports/CCS/C2000_C28x/portasm.asm

@@ -0,0 +1,316 @@
+;-------------------------------------------------------------------------------------------------
+; Author: Ivan Zaitsev, ivan.zaitsev@gmail.com
+;
+; This file follows the FreeRTOS distribution license.
+;
+; FreeRTOS is free software; you can redistribute it and/or modify it under
+; the terms of the GNU General Public License (version 2) as published by the
+; Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
+;
+; ***************************************************************************
+; >>!   NOTE: The modification to the GPL is included to allow you to     !<<
+; >>!   distribute a combined work that includes FreeRTOS without being   !<<
+; >>!   obliged to provide the source code for proprietary components     !<<
+; >>!   outside of the FreeRTOS kernel.                                   !<<
+; ***************************************************************************
+;
+; FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+; WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+; FOR A PARTICULAR PURPOSE.  Full license text is available on the following
+; link: http://www.freertos.org/a00114.html
+;-------------------------------------------------------------------------------------------------
+
+  .if __TI_EABI__                      
+  .asg    pxCurrentTCB, _pxCurrentTCB
+  .asg    bYield, _bYield
+  .asg    bPreemptive, _bPreemptive
+  .asg    ulCriticalNesting, _ulCriticalNesting
+  .asg    xTaskIncrementTick, _xTaskIncrementTick
+  .asg    vTaskSwitchContext, _vTaskSwitchContext
+  .asg    portTICK_ISR, _portTICK_ISR
+  .asg    portRESTORE_FIRST_CONTEXT, _portRESTORE_FIRST_CONTEXT
+  .asg    getSTF, _getSTF
+  .endif
+
+  .ref _pxCurrentTCB
+  .ref _bYield
+  .ref _bPreemptive
+  .ref _ulCriticalNesting
+  .ref _xTaskIncrementTick
+  .ref _vTaskSwitchContext
+
+  .def _portTICK_ISR
+  .def _portRESTORE_FIRST_CONTEXT
+
+  .if .TMS320C2800_FPU32 = 1
+
+  .def _getSTF
+
+_getSTF:
+  MOV32   *SP++, STF
+  POP     ACC
+  LRETR
+
+_portRESTORE_FIRST_CONTEXT:
+; Restore stack pointer from new task control block.
+  MOVL    XAR0, #_pxCurrentTCB
+  MOVL    XAR0, *XAR0
+  MOVL    XAR0, *XAR0
+  MOV     @SP, AR0
+
+; Restore XAR4 and RPC from saved task stack.
+; and return to main task function.
+; SP should be set to stack start plus 2 before LRETR.
+  SUBB   SP, #28
+  POP    XAR4
+  SUBB   SP, #14
+  POP    RPC
+  SUBB   SP, #10
+  LRETR
+
+_portTICK_ISR:
+; Save context
+  ASP
+  PUSH    RB
+  PUSH    AR1H:AR0H
+  PUSH    RPC
+  MOVL    *SP++, XT
+  MOVL    *SP++, XAR2
+  MOVL    *SP++, XAR3
+  MOVL    *SP++, XAR4
+  MOVL    *SP++, XAR5
+  MOVL    *SP++, XAR6
+  MOVL    *SP++, XAR7
+  MOV32   *SP++, STF
+  MOV32   *SP++, R0H
+  MOV32   *SP++, R1H
+  MOV32   *SP++, R2H
+  MOV32   *SP++, R3H
+  MOV32   *SP++, R4H
+  MOV32   *SP++, R5H
+  MOV32   *SP++, R6H
+  MOV32   *SP++, R7H
+  PUSH    DP:ST1
+
+; Save critical section nesting counter
+  MOVL    XAR0, #_ulCriticalNesting
+  MOVL    ACC, *XAR0
+  PUSH    ACC
+
+; Save stack pointer in the task control block.
+  MOVL    XAR0, #_pxCurrentTCB
+  MOVL    XAR0, *XAR0
+  MOVL    XAR6, #0     ;set to 0 XAR6 before move the new value of pxTopOfStack
+  MOV     AR6, @SP
+  MOVL    *XAR0, XAR6
+
+; Save IER on stack to avoid corruption.
+; Depending on stack alignment bit IER can be found in two locations.
+  PUSH    ST1
+  POP     AL
+  TBIT    AL, #4
+  SB      SPA_BIT_SET, TC
+  MOV     AR7, *-SP[46]
+  SB      SAVE_IER, UNC
+SPA_BIT_SET:
+  MOV     AR7, *-SP[48]
+SAVE_IER:
+  MOVL    *SP++, XAR7
+
+; Increment tick counter if timer tick is executed.
+; Don't increment if explicitly yielded.
+  MOVL    XAR0, #_bYield
+  MOV     ACC, *XAR0
+  SB      RESET_YIELD_FLAG, NEQ
+  LCR     _xTaskIncrementTick
+
+RESET_YIELD_FLAG:
+; Save bYield in AR1 and clear it in memory.
+  MOV     AR1, ACC
+  MOV     ACC, #0
+  MOV     *XAR0, ACC
+
+; Do context switch if bYield=1 or bPreemptive=1
+  MOVL    XAR0, #_bPreemptive
+  MOV     ACC, *XAR0
+  CMPB    AL, #0x1
+  SB      CONTEXT_SWITCH, EQ
+  MOV     ACC, AR1
+  CMPB    AL, #0x1
+  SB      SKIP_CONTEXT_SWITCH, NEQ
+
+CONTEXT_SWITCH:
+  LCR     _vTaskSwitchContext
+
+SKIP_CONTEXT_SWITCH:
+; Restore IER value from stack.
+  MOVL    XAR7, *--SP
+
+; Restore stack pointer from new task control block.
+  MOVL    XAR0, #_pxCurrentTCB
+  MOVL    XAR0, *XAR0
+  MOVL    XAR0, *XAR0
+  MOV     @SP, AR0
+
+; Restore critical section nesting counter
+  MOVL    XAR0, #_ulCriticalNesting
+  POP     ACC
+  MOVL    *XAR0, ACC
+
+; Update IER value in target context.
+; Depending on stack alignment bit IER can be found in two locations.
+  POP     DP:ST1
+  PUSH    ST1
+  POP     AL
+  TBIT    AL, #4
+  SB      SPA_BIT_SET_RESTORE, TC
+  MOV     *-SP[42], AR7
+  SB      RESTORE_CONTEXT, UNC
+SPA_BIT_SET_RESTORE:
+  MOV     *-SP[44], AR7
+
+RESTORE_CONTEXT:
+  MOV32   R7H, *--SP
+  MOV32   R6H, *--SP
+  MOV32   R5H, *--SP
+  MOV32   R4H, *--SP
+  MOV32   R3H, *--SP
+  MOV32   R2H, *--SP
+  MOV32   R1H, *--SP
+  MOV32   R0H, *--SP
+  MOV32   STF, *--SP
+  MOVL    XAR7, *--SP
+  MOVL    XAR6, *--SP
+  MOVL    XAR5, *--SP
+  MOVL    XAR4, *--SP
+  MOVL    XAR3, *--SP
+  MOVL    XAR2, *--SP
+  MOVL    XT, *--SP
+  POP     RPC
+  POP     AR1H:AR0H
+  POP     RB
+  NASP
+  IRET
+
+  .else
+
+_portRESTORE_FIRST_CONTEXT:
+; Restore stack pointer from new task control block.
+  MOVL    XAR0, #_pxCurrentTCB
+  MOVL    XAR0, *XAR0
+  MOVL    XAR0, *XAR0
+  MOV     @SP, AR0
+
+; Restore XAR4 and RPC from saved task stack.
+; and return to main task function.
+; SP should be set to stack start plus 2 before LRETR.
+  SUBB   SP, #10
+  POP    XAR4
+  SUBB   SP, #12
+  POP    RPC
+  SUBB   SP, #10
+  LRETR
+
+_portTICK_ISR:
+; Save context
+  ASP
+  PUSH    AR1H:AR0H
+  PUSH    RPC
+  MOVL    *SP++, XT
+  MOVL    *SP++, XAR2
+  MOVL    *SP++, XAR3
+  MOVL    *SP++, XAR4
+  MOVL    *SP++, XAR5
+  MOVL    *SP++, XAR6
+  MOVL    *SP++, XAR7
+  PUSH    DP:ST1
+
+; Save critical section nesting counter
+  MOVL    XAR0, #_ulCriticalNesting
+  MOVL    ACC, *XAR0
+  PUSH    ACC
+
+; Save stack pointer in the task control block.
+  MOVL    XAR0, #_pxCurrentTCB
+  MOVL    XAR0, *XAR0
+  MOVL    XAR6, #0     ;set to 0 XAR6 before move the new value of pxTopOfStack
+  MOV     AR6, @SP
+  MOVL    *XAR0, XAR6
+
+; Save IER on stack to avoid corruption.
+  PUSH    ST1
+  POP     AL
+  TBIT    AL, #4
+  SB      SPA_BIT_SET, TC
+  MOV     AR7, *-SP[26]
+  SB      SAVE_IER, UNC
+SPA_BIT_SET:
+  MOV     AR7, *-SP[28]
+SAVE_IER:
+  MOVL    *SP++, XAR7
+
+; Increment tick counter if timer tick is executed.
+; Don't increment if explicitly yielded.
+  MOVL    XAR0, #_bYield
+  MOV     ACC, *XAR0
+  SB      RESET_YIELD_FLAG, NEQ
+  LCR     _xTaskIncrementTick
+
+RESET_YIELD_FLAG:
+; Save bYield in AR1 and clear it in memory.
+  MOV     AR1, ACC
+  MOV     ACC, #0
+  MOV     *XAR0, ACC
+
+; Do context switch if bYield=1 or bPreemptive=1
+  MOVL    XAR0, #_bPreemptive
+  MOV     ACC, *XAR0
+  CMPB    AL, #0x1
+  SB      CONTEXT_SWITCH, EQ
+  MOV     ACC, AR1
+  CMPB    AL, #0x1
+  SB      SKIP_CONTEXT_SWITCH, NEQ
+
+CONTEXT_SWITCH:
+  LCR     _vTaskSwitchContext
+
+SKIP_CONTEXT_SWITCH:
+; Restore IER value from stack.
+  MOVL    XAR7, *--SP
+
+; Restore stack pointer from new task control block.
+  MOVL    XAR0, #_pxCurrentTCB
+  MOVL    XAR0, *XAR0
+  MOVL    XAR0, *XAR0
+  MOV     @SP, AR0
+
+; Restore critical section nesting counter
+  MOVL    XAR0, #_ulCriticalNesting
+  POP     ACC
+  MOVL    *XAR0, ACC
+
+; Update IER value in target context.
+  POP     DP:ST1
+  PUSH    ST1
+  POP     AL
+  TBIT    AL, #4
+  SB      SPA_BIT_SET_RESTORE, TC
+  MOV     *-SP[22], AR7
+  SB      RESTORE_CONTEXT, UNC
+SPA_BIT_SET_RESTORE:
+  MOV     *-SP[24], AR7
+
+RESTORE_CONTEXT:
+  MOVL    XAR7, *--SP
+  MOVL    XAR6, *--SP
+  MOVL    XAR5, *--SP
+  MOVL    XAR4, *--SP
+  MOVL    XAR3, *--SP
+  MOVL    XAR2, *--SP
+  MOVL    XT, *--SP
+  POP     RPC
+  POP     AR1H:AR0H
+  NASP
+  IRET
+
+  .endif

kernel/FreeRTOS/Source/portable/ThirdParty/Community-Supported-Ports/CCS/C2000_C28x/portmacro.h

@@ -0,0 +1,103 @@
+//-------------------------------------------------------------------------------------------------
+// Author: Ivan Zaitsev, ivan.zaitsev@gmail.com
+//
+// This file follows the FreeRTOS distribution license.
+//
+// FreeRTOS is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License (version 2) as published by the
+// Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
+//
+// ***************************************************************************
+// >>!   NOTE: The modification to the GPL is included to allow you to     !<<
+// >>!   distribute a combined work that includes FreeRTOS without being   !<<
+// >>!   obliged to provide the source code for proprietary components     !<<
+// >>!   outside of the FreeRTOS kernel.                                   !<<
+// ***************************************************************************
+//
+// FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+// FOR A PARTICULAR PURPOSE.  Full license text is available on the following
+// link: http://www.freertos.org/a00114.html
+//-------------------------------------------------------------------------------------------------
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+//-------------------------------------------------------------------------------------------------
+// Port specific definitions.
+//
+// The settings in this file configure FreeRTOS correctly for the
+// given hardware and compiler.
+//
+// These settings should not be altered.
+//-------------------------------------------------------------------------------------------------
+
+//-------------------------------------------------------------------------------------------------
+// Hardware includes
+//-------------------------------------------------------------------------------------------------
+
+//-------------------------------------------------------------------------------------------------
+// Type definitions.
+//-------------------------------------------------------------------------------------------------
+#define portCHAR        uint16_t
+#define portFLOAT       float
+#define portDOUBLE      double
+#define portLONG        uint32_t
+#define portSHORT       uint16_t
+#define portBASE_TYPE   uint16_t
+#define uint8_t         uint16_t
+#define int8_t          int16_t
+#define portSTACK_TYPE  uint16_t
+
+typedef portSTACK_TYPE StackType_t;
+typedef int16_t        BaseType_t;
+typedef uint16_t       UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+  typedef uint16_t TickType_t;
+  #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+  typedef uint32_t TickType_t;
+  #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+
+//-------------------------------------------------------------------------------------------------
+// Interrupt control macros.
+//-------------------------------------------------------------------------------------------------
+#define portDISABLE_INTERRUPTS()  __asm(" setc INTM")
+#define portENABLE_INTERRUPTS()   __asm(" clrc INTM")
+
+//-------------------------------------------------------------------------------------------------
+// Critical section control macros.
+//-------------------------------------------------------------------------------------------------
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+#define portENTER_CRITICAL()  vPortEnterCritical()
+#define portEXIT_CRITICAL()   vPortExitCritical()
+
+//-------------------------------------------------------------------------------------------------
+// Task utilities.
+//-------------------------------------------------------------------------------------------------
+#define portYIELD() do{bYield = 1; __asm(" INTR INT14");}while(0)
+#define portYIELD_FROM_ISR( x )  do{if(x == pdTRUE){bYield = 1; __asm(" OR IFR, #0x2000");}}while(0)
+
+extern void portTICK_ISR( void );
+extern void portRESTORE_FIRST_CONTEXT( void );
+extern void vTaskSwitchContext( void );
+extern volatile uint16_t bYield;
+
+//-------------------------------------------------------------------------------------------------
+// Hardware specifics.
+//-------------------------------------------------------------------------------------------------
+#define portBYTE_ALIGNMENT      2
+#define portSTACK_GROWTH        ( 1 )
+#define portTICK_PERIOD_MS      ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP()               __asm(" NOP")
+
+//-------------------------------------------------------------------------------------------------
+// Task function macros as described on the FreeRTOS.org WEB site.
+//-------------------------------------------------------------------------------------------------
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#endif /* PORTMACRO_H */

kernel/FreeRTOS/Source/portable/ThirdParty/Community-Supported-Ports/GCC/MSP430FR5969/port.c

@@ -0,0 +1,317 @@
+/*
+ * FreeRTOS Kernel V10.4.2
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* Standard includes. */
+#include <stdlib.h>
+#include <signal.h>
+
+#include <msp430.h>
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the MSP430 port.
+ *----------------------------------------------------------*/
+
+/* Constants required for hardware setup.  The tick ISR runs off the ACLK,
+not the MCLK. */
+#define portACLK_FREQUENCY_HZ           ( ( TickType_t ) 32768 )
+#define portINITIAL_CRITICAL_NESTING    ( ( uint16_t ) 10 )
+#define portFLAGS_INT_ENABLED           ( ( StackType_t ) 0x08 )
+
+/* We require the address of the pxCurrentTCB variable, but don't want to know
+any details of its type. */
+typedef void TCB_t;
+extern volatile TCB_t * volatile pxCurrentTCB;
+
+/* Most ports implement critical sections by placing the interrupt flags on
+the stack before disabling interrupts.  Exiting the critical section is then
+simply a case of popping the flags from the stack.  As mspgcc does not use
+a frame pointer this cannot be done as modifying the stack will clobber all
+the stack variables.  Instead each task maintains a count of the critical
+section nesting depth.  Each time a critical section is entered the count is
+incremented.  Each time a critical section is left the count is decremented -
+with interrupts only being re-enabled if the count is zero.
+
+usCriticalNesting will get set to zero when the scheduler starts, but must
+not be initialised to zero as this will cause problems during the startup
+sequence. */
+volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING;
+/*-----------------------------------------------------------*/
+
+/*
+ * Macro to save a task context to the task stack.  This simply pushes all the
+ * general purpose msp430 registers onto the stack, followed by the
+ * usCriticalNesting value used by the task.  Finally the resultant stack
+ * pointer value is saved into the task control block so it can be retrieved
+ * the next time the task executes.
+ */
+#ifdef __LARGE_DATA_MODEL__
+#define portSAVE_CONTEXT()                                   \
+    asm volatile (  "pushm.a #12, r15                 \n\t"  \
+                    "movx.w &usCriticalNesting, r14   \n\t"  \
+                    "pushm.a #1, r14                  \n\t"  \
+                    "movx.a &pxCurrentTCB, r12        \n\t"  \
+                    "movx.a sp, 0(r12)                \n\t"  \
+                );
+#else
+#define portSAVE_CONTEXT()                                   \
+    asm volatile (  "pushm.w #12, r15                 \n\t"  \
+                    "mov.w &usCriticalNesting, r14    \n\t"  \
+                    "push.w r14                       \n\t"  \
+                    "mov.w &pxCurrentTCB, r12         \n\t"  \
+                    "mov.w sp, 0(r12)                 \r\t"  \
+                );
+#endif
+
+/*
+ * Macro to restore a task context from the task stack.  This is effectively
+ * the reverse of portSAVE_CONTEXT().  First the stack pointer value is
+ * loaded from the task control block.  Next the value for usCriticalNesting
+ * used by the task is retrieved from the stack - followed by the value of all
+ * the general purpose msp430 registers.
+ *
+ */
+#ifdef __LARGE_DATA_MODEL__
+#define portRESTORE_CONTEXT()                                \
+    asm volatile (  "movx.a &pxCurrentTCB, r12        \n\t"  \
+                    "movx.a @r12, sp                  \n\t"  \
+                    "popm.a #1, r15                   \n\t"  \
+                    "movx.w r15, &usCriticalNesting   \n\t"  \
+                    "popm.a #12, r15                  \n\t"  \
+                    "nop                              \n\t"  \
+                    "pop.w sr                         \n\t"  \
+                    "nop                              \n\t"  \
+                    "reta                             \n\t"  \
+                );
+#else
+#define portRESTORE_CONTEXT()                                \
+    asm volatile (  "mov.w  &pxCurrentTCB, r12       \n\t"   \
+                    "mov.w @r12, sp                  \n\t"   \
+                    "pop.w r15                       \n\t"   \
+                    "mov.w r15, &usCriticalNesting   \n\t"   \
+                    "popm.w #12, r15                 \n\t"   \
+                    "nop                             \n\t"   \
+                    "pop.w sr                        \n\t"   \
+                    "nop                             \n\t"   \
+                    "ret                             \n\t"   \
+                );
+#endif
+/*-----------------------------------------------------------*/
+
+/*
+ * Sets up the periodic ISR used for the RTOS tick.  This uses timer 0, but
+ * could have alternatively used the watchdog timer or timer 1.
+ */
+static void prvSetupTimerInterrupt( void );
+/*-----------------------------------------------------------*/
+
+/*
+ * Initialise the stack of a task to look exactly as if a call to
+ * portSAVE_CONTEXT had been called.
+ *
+ * See the header file portable.h.
+ */
+
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+    uint16_t *pusTopOfStack;
+    uint32_t *pulTopOfStack, ulTemp;
+
+    /*
+        Place a few bytes of known values on the bottom of the stack.
+        This is just useful for debugging and can be included if required.
+
+        *pxTopOfStack = ( StackType_t ) 0x1111;
+        pxTopOfStack--;
+        *pxTopOfStack = ( StackType_t ) 0x2222;
+        pxTopOfStack--;
+        *pxTopOfStack = ( StackType_t ) 0x3333;
+        pxTopOfStack--;
+    */
+
+    /* Data types are need either 16 bits or 32 bits depending on the data
+    and code model used. */
+    if( sizeof( pxCode ) == sizeof( uint16_t ) )
+    {
+        pusTopOfStack = ( uint16_t * ) pxTopOfStack;
+        ulTemp = ( uint32_t ) pxCode;
+        *pusTopOfStack = ( uint16_t ) ulTemp;
+    }
+    else
+    {
+        /* Make room for a 20 bit value stored as a 32 bit value. */
+        pusTopOfStack = ( uint16_t * ) pxTopOfStack;
+        pusTopOfStack--;
+        pulTopOfStack = ( uint32_t * ) pusTopOfStack;
+        *pulTopOfStack = ( uint32_t ) pxCode;
+    }
+
+    pusTopOfStack--;
+    *pusTopOfStack = portFLAGS_INT_ENABLED;
+    pusTopOfStack -= ( sizeof( StackType_t ) / 2 );
+
+    /* From here on the size of stacked items depends on the memory model. */
+    pxTopOfStack = ( StackType_t * ) pusTopOfStack;
+
+    /* Next the general purpose registers. */
+    #ifdef PRELOAD_REGISTER_VALUES
+        *pxTopOfStack = ( StackType_t ) 0xffff;
+        pxTopOfStack--;
+        *pxTopOfStack = ( StackType_t ) 0xeeee;
+        pxTopOfStack--;
+        *pxTopOfStack = ( StackType_t ) 0xdddd;
+        pxTopOfStack--;
+        *pxTopOfStack = ( StackType_t ) pvParameters;
+        pxTopOfStack--;
+        *pxTopOfStack = ( StackType_t ) 0xbbbb;
+        pxTopOfStack--;
+        *pxTopOfStack = ( StackType_t ) 0xaaaa;
+        pxTopOfStack--;
+        *pxTopOfStack = ( StackType_t ) 0x9999;
+        pxTopOfStack--;
+        *pxTopOfStack = ( StackType_t ) 0x8888;
+        pxTopOfStack--;
+        *pxTopOfStack = ( StackType_t ) 0x7777;
+        pxTopOfStack--;
+        *pxTopOfStack = ( StackType_t ) 0x6666;
+        pxTopOfStack--;
+        *pxTopOfStack = ( StackType_t ) 0x5555;
+        pxTopOfStack--;
+        *pxTopOfStack = ( StackType_t ) 0x4444;
+        pxTopOfStack--;
+    #else
+        pxTopOfStack -= 3;
+        *pxTopOfStack = ( StackType_t ) pvParameters;
+        pxTopOfStack -= 9;
+    #endif
+
+    /* A variable is used to keep track of the critical section nesting.
+    This variable has to be stored as part of the task context and is
+    initially set to zero. */
+    *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING;
+
+    /* Return a pointer to the top of the stack we have generated so this can
+    be stored in the task control block for the task. */
+    return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+    /* Setup the hardware to generate the tick.  Interrupts are disabled when
+    this function is called. */
+    prvSetupTimerInterrupt();
+
+    /* Restore the context of the first task that is going to run. */
+    portRESTORE_CONTEXT();
+
+    /* Should not get here as the tasks are now running! */
+    return pdTRUE;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+    /* It is unlikely that the MSP430 port will get stopped.  If required simply
+    disable the tick interrupt here. */
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Manual context switch called by portYIELD or taskYIELD.
+ *
+ * The first thing we do is save the registers so we can use a naked attribute.
+ */
+
+void vPortYield( void ) __attribute__ ( ( naked ) );
+void vPortYield( void )
+{
+    asm volatile ( "push.w  sr" );
+
+    portDISABLE_INTERRUPTS();
+    portSAVE_CONTEXT();
+
+    vTaskSwitchContext();
+
+    portRESTORE_CONTEXT();
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Hardware initialisation to generate the RTOS tick.  This uses timer 0
+ * but could alternatively use the watchdog timer or timer 1.
+ */
+static void prvSetupTimerInterrupt( void )
+{
+    vApplicationSetupTimerInterrupt();
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * The interrupt service routine used depends on whether the pre-emptive
+ * scheduler is being used or not.
+ */
+
+#if configUSE_PREEMPTION == 1
+void vPortPreemptiveTickISR(void)
+{
+    asm volatile("push.w sr");
+    portSAVE_CONTEXT();
+
+    if(xTaskIncrementTick() != pdFALSE)
+    {
+        vTaskSwitchContext();
+    }
+
+    portRESTORE_CONTEXT();
+}
+
+__attribute__((interrupt(configTICK_VECTOR))) void prvTickISR(void)
+{
+    __bic_SR_register_on_exit( SCG1 + SCG0 + OSCOFF + CPUOFF );
+    vPortPreemptiveTickISR();
+}
+#else
+void vPortCooperativeTickISR(void)
+{
+    asm volatile("push.w sr");
+    portSAVE_CONTEXT();
+
+    xTaskIncrementTick();
+
+    portRESTORE_CONTEXT();
+}
+
+__attribute__((interrupt(configTICK_VECTOR))) void prvTickISR(void)
+{
+    __bic_SR_register_on_exit( SCG1 + SCG0 + OSCOFF + CPUOFF );
+
+    vPortCooperativeTickISR();
+}
+#endif

kernel/FreeRTOS/Source/portable/ThirdParty/Community-Supported-Ports/GCC/MSP430FR5969/portmacro.h

@@ -0,0 +1,132 @@
+/*
+ * FreeRTOS Kernel V10.4.2
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Hardware includes. */
+#include <msp430.h>
+
+/* Type definitions. */
+#define portCHAR        char
+#define portFLOAT       float
+#define portDOUBLE      double
+#define portLONG        long
+#define portSHORT       int
+#define portBASE_TYPE   short
+
+/* The stack type changes depending on the data model. */
+#ifdef __LARGE_DATA_MODEL__
+    #define portSTACK_TYPE  uint32_t
+#else
+    #define portSTACK_TYPE  uint16_t
+    #define portPOINTER_SIZE_TYPE uint16_t
+#endif
+
+typedef portSTACK_TYPE StackType_t;
+typedef short BaseType_t;
+typedef unsigned short UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+    typedef uint16_t TickType_t;
+    #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+    typedef uint32_t TickType_t;
+    #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+
+/*-----------------------------------------------------------*/
+
+/* Interrupt control macros. */
+#define portDISABLE_INTERRUPTS()    asm volatile ( "NOP" ); asm volatile ( "DINT" ); asm volatile ( "NOP" )
+#define portENABLE_INTERRUPTS()     asm volatile ( "NOP" ); asm volatile ( "EINT" ); asm volatile ( "NOP" )
+/*-----------------------------------------------------------*/
+
+/* Critical section control macros. */
+#define portNO_CRITICAL_SECTION_NESTING     ( ( uint16_t ) 0 )
+
+#define portENTER_CRITICAL()                                                    \
+{                                                                               \
+extern volatile uint16_t usCriticalNesting;                         \
+                                                                                \
+    portDISABLE_INTERRUPTS();                                                   \
+                                                                                \
+    /* Now interrupts are disabled ulCriticalNesting can be accessed */         \
+    /* directly.  Increment ulCriticalNesting to keep a count of how many */    \
+    /* times portENTER_CRITICAL() has been called. */                           \
+    usCriticalNesting++;                                                        \
+}
+
+#define portEXIT_CRITICAL()                                                     \
+{                                                                               \
+extern volatile uint16_t usCriticalNesting;                         \
+                                                                                \
+    if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING )                   \
+    {                                                                           \
+        /* Decrement the nesting count as we are leaving a critical section. */ \
+        usCriticalNesting--;                                                    \
+                                                                                \
+        /* If the nesting level has reached zero then interrupts should be */   \
+        /* re-enabled. */                                                       \
+        if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING )              \
+        {                                                                       \
+            portENABLE_INTERRUPTS();                                            \
+        }                                                                       \
+    }                                                                           \
+}
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+extern void vPortYield( void ) __attribute__ ( ( naked ) );
+#define portYIELD()         vPortYield()
+#define portNOP()           asm volatile ( "NOP" )
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT          2
+#define portSTACK_GROWTH            ( -1 )
+#define portTICK_PERIOD_MS          ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+extern void vTaskSwitchContext(void);
+#define portYIELD_FROM_ISR( x ) if( x ) vPortYield()
+void vApplicationSetupTimerInterrupt( void );
+
+#endif /* PORTMACRO_H */

kernel/FreeRTOS/Source/portable/ThirdParty/Community-Supported-Ports/GCC/RISC-V/chip_specific_extensions/THEAD_RV32/freertos_risc_v_chip_specific_extensions.h

@@ -0,0 +1,210 @@
+/*
+ * FreeRTOS Kernel V10.4.0
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * The FreeRTOS kernel's RISC-V port is split between the the code that is
+ * common across all currently supported RISC-V chips (implementations of the
+ * RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
+ *
+ * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that
+ *   is common to all currently supported RISC-V chips.  There is only one
+ *   portASM.S file because the same file is built for all RISC-V target chips.
+ *
+ * + Header files called freertos_risc_v_chip_specific_extensions.h contain the
+ *   code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V
+ *   chip.  There are multiple freertos_risc_v_chip_specific_extensions.h files
+ *   as there are multiple RISC-V chip implementations.
+ *
+ * !!!NOTE!!!
+ * TAKE CARE TO INCLUDE THE CORRECT freertos_risc_v_chip_specific_extensions.h
+ * HEADER FILE FOR THE CHIP IN USE.  This is done using the assembler's (not the
+ * compiler's!) include path.  For example, if the chip in use includes a core
+ * local interrupter (CLINT) and does not include any chip specific register
+ * extensions then add the path below to the assembler's include path:
+ * FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions
+ *
+ */
+
+
+#ifndef __FREERTOS_RISC_V_EXTENSIONS_H__
+#define __FREERTOS_RISC_V_EXTENSIONS_H__
+
+#define portasmHANDLE_INTERRUPT Default_IRQHandler
+#define portasmHAS_SIFIVE_CLINT 1
+#define portasmHAS_MTIME 0
+#define portasmADDITIONAL_CONTEXT_SIZE 0 /* Must be even number on 32-bit cores. */
+
+.macro portasmSAVE_ADDITIONAL_REGISTERS
+	/* save float registers */
+#if __riscv_flen == 64
+        addi    sp,  sp, -(128+128)
+
+        fsd     f31, (0  + 0 )(sp)
+        fsd     f30, (4  + 4 )(sp)
+        fsd     f29, (8  + 8 )(sp)
+        fsd     f28, (12 + 12)(sp)
+        fsd     f27, (16 + 16)(sp)
+        fsd     f26, (20 + 20)(sp)
+        fsd     f25, (24 + 24)(sp)
+        fsd     f24, (28 + 28)(sp)
+        fsd     f23, (32 + 32)(sp)
+        fsd     f22, (36 + 36)(sp)
+        fsd     f21, (40 + 40)(sp)
+        fsd     f20, (44 + 44)(sp)
+        fsd     f19, (48 + 48)(sp)
+        fsd     f18, (52 + 52)(sp)
+        fsd     f17, (56 + 56)(sp)
+        fsd     f16, (60 + 60)(sp)
+        fsd     f15, (64 + 64)(sp)
+        fsd     f14, (68 + 68)(sp)
+        fsd     f13, (72 + 72)(sp)
+        fsd     f12, (76 + 76)(sp)
+        fsd     f11, (80 + 80)(sp)
+        fsd     f10, (84 + 84)(sp)
+        fsd     f9,  (88 + 88)(sp)
+        fsd     f8,  (92 + 92)(sp)
+        fsd     f7,  (96 + 96)(sp)
+        fsd     f6,  (100+100)(sp)
+        fsd     f5,  (104+104)(sp)
+        fsd     f4,  (108+108)(sp)
+        fsd     f3,  (112+112)(sp)
+        fsd     f2,  (116+116)(sp)
+        fsd     f1,  (120+120)(sp)
+        fsd     f0,  (124+124)(sp)
+#elif __riscv_flen == 32
+        addi    sp,  sp, -(128)
+
+        fsw     f31, (0  )(sp)
+        fsw     f30, (4  )(sp)
+        fsw     f29, (8  )(sp)
+        fsw     f28, (12 )(sp)
+        fsw     f27, (16 )(sp)
+        fsw     f26, (20 )(sp)
+        fsw     f25, (24 )(sp)
+        fsw     f24, (28 )(sp)
+        fsw     f23, (32 )(sp)
+        fsw     f22, (36 )(sp)
+        fsw     f21, (40 )(sp)
+        fsw     f20, (44 )(sp)
+        fsw     f19, (48 )(sp)
+        fsw     f18, (52 )(sp)
+        fsw     f17, (56 )(sp)
+        fsw     f16, (60 )(sp)
+        fsw     f15, (64 )(sp)
+        fsw     f14, (68 )(sp)
+        fsw     f13, (72 )(sp)
+        fsw     f12, (76 )(sp)
+        fsw     f11, (80 )(sp)
+        fsw     f10, (84 )(sp)
+        fsw     f9,  (88 )(sp)
+        fsw     f8,  (92 )(sp)
+        fsw     f7,  (96 )(sp)
+        fsw     f6,  (100)(sp)
+        fsw     f5,  (104)(sp)
+        fsw     f4,  (108)(sp)
+        fsw     f3,  (112)(sp)
+        fsw     f2,  (116)(sp)
+        fsw     f1,  (120)(sp)
+        fsw     f0,  (124)(sp)
+#endif
+	.endm
+
+.macro portasmRESTORE_ADDITIONAL_REGISTERS
+	/* load float registers */
+#if __riscv_flen == 64
+        fld     f31, (0  + 0 )(sp)
+        fld     f30, (4  + 4 )(sp)
+        fld     f29, (8  + 8 )(sp)
+        fld     f28, (12 + 12)(sp)
+        fld     f27, (16 + 16)(sp)
+        fld     f26, (20 + 20)(sp)
+        fld     f25, (24 + 24)(sp)
+        fld     f24, (28 + 28)(sp)
+        fld     f23, (32 + 32)(sp)
+        fld     f22, (36 + 36)(sp)
+        fld     f21, (40 + 40)(sp)
+        fld     f20, (44 + 44)(sp)
+        fld     f19, (48 + 48)(sp)
+        fld     f18, (52 + 52)(sp)
+        fld     f17, (56 + 56)(sp)
+        fld     f16, (60 + 60)(sp)
+        fld     f15, (64 + 64)(sp)
+        fld     f14, (68 + 68)(sp)
+        fld     f13, (72 + 72)(sp)
+        fld     f12, (76 + 76)(sp)
+        fld     f11, (80 + 80)(sp)
+        fld     f10, (84 + 84)(sp)
+        fld     f9,  (88 + 88)(sp)
+        fld     f8,  (92 + 92)(sp)
+        fld     f7,  (96 + 96)(sp)
+        fld     f6,  (100+100)(sp)
+        fld     f5,  (104+104)(sp)
+        fld     f4,  (108+108)(sp)
+        fld     f3,  (112+112)(sp)
+        fld     f2,  (116+116)(sp)
+        fld     f1,  (120+120)(sp)
+        fld     f0,  (124+124)(sp)
+
+        addi    sp, sp, (128+128)
+#elif __riscv_flen == 32
+        flw     f31, (0  )(sp)
+        flw     f30, (4  )(sp)
+        flw     f29, (8  )(sp)
+        flw     f28, (12 )(sp)
+        flw     f27, (16 )(sp)
+        flw     f26, (20 )(sp)
+        flw     f25, (24 )(sp)
+        flw     f24, (28 )(sp)
+        flw     f23, (32 )(sp)
+        flw     f22, (36 )(sp)
+        flw     f21, (40 )(sp)
+        flw     f20, (44 )(sp)
+        flw     f19, (48 )(sp)
+        flw     f18, (52 )(sp)
+        flw     f17, (56 )(sp)
+        flw     f16, (60 )(sp)
+        flw     f15, (64 )(sp)
+        flw     f14, (68 )(sp)
+        flw     f13, (72 )(sp)
+        flw     f12, (76 )(sp)
+        flw     f11, (80 )(sp)
+        flw     f10, (84 )(sp)
+        flw     f9,  (88 )(sp)
+        flw     f8,  (92 )(sp)
+        flw     f7,  (96 )(sp)
+        flw     f6,  (100)(sp)
+        flw     f5,  (104)(sp)
+        flw     f4,  (108)(sp)
+        flw     f3,  (112)(sp)
+        flw     f2,  (116)(sp)
+        flw     f1,  (120)(sp)
+        flw     f0,  (124)(sp)
+
+        addi    sp, sp, (128)
+#endif
+	.endm
+#endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */

kernel/FreeRTOS/Source/portable/ThirdParty/Community-Supported-Ports/GCC/TriCore_38xa/port.c

@@ -0,0 +1,573 @@
+/*
+ * FreeRTOS Kernel V10.4.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#include "port.h"
+
+/* Standard includes. */
+#include <stdlib.h>
+#include <string.h>
+
+/* TriCore specific includes. */
+#include <machine/intrinsics.h>
+#include <machine/cint.h>
+#include <machine/wdtcon.h>
+#include <tc38xa/Ifx_reg.h>
+#include <tc38xa/IfxScu_reg.h>
+#include "interrupts.h"
+
+/* Kernel includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "list.h"
+
+#if configCHECK_FOR_STACK_OVERFLOW > 0
+	#error "Stack checking cannot be used with this port, as, unlike most ports, the pxTopOfStack member of the TCB is consumed CSA.  CSA starvation, loosely equivalent to stack overflow, will result in a trap exception."
+	/* The stack pointer is accessible using portCSA_TO_ADDRESS( portCSA_TO_ADDRESS( pxCurrentTCB->pxTopOfStack )[ 0 ] )[ 2 ]; */
+#endif /* configCHECK_FOR_STACK_OVERFLOW */
+
+#define CPU_ID (_mfcr(CPU_CORE_ID) & 0x0f)
+
+static volatile Ifx_STM* STMs[4] = {&MODULE_STM0, &MODULE_STM1, &MODULE_STM2, &MODULE_STM3};
+static const unsigned short STM_SRCs[4] = {SRC_ID_STM0SR0, SRC_ID_STM1SR0, SRC_ID_STM2SR0, SRC_ID_STM3SR0};
+static volatile Ifx_INT_SRB* SRBs[4] = {&INT_SRB0, &INT_SRB1, &INT_SRB2, &INT_SRB3};
+static const unsigned short GPSRs[4] = {SRC_ID_GPSR00, SRC_ID_GPSR10, SRC_ID_GPSR20, SRC_ID_GPSR30};
+
+typedef struct
+{
+	unsigned int PCXI, PSW, A10, A11, D8, D9, D10, D11, A12, A13, A14, A15, D12, D13, D14, D15;
+} UPPER_CONTEXT;
+
+/*-----------------------------------------------------------*/
+
+/* System register Definitions. */
+#define portSYSTEM_PROGRAM_STATUS_WORD					( 0x000008FFUL ) /* Supervisor Mode, MPU Register Set 0 and Call Depth Counting disabled. */
+#define portINITIAL_PRIVILEGED_PROGRAM_STATUS_WORD		( 0x000014FFUL ) /* IO Level 1, MPU Register Set 1 and Call Depth Counting disabled. */
+#define portINITIAL_UNPRIVILEGED_PROGRAM_STATUS_WORD	( 0x000010FFUL ) /* IO Level 0, MPU Register Set 1 and Call Depth Counting disabled. */
+//#define portINITIAL_PCXI_UPPER_CONTEXT_WORD	        ( 0x00C00000UL ) /* The lower 20 bits identify the CSA address. */
+//#define portINITIAL_PCXI_UPPER_CONTEXT_WORD			( 0x10300000UL ) // ATENlower 20 bits identify the CSA address. */
+#define portINITIAL_PCXI_UPPER_CONTEXT_WORD				( 0x00300000UL ) // ATEN, default value as read from the CPU after init
+#define portINITIAL_SYSCON								( 0x00000000UL ) /* MPU Disable. */
+
+/* CSA manipulation macros. */
+#define portCSA_FCX_MASK					( 0x000FFFFFUL )
+
+/* OS Interrupt and Trap mechanisms. */
+#define portRESTORE_PSW_MASK				( ~( 0x000000FFUL ) )
+#define portSYSCALL_TRAP					( 6 )
+
+/* Each CSA contains 16 words of data. */
+#define portNUM_WORDS_IN_CSA				( 16 )
+
+/* The interrupt enable bit in the PCP_SRC register. */
+#define portENABLE_CPU_INTERRUPT 			( 1U << 12U )
+/*-----------------------------------------------------------*/
+
+/*
+ * Perform any hardware configuration necessary to generate the tick interrupt.
+ */
+static void prvSystemTickHandler( int ) __attribute__((longcall));
+static void prvERUISRHandler( int ) __attribute__((longcall));
+static void prvSetupTimerInterrupt( void );
+
+#define ERUInterruptCoreID 0
+static void prvSetupERUInterrupt(void);
+
+/*
+ * Priority 1 interrupt handler for yields pended from an interrupt.
+ */
+static void prvInterruptYield( int iTrapIdentification );
+
+/*-----------------------------------------------------------*/
+
+/* This reference is required by the save/restore context macros. */
+extern volatile uint32_t *pxCurrentTCB;
+
+extern TaskHandle_t xTaskHandle0[E_TASKS_CPU0_SIZE];
+
+/* Precalculate the compare match value at compile time. */
+static const uint32_t ulCompareMatchValue = ( configPERIPHERAL_CLOCK_HZ / configTICK_RATE_HZ );
+
+/*-----------------------------------------------------------*/
+
+StackType_t *pxPortInitialiseStack( StackType_t * pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+uint32_t *pulUpperCSA = NULL;
+uint32_t *pulLowerCSA = NULL;
+
+	/* 16 Address Registers (4 Address registers are global), 16 Data
+	Registers, and 3 System Registers.
+
+	There are 3 registers that track the CSAs.
+		FCX points to the head of globally free set of CSAs.
+		PCX for the task needs to point to Lower->Upper->NULL arrangement.
+		LCX points to the last free CSA so that corrective action can be taken.
+
+	Need two CSAs to store the context of a task.
+		The upper context contains D8-D15, A10-A15, PSW and PCXI->NULL.
+		The lower context contains D0-D7, A2-A7, A11 and PCXI->UpperContext.
+		The pxCurrentTCB->pxTopOfStack points to the Lower Context RSLCX matching the initial BISR.
+		The Lower Context points to the Upper Context ready for the return from the interrupt handler.
+
+	 The Real stack pointer for the task is stored in the A10 which is restored
+	 with the upper context. */
+
+	/* Have to disable interrupts here because the CSAs are going to be
+	manipulated. */
+	portENTER_CRITICAL();
+	{
+		/* DSync to ensure that buffering is not a problem. */
+		_dsync();
+
+		/* Consume two free CSAs. */
+		pulLowerCSA = portCSA_TO_ADDRESS( __MFCR( $FCX ) );
+		if( NULL != pulLowerCSA )
+		{
+			/* The Lower Links to the Upper. */
+			pulUpperCSA = portCSA_TO_ADDRESS( pulLowerCSA[ 0 ] );
+		}
+
+		/* Check that we have successfully reserved two CSAs. */
+		if( ( NULL != pulLowerCSA ) && ( NULL != pulUpperCSA ) )
+		{
+			/* Remove the two consumed CSAs from the free CSA list. */
+			_disable();
+			_dsync();
+			_mtcr( $FCX, pulUpperCSA[ 0 ] );
+			_isync();
+			_enable();
+		}
+		else
+		{
+			/* Simply trigger a context list depletion trap. */
+			_svlcx();
+		}
+	}
+	portEXIT_CRITICAL();
+
+	/* Clear the upper CSA. */
+	memset( pulUpperCSA, 0, portNUM_WORDS_IN_CSA * sizeof( uint32_t ) );
+
+	/* Upper Context. */
+	pulUpperCSA[ 2 ] = ( uint32_t )pxTopOfStack;		/* A10;	Stack Return aka Stack Pointer */
+	pulUpperCSA[ 1 ] = portSYSTEM_PROGRAM_STATUS_WORD;		/* PSW	*/
+
+	/* Clear the lower CSA. */
+	memset( pulLowerCSA, 0, portNUM_WORDS_IN_CSA * sizeof( uint32_t ) );
+
+	/* Lower Context. */
+	pulLowerCSA[ 8 ] = ( uint32_t ) pvParameters;		/* A4;	Address Type Parameter Register	*/
+	pulLowerCSA[ 1 ] = ( uint32_t ) pxCode;			/* A11;	Return Address aka RA */
+
+	/* PCXI pointing to the Upper context. */
+	pulLowerCSA[ 0 ] = ( portINITIAL_PCXI_UPPER_CONTEXT_WORD | ( uint32_t ) portADDRESS_TO_CSA( pulUpperCSA ) );
+
+	/* Save the link to the CSA in the top of stack. */
+	pxTopOfStack = (uint32_t * ) portADDRESS_TO_CSA( pulLowerCSA );
+
+	/* DSync to ensure that buffering is not a problem. */
+	_dsync();
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+int32_t xPortStartScheduler( void )
+{
+	extern void vTrapInstallHandlers( void );
+	uint32_t ulMFCR = 0UL;
+	uint32_t *pulUpperCSA = NULL;
+	uint32_t *pulLowerCSA = NULL;
+
+	/* prevent compiler warnings */
+	(void)pulUpperCSA;
+
+	/* Interrupts at or below configMAX_SYSCALL_INTERRUPT_PRIORITY are disable
+	when this function is called. */
+
+	/* Set-up the ERU interrupt. */
+	prvSetupERUInterrupt();
+
+	/* Set-up the timer interrupt. */
+	prvSetupTimerInterrupt();
+
+	/* Install the Trap Handlers. */
+	// vTrapInstallHandlers();
+
+	/* Install the Syscall Handler for yield calls. */
+	// if( 0 == _install_trap_handler( portSYSCALL_TRAP, prvTrapYield ) )
+	// {
+	// 	/* Failed to install the yield handler, force an assert. */
+	// 	configASSERT( ( ( volatile void * ) NULL ) );
+	// }
+
+	/* Enable and install the priority 1 interrupt for pending context switches from an ISR. */
+	InterruptInstall(GPSRs[CPU_ID], prvInterruptYield, configKERNEL_YIELD_PRIORITY, 0);       //ATEN
+
+	_disable();
+
+	/* Load the initial SYSCON. */
+	_mtcr( $SYSCON, portINITIAL_SYSCON );
+	_isync();
+
+	/* ENDINIT has already been applied in the 'cstart.c' code. */
+
+	/* Clear the PSW.CDC to enable the use of an RFE without it generating an
+	exception because this code is not genuinely in an exception. */
+	ulMFCR = __MFCR( $PSW );
+	ulMFCR &= portRESTORE_PSW_MASK;
+	_dsync();
+	_mtcr( $PSW, ulMFCR );
+	_isync();
+
+	/* Finally, perform the equivalent of a portRESTORE_CONTEXT() */
+	pulLowerCSA = portCSA_TO_ADDRESS( ( *pxCurrentTCB ) );
+	pulUpperCSA = portCSA_TO_ADDRESS( pulLowerCSA[0] );
+
+	_dsync();
+	_mtcr( $PCXI, *pxCurrentTCB );
+	_isync();
+	_nop();
+	_rslcx();
+	_nop();
+
+
+	/* Return to the first task selected to execute. */
+	__asm volatile( "rfe" );
+
+	/* Will not get here. */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void )
+{
+	unsigned short cpuid = CPU_ID;
+
+	//  Install handler for timer interrupt & reset interrupt flag
+	STMs[cpuid]->ISCR.U = 1;
+	InterruptInstall(STM_SRCs[cpuid], prvSystemTickHandler, configKERNEL_INTERRUPT_PRIORITY, 0);
+
+	// prepare compare register for first interrupt
+	STMs[cpuid]->CMP[0].U = STMs[cpuid]->TIM0.U + ulCompareMatchValue;
+	STMs[cpuid]->CMCON.U  = 31;
+	STMs[cpuid]->OCS.B.SUS = 2;
+	STMs[cpuid]->ICR.B.CMP0EN = 1;
+
+}
+/*-----------------------------------------------------------*/
+
+/*****************************************************************/
+static void prvSetupERUInterrupt(void)
+{
+	unsigned short cpuid = CPU_ID;
+
+	if(cpuid == ERUInterruptCoreID)
+	{
+		SCU_FMR.B.FC0 = 1;	//Clear the interrupt flag
+		InterruptInstall(SRC_ID_SCUERU0, prvERUISRHandler, 3, 0);	//Load the interrupt routine and priortiy
+	}
+}
+
+/*****************************************************************/
+
+static void prvSystemTickHandler( int iArg )
+{
+uint32_t ulSavedInterruptMask;
+uint32_t *pxUpperCSA = NULL;
+uint32_t xUpperCSA = 0UL;
+extern volatile uint32_t *pxCurrentTCB;
+int32_t lYieldRequired;
+unsigned short cpuid = CPU_ID;
+
+	/* Just to avoid compiler warnings about unused parameters. */
+	( void ) iArg;
+
+	/* Clear the interrupt source. */
+	//STM_ISRR.reg = 1UL; //ATEN
+
+	/* Reload the Compare Match register for X ticks into the future.
+
+	If critical section or interrupt nesting budgets are exceeded, then
+	it is possible that the calculated next compare match value is in the
+	past.  If this occurs (unlikely), it is possible that the resulting
+	time slippage will exceed a single tick period.  Any adverse effect of
+	this is time bounded by the fact that only the first n bits of the 56 bit
+	STM timer are being used for a compare match, so another compare match
+	will occur after an overflow in just those n bits (not the entire 56 bits).
+	As an example, if the peripheral clock is 75MHz, and the tick rate is 1KHz,
+	a missed tick could result in the next tick interrupt occurring within a
+	time that is 1.7 times the desired period.  The fact that this is greater
+	than a single tick period is an effect of using a timer that cannot be
+	automatically reset, in hardware, by the occurrence of a tick interrupt.
+	Changing the tick source to a timer that has an automatic reset on compare
+	match (such as a GPTA timer) will reduce the maximum possible additional
+	period to exactly 1 times the desired period. */
+
+	STMs[cpuid]->CMP[0].U = STMs[cpuid]->TIM0.U + ulCompareMatchValue; //ATEN
+	STMs[cpuid]->ISCR.B.CMP0IRR = 1;
+	//STM_CMP0.reg += ulCompareMatchValue;
+
+	/* Kernel API calls require Critical Sections. */
+	ulSavedInterruptMask = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		/* Increment the Tick. */
+		lYieldRequired = xTaskIncrementTick();
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( ulSavedInterruptMask );
+
+	if( lYieldRequired != pdFALSE )
+	{
+		/* Save the context of a task.
+		The upper context is automatically saved when entering a trap or interrupt.
+		Need to save the lower context as well and copy the PCXI CSA ID into
+		pxCurrentTCB->pxTopOfStack. Only Lower Context CSA IDs may be saved to the
+		TCB of a task.
+
+		Call vTaskSwitchContext to select the next task, note that this changes the
+		value of pxCurrentTCB so that it needs to be reloaded.
+
+		Call vPortSetMPURegisterSetOne to change the MPU mapping for the task
+		that has just been switched in.
+
+		Load the context of the task.
+		Need to restore the lower context by loading the CSA from
+		pxCurrentTCB->pxTopOfStack into PCXI (effectively changing the call stack).
+		In the Interrupt handler post-amble, RSLCX will restore the lower context
+		of the task. RFE will restore the upper context of the task, jump to the
+		return address and restore the previous state of interrupts being
+		enabled/disabled. */
+		_disable();
+		_dsync();
+		xUpperCSA = __MFCR( $PCXI );
+		pxUpperCSA = portCSA_TO_ADDRESS( xUpperCSA );
+		*pxCurrentTCB = pxUpperCSA[ 0 ];
+		vTaskSwitchContext();
+		pxUpperCSA[ 0 ] = *pxCurrentTCB;
+		SRBs[cpuid]->B.TRIG0 = 0;       //ATEN
+		//CPU_SRC0.bits.SETR = 0;
+		_isync();
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvERUISRHandler( int iArg )
+{
+	BaseType_t checkIfYieldRequired;
+	/* Just to avoid compiler warnings about unused parameters. */
+	( void ) iArg;
+
+	SCU_FMR.B.FC0 = 1;	//Clear the interrupt flag
+
+	checkIfYieldRequired = xTaskResumeFromISR(xTaskHandle0[E_FPGA_TASK]);	//Check the state of the FPGA task
+	portYIELD_FROM_ISR(checkIfYieldRequired);	//Yield the FPGA task if it was suspended
+}
+
+/*
+ * When a task is deleted, it is yielded permanently until the IDLE task
+ * has an opportunity to reclaim the memory that that task was using.
+ * Typically, the memory used by a task is the TCB and Stack but in the
+ * TriCore this includes the CSAs that were consumed as part of the Call
+ * Stack. These CSAs can only be returned to the Globally Free Pool when
+ * they are not part of the current Call Stack, hence, delaying the
+ * reclamation until the IDLE task is freeing the task's other resources.
+ * This function uses the head of the linked list of CSAs (from when the
+ * task yielded for the last time) and finds the tail (the very bottom of
+ * the call stack) and inserts this list at the head of the Free list,
+ * attaching the existing Free List to the tail of the reclaimed call stack.
+ *
+ * NOTE: the IDLE task needs processing time to complete this function
+ * and in heavily loaded systems, the Free CSAs may be consumed faster
+ * than they can be freed assuming that tasks are being spawned and
+ * deleted frequently.
+ */
+void vPortReclaimCSA( uint32_t *pxTCB )
+{
+uint32_t pxHeadCSA, pxTailCSA, pxFreeCSA;
+uint32_t *pulNextCSA;
+
+	/* A pointer to the first CSA in the list of CSAs consumed by the task is
+	stored in the first element of the tasks TCB structure (where the stack
+	pointer would be on a traditional stack based architecture). */
+	pxHeadCSA = ( *pxTCB ) & portCSA_FCX_MASK;
+
+	/* Mask off everything in the CSA link field other than the address.  If
+	the	address is NULL, then the CSA is not linking anywhere and there is
+	nothing	to do. */
+	pxTailCSA = pxHeadCSA;
+
+	/* Convert the link value to contain just a raw address and store this
+	in a local variable. */
+	pulNextCSA = portCSA_TO_ADDRESS( pxTailCSA );
+
+	/* Iterate over the CSAs that were consumed as part of the task.  The
+	first field in the CSA is the pointer to then next CSA.  Mask off
+	everything in the pointer to the next CSA, other than the link address.
+	If this is NULL, then the CSA currently being pointed to is the last in
+	the chain. */
+	while( 0UL != ( pulNextCSA[ 0 ] & portCSA_FCX_MASK ) )
+	{
+		/* Clear all bits of the pointer to the next in the chain, other
+		than the address bits themselves. */
+		pulNextCSA[ 0 ] = pulNextCSA[ 0 ] & portCSA_FCX_MASK;
+
+		/* Move the pointer to point to the next CSA in the list. */
+		pxTailCSA = pulNextCSA[ 0 ];
+
+		/* Update the local pointer to the CSA. */
+		pulNextCSA = portCSA_TO_ADDRESS( pxTailCSA );
+	}
+
+	_disable();
+	{
+		/* Look up the current free CSA head. */
+		_dsync();
+		pxFreeCSA = __MFCR( $FCX );
+
+		/* Join the current Free onto the Tail of what is being reclaimed. */
+		portCSA_TO_ADDRESS( pxTailCSA )[ 0 ] = pxFreeCSA;
+
+		/* Move the head of the reclaimed into the Free. */
+		_dsync();
+		_mtcr( $FCX, pxHeadCSA );
+		_isync();
+	}
+	_enable();
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Nothing to do. Unlikely to want to end. */
+}
+/*-----------------------------------------------------------*/
+
+void vTrapSysCallYield( int iTrapIdentification )
+{
+uint32_t *pxUpperCSA = NULL;
+uint32_t xUpperCSA = 0UL;
+
+extern volatile uint32_t *pxCurrentTCB;
+
+	switch( iTrapIdentification )
+	{
+		case portSYSCALL_TASK_YIELD:
+			/* Save the context of a task.
+			The upper context is automatically saved when entering a trap or interrupt.
+			Need to save the lower context as well and copy the PCXI CSA ID into
+			pxCurrentTCB->pxTopOfStack. Only Lower Context CSA IDs may be saved to the
+			TCB of a task.
+
+			Call vTaskSwitchContext to select the next task, note that this changes the
+			value of pxCurrentTCB so that it needs to be reloaded.
+
+			Call vPortSetMPURegisterSetOne to change the MPU mapping for the task
+			that has just been switched in.
+
+			Load the context of the task.
+			Need to restore the lower context by loading the CSA from
+			pxCurrentTCB->pxTopOfStack into PCXI (effectively changing the call stack).
+			In the Interrupt handler post-amble, RSLCX will restore the lower context
+			of the task. RFE will restore the upper context of the task, jump to the
+			return address and restore the previous state of interrupts being
+			enabled/disabled. */
+			_disable();
+			_dsync();
+			xUpperCSA = __MFCR( $PCXI );
+			pxUpperCSA = portCSA_TO_ADDRESS( xUpperCSA );
+			*pxCurrentTCB = pxUpperCSA[ 0 ];
+			vTaskSwitchContext();
+			pxUpperCSA[ 0 ] = *pxCurrentTCB;
+			SRBs[CPU_ID]->B.TRIG0 = 0; //ATEN
+			// CPU_SRC0.bits.SETR = 0;
+			_isync();
+			break;
+
+		default:
+			/* Unimplemented trap called. */
+			configASSERT( ( ( volatile void * ) NULL ) );
+			break;
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvInterruptYield( int iId )
+{
+uint32_t *pxUpperCSA = NULL;
+uint32_t xUpperCSA = 0UL;
+extern volatile uint32_t *pxCurrentTCB;
+
+	/* Just to remove compiler warnings. */
+	( void ) iId;
+
+	/* Save the context of a task.
+	The upper context is automatically saved when entering a trap or interrupt.
+	Need to save the lower context as well and copy the PCXI CSA ID into
+	pxCurrentTCB->pxTopOfStack. Only Lower Context CSA IDs may be saved to the
+	TCB of a task.
+
+	Call vTaskSwitchContext to select the next task, note that this changes the
+	value of pxCurrentTCB so that it needs to be reloaded.
+
+	Call vPortSetMPURegisterSetOne to change the MPU mapping for the task
+	that has just been switched in.
+
+	Load the context of the task.
+	Need to restore the lower context by loading the CSA from
+	pxCurrentTCB->pxTopOfStack into PCXI (effectively changing the call stack).
+	In the Interrupt handler post-amble, RSLCX will restore the lower context
+	of the task. RFE will restore the upper context of the task, jump to the
+	return address and restore the previous state of interrupts being
+	enabled/disabled. */
+	_disable();
+	_dsync();
+	xUpperCSA = __MFCR( $PCXI );
+	pxUpperCSA = portCSA_TO_ADDRESS( xUpperCSA );
+	*pxCurrentTCB = pxUpperCSA[ 0 ];
+	vTaskSwitchContext();
+	pxUpperCSA[ 0 ] = *pxCurrentTCB;
+	SRBs[CPU_ID]->B.TRIG0 = 0;      //ATEN
+	//CPU_SRC0.bits.SETR = 0;
+	_isync();
+}
+/*-----------------------------------------------------------*/
+
+uint32_t uxPortSetInterruptMaskFromISR( void )
+{
+uint32_t uxReturn = 0UL;
+
+	_disable();
+	uxReturn = __MFCR( $ICR );
+	_mtcr( $ICR, ( ( uxReturn & ~portCCPN_MASK ) | configMAX_SYSCALL_INTERRUPT_PRIORITY ) );
+	_isync();
+	_enable();
+
+	/* Return just the interrupt mask bits. */
+	return ( uxReturn & portCCPN_MASK );
+}
+/*-----------------------------------------------------------*/
+
+

kernel/FreeRTOS/Source/portable/ThirdParty/Community-Supported-Ports/GCC/TriCore_38xa/port.h

@@ -0,0 +1,42 @@
+/*
+ * FreeRTOS Kernel V10.4.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef _PORTABLE_GCC_TRICORE_PORT_H_
+#define _PORTABLE_GCC_TRICORE_PORT_H_
+
+//These definitions seem to be missing within the TC3xx include files
+//Compile the project with the "-fdollars-in-identifiers" option!!
+
+#define $FCX 0xFE38
+#define $ICR 0xFE2C
+#define $PCXI 0xFE00
+#define $PSW 0xFE04
+#define $SYSCON 0xFE14
+
+extern void vTrapSysCallYield( int iTrapIdentification );
+
+#endif /* _PORTABLE_GCC_TRICORE_PORT_H_ */

kernel/FreeRTOS/Source/portable/ThirdParty/Community-Supported-Ports/GCC/TriCore_38xa/portmacro.h

@@ -0,0 +1,175 @@
+/*
+ * FreeRTOS Kernel V10.4.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef _PORTABLE_GCC_TRICORE_PORTMACRO_H_
+#define _PORTABLE_GCC_TRICORE_PORTMACRO_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "port.h"
+
+/* System Includes. */
+#include <machine/intrinsics.h>
+#include <tc38xaIfx_reg.h>
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	unsigned long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*---------------------------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH							( -1 )
+#define portTICK_PERIOD_MS							( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT							4
+#define portNOP()									__asm volatile( " nop " )
+#define portCRITICAL_NESTING_IN_TCB					1
+#define portRESTORE_FIRST_TASK_PRIORITY_LEVEL		1
+
+
+/*---------------------------------------------------------------------------*/
+
+typedef struct MPU_SETTINGS { uint32_t ulNotUsed; } xMPU_SETTINGS;
+
+/* Define away the instruction from the Restore Context Macro. */
+#define portPRIVILEGE_BIT							0x0UL
+
+#define portCCPN_MASK						( 0x000000FFUL )
+
+extern void vTaskEnterCritical( void );
+extern void vTaskExitCritical( void );
+#define portENTER_CRITICAL()			vTaskEnterCritical()
+#define portEXIT_CRITICAL()				vTaskExitCritical()
+/*---------------------------------------------------------------------------*/
+
+/* CSA Manipulation. */
+#define portCSA_TO_ADDRESS( pCSA )			( ( uint32_t * )( ( ( ( pCSA ) & 0x000F0000 ) << 12 ) | ( ( ( pCSA ) & 0x0000FFFF ) << 6 ) ) )
+#define portADDRESS_TO_CSA( pAddress )		( ( uint32_t )( ( ( ( (uint32_t)( pAddress ) ) & 0xF0000000 ) >> 12 ) | ( ( ( uint32_t )( pAddress ) & 0x003FFFC0 ) >> 6 ) ) )
+/*---------------------------------------------------------------------------*/
+
+#define portYIELD()								_syscall( 0 )
+/* Port Restore is implicit in the platform when the function is returned from the original PSW is automatically replaced. */
+#define portSYSCALL_TASK_YIELD					0
+#define portSYSCALL_RAISE_PRIORITY				1
+/*---------------------------------------------------------------------------*/
+
+/* Critical section management. */
+
+/* Set ICR.CCPN to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+#define portDISABLE_INTERRUPTS()	{																									\
+										uint32_t ulICR;																			\
+										_disable();																						\
+										ulICR = __MFCR( $ICR ); 		/* Get current ICR value. */										\
+										ulICR &= ~portCCPN_MASK;	/* Clear down mask bits. */											\
+										ulICR |= configMAX_SYSCALL_INTERRUPT_PRIORITY; /* Set mask bits to required priority mask. */	\
+										_mtcr( $ICR, ulICR );		/* Write back updated ICR. */										\
+										_isync();																						\
+										_enable();																						\
+									}
+
+/* Clear ICR.CCPN to allow all interrupt priorities. */
+#define portENABLE_INTERRUPTS()		{																	\
+										uint32_t ulICR;											\
+										_disable();														\
+										ulICR = __MFCR( $ICR );		/* Get current ICR value. */		\
+										ulICR &= ~portCCPN_MASK;	/* Clear down mask bits. */			\
+										_mtcr( $ICR, ulICR );		/* Write back updated ICR. */		\
+										_isync();														\
+										_enable();														\
+									}
+
+/* Set ICR.CCPN to uxSavedMaskValue. */
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedMaskValue ) 	{																						\
+																	uint32_t ulICR;																\
+																	_disable();																			\
+																	ulICR = __MFCR( $ICR );		/* Get current ICR value. */							\
+																	ulICR &= ~portCCPN_MASK;	/* Clear down mask bits. */								\
+																	ulICR |= uxSavedMaskValue;	/* Set mask bits to previously saved mask value. */		\
+																	_mtcr( $ICR, ulICR );		/* Write back updated ICR. */							\
+																	_isync();																			\
+																	_enable();																			\
+																}
+
+
+/* Set ICR.CCPN to configMAX_SYSCALL_INTERRUPT_PRIORITY */
+extern uint32_t uxPortSetInterruptMaskFromISR( void );
+#define portSET_INTERRUPT_MASK_FROM_ISR() 	uxPortSetInterruptMaskFromISR()
+
+/* Pend a priority 1 interrupt, which will take care of the context switch. */
+#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) 		if( xHigherPriorityTaskWoken != pdFALSE ) {	 _isync(); }
+
+/*---------------------------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+/*---------------------------------------------------------------------------*/
+
+/*
+ * Port specific clean up macro required to free the CSAs that were consumed by
+ * a task that has since been deleted.
+ */
+void vPortReclaimCSA( uint32_t *pxTCB );
+#define portCLEAN_UP_TCB( pxTCB )		vPortReclaimCSA( ( uint32_t * ) ( pxTCB ) )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _PORTABLE_GCC_TRICORE_PORTMACRO_H_ */

kernel/FreeRTOS/Source/portable/ThirdParty/Community-Supported-Ports/GCC/TriCore_38xa/porttrap.c

@@ -0,0 +1,281 @@
+/*
+ * FreeRTOS Kernel V10.4.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Kernel includes. */
+#include "FreeRTOS.h"
+
+/* Machine includes */
+#include <machine/intrinsics.h>
+#include <machine/cint.h>
+#include <tc38xa/Ifx_reg.h>
+/*---------------------------------------------------------------------------*/
+
+/*
+ * This reference is required by the Save/Restore Context Macros.
+ */
+extern volatile uint32_t *pxCurrentTCB;
+/*-----------------------------------------------------------*/
+
+/*
+ * This file contains base definitions for all of the possible traps in the system.
+ * It is suggested to provide implementations for all of the traps but for
+ * the time being they simply trigger a DEBUG instruction so that it is easy
+ * to see what caused a particular trap.
+ *
+ * Trap Class 6, the SYSCALL, is used exclusively by the operating system.
+ */
+
+/* The Trap Classes. */
+#define portMMU_TRAP										0
+#define portIPT_TRAP										1
+#define portIE_TRAP											2
+#define portCM_TRAP											3
+#define portSBP_TRAP										4
+#define portASSERT_TRAP										5
+#define portNMI_TRAP										7
+
+/* MMU Trap Identifications. */
+#define portTIN_MMU_VIRTUAL_ADDRESS_FILL					0
+#define portTIN_MMU_VIRTUAL_ADDRESS_PROTECTION				1
+
+/* Internal Protection Trap Identifications. */
+#define portTIN_IPT_PRIVILIGED_INSTRUCTION					1
+#define portTIN_IPT_MEMORY_PROTECTION_READ					2
+#define portTIN_IPT_MEMORY_PROTECTION_WRITE					3
+#define portTIN_IPT_MEMORY_PROTECTION_EXECUTION				4
+#define portTIN_IPT_MEMORY_PROTECTION_PERIPHERAL_ACCESS		5
+#define portTIN_IPT_MEMORY_PROTECTION_NULL_ADDRESS			6
+#define portTIN_IPT_MEMORY_PROTECTION_GLOBAL_REGISTER_WRITE_PROTECTION	7
+
+/* Instruction Error Trap Identifications. */
+#define portTIN_IE_ILLEGAL_OPCODE							1
+#define portTIN_IE_UNIMPLEMENTED_OPCODE						2
+#define portTIN_IE_INVALID_OPERAND							3
+#define portTIN_IE_DATA_ADDRESS_ALIGNMENT					4
+#define portTIN_IE_INVALID_LOCAL_MEMORY_ADDRESS				5
+
+/* Context Management Trap Identifications. */
+#define portTIN_CM_FREE_CONTEXT_LIST_DEPLETION				1
+#define portTIN_CM_CALL_DEPTH_OVERFLOW						2
+#define portTIN_CM_CALL_DEPTH_UNDEFLOW						3
+#define portTIN_CM_FREE_CONTEXT_LIST_UNDERFLOW				4
+#define portTIN_CM_CALL_STACK_UNDERFLOW						5
+#define portTIN_CM_CONTEXT_TYPE								6
+#define portTIN_CM_NESTING_ERROR							7
+
+/* System Bus and Peripherals Trap Identifications. */
+#define portTIN_SBP_PROGRAM_FETCH_SYNCHRONOUS_ERROR			1
+#define portTIN_SBP_DATA_ACCESS_SYNCHRONOUS_ERROR			2
+#define portTIN_SBP_DATA_ACCESS_ASYNCHRONOUS_ERROR			3
+#define portTIN_SBP_COPROCESSOR_TRAP_ASYNCHRONOUS_ERROR		4
+#define portTIN_SBP_PROGRAM_MEMORY_INTEGRITY_ERROR			5
+#define portTIN_SBP_DATA_MEMORY_INTEGRITY_ERROR				6
+
+/* Assertion Trap Identifications. */
+#define portTIN_ASSERT_ARITHMETIC_OVERFLOW					1
+#define portTIN_ASSERT_STICKY_ARITHMETIC_OVERFLOW			2
+
+/* Non-maskable Interrupt Trap Identifications. */
+#define portTIN_NMI_NON_MASKABLE_INTERRUPT					0
+/*---------------------------------------------------------------------------*/
+
+void vMMUTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );
+void vInternalProtectionTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );
+void vInstructionErrorTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );
+void vContextManagementTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );
+void vSystemBusAndPeripheralsTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );
+void vAssertionTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );
+void vNonMaskableInterruptTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );
+/*---------------------------------------------------------------------------*/
+
+void vTrapInstallHandlers( void )
+{
+	if( 0 == _install_trap_handler ( portMMU_TRAP, vMMUTrap ) )
+	{
+		_debug();
+	}
+
+	if( 0 == _install_trap_handler ( portIPT_TRAP, vInternalProtectionTrap ) )
+	{
+		_debug();
+	}
+
+	if( 0 == _install_trap_handler ( portIE_TRAP, vInstructionErrorTrap ) )
+	{
+		_debug();
+	}
+
+	if( 0 == _install_trap_handler ( portCM_TRAP, vContextManagementTrap ) )
+	{
+		_debug();
+	}
+
+	if( 0 == _install_trap_handler ( portSBP_TRAP, vSystemBusAndPeripheralsTrap ) )
+	{
+		_debug();
+	}
+
+	if( 0 == _install_trap_handler ( portASSERT_TRAP, vAssertionTrap ) )
+	{
+		_debug();
+	}
+
+	if( 0 == _install_trap_handler ( portNMI_TRAP, vNonMaskableInterruptTrap ) )
+	{
+		_debug();
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vMMUTrap( int iTrapIdentification )
+{
+	switch( iTrapIdentification )
+	{
+	case portTIN_MMU_VIRTUAL_ADDRESS_FILL:
+	case portTIN_MMU_VIRTUAL_ADDRESS_PROTECTION:
+	default:
+		_debug();
+		break;
+	}
+}
+/*---------------------------------------------------------------------------*/
+
+void vInternalProtectionTrap( int iTrapIdentification )
+{
+	/* Deliberate fall through to default. */
+	switch( iTrapIdentification )
+	{
+		case portTIN_IPT_PRIVILIGED_INSTRUCTION:
+			/* Instruction is not allowed at current execution level, eg DISABLE at User-0. */
+
+		case portTIN_IPT_MEMORY_PROTECTION_READ:
+			/* Load word using invalid address. */
+
+		case portTIN_IPT_MEMORY_PROTECTION_WRITE:
+			/* Store Word using invalid address. */
+
+		case portTIN_IPT_MEMORY_PROTECTION_EXECUTION:
+			/* PC jumped to an address outside of the valid range. */
+
+		case portTIN_IPT_MEMORY_PROTECTION_PERIPHERAL_ACCESS:
+			/* Access to a peripheral denied at current execution level. */
+
+		case portTIN_IPT_MEMORY_PROTECTION_NULL_ADDRESS:
+			/* NULL Pointer. */
+
+		case portTIN_IPT_MEMORY_PROTECTION_GLOBAL_REGISTER_WRITE_PROTECTION:
+			/* Tried to modify a global address pointer register. */
+
+		default:
+
+			pxCurrentTCB[ 0 ] = __MFCR( $PCXI );
+			_debug();
+			break;
+	}
+}
+/*---------------------------------------------------------------------------*/
+
+void vInstructionErrorTrap( int iTrapIdentification )
+{
+	/* Deliberate fall through to default. */
+	switch( iTrapIdentification )
+	{
+		case portTIN_IE_ILLEGAL_OPCODE:
+		case portTIN_IE_UNIMPLEMENTED_OPCODE:
+		case portTIN_IE_INVALID_OPERAND:
+		case portTIN_IE_DATA_ADDRESS_ALIGNMENT:
+		case portTIN_IE_INVALID_LOCAL_MEMORY_ADDRESS:
+		default:
+			_debug();
+			break;
+	}
+}
+/*---------------------------------------------------------------------------*/
+
+void vContextManagementTrap( int iTrapIdentification )
+{
+	/* Deliberate fall through to default. */
+	switch( iTrapIdentification )
+	{
+		case portTIN_CM_FREE_CONTEXT_LIST_DEPLETION:
+		case portTIN_CM_CALL_DEPTH_OVERFLOW:
+		case portTIN_CM_CALL_DEPTH_UNDEFLOW:
+		case portTIN_CM_FREE_CONTEXT_LIST_UNDERFLOW:
+		case portTIN_CM_CALL_STACK_UNDERFLOW:
+		case portTIN_CM_CONTEXT_TYPE:
+		case portTIN_CM_NESTING_ERROR:
+		default:
+			_debug();
+			break;
+	}
+}
+/*---------------------------------------------------------------------------*/
+
+void vSystemBusAndPeripheralsTrap( int iTrapIdentification )
+{
+	/* Deliberate fall through to default. */
+	switch( iTrapIdentification )
+	{
+		case portTIN_SBP_PROGRAM_FETCH_SYNCHRONOUS_ERROR:
+		case portTIN_SBP_DATA_ACCESS_SYNCHRONOUS_ERROR:
+		case portTIN_SBP_DATA_ACCESS_ASYNCHRONOUS_ERROR:
+		case portTIN_SBP_COPROCESSOR_TRAP_ASYNCHRONOUS_ERROR:
+		case portTIN_SBP_PROGRAM_MEMORY_INTEGRITY_ERROR:
+		case portTIN_SBP_DATA_MEMORY_INTEGRITY_ERROR:
+		default:
+			_debug();
+			break;
+	}
+}
+/*---------------------------------------------------------------------------*/
+
+void vAssertionTrap( int iTrapIdentification )
+{
+	/* Deliberate fall through to default. */
+	switch( iTrapIdentification )
+	{
+		case portTIN_ASSERT_ARITHMETIC_OVERFLOW:
+		case portTIN_ASSERT_STICKY_ARITHMETIC_OVERFLOW:
+		default:
+			_debug();
+			break;
+	}
+}
+/*---------------------------------------------------------------------------*/
+
+void vNonMaskableInterruptTrap( int iTrapIdentification )
+{
+	/* Deliberate fall through to default. */
+	switch( iTrapIdentification )
+	{
+		case portTIN_NMI_NON_MASKABLE_INTERRUPT:
+		default:
+			_debug();
+			break;
+	}
+}
+/*---------------------------------------------------------------------------*/

kernel/FreeRTOS/Source/portable/ThirdParty/Community-Supported-Ports/GCC/TriCore_38xa/readme.txt

@@ -0,0 +1 @@
+Compile the project with the "-fdollars-in-identifiers" option!!

kernel/FreeRTOS/Source/portable/ThirdParty/Community-Supported-Ports/LICENSE

@@ -0,0 +1 @@
+This repository contains multiple directories, each individually licensed. Please see the LICENSE file in each directory.

kernel/FreeRTOS/Source/portable/ThirdParty/Community-Supported-Ports/README.md

@@ -0,0 +1,19 @@
+## FreeRTOS Community Supported Ports
+
+This repository contains FreeRTOS ports supported by FreeRTOS community members.
+Follow the steps below to contribute a FreeRTOS port to this repository:
+
+1. Write FreeRTOS port for your Compiler and Architecture.
+2. *[Optional]* Create a project in the [FreeRTOS Community Supported Demos Repository](https://github.com/FreeRTOS/FreeRTOS-Community-Supported-Demos/tree/main)
+   for your hardware for running tests as mentioned [here](https://github.com/FreeRTOS/FreeRTOS/blob/main/FreeRTOS/Demo/ThirdParty/Template/README.md).
+3. *[Optional]* Make sure all the tests pass. Add the test results in the Pull Request description.
+4. Add a README file with the following information:
+    1. How to use this port?
+    2. *[Optional]* Link to the test project created in Step 2.
+    3. Any other relevant information.
+5. Raise a pull request to merge the port.
+6. *[Optional]* Raise another PR to merge the test project in the [FreeRTOS Partner Supported Demos Repository](https://github.com/FreeRTOS/FreeRTOS-Partner-Supported-Demos/tree/main).
+
+## License
+
+This repository contains multiple directories, each individually licensed. Please see the LICENSE file in each directory.

kernel/FreeRTOS/Source/portable/ThirdParty/Community-Supported-Ports/Z88DK/Z180/port.c

@@ -0,0 +1,283 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+
+#include <stdlib.h>
+
+#include "include/FreeRTOS.h"
+
+#if __SDCC
+#include "include/sdcc/task.h"
+#elif __SCCZ80
+#include "include/sccz80/task.h"
+#endif
+
+/*-----------------------------------------------------------*/
+
+/* We require the address of the pxCurrentTCB variable, but don't want to know
+any details of its type. */
+
+typedef void TCB_t;
+extern volatile TCB_t * volatile pxCurrentTCB;
+/*-----------------------------------------------------------*/
+
+/*
+ * Macro to save all the general purpose registers, the save the stack pointer
+ * into the TCB.
+ *
+ * The first thing we do is save the flags then disable interrupts. This is to
+ * guard our stack against having a context switch interrupt after we have already
+ * pushed the registers onto the stack.
+ *
+ * The interrupts will have been disabled during the call to portSAVE_CONTEXT()
+ * so we need not worry about reading/writing to the stack pointer.
+ */
+
+#define configTICK_RATE_HZ              (256)               /* Timer configured */
+#define configISR_ORG                   ASMPC               /* ISR relocation */
+#define configISR_IVT                   0xFFE6              /* PRT1 address */
+
+#ifdef __SCCZ80
+
+#define configSETUP_TIMER_INTERRUPT()                           \
+    do{                                                         \
+        asm(                                                    \
+            "EXTERN __CPU_CLOCK                             \n" \
+            "EXTERN RLDR1L, RLDR1H                          \n" \
+            "EXTERN TCR, TCR_TIE1, TCR_TDE1                 \n" \
+            "ld de,_timer_isr                               \n" \
+            "ld hl,"string(configISR_IVT)" ; PRT1 address   \n" \
+            "ld (hl),e                                      \n" \
+            "inc hl                                         \n" \
+            "ld (hl),d                                      \n" \
+            "; we do configTICK_RATE_HZ ticks per second    \n" \
+            "ld hl,__CPU_CLOCK/"string(configTICK_RATE_HZ)"/20-1 \n" \
+            "out0(RLDR1L),l                                 \n" \
+            "out0(RLDR1H),h                                 \n" \
+            "in0 a,(TCR)                                    \n" \
+            "or TCR_TIE1|TCR_TDE1                           \n" \
+            "out0 (TCR),a                                   \n" \
+            );                                                  \
+    }while(0)
+
+#define configRESET_TIMER_INTERRUPT()                           \
+    do{                                                         \
+        asm(                                                    \
+            "EXTERN TCR, TMDR1L                             \n" \
+            "in0 a,(TCR)                                    \n" \
+            "in0 a,(TMDR1L)                                 \n" \
+            );                                                  \
+    }while(0)
+
+#define configSTOP_TIMER_INTERRUPT()                            \
+    do{                                                         \
+        asm(                                                    \
+            "EXTERN TCR, TCR_TIE1, TCR_TDE1                 \n" \
+            "; disable down counting and interrupts for PRT1\n" \
+            "in0 a,(TCR)                                    \n" \
+            "xor TCR_TIE1|TCR_TDE1                          \n" \
+            "out0 (TCR),a                                   \n" \
+            );                                                  \
+    }while(0)
+
+#endif
+
+#ifdef __SDCC
+
+#define configSETUP_TIMER_INTERRUPT()                           \
+    do{                                                         \
+        __asm                                                   \
+            EXTERN __CPU_CLOCK                                  \
+            EXTERN RLDR1L, RLDR1H                               \
+            EXTERN TCR, TCR_TIE1, TCR_TDE1                      \
+            ; address of ISR                                    \
+            ld de,_timer_isr                                    \
+            ld hl,configISR_IVT ; PRT1 address                  \
+            ld (hl),e                                           \
+            inc hl                                              \
+            ld (hl),d                                           \
+            ; we do configTICK_RATE_HZ ticks per second         \
+            ld hl,__CPU_CLOCK/configTICK_RATE_HZ/20-1           \
+            out0(RLDR1L),l                                      \
+            out0(RLDR1H),h                                      \
+            ; enable down counting and interrupts for PRT1      \
+            in0 a,(TCR)                                         \
+            or TCR_TIE1|TCR_TDE1                                \
+            out0 (TCR),a                                        \
+        __endasm;                                               \
+    }while(0)
+
+#define configRESET_TIMER_INTERRUPT()                           \
+    do{                                                         \
+        __asm                                                   \
+            EXTERN TCR, TMDR1L                                  \
+            ; reset interrupt for PRT1                          \
+            in0 a,(TCR)                                         \
+            in0 a,(TMDR1L)                                      \
+        __endasm;                                               \
+    }while(0)
+
+#define configSTOP_TIMER_INTERRUPT()                            \
+    do{                                                         \
+        __asm                                                   \
+            EXTERN TCR, TCR_TIE1, TCR_TDE1                      \
+            ; disable down counting and interrupts for PRT1     \
+            in0 a,(TCR)                                         \
+            xor TCR_TIE1|TCR_TDE1                               \
+            out0 (TCR),a                                        \
+        __endasm;                                               \
+    }while(0)
+
+#endif
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Perform hardware setup to enable ticks from Timer.
+ */
+static void prvSetupTimerInterrupt( void ) __preserves_regs(iyh,iyl);
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+    /* Place the parameter on the stack in the expected location. */
+    *pxTopOfStack-- = ( StackType_t ) pvParameters;
+
+    /* Place the task return address on stack. Not used */
+    *pxTopOfStack-- = ( StackType_t ) 0;
+
+    /* The start of the task code will be popped off the stack last, so place
+    it on first. */
+    *pxTopOfStack-- = ( StackType_t ) pxCode;
+
+    /* Now the registers. */
+    *pxTopOfStack-- = ( StackType_t ) 0xAFAF;   /* AF  */
+    *pxTopOfStack-- = ( StackType_t ) 0x0404;   /* IF  */
+    *pxTopOfStack-- = ( StackType_t ) 0xBCBC;   /* BC  */
+    *pxTopOfStack-- = ( StackType_t ) 0xDEDE;   /* DE  */
+    *pxTopOfStack-- = ( StackType_t ) 0xEFEF;   /* HL  */
+    *pxTopOfStack-- = ( StackType_t ) 0xFAFA;   /* AF' */
+    *pxTopOfStack-- = ( StackType_t ) 0xCBCB;   /* BC' */
+    *pxTopOfStack-- = ( StackType_t ) 0xEDED;   /* DE' */
+    *pxTopOfStack-- = ( StackType_t ) 0xFEFE;   /* HL' */
+    *pxTopOfStack-- = ( StackType_t ) 0xCEFA;   /* IX  */
+    *pxTopOfStack   = ( StackType_t ) 0xADDE;   /* IY  */
+
+    return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void ) __preserves_regs(a,b,c,d,e,iyh,iyl) __naked
+{
+    /* Setup the relevant timer hardware to generate the tick. */
+    prvSetupTimerInterrupt();
+
+    /* Restore the context of the first task that is going to run. */
+    portRESTORE_CONTEXT();
+
+    /* Should not get here. */
+    return pdFALSE;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void ) __preserves_regs(b,c,d,e,h,l,iyh,iyl)
+{
+    /*
+     * It is unlikely that the Z80 port will get stopped.
+     * If required simply disable the tick interrupt here.
+     */
+    configSTOP_TIMER_INTERRUPT();
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Manual context switch.  The first thing we do is save the registers so we
+ * can use a naked attribute. This is called by the application, so we don't have
+ * to check which bank is loaded.
+ */
+void vPortYield( void ) __preserves_regs(a,b,c,d,e,h,l,iyh,iyl) __naked
+{
+    portSAVE_CONTEXT();
+    vTaskSwitchContext();
+    portRESTORE_CONTEXT();
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Manual context switch callable from ISRs. The first thing we do is save
+ * the registers so we can use a naked attribute.
+ */
+void vPortYieldFromISR(void)  __preserves_regs(a,b,c,d,e,h,l,iyh,iyl) __naked
+void vPortYieldFromISR(void)
+{
+    portSAVE_CONTEXT_IN_ISR();
+    vTaskSwitchContext();
+    portRESTORE_CONTEXT_IN_ISR();
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Initialize Timer (PRT1 for YAZ180, and SCZ180 HBIOS).
+ */
+void prvSetupTimerInterrupt( void ) __preserves_regs(iyh,iyl)
+{
+    configSETUP_TIMER_INTERRUPT();
+}
+/*-----------------------------------------------------------*/
+
+void timer_isr(void) __preserves_regs(a,b,c,d,e,h,l,iyh,iyl) __naked
+{
+#if configUSE_PREEMPTION == 1
+    /*
+     * Tick ISR for preemptive scheduler.  We can use a naked attribute as
+     * the context is saved at the start of timer_isr().  The tick
+     * count is incremented after the context is saved.
+     *
+     * Context switch function used by the tick.  This must be identical to
+     * vPortYield() from the call to vTaskSwitchContext() onwards.  The only
+     * difference from vPortYield() is the tick count is incremented as the
+     * call comes from the tick ISR.
+     */
+    portSAVE_CONTEXT_IN_ISR();
+    configRESET_TIMER_INTERRUPT();
+    xTaskIncrementTick();
+    vTaskSwitchContext();
+    portRESTORE_CONTEXT_IN_ISR();
+#else
+    /*
+     * Tick ISR for the cooperative scheduler.  All this does is increment the
+     * tick count.  We don't need to switch context, this can only be done by
+     * manual calls to taskYIELD();
+     */
+    portSAVE_CONTEXT_IN_ISR();
+    configRESET_TIMER_INTERRUPT();
+    xTaskIncrementTick();
+    portRESTORE_CONTEXT_IN_ISR();
+#endif
+} // configUSE_PREEMPTION

kernel/FreeRTOS/Source/portable/ThirdParty/Community-Supported-Ports/Z88DK/Z180/portmacro.h

@@ -0,0 +1,431 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given Z80 (Z180, Z80N) hardware and SCCZ80 or SDCC compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR                    char
+#define portFLOAT                   float
+#define portDOUBLE                  double
+#define portLONG                    long
+#define portSHORT                   int
+
+typedef uint16_t StackType_t;
+typedef int8_t BaseType_t;
+typedef uint8_t UBaseType_t;
+
+#if configUSE_16_BIT_TICKS == 1
+    typedef uint16_t TickType_t;
+    #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+    typedef uint32_t TickType_t;
+    #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* General purpose stringify macros. */
+
+#define string(a) __string(a)
+#define __string(a) #a
+/*-----------------------------------------------------------*/
+
+/* Critical section management using sccz80 compiler. */
+
+#ifdef __SCCZ80
+
+#define portENTER_CRITICAL()        \
+    do{                             \
+        asm(                        \
+            "ld a,i             \n" \
+            "di                 \n" \
+            "push af            \n" \
+            );                      \
+    }while(0)
+
+#define portEXIT_CRITICAL()         \
+    do{                             \
+        asm(                        \
+            "pop af             \n" \
+            "; di    ; unneeded \n" \
+            "jp PO,ASMPC+4      \n" \
+            "ei                 \n" \
+            );                      \
+    }while(0)
+
+#define portDISABLE_INTERRUPTS()    \
+    do{                             \
+        asm(                        \
+            "di                 \n" \
+            );                      \
+    }while(0)
+
+#define portENABLE_INTERRUPTS()     \
+    do{                             \
+        asm(                        \
+            "ei                 \n" \
+            );                      \
+    }while(0)
+
+#define portNOP()                   \
+    do{                             \
+        asm(                        \
+            "nop                \n" \
+            );                      \
+    }while(0)
+
+/*
+ * Macros to save all the registers, and save the stack pointer into the TCB.
+ */
+
+#define portSAVE_CONTEXT()          \
+    do{                             \
+        asm(                        \
+            "push af            \n" \
+            "ld a,i             \n" \
+            "di                 \n" \
+            "push af ; iff1:iff2\n" \
+            "push bc            \n" \
+            "push de            \n" \
+            "push hl            \n" \
+            "exx                \n" \
+            "ex af,af           \n" \
+            "push af            \n" \
+            "push bc            \n" \
+            "push de            \n" \
+            "push hl            \n" \
+            "push ix            \n" \
+            "push iy            \n" \
+            "ld hl,0            \n" \
+            "add hl,sp          \n" \
+            "ld de,(_pxCurrentTCB)  \n"\
+            "ex de,hl           \n" \
+            "ld (hl),e          \n" \
+            "inc hl             \n" \
+            "ld (hl),d          \n" \
+            );                      \
+    }while(0)
+
+#define portRESTORE_CONTEXT()       \
+    do{                             \
+        asm(                        \
+            "ld hl,(_pxCurrentTCB)  \n" \
+            "ld e,(hl)          \n" \
+            "inc hl             \n" \
+            "ld d,(hl)          \n" \
+            "ex de,hl           \n" \
+            "ld sp,hl           \n" \
+            "pop iy             \n" \
+            "pop ix             \n" \
+            "pop hl             \n" \
+            "pop de             \n" \
+            "pop bc             \n" \
+            "pop af             \n" \
+            "ex af,af           \n" \
+            "exx                \n" \
+            "pop hl             \n" \
+            "pop de             \n" \
+            "pop bc             \n" \
+            "pop af  ; iff1:iff2\n" \
+            "; di    ; unneeded \n" \
+            "jp PO,ASMPC+4      \n" \
+            "ei                 \n" \
+            "pop af             \n" \
+            "ret                \n" \
+            );                      \
+    }while(0)
+
+#define portSAVE_CONTEXT_IN_ISR()   \
+    do{                             \
+        asm(                        \
+            "PHASE "string(configISR_ORG)"  \n" \
+            "._timer_isr_start  \n" \
+            "push af            \n" \
+            "ld a,0x7F          \n" \
+            "inc a   ; set PE   \n" \
+            "push af ; iff1:iff2\n" \
+            "push bc            \n" \
+            "push de            \n" \
+            "push hl            \n" \
+            "exx                \n" \
+            "ex af,af           \n" \
+            "push af            \n" \
+            "push bc            \n" \
+            "push de            \n" \
+            "push hl            \n" \
+            "push ix            \n" \
+            "push iy            \n" \
+            "ld hl,0            \n" \
+            "add hl,sp          \n" \
+            "ld de,(_pxCurrentTCB)  \n" \
+            "ex de,hl           \n" \
+            "ld (hl),e          \n" \
+            "inc hl             \n" \
+            "ld (hl),d          \n" \
+            );                      \
+    }while(0)
+
+#define portRESTORE_CONTEXT_IN_ISR()\
+    do{                             \
+        asm(                        \
+            "ld hl,(_pxCurrentTCB)  \n" \
+            "ld e,(hl)          \n" \
+            "inc hl             \n" \
+            "ld d,(hl)          \n" \
+            "ex de,hl           \n" \
+            "ld sp,hl           \n" \
+            "pop iy             \n" \
+            "pop ix             \n" \
+            "pop hl             \n" \
+            "pop de             \n" \
+            "pop bc             \n" \
+            "pop af             \n" \
+            "ex af,af           \n" \
+            "exx                \n" \
+            "pop hl             \n" \
+            "pop de             \n" \
+            "pop bc             \n" \
+            "pop af  ; iff1:iff2\n" \
+            "; di    ; unneeded \n" \
+            "jp PO,ASMPC+4      \n" \
+            "ei                 \n" \
+            "pop af             \n" \
+            "reti               \n" \
+            "._timer_isr_end    \n" \
+            "DEPHASE            \n" \
+            );                      \
+    }while(0)
+
+#endif
+/*-----------------------------------------------------------*/
+
+/* Critical section management using sdcc compiler. */
+
+#ifdef __SDCC
+
+#define portENTER_CRITICAL()        \
+    do{                             \
+        __asm                       \
+            ld a,i                  \
+            di                      \
+            push af                 \
+        __endasm;                   \
+    }while(0)
+
+#define portEXIT_CRITICAL()         \
+    do{                             \
+        __asm                       \
+            pop af                  \
+            ; di    ; unneeded      \
+            jp PO,ASMPC+4           \
+            ei                      \
+        __endasm;                   \
+    }while(0)
+
+#define portDISABLE_INTERRUPTS()    \
+    do{                             \
+        __asm                       \
+            di                      \
+        __endasm;                   \
+    }while(0)
+
+#define portENABLE_INTERRUPTS()     \
+    do{                             \
+        __asm                       \
+            ei                      \
+        __endasm;                   \
+    }while(0)
+
+#define portNOP()                   \
+    do{                             \
+        __asm                       \
+            nop                     \
+        __endasm;                   \
+    }while(0)
+
+/*
+ * Macros to save all the registers, and save the stack pointer into the TCB.
+ */
+
+#define portSAVE_CONTEXT()          \
+    do{                             \
+        __asm                       \
+            push af                 \
+            ld a,i                  \
+            di                      \
+            push af ; iff1:iff2     \
+            push bc                 \
+            push de                 \
+            push hl                 \
+            exx                     \
+            ex af,af                \
+            push af                 \
+            push bc                 \
+            push de                 \
+            push hl                 \
+            push ix                 \
+            push iy                 \
+            ld hl,0                 \
+            add hl,sp               \
+            ld de,(_pxCurrentTCB)   \
+            ex de,hl                \
+            ld (hl),e               \
+            inc hl                  \
+            ld (hl),d               \
+        __endasm;                   \
+    }while(0)
+
+#define portRESTORE_CONTEXT()       \
+    do{                             \
+        __asm                       \
+            ld hl,(_pxCurrentTCB)   \
+            ld e,(hl)               \
+            inc hl                  \
+            ld d,(hl)               \
+            ex de,hl                \
+            ld sp,hl                \
+            pop iy                  \
+            pop ix                  \
+            pop hl                  \
+            pop de                  \
+            pop bc                  \
+            pop af                  \
+            ex af,af                \
+            exx                     \
+            pop hl                  \
+            pop de                  \
+            pop bc                  \
+            pop af  ; iff1:iff2     \
+            ; di    ; unneeded      \
+            jp PO,ASMPC+4           \
+            ei                      \
+            pop af                  \
+            ret                     \
+        __endasm;                   \
+    }while(0)
+
+#define portSAVE_CONTEXT_IN_ISR()   \
+    do{                             \
+        __asm                       \
+            PHASE configISR_ORG     \
+            _timer_isr_start:       \
+            push af                 \
+            ld a,0x7F               \
+            inc a   ; set PE        \
+            push af ; iff1:iff2     \
+            push bc                 \
+            push de                 \
+            push hl                 \
+            exx                     \
+            ex af,af                \
+            push af                 \
+            push bc                 \
+            push de                 \
+            push hl                 \
+            push ix                 \
+            push iy                 \
+            ld hl,0                 \
+            add hl,sp               \
+            ld de,(_pxCurrentTCB)   \
+            ex de,hl                \
+            ld (hl),e               \
+            inc hl                  \
+            ld (hl),d               \
+        __endasm;                   \
+    }while(0)
+
+#define portRESTORE_CONTEXT_IN_ISR()\
+    do{                             \
+        __asm                       \
+            ld hl,(_pxCurrentTCB)   \
+            ld e,(hl)               \
+            inc hl                  \
+            ld d,(hl)               \
+            ex de,hl                \
+            ld sp,hl                \
+            pop iy                  \
+            pop ix                  \
+            pop hl                  \
+            pop de                  \
+            pop bc                  \
+            pop af                  \
+            ex af,af                \
+            exx                     \
+            pop hl                  \
+            pop de                  \
+            pop bc                  \
+            pop af  ; iff1:iff2     \
+            ; di    ; unneeded      \
+            jp PO,ASMPC+4           \
+            ei                      \
+            pop af                  \
+            reti                    \
+            _timer_isr_end:         \
+            DEPHASE                 \
+        __endasm;                   \
+    }while(0)
+
+#endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+
+#define portSTACK_GROWTH            ( -1 )
+#define portTICK_PERIOD_MS          ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT          1
+/*-----------------------------------------------------------*/
+
+/* Kernel utilities. */
+extern void vPortYield( void );
+#define portYIELD()                 vPortYield()
+
+extern void vPortYieldFromISR( void );
+#define portYIELD_FROM_ISR()        vPortYieldFromISR()
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */

kernel/FreeRTOS/Source/portable/ThirdParty/Community-Supported-Ports/Z88DK/Z180/readme.md

@@ -0,0 +1,13 @@
+<h1>z180 support</h1>
+
+Description
+-----------
+This PR establishes support for a Zilog z180 port, using the Programmable Reload Timer 1, configured at 256 Hz.
+
+Because of the generality of the z180, the address of the Interrupt Vector for PRT1 is configurable, and must be configured by the `crt0.asm` outside of this port. A configuration assumption has been made.
+
+The two compilers ([used by the z88dk](https://github.com/z88dk/z88dk)) are supported. The sccz80 compiler and the sdcc compiler. The PR is located under Z88dk.
+
+Background
+-----------
+This PR is based on running code for the [SC130](https://smallcomputercentral.wordpress.com/sc130-z180-motherboard/)/[SC131](https://smallcomputercentral.wordpress.com/sc131-z180-pocket-computer/) and [YAZ180](https://github.com/feilipu/yaz180) platforms, and is maintained by the z88dk team in this [z88dk-libraries](https://github.com/feilipu/z88dk-libraries/tree/master/freertos) repository.

kernel/FreeRTOS/Source/portable/ThirdParty/GCC/ARC_EM_HS/arc_freertos_exceptions.c

@@ -0,0 +1,52 @@
+/*
+ * FreeRTOS Kernel V10.5.1
+ * Copyright (C) 2020 Synopsys, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/**
+ * \file
+ * \brief   exception processing for freertos
+ */
+
+/* #include "embARC.h" */
+
+#include "arc_freertos_exceptions.h"
+
+#ifdef __GNU__
+    extern void gnu_printf_setup( void );
+#endif
+
+/**
+ * \brief  freertos related cpu exception initialization, all the interrupts handled by freertos must be not
+ * fast irqs. If fiq is needed, please install the default firq_exc_entry or your own fast irq entry into
+ * the specific interrupt exception.
+ */
+void freertos_exc_init( void )
+{
+    #ifdef __GNU__
+        gnu_printf_setup();
+    #endif
+}

kernel/FreeRTOS/Source/portable/ThirdParty/GCC/ARC_EM_HS/arc_freertos_exceptions.h

@@ -0,0 +1,46 @@
+/*
+ * FreeRTOS Kernel V10.5.1
+ * Copyright (C) 2020 Synopsys, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef ARC_FREERTOS_EXCEPTIONS_H
+#define ARC_FREERTOS_EXCEPTIONS_H
+
+/*
+ * here, all arc cpu exceptions share the same entry, also for all interrupt
+ * exceptions
+ */
+extern void exc_entry_cpu( void ); /* cpu exception entry for freertos */
+extern void exc_entry_int( void ); /* int exception entry for freertos */
+
+/* task dispatch functions in .s */
+extern void start_r( void );
+extern void start_dispatch();
+extern void dispatch();
+
+extern void freertos_exc_init( void );
+
+#endif /* ARC_FREERTOS_EXCEPTIONS_H */

kernel/FreeRTOS/Source/portable/ThirdParty/GCC/ARC_EM_HS/arc_support.s

@@ -0,0 +1,522 @@
+/*
+ * FreeRTOS Kernel V10.5.1
+ * Copyright (C) 2020 Synopsys, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/**
+ * \file
+ * \ingroup OS_FREERTOS
+ * \brief  freertos support for arc processor
+ *	like task dispatcher, interrupt handler
+ */
+/** @cond OS_FREERTOS_ASM_ARC_SUPPORT */
+
+/*
+ * core-dependent part in assemble language (for arc)
+ */
+#define __ASSEMBLY__
+#include "arc/arc.h"
+#include "arc/arc_asm_common.h"
+
+/*
+ *  task dispatcher
+ *
+ */
+	.text
+	.align 4
+	.global dispatch
+dispatch:
+/*
+ *  the pre-conditions of this routine are task context, CPU is
+ *  locked, dispatch is enabled.
+ */
+	SAVE_NONSCRATCH_REGS		/* save callee save registers */
+	mov	r1, dispatch_r
+	PUSH	r1			/* save return address */
+	ld	r0, [pxCurrentTCB]
+	bl	dispatcher
+
+/* return routine when task dispatch happened in task context */
+dispatch_r:
+	RESTORE_NONSCRATCH_REGS		/* recover registers */
+	j	[blink]
+
+/*
+ *  start dispatch
+ */
+	.global start_dispatch
+	.align 4
+start_dispatch:
+/*
+ *  this routine is called in the non-task context during the startup of the kernel
+ *  , and all the interrupts are locked.
+ *
+ *  when the dispatcher is called, the cpu is locked, no nest exception (CPU exception/interrupt).
+ *  In target_initialize, all interrupt priority mask should be cleared, cpu should be
+ *  locked, the interrupts outside the kernel such as fiq can be
+ *  enabled.
+ */
+	clri
+	mov	r0, 0
+	st	r0, [exc_nest_count]
+	b	dispatcher_0
+/*
+ *  dispatcher
+ */
+dispatcher:
+	ld	r1, [ulCriticalNesting]
+	PUSH	r1			/* save critical nesting */
+	st	sp, [r0]		/* save stack pointer of current task, r0->pxCurrentTCB */
+	jl	vTaskSwitchContext	/* change the value of pxCurrentTCB */
+/*
+ *  before dispatcher is called, task context | cpu locked | dispatch enabled
+ *  should be satisfied. In this routine, the processor will jump
+ *  into the entry of next to run task
+ *
+ *  i.e. kernel mode, IRQ disabled, dispatch enabled
+ */
+dispatcher_0:
+	ld	r1, [pxCurrentTCB]
+	ld	sp, [r1]	/* recover task stack */
+#if ARC_FEATURE_STACK_CHECK
+#if ARC_FEATURE_SEC_PRESENT
+	lr r0, [AUX_SEC_STAT]
+	bclr r0, r0, AUX_SEC_STAT_BIT_SSC
+	sflag r0
+#else
+	lr r0, [AUX_STATUS32]
+	bclr r0, r0, AUX_STATUS_BIT_SC
+	kflag r0
+#endif
+	jl	vPortSetStackCheck
+#if ARC_FEATURE_SEC_PRESENT
+	lr r0, [AUX_SEC_STAT]
+	bset r0, r0, AUX_SEC_STAT_BIT_SSC
+	sflag r0
+#else
+	lr r0, [AUX_STATUS32]
+	bset r0, r0, AUX_STATUS_BIT_SC
+	kflag r0
+#endif
+#endif
+	POP	r0		/* get critical nesting */
+	st	r0, [ulCriticalNesting]
+	POP	r0		/* get return address  */
+	j	[r0]
+
+/*
+ *  task startup routine
+ *
+ */
+	.text
+	.global start_r
+	.align 4
+start_r:
+	seti	/* unlock cpu */
+	mov	blink, vPortEndTask	/* set return address */
+	POP	r1			/* get task function body */
+	POP	r0			/* get task parameters */
+	j	[r1]
+
+/****** exceptions and interrupts handing ******/
+/****** entry for exception handling ******/
+	.global exc_entry_cpu
+	.align 4
+exc_entry_cpu:
+
+	EXCEPTION_PROLOGUE
+
+	mov	blink,	sp
+	mov	r3, sp		/* as exception handler's para(p_excinfo) */
+
+	ld	r0, [exc_nest_count]
+	add	r1, r0, 1
+	st	r1, [exc_nest_count]
+	brne	r0, 0, exc_handler_1
+/* change to exception stack if interrupt happened in task context */
+	mov	sp, _e_stack
+exc_handler_1:
+	PUSH	blink
+
+	lr	r0, [AUX_ECR]
+	lsr	r0, r0, 16
+	mov	r1, exc_int_handler_table
+	ld.as	r2, [r1, r0]
+
+	mov	r0, r3
+	jl	[r2]		/* !!!!jump to exception handler where interrupts are not allowed! */
+
+/* interrupts are not allowed */
+ret_exc:
+	POP	sp
+	mov	r1, exc_nest_count
+	ld	r0, [r1]
+	sub	r0, r0, 1
+	st 	r0, [r1]
+	brne	r0, 0, ret_exc_1 /* nest exception case */
+	lr	r1, [AUX_IRQ_ACT] /* nest interrupt case */
+	brne	r1, 0, ret_exc_1
+
+	ld	r0, [context_switch_reqflg]
+	brne	r0, 0, ret_exc_2
+ret_exc_1:	/* return from non-task context, interrupts or exceptions are nested */
+
+	EXCEPTION_EPILOGUE
+	rtie
+
+/* there is a dispatch request */
+ret_exc_2:
+	/* clear dispatch request */
+	mov	r0, 0
+	st	r0, [context_switch_reqflg]
+
+	ld	r0, [pxCurrentTCB]
+	breq	r0, 0, ret_exc_1
+
+	SAVE_CALLEE_REGS	/* save callee save registers */
+
+	lr	r0, [AUX_STATUS32]
+	bclr	r0, r0, AUX_STATUS_BIT_AE	/* clear exception bit */
+	kflag	r0
+
+	mov	r1, ret_exc_r	/* save return address */
+	PUSH	r1
+
+	bl	dispatcher	/* r0->pxCurrentTCB */
+
+ret_exc_r:
+	/* recover exception status */
+	lr	r0, [AUX_STATUS32]
+	bset	r0, r0, AUX_STATUS_BIT_AE
+	kflag	r0
+
+	RESTORE_CALLEE_REGS	/* recover registers */
+	EXCEPTION_EPILOGUE
+	rtie
+
+/****** entry for normal interrupt exception handling ******/
+	.global exc_entry_int	/* entry for interrupt handling */
+	.align 4
+exc_entry_int:
+#if ARC_FEATURE_FIRQ == 1
+#if ARC_FEATURE_RGF_NUM_BANKS > 1
+	lr	r0, [AUX_IRQ_ACT]			/*  check whether it is P0 interrupt */
+	btst	r0, 0
+	jnz	exc_entry_firq
+#else
+	PUSH	r10
+	lr	r10, [AUX_IRQ_ACT]
+	btst	r10, 0
+	POP	r10
+	jnz	exc_entry_firq
+#endif
+#endif
+	INTERRUPT_PROLOGUE
+
+	mov	blink, sp
+
+	clri	/* disable interrupt */
+	ld	r3, [exc_nest_count]
+	add	r2, r3, 1
+	st	r2, [exc_nest_count]
+	seti	/* enable higher priority interrupt */
+
+	brne	r3, 0, irq_handler_1
+/* change to exception stack if interrupt happened in task context */
+	mov	sp, _e_stack
+#if ARC_FEATURE_STACK_CHECK
+#if ARC_FEATURE_SEC_PRESENT
+	lr r0, [AUX_SEC_STAT]
+	bclr r0, r0, AUX_SEC_STAT_BIT_SSC
+	sflag r0
+#else
+	lr r0, [AUX_STATUS32]
+	bclr r0, r0, AUX_STATUS_BIT_SC
+	kflag r0
+#endif
+#endif
+irq_handler_1:
+	PUSH	blink
+
+	lr	r0, [AUX_IRQ_CAUSE]
+	mov	r1, exc_int_handler_table
+	ld.as	r2, [r1, r0]	/* r2 = exc_int_handler_table + irqno *4 */
+/* handle software triggered interrupt */
+	lr	r3, [AUX_IRQ_HINT]
+	cmp	r3, r0
+	bne.d irq_hint_handled
+	xor	r3, r3, r3
+	sr	r3, [AUX_IRQ_HINT]
+irq_hint_handled:
+
+	jl	[r2]		/* jump to interrupt handler */
+/* no interrupts are allowed from here */
+ret_int:
+	clri	/* disable interrupt */
+
+	POP	sp
+	mov	r1, exc_nest_count
+	ld	r0, [r1]
+	sub	r0, r0, 1
+	st	r0, [r1]
+/* if there are multi-bits set in IRQ_ACT, it's still in nest interrupt */
+	lr	r0, [AUX_IRQ_CAUSE]
+	sr	r0, [AUX_IRQ_SELECT]
+	lr 	r3, [AUX_IRQ_PRIORITY]
+	lr	r1, [AUX_IRQ_ACT]
+	bclr	r2, r1, r3
+	brne	r2, 0, ret_int_1
+
+	ld	r0, [context_switch_reqflg]
+	brne	r0, 0, ret_int_2
+ret_int_1:	/* return from non-task context */
+	INTERRUPT_EPILOGUE
+	rtie
+/* there is a dispatch request */
+ret_int_2:
+	/* clear dispatch request */
+	mov	r0, 0
+	st	r0, [context_switch_reqflg]
+
+	ld	r0, [pxCurrentTCB]
+	breq 	r0, 0, ret_int_1
+
+/* r1 has old AUX_IRQ_ACT */
+	PUSH	r1
+/* clear related bits in IRQ_ACT manually to simulate a irq return  */
+	sr	r2, [AUX_IRQ_ACT]
+
+	SAVE_CALLEE_REGS	/* save callee save registers */
+	mov	r1, ret_int_r	/* save return address */
+	PUSH	r1
+
+	bl	dispatcher	/* r0->pxCurrentTCB */
+
+ret_int_r:
+	RESTORE_CALLEE_REGS	/* recover registers */
+	POPAX	AUX_IRQ_ACT
+	INTERRUPT_EPILOGUE
+	rtie
+
+#if ARC_FEATURE_FIRQ == 1
+	.global exc_entry_firq
+	.align 4
+exc_entry_firq:
+#if ARC_FEATURE_STACK_CHECK && ARC_FEATURE_RGF_NUM_BANKS > 1
+#if ARC_FEATURE_SEC_PRESENT
+	lr r0, [AUX_SEC_STAT]
+	bclr r0, r0, AUX_SEC_STAT_BIT_SSC
+	sflag r0
+#else
+	lr r0, [AUX_STATUS32]
+	bclr r0, r0, AUX_STATUS_BIT_SC
+	kflag r0
+#endif
+#endif
+	SAVE_FIQ_EXC_REGS
+
+	mov	blink, sp
+
+	ld	r3, [exc_nest_count]
+	add	r2, r3, 1
+	st	r2, [exc_nest_count]
+
+	brne	r3, 0, firq_handler_1
+#if ARC_FEATURE_STACK_CHECK && ARC_FEATURE_RGF_NUM_BANKS == 1
+#if ARC_FEATURE_SEC_PRESENT
+	lr r0, [AUX_SEC_STAT]
+	bclr r0, r0, AUX_SEC_STAT_BIT_SSC
+	sflag r0
+#else
+	lr r0, [AUX_STATUS32]
+	bclr r0, r0, AUX_STATUS_BIT_SC
+	kflag r0
+#endif
+#endif
+/* change to exception stack if interrupt happened in task context */
+	mov	sp, _e_stack
+firq_handler_1:
+	PUSH	blink
+
+	lr	r0, [AUX_IRQ_CAUSE]
+	mov	r1, exc_int_handler_table
+	ld.as	r2, [r1, r0]	/* r2 = exc_int_handler_table + irqno *4 */
+/* handle software triggered interrupt */
+	lr	r3, [AUX_IRQ_HINT]
+	brne	r3, r0, firq_hint_handled
+	xor	r3, r3, r3
+	sr	r3, [AUX_IRQ_HINT]
+firq_hint_handled:
+
+	jl	[r2]		/* jump to interrupt handler */
+/* no interrupts are allowed from here */
+ret_firq:
+	clri
+	POP	sp
+
+	mov	r1, exc_nest_count
+	ld	r0, [r1]
+	sub	r0, r0, 1
+	st	r0, [r1]
+/* if there are multi-bits set in IRQ_ACT, it's still in nest interrupt */
+	lr	r1, [AUX_IRQ_ACT]
+	bclr	r1, r1, 0
+	brne	r1, 0, ret_firq_1
+
+	ld	r0, [context_switch_reqflg]
+	brne	r0, 0, ret_firq_2
+ret_firq_1:	/* return from non-task context */
+	RESTORE_FIQ_EXC_REGS
+	rtie
+/* there is a dispatch request */
+ret_firq_2:
+	/* clear dispatch request */
+	mov	r0, 0
+	st	r0, [context_switch_reqflg]
+
+	ld	r0, [pxCurrentTCB]
+	breq 	r0, 0, ret_firq_1
+
+/* reconstruct the interruptted context
+ * When ARC_FEATURE_RGF_BANKED_REGS >= 16 (16, 32), sp is banked
+ * so need to restore the fast irq stack.
+ */
+#if ARC_FEATURE_RGF_BANKED_REGS >= 16
+	RESTORE_LP_REGS
+#if ARC_FEATURE_CODE_DENSITY
+	RESTORE_CODE_DENSITY
+#endif
+	RESTORE_R58_R59
+#endif
+
+/* when BANKED_REGS == 16, r4-r9 wiil be also saved in fast irq stack
+ * so pop them out
+ */
+#if  ARC_FEATURE_RGF_BANKED_REGS == 16 && !defined(ARC_FEATURE_RF16)
+	POP		r9
+	POP		r8
+	POP		r7
+	POP		r6
+	POP		r5
+	POP		r4
+#endif
+
+/* for other cases, unbanked regs are already in interrupted context's stack,
+ * so just need to save and pop the banked regs
+ */
+
+/* save the interruptted context */
+#if ARC_FEATURE_RGF_BANKED_REGS > 0
+/* switch back to bank0  */
+	lr r0, [AUX_STATUS32]
+	bic     r0, r0, 0x70000
+	kflag   r0
+#endif
+
+#if ARC_FEATURE_RGF_BANKED_REGS == 4
+/* r4 - r12, gp, fp, r30, blink already saved */
+	PUSH	r0
+	PUSH	r1
+	PUSH	r2
+	PUSH	r3
+#elif ARC_FEATURE_RGF_BANKED_REGS == 8
+/* r4 - r9, r0, r11 gp, fp, r30, blink already saved */
+	PUSH	r0
+	PUSH	r1
+	PUSH	r2
+	PUSH	r3
+	PUSH	r12
+#elif ARC_FEATURE_RGF_BANKED_REGS >= 16
+/* nothing is saved, */
+	SAVE_R0_TO_R12
+
+	SAVE_R58_R59
+	PUSH	gp
+	PUSH	fp
+	PUSH	r30		/* general purpose */
+	PUSH	blink
+
+#if ARC_FEATURE_CODE_DENSITY
+	SAVE_CODE_DENSITY
+#endif
+	SAVE_LP_REGS
+#endif
+	PUSH	ilink
+	lr	r0, [AUX_STATUS32_P0]
+	PUSH	r0
+	lr	r0, [AUX_IRQ_ACT]
+	PUSH	r0
+	bclr	r0, r0, 0
+	sr	r0, [AUX_IRQ_ACT]
+
+	SAVE_CALLEE_REGS	/* save callee save registers */
+
+	mov	r1, ret_firq_r	/* save return address */
+	PUSH	r1
+	ld	r0, [pxCurrentTCB]
+	bl	dispatcher	/* r0->pxCurrentTCB */
+
+ret_firq_r:
+	RESTORE_CALLEE_REGS	/* recover registers */
+	POPAX	AUX_IRQ_ACT
+	POPAX	AUX_STATUS32_P0
+	POP	ilink
+
+#if ARC_FEATURE_RGF_NUM_BANKS > 1
+#if ARC_FEATURE_RGF_BANKED_REGS == 4
+/* r4 - r12, gp, fp, r30, blink already saved */
+	POP	r3
+	POP	r2
+	POP	r1
+	POP	r0
+	RESTORE_FIQ_EXC_REGS
+#elif ARC_FEATURE_RGF_BANKED_REGS == 8
+/* r4 - r9, gp, fp, r30, blink already saved */
+	POP	r12
+	POP	r3
+	POP	r2
+	POP	r1
+	POP	r0
+	RESTORE_FIQ_EXC_REGS
+#elif ARC_FEATURE_RGF_BANKED_REGS >= 16
+	RESTORE_LP_REGS
+#if ARC_FEATURE_CODE_DENSITY
+	RESTORE_CODE_DENSITY
+#endif
+	POP	blink
+	POP	r30
+	POP	fp
+	POP	gp
+
+	RESTORE_R58_R59
+	RESTORE_R0_TO_R12
+#endif /* ARC_FEATURE_RGF_BANKED_REGS  */
+#else
+	RESTORE_FIQ_EXC_REGS
+#endif /* ARC_FEATURE_RGF_NUM_BANKS */
+	rtie
+#endif
+/** @endcond */

kernel/FreeRTOS/Source/portable/ThirdParty/GCC/ARC_EM_HS/freertos_tls.c

@@ -0,0 +1,240 @@
+/*
+ * FreeRTOS Kernel V10.5.1
+ * Copyright (C) 2020 Synopsys, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#if defined( __MW__ )
+
+    #include <stdint.h>
+    #include <stdlib.h>
+    #include <string.h>
+
+    #include "FreeRTOS.h"
+
+    #include "queue.h"
+    #include "semphr.h"
+    #include "task.h"
+
+    #include "arc/arc_exception.h"
+    #include "embARC_toolchain.h"
+    #include "embARC_debug.h"
+
+    #ifdef ENABLE_FREERTOS_TLS_DEBUG
+        #define TLS_DEBUG( fmt, ... )    EMBARC_PRINTF( fmt, ## __VA_ARGS__ )
+    #else
+        #define TLS_DEBUG( fmt, ... )
+    #endif
+
+/*
+ * Runtime routines to execute constructors and
+ * destructors for task local storage.
+ */
+    extern void __mw_run_tls_dtor();
+    extern void __mw_run_tls_ctor();
+
+    extern uint32_t exc_nest_count;
+
+/*
+ * Linker generated symbols to mark .tls section addresses
+ * first byte .. last byte
+ */
+    extern char _ftls[], _etls[];
+    #pragma weak _ftls
+    #pragma weak _etls
+
+    void executable_requires_tls_section( void )
+    {
+        #if _ARC
+            for( ; ; )
+            {
+                _flag( 1 );
+                _nop();
+                _nop();
+                _nop();
+                _nop();
+                _nop();
+            }
+        #endif
+    }
+    #pragma off_inline(executable_requires_tls_section);
+    #pragma alias(executable_requires_tls_section, "executable_requires_.tls_section");
+
+    static void * init_task_tls( void )
+    {
+        uint32_t len = ( uint32_t ) ( _etls - _ftls );
+        void * tls = NULL;
+
+        #if FREERTOS_HEAP_SEL == 3
+        #warning "FreeRTOS TLS support is not compatible with heap 3 solution(FREERTOS_HEAP_SEL=3)!"
+        #warning "You can change FREERTOS_HEAP_SEL in freertos.mk to select other heap solution."
+        #else
+            tls = pvPortMalloc( len );
+        #endif
+
+        if( tls )
+        {
+            TLS_DEBUG( "Malloc task tls:%dbytes\r\n", len );
+            memcpy( tls, _ftls, len );
+            __mw_run_tls_ctor(); /* Run constructors */
+        }
+
+        return tls;
+    }
+
+    static void free_task_tls( void * pxTCB )
+    {
+        TaskHandle_t task2free = ( TaskHandle_t ) pxTCB;
+
+        if( task2free != NULL )
+        {
+            void * tls = pvTaskGetThreadLocalStoragePointer( task2free, 0 );
+
+            if( tls )
+            {
+                TLS_DEBUG( "Free task tls\r\n" );
+                __mw_run_tls_dtor();
+                vPortFree( tls );
+                vTaskSetThreadLocalStoragePointer( task2free, 0, NULL );
+            }
+        }
+    }
+
+    void task_end_hook( void * pxTCB )
+    {
+        free_task_tls( pxTCB );
+    }
+
+    static void * get_isr_tls( void )
+    {
+        /* In an ISR */
+        static int first = 1;
+
+        if( _Rarely( first ) )
+        {
+            first = 0;
+            __mw_run_tls_ctor(); /* Run constructors */
+        }
+
+        return ( void * ) _ftls;
+    }
+    #pragma off_inline(get_isr_tls)
+
+    static void * get_task_tls( void )
+    {
+        TaskHandle_t cur_task;
+
+        cur_task = xTaskGetCurrentTaskHandle();
+
+        if( cur_task == NULL )
+        {
+            return get_isr_tls();
+        }
+
+        void * tls = pvTaskGetThreadLocalStoragePointer( cur_task, 0 );
+
+        if( tls == NULL )
+        {
+            tls = init_task_tls();
+
+            if( tls )
+            {
+                vTaskSetThreadLocalStoragePointer( cur_task, 0, tls );
+            }
+            else
+            {
+                tls = get_isr_tls();
+            }
+        }
+
+        return tls;
+    }
+    #pragma off_inline(get_task_tls)
+
+    #if _ARC /* for ARC XCALLs need to preserve flags */
+        extern void * _Preserve_flags _mwget_tls( void );
+    #endif
+
+/*
+ * Back end gens calls to find local data for this task
+ */
+    void * _mwget_tls( void )
+    {
+        if( _ftls == ( char * ) 0 )
+        {
+            executable_requires_tls_section();
+        }
+
+        if( exc_nest_count > 0 ) /* In ISR */
+        {
+            return get_isr_tls();
+        }
+        else /* In Task */
+        {
+            return get_task_tls();
+        }
+    }
+
+
+/* simple interface of thread safe */
+    typedef xSemaphoreHandle _lock_t;
+    #if configUSE_RECURSIVE_MUTEXES != 1
+        #error "configUSE_RECURSIVE_MUTEXES in FreeRTOSConfig.h need to 1"
+    #endif
+
+    void _mwmutex_create( _lock_t * mutex_ptr )
+    {
+        *mutex_ptr = xSemaphoreCreateRecursiveMutex();
+    }
+
+    void _mwmutex_delete( _lock_t * mutex_ptr )
+    {
+        if( ( *mutex_ptr ) != NULL )
+        {
+            vSemaphoreDelete( *mutex_ptr );
+        }
+    }
+
+    void _mwmutex_lock( _lock_t mutex )
+    {
+        if( ( mutex ) != NULL )
+        {
+            while( xSemaphoreTakeRecursive( mutex, portMAX_DELAY ) != pdTRUE )
+            {
+            }
+        }
+    }
+
+    void _mwmutex_unlock( _lock_t mutex )
+    {
+        if( ( mutex ) != NULL )
+        {
+            xSemaphoreGiveRecursive( mutex );
+        }
+    }
+
+#else /* if defined( __MW__ ) */
+
+#endif /* __MW__ */

kernel/FreeRTOS/Source/portable/ThirdParty/GCC/ARC_EM_HS/port.c

@@ -0,0 +1,301 @@
+/*
+ * FreeRTOS Kernel V10.5.1
+ * Copyright (C) 2020 Synopsys, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/*
+ * Implementation of functions defined in portable.h
+ */
+
+#include "FreeRTOS.h"
+#include "task.h"
+#include "FreeRTOSConfig.h"
+
+#include "arc/arc_exception.h"
+#include "arc/arc_timer.h"
+#include "board.h"
+
+#include "arc_freertos_exceptions.h"
+
+volatile unsigned int ulCriticalNesting = 999UL;
+volatile unsigned int context_switch_reqflg; /* task context switch request flag in exceptions and interrupts handling */
+
+/**
+ * \var exc_nest_count
+ * \brief the counter for exc/int processing, =0 no int/exc
+ * >1 in int/exc processing
+ * @}
+ */
+uint32_t exc_nest_count;
+/* --------------------------------------------------------------------------*/
+
+/**
+ * @brief kernel tick interrupt handler of freertos
+ */
+/* ----------------------------------------------------------------------------*/
+static void vKernelTick( void * ptr )
+{
+    /* clear timer interrupt */
+    arc_timer_int_clear( BOARD_OS_TIMER_ID );
+    board_timer_update( configTICK_RATE_HZ );
+
+    if( xTaskIncrementTick() )
+    {
+        portYIELD_FROM_ISR(); /* need to make task switch */
+    }
+}
+
+/* --------------------------------------------------------------------------*/
+
+/**
+ * @brief  setup freertos kernel tick
+ */
+/* ----------------------------------------------------------------------------*/
+static void prvSetupTimerInterrupt( void )
+{
+    unsigned int cyc = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
+
+    int_disable( BOARD_OS_TIMER_INTNO ); /* disable os timer interrupt */
+    arc_timer_stop( BOARD_OS_TIMER_ID );
+    arc_timer_start( BOARD_OS_TIMER_ID, TIMER_CTRL_IE | TIMER_CTRL_NH, cyc );
+
+    int_handler_install( BOARD_OS_TIMER_INTNO, ( INT_HANDLER_T ) vKernelTick );
+    int_pri_set( BOARD_OS_TIMER_INTNO, INT_PRI_MIN );
+    int_enable( BOARD_OS_TIMER_INTNO );
+}
+
+/*
+ * Setup the stack of a new task so it is ready to be placed under the
+ * scheduler control.  The registers have to be placed on the stack in
+ * the order that the port expects to find them.
+ *
+ * For ARC, task context switch is implemented with the help of SWI exception
+ * It's not efficient but simple.
+ *
+ */
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
+{
+    /* To ensure asserts in tasks.c don't fail, although in this case the assert
+     * is not really required. */
+    pxTopOfStack--;
+
+    /* Setup the initial stack of the task.  The stack is set exactly as
+     * expected by the portRESTORE_CONTEXT() macro. */
+
+    /* When the task starts is will expect to find the function parameter in
+     * R0. */
+    *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) pxCode; /* function body */
+
+    /* PC */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) start_r; /* dispatch return address */
+
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_NESTING;
+    return pxTopOfStack;
+}
+
+/* --------------------------------------------------------------------------*/
+
+/**
+ * @brief  start the freertos scheduler, go to the first task
+ *
+ * @returns
+ */
+/* ----------------------------------------------------------------------------*/
+BaseType_t xPortStartScheduler( void )
+{
+    /* Start the timer that generates the tick ISR. */
+    prvSetupTimerInterrupt();
+    start_dispatch();
+
+    /* Should not get here! */
+    return 0;
+}
+
+/* --------------------------------------------------------------------------*/
+
+/**
+ * @brief
+ */
+/* ----------------------------------------------------------------------------*/
+void vPortEndScheduler( void )
+{
+}
+
+/* --------------------------------------------------------------------------*/
+
+/**
+ * @brief  generate a task switch request in ISR
+ */
+/* ----------------------------------------------------------------------------*/
+void vPortYieldFromIsr( void )
+{
+    unsigned int status32;
+
+    status32 = cpu_lock_save();
+    context_switch_reqflg = true;
+    cpu_unlock_restore( status32 );
+}
+
+/* --------------------------------------------------------------------------*/
+
+/**
+ * @brief
+ */
+/* ----------------------------------------------------------------------------*/
+void vPortYield( void )
+{
+    unsigned int status32;
+
+    status32 = cpu_lock_save();
+    dispatch();
+    cpu_unlock_restore( status32 );
+}
+
+/* --------------------------------------------------------------------------*/
+
+/**
+ * @brief
+ */
+/* ----------------------------------------------------------------------------*/
+void vPortEndTask( void )
+{
+    #if ( INCLUDE_vTaskDelete == 1 )
+        vTaskDelete( NULL ); /* Delete task itself */
+    #endif
+
+    while( 1 ) /* Yield to other task */
+    {
+        vPortYield();
+    }
+}
+
+#if ARC_FEATURE_STACK_CHECK
+
+/*
+ * !!! Note !!!
+ * This a trick!!!
+ * It's a copy from task.c. We need to konw the definition of TCB for the purpose of hardware
+ * stack check. Pls don't forget to update it when FreeRTOS is updated.
+ */
+    typedef struct tskTaskControlBlock       /* The old naming convention is used to prevent breaking kernel aware debuggers. */
+    {
+        volatile StackType_t * pxTopOfStack; /*< Points to the location of the last item placed on the tasks stack.  THIS MUST BE THE FIRST MEMBER OF THE TCB STRUCT. */
+
+        #if ( portUSING_MPU_WRAPPERS == 1 )
+            xMPU_SETTINGS xMPUSettings; /*< The MPU settings are defined as part of the port layer.  THIS MUST BE THE SECOND MEMBER OF THE TCB STRUCT. */
+        #endif
+
+        ListItem_t xStateListItem;                  /*< The list that the state list item of a task is reference from denotes the state of that task (Ready, Blocked, Suspended ). */
+        ListItem_t xEventListItem;                  /*< Used to reference a task from an event list. */
+        UBaseType_t uxPriority;                     /*< The priority of the task.  0 is the lowest priority. */
+        StackType_t * pxStack;                      /*< Points to the start of the stack. */
+        char pcTaskName[ configMAX_TASK_NAME_LEN ]; /*< Descriptive name given to the task when created.  Facilitates debugging only. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+        #if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) )
+            StackType_t * pxEndOfStack; /*< Points to the highest valid address for the stack. */
+        #endif
+
+        #if ( portCRITICAL_NESTING_IN_TCB == 1 )
+            UBaseType_t uxCriticalNesting; /*< Holds the critical section nesting depth for ports that do not maintain their own count in the port layer. */
+        #endif
+
+        #if ( configUSE_TRACE_FACILITY == 1 )
+            UBaseType_t uxTCBNumber;  /*< Stores a number that increments each time a TCB is created.  It allows debuggers to determine when a task has been deleted and then recreated. */
+            UBaseType_t uxTaskNumber; /*< Stores a number specifically for use by third party trace code. */
+        #endif
+
+        #if ( configUSE_MUTEXES == 1 )
+            UBaseType_t uxBasePriority; /*< The priority last assigned to the task - used by the priority inheritance mechanism. */
+            UBaseType_t uxMutexesHeld;
+        #endif
+
+        #if ( configUSE_APPLICATION_TASK_TAG == 1 )
+            TaskHookFunction_t pxTaskTag;
+        #endif
+
+        #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 )
+            void * pvThreadLocalStoragePointers[ configNUM_THREAD_LOCAL_STORAGE_POINTERS ];
+        #endif
+
+        #if ( configGENERATE_RUN_TIME_STATS == 1 )
+            uint32_t ulRunTimeCounter; /*< Stores the amount of time the task has spent in the Running state. */
+        #endif
+
+        #if ( configUSE_NEWLIB_REENTRANT == 1 )
+
+            /* Allocate a Newlib reent structure that is specific to this task.
+             * Note Newlib support has been included by popular demand, but is not
+             * used by the FreeRTOS maintainers themselves.  FreeRTOS is not
+             * responsible for resulting newlib operation.  User must be familiar with
+             * newlib and must provide system-wide implementations of the necessary
+             * stubs. Be warned that (at the time of writing) the current newlib design
+             * implements a system-wide malloc() that must be provided with locks. */
+            struct  _reent xNewLib_reent;
+        #endif
+
+        #if ( configUSE_TASK_NOTIFICATIONS == 1 )
+            volatile uint32_t ulNotifiedValue;
+            volatile uint8_t ucNotifyState;
+        #endif
+
+        /* See the comments above the definition of
+         * tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE. */
+        #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
+            uint8_t ucStaticallyAllocated;                     /*< Set to pdTRUE if the task is a statically allocated to ensure no attempt is made to free the memory. */
+        #endif
+
+        #if ( INCLUDE_xTaskAbortDelay == 1 )
+            uint8_t ucDelayAborted;
+        #endif
+
+        #if ( configUSE_POSIX_ERRNO == 1 )
+            int iTaskErrno;
+        #endif
+    } tskTCB;
+
+
+    void vPortSetStackCheck( TaskHandle_t old,
+                             TaskHandle_t new )
+    {
+        if( new != NULL )
+        {
+            #if ARC_FEATURE_SEC_PRESENT
+                arc_aux_write( AUX_S_KSTACK_BASE, ( uint32_t ) ( new->pxEndOfStack ) );
+                arc_aux_write( AUX_S_KSTACK_TOP, ( uint32_t ) ( new->pxStack ) );
+            #else
+                arc_aux_write( AUX_KSTACK_BASE, ( uint32_t ) ( new->pxEndOfStack ) );
+                arc_aux_write( AUX_KSTACK_TOP, ( uint32_t ) ( new->pxStack ) );
+            #endif
+        }
+    }
+#endif /* if ARC_FEATURE_STACK_CHECK */

kernel/FreeRTOS/Source/portable/ThirdParty/GCC/ARC_EM_HS/portmacro.h

@@ -0,0 +1,158 @@
+/*
+ * FreeRTOS Kernel V10.5.1
+ * Copyright (C) 2020 Synopsys, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+    extern "C" {
+#endif
+/* *INDENT-ON* */
+
+/* record stack high address for stack check */
+#ifndef configRECORD_STACK_HIGH_ADDRESS
+    #define configRECORD_STACK_HIGH_ADDRESS    1
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    unsigned int
+#define portBASE_TYPE     portLONG
+
+#ifndef Asm
+    #define Asm           __asm__ volatile
+#endif
+
+/*
+ *  normal constants
+ */
+#ifndef NULL
+    #define NULL    0           /* invalid pointer */
+#endif /* NULL */
+
+#ifndef true
+    #define true    1           /* true */
+#endif /* true */
+
+#ifndef false
+    #define false    0          /* false */
+#endif /* false */
+
+typedef portSTACK_TYPE     StackType_t;
+typedef long               BaseType_t;
+typedef unsigned long      UBaseType_t;
+
+#if ( configUSE_16_BIT_TICKS == 1 )
+    typedef uint16_t       TickType_t;
+    #define portMAX_DELAY          ( TickType_t ) 0xffff
+#else
+    typedef unsigned int   TickType_t;
+    #define portMAX_DELAY          ( TickType_t ) 0xffffffffUL
+#endif
+
+#define portNO_CRITICAL_NESTING    ( ( uint32_t ) 0 )
+#define portSTACK_GROWTH           ( -1 )
+#define portTICK_PERIOD_MS         ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT         8
+#define portNOP()               Asm( "nop_s" );
+#define IPM_ENABLE_ALL             1
+
+#define portYIELD_FROM_ISR()    vPortYieldFromIsr()
+#define portYIELD()             vPortYield()
+
+/* Critical section management. */
+#define portDISABLE_INTERRUPTS() \
+    {                            \
+        Asm( "clri" );           \
+        Asm( "" ::: "memory" );  \
+    }                            \
+
+#define portENABLE_INTERRUPTS() \
+    {                           \
+        Asm( "" ::: "memory" ); \
+        Asm( "seti" );          \
+    }                           \
+
+extern volatile unsigned int ulCriticalNesting;
+
+#define portENTER_CRITICAL()     \
+    {                            \
+        portDISABLE_INTERRUPTS() \
+        ulCriticalNesting++;     \
+    }
+
+
+#define portEXIT_CRITICAL()                                    \
+    {                                                          \
+        if( ulCriticalNesting > portNO_CRITICAL_NESTING )      \
+        {                                                      \
+            ulCriticalNesting--;                               \
+            if( ulCriticalNesting == portNO_CRITICAL_NESTING ) \
+            {                                                  \
+                portENABLE_INTERRUPTS()                        \
+            }                                                  \
+        }                                                      \
+    }
+
+
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+
+#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS()              do {} while( 0 )     /* we use the timer */
+#define portALT_GET_RUN_TIME_COUNTER_VALUE( dest )            ( dest = xTickCount )
+
+#if defined( __MW__ )
+    extern void task_end_hook( void * pxTCB );
+    #define portCLEAN_UP_TCB( pxTCB )    task_end_hook( ( void * ) pxTCB )
+#endif
+
+void vPortYield( void );
+void vPortYieldFromIsr( void );
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+    }
+#endif
+/* *INDENT-ON* */
+
+#endif /* PORTMACRO_H */

kernel/FreeRTOS/Source/portable/ThirdParty/GCC/ARC_v1/arc_freertos_exceptions.c

@@ -0,0 +1,52 @@
+/*
+ * FreeRTOS Kernel V10.5.1
+ * Copyright (C) 2020 Synopsys, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/**
+ * \file
+ * \brief   exception processing for freertos
+ */
+
+/* #include "embARC.h" */
+
+#include "arc_freertos_exceptions.h"
+
+#ifdef __GNU__
+    extern void gnu_printf_setup( void );
+#endif
+
+/**
+ * \brief  freertos related cpu exception initialization, all the interrupts handled by freertos must be not
+ * fast irqs. If fiq is needed, please install the default firq_exc_entry or your own fast irq entry into
+ * the specific interrupt exception.
+ */
+void freertos_exc_init( void )
+{
+    #ifdef __GNU__
+        gnu_printf_setup();
+    #endif
+}

kernel/FreeRTOS/Source/portable/ThirdParty/GCC/ARC_v1/arc_freertos_exceptions.h

@@ -0,0 +1,46 @@
+/*
+ * FreeRTOS Kernel V10.5.1
+ * Copyright (C) 2020 Synopsys, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef ARC_FREERTOS_EXCEPTIONS_H
+#define ARC_FREERTOS_EXCEPTIONS_H
+
+/*
+ * here, all arc cpu exceptions share the same entry, also for all interrupt
+ * exceptions
+ */
+extern void exc_entry_cpu( void ); /* cpu exception entry for freertos */
+extern void exc_entry_int( void ); /* int exception entry for freertos */
+
+/* task dispatch functions in .s */
+extern void start_r( void );
+extern void start_dispatch();
+extern void dispatch();
+
+extern void freertos_exc_init( void );
+
+#endif /* ARC_FREERTOS_EXCEPTIONS_H */

kernel/FreeRTOS/Source/portable/ThirdParty/GCC/ARC_v1/arc_support.s

@@ -0,0 +1,322 @@
+/*
+ * FreeRTOS Kernel V10.5.1
+ * Copyright (C) 2020 Synopsys, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/**
+ * \file
+ * \ingroup OS_FREERTOS
+ * \brief  freertos support for arc processor
+ *	like task dispatcher, interrupt handler
+ */
+/** @cond OS_FREERTOS_ASM_ARC_SUPPORT */
+
+/*
+ * core-dependent part in assemble language (for arc)
+ */
+#define __ASSEMBLY__
+#include "arc/arc.h"
+#include "arc/arc_asm_common.h"
+
+/*
+ *  task dispatcher
+ *
+ */
+	.text
+	.align 4
+	.global dispatch
+dispatch:
+/*
+ *  the pre-conditions of this routine are task context, CPU is
+ *  locked, dispatch is enabled.
+ */
+	SAVE_NONSCRATCH_REGS		/* save callee save registers */
+	mov	r1, dispatch_r
+	PUSH	r1			/* save return address */
+	ld	r0, [pxCurrentTCB]
+	bl	dispatcher
+
+/* return routine when task dispatch happened in task context */
+dispatch_r:
+	RESTORE_NONSCRATCH_REGS		/* recover registers */
+	j	[blink]
+
+/*
+ *  start dispatch
+ */
+	.global start_dispatch
+	.align 4
+start_dispatch:
+/*
+ *  this routine is called in the non-task context during the startup of the kernel
+ *  , and all the interrupts are locked.
+ *
+ *  when the dispatcher is called, the cpu is locked, no nest exception (CPU exception/interrupt).
+ *  In target_initialize, all interrupt priority mask should be cleared, cpu should be
+ *  locked, the interrupts outside the kernel such as fiq can be
+ *  enabled.
+ */
+	clri
+	mov	r0, 0
+	st	r0, [exc_nest_count]
+	b	dispatcher_0
+/*
+ *  dispatcher
+ */
+dispatcher:
+	ld	r1, [ulCriticalNesting]
+	PUSH	r1			/* save critical nesting */
+	st	sp, [r0]		/* save stack pointer of current task, r0->pxCurrentTCB */
+	jl	vTaskSwitchContext	/* change the value of pxCurrentTCB */
+/*
+ *  before dispatcher is called, task context | cpu locked | dispatch enabled
+ *  should be satisfied. In this routine, the processor will jump
+ *  into the entry of next to run task
+ *
+ *  i.e. kernel mode, IRQ disabled, dispatch enabled
+ */
+dispatcher_0:
+	ld	r1, [pxCurrentTCB]
+	ld	sp, [r1]	/* recover task stack */
+#if ARC_FEATURE_STACK_CHECK
+	lr r0, [AUX_STATUS32]
+	bclr r0, r0, AUX_STATUS_BIT_SC
+	flag r0
+	jl	vPortSetStackCheck
+	lr r0, [AUX_STATUS32]
+	bset r0, r0, AUX_STATUS_BIT_SC
+	flag r0
+#endif
+	POP	r0		/* get critical nesting */
+	st	r0, [ulCriticalNesting]
+	POP	r0		/* get return address  */
+	j	[r0]
+
+/*
+ *  task startup routine
+ *
+ */
+	.text
+	.global start_r
+	.align 4
+start_r:
+	seti	/* unlock cpu */
+	mov	blink, vPortEndTask	/* set return address */
+	POP	r1			/* get task function body */
+	POP	r0			/* get task parameters */
+	j	[r1]
+
+/****** exceptions and interrupts handing ******/
+/****** entry for exception handling ******/
+	.global exc_entry_cpu
+	.align 4
+exc_entry_cpu:
+
+	EXCEPTION_PROLOGUE
+
+
+	mov	blink,	sp
+	mov	r3, sp		/* as exception handler's para(p_excinfo) */
+
+	ld	r1, [exc_nest_count]
+	add	r1, r1, 1
+	st	r1, [exc_nest_count]
+	brne	r1, 0, exc_handler_1
+/* change to exception stack if interrupt happened in task context */
+	mov	sp, _e_stack
+exc_handler_1:
+	PUSH	blink
+
+/* find the exception cause */
+#if ARC_FEATURE_CORE_700
+	lr	r0, [AUX_ECR]
+	lsr	r0, r0, 16
+	bmsk	r0, r0, 7
+#endif
+	mov	r1, exc_int_handler_table
+	ld.as	r2, [r1, r0]
+
+	mov	r0, r3
+	jl	[r2]		/* !!!!jump to exception handler where interrupts are not allowed! */
+
+/* interrupts are not allowed */
+ret_exc:
+	POP	sp
+	mov	r1, exc_nest_count
+	ld	r0, [r1]
+	sub	r0, r0, 1
+	st 	r0, [r1]
+	brne	r0, 0, ret_exc_1  /* nested exception case */
+	lr	r1, [AUX_IRQ_LV12]
+	brne	r1, 0, ret_exc_1  /* nested or pending interrupt case */
+
+	ld	r0, [context_switch_reqflg]
+	brne	r0, 0, ret_exc_2
+ret_exc_1:	/* return from non-task context, interrupts or exceptions are nested */
+
+	EXCEPTION_EPILOGUE
+#if ARC_FEATURE_CORE_600
+	rtie ilink2
+#else
+	rtie
+#endif
+
+/* there is a dispatch request */
+ret_exc_2:
+	/* clear dispatch request */
+	mov	r0, 0
+	st	r0, [context_switch_reqflg]
+
+	ld	r0, [pxCurrentTCB]
+	breq	r0, 0, ret_exc_1
+
+	SAVE_CALLEE_REGS	/* save callee save registers */
+
+	lr	r0, [AUX_STATUS32]
+	bclr	r0, r0, AUX_STATUS_BIT_AE	/* clear exception bit */
+	flag	r0
+
+	mov	r1, ret_exc_r	/* save return address */
+	PUSH	r1
+
+	bl	dispatcher	/* r0->pxCurrentTCB */
+
+ret_exc_r:
+	/* recover exception status */
+	lr	r0, [AUX_STATUS32]
+	bset	r0, r0, AUX_STATUS_BIT_AE
+	flag	r0
+
+	RESTORE_CALLEE_REGS	/* recover registers */
+	EXCEPTION_EPILOGUE
+#if ARC_FEATURE_CORE_600
+	rtie ilink2
+#else
+	rtie
+#endif
+
+/****** entry for normal interrupt exception handling ******/
+	.global exc_entry_int	/* entry for interrupt handling */
+	.align 4
+exc_entry_int:
+
+	INTERRUPT_PROLOGUE
+
+	mov	blink, sp
+
+	/* disable interrupt */
+	push r0
+	lr  r0, [AUX_STATUS32]
+	push r0
+    bclr r0, r0, AUX_STATUS_BIT_E1
+    bclr r0, r0, AUX_STATUS_BIT_E2
+    flag r0
+	ld	r3, [exc_nest_count]
+	add	r2, r3, 1
+	st	r2, [exc_nest_count]
+	/* enable interrupt */
+	pop r0
+	flag r0
+	pop r0
+
+	brne	r3, 0, irq_handler_1
+/* change to exception stack if interrupt happened in task context */
+	mov	sp, _e_stack
+#if ARC_FEATURE_STACK_CHECK
+	lr r0, [AUX_STATUS32]
+	bclr r0, r0, AUX_STATUS_BIT_SC
+	flag r0
+#endif
+irq_handler_1:
+	PUSH	blink
+
+/* critical area */
+#if ARC_FEATURE_CORE_700
+	lr	r0, [AUX_IRQ_CAUSE1]
+#endif
+	mov	r1, exc_int_handler_table
+	ld.as	r2, [r1, r0]	/* r2 = exc_int_handler_table + irqno *4 */
+/* handle software triggered interrupt */
+	lr	r3, [AUX_IRQ_HINT]
+	cmp	r3, r0
+	bne.d irq_hint_handled
+	xor	r3, r3, r3
+	sr	r3, [AUX_IRQ_HINT]
+irq_hint_handled:
+
+	jl	[r2]		/* jump to interrupt handler */
+/* no interrupts are allowed from here */
+ret_int:
+	clri	/* disable interrupt */
+
+	POP	sp
+	mov	r1, exc_nest_count
+	ld	r0, [r1]
+	sub	r0, r0, 1
+	st	r0, [r1]
+/* if there are multi-bits set in IRQ_LV12, it's still in nest interrupt */
+	lr	r1, [AUX_IRQ_LV12]
+
+	ld	r0, [context_switch_reqflg]
+	brne	r0, 0, ret_int_2
+ret_int_1:	/* return from non-task context */
+	INTERRUPT_EPILOGUE
+#if ARC_FEATURE_CORE_600
+/* TODO: series 600 IRQ6 and IRQ7 uses ilink2 */
+	rtie ilink1
+#else
+	rtie
+#endif
+/* there is a dispatch request */
+ret_int_2:
+	/* clear dispatch request */
+	mov	r0, 0
+	st	r0, [context_switch_reqflg]
+
+	ld	r0, [pxCurrentTCB]
+	breq 	r0, 0, ret_int_1
+
+/* r1 has old AUX_IRQ_LV12 */
+	PUSH	r1
+/* clear related bits in IRQ_ACT manually to simulate a irq return  */
+
+	SAVE_CALLEE_REGS	/* save callee save registers */
+	mov	r1, ret_int_r	/* save return address */
+	PUSH	r1
+
+	bl	dispatcher	/* r0->pxCurrentTCB */
+
+ret_int_r:
+	RESTORE_CALLEE_REGS	/* recover registers */
+	POPAX	AUX_IRQ_LV12
+	INTERRUPT_EPILOGUE
+#if ARC_FEATURE_CORE_600
+	rtie ilink1
+#else
+	rtie
+#endif
+
+/** @endcond */

kernel/FreeRTOS/Source/portable/ThirdParty/GCC/ARC_v1/port.c

@@ -0,0 +1,296 @@
+/*
+ * FreeRTOS Kernel V10.5.1
+ * Copyright (C) 2020 Synopsys, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/*
+ * Implementation of functions defined in portable.h
+ */
+
+#include "FreeRTOS.h"
+#include "task.h"
+#include "FreeRTOSConfig.h"
+
+#include "arc/arc_exception.h"
+#include "arc/arc_timer.h"
+#include "board.h"
+
+#include "arc_freertos_exceptions.h"
+
+volatile unsigned int ulCriticalNesting = 999UL;
+volatile unsigned int context_switch_reqflg; /* task context switch request flag in exceptions and interrupts handling */
+
+/**
+ * \var exc_nest_count
+ * \brief the counter for exc/int processing, =0 no int/exc
+ * >1 in int/exc processing
+ * @}
+ */
+uint32_t exc_nest_count;
+/* --------------------------------------------------------------------------*/
+
+/**
+ * @brief kernel tick interrupt handler of freertos
+ */
+/* ----------------------------------------------------------------------------*/
+static void vKernelTick( void * ptr )
+{
+    /* clear timer interrupt */
+    arc_timer_int_clear( BOARD_OS_TIMER_ID );
+    board_timer_update( configTICK_RATE_HZ );
+
+    if( xTaskIncrementTick() )
+    {
+        portYIELD_FROM_ISR(); /* need to make task switch */
+    }
+}
+
+/* --------------------------------------------------------------------------*/
+
+/**
+ * @brief  setup freertos kernel tick
+ */
+/* ----------------------------------------------------------------------------*/
+static void prvSetupTimerInterrupt( void )
+{
+    unsigned int cyc = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
+
+    int_disable( BOARD_OS_TIMER_INTNO ); /* disable os timer interrupt */
+    arc_timer_stop( BOARD_OS_TIMER_ID );
+    arc_timer_start( BOARD_OS_TIMER_ID, TIMER_CTRL_IE | TIMER_CTRL_NH, cyc );
+
+    int_handler_install( BOARD_OS_TIMER_INTNO, ( INT_HANDLER_T ) vKernelTick );
+    int_pri_set( BOARD_OS_TIMER_INTNO, INT_PRI_MIN );
+    int_enable( BOARD_OS_TIMER_INTNO );
+}
+
+/*
+ * Setup the stack of a new task so it is ready to be placed under the
+ * scheduler control.  The registers have to be placed on the stack in
+ * the order that the port expects to find them.
+ *
+ * For ARC, task context switch is implemented with the help of SWI exception
+ * It's not efficient but simple.
+ *
+ */
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
+{
+    /* To ensure asserts in tasks.c don't fail, although in this case the assert
+     * is not really required. */
+    pxTopOfStack--;
+
+    /* Setup the initial stack of the task.  The stack is set exactly as
+     * expected by the portRESTORE_CONTEXT() macro. */
+
+    /* When the task starts is will expect to find the function parameter in
+     * R0. */
+    *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) pxCode; /* function body */
+
+    /* PC */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) start_r; /* dispatch return address */
+
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_NESTING;
+    return pxTopOfStack;
+}
+
+/* --------------------------------------------------------------------------*/
+
+/**
+ * @brief  start the freertos scheduler, go to the first task
+ *
+ * @returns
+ */
+/* ----------------------------------------------------------------------------*/
+BaseType_t xPortStartScheduler( void )
+{
+    /* Start the timer that generates the tick ISR. */
+    prvSetupTimerInterrupt();
+    start_dispatch();
+
+    /* Should not get here! */
+    return 0;
+}
+
+/* --------------------------------------------------------------------------*/
+
+/**
+ * @brief
+ */
+/* ----------------------------------------------------------------------------*/
+void vPortEndScheduler( void )
+{
+}
+
+/* --------------------------------------------------------------------------*/
+
+/**
+ * @brief  generate a task switch request in ISR
+ */
+/* ----------------------------------------------------------------------------*/
+void vPortYieldFromIsr( void )
+{
+    unsigned int status32;
+
+    status32 = cpu_lock_save();
+    context_switch_reqflg = true;
+    cpu_unlock_restore( status32 );
+}
+
+/* --------------------------------------------------------------------------*/
+
+/**
+ * @brief
+ */
+/* ----------------------------------------------------------------------------*/
+void vPortYield( void )
+{
+    unsigned int status32;
+
+    status32 = cpu_lock_save();
+    dispatch();
+    cpu_unlock_restore( status32 );
+}
+
+/* --------------------------------------------------------------------------*/
+
+/**
+ * @brief
+ */
+/* ----------------------------------------------------------------------------*/
+void vPortEndTask( void )
+{
+    #if ( INCLUDE_vTaskDelete == 1 )
+        vTaskDelete( NULL ); /* Delete task itself */
+    #endif
+
+    while( 1 ) /* Yield to other task */
+    {
+        vPortYield();
+    }
+}
+
+#if ARC_FEATURE_STACK_CHECK
+
+/*
+ * !!! Note !!!
+ * This a trick!!!
+ * It's a copy from task.c. We need to konw the definition of TCB for the purpose of hardware
+ * stack check. Pls don't forget to update it when FreeRTOS is updated.
+ */
+    typedef struct tskTaskControlBlock       /* The old naming convention is used to prevent breaking kernel aware debuggers. */
+    {
+        volatile StackType_t * pxTopOfStack; /*< Points to the location of the last item placed on the tasks stack.  THIS MUST BE THE FIRST MEMBER OF THE TCB STRUCT. */
+
+        #if ( portUSING_MPU_WRAPPERS == 1 )
+            xMPU_SETTINGS xMPUSettings;     /*< The MPU settings are defined as part of the port layer.  THIS MUST BE THE SECOND MEMBER OF THE TCB STRUCT. */
+        #endif
+
+        ListItem_t xStateListItem;                  /*< The list that the state list item of a task is reference from denotes the state of that task (Ready, Blocked, Suspended ). */
+        ListItem_t xEventListItem;                  /*< Used to reference a task from an event list. */
+        UBaseType_t uxPriority;                     /*< The priority of the task.  0 is the lowest priority. */
+        StackType_t * pxStack;                      /*< Points to the start of the stack. */
+        char pcTaskName[ configMAX_TASK_NAME_LEN ]; /*< Descriptive name given to the task when created.  Facilitates debugging only. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+        #if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) )
+            StackType_t * pxEndOfStack;     /*< Points to the highest valid address for the stack. */
+        #endif
+
+        #if ( portCRITICAL_NESTING_IN_TCB == 1 )
+            UBaseType_t uxCriticalNesting;  /*< Holds the critical section nesting depth for ports that do not maintain their own count in the port layer. */
+        #endif
+
+        #if ( configUSE_TRACE_FACILITY == 1 )
+            UBaseType_t uxTCBNumber;        /*< Stores a number that increments each time a TCB is created.  It allows debuggers to determine when a task has been deleted and then recreated. */
+            UBaseType_t uxTaskNumber;       /*< Stores a number specifically for use by third party trace code. */
+        #endif
+
+        #if ( configUSE_MUTEXES == 1 )
+            UBaseType_t uxBasePriority;     /*< The priority last assigned to the task - used by the priority inheritance mechanism. */
+            UBaseType_t uxMutexesHeld;
+        #endif
+
+        #if ( configUSE_APPLICATION_TASK_TAG == 1 )
+            TaskHookFunction_t pxTaskTag;
+        #endif
+
+        #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 )
+            void * pvThreadLocalStoragePointers[ configNUM_THREAD_LOCAL_STORAGE_POINTERS ];
+        #endif
+
+        #if ( configGENERATE_RUN_TIME_STATS == 1 )
+            uint32_t ulRunTimeCounter;      /*< Stores the amount of time the task has spent in the Running state. */
+        #endif
+
+        #if ( configUSE_NEWLIB_REENTRANT == 1 )
+
+            /* Allocate a Newlib reent structure that is specific to this task.
+             * Note Newlib support has been included by popular demand, but is not
+             * used by the FreeRTOS maintainers themselves.  FreeRTOS is not
+             * responsible for resulting newlib operation.  User must be familiar with
+             * newlib and must provide system-wide implementations of the necessary
+             * stubs. Be warned that (at the time of writing) the current newlib design
+             * implements a system-wide malloc() that must be provided with locks. */
+            struct  _reent xNewLib_reent;
+        #endif
+
+        #if ( configUSE_TASK_NOTIFICATIONS == 1 )
+            volatile uint32_t ulNotifiedValue;
+            volatile uint8_t ucNotifyState;
+        #endif
+
+        /* See the comments above the definition of
+         * tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE. */
+        #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
+            uint8_t ucStaticallyAllocated;                     /*< Set to pdTRUE if the task is a statically allocated to ensure no attempt is made to free the memory. */
+        #endif
+
+        #if ( INCLUDE_xTaskAbortDelay == 1 )
+            uint8_t ucDelayAborted;
+        #endif
+
+        #if ( configUSE_POSIX_ERRNO == 1 )
+            int iTaskErrno;
+        #endif
+    } tskTCB;
+
+
+    void vPortSetStackCheck( TaskHandle_t old,
+                             TaskHandle_t new )
+    {
+        if( new != NULL )
+        {
+            arc_aux_write( AUX_USTACK_BASE, ( uint32_t ) ( new->pxEndOfStack ) );
+            arc_aux_write( AUX_USTACK_TOP, ( uint32_t ) ( new->pxStack ) );
+        }
+    }
+#endif /* if ARC_FEATURE_STACK_CHECK */

kernel/FreeRTOS/Source/portable/ThirdParty/GCC/ARC_v1/portmacro.h

@@ -0,0 +1,148 @@
+/*
+ * FreeRTOS Kernel V10.5.1
+ * Copyright (C) 2020 Synopsys, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef PORTMACRO_H
+    #define PORTMACRO_H
+    #include "embARC.h"
+
+    #ifdef __cplusplus
+        extern "C" {
+    #endif
+
+/* record stack high address for stack check */
+    #ifndef configRECORD_STACK_HIGH_ADDRESS
+        #define configRECORD_STACK_HIGH_ADDRESS    1
+    #endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+    #define portCHAR          char
+    #define portFLOAT         float
+    #define portDOUBLE        double
+    #define portLONG          long
+    #define portSHORT         short
+    #define portSTACK_TYPE    unsigned int
+    #define portBASE_TYPE     portLONG
+
+    #ifndef Asm
+        #define Asm           __asm__ volatile
+    #endif
+
+/*
+ *  normal constants
+ */
+    #ifndef NULL
+        #define NULL    0       /* invalid pointer */
+    #endif /* NULL */
+
+    #ifndef true
+        #define true    1       /* true */
+    #endif /* true */
+
+    #ifndef false
+        #define false    0      /* false */
+    #endif /* false */
+
+    typedef portSTACK_TYPE     StackType_t;
+    typedef long               BaseType_t;
+    typedef unsigned long      UBaseType_t;
+
+    #if ( configUSE_16_BIT_TICKS == 1 )
+        typedef uint16_t       TickType_t;
+        #define portMAX_DELAY          ( TickType_t ) 0xffff
+    #else
+        typedef unsigned int   TickType_t;
+        #define portMAX_DELAY          ( TickType_t ) 0xffffffffUL
+    #endif
+
+    #define portNO_CRITICAL_NESTING    ( ( uint32_t ) 0 )
+    #define portSTACK_GROWTH           ( -1 )
+    #define portTICK_PERIOD_MS         ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+    #define portBYTE_ALIGNMENT         8
+    #define portNOP()               Asm( "nop_s" );
+    #define IPM_ENABLE_ALL             1
+
+    #define portYIELD_FROM_ISR()    vPortYieldFromIsr()
+    #define portYIELD()             vPortYield()
+
+/* Critical section management. */
+    #define portDISABLE_INTERRUPTS() \
+    {                                \
+        arc_lock();                  \
+    }                                \
+
+    #define portENABLE_INTERRUPTS() \
+    {                               \
+        arc_unlock();               \
+    }                               \
+
+    extern volatile unsigned int ulCriticalNesting;
+
+    #define portENTER_CRITICAL() \
+    {                            \
+        portDISABLE_INTERRUPTS() \
+        ulCriticalNesting++;     \
+    }
+
+
+    #define portEXIT_CRITICAL()                                \
+    {                                                          \
+        if( ulCriticalNesting > portNO_CRITICAL_NESTING )      \
+        {                                                      \
+            ulCriticalNesting--;                               \
+            if( ulCriticalNesting == portNO_CRITICAL_NESTING ) \
+            {                                                  \
+                portENABLE_INTERRUPTS()                        \
+            }                                                  \
+        }                                                      \
+    }
+
+
+    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+
+    #define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS()              do {} while( 0 ) /* we use the timer */
+    #define portALT_GET_RUN_TIME_COUNTER_VALUE( dest )            ( dest = xTickCount )
+
+    void vPortYield( void );
+    void vPortYieldFromIsr( void );
+
+    #ifdef __cplusplus
+}
+    #endif
+
+#endif /* PORTMACRO_H */

kernel/FreeRTOS/Source/portable/ThirdParty/GCC/ARM_TFM/README.md

@@ -0,0 +1,80 @@
+# Target of this port
+
+This port adds the support that FreeRTOS applications can call the secure
+services in Trusted Firmware M(TF-M) through Platform Security Architecture
+(PSA) API based on the ARM Cortex-M23, Cortex-M33, Cortex-M55 and Cortex-M85
+platform.
+
+The Platform Security Architecture (PSA) makes it quicker, easier and cheaper
+to design security into a device from the ground up. PSA is made up of four key
+stages: analyze, architect, implement, and certify. See [PSA Resource Page](https://developer.arm.com/architectures/security-architectures/platform-security-architecture).
+
+TF-M is an open source project. It provides a reference implementation of PSA
+for Arm M-profile architecture. Please get the details from this [link](https://git.trustedfirmware.org/TF-M/trusted-firmware-m.git/about/).
+
+# Derivation of the source code
+
+* ```os_wrapper_freertos.c```
+  The implementation of APIs which are defined in ```\ns_interface\os_wrapper\mutex.h``` by tf-m-tests
+  (tag: TF-Mv1.5.0 & TF-Mv1.6.0). The implementation is based on FreeRTOS mutex type semaphore.
+
+# Usage notes
+
+To build a project based on this port:
+* Step 1: build the secure image. Please follow the **Build the Secure Side** section for details.
+* Step 2: build the nonsecure image. Please follow the **Build the Non-Secure Side** for details.
+
+## Build the Secure Side
+
+### Get the TF-M source code
+
+See the [link](https://git.trustedfirmware.org/TF-M/trusted-firmware-m.git/) to get the source code. This port is supported by TF-M version **tag: TF-Mv1.5.0** & **tag: TF-Mv1.6.0**.
+
+### Build TF-M
+
+Please refer to this [link](https://tf-m-user-guide.trustedfirmware.org/docs/technical_references/instructions/tfm_build_instruction.html) to build the secure side.
+_**Note:** ```TFM_NS_MANAGE_NSID``` must be configured as "OFF" when building TF-M_.
+
+## Build the Non-Secure Side
+
+Please copy all the files in ```freertos_kernel\portable\GCC\ARM_CM[23|33|55|85]_NTZ``` into the ```freertos_kernel\portable\ThirdParty\GCC\ARM_TFM``` folder before using this port. Note that TrustZone is enabled in this port. The TF-M runs in the Secure Side.
+
+Please call the API ```tfm_ns_interface_init()``` which is defined in ```\app\tfm_ns_interface.c``` by tf-m-tests
+(tag: TF-Mv1.5.0 & TF-Mv1.6.0) at the very beginning of your application. Otherwise, it will always fail when calling a TF-M service in the Nonsecure Side.
+
+### Configuration in FreeRTOS kernel
+
+* ```configRUN_FREERTOS_SECURE_ONLY```
+This macro should be configured as 0. In this port, TF-M runs in the Secure Side while FreeRTOS
+Kernel runs in the Non-Secure Side.
+
+* ```configENABLE_FPU```
+The setting of this macro is decided by the setting in Secure Side which is platform-specific.
+If the Secure Side enables Non-Secure access to FPU, then this macro can be configured as 0 or 1. Otherwise, this macro can only be configured as 0.
+Please note that Cortex-M23 does not support FPU.
+Please refer to [TF-M documentation](https://tf-m-user-guide.trustedfirmware.org/integration_guide/tfm_fpu_support.html) for FPU usage on the Non-Secure side.
+
+* ```configENABLE_MVE```
+The setting of this macro is decided by the setting in Secure Side which is platform-specific.
+If the Secure Side enables Non-Secure access to MVE, then this macro can be configured as 0 or 1. Otherwise, this macro can only be configured as 0.
+Please note that only Cortex-M55 and Cortex-M85 support MVE.
+Please refer to [TF-M documentation](https://tf-m-user-guide.trustedfirmware.org/integration_guide/tfm_fpu_support.html) for MVE usage on the Non-Secure side.
+
+* ```configENABLE_TRUSTZONE```
+This macro should be configured as 0 because TF-M doesn't use the secure context management function of FreeRTOS. New secure context management might be introduced when TF-M supports multiple secure context.
+
+
+### Integrate TF-M Non-Secure interface with FreeRTOS project
+
+To enable calling TF-M services by the Non-Secure Side, the files below should be included in the FreeRTOS project and built together.
+* files in ```trusted-firmware-m\build\install\interface\src```
+  These files contain the implementation of PSA Functional Developer APIs which can be called by Non-Secure Side directly and PSA Firmware Framework APIs in the IPC model. These files should be taken as part of the Non-Secure source code.
+* files in ```trusted-firmware-m\build\install\interface\include```
+  These files are the necessary header files to call TF-M services.
+* ```trusted-firmware-m\build\install\interface\lib\s_veneers.o```
+  This object file contains all the Non-Secure callable functions exported by
+  TF-M and it should be linked when generating the Non-Secure image.
+
+
+
+*Copyright (c) 2020-2022, Arm Limited. All rights reserved.*

kernel/FreeRTOS/Source/portable/ThirdParty/GCC/ARM_TFM/os_wrapper_freertos.c

@@ -0,0 +1,98 @@
+/*
+ * Copyright (c) 2019-2020, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+/*
+ * This file contains the implementation of APIs which are defined in
+ * os_wrapper/mutex.h by TF-M(tag: TF-Mv1.1). The implementation is based
+ * on FreeRTOS mutex type semaphore.
+ */
+
+#include "os_wrapper/mutex.h"
+
+#include "FreeRTOS.h"
+#include "semphr.h"
+#include "mpu_wrappers.h"
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	/*
+	 * In the static allocation, the RAM is required to hold the semaphore's
+	 * state.
+	 */
+	StaticSemaphore_t xSecureMutexBuffer;
+#endif
+
+void * os_wrapper_mutex_create( void )
+{
+SemaphoreHandle_t xMutexHandle = NULL;
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	xMutexHandle = xSemaphoreCreateMutex();
+#elif( configSUPPORT_STATIC_ALLOCATION == 1 )
+	xMutexHandle = xSemaphoreCreateMutexStatic( &xSecureMutexBuffer );
+#endif
+	return ( void * ) xMutexHandle;
+}
+/*-----------------------------------------------------------*/
+
+uint32_t os_wrapper_mutex_acquire( void * handle, uint32_t timeout )
+{
+BaseType_t xRet;
+
+	if( ! handle )
+		return OS_WRAPPER_ERROR;
+
+	xRet = xSemaphoreTake( ( SemaphoreHandle_t ) handle,
+						   ( timeout == OS_WRAPPER_WAIT_FOREVER ) ?
+                           portMAX_DELAY : ( TickType_t ) timeout );
+
+	if( xRet != pdPASS )
+		return OS_WRAPPER_ERROR;
+	else
+		return OS_WRAPPER_SUCCESS;
+}
+/*-----------------------------------------------------------*/
+
+uint32_t os_wrapper_mutex_release( void * handle )
+{
+BaseType_t xRet;
+
+	if( !handle )
+		return OS_WRAPPER_ERROR;
+
+	xRet = xSemaphoreGive( ( SemaphoreHandle_t ) handle );
+
+	if( xRet != pdPASS )
+		return OS_WRAPPER_ERROR;
+	else
+		return OS_WRAPPER_SUCCESS;
+}
+/*-----------------------------------------------------------*/
+
+uint32_t os_wrapper_mutex_delete( void * handle )
+{
+	vSemaphoreDelete( ( SemaphoreHandle_t ) handle );
+
+	return OS_WRAPPER_SUCCESS;
+}
+/*-----------------------------------------------------------*/

kernel/FreeRTOS/Source/portable/ThirdParty/GCC/ATmega/port.c

@@ -0,0 +1,768 @@
+/*
+ * FreeRTOS Kernel V10.5.1
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+
+#include <stdlib.h>
+
+#include <avr/io.h>
+#include <avr/interrupt.h>
+#include <avr/wdt.h>
+
+#include "FreeRTOS.h"
+#include "task.h"
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the AVR port.
+ *----------------------------------------------------------*/
+
+/* Start tasks with interrupts enabled. */
+#define portFLAGS_INT_ENABLED           ( (StackType_t) 0x80 )
+
+#if defined( portUSE_WDTO)
+    #warning "Watchdog Timer used for scheduler."
+    #define portSCHEDULER_ISR           WDT_vect
+
+#elif defined( portUSE_TIMER0 )
+/* Hardware constants for Timer0. */
+    #warning "Timer0 used for scheduler."
+    #define portSCHEDULER_ISR           TIMER0_COMPA_vect
+    #define portCLEAR_COUNTER_ON_MATCH  ( (uint8_t) _BV(WGM01) )
+    #define portPRESCALE_1024           ( (uint8_t) (_BV(CS02)|_BV(CS00)) )
+    #define portCLOCK_PRESCALER         ( (uint32_t) 1024 )
+    #define portCOMPARE_MATCH_A_INTERRUPT_ENABLE    ( (uint8_t) _BV(OCIE0A) )
+    #define portOCRL                    OCR0A
+    #define portTCCRa                   TCCR0A
+    #define portTCCRb                   TCCR0B
+    #define portTIMSK                   TIMSK0
+    #define portTIFR                    TIFR0
+
+#else
+    #error "No Timer defined for scheduler"
+#endif
+
+/*-----------------------------------------------------------*/
+
+/* We require the address of the pxCurrentTCB variable, but don't want to know
+any details of its type. */
+typedef void TCB_t;
+extern volatile TCB_t * volatile pxCurrentTCB;
+
+/*-----------------------------------------------------------*/
+
+/**
+    Enable the watchdog timer, configuring it for expire after
+    (value) timeout (which is a combination of the WDP0
+    through WDP3 bits).
+
+    This function is derived from <avr/wdt.h> but enables only
+    the interrupt bit (WDIE), rather than the reset bit (WDE).
+
+    Can't find it documented but the WDT, once enabled,
+    rolls over and fires a new interrupt each time.
+
+    See also the symbolic constants WDTO_15MS et al.
+
+    Updated to match avr-libc 2.0.0
+*/
+
+#if defined( portUSE_WDTO)
+
+static __inline__
+__attribute__ ((__always_inline__))
+void wdt_interrupt_enable (const uint8_t value)
+{
+    if (_SFR_IO_REG_P (_WD_CONTROL_REG))
+    {
+        __asm__ __volatile__ (
+                "in __tmp_reg__,__SREG__"   "\n\t"
+                "cli"                       "\n\t"
+                "wdr"                       "\n\t"
+                "out %0, %1"                "\n\t"
+                "out __SREG__,__tmp_reg__"  "\n\t"
+                "out %0, %2"                "\n\t"
+                : /* no outputs */
+                : "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)),
+                "r" ((uint8_t)(_BV(_WD_CHANGE_BIT) | _BV(WDE))),
+                "r" ((uint8_t) ((value & 0x08 ? _WD_PS3_MASK : 0x00) |
+                        _BV(WDIF) | _BV(WDIE) | (value & 0x07)) )
+                : "r0"
+        );
+    }
+    else
+    {
+        __asm__ __volatile__ (
+                "in __tmp_reg__,__SREG__"   "\n\t"
+                "cli"                       "\n\t"
+                "wdr"                       "\n\t"
+                "sts %0, %1"                "\n\t"
+                "out __SREG__,__tmp_reg__"  "\n\t"
+                "sts %0, %2"                "\n\t"
+                : /* no outputs */
+                : "n" (_SFR_MEM_ADDR(_WD_CONTROL_REG)),
+                "r" ((uint8_t)(_BV(_WD_CHANGE_BIT) | _BV(WDE))),
+                "r" ((uint8_t) ((value & 0x08 ? _WD_PS3_MASK : 0x00) |
+                        _BV(WDIF) | _BV(WDIE) | (value & 0x07)) )
+                : "r0"
+        );
+    }
+}
+#endif
+
+/*-----------------------------------------------------------*/
+/**
+    Enable the watchdog timer, configuring it for expire after
+    (value) timeout (which is a combination of the WDP0
+    through WDP3 bits).
+
+    This function is derived from <avr/wdt.h> but enables both
+    the reset bit (WDE), and the interrupt bit (WDIE).
+
+    This will ensure that if the interrupt is not serviced
+    before the second timeout, the AVR will reset.
+
+    Servicing the interrupt automatically clears it,
+    and ensures the AVR does not reset.
+
+    Can't find it documented but the WDT, once enabled,
+    rolls over and fires a new interrupt each time.
+
+    See also the symbolic constants WDTO_15MS et al.
+
+    Updated to match avr-libc 2.0.0
+*/
+
+#if defined( portUSE_WDTO)
+
+static __inline__
+__attribute__ ((__always_inline__))
+void wdt_interrupt_reset_enable (const uint8_t value)
+{
+    if (_SFR_IO_REG_P (_WD_CONTROL_REG))
+    {
+        __asm__ __volatile__ (
+                "in __tmp_reg__,__SREG__"   "\n\t"
+                "cli"                       "\n\t"
+                "wdr"                       "\n\t"
+                "out %0, %1"                "\n\t"
+                "out __SREG__,__tmp_reg__"  "\n\t"
+                "out %0, %2"                "\n\t"
+                : /* no outputs */
+                : "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)),
+                "r" ((uint8_t)(_BV(_WD_CHANGE_BIT) | _BV(WDE))),
+                "r" ((uint8_t) ((value & 0x08 ? _WD_PS3_MASK : 0x00) |
+                        _BV(WDIF) | _BV(WDIE) | _BV(WDE) | (value & 0x07)) )
+                : "r0"
+        );
+    }
+    else
+    {
+        __asm__ __volatile__ (
+                "in __tmp_reg__,__SREG__"   "\n\t"
+                "cli"                       "\n\t"
+                "wdr"                       "\n\t"
+                "sts %0, %1"                "\n\t"
+                "out __SREG__,__tmp_reg__"  "\n\t"
+                "sts %0, %2"                "\n\t"
+                : /* no outputs */
+                : "n" (_SFR_MEM_ADDR(_WD_CONTROL_REG)),
+                "r" ((uint8_t)(_BV(_WD_CHANGE_BIT) | _BV(WDE))),
+                "r" ((uint8_t) ((value & 0x08 ? _WD_PS3_MASK : 0x00) |
+                        _BV(WDIF) | _BV(WDIE) | _BV(WDE) | (value & 0x07)) )
+                : "r0"
+        );
+    }
+}
+#endif
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Macro to save all the general purpose registers, the save the stack pointer
+ * into the TCB.
+ *
+ * The first thing we do is save the flags then disable interrupts. This is to
+ * guard our stack against having a context switch interrupt after we have already
+ * pushed the registers onto the stack - causing the 32 registers to be on the
+ * stack twice.
+ *
+ * r1 is set to zero (__zero_reg__) as the compiler expects it to be thus, however
+ * some of the math routines make use of R1.
+ *
+ * r0 is set to __tmp_reg__ as the compiler expects it to be thus.
+ *
+ * #if defined(__AVR_HAVE_RAMPZ__)
+ * #define __RAMPZ__ 0x3B
+ * #endif
+ *
+ * #if defined(__AVR_3_BYTE_PC__)
+ * #define __EIND__ 0x3C
+ * #endif
+ *
+ * The interrupts will have been disabled during the call to portSAVE_CONTEXT()
+ * so we need not worry about reading/writing to the stack pointer.
+ */
+#if defined(__AVR_3_BYTE_PC__) && defined(__AVR_HAVE_RAMPZ__)
+/* 3-Byte PC Save  with RAMPZ */
+#define portSAVE_CONTEXT()                                                              \
+        __asm__ __volatile__ (  "push   __tmp_reg__                             \n\t"   \
+                                "in     __tmp_reg__, __SREG__                   \n\t"   \
+                                "cli                                            \n\t"   \
+                                "push   __tmp_reg__                             \n\t"   \
+                                "in     __tmp_reg__, 0x3B                       \n\t"   \
+                                "push   __tmp_reg__                             \n\t"   \
+                                "in     __tmp_reg__, 0x3C                       \n\t"   \
+                                "push   __tmp_reg__                             \n\t"   \
+                                "push   __zero_reg__                            \n\t"   \
+                                "clr    __zero_reg__                            \n\t"   \
+                                "push   r2                                      \n\t"   \
+                                "push   r3                                      \n\t"   \
+                                "push   r4                                      \n\t"   \
+                                "push   r5                                      \n\t"   \
+                                "push   r6                                      \n\t"   \
+                                "push   r7                                      \n\t"   \
+                                "push   r8                                      \n\t"   \
+                                "push   r9                                      \n\t"   \
+                                "push   r10                                     \n\t"   \
+                                "push   r11                                     \n\t"   \
+                                "push   r12                                     \n\t"   \
+                                "push   r13                                     \n\t"   \
+                                "push   r14                                     \n\t"   \
+                                "push   r15                                     \n\t"   \
+                                "push   r16                                     \n\t"   \
+                                "push   r17                                     \n\t"   \
+                                "push   r18                                     \n\t"   \
+                                "push   r19                                     \n\t"   \
+                                "push   r20                                     \n\t"   \
+                                "push   r21                                     \n\t"   \
+                                "push   r22                                     \n\t"   \
+                                "push   r23                                     \n\t"   \
+                                "push   r24                                     \n\t"   \
+                                "push   r25                                     \n\t"   \
+                                "push   r26                                     \n\t"   \
+                                "push   r27                                     \n\t"   \
+                                "push   r28                                     \n\t"   \
+                                "push   r29                                     \n\t"   \
+                                "push   r30                                     \n\t"   \
+                                "push   r31                                     \n\t"   \
+                                "lds    r26, pxCurrentTCB                       \n\t"   \
+                                "lds    r27, pxCurrentTCB + 1                   \n\t"   \
+                                "in     __tmp_reg__, __SP_L__                   \n\t"   \
+                                "st     x+, __tmp_reg__                         \n\t"   \
+                                "in     __tmp_reg__, __SP_H__                   \n\t"   \
+                                "st     x+, __tmp_reg__                         \n\t"   \
+                             );
+#elif defined(__AVR_HAVE_RAMPZ__)
+/* 2-Byte PC Save  with RAMPZ */
+#define portSAVE_CONTEXT()                                                              \
+        __asm__ __volatile__ (  "push   __tmp_reg__                             \n\t"   \
+                                "in     __tmp_reg__, __SREG__                   \n\t"   \
+                                "cli                                            \n\t"   \
+                                "push   __tmp_reg__                             \n\t"   \
+                                "in     __tmp_reg__, 0x3B                       \n\t"   \
+                                "push   __tmp_reg__                             \n\t"   \
+                                "push   __zero_reg__                            \n\t"   \
+                                "clr    __zero_reg__                            \n\t"   \
+                                "push   r2                                      \n\t"   \
+                                "push   r3                                      \n\t"   \
+                                "push   r4                                      \n\t"   \
+                                "push   r5                                      \n\t"   \
+                                "push   r6                                      \n\t"   \
+                                "push   r7                                      \n\t"   \
+                                "push   r8                                      \n\t"   \
+                                "push   r9                                      \n\t"   \
+                                "push   r10                                     \n\t"   \
+                                "push   r11                                     \n\t"   \
+                                "push   r12                                     \n\t"   \
+                                "push   r13                                     \n\t"   \
+                                "push   r14                                     \n\t"   \
+                                "push   r15                                     \n\t"   \
+                                "push   r16                                     \n\t"   \
+                                "push   r17                                     \n\t"   \
+                                "push   r18                                     \n\t"   \
+                                "push   r19                                     \n\t"   \
+                                "push   r20                                     \n\t"   \
+                                "push   r21                                     \n\t"   \
+                                "push   r22                                     \n\t"   \
+                                "push   r23                                     \n\t"   \
+                                "push   r24                                     \n\t"   \
+                                "push   r25                                     \n\t"   \
+                                "push   r26                                     \n\t"   \
+                                "push   r27                                     \n\t"   \
+                                "push   r28                                     \n\t"   \
+                                "push   r29                                     \n\t"   \
+                                "push   r30                                     \n\t"   \
+                                "push   r31                                     \n\t"   \
+                                "lds    r26, pxCurrentTCB                       \n\t"   \
+                                "lds    r27, pxCurrentTCB + 1                   \n\t"   \
+                                "in     __tmp_reg__, __SP_L__                   \n\t"   \
+                                "st     x+, __tmp_reg__                         \n\t"   \
+                                "in     __tmp_reg__, __SP_H__                   \n\t"   \
+                                "st     x+, __tmp_reg__                         \n\t"   \
+                             );
+#else
+/* 2-Byte PC Save */
+#define portSAVE_CONTEXT()                                                              \
+        __asm__ __volatile__ (  "push   __tmp_reg__                             \n\t"   \
+                                "in     __tmp_reg__, __SREG__                   \n\t"   \
+                                "cli                                            \n\t"   \
+                                "push   __tmp_reg__                             \n\t"   \
+                                "push   __zero_reg__                            \n\t"   \
+                                "clr    __zero_reg__                            \n\t"   \
+                                "push   r2                                      \n\t"   \
+                                "push   r3                                      \n\t"   \
+                                "push   r4                                      \n\t"   \
+                                "push   r5                                      \n\t"   \
+                                "push   r6                                      \n\t"   \
+                                "push   r7                                      \n\t"   \
+                                "push   r8                                      \n\t"   \
+                                "push   r9                                      \n\t"   \
+                                "push   r10                                     \n\t"   \
+                                "push   r11                                     \n\t"   \
+                                "push   r12                                     \n\t"   \
+                                "push   r13                                     \n\t"   \
+                                "push   r14                                     \n\t"   \
+                                "push   r15                                     \n\t"   \
+                                "push   r16                                     \n\t"   \
+                                "push   r17                                     \n\t"   \
+                                "push   r18                                     \n\t"   \
+                                "push   r19                                     \n\t"   \
+                                "push   r20                                     \n\t"   \
+                                "push   r21                                     \n\t"   \
+                                "push   r22                                     \n\t"   \
+                                "push   r23                                     \n\t"   \
+                                "push   r24                                     \n\t"   \
+                                "push   r25                                     \n\t"   \
+                                "push   r26                                     \n\t"   \
+                                "push   r27                                     \n\t"   \
+                                "push   r28                                     \n\t"   \
+                                "push   r29                                     \n\t"   \
+                                "push   r30                                     \n\t"   \
+                                "push   r31                                     \n\t"   \
+                                "lds    r26, pxCurrentTCB                       \n\t"   \
+                                "lds    r27, pxCurrentTCB + 1                   \n\t"   \
+                                "in     __tmp_reg__, __SP_L__                   \n\t"   \
+                                "st     x+, __tmp_reg__                         \n\t"   \
+                                "in     __tmp_reg__, __SP_H__                   \n\t"   \
+                                "st     x+, __tmp_reg__                         \n\t"   \
+                             );
+#endif
+
+/*
+ * Opposite to portSAVE_CONTEXT().  Interrupts will have been disabled during
+ * the context save so we can write to the stack pointer.
+ */
+#if defined(__AVR_3_BYTE_PC__) && defined(__AVR_HAVE_RAMPZ__)
+/* 3-Byte PC Restore with RAMPZ */
+#define portRESTORE_CONTEXT()                                                           \
+        __asm__ __volatile__ (  "lds    r26, pxCurrentTCB                       \n\t"   \
+                                "lds    r27, pxCurrentTCB + 1                   \n\t"   \
+                                "ld     r28, x+                                 \n\t"   \
+                                "out    __SP_L__, r28                           \n\t"   \
+                                "ld     r29, x+                                 \n\t"   \
+                                "out    __SP_H__, r29                           \n\t"   \
+                                "pop    r31                                     \n\t"   \
+                                "pop    r30                                     \n\t"   \
+                                "pop    r29                                     \n\t"   \
+                                "pop    r28                                     \n\t"   \
+                                "pop    r27                                     \n\t"   \
+                                "pop    r26                                     \n\t"   \
+                                "pop    r25                                     \n\t"   \
+                                "pop    r24                                     \n\t"   \
+                                "pop    r23                                     \n\t"   \
+                                "pop    r22                                     \n\t"   \
+                                "pop    r21                                     \n\t"   \
+                                "pop    r20                                     \n\t"   \
+                                "pop    r19                                     \n\t"   \
+                                "pop    r18                                     \n\t"   \
+                                "pop    r17                                     \n\t"   \
+                                "pop    r16                                     \n\t"   \
+                                "pop    r15                                     \n\t"   \
+                                "pop    r14                                     \n\t"   \
+                                "pop    r13                                     \n\t"   \
+                                "pop    r12                                     \n\t"   \
+                                "pop    r11                                     \n\t"   \
+                                "pop    r10                                     \n\t"   \
+                                "pop    r9                                      \n\t"   \
+                                "pop    r8                                      \n\t"   \
+                                "pop    r7                                      \n\t"   \
+                                "pop    r6                                      \n\t"   \
+                                "pop    r5                                      \n\t"   \
+                                "pop    r4                                      \n\t"   \
+                                "pop    r3                                      \n\t"   \
+                                "pop    r2                                      \n\t"   \
+                                "pop    __zero_reg__                            \n\t"   \
+                                "pop    __tmp_reg__                             \n\t"   \
+                                "out    0x3C, __tmp_reg__                       \n\t"   \
+                                "pop    __tmp_reg__                             \n\t"   \
+                                "out    0x3B, __tmp_reg__                       \n\t"   \
+                                "pop    __tmp_reg__                             \n\t"   \
+                                "out    __SREG__, __tmp_reg__                   \n\t"   \
+                                "pop    __tmp_reg__                             \n\t"   \
+                             );
+#elif defined(__AVR_HAVE_RAMPZ__)
+/* 2-Byte PC Restore with RAMPZ */
+#define portRESTORE_CONTEXT()                                                           \
+        __asm__ __volatile__ (  "lds    r26, pxCurrentTCB                       \n\t"   \
+                                "lds    r27, pxCurrentTCB + 1                   \n\t"   \
+                                "ld     r28, x+                                 \n\t"   \
+                                "out    __SP_L__, r28                           \n\t"   \
+                                "ld     r29, x+                                 \n\t"   \
+                                "out    __SP_H__, r29                           \n\t"   \
+                                "pop    r31                                     \n\t"   \
+                                "pop    r30                                     \n\t"   \
+                                "pop    r29                                     \n\t"   \
+                                "pop    r28                                     \n\t"   \
+                                "pop    r27                                     \n\t"   \
+                                "pop    r26                                     \n\t"   \
+                                "pop    r25                                     \n\t"   \
+                                "pop    r24                                     \n\t"   \
+                                "pop    r23                                     \n\t"   \
+                                "pop    r22                                     \n\t"   \
+                                "pop    r21                                     \n\t"   \
+                                "pop    r20                                     \n\t"   \
+                                "pop    r19                                     \n\t"   \
+                                "pop    r18                                     \n\t"   \
+                                "pop    r17                                     \n\t"   \
+                                "pop    r16                                     \n\t"   \
+                                "pop    r15                                     \n\t"   \
+                                "pop    r14                                     \n\t"   \
+                                "pop    r13                                     \n\t"   \
+                                "pop    r12                                     \n\t"   \
+                                "pop    r11                                     \n\t"   \
+                                "pop    r10                                     \n\t"   \
+                                "pop    r9                                      \n\t"   \
+                                "pop    r8                                      \n\t"   \
+                                "pop    r7                                      \n\t"   \
+                                "pop    r6                                      \n\t"   \
+                                "pop    r5                                      \n\t"   \
+                                "pop    r4                                      \n\t"   \
+                                "pop    r3                                      \n\t"   \
+                                "pop    r2                                      \n\t"   \
+                                "pop    __zero_reg__                            \n\t"   \
+                                "pop    __tmp_reg__                             \n\t"   \
+                                "out    0x3B, __tmp_reg__                       \n\t"   \
+                                "pop    __tmp_reg__                             \n\t"   \
+                                "out    __SREG__, __tmp_reg__                   \n\t"   \
+                                "pop    __tmp_reg__                             \n\t"   \
+                             );
+#else
+/* 2-Byte PC Restore */
+#define portRESTORE_CONTEXT()                                                           \
+        __asm__ __volatile__ (  "lds    r26, pxCurrentTCB                       \n\t"   \
+                                "lds    r27, pxCurrentTCB + 1                   \n\t"   \
+                                "ld     r28, x+                                 \n\t"   \
+                                "out    __SP_L__, r28                           \n\t"   \
+                                "ld     r29, x+                                 \n\t"   \
+                                "out    __SP_H__, r29                           \n\t"   \
+                                "pop    r31                                     \n\t"   \
+                                "pop    r30                                     \n\t"   \
+                                "pop    r29                                     \n\t"   \
+                                "pop    r28                                     \n\t"   \
+                                "pop    r27                                     \n\t"   \
+                                "pop    r26                                     \n\t"   \
+                                "pop    r25                                     \n\t"   \
+                                "pop    r24                                     \n\t"   \
+                                "pop    r23                                     \n\t"   \
+                                "pop    r22                                     \n\t"   \
+                                "pop    r21                                     \n\t"   \
+                                "pop    r20                                     \n\t"   \
+                                "pop    r19                                     \n\t"   \
+                                "pop    r18                                     \n\t"   \
+                                "pop    r17                                     \n\t"   \
+                                "pop    r16                                     \n\t"   \
+                                "pop    r15                                     \n\t"   \
+                                "pop    r14                                     \n\t"   \
+                                "pop    r13                                     \n\t"   \
+                                "pop    r12                                     \n\t"   \
+                                "pop    r11                                     \n\t"   \
+                                "pop    r10                                     \n\t"   \
+                                "pop    r9                                      \n\t"   \
+                                "pop    r8                                      \n\t"   \
+                                "pop    r7                                      \n\t"   \
+                                "pop    r6                                      \n\t"   \
+                                "pop    r5                                      \n\t"   \
+                                "pop    r4                                      \n\t"   \
+                                "pop    r3                                      \n\t"   \
+                                "pop    r2                                      \n\t"   \
+                                "pop    __zero_reg__                            \n\t"   \
+                                "pop    __tmp_reg__                             \n\t"   \
+                                "out    __SREG__, __tmp_reg__                   \n\t"   \
+                                "pop    __tmp_reg__                             \n\t"   \
+                             );
+#endif
+/*-----------------------------------------------------------*/
+
+/*
+ * Perform hardware setup to enable ticks from relevant Timer.
+ */
+static void prvSetupTimerInterrupt( void );
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+uint16_t usAddress;
+    /* Simulate how the stack would look after a call to vPortYield() generated by
+    the compiler. */
+
+    /* The start of the task code will be popped off the stack last, so place
+    it on first. */
+    usAddress = ( uint16_t ) pxCode;
+    *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
+    pxTopOfStack--;
+
+    usAddress >>= 8;
+    *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
+    pxTopOfStack--;
+
+#if defined(__AVR_3_BYTE_PC__)
+    /* The AVR ATmega2560/ATmega2561 have 256KBytes of program memory and a 17-bit
+     * program counter. When a code address is stored on the stack, it takes 3 bytes
+     * instead of 2 for the other ATmega* chips.
+     *
+     * Store 0 as the top byte since we force all task routines to the bottom 128K
+     * of flash. We do this by using the .lowtext label in the linker script.
+     *
+     * In order to do this properly, we would need to get a full 3-byte pointer to
+     * pxCode. That requires a change to GCC. Not likely to happen any time soon.
+     */
+    *pxTopOfStack = 0;
+    pxTopOfStack--;
+#endif
+
+    /* Next simulate the stack as if after a call to portSAVE_CONTEXT().
+    portSAVE_CONTEXT places the flags on the stack immediately after r0
+    to ensure the interrupts get disabled as soon as possible, and so ensuring
+    the stack use is minimal should a context switch interrupt occur. */
+    *pxTopOfStack = ( StackType_t ) 0x00;    /* R0 */
+    pxTopOfStack--;
+    *pxTopOfStack = portFLAGS_INT_ENABLED;
+    pxTopOfStack--;
+
+#if defined(__AVR_3_BYTE_PC__)
+    /* If we have an ATmega256x, we are also saving the EIND register.
+     * We should default to 0.
+     */
+    *pxTopOfStack = ( StackType_t ) 0x00;    /* EIND */
+    pxTopOfStack--;
+#endif
+
+#if defined(__AVR_HAVE_RAMPZ__)
+    /* We are saving the RAMPZ register.
+     * We should default to 0.
+     */
+    *pxTopOfStack = ( StackType_t ) 0x00;    /* RAMPZ */
+    pxTopOfStack--;
+#endif
+
+    /* Now the remaining registers. The compiler expects R1 to be 0. */
+    *pxTopOfStack = ( StackType_t ) 0x00;    /* R1 */
+
+    /* Leave R2 - R23 untouched */
+    pxTopOfStack -= 23;
+
+    /* Place the parameter on the stack in the expected location. */
+    usAddress = ( uint16_t ) pvParameters;
+    *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
+    pxTopOfStack--;
+
+    usAddress >>= 8;
+    *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
+
+    /* Leave register R26 - R31 untouched */
+    pxTopOfStack -= 7;
+
+    return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+    /* Setup the relevant timer hardware to generate the tick. */
+    prvSetupTimerInterrupt();
+
+    /* Restore the context of the first task that is going to run. */
+    portRESTORE_CONTEXT();
+
+    /* Simulate a function call end as generated by the compiler. We will now
+    jump to the start of the task the context of which we have just restored. */
+    __asm__ __volatile__ ( "ret" );
+
+    /* Should not get here. */
+    return pdTRUE;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* It is unlikely that the ATmega port will get stopped. */
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Manual context switch. The first thing we do is save the registers so we
+ * can use a naked attribute.
+ */
+void vPortYield( void ) __attribute__ ( ( hot, flatten, naked ) );
+void vPortYield( void )
+{
+    portSAVE_CONTEXT();
+    vTaskSwitchContext();
+    portRESTORE_CONTEXT();
+
+    __asm__ __volatile__ ( "ret" );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Manual context switch callable from ISRs. The first thing we do is save
+ * the registers so we can use a naked attribute.
+ */
+void vPortYieldFromISR(void) __attribute__ ( ( hot, flatten, naked ) );
+void vPortYieldFromISR(void)
+{
+    portSAVE_CONTEXT();
+    vTaskSwitchContext();
+    portRESTORE_CONTEXT();
+
+    __asm__ __volatile__ ( "reti" );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Context switch function used by the tick. This must be identical to
+ * vPortYield() from the call to vTaskSwitchContext() onwards. The only
+ * difference from vPortYield() is the tick count is incremented as the
+ * call comes from the tick ISR.
+ */
+void vPortYieldFromTick( void ) __attribute__ ( ( hot, flatten, naked ) );
+void vPortYieldFromTick( void )
+{
+    portSAVE_CONTEXT();
+    if( xTaskIncrementTick() != pdFALSE )
+    {
+        vTaskSwitchContext();
+    }
+    portRESTORE_CONTEXT();
+
+    __asm__ __volatile__ ( "ret" );
+}
+/*-----------------------------------------------------------*/
+
+#if defined(portUSE_WDTO)
+/*
+ * Setup WDT to generate a tick interrupt.
+ */
+void prvSetupTimerInterrupt( void )
+{
+    /* reset watchdog */
+    wdt_reset();
+
+    /* set up WDT Interrupt (rather than the WDT Reset). */
+    wdt_interrupt_enable( portUSE_WDTO );
+}
+
+#elif defined (portUSE_TIMER0)
+/*
+ * Setup Timer0 compare match A to generate a tick interrupt.
+ */
+static void prvSetupTimerInterrupt( void )
+{
+uint32_t ulCompareMatch;
+uint8_t ucLowByte;
+
+    /* Using 8bit Timer0 to generate the tick. Correct fuses must be
+    selected for the configCPU_CLOCK_HZ clock.*/
+
+    ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
+
+    /* We only have 8 bits so have to scale 1024 to get our required tick rate. */
+    ulCompareMatch /= portCLOCK_PRESCALER;
+
+    /* Adjust for correct value. */
+    ulCompareMatch -= ( uint32_t ) 1;
+
+    /* Setup compare match value for compare match A. Interrupts are disabled
+    before this is called so we need not worry here. */
+    ucLowByte = ( uint8_t ) ( ulCompareMatch & ( uint32_t ) 0xff );
+    portOCRL = ucLowByte;
+
+    /* Setup clock source and compare match behaviour. */
+    portTCCRa = portCLEAR_COUNTER_ON_MATCH;
+    portTCCRb = portPRESCALE_1024;
+
+
+    /* Enable the interrupt - this is okay as interrupt are currently globally disabled. */
+    ucLowByte = portTIMSK;
+    ucLowByte |= portCOMPARE_MATCH_A_INTERRUPT_ENABLE;
+    portTIMSK = ucLowByte;
+}
+
+#endif
+
+/*-----------------------------------------------------------*/
+
+#if configUSE_PREEMPTION == 1
+
+    /*
+     * Tick ISR for preemptive scheduler. We can use a naked attribute as
+     * the context is saved at the start of vPortYieldFromTick(). The tick
+     * count is incremented after the context is saved.
+     *
+     * use ISR_NOBLOCK where there is an important timer running, that should preempt the scheduler.
+     *
+     */
+    ISR(portSCHEDULER_ISR, ISR_NAKED) __attribute__ ((hot, flatten));
+/*  ISR(portSCHEDULER_ISR, ISR_NAKED ISR_NOBLOCK) __attribute__ ((hot, flatten));
+ */
+    ISR(portSCHEDULER_ISR)
+    {
+        vPortYieldFromTick();
+        __asm__ __volatile__ ( "reti" );
+    }
+#else
+
+    /*
+     * Tick ISR for the cooperative scheduler. All this does is increment the
+     * tick count. We don't need to switch context, this can only be done by
+     * manual calls to taskYIELD();
+     *
+     * use ISR_NOBLOCK where there is an important timer running, that should preempt the scheduler.
+     */
+    ISR(portSCHEDULER_ISR) __attribute__ ((hot, flatten));
+/*  ISR(portSCHEDULER_ISR, ISR_NOBLOCK) __attribute__ ((hot, flatten));
+ */
+    ISR(portSCHEDULER_ISR)
+    {
+        xTaskIncrementTick();
+    }
+#endif
+
+

kernel/FreeRTOS/Source/portable/ThirdParty/GCC/ATmega/portmacro.h

@@ -0,0 +1,157 @@
+/*
+ * FreeRTOS Kernel V10.5.1
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+*/
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+#include <avr/wdt.h>
+
+/* Type definitions. */
+#define portCHAR                    char
+#define portFLOAT                   float
+#define portDOUBLE                  double
+#define portLONG                    long
+#define portSHORT                   int
+
+typedef uint8_t                     StackType_t;
+typedef int8_t                      BaseType_t;
+typedef uint8_t                     UBaseType_t;
+
+#if configUSE_16_BIT_TICKS == 1
+    typedef uint16_t                TickType_t;
+    #define portMAX_DELAY           ( TickType_t ) 0xffff
+#else
+    typedef uint32_t                TickType_t;
+    #define portMAX_DELAY           ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+
+#define portENTER_CRITICAL()        __asm__ __volatile__ (                          \
+                                        "in __tmp_reg__, __SREG__"        "\n\t"    \
+                                        "cli"                             "\n\t"    \
+                                        "push __tmp_reg__"                "\n\t"    \
+                                        ::: "memory"                                \
+                                        )
+
+
+#define portEXIT_CRITICAL()         __asm__ __volatile__ (                          \
+                                        "pop __tmp_reg__"                 "\n\t"    \
+                                        "out __SREG__, __tmp_reg__"       "\n\t"    \
+                                        ::: "memory"                                \
+                                        )
+
+
+#define portDISABLE_INTERRUPTS()    __asm__ __volatile__ ( "cli" ::: "memory")
+#define portENABLE_INTERRUPTS()     __asm__ __volatile__ ( "sei" ::: "memory")
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+
+/* System Tick  - Scheduler timer
+ * Prefer to use the enhanced Watchdog Timer, but also Timer0 is ok.
+ */
+
+#if defined(WDIE) && defined(WDIF)              /* If Enhanced WDT with interrupt capability is available */
+
+#define portUSE_WDTO                WDTO_15MS   /* use the Watchdog Timer for xTaskIncrementTick */
+
+/* Watchdog period options:         WDTO_15MS
+                                    WDTO_30MS
+                                    WDTO_60MS
+                                    WDTO_120MS
+                                    WDTO_250MS
+                                    WDTO_500MS
+                                    WDTO_1S
+                                    WDTO_2S
+*/
+
+#else
+
+#define portUSE_TIMER0                          /* use the 8-bit Timer0 for xTaskIncrementTick */
+
+#endif
+
+#define portSTACK_GROWTH            ( -1 )
+
+/* Timing for the scheduler.
+ * Watchdog Timer is 128kHz nominal,
+ * but 120 kHz at 5V DC and 25 degrees is actually more accurate,
+ * from data sheet.
+ */
+#if defined( portUSE_WDTO )
+#define portTICK_PERIOD_MS          ( (TickType_t) _BV( portUSE_WDTO + 4 ) )
+#else
+#define portTICK_PERIOD_MS          ( (TickType_t) 1000 / configTICK_RATE_HZ )
+#endif
+
+#define portBYTE_ALIGNMENT          1
+#define portNOP()                   __asm__ __volatile__ ( "nop" );
+/*-----------------------------------------------------------*/
+
+/* Kernel utilities. */
+extern void vPortYield( void )      __attribute__ ( ( naked ) );
+#define portYIELD()                 vPortYield()
+
+extern void vPortYieldFromISR( void )   __attribute__ ( ( naked ) );
+#define portYIELD_FROM_ISR()            vPortYieldFromISR()
+/*-----------------------------------------------------------*/
+
+#if defined(__AVR_3_BYTE_PC__)
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+
+/* Add .lowtext tag from the avr linker script avr6.x for ATmega2560 and ATmega2561
+ * to make sure functions are loaded in low memory.
+ */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) __attribute__ ((section (".lowtext")))
+#else
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#endif
+
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */

kernel/FreeRTOS/Source/portable/ThirdParty/GCC/ATmega/readme.md

@@ -0,0 +1,86 @@
+<h2>ATmegaxxxx</h2>
+
+__Port for generalised Microchip ATmega architecture__
+
+<h3>Description</h3>
+
+This port provides a basis for supporting all modern ATmega devices using either the Enhanced Watchdog Timer, or Timer0 (an 8-bit Timer generally available across the whole range).
+
+This initial commit contains the information required to build with System Tick being generated by either the:
+- Watchdog Timer, or
+- Timer0 - an 8-bit Timer, or
+- TimerN - a 16-bit Timer which will be configured by the user.
+
+Further commits can add support for 16-bit Timers available on many relevant devices. The availability of these 16-bit Timers is somewhat device specific, and these complex and highly configurable Timers are often used to generate phase correct PWM timing (for example) and they would be wasted as a simple System Tick.
+
+The port also provides support for the 3 byte program counter devices __ATmega2560__ and __ATmega2561__. Specific to these two devices the `EIND` register need to be preserved during a context switch. Also, due to a limitation in GCC, the scheduler needs to reside in the lower 128kB of flash for both of these devices. This is achieved by adding the `.lowtext` section attribute to the function prototype.
+
+To build generic Microchip (AVR) ATmega support the similarities across the family must be considered, and differences respected. Some comments on the strategy follow.
+
+<h3>System Tick</h3>
+
+The Microchip (AVR) ATmega family has limited Timer and Pin capabilities, and is designed to be used in physical applications, controlling hardware with PWM and recognising level and edge voltage changes. It does this mainly through the use of 16-bit Timers (for generating phase correct PWM by up/down counting), and Pins attached to Interrupts. The 8-bit Timers are also attached to Pins, and they can be used for more simple timing tasks, requiring only a single counting direction.
+
+The Timers not attached to Pins (and therefore not impacting the application of the device) are some 16-bit Timers (very device dependent, eg Timer3 on 1284p), The RTC Timer, and the Watch Dog Timer.
+
+The Watch Dog Timer is configured identically across most of the ATmega devices. It comes in two variants. 1. Old style (eg ATmega32) which does not have an Interrupt capability, and hence on these old devices cannot be used as the System Tick. and 2. New style enhanced WDT, which can generate an Interrupt, and is available on every relevant device.
+
+Using the Watch Dog Timer (WDT) to generate the System Tick does not impact its use as a watch dog. It can be configured to generate a System Tick interrupt, and then one period later to Reset the device if the interrupt is not serviced.
+
+Configuration and usage of the WDT is covered in `<avr/wdt.h>` which was revised in avr-libc 2.0.0.
+
+Two additional WDT functions are provided in `port.c`, which extend avr-libc functions to enable the WDT Interrupt without enabling Reset `wdt_interrupt_enable()`, and to enable both the Interrupt and the Reset `wdt_interrupt_reset_enable()`.
+
+<h3>3 Byte PC Devices</h3>
+
+The ATtiny, ATmega, ATxmega families can optionally support both 3 byte PC and 3 byte RAM addresses. However, focusing on just the ATmega family only two devices have a large Flash requiring them to use 3 byte PC. These are the __ATmega2560__ and __ATmega2561__. This PR provides support for these two devices in two ways.
+
+ - providing `portSAVE_CONTEXT()` and `portRESTORE_CONTEXT` saving both the __RAMPZ__ and __EIND__ registers.
+ - providing a `portTASK_FUNCTION_PROTO()` with the linker attribute `.lowtext` which is used to ensure that the scheduler and relevant functions remain in the lower 128kB of Flash.
+
+For devices which can support __XRAM__ and have the __RAMPZ__ register, this register is also preserved during the context switch.
+
+<h3>Interrupt Nesting</h3>
+
+The ATmega family does not support interrupt nesting, having only one interrupt priority. This means that when the Scheduler is running, interrupts are normally disabled.
+
+When a very time critical process is running, based on microsecond timing generated by one of the Timers, it is important to re-enable interrupts as early as possible in processing a Yield. Fortunately, this is supported through the use of the `NO_BLOCK` decorator when defining the Interrupt Service Routine.
+
+The `NO_BLOCK` decorator will enable the global interrupt early in the handling of an ISR (in this case for the Scheduler), and enable interrupts to be nested. Using this method, I've been able to successfully implement an [Audio Synthesiser](https://feilipu.me/2015/06/02/goldilocks-analogue-synthesizer/) with less than 83 microseconds for each cycle, whilst still running the Scheduler to handle display and input.
+
+Using `NO_BLOCK` is optional, and should only be done if a critical Timer should interrupt the Scheduler.
+
+<h3>Heap Management</h3>
+
+Most users of FreeRTOS will choose to manage their own heap using one of the pre-allocated heap management algorithms, but for those that choose to use `heap_3.c`, the wrappered `malloc()` method, there is an issue that needs to be addressed.
+
+The avr-libc library assumes that the stack will always be above the heap, and does a check for this when responding to a `malloc()` request. This is not the case when Tasks are running, as their stack is located in the early allocated heap address ranges which will be below free heap memory, and so the `malloc()` request will fail even though heap space is available.
+
+To avoid this issue causing `pvPort_Malloc()` to failing, the user needs to issue this tuning statement BEFORE they use the heap, or use the `xTaskCreate()` API.
+
+```c
+if( __malloc_heap_end == 0 )
+    __malloc_heap_end = (char *)(RAMEND - __malloc_margin);
+```
+Unfortunately in the repository there is nowhere sensible to include this statement as it should be included early in the `main()` function.
+
+For devices which can support __XRAM__ the user will need to tune the location of stack and heap according to their own requirements.
+
+<h3>Supported Devices</h3>
+
+ATmega devices with __ENHANCED WDT__ Interrupt capability - will use WDT.
+
+ - ATmega8U2/16U2/32U2 -> 2kB RAM
+ - ATmega16U4/32U4 - Arduino Leonardo -> 2.5kB RAM
+ - ATmega48PB/88PB/168PB/328PB - Arduino Uno -> 2kB RAM
+ - ATmega164PA/324PA/644PA/1284P - Goldilocks -> __16kB RAM__
+ - ATmega324PB -> 2kB RAM
+ - ATmega640/1280/2560/1281/2561 - Arduino Mega -> __8kB RAM + XRAM__
+
+ATmega devices without enhanced __WDT__ Interrupt capability - will use a 8-bit or 16-bit Timer.
+
+ - ATmega8A/16A/32A/64A/128A -> 4kB RAM
+ - ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P -> 4kB RAM
+ - ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P -> 4kB RAM
+ - ATmega808/809/1608/1609/3208/3209/4808/4809 - megaAVR 0-Series -> 6kB RAM
+ 

kernel/FreeRTOS/Source/portable/ThirdParty/GCC/Posix/FreeRTOS-simulator-for-Linux.url

@@ -0,0 +1,5 @@
+[{000214A0-0000-0000-C000-000000000046}]
+Prop3=19,11
+[InternetShortcut]
+IDList=
+URL=https://www.freertos.org/FreeRTOS-simulator-for-Linux.html

kernel/FreeRTOS/Source/portable/ThirdParty/GCC/Posix/port.c

@@ -0,0 +1,583 @@
+/*
+ * FreeRTOS Kernel V10.5.1
+ * Copyright (C) 2020 Cambridge Consultants Ltd.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/*-----------------------------------------------------------
+* Implementation of functions defined in portable.h for the Posix port.
+*
+* Each task has a pthread which eases use of standard debuggers
+* (allowing backtraces of tasks etc). Threads for tasks that are not
+* running are blocked in sigwait().
+*
+* Task switch is done by resuming the thread for the next task by
+* signaling the condition variable and then waiting on a condition variable
+* with the current thread.
+*
+* The timer interrupt uses SIGALRM and care is taken to ensure that
+* the signal handler runs only on the thread for the current task.
+*
+* Use of part of the standard C library requires care as some
+* functions can take pthread mutexes internally which can result in
+* deadlocks as the FreeRTOS kernel can switch tasks while they're
+* holding a pthread mutex.
+*
+* stdio (printf() and friends) should be called from a single task
+* only or serialized with a FreeRTOS primitive such as a binary
+* semaphore or mutex.
+*----------------------------------------------------------*/
+#include "portmacro.h"
+
+#include <errno.h>
+#include <pthread.h>
+#include <signal.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/time.h>
+#include <sys/times.h>
+#include <time.h>
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "timers.h"
+#include "utils/wait_for_event.h"
+/*-----------------------------------------------------------*/
+
+#define SIG_RESUME    SIGUSR1
+
+typedef struct THREAD
+{
+    pthread_t pthread;
+    pdTASK_CODE pxCode;
+    void * pvParams;
+    BaseType_t xDying;
+    struct event * ev;
+} Thread_t;
+
+/*
+ * The additional per-thread data is stored at the beginning of the
+ * task's stack.
+ */
+static inline Thread_t * prvGetThreadFromTask( TaskHandle_t xTask )
+{
+    StackType_t * pxTopOfStack = *( StackType_t ** ) xTask;
+
+    return ( Thread_t * ) ( pxTopOfStack + 1 );
+}
+
+/*-----------------------------------------------------------*/
+
+static pthread_once_t hSigSetupThread = PTHREAD_ONCE_INIT;
+static sigset_t xAllSignals;
+static sigset_t xSchedulerOriginalSignalMask;
+static pthread_t hMainThread = ( pthread_t ) NULL;
+static volatile portBASE_TYPE uxCriticalNesting;
+/*-----------------------------------------------------------*/
+
+static portBASE_TYPE xSchedulerEnd = pdFALSE;
+/*-----------------------------------------------------------*/
+
+static void prvSetupSignalsAndSchedulerPolicy( void );
+static void prvSetupTimerInterrupt( void );
+static void * prvWaitForStart( void * pvParams );
+static void prvSwitchThread( Thread_t * xThreadToResume,
+                             Thread_t * xThreadToSuspend );
+static void prvSuspendSelf( Thread_t * thread );
+static void prvResumeThread( Thread_t * xThreadId );
+static void vPortSystemTickHandler( int sig );
+static void vPortStartFirstTask( void );
+static void prvPortYieldFromISR( void );
+/*-----------------------------------------------------------*/
+
+static void prvFatalError( const char * pcCall,
+                           int iErrno )
+{
+    fprintf( stderr, "%s: %s\n", pcCall, strerror( iErrno ) );
+    abort();
+}
+
+/*
+ * See header file for description.
+ */
+portSTACK_TYPE * pxPortInitialiseStack( portSTACK_TYPE * pxTopOfStack,
+                                        portSTACK_TYPE * pxEndOfStack,
+                                        pdTASK_CODE pxCode,
+                                        void * pvParameters )
+{
+    Thread_t * thread;
+    pthread_attr_t xThreadAttributes;
+    size_t ulStackSize;
+    int iRet;
+
+    ( void ) pthread_once( &hSigSetupThread, prvSetupSignalsAndSchedulerPolicy );
+
+    /*
+     * Store the additional thread data at the start of the stack.
+     */
+    thread = ( Thread_t * ) ( pxTopOfStack + 1 ) - 1;
+    pxTopOfStack = ( portSTACK_TYPE * ) thread - 1;
+    ulStackSize = ( pxTopOfStack + 1 - pxEndOfStack ) * sizeof( *pxTopOfStack );
+
+    thread->pxCode = pxCode;
+    thread->pvParams = pvParameters;
+    thread->xDying = pdFALSE;
+
+    pthread_attr_init( &xThreadAttributes );
+    iRet = pthread_attr_setstack( &xThreadAttributes, pxEndOfStack, ulStackSize );
+    if( iRet != 0 )
+    {
+        fprintf( stderr, "[WARN] pthread_attr_setstack failed with return value: %d. Default stack will be used.\n", iRet );
+        fprintf( stderr, "[WARN] Increase the stack size to PTHREAD_STACK_MIN.\n" );
+    }
+
+    thread->ev = event_create();
+
+    vPortEnterCritical();
+
+    iRet = pthread_create( &thread->pthread, &xThreadAttributes,
+                           prvWaitForStart, thread );
+
+    if( iRet != 0 )
+    {
+        prvFatalError( "pthread_create", iRet );
+    }
+
+    vPortExitCritical();
+
+    return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+void vPortStartFirstTask( void )
+{
+    Thread_t * pxFirstThread = prvGetThreadFromTask( xTaskGetCurrentTaskHandle() );
+
+    /* Start the first task. */
+    prvResumeThread( pxFirstThread );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+portBASE_TYPE xPortStartScheduler( void )
+{
+    int iSignal;
+    sigset_t xSignals;
+
+    hMainThread = pthread_self();
+
+    /* Start the timer that generates the tick ISR(SIGALRM).
+     * Interrupts are disabled here already. */
+    prvSetupTimerInterrupt();
+
+    /*
+     * Block SIG_RESUME before starting any tasks so the main thread can sigwait on it.
+     * To sigwait on an unblocked signal is undefined.
+     * https://pubs.opengroup.org/onlinepubs/009604499/functions/sigwait.html
+     */
+    sigemptyset( &xSignals );
+    sigaddset( &xSignals, SIG_RESUME );
+    ( void ) pthread_sigmask( SIG_BLOCK, &xSignals, NULL );
+
+    /* Start the first task. */
+    vPortStartFirstTask();
+
+    /* Wait until signaled by vPortEndScheduler(). */
+    while( xSchedulerEnd != pdTRUE )
+    {
+        sigwait( &xSignals, &iSignal );
+    }
+
+    /* Cancel the Idle task and free its resources */
+    #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
+        vPortCancelThread( xTaskGetIdleTaskHandle() );
+    #endif
+
+    #if ( configUSE_TIMERS == 1 )
+        /* Cancel the Timer task and free its resources */
+        vPortCancelThread( xTimerGetTimerDaemonTaskHandle() );
+    #endif /* configUSE_TIMERS */
+
+    /* Restore original signal mask. */
+    ( void ) pthread_sigmask( SIG_SETMASK, &xSchedulerOriginalSignalMask, NULL );
+
+    return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+    struct itimerval itimer;
+    struct sigaction sigtick;
+    Thread_t * xCurrentThread;
+
+    /* Stop the timer and ignore any pending SIGALRMs that would end
+     * up running on the main thread when it is resumed. */
+    itimer.it_value.tv_sec = 0;
+    itimer.it_value.tv_usec = 0;
+
+    itimer.it_interval.tv_sec = 0;
+    itimer.it_interval.tv_usec = 0;
+    ( void ) setitimer( ITIMER_REAL, &itimer, NULL );
+
+    sigtick.sa_flags = 0;
+    sigtick.sa_handler = SIG_IGN;
+    sigemptyset( &sigtick.sa_mask );
+    sigaction( SIGALRM, &sigtick, NULL );
+
+    /* Signal the scheduler to exit its loop. */
+    xSchedulerEnd = pdTRUE;
+    ( void ) pthread_kill( hMainThread, SIG_RESUME );
+
+    xCurrentThread = prvGetThreadFromTask( xTaskGetCurrentTaskHandle() );
+    prvSuspendSelf( xCurrentThread );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+    if( uxCriticalNesting == 0 )
+    {
+        vPortDisableInterrupts();
+    }
+
+    uxCriticalNesting++;
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+    uxCriticalNesting--;
+
+    /* If we have reached 0 then re-enable the interrupts. */
+    if( uxCriticalNesting == 0 )
+    {
+        vPortEnableInterrupts();
+    }
+}
+/*-----------------------------------------------------------*/
+
+static void prvPortYieldFromISR( void )
+{
+    Thread_t * xThreadToSuspend;
+    Thread_t * xThreadToResume;
+
+    xThreadToSuspend = prvGetThreadFromTask( xTaskGetCurrentTaskHandle() );
+
+    vTaskSwitchContext();
+
+    xThreadToResume = prvGetThreadFromTask( xTaskGetCurrentTaskHandle() );
+
+    prvSwitchThread( xThreadToResume, xThreadToSuspend );
+}
+/*-----------------------------------------------------------*/
+
+void vPortYield( void )
+{
+    vPortEnterCritical();
+
+    prvPortYieldFromISR();
+
+    vPortExitCritical();
+}
+/*-----------------------------------------------------------*/
+
+void vPortDisableInterrupts( void )
+{
+    pthread_sigmask( SIG_BLOCK, &xAllSignals, NULL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnableInterrupts( void )
+{
+    pthread_sigmask( SIG_UNBLOCK, &xAllSignals, NULL );
+}
+/*-----------------------------------------------------------*/
+
+portBASE_TYPE xPortSetInterruptMask( void )
+{
+    /* Interrupts are always disabled inside ISRs (signals
+     * handlers). */
+    return pdTRUE;
+}
+/*-----------------------------------------------------------*/
+
+void vPortClearInterruptMask( portBASE_TYPE xMask )
+{
+    ( void ) xMask;
+}
+/*-----------------------------------------------------------*/
+
+static uint64_t prvGetTimeNs( void )
+{
+    struct timespec t;
+
+    clock_gettime( CLOCK_MONOTONIC, &t );
+
+    return t.tv_sec * 1000000000ULL + t.tv_nsec;
+}
+
+static uint64_t prvStartTimeNs;
+
+/* commented as part of the code below in vPortSystemTickHandler,
+ * to adjust timing according to full demo requirements */
+/* static uint64_t prvTickCount; */
+
+/*
+ * Setup the systick timer to generate the tick interrupts at the required
+ * frequency.
+ */
+void prvSetupTimerInterrupt( void )
+{
+    struct itimerval itimer;
+    int iRet;
+
+    /* Initialise the structure with the current timer information. */
+    iRet = getitimer( ITIMER_REAL, &itimer );
+
+    if( iRet == -1 )
+    {
+        prvFatalError( "getitimer", errno );
+    }
+
+    /* Set the interval between timer events. */
+    itimer.it_interval.tv_sec = 0;
+    itimer.it_interval.tv_usec = portTICK_RATE_MICROSECONDS;
+
+    /* Set the current count-down. */
+    itimer.it_value.tv_sec = 0;
+    itimer.it_value.tv_usec = portTICK_RATE_MICROSECONDS;
+
+    /* Set-up the timer interrupt. */
+    iRet = setitimer( ITIMER_REAL, &itimer, NULL );
+
+    if( iRet == -1 )
+    {
+        prvFatalError( "setitimer", errno );
+    }
+
+    prvStartTimeNs = prvGetTimeNs();
+}
+/*-----------------------------------------------------------*/
+
+static void vPortSystemTickHandler( int sig )
+{
+    Thread_t * pxThreadToSuspend;
+    Thread_t * pxThreadToResume;
+
+    ( void ) sig;
+
+/* uint64_t xExpectedTicks; */
+
+    uxCriticalNesting++; /* Signals are blocked in this signal handler. */
+
+    #if ( configUSE_PREEMPTION == 1 )
+        pxThreadToSuspend = prvGetThreadFromTask( xTaskGetCurrentTaskHandle() );
+    #endif
+
+    /* Tick Increment, accounting for any lost signals or drift in
+     * the timer. */
+
+/*
+ *      Comment code to adjust timing according to full demo requirements
+ *      xExpectedTicks = (prvGetTimeNs() - prvStartTimeNs)
+ *        / (portTICK_RATE_MICROSECONDS * 1000);
+ * do { */
+    xTaskIncrementTick();
+
+/*        prvTickCount++;
+ *    } while (prvTickCount < xExpectedTicks);
+ */
+
+    #if ( configUSE_PREEMPTION == 1 )
+        /* Select Next Task. */
+        vTaskSwitchContext();
+
+        pxThreadToResume = prvGetThreadFromTask( xTaskGetCurrentTaskHandle() );
+
+        prvSwitchThread( pxThreadToResume, pxThreadToSuspend );
+    #endif
+
+    uxCriticalNesting--;
+}
+/*-----------------------------------------------------------*/
+
+void vPortThreadDying( void * pxTaskToDelete,
+                       volatile BaseType_t * pxPendYield )
+{
+    Thread_t * pxThread = prvGetThreadFromTask( pxTaskToDelete );
+
+    ( void ) pxPendYield;
+
+    pxThread->xDying = pdTRUE;
+}
+
+void vPortCancelThread( void * pxTaskToDelete )
+{
+    Thread_t * pxThreadToCancel = prvGetThreadFromTask( pxTaskToDelete );
+
+    /*
+     * The thread has already been suspended so it can be safely cancelled.
+     */
+    pthread_cancel( pxThreadToCancel->pthread );
+    pthread_join( pxThreadToCancel->pthread, NULL );
+    event_delete( pxThreadToCancel->ev );
+}
+/*-----------------------------------------------------------*/
+
+static void * prvWaitForStart( void * pvParams )
+{
+    Thread_t * pxThread = pvParams;
+
+    prvSuspendSelf( pxThread );
+
+    /* Resumed for the first time, unblocks all signals. */
+    uxCriticalNesting = 0;
+    vPortEnableInterrupts();
+
+    /* Call the task's entry point. */
+    pxThread->pxCode( pxThread->pvParams );
+
+    /* A function that implements a task must not exit or attempt to return to
+     * its caller as there is nothing to return to. If a task wants to exit it
+     * should instead call vTaskDelete( NULL ). Artificially force an assert()
+     * to be triggered if configASSERT() is defined, so application writers can
+     * catch the error. */
+    configASSERT( pdFALSE );
+
+    return NULL;
+}
+/*-----------------------------------------------------------*/
+
+static void prvSwitchThread( Thread_t * pxThreadToResume,
+                             Thread_t * pxThreadToSuspend )
+{
+    BaseType_t uxSavedCriticalNesting;
+
+    if( pxThreadToSuspend != pxThreadToResume )
+    {
+        /*
+         * Switch tasks.
+         *
+         * The critical section nesting is per-task, so save it on the
+         * stack of the current (suspending thread), restoring it when
+         * we switch back to this task.
+         */
+        uxSavedCriticalNesting = uxCriticalNesting;
+
+        prvResumeThread( pxThreadToResume );
+
+        if( pxThreadToSuspend->xDying == pdTRUE )
+        {
+            pthread_exit( NULL );
+        }
+
+        prvSuspendSelf( pxThreadToSuspend );
+
+        uxCriticalNesting = uxSavedCriticalNesting;
+    }
+}
+/*-----------------------------------------------------------*/
+
+static void prvSuspendSelf( Thread_t * thread )
+{
+    /*
+     * Suspend this thread by waiting for a pthread_cond_signal event.
+     *
+     * A suspended thread must not handle signals (interrupts) so
+     * all signals must be blocked by calling this from:
+     *
+     * - Inside a critical section (vPortEnterCritical() /
+     *   vPortExitCritical()).
+     *
+     * - From a signal handler that has all signals masked.
+     *
+     * - A thread with all signals blocked with pthread_sigmask().
+     */
+    event_wait( thread->ev );
+}
+
+/*-----------------------------------------------------------*/
+
+static void prvResumeThread( Thread_t * xThreadId )
+{
+    if( pthread_self() != xThreadId->pthread )
+    {
+        event_signal( xThreadId->ev );
+    }
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupSignalsAndSchedulerPolicy( void )
+{
+    struct sigaction sigtick;
+    int iRet;
+
+    hMainThread = pthread_self();
+
+    /* Initialise common signal masks. */
+    sigfillset( &xAllSignals );
+
+    /* Don't block SIGINT so this can be used to break into GDB while
+     * in a critical section. */
+    sigdelset( &xAllSignals, SIGINT );
+
+    /*
+     * Block all signals in this thread so all new threads
+     * inherits this mask.
+     *
+     * When a thread is resumed for the first time, all signals
+     * will be unblocked.
+     */
+    ( void ) pthread_sigmask( SIG_SETMASK,
+                              &xAllSignals,
+                              &xSchedulerOriginalSignalMask );
+
+    sigtick.sa_flags = 0;
+    sigtick.sa_handler = vPortSystemTickHandler;
+    sigfillset( &sigtick.sa_mask );
+
+    iRet = sigaction( SIGALRM, &sigtick, NULL );
+
+    if( iRet == -1 )
+    {
+        prvFatalError( "sigaction", errno );
+    }
+}
+/*-----------------------------------------------------------*/
+
+unsigned long ulPortGetRunTime( void )
+{
+    struct tms xTimes;
+
+    times( &xTimes );
+
+    return ( unsigned long ) xTimes.tms_utime;
+}
+/*-----------------------------------------------------------*/

kernel/FreeRTOS/Source/portable/ThirdParty/GCC/Posix/portmacro.h

@@ -0,0 +1,135 @@
+/*
+ * FreeRTOS Kernel V10.5.1
+ * Copyright 2020 Cambridge Consultants Ltd.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <limits.h>
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	unsigned long
+#define portBASE_TYPE	long
+#define portPOINTER_SIZE_TYPE intptr_t
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+typedef unsigned long TickType_t;
+#define portMAX_DELAY ( TickType_t ) ULONG_MAX
+
+#define portTICK_TYPE_IS_ATOMIC 1
+
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portHAS_STACK_OVERFLOW_CHECKING	( 1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portTICK_RATE_MICROSECONDS	( ( portTickType ) 1000000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT			8
+/*-----------------------------------------------------------*/
+
+/* Scheduler utilities. */
+extern void vPortYield( void );
+
+#define portYIELD() vPortYield()
+
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) vPortYield()
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+extern void vPortDisableInterrupts( void );
+extern void vPortEnableInterrupts( void );
+#define portSET_INTERRUPT_MASK()        ( vPortDisableInterrupts() )
+#define portCLEAR_INTERRUPT_MASK()      ( vPortEnableInterrupts() )
+
+extern portBASE_TYPE xPortSetInterruptMask( void );
+extern void vPortClearInterruptMask( portBASE_TYPE xMask );
+
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+#define portSET_INTERRUPT_MASK_FROM_ISR()		xPortSetInterruptMask()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	vPortClearInterruptMask(x)
+#define portDISABLE_INTERRUPTS()				portSET_INTERRUPT_MASK()
+#define portENABLE_INTERRUPTS()					portCLEAR_INTERRUPT_MASK()
+#define portENTER_CRITICAL()					vPortEnterCritical()
+#define portEXIT_CRITICAL()						vPortExitCritical()
+
+/*-----------------------------------------------------------*/
+
+extern void vPortThreadDying( void *pxTaskToDelete, volatile BaseType_t *pxPendYield );
+extern void vPortCancelThread( void *pxTaskToDelete );
+#define portPRE_TASK_DELETE_HOOK( pvTaskToDelete, pxPendYield ) vPortThreadDying( ( pvTaskToDelete ), ( pxPendYield ) )
+#define portCLEAN_UP_TCB( pxTCB )	vPortCancelThread( pxTCB )
+/*-----------------------------------------------------------*/
+
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+/*
+ * Tasks run in their own pthreads and context switches between them
+ * are always a full memory barrier. ISRs are emulated as signals
+ * which also imply a full memory barrier.
+ *
+ * Thus, only a compilier barrier is needed to prevent the compiler
+ * reordering.
+ */
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+
+extern unsigned long ulPortGetRunTime( void );
+#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() /* no-op */
+#define portGET_RUN_TIME_COUNTER_VALUE()         ulPortGetRunTime()
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */

kernel/FreeRTOS/Source/portable/ThirdParty/GCC/Posix/utils/wait_for_event.c

@@ -0,0 +1,104 @@
+/*
+ * FreeRTOS Kernel V10.5.1
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#include <pthread.h>
+#include <stdlib.h>
+#include <errno.h>
+
+#include "wait_for_event.h"
+
+struct event
+{
+    pthread_mutex_t mutex;
+    pthread_cond_t cond;
+    bool event_triggered;
+};
+
+struct event * event_create( void )
+{
+    struct event * ev = malloc( sizeof( struct event ) );
+
+    ev->event_triggered = false;
+    pthread_mutex_init( &ev->mutex, NULL );
+    pthread_cond_init( &ev->cond, NULL );
+    return ev;
+}
+
+void event_delete( struct event * ev )
+{
+    pthread_mutex_destroy( &ev->mutex );
+    pthread_cond_destroy( &ev->cond );
+    free( ev );
+}
+
+bool event_wait( struct event * ev )
+{
+    pthread_mutex_lock( &ev->mutex );
+
+    while( ev->event_triggered == false )
+    {
+        pthread_cond_wait( &ev->cond, &ev->mutex );
+    }
+
+    ev->event_triggered = false;
+    pthread_mutex_unlock( &ev->mutex );
+    return true;
+}
+bool event_wait_timed( struct event * ev,
+                       time_t ms )
+{
+    struct timespec ts;
+    int ret = 0;
+
+    clock_gettime( CLOCK_REALTIME, &ts );
+    ts.tv_sec += ms / 1000;
+    ts.tv_nsec += ((ms % 1000) * 1000000);
+    pthread_mutex_lock( &ev->mutex );
+
+    while( (ev->event_triggered == false) && (ret == 0) )
+    {
+        ret = pthread_cond_timedwait( &ev->cond, &ev->mutex, &ts );
+
+        if( ( ret == -1 ) && ( errno == ETIMEDOUT ) )
+        {
+            return false;
+        }
+    }
+
+    ev->event_triggered = false;
+    pthread_mutex_unlock( &ev->mutex );
+    return true;
+}
+
+void event_signal( struct event * ev )
+{
+    pthread_mutex_lock( &ev->mutex );
+    ev->event_triggered = true;
+    pthread_cond_signal( &ev->cond );
+    pthread_mutex_unlock( &ev->mutex );
+}

kernel/FreeRTOS/Source/portable/ThirdParty/GCC/Posix/utils/wait_for_event.h

@@ -0,0 +1,46 @@
+/*
+ * FreeRTOS Kernel V10.5.1
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef _WAIT_FOR_EVENT_H_
+#define _WAIT_FOR_EVENT_H_
+
+#include <stdbool.h>
+#include <time.h>
+
+struct event;
+
+struct event * event_create( void );
+void event_delete( struct event * );
+bool event_wait( struct event * ev );
+bool event_wait_timed( struct event * ev,
+                       time_t ms );
+void event_signal( struct event * ev );
+
+
+
+#endif /* ifndef _WAIT_FOR_EVENT_H_ */

kernel/FreeRTOS/Source/portable/ThirdParty/GCC/RISC-V/README-for-info-on-official-MIT-license-port.txt

@@ -0,0 +1,6 @@
+The official and MIT licensed FreeRTOS ports for RISC-V are located in the following directories:
+\FreeRTOS\Source\portable\GCC\RISC-V
+\FreeRTOS\Source\portable\IAR\RISC-V
+
+Also so https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
+

kernel/FreeRTOS/Source/portable/ThirdParty/GCC/RP2040/.gitignore

@@ -0,0 +1,2 @@
+**/cmake-*
+.idea

kernel/FreeRTOS/Source/portable/ThirdParty/GCC/RP2040/CMakeLists.txt

@@ -0,0 +1,51 @@
+cmake_minimum_required(VERSION 3.13)
+
+if (NOT TARGET _FreeRTOS_kernel_inclusion_marker)
+    add_library(_FreeRTOS_kernel_inclusion_marker INTERFACE)
+
+    # Pull in PICO SDK (must be before project)
+    include(pico_sdk_import.cmake)
+    if (PICO_SDK_VERSION_STRING VERSION_LESS "1.2.0")
+        message(FATAL_ERROR "Require at least Raspberry Pi Pico SDK version 1.2.0")
+    endif()
+
+    if (NOT FREERTOS_KERNEL_PATH)
+        get_filename_component(FREERTOS_KERNEL_PATH ${CMAKE_CURRENT_LIST_DIR}/../../../.. REALPATH)
+    endif ()
+
+    message(DEBUG "FREERTOS_KERNEL_PATH is ${FREERTOS_KERNEL_PATH}")
+    project(FreeRTOS-Kernel C CXX)
+
+    set(CMAKE_C_STANDARD 11)
+    set(CMAKE_CXX_STANDARD 17)
+
+    pico_is_top_level_project(FREERTOS_KERNEL_TOP_LEVEL_PROJECT)
+
+    # if the SDK has already been initialized, then just add our libraries now - this allows
+    # this FreeRTOS port to just be added as a sub-directory or include within another project, rather than
+    # having to include it at the top level before pico_sdk_init()
+    if (TARGET _pico_sdk_inclusion_marker)
+        if (PICO_SDK_VERSION_STRING VERSION_LESS "1.3.2")
+            message(FATAL_ERROR "Require at least Raspberry Pi Pico SDK version 1.3.2 to include FreeRTOS after pico_sdk_init()")
+        endif()
+        include(${CMAKE_CURRENT_LIST_DIR}/library.cmake)
+    else()
+        # The real work gets done in library.cmake which is called at the end of pico_sdk_init
+        list(APPEND PICO_SDK_POST_LIST_FILES ${CMAKE_CURRENT_LIST_DIR}/library.cmake)
+        if (PICO_SDK_VERSION_STRING VERSION_LESS "1.3.2")
+            # We need to inject the following header file into ALL SDK files (which we do via the config header)
+            list(APPEND PICO_CONFIG_HEADER_FILES ${CMAKE_CURRENT_LIST_DIR}/include/freertos_sdk_config.h)
+        endif()
+
+        if (FREERTOS_KERNEL_TOP_LEVEL_PROJECT)
+            message("FreeRTOS: initialize SDK since we're the top-level")
+            # Initialize the SDK
+            pico_sdk_init()
+        else()
+            set(FREERTOS_KERNEL_PATH ${FREERTOS_KERNEL_PATH} PARENT_SCOPE)
+            set(PICO_CONFIG_HEADER_FILES ${PICO_CONFIG_HEADER_FILES} PARENT_SCOPE)
+            set(PICO_SDK_POST_LIST_FILES ${PICO_SDK_POST_LIST_FILES} PARENT_SCOPE)
+        endif()
+    endif()
+endif()
+

kernel/FreeRTOS/Source/portable/ThirdParty/GCC/RP2040/FreeRTOS_Kernel_import.cmake

@@ -0,0 +1,61 @@
+# This is a copy of <FREERTOS_KERNEL_PATH>/portable/ThirdParty/GCC/RP2040/FREERTOS_KERNEL_import.cmake
+
+# This can be dropped into an external project to help locate the FreeRTOS kernel
+# It should be include()ed prior to project(). Alternatively this file may
+# or the CMakeLists.txt in this directory may be included or added via add_subdirectory
+# respectively.
+
+if (DEFINED ENV{FREERTOS_KERNEL_PATH} AND (NOT FREERTOS_KERNEL_PATH))
+    set(FREERTOS_KERNEL_PATH $ENV{FREERTOS_KERNEL_PATH})
+    message("Using FREERTOS_KERNEL_PATH from environment ('${FREERTOS_KERNEL_PATH}')")
+endif ()
+
+set(FREERTOS_KERNEL_RP2040_RELATIVE_PATH "portable/ThirdParty/GCC/RP2040")
+# undo the above
+set(FREERTOS_KERNEL_RP2040_BACK_PATH "../../../..")
+
+if (NOT FREERTOS_KERNEL_PATH)
+    # check if we are inside the FreeRTOS kernel tree (i.e. this file has been included directly)
+    get_filename_component(_ACTUAL_PATH ${CMAKE_CURRENT_LIST_DIR} REALPATH)
+    get_filename_component(_POSSIBLE_PATH ${CMAKE_CURRENT_LIST_DIR}/${FREERTOS_KERNEL_RP2040_BACK_PATH}/${FREERTOS_KERNEL_RP2040_RELATIVE_PATH} REALPATH)
+    if (_ACTUAL_PATH STREQUAL _POSSIBLE_PATH)
+        get_filename_component(FREERTOS_KERNEL_PATH ${CMAKE_CURRENT_LIST_DIR}/${FREERTOS_KERNEL_RP2040_BACK_PATH} REALPATH)
+    endif()
+    if (_ACTUAL_PATH STREQUAL _POSSIBLE_PATH)
+        get_filename_component(FREERTOS_KERNEL_PATH ${CMAKE_CURRENT_LIST_DIR}/${FREERTOS_KERNEL_RP2040_BACK_PATH} REALPATH)
+        message("Setting FREERTOS_KERNEL_PATH to ${FREERTOS_KERNEL_PATH} based on location of FreeRTOS-Kernel-import.cmake")
+    elseif (PICO_SDK_PATH AND EXISTS "${PICO_SDK_PATH}/../FreeRTOS-Kernel")
+        set(FREERTOS_KERNEL_PATH ${PICO_SDK_PATH}/../FreeRTOS-Kernel)
+        message("Defaulting FREERTOS_KERNEL_PATH as sibling of PICO_SDK_PATH: ${FREERTOS_KERNEL_PATH}")
+    endif()
+endif ()
+
+if (NOT FREERTOS_KERNEL_PATH)
+    foreach(POSSIBLE_SUFFIX Source FreeRTOS-Kernel FreeRTOS/Source)
+        # check if FreeRTOS-Kernel exists under directory that included us
+        set(SEARCH_ROOT ${CMAKE_CURRENT_SOURCE_DIR})
+        get_filename_component(_POSSIBLE_PATH ${SEARCH_ROOT}/${POSSIBLE_SUFFIX} REALPATH)
+        if (EXISTS ${_POSSIBLE_PATH}/${FREERTOS_KERNEL_RP2040_RELATIVE_PATH}/CMakeLists.txt)
+            get_filename_component(FREERTOS_KERNEL_PATH ${_POSSIBLE_PATH} REALPATH)
+            message("Setting FREERTOS_KERNEL_PATH to '${FREERTOS_KERNEL_PATH}' found relative to enclosing project")
+            break()
+        endif()
+    endforeach()
+endif()
+
+if (NOT FREERTOS_KERNEL_PATH)
+    message(FATAL_ERROR "FreeRTOS location was not specified. Please set FREERTOS_KERNEL_PATH.")
+endif()
+
+set(FREERTOS_KERNEL_PATH "${FREERTOS_KERNEL_PATH}" CACHE PATH "Path to the FreeRTOS Kernel")
+
+get_filename_component(FREERTOS_KERNEL_PATH "${FREERTOS_KERNEL_PATH}" REALPATH BASE_DIR "${CMAKE_BINARY_DIR}")
+if (NOT EXISTS ${FREERTOS_KERNEL_PATH})
+    message(FATAL_ERROR "Directory '${FREERTOS_KERNEL_PATH}' not found")
+endif()
+if (NOT EXISTS ${FREERTOS_KERNEL_PATH}/${FREERTOS_KERNEL_RP2040_RELATIVE_PATH}/CMakeLists.txt)
+    message(FATAL_ERROR "Directory '${FREERTOS_KERNEL_PATH}' does not contain an RP2040 port here: ${FREERTOS_KERNEL_RP2040_RELATIVE_PATH}")
+endif()
+set(FREERTOS_KERNEL_PATH ${FREERTOS_KERNEL_PATH} CACHE PATH "Path to the FreeRTOS_KERNEL" FORCE)
+
+add_subdirectory(${FREERTOS_KERNEL_PATH}/${FREERTOS_KERNEL_RP2040_RELATIVE_PATH} FREERTOS_KERNEL)

kernel/FreeRTOS/Source/portable/ThirdParty/GCC/RP2040/LICENSE.md

@@ -0,0 +1,23 @@
+BSD-3-Clause License
+
+Copyright (c) 2020-2021 Raspberry Pi (Trading) Ltd.
+
+Redistribution and use in source and binary forms, with or without modification, are permitted provided that the
+following conditions are met:
+
+1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following
+   disclaimer.
+
+2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
+   disclaimer in the documentation and/or other materials provided with the distribution.
+
+3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products
+   derived from this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

kernel/FreeRTOS/Source/portable/ThirdParty/GCC/RP2040/README.md

@@ -0,0 +1,42 @@
+## Overview
+
+This directory provides a FreeRTOS-Kernel port that can be used with the Raspberry Pi Pico SDK. It supports:
+
+ * Simple CMake INTERFACE libraries, to provide the FreeRTOS-Kernel and also the individual allocator types, without copying code into the user's project.
+ * Running the FreeRTOS-Kernel and tasks on either core 0 or core 1
+ * Use of SDK synchronization primitives (such as mutexes, semaphores, queues from pico_sync) between FreeRTOS tasks and code executing on the other core, or in IRQ handlers.
+
+Note that a FreeRTOS SMP version of this port is also available in the FreeRTOS-Kernel smp branch, which additionally supports utilizing both RP2040 CPU cores for FreeRTOS tasks simultaneously.
+
+## Using this port
+
+You can copy [FreeRTOS-Kernel-import.cmake](FreeRTOS-Kernel-import.cmake) into your project, and
+add the following in your `CMakeLists.txt`:
+
+```cmake
+include(FreeRTOS_Kernel_import.cmake)
+```
+
+This will locate the FreeRTOS kernel if it is a direct sub-module of your project, or if you provide the 
+`FREERTOS_KERNEL_PATH` variable in your environment or via `-DFREERTOS_KERNEL_PATH=/path/to/FreeRTOS-Kernel` on the CMake command line.
+
+**NOTE:** If you are using version 1.3.1 or older of the Raspberry Pi Pico SDK then this line must appear before the 
+`pico_sdk_init()` and will cause FreeRTOS to be included/required in all RP2040 targets in your project. After this SDK 
+version, you can include the FreeRTOS-Kernel support later in your CMake build (possibly in a subdirectory) and the 
+FreeRTOS-Kernel support will only apply to those targets which explicitly include FreeRTOS support.
+
+As an alternative to the `import` statement above, you can just add this directory directly via thw following (with 
+the same placement restrictions related to the Raspberry Pi Pico SDK version above): 
+
+```cmake
+add_subdirectory(path/to/this/directory FreeRTOS-Kernel)
+```
+
+
+## Advanced Configuration
+
+Some additional `config` options are defined [here](include/rp2040_config.h) which control some low level implementation details.
+
+## Known Limitations
+
+- Tickless idle has not currently been tested, and is likely non-functional

kernel/FreeRTOS/Source/portable/ThirdParty/GCC/RP2040/idle_task_static_memory.c

@@ -0,0 +1,52 @@
+/*
+ * FreeRTOS Kernel V10.5.1
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: MIT AND BSD-3-Clause
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ */
+
+#include "FreeRTOS.h"
+
+void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer,
+                                    StackType_t **ppxIdleTaskStackBuffer,
+                                    uint32_t *pulIdleTaskStackSize )
+{
+    /* If the buffers to be provided to the Idle task are declared inside this
+    function then they must be declared static - otherwise they will be allocated on
+    the stack and so not exists after this function exits. */
+    static StaticTask_t xIdleTaskTCB;
+    static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ];
+
+    /* Pass out a pointer to the StaticTask_t structure in which the Idle task's
+    state will be stored. */
+    *ppxIdleTaskTCBBuffer = &xIdleTaskTCB;
+
+    /* Pass out the array that will be used as the Idle task's stack. */
+    *ppxIdleTaskStackBuffer = uxIdleTaskStack;
+
+    /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer.
+    Note that, as the array is necessarily of type StackType_t,
+    configMINIMAL_STACK_SIZE is specified in words, not bytes. */
+    *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE;
+}

kernel/FreeRTOS/Source/portable/ThirdParty/GCC/RP2040/include/freertos_sdk_config.h

@@ -0,0 +1,73 @@
+/*
+ * FreeRTOS Kernel V10.5.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ */
+
+#ifndef FREERTOS_SDK_CONFIG_H
+#define FREERTOS_SDK_CONFIG_H
+
+#ifndef __ASSEMBLER__
+    #include "FreeRTOSConfig.h"
+    #include "rp2040_config.h"
+    #ifndef PICO_USE_MALLOC_MUTEX
+        // malloc needs to be made thread safe
+        #define PICO_USE_MALLOC_MUTEX 1
+    #endif /* PICO_USE_MALLOC_MUTEX */
+    #if ( configSUPPORT_PICO_SYNC_INTEROP == 1 )
+        // increase the amount of time it may reasonably take to wake us up
+        #ifndef PICO_TIME_SLEEP_OVERHEAD_ADJUST_US
+        #define PICO_TIME_SLEEP_OVERHEAD_ADJUST_US 150
+        #endif
+
+        #define lock_owner_id_t uint32_t
+        extern uint32_t ulPortLockGetCurrentOwnerId(void);
+        #define lock_get_caller_owner_id() ulPortLockGetCurrentOwnerId()
+        #define LOCK_INVALID_OWNER_ID ((uint32_t)-1)
+
+        struct lock_core;
+        #ifndef lock_internal_spin_unlock_with_wait
+        extern void vPortLockInternalSpinUnlockWithWait( struct lock_core *pxLock, uint32_t ulSave);
+        #define lock_internal_spin_unlock_with_wait(lock, save) vPortLockInternalSpinUnlockWithWait(lock, save)
+        #endif
+
+        #ifndef lock_internal_spin_unlock_with_notify
+        extern void vPortLockInternalSpinUnlockWithNotify( struct lock_core *pxLock, uint32_t save);
+        #define lock_internal_spin_unlock_with_notify(lock, save) vPortLockInternalSpinUnlockWithNotify(lock, save);
+        #endif
+
+        #ifndef lock_internal_spin_unlock_with_best_effort_wait_or_timeout
+        extern bool xPortLockInternalSpinUnlockWithBestEffortWaitOrTimeout( struct lock_core *pxLock, uint32_t ulSave, absolute_time_t uxUntil);
+        #define lock_internal_spin_unlock_with_best_effort_wait_or_timeout(lock, save, until) \
+            xPortLockInternalSpinUnlockWithBestEffortWaitOrTimeout(lock, save, until)
+        #endif
+    #endif /* configSUPPORT_PICO_SYNC_INTEROP */
+
+    #if ( configSUPPORT_PICO_TIME_INTEROP == 1 )
+        extern void xPortSyncInternalYieldUntilBefore(absolute_time_t t);
+        #define sync_internal_yield_until_before(t) xPortSyncInternalYieldUntilBefore(t)
+    #endif /* configSUPPORT_PICO_TIME_INTEROP */
+#endif /* __ASSEMBLER__ */
+#endif

kernel/FreeRTOS/Source/portable/ThirdParty/GCC/RP2040/include/portmacro.h

@@ -0,0 +1,151 @@
+/*
+ * FreeRTOS Kernel V10.5.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: MIT AND BSD-3-Clause
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef PORTMACRO_H
+    #define PORTMACRO_H
+
+    #ifdef __cplusplus
+        extern "C" {
+    #endif
+
+    #include "pico.h"
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+    #define portCHAR          char
+    #define portFLOAT         float
+    #define portDOUBLE        double
+    #define portLONG          long
+    #define portSHORT         short
+    #define portSTACK_TYPE    uint32_t
+    #define portBASE_TYPE     long
+
+    typedef portSTACK_TYPE    StackType_t;
+    typedef int32_t           BaseType_t;
+    typedef uint32_t          UBaseType_t;
+
+    #if ( configUSE_16_BIT_TICKS == 1 )
+        typedef uint16_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffff
+    #else
+        typedef uint32_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
+
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+        #define portTICK_TYPE_IS_ATOMIC    1
+    #endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+    #define portSTACK_GROWTH      ( -1 )
+    #define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+    #define portBYTE_ALIGNMENT    8
+    #define portDONT_DISCARD      __attribute__( ( used ) )
+    /* We have to use PICO_DIVIDER_DISABLE_INTERRUPTS as the source of truth rathern than our config,
+     * as our FreeRTOSConfig.h header cannot be included by ASM code - which is what this affects in the SDK */
+    #define portUSE_DIVIDER_SAVE_RESTORE !PICO_DIVIDER_DISABLE_INTERRUPTS
+    #if portUSE_DIVIDER_SAVE_RESTORE
+    #define portSTACK_LIMIT_PADDING 4
+    #endif
+
+/*-----------------------------------------------------------*/
+
+
+/* Scheduler utilities. */
+    extern void vPortYield( void );
+    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
+    #define portYIELD()                                 vPortYield()
+    #define portEND_SWITCHING_ISR( xSwitchRequired )    if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
+    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
+
+/*-----------------------------------------------------------*/
+
+/* Exception handlers */
+    #if (configUSE_DYNAMIC_EXCEPTION_HANDLERS == 0)
+        /* We only need to override the SDK's weak functions if we want to replace them at compile time */
+        #define vPortSVCHandler isr_svcall
+        #define xPortPendSVHandler isr_pendsv
+        #define xPortSysTickHandler isr_systick
+    #endif
+
+    #define portCHECK_IF_IN_ISR() ({ \
+        uint32_t ulIPSR;                                                  \
+       __asm volatile ("mrs %0, IPSR" : "=r" (ulIPSR)::);             \
+       ((uint8_t)ulIPSR)>0;})
+
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+    extern uint32_t ulSetInterruptMaskFromISR( void ) __attribute__( ( naked ) );
+    extern void vClearInterruptMaskFromISR( uint32_t ulMask )  __attribute__( ( naked ) );
+    #define portSET_INTERRUPT_MASK_FROM_ISR()         ulSetInterruptMaskFromISR()
+    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vClearInterruptMaskFromISR( x )
+
+    #define portDISABLE_INTERRUPTS()                  __asm volatile ( " cpsid i " ::: "memory" )
+
+    extern void vPortEnableInterrupts();
+    #define portENABLE_INTERRUPTS()                   vPortEnableInterrupts()
+
+    extern void vPortEnterCritical( void );
+    extern void vPortExitCritical( void );
+    #define portENTER_CRITICAL()                      vPortEnterCritical()
+    #define portEXIT_CRITICAL()                       vPortExitCritical()
+
+/*-----------------------------------------------------------*/
+
+/* Tickless idle/low power functionality. */
+    #ifndef portSUPPRESS_TICKS_AND_SLEEP
+        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )
+    #endif
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+
+    #define portNOP()
+
+    #define portMEMORY_BARRIER()    __asm volatile ( "" ::: "memory" )
+
+    #ifdef __cplusplus
+        }
+    #endif
+
+#endif /* PORTMACRO_H */

kernel/FreeRTOS/Source/portable/ThirdParty/GCC/RP2040/include/rp2040_config.h

@@ -0,0 +1,70 @@
+/*
+ * FreeRTOS Kernel V10.5.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: MIT AND BSD-3-Clause
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ */
+
+#ifndef RP2040_CONFIG_H
+#define RP2040_CONFIG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* configUSE_DYNAMIC_EXCEPTION_HANDLERS == 1 means set the exception handlers dynamically on cores
+ * that need them in case the user has set up distinct vector table offsets per core
+ */
+#ifndef configUSE_DYNAMIC_EXCEPTION_HANDLERS
+    #if defined( PICO_NO_RAM_VECTOR_TABLE ) && ( PICO_NO_RAM_VECTOR_TABLE == 1 )
+        #define configUSE_DYNAMIC_EXCEPTION_HANDLERS 0
+    #else
+        #define configUSE_DYNAMIC_EXCEPTION_HANDLERS 1
+    #endif
+#endif
+
+/* configSUPPORT_PICO_SYNC_INTEROP == 1 means that SDK pico_sync
+ * sem/mutex/queue etc. will work correctly when called from FreeRTOS tasks
+ */
+#ifndef configSUPPORT_PICO_SYNC_INTEROP
+    #if LIB_PICO_SYNC
+        #define configSUPPORT_PICO_SYNC_INTEROP 1
+    #endif
+#endif
+
+/* configSUPPORT_PICO_SYNC_INTEROP == 1 means that SDK pico_time
+ * sleep_ms/sleep_us/sleep_until will work correctly when called from FreeRTOS
+ * tasks, and will actually block at the FreeRTOS level
+ */
+#ifndef configSUPPORT_PICO_TIME_INTEROP
+    #if LIB_PICO_TIME
+        #define configSUPPORT_PICO_TIME_INTEROP 1
+    #endif
+#endif
+
+#ifdef __cplusplus
+};
+#endif
+
+#endif

kernel/FreeRTOS/Source/portable/ThirdParty/GCC/RP2040/library.cmake

@@ -0,0 +1,69 @@
+# Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+
+# Called after the Raspberry Pi Pico SDK has been initialized to add our libraries
+
+add_library(FreeRTOS-Kernel-Core INTERFACE)
+target_sources(FreeRTOS-Kernel-Core INTERFACE
+        ${FREERTOS_KERNEL_PATH}/croutine.c
+        ${FREERTOS_KERNEL_PATH}/event_groups.c
+        ${FREERTOS_KERNEL_PATH}/list.c
+        ${FREERTOS_KERNEL_PATH}/queue.c
+        ${FREERTOS_KERNEL_PATH}/stream_buffer.c
+        ${FREERTOS_KERNEL_PATH}/tasks.c
+        ${FREERTOS_KERNEL_PATH}/timers.c
+        )
+target_include_directories(FreeRTOS-Kernel-Core INTERFACE ${FREERTOS_KERNEL_PATH}/include)
+
+if (PICO_SDK_VERSION_STRING VERSION_GREATER_EQUAL "1.3.2")
+    target_compile_definitions(FreeRTOS-Kernel-Core INTERFACE
+            PICO_CONFIG_RTOS_ADAPTER_HEADER=${CMAKE_CURRENT_LIST_DIR}/include/freertos_sdk_config.h)
+endif()
+
+add_library(FreeRTOS-Kernel INTERFACE)
+target_sources(FreeRTOS-Kernel INTERFACE
+        ${CMAKE_CURRENT_LIST_DIR}/port.c
+)
+
+target_include_directories(FreeRTOS-Kernel INTERFACE
+        ${CMAKE_CURRENT_LIST_DIR}/include
+        ${FREERTOS_CONFIG_FILE_DIRECTORY})
+
+target_link_libraries(FreeRTOS-Kernel INTERFACE
+        FreeRTOS-Kernel-Core
+        pico_base_headers
+        hardware_exception)
+
+target_compile_definitions(FreeRTOS-Kernel INTERFACE
+        LIB_FREERTOS_KERNEL=1
+        FREERTOS_KERNEL_SMP=0
+)
+
+add_library(FreeRTOS-Kernel-Static INTERFACE)
+target_compile_definitions(FreeRTOS-Kernel-Static INTERFACE
+        configSUPPORT_STATIC_ALLOCATION=1
+        )
+
+target_sources(FreeRTOS-Kernel-Static INTERFACE ${CMAKE_CURRENT_LIST_DIR}/idle_task_static_memory.c)
+target_link_libraries(FreeRTOS-Kernel-Static INTERFACE FreeRTOS-Kernel)
+
+add_library(FreeRTOS-Kernel-Heap1 INTERFACE)
+target_sources(FreeRTOS-Kernel-Heap1 INTERFACE ${FREERTOS_KERNEL_PATH}/portable/MemMang/heap_1.c)
+target_link_libraries(FreeRTOS-Kernel-Heap1 INTERFACE FreeRTOS-Kernel)
+
+add_library(FreeRTOS-Kernel-Heap2 INTERFACE)
+target_sources(FreeRTOS-Kernel-Heap2 INTERFACE ${FREERTOS_KERNEL_PATH}/portable/MemMang/heap_2.c)
+target_link_libraries(FreeRTOS-Kernel-Heap2 INTERFACE FreeRTOS-Kernel)
+
+add_library(FreeRTOS-Kernel-Heap3 INTERFACE)
+target_sources(FreeRTOS-Kernel-Heap3 INTERFACE ${FREERTOS_KERNEL_PATH}/portable/MemMang/heap_3.c)
+target_link_libraries(FreeRTOS-Kernel-Heap3 INTERFACE FreeRTOS-Kernel)
+
+add_library(FreeRTOS-Kernel-Heap4 INTERFACE)
+target_sources(FreeRTOS-Kernel-Heap4 INTERFACE ${FREERTOS_KERNEL_PATH}/portable/MemMang/heap_4.c)
+target_link_libraries(FreeRTOS-Kernel-Heap4 INTERFACE FreeRTOS-Kernel)
+
+add_library(FreeRTOS-Kernel-Heap5 INTERFACE)
+target_sources(FreeRTOS-Kernel-Heap5 INTERFACE ${FREERTOS_KERNEL_PATH}/portable/MemMang/heap_5.c)
+target_link_libraries(FreeRTOS-Kernel-Heap5 INTERFACE FreeRTOS-Kernel)

kernel/FreeRTOS/Source/portable/ThirdParty/GCC/RP2040/pico_sdk_import.cmake

@@ -0,0 +1,66 @@
+# Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+
+# This is a copy of <PICO_SDK_PATH>/external/pico_sdk_import.cmake
+
+# This can be dropped into an external project to help locate this SDK
+# It should be include()ed prior to project()
+
+if (DEFINED ENV{PICO_SDK_PATH} AND (NOT PICO_SDK_PATH))
+    set(PICO_SDK_PATH $ENV{PICO_SDK_PATH})
+    message("Using PICO_SDK_PATH from environment ('${PICO_SDK_PATH}')")
+endif ()
+
+if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT} AND (NOT PICO_SDK_FETCH_FROM_GIT))
+    set(PICO_SDK_FETCH_FROM_GIT $ENV{PICO_SDK_FETCH_FROM_GIT})
+    message("Using PICO_SDK_FETCH_FROM_GIT from environment ('${PICO_SDK_FETCH_FROM_GIT}')")
+endif ()
+
+if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT_PATH} AND (NOT PICO_SDK_FETCH_FROM_GIT_PATH))
+    set(PICO_SDK_FETCH_FROM_GIT_PATH $ENV{PICO_SDK_FETCH_FROM_GIT_PATH})
+    message("Using PICO_SDK_FETCH_FROM_GIT_PATH from environment ('${PICO_SDK_FETCH_FROM_GIT_PATH}')")
+endif ()
+
+set(PICO_SDK_PATH "${PICO_SDK_PATH}" CACHE PATH "Path to the Raspberry Pi Pico SDK")
+set(PICO_SDK_FETCH_FROM_GIT "${PICO_SDK_FETCH_FROM_GIT}" CACHE BOOL "Set to ON to fetch copy of SDK from git if not otherwise locatable")
+set(PICO_SDK_FETCH_FROM_GIT_PATH "${PICO_SDK_FETCH_FROM_GIT_PATH}" CACHE FILEPATH "location to download SDK")
+
+if (NOT PICO_SDK_PATH)
+    if (PICO_SDK_FETCH_FROM_GIT)
+        include(FetchContent)
+        set(FETCHCONTENT_BASE_DIR_SAVE ${FETCHCONTENT_BASE_DIR})
+        if (PICO_SDK_FETCH_FROM_GIT_PATH)
+            get_filename_component(FETCHCONTENT_BASE_DIR "${PICO_SDK_FETCH_FROM_GIT_PATH}" REALPATH BASE_DIR "${CMAKE_SOURCE_DIR}")
+        endif ()
+        FetchContent_Declare(
+                pico_sdk
+                GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk
+                GIT_TAG master
+        )
+        if (NOT pico_sdk)
+            message("Downloading Raspberry Pi Pico SDK")
+            FetchContent_Populate(pico_sdk)
+            set(PICO_SDK_PATH ${pico_sdk_SOURCE_DIR})
+        endif ()
+        set(FETCHCONTENT_BASE_DIR ${FETCHCONTENT_BASE_DIR_SAVE})
+    else ()
+        message(FATAL_ERROR
+                "SDK location was not specified. Please set PICO_SDK_PATH or set PICO_SDK_FETCH_FROM_GIT to on to fetch from git."
+                )
+    endif ()
+endif ()
+
+get_filename_component(PICO_SDK_PATH "${PICO_SDK_PATH}" REALPATH BASE_DIR "${CMAKE_BINARY_DIR}")
+if (NOT EXISTS ${PICO_SDK_PATH})
+    message(FATAL_ERROR "Directory '${PICO_SDK_PATH}' not found")
+endif ()
+
+set(PICO_SDK_INIT_CMAKE_FILE ${PICO_SDK_PATH}/pico_sdk_init.cmake)
+if (NOT EXISTS ${PICO_SDK_INIT_CMAKE_FILE})
+    message(FATAL_ERROR "Directory '${PICO_SDK_PATH}' does not appear to contain the Raspberry Pi Pico SDK")
+endif ()
+
+set(PICO_SDK_PATH ${PICO_SDK_PATH} CACHE PATH "Path to the Raspberry Pi Pico SDK" FORCE)
+
+include(${PICO_SDK_INIT_CMAKE_FILE})

kernel/FreeRTOS/Source/portable/ThirdParty/GCC/RP2040/port.c

@@ -0,0 +1,876 @@
+/*
+ * FreeRTOS Kernel V10.5.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: MIT AND BSD-3-Clause
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/*----------------------------------------------------------------------
+* Implementation of functions defined in portable.h for the RP2040 port.
+*----------------------------------------------------------------------*/
+
+#include "FreeRTOS.h"
+#include "task.h"
+#include "rp2040_config.h"
+#include "hardware/clocks.h"
+#include "hardware/exception.h"
+
+/*
+ * LIB_PICO_MULTICORE == 1, if we are linked with pico_multicore (note that
+ * the non SMP FreeRTOS_Kernel is not linked with pico_multicore itself). We
+ * use this flag to determine if we need multi-core functionality.
+ */
+#if ( LIB_PICO_MULTICORE == 1)
+    #include "pico/multicore.h"
+#endif /* LIB_PICO_MULTICORE */
+
+/* Constants required to manipulate the NVIC. */
+#define portNVIC_SYSTICK_CTRL_REG             ( *( ( volatile uint32_t * ) 0xe000e010 ) )
+#define portNVIC_SYSTICK_LOAD_REG             ( *( ( volatile uint32_t * ) 0xe000e014 ) )
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG    ( *( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_INT_CTRL_REG                 ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_SHPR3_REG                    ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
+#define portNVIC_SYSTICK_CLK_BIT              ( 1UL << 2UL )
+#define portNVIC_SYSTICK_INT_BIT              ( 1UL << 1UL )
+#define portNVIC_SYSTICK_ENABLE_BIT           ( 1UL << 0UL )
+#define portNVIC_SYSTICK_COUNT_FLAG_BIT       ( 1UL << 16UL )
+#define portNVIC_PENDSVSET_BIT                ( 1UL << 28UL )
+#define portMIN_INTERRUPT_PRIORITY            ( 255UL )
+#define portNVIC_PENDSV_PRI                   ( portMIN_INTERRUPT_PRIORITY << 16UL )
+#define portNVIC_SYSTICK_PRI                  ( portMIN_INTERRUPT_PRIORITY << 24UL )
+
+/* Constants required to set up the initial stack. */
+#define portINITIAL_XPSR                      ( 0x01000000 )
+
+/* The systick is a 24-bit counter. */
+#define portMAX_24_BIT_NUMBER                 ( 0xffffffUL )
+
+/* A fiddle factor to estimate the number of SysTick counts that would have
+ * occurred while the SysTick counter is stopped during tickless idle
+ * calculations. */
+#ifndef portMISSED_COUNTS_FACTOR
+    #define portMISSED_COUNTS_FACTOR    ( 45UL )
+#endif
+
+/* Let the user override the pre-loading of the initial LR with the address of
+ * prvTaskExitError() in case it messes up unwinding of the stack in the
+ * debugger. */
+#ifdef configTASK_RETURN_ADDRESS
+    #define portTASK_RETURN_ADDRESS    configTASK_RETURN_ADDRESS
+#else
+    #define portTASK_RETURN_ADDRESS    prvTaskExitError
+#endif
+
+/*
+ * Setup the timer to generate the tick interrupts.  The implementation in this
+ * file is weak to allow application writers to change the timer used to
+ * generate the tick interrupt.
+ */
+void vPortSetupTimerInterrupt( void );
+
+/*
+ * Exception handlers.
+ */
+void xPortPendSVHandler( void ) __attribute__( ( naked ) );
+void xPortSysTickHandler( void );
+void vPortSVCHandler( void );
+
+/*
+ * Start first task is a separate function so it can be tested in isolation.
+ */
+static void vPortStartFirstTask( void ) __attribute__( ( naked ) );
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void );
+
+/*-----------------------------------------------------------*/
+
+/* Each task maintains its own interrupt status in the critical nesting
+ * variable. This is initialized to 0 to allow vPortEnter/ExitCritical
+ * to be called before the scheduler is started */
+static UBaseType_t uxCriticalNesting;
+
+/*-----------------------------------------------------------*/
+
+#if ( configSUPPORT_PICO_SYNC_INTEROP == 1 )
+    #include "pico/lock_core.h"
+    #include "hardware/irq.h"
+    #include "event_groups.h"
+    #if configSUPPORT_STATIC_ALLOCATION
+        static StaticEventGroup_t xStaticEventGroup;
+        #define pEventGroup (&xStaticEventGroup)
+    #endif /* configSUPPORT_STATIC_ALLOCATION */
+    static EventGroupHandle_t xEventGroup;
+    #if ( LIB_PICO_MULTICORE == 1 )
+        static EventBits_t uxCrossCoreEventBits;
+        static spin_lock_t * pxCrossCoreSpinLock;
+    #endif /* LIB_PICO_MULTICORE */
+
+    static spin_lock_t * pxYieldSpinLock;
+    static uint32_t ulYieldSpinLockSaveValue;
+#endif /* configSUPPORT_PICO_SYNC_INTEROP */
+
+/*
+ * The number of SysTick increments that make up one tick period.
+ */
+#if ( configUSE_TICKLESS_IDLE == 1 )
+    static uint32_t ulTimerCountsForOneTick = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * The maximum number of tick periods that can be suppressed is limited by the
+ * 24 bit resolution of the SysTick timer.
+ */
+#if ( configUSE_TICKLESS_IDLE == 1 )
+    static uint32_t xMaximumPossibleSuppressedTicks = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Compensate for the CPU cycles that pass while the SysTick is stopped (low
+ * power functionality only.
+ */
+#if ( configUSE_TICKLESS_IDLE == 1 )
+    static uint32_t ulStoppedTimerCompensation = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*-----------------------------------------------------------*/
+
+#define INVALID_LAUNCH_CORE_NUM 0xffu
+static uint8_t ucLaunchCoreNum = INVALID_LAUNCH_CORE_NUM;
+#define portIS_FREE_RTOS_CORE() ( ucLaunchCoreNum == get_core_num() )
+
+/*
+ * See header file for description.
+ */
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
+{
+    /* Simulate the stack frame as it would be created by a context switch
+     * interrupt. */
+    pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+    *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
+    pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */
+    *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0 */
+    pxTopOfStack -= 8;                                       /* R11..R4. */
+
+    return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+    /* A function that implements a task must not exit or attempt to return to
+     * its caller as there is nothing to return to.  If a task wants to exit it
+     * should instead call vTaskDelete( NULL ). */
+    panic_unsupported();
+}
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler( void )
+{
+    /* This function is no longer used, but retained for backward
+     * compatibility. */
+}
+/*-----------------------------------------------------------*/
+
+void vPortStartFirstTask( void )
+{
+    __asm volatile (
+        "   .syntax unified             \n"
+        "   ldr  r2, pxCurrentTCBConst1 \n"/* Obtain location of pxCurrentTCB. */
+        "   ldr  r3, [r2]               \n"
+        "   ldr  r0, [r3]               \n"/* The first item in pxCurrentTCB is the task top of stack. */
+        "   adds r0, #32                \n"/* Discard everything up to r0. */
+        "   msr  psp, r0                \n"/* This is now the new top of stack to use in the task. */
+        "   movs r0, #2                 \n"/* Switch to the psp stack. */
+        "   msr  CONTROL, r0            \n"
+        "   isb                         \n"
+        "   pop  {r0-r5}                \n"/* Pop the registers that are saved automatically. */
+        "   mov  lr, r5                 \n"/* lr is now in r5. */
+        "   pop  {r3}                   \n"/* Return address is now in r3. */
+        "   pop  {r2}                   \n"/* Pop and discard XPSR. */
+        "   cpsie i                     \n"/* The first task has its context and interrupts can be enabled. */
+        "   bx   r3                     \n"/* Finally, jump to the user defined task code. */
+	"   .align 4                       \n"
+	"pxCurrentTCBConst1: .word pxCurrentTCB\n"
+    );
+}
+/*-----------------------------------------------------------*/
+
+#if ( LIB_PICO_MULTICORE == 1 ) && ( configSUPPORT_PICO_SYNC_INTEROP == 1)
+    static void prvFIFOInterruptHandler()
+    {
+        /* We must remove the contents (which we don't care about)
+         * to clear the IRQ */
+        multicore_fifo_drain();
+        multicore_fifo_clear_irq();
+        BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+        uint32_t ulSave = spin_lock_blocking( pxCrossCoreSpinLock );
+        EventBits_t ulBits = uxCrossCoreEventBits;
+        uxCrossCoreEventBits &= ~ulBits;
+        spin_unlock( pxCrossCoreSpinLock, ulSave );
+        xEventGroupSetBitsFromISR( xEventGroup, ulBits, &xHigherPriorityTaskWoken );
+        portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+    }
+#endif
+
+/*
+ * See header file for description.
+ */
+BaseType_t xPortStartScheduler( void )
+{
+    /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+    portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
+    portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+
+    #if (configUSE_DYNAMIC_EXCEPTION_HANDLERS == 1)
+        exception_set_exclusive_handler( PENDSV_EXCEPTION, xPortPendSVHandler );
+        exception_set_exclusive_handler( SYSTICK_EXCEPTION, xPortSysTickHandler );
+        exception_set_exclusive_handler( SVCALL_EXCEPTION, vPortSVCHandler );
+    #endif
+
+    /* Start the timer that generates the tick ISR.  Interrupts are disabled
+     * here already. */
+    vPortSetupTimerInterrupt();
+
+    /* Initialise the critical nesting count ready for the first task. */
+    uxCriticalNesting = 0;
+
+    ucLaunchCoreNum = get_core_num();
+    #if (LIB_PICO_MULTICORE == 1)
+        #if ( configSUPPORT_PICO_SYNC_INTEROP == 1)
+            multicore_fifo_clear_irq();
+            multicore_fifo_drain();
+            uint32_t irq_num = 15 + get_core_num();
+            irq_set_priority( irq_num, portMIN_INTERRUPT_PRIORITY );
+            irq_set_exclusive_handler( irq_num, prvFIFOInterruptHandler );
+            irq_set_enabled( irq_num, 1 );
+        #endif
+    #endif
+
+    /* Start the first task. */
+    vPortStartFirstTask();
+
+    /* Should never get here as the tasks will now be executing!  Call the task
+     * exit error function to prevent compiler warnings about a static function
+     * not being called in the case that the application writer overrides this
+     * functionality by defining configTASK_RETURN_ADDRESS.  Call
+     * vTaskSwitchContext() so link time optimisation does not remove the
+     * symbol. */
+    vTaskSwitchContext();
+    prvTaskExitError();
+
+    /* Should not get here! */
+    return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+    /* Not implemented in ports where there is nothing to return to. */
+    panic_unsupported();
+}
+/*-----------------------------------------------------------*/
+
+void vPortYield( void )
+{
+    #if ( configSUPPORT_PICO_SYNC_INTEROP == 1 )
+        /* We are not in an ISR, and pxYieldSpinLock is always dealt with and
+         * cleared interrupts are re-enabled, so should be NULL */
+        configASSERT( pxYieldSpinLock == NULL );
+    #endif /* configSUPPORT_PICO_SYNC_INTEROP */
+
+    /* Set a PendSV to request a context switch. */
+    portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+
+    /* Barriers are normally not required but do ensure the code is completely
+     * within the specified behaviour for the architecture. */
+    __asm volatile ( "dsb" ::: "memory" );
+    __asm volatile ( "isb" );
+}
+
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+    portDISABLE_INTERRUPTS();
+    uxCriticalNesting++;
+    __asm volatile ( "dsb" ::: "memory" );
+    __asm volatile ( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+    configASSERT( uxCriticalNesting );
+    uxCriticalNesting--;
+    if( uxCriticalNesting == 0 )
+    {
+        portENABLE_INTERRUPTS();
+    }
+}
+
+void vPortEnableInterrupts() {
+    #if ( configSUPPORT_PICO_SYNC_INTEROP == 1 )
+        if( pxYieldSpinLock )
+        {
+            spin_unlock(pxYieldSpinLock, ulYieldSpinLockSaveValue);
+            pxYieldSpinLock = NULL;
+        }
+    #endif
+    __asm volatile ( " cpsie i " ::: "memory" );
+}
+
+/*-----------------------------------------------------------*/
+
+uint32_t ulSetInterruptMaskFromISR( void )
+{
+    __asm volatile (
+        " mrs r0, PRIMASK    \n"
+        " cpsid i            \n"
+        " bx lr                "
+        ::: "memory"
+        );
+}
+/*-----------------------------------------------------------*/
+
+void vClearInterruptMaskFromISR( __attribute__( ( unused ) ) uint32_t ulMask )
+{
+    __asm volatile (
+        " msr PRIMASK, r0    \n"
+        " bx lr                "
+        ::: "memory"
+        );
+}
+/*-----------------------------------------------------------*/
+
+void xPortPendSVHandler( void )
+{
+    /* This is a naked function. */
+
+    __asm volatile
+    (
+        "   .syntax unified                     \n"
+        "   mrs r0, psp                         \n"
+        "                                       \n"
+        "   ldr r3, pxCurrentTCBConst2          \n"/* Get the location of the current TCB. */
+        "   ldr r2, [r3]                        \n"
+        "                                       \n"
+        "   subs r0, r0, #32                    \n"/* Make space for the remaining low registers. */
+        "   str r0, [r2]                        \n"/* Save the new top of stack. */
+        "   stmia r0!, {r4-r7}                  \n"/* Store the low registers that are not saved automatically. */
+        "   mov r4, r8                          \n"/* Store the high registers. */
+        "   mov r5, r9                          \n"
+        "   mov r6, r10                         \n"
+        "   mov r7, r11                         \n"
+        "   stmia r0!, {r4-r7}                  \n"
+        #if portUSE_DIVIDER_SAVE_RESTORE
+            "   movs r2, #0xd                   \n"/* Store the divider state. */
+            "   lsls r2, #28                    \n"
+            /* We expect that the divider is ready at this point (which is
+             * necessary to safely save/restore), because:
+             * a) if we have not been interrupted since we entered this method,
+             *    then >8 cycles have clearly passed, so the divider is done
+             * b) if we were interrupted in the interim, then any "safe" - i.e.
+             *    does the right thing in an IRQ - use of the divider should
+             *    have waited for any in-process divide to complete, saved and
+             *    then fully restored the result, thus the result is ready in
+             *    that case too. */
+            "   ldr r4, [r2, #0x60]             \n"/* SIO_DIV_UDIVIDEND_OFFSET */
+            "   ldr r5, [r2, #0x64]             \n"/* SIO_DIV_UDIVISOR_OFFSET */
+            "   ldr r6, [r2, #0x74]             \n"/* SIO_DIV_REMAINDER_OFFSET */
+            "   ldr r7, [r2, #0x70]             \n"/* SIO_DIV_QUOTIENT_OFFSET */
+            /* We actually save the divider state in the 4 words below
+             * our recorded stack pointer, so as not to disrupt the stack
+             * frame expected by debuggers - this is addressed by
+             * portEXTRA_STACK_SIZE */
+            "   subs r0, r0, #48                \n"
+            "   stmia r0!, {r4-r7}              \n"
+        #endif /* portUSE_DIVIDER_SAVE_RESTORE */
+        "   push {r3, r14}                      \n"
+        "   cpsid i                             \n"
+        "   bl vTaskSwitchContext               \n"
+        "   cpsie i                             \n"
+        "   pop {r2, r3}                        \n"/* lr goes in r3. r2 now holds tcb pointer. */
+        "                                       \n"
+        "   ldr r1, [r2]                        \n"
+        "   ldr r0, [r1]                        \n"/* The first item in pxCurrentTCB is the task top of stack. */
+        "   adds r0, r0, #16                    \n"/* Move to the high registers. */
+        "   ldmia r0!, {r4-r7}                  \n"/* Pop the high registers. */
+        "   mov r8, r4                          \n"
+        "   mov r9, r5                          \n"
+        "   mov r10, r6                         \n"
+        "   mov r11, r7                         \n"
+        "                                       \n"
+        "   msr psp, r0                         \n"/* Remember the new top of stack for the task. */
+        "                                       \n"
+        #if portUSE_DIVIDER_SAVE_RESTORE
+        "   movs r2, #0xd                       \n"/* Pop the divider state. */
+        "   lsls r2, #28                        \n"
+        "   subs r0, r0, #48                    \n"/* Go back for the divider state */
+        "   ldmia r0!, {r4-r7}                  \n"/* Pop the divider state. */
+        /* Note always restore via SIO_DIV_UDIVI*, because we will overwrite the
+         * results stopping the calculation anyway, however the sign of results
+         * is adjusted by the h/w at read time based on whether the last started
+         * division was signed and the inputs' signs differed */
+        "   str r4, [r2, #0x60]                 \n"/* SIO_DIV_UDIVIDEND_OFFSET */
+        "   str r5, [r2, #0x64]                 \n"/* SIO_DIV_UDIVISOR_OFFSET */
+        "   str r6, [r2, #0x74]                 \n"/* SIO_DIV_REMAINDER_OFFSET */
+        "   str r7, [r2, #0x70]                 \n"/* SIO_DIV_QUOTIENT_OFFSET */
+        #else
+        "   subs r0, r0, #32                    \n"/* Go back for the low registers that are not automatically restored. */
+        #endif /* portUSE_DIVIDER_SAVE_RESTORE */
+        "   ldmia r0!, {r4-r7}                  \n"/* Pop low registers.  */
+        "                                       \n"
+        "   bx r3                               \n"
+	"   .align 4                            \n"
+	"pxCurrentTCBConst2: .word pxCurrentTCB \n"
+    );
+}
+/*-----------------------------------------------------------*/
+
+void xPortSysTickHandler( void )
+{
+    uint32_t ulPreviousMask;
+
+    ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+    {
+        /* Increment the RTOS tick. */
+        if( xTaskIncrementTick() != pdFALSE )
+        {
+            /* Pend a context switch. */
+            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+        }
+    }
+    portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the systick timer to generate the tick interrupts at the required
+ * frequency.
+ */
+__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )
+{
+    /* Calculate the constants required to configure the tick interrupt. */
+    #if ( configUSE_TICKLESS_IDLE == 1 )
+        {
+            ulTimerCountsForOneTick = ( clock_get_hz(clk_sys) / configTICK_RATE_HZ );
+            xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+            ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR;
+        }
+    #endif /* configUSE_TICKLESS_IDLE */
+
+    /* Stop and reset the SysTick. */
+    portNVIC_SYSTICK_CTRL_REG = 0UL;
+    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+    /* Configure SysTick to interrupt at the requested rate. */
+    portNVIC_SYSTICK_LOAD_REG = ( clock_get_hz( clk_sys ) / configTICK_RATE_HZ ) - 1UL;
+    portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TICKLESS_IDLE == 1 )
+
+    __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
+    {
+        uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
+        TickType_t xModifiableIdleTime;
+
+        /* Make sure the SysTick reload value does not overflow the counter. */
+        if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
+        {
+            xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
+        }
+
+        /* Stop the SysTick momentarily.  The time the SysTick is stopped for
+         * is accounted for as best it can be, but using the tickless mode will
+         * inevitably result in some tiny drift of the time maintained by the
+         * kernel with respect to calendar time. */
+        portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
+
+        /* Calculate the reload value required to wait xExpectedIdleTime
+         * tick periods.  -1 is used because this code will execute part way
+         * through one of the tick periods. */
+        ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
+
+        if( ulReloadValue > ulStoppedTimerCompensation )
+        {
+            ulReloadValue -= ulStoppedTimerCompensation;
+        }
+
+        /* Enter a critical section but don't use the taskENTER_CRITICAL()
+         * method as that will mask interrupts that should exit sleep mode. */
+        __asm volatile ( "cpsid i" ::: "memory" );
+        __asm volatile ( "dsb" );
+        __asm volatile ( "isb" );
+
+        /* If a context switch is pending or a task is waiting for the scheduler
+         * to be unsuspended then abandon the low power entry. */
+        if( eTaskConfirmSleepModeStatus() == eAbortSleep )
+        {
+            /* Restart from whatever is left in the count register to complete
+             * this tick period. */
+            portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+            /* Restart SysTick. */
+            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+            /* Reset the reload register to the value required for normal tick
+             * periods. */
+            portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+            /* Re-enable interrupts - see comments above the cpsid instruction()
+             * above. */
+            __asm volatile ( "cpsie i" ::: "memory" );
+        }
+        else
+        {
+            /* Set the new reload value. */
+            portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
+
+            /* Clear the SysTick count flag and set the count value back to
+             * zero. */
+            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+            /* Restart SysTick. */
+            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+            /* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can
+             * set its parameter to 0 to indicate that its implementation contains
+             * its own wait for interrupt or wait for event instruction, and so wfi
+             * should not be executed again.  However, the original expected idle
+             * time variable must remain unmodified, so a copy is taken. */
+            xModifiableIdleTime = xExpectedIdleTime;
+            configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
+
+            if( xModifiableIdleTime > 0 )
+            {
+                __asm volatile ( "dsb" ::: "memory" );
+                __asm volatile ( "wfi" );
+                __asm volatile ( "isb" );
+            }
+
+            configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
+
+            /* Re-enable interrupts to allow the interrupt that brought the MCU
+             * out of sleep mode to execute immediately.  see comments above
+             * __disable_interrupt() call above. */
+            __asm volatile ( "cpsie i" ::: "memory" );
+            __asm volatile ( "dsb" );
+            __asm volatile ( "isb" );
+
+            /* Disable interrupts again because the clock is about to be stopped
+             * and interrupts that execute while the clock is stopped will increase
+             * any slippage between the time maintained by the RTOS and calendar
+             * time. */
+            __asm volatile ( "cpsid i" ::: "memory" );
+            __asm volatile ( "dsb" );
+            __asm volatile ( "isb" );
+
+            /* Disable the SysTick clock without reading the
+             * portNVIC_SYSTICK_CTRL_REG register to ensure the
+             * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again,
+             * the time the SysTick is stopped for is accounted for as best it can
+             * be, but using the tickless mode will inevitably result in some tiny
+             * drift of the time maintained by the kernel with respect to calendar
+             * time*/
+            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
+
+            /* Determine if the SysTick clock has already counted to zero and
+             * been set back to the current reload value (the reload back being
+             * correct for the entire expected idle time) or if the SysTick is yet
+             * to count to zero (in which case an interrupt other than the SysTick
+             * must have brought the system out of sleep mode). */
+            if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+            {
+                uint32_t ulCalculatedLoadValue;
+
+                /* The tick interrupt is already pending, and the SysTick count
+                 * reloaded with ulReloadValue.  Reset the
+                 * portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
+                 * period. */
+                ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
+
+                /* Don't allow a tiny value, or values that have somehow
+                 * underflowed because the post sleep hook did something
+                 * that took too long. */
+                if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
+                {
+                    ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
+                }
+
+                portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
+
+                /* As the pending tick will be processed as soon as this
+                 * function exits, the tick value maintained by the tick is stepped
+                 * forward by one less than the time spent waiting. */
+                ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
+            }
+            else
+            {
+                /* Something other than the tick interrupt ended the sleep.
+                 * Work out how long the sleep lasted rounded to complete tick
+                 * periods (not the ulReload value which accounted for part
+                 * ticks). */
+                ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+                /* How many complete tick periods passed while the processor
+                 * was waiting? */
+                ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
+
+                /* The reload value is set to whatever fraction of a single tick
+                 * period remains. */
+                portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
+            }
+
+            /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
+             * again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
+             * value. */
+            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+            vTaskStepTick( ulCompleteTickPeriods );
+            portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+            /* Exit with interrupts enabled. */
+            __asm volatile ( "cpsie i" ::: "memory" );
+        }
+    }
+
+#endif /* configUSE_TICKLESS_IDLE */
+
+#if ( configSUPPORT_PICO_SYNC_INTEROP == 1 ) || ( configSUPPORT_PICO_TIME_INTEROP == 1 )
+    static TickType_t prvGetTicksToWaitBefore( absolute_time_t t )
+    {
+        int64_t xDelay = absolute_time_diff_us(get_absolute_time(), t);
+        const uint32_t ulTickPeriod = 1000000 / configTICK_RATE_HZ;
+        xDelay -= ulTickPeriod;
+        if( xDelay >= ulTickPeriod )
+        {
+            return xDelay / ulTickPeriod;
+        }
+        return 0;
+    }
+#endif
+
+#if ( configSUPPORT_PICO_SYNC_INTEROP == 1 )
+    uint32_t ulPortLockGetCurrentOwnerId()
+    {
+        if( portIS_FREE_RTOS_CORE())
+        {
+            uint32_t exception = __get_current_exception();
+            if( !exception )
+            {
+                return ( uintptr_t ) xTaskGetCurrentTaskHandle();
+            }
+            /* Note: since ROM as at 0x00000000, these can't be confused with
+             * valid task handles (pointers) in RAM */
+            /* We make all exception handler/core combinations distinct owners */
+            return get_core_num() + exception * 2;
+        }
+        /* Note: since ROM as at 0x00000000, this can't be confused with
+         * valid task handles (pointers) in RAM */
+        return get_core_num();
+    }
+
+    static inline EventBits_t prvGetEventGroupBit( spin_lock_t * spinLock )
+    {
+        uint32_t ulBit;
+        #if ( configUSE_16_BIT_TICKS == 1 )
+            ulBit = 1u << (spin_lock_get_num(spinLock) & 0x7u);
+        #else
+            ulBit = 1u << spin_lock_get_num(spinLock);
+            /* reduce to range 0-24 */
+            ulBit |= ulBit << 8u;
+            ulBit >>= 8u;
+        #endif /* configUSE_16_BIT_TICKS */
+        return ( EventBits_t ) ulBit;
+    }
+
+    static inline EventBits_t prvGetAllEventGroupBits()
+    {
+        #if ( configUSE_16_BIT_TICKS == 1 )
+            return (EventBits_t) 0xffu;
+        #else
+            return ( EventBits_t ) 0xffffffu;
+        #endif /* configUSE_16_BIT_TICKS */
+    }
+
+    void vPortLockInternalSpinUnlockWithWait( struct lock_core * pxLock, uint32_t ulSave )
+    {
+        configASSERT( !portCHECK_IF_IN_ISR() );
+        if( !portIS_FREE_RTOS_CORE() )
+        {
+            spin_unlock(pxLock->spin_lock, ulSave );
+            __wfe();
+        }
+        else
+        {
+            configASSERT( pxYieldSpinLock == NULL );
+
+            // we want to hold the lock until the event bits have been set; since interrupts are currently disabled
+            // by the spinlock, we can defer until portENABLE_INTERRUPTS is called which is always called when
+            // the scheduler is unlocked during this call
+            configASSERT(pxLock->spin_lock);
+            pxYieldSpinLock = pxLock->spin_lock;
+            ulYieldSpinLockSaveValue = ulSave;
+            xEventGroupWaitBits( xEventGroup, prvGetEventGroupBit(pxLock->spin_lock),
+                                 pdTRUE, pdFALSE, portMAX_DELAY);
+        }
+    }
+
+    void vPortLockInternalSpinUnlockWithNotify( struct lock_core *pxLock, uint32_t ulSave ) {
+        EventBits_t uxBits = prvGetEventGroupBit(pxLock->spin_lock );
+        if (portIS_FREE_RTOS_CORE()) {
+            #if LIB_PICO_MULTICORE
+                /* signal an event in case a regular core is waiting */
+                __sev();
+            #endif
+            spin_unlock(pxLock->spin_lock, ulSave );
+            if( !portCHECK_IF_IN_ISR() )
+            {
+                xEventGroupSetBits( xEventGroup, uxBits );
+            }
+            else
+            {
+                BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+                xEventGroupSetBitsFromISR( xEventGroup, uxBits, &xHigherPriorityTaskWoken );
+                portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+            }
+        }
+        else
+        {
+            __sev();
+            #if ( LIB_PICO_MULTICORE == 1)
+                /* We could sent the bits across the FIFO which would have required us to block here if the FIFO was full,
+                 * or we could have just set all bits on the other side, however it seems reasonable instead to take
+                 * the hit of another spin lock to protect an accurate bit set. */
+                if( pxCrossCoreSpinLock != pxLock->spin_lock )
+                {
+                    spin_lock_unsafe_blocking(pxCrossCoreSpinLock);
+                    uxCrossCoreEventBits |= uxBits;
+                    spin_unlock_unsafe(pxCrossCoreSpinLock);
+                }
+                else
+                {
+                    uxCrossCoreEventBits |= uxBits;
+                }
+                /* This causes fifo irq on the other (FreeRTOS) core which will do the set the event bits */
+                sio_hw->fifo_wr = 0;
+            #endif /* LIB_PICO_MULTICORE */
+            spin_unlock(pxLock->spin_lock, ulSave);
+        }
+    }
+
+    bool xPortLockInternalSpinUnlockWithBestEffortWaitOrTimeout( struct lock_core * pxLock, uint32_t ulSave, absolute_time_t uxUntil )
+    {
+        configASSERT( !portCHECK_IF_IN_ISR() );
+        // note no need to check LIB_PICO_MULTICORE, as this is always returns true if that is not defined
+        if( !portIS_FREE_RTOS_CORE() )
+        {
+            spin_unlock(pxLock->spin_lock, ulSave);
+            return best_effort_wfe_or_timeout(uxUntil);
+        }
+        else
+        {
+            configASSERT( pxYieldSpinLock == NULL );
+
+            TickType_t uxTicksToWait = prvGetTicksToWaitBefore( uxUntil );
+            if( uxTicksToWait )
+            {
+                /* We want to hold the lock until the event bits have been set; since interrupts are currently disabled
+                 * by the spinlock, we can defer until portENABLE_INTERRUPTS is called which is always called when
+                 * the scheduler is unlocked during this call */
+                configASSERT(pxLock->spin_lock);
+                pxYieldSpinLock = pxLock->spin_lock;
+                ulYieldSpinLockSaveValue = ulSave;
+                xEventGroupWaitBits( xEventGroup,
+                                     prvGetEventGroupBit(pxLock->spin_lock), pdTRUE,
+                                     pdFALSE, uxTicksToWait );
+                /* sanity check that interrupts were disabled, then re-enabled during the call, which will have
+                 * taken care of the yield */
+                configASSERT( pxYieldSpinLock == NULL );
+            }
+            else
+            {
+                spin_unlock( pxLock->spin_lock, ulSave );
+            }
+            if ( time_reached( uxUntil ) )
+            {
+                return true;
+            }
+            else
+            {
+                /* We do not want to hog the core */
+                portYIELD();
+                /* We aren't sure if we've reached the timeout yet; the caller will check */
+                return false;
+            }
+        }
+    }
+
+    #if ( configSUPPORT_PICO_SYNC_INTEROP == 1)
+        /* runs before main */
+        static void __attribute__((constructor)) prvRuntimeInitializer( void )
+        {
+            /* This must be done even before the scheduler is started, as the spin lock
+             * is used by the overrides of the SDK wait/notify primitives */
+            #if ( LIB_PICO_MULTICORE == 1 )
+                pxCrossCoreSpinLock = spin_lock_instance( next_striped_spin_lock_num() );
+            #endif /* portRUNNING_ON_BOTH_CORES */
+
+            /* The event group is not used prior to scheduler init, but is initialized
+             * here to since it logically belongs with the spin lock */
+            #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+                xEventGroup = xEventGroupCreateStatic(&xStaticEventGroup);
+            #else
+                /* Note that it is slightly dubious calling this here before the scheduler is initialized,
+                 * however the only thing it touches is the allocator which then calls vPortEnterCritical
+                 * and vPortExitCritical, and allocating here saves us checking the one time initialized variable in
+                 * some rather critical code paths */
+                xEventGroup = xEventGroupCreate();
+            #endif /* configSUPPORT_STATIC_ALLOCATION */
+        }
+    #endif
+#endif /* configSUPPORT_PICO_SYNC_INTEROP */
+
+#if ( configSUPPORT_PICO_TIME_INTEROP == 1 )
+    void xPortSyncInternalYieldUntilBefore( absolute_time_t t )
+    {
+        TickType_t uxTicksToWait = prvGetTicksToWaitBefore(t);
+        if( uxTicksToWait )
+        {
+            vTaskDelay(uxTicksToWait);
+        }
+    }
+#endif /* configSUPPORT_PICO_TIME_INTEROP */

kernel/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/FreeRTOS-openocd.c

@@ -0,0 +1,27 @@
+/*
+ * Since at least FreeRTOS V7.5.3 uxTopUsedPriority is no longer
+ * present in the kernel, so it has to be supplied by other means for
+ * OpenOCD's threads awareness.
+ *
+ * Add this file to your project, and, if you're using --gc-sections,
+ * ``--undefined=uxTopUsedPriority'' (or
+ * ``-Wl,--undefined=uxTopUsedPriority'' when using gcc for final
+ * linking) to your LDFLAGS; same with all the other symbols you need.
+ */
+
+#include "FreeRTOS.h"
+#include "esp_attr.h"
+#include "sdkconfig.h"
+
+#ifdef __GNUC__
+    #define USED    __attribute__( ( used ) )
+#else
+    #define USED
+#endif
+
+/* 
+ * This file is no longer needed as AFTER FreeRTOS V10.14.1 OpenOCD is fixed in the kernel.
+ * #ifdef CONFIG_ESP32_DEBUG_OCDAWARE
+ *   const int USED DRAM_ATTR uxTopUsedPriority = configMAX_PRIORITIES - 1;
+ * #endif 
+ */

kernel/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/FreeRTOSConfig_arch.h

@@ -0,0 +1,134 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Amazon.com, Inc. or its affiliates
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD
+ */
+/*
+ * FreeRTOS Kernel V10.5.1
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef FREERTOS_CONFIG_XTENSA_H
+#define FREERTOS_CONFIG_XTENSA_H
+
+#include "sdkconfig.h"
+
+/* enable use of optimized task selection by the scheduler */
+#if defined (CONFIG_FREERTOS_OPTIMIZED_SCHEDULER) && !defined(configUSE_PORT_OPTIMISED_TASK_SELECTION)
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION         1
+#endif
+
+#define XT_USE_THREAD_SAFE_CLIB                         0
+#undef XT_USE_SWPRI
+
+#if CONFIG_FREERTOS_CORETIMER_0
+#define XT_TIMER_INDEX                                  0
+#elif CONFIG_FREERTOS_CORETIMER_1
+#define XT_TIMER_INDEX                                  1
+#endif
+
+#ifndef __ASSEMBLER__
+/**
+ * This function is defined to provide a deprecation warning whenever
+ * XT_CLOCK_FREQ macro is used.
+ * Update the code to use esp_clk_cpu_freq function instead.
+ * @return current CPU clock frequency, in Hz
+ */
+int xt_clock_freq(void) __attribute__((deprecated));
+
+#define XT_CLOCK_FREQ   (xt_clock_freq())
+
+#endif // __ASSEMBLER__
+
+/* Required for configuration-dependent settings */
+#include <xtensa_config.h>
+
+/* configASSERT behaviour */
+#ifndef __ASSEMBLER__
+#include <assert.h>
+#include "esp_rom_sys.h"
+#if CONFIG_IDF_TARGET_ESP32
+#include "esp32/rom/ets_sys.h"  // will be removed in idf v5.0
+#elif CONFIG_IDF_TARGET_ESP32S2
+#include "esp32s2/rom/ets_sys.h"
+#elif CONFIG_IDF_TARGET_ESP32S3
+#include "esp32s3/rom/ets_sys.h"
+#endif
+#endif // __ASSEMBLER__
+
+// If CONFIG_FREERTOS_ASSERT_DISABLE is set then configASSERT is defined empty later in FreeRTOS.h and the macro
+// configASSERT_DEFINED remains unset (meaning some warnings are avoided)
+#ifdef configASSERT
+#undef configASSERT
+#if defined(CONFIG_FREERTOS_ASSERT_FAIL_PRINT_CONTINUE)
+#define configASSERT(a) if (unlikely(!(a))) {                           \
+        esp_rom_printf("%s:%d (%s)- assert failed!\n", __FILE__, __LINE__,  \
+                   __FUNCTION__);                                           \
+    }
+#elif defined(CONFIG_FREERTOS_ASSERT_FAIL_ABORT)
+#define configASSERT(a) assert(a)
+#endif
+#endif
+
+#if CONFIG_FREERTOS_ASSERT_ON_UNTESTED_FUNCTION
+#define UNTESTED_FUNCTION() { esp_rom_printf("Untested FreeRTOS function %s\r\n", __FUNCTION__); configASSERT(false); } while(0)
+#else
+#define UNTESTED_FUNCTION()
+#endif
+
+#define configXT_BOARD                                  1   /* Board mode */
+#define configXT_SIMULATOR                              0
+
+/* The maximum interrupt priority from which FreeRTOS.org API functions can
+   be called.  Only API functions that end in ...FromISR() can be used within
+   interrupts. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY	XCHAL_EXCM_LEVEL
+
+/* Stack alignment, architecture specifc. Must be a power of two. */
+#define configSTACK_ALIGNMENT                           16
+
+
+/* The Xtensa port uses a separate interrupt stack. Adjust the stack size
+ * to suit the needs of your specific application.
+ * Size needs to be aligned to the stack increment, since the location of
+ * the stack for the 2nd CPU will be calculated using configISR_STACK_SIZE.
+ */
+#ifndef configISR_STACK_SIZE
+#define configISR_STACK_SIZE                            ((CONFIG_FREERTOS_ISR_STACKSIZE + configSTACK_ALIGNMENT - 1) & (~(configSTACK_ALIGNMENT - 1)))
+#endif
+
+#ifndef __ASSEMBLER__
+#if CONFIG_APPTRACE_SV_ENABLE
+extern uint32_t port_switch_flag[];
+#define os_task_switch_is_pended(_cpu_) (port_switch_flag[_cpu_])
+#else
+#define os_task_switch_is_pended(_cpu_) (false)
+#endif
+#endif
+
+#endif // FREERTOS_CONFIG_XTENSA_H

kernel/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/port_systick.h

@@ -0,0 +1,20 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Set up the SysTick interrupt
+ */
+void vPortSetupTimer(void);
+
+#ifdef __cplusplus
+}
+#endif

kernel/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/portbenchmark.h

@@ -0,0 +1,52 @@
+/*
+ * SPDX-FileCopyrightText: 2015-2019 Cadence Design Systems, Inc.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD
+ */
+/*
+ * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * This utility helps benchmarking interrupt latency and context switches.
+ * In order to enable it, set configBENCHMARK to 1 in FreeRTOSConfig.h.
+ * You will also need to download the FreeRTOS_trace patch that contains
+ * portbenchmark.c and the complete version of portbenchmark.h
+ */
+
+#ifndef PORTBENCHMARK_H
+#define PORTBENCHMARK_H
+
+#if configBENCHMARK
+    #error "You need to download the FreeRTOS_trace patch that overwrites this file"
+#endif
+
+#define portbenchmarkINTERRUPT_DISABLE()
+#define portbenchmarkINTERRUPT_RESTORE( newstate )
+#define portbenchmarkIntLatency()
+#define portbenchmarkIntWait()
+#define portbenchmarkReset()
+#define portbenchmarkPrint()
+
+#endif /* PORTBENCHMARK */

kernel/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/portmacro.h

@@ -0,0 +1,570 @@
+/*
+ * SPDX-FileCopyrightText: 2017 Amazon.com, Inc. or its affiliates
+ * SPDX-FileCopyrightText: 2015-2019 Cadence Design Systems, Inc.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD
+ */
+/*
+ * FreeRTOS Kernel V10.5.1
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+    extern "C" {
+#endif
+/* *INDENT-ON* */
+
+#ifndef __ASSEMBLER__
+
+    #include <stdint.h>
+
+    #include <xtensa/hal.h>
+    #include <xtensa/config/core.h>
+    #include <xtensa/config/system.h> /* required for XSHAL_CLIB */
+    #include <xtensa/xtruntime.h>
+    #include "soc/spinlock.h"
+    #include "esp_timer.h"            /* required for FreeRTOS run time stats */
+    #include "esp_system.h"
+    #include "esp_idf_version.h"
+    #include "esp_heap_caps.h"
+
+    /* TODO: Resolve build warnings generated due to this header inclusion */
+    #include "hal/cpu_hal.h"
+
+    /* TODO: These includes are not directly used in this file. They are kept into to prevent a breaking change. Remove these. */
+    #include <limits.h>
+    #include <xtensa/xtensa_api.h>
+
+    #include "soc/cpu.h"
+    #include "soc/soc_memory_layout.h"
+#if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0))
+    #include "soc/compare_set.h"
+#endif /* ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0) */
+
+/*#include "xtensa_context.h" */
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+
+    #define portCHAR          int8_t
+    #define portFLOAT         float
+    #define portDOUBLE        double
+    #define portLONG          int32_t
+    #define portSHORT         int16_t
+    #define portSTACK_TYPE    uint8_t
+    #define portBASE_TYPE     int
+
+    typedef portSTACK_TYPE           StackType_t;
+    typedef portBASE_TYPE            BaseType_t;
+    typedef unsigned portBASE_TYPE   UBaseType_t;
+
+    #if ( configUSE_16_BIT_TICKS == 1 )
+        typedef uint16_t             TickType_t;
+        #define portMAX_DELAY    ( TickType_t ) 0xffff
+    #else
+        typedef uint32_t             TickType_t;
+        #define portMAX_DELAY    ( TickType_t ) 0xffffffffUL
+    #endif
+/*-----------------------------------------------------------*/
+
+/* portbenchmark */
+    #include "portbenchmark.h"
+
+    #include "sdkconfig.h"
+    #include "esp_attr.h"
+
+/* "mux" data structure (spinlock) */
+    typedef spinlock_t                          portMUX_TYPE;               /**< Spinlock type used by FreeRTOS critical sections */
+    #define portMUX_INITIALIZER_UNLOCKED        SPINLOCK_INITIALIZER        /**< Spinlock initializer */
+    #define portMUX_FREE_VAL                    SPINLOCK_FREE               /**< Spinlock is free. [refactor-todo] check if this is still required */
+    #define portMUX_NO_TIMEOUT                  SPINLOCK_WAIT_FOREVER       /**< When passed for 'timeout_cycles', spin forever if necessary. [refactor-todo] check if this is still required */
+    #define portMUX_TRY_LOCK                    SPINLOCK_NO_WAIT            /**< Try to acquire the spinlock a single time only. [refactor-todo] check if this is still required */
+    #define portMUX_INITIALIZE(mux)             spinlock_initialize(mux)    /*< Initialize a spinlock to its unlocked state */
+
+    #define portCRITICAL_NESTING_IN_TCB    1
+
+/*
+ * Modifications to portENTER_CRITICAL.
+ *
+ * For an introduction, see "Critical Sections & Disabling Interrupts" in docs/api-guides/freertos-smp.rst
+ *
+ * The original portENTER_CRITICAL only disabled the ISRs. This is enough for single-CPU operation: by
+ * disabling the interrupts, there is no task switch so no other tasks can meddle in the data, and because
+ * interrupts are disabled, ISRs can't corrupt data structures either.
+ *
+ * For multiprocessing, things get a bit more hairy. First of all, disabling the interrupts doesn't stop
+ * the tasks or ISRs on the other processors meddling with our CPU. For tasks, this is solved by adding
+ * a spinlock to the portENTER_CRITICAL macro. A task running on the other CPU accessing the same data will
+ * spinlock in the portENTER_CRITICAL code until the first CPU is done.
+ *
+ * For ISRs, we now also need muxes: while portENTER_CRITICAL disabling interrupts will stop ISRs on the same
+ * CPU from meddling with the data, it does not stop interrupts on the other cores from interfering with the
+ * data. For this, we also use a spinlock in the routines called by the ISR, but these spinlocks
+ * do not disable the interrupts (because they already are).
+ *
+ * This all assumes that interrupts are either entirely disabled or enabled. Interrupt priority levels
+ * will break this scheme.
+ *
+ * Remark: For the ESP32, portENTER_CRITICAL and portENTER_CRITICAL_ISR both alias vPortEnterCritical, meaning
+ * that either function can be called both from ISR as well as task context. This is not standard FreeRTOS
+ * behaviour; please keep this in mind if you need any compatibility with other FreeRTOS implementations.
+ */
+    void vPortCPUInitializeMutex( portMUX_TYPE * mux );
+    #ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
+        #error CONFIG_FREERTOS_PORTMUX_DEBUG not supported in Amazon FreeRTOS
+    #endif
+
+    void vTaskExitCritical();
+    void vTaskEnterCritical();
+    static inline void vPortConsumeSpinlockArg( int unused,
+                                                ... )
+    {
+    }
+
+/** @brief Acquire a portmux spinlock with a timeout
+ *
+ * @param mux Pointer to portmux to acquire.
+ * @param timeout_cycles Timeout to spin, in CPU cycles. Pass portMUX_NO_TIMEOUT to wait forever,
+ * portMUX_TRY_LOCK to try a single time to acquire the lock.
+ *
+ * @return true if mutex is successfully acquired, false on timeout.
+ */
+    bool vPortCPUAcquireMutexTimeout( portMUX_TYPE * mux,
+                                      int timeout_cycles );
+    void vPortCPUReleaseMutex( portMUX_TYPE * mux );
+
+    #define portENTER_CRITICAL( ... )        do { vTaskEnterCritical(); vPortConsumeSpinlockArg( 0, ## __VA_ARGS__ ); } while( 0 )
+    #define portEXIT_CRITICAL( ... )         do { vTaskExitCritical(); vPortConsumeSpinlockArg( 0, ## __VA_ARGS__ ); } while( 0 )
+
+
+    #define portENTER_CRITICAL_ISR( mux )    vPortCPUAcquireMutexTimeout( mux, portMUX_NO_TIMEOUT )
+    #define portEXIT_CRITICAL_ISR( mux )     vPortCPUReleaseMutex( mux )
+
+    #define portENTER_CRITICAL_SAFE( mux ) \
+    do {                                   \
+        if( xPortInIsrContext() ) {        \
+            portENTER_CRITICAL_ISR( mux ); \
+        }                                  \
+        else {                             \
+            portENTER_CRITICAL( mux );     \
+        }                                  \
+    } while( 0 )
+
+    #define portEXIT_CRITICAL_SAFE( mux ) \
+    do {                                  \
+        if( xPortInIsrContext() ) {       \
+            portEXIT_CRITICAL_ISR( mux ); \
+        }                                 \
+        else {                            \
+            portEXIT_CRITICAL( mux );     \
+        }                                 \
+    } while( 0 )
+
+    #define portASSERT_IF_IN_ISR()  vPortAssertIfInISR()
+    void vPortAssertIfInISR(void);
+
+/* Critical section management. NW-TODO: replace XTOS_SET_INTLEVEL with more efficient version, if any? */
+/* These cannot be nested. They should be used with a lot of care and cannot be called from interrupt level. */
+/* */
+/* Only applies to one CPU. See notes above & below for reasons not to use these. */
+    #define portDISABLE_INTERRUPTS()    do { XTOS_SET_INTLEVEL( XCHAL_EXCM_LEVEL ); portbenchmarkINTERRUPT_DISABLE(); } while( 0 )
+    #define portENABLE_INTERRUPTS()     do { portbenchmarkINTERRUPT_RESTORE( 0 ); XTOS_SET_INTLEVEL( 0 ); } while( 0 )
+
+/* Cleaner solution allows nested interrupts disabling and restoring via local registers or stack. */
+/* They can be called from interrupts too. */
+/* WARNING: Only applies to current CPU. See notes above. */
+    static inline UBaseType_t __attribute__( ( always_inline ) ) xPortSetInterruptMaskFromISR( void )
+    {
+        UBaseType_t prev_int_level = XTOS_SET_INTLEVEL( XCHAL_EXCM_LEVEL );
+        portbenchmarkINTERRUPT_DISABLE();
+        return prev_int_level;
+    }
+
+    static inline void __attribute__( ( always_inline ) ) vPortClearInterruptMaskFromISR( UBaseType_t prev_level )
+    {
+        portbenchmarkINTERRUPT_RESTORE( prev_level );
+        XTOS_RESTORE_JUST_INTLEVEL( prev_level );
+    }
+
+/* These FreeRTOS versions are similar to the nested versions above */
+    #define portSET_INTERRUPT_MASK_FROM_ISR()                  xPortSetInterruptMaskFromISR()
+    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( prev_level )    vPortClearInterruptMaskFromISR( prev_level )
+
+/*Because the ROM routines don't necessarily handle a stack in external RAM correctly, we force */
+/*the stack memory to always be internal. */
+    #define portTcbMemoryCaps (MALLOC_CAP_INTERNAL|MALLOC_CAP_8BIT)
+    #define portStackMemoryCaps (MALLOC_CAP_INTERNAL|MALLOC_CAP_8BIT)
+
+    #define pvPortMallocTcbMem(size) heap_caps_malloc(size, portTcbMemoryCaps)
+    #define pvPortMallocStackMem(size)  heap_caps_malloc(size, portStackMemoryCaps)
+
+/*xTaskCreateStatic uses these functions to check incoming memory. */
+    #define portVALID_TCB_MEM( ptr )          ( esp_ptr_internal( ptr ) && esp_ptr_byte_accessible( ptr ) )
+    #ifdef CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
+        #define portVALID_STACK_MEM( ptr )    esp_ptr_byte_accessible( ptr )
+    #else
+        #define portVALID_STACK_MEM( ptr )    ( esp_ptr_internal( ptr ) && esp_ptr_byte_accessible( ptr ) )
+    #endif
+
+/*
+ * Wrapper for the Xtensa compare-and-set instruction. This subroutine will atomically compare
+ * *addr to 'compare'. If *addr == compare, *addr is set to *set. *set is updated with the previous
+ * value of *addr (either 'compare' or some other value.)
+ *
+ * Warning: From the ISA docs: in some (unspecified) cases, the s32c1i instruction may return the
+ * *bitwise inverse* of the old mem if the mem wasn't written. This doesn't seem to happen on the
+ * ESP32 (portMUX assertions would fail).
+ */
+        static inline void uxPortCompareSet( volatile uint32_t * addr,
+                                             uint32_t compare,
+                                             uint32_t * set )
+        {
+            #if (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0))
+            __asm__ __volatile__ (
+                "WSR       %2,SCOMPARE1 \n"
+                "S32C1I     %0, %1, 0   \n"
+                : "=r" ( *set )
+                : "r" ( addr ), "r" ( compare ), "0" ( *set )
+                );
+            #else
+            #if ( XCHAL_HAVE_S32C1I > 0 )
+                __asm__ __volatile__ (
+                    "WSR 	    %2,SCOMPARE1 \n"
+                    "S32C1I     %0, %1, 0	 \n"
+                    : "=r" ( *set )
+                    : "r" ( addr ), "r" ( compare ), "0" ( *set )
+                    );
+            #else
+                /* No S32C1I, so do this by disabling and re-enabling interrupts (slower) */
+                uint32_t intlevel, old_value;
+                __asm__ __volatile__ ( "rsil %0, " XTSTR( XCHAL_EXCM_LEVEL ) "\n"
+                                       : "=r" ( intlevel ) );
+
+                old_value = *addr;
+
+                if( old_value == compare )
+                {
+                    *addr = *set;
+                }
+
+                __asm__ __volatile__ ( "memw \n"
+                                       "wsr %0, ps\n"
+                                       : : "r" ( intlevel ) );
+
+                *set = old_value;
+            #endif /* if ( XCHAL_HAVE_S32C1I > 0 ) */
+            #endif /* #if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0)) */
+        }
+
+        #if (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0))
+        void uxPortCompareSetExtram( volatile uint32_t * addr,
+                                     uint32_t compare,
+                                     uint32_t * set );
+        #else
+        static inline void uxPortCompareSetExtram(volatile uint32_t *addr, uint32_t compare, uint32_t *set)
+        {
+        #if defined(CONFIG_SPIRAM)
+            compare_and_set_extram(addr, compare, set);
+        #endif
+        }
+        #endif
+
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+    #define portSTACK_GROWTH      ( -1 )
+    #define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+    #define portBYTE_ALIGNMENT    4
+    #define portNOP()    XT_NOP()
+/*-----------------------------------------------------------*/
+
+/* Fine resolution time */
+    #define portGET_RUN_TIME_COUNTER_VALUE()    xthal_get_ccount()
+/*ccount or esp_timer are initialized elsewhere */
+    #define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS()
+
+    #ifdef CONFIG_FREERTOS_RUN_TIME_STATS_USING_ESP_TIMER
+/* Coarse resolution time (us) */
+        #define portALT_GET_RUN_TIME_COUNTER_VALUE( x )     do { x = ( uint32_t )esp_timer_get_time(); } while( 0 )
+    #endif
+
+
+
+/* Kernel utilities. */
+    void vPortYield( void );
+    void vPortEvaluateYieldFromISR( int argc, ... );
+    void _frxt_setup_switch( void );
+/* Macro to count number of arguments of a __VA_ARGS__ used to support portYIELD_FROM_ISR with,
+ * or without arguments. The macro counts only 0 or 1 arguments.
+ *
+ * In the future, we want to switch to C++20. We also want to become compatible with clang.
+ * Hence, we provide two versions of the following macros which are using variadic arguments.
+ * The first one is using the GNU extension ##__VA_ARGS__. The second one is using the C++20 feature __VA_OPT__(,).
+ * This allows users to compile their code with standard C++20 enabled instead of the GNU extension.
+ * Below C++20, we haven't found any good alternative to using ##__VA_ARGS__.
+ */
+    #if defined( __cplusplus ) && ( __cplusplus >  201703L )
+    #define portGET_ARGUMENT_COUNT(...) portGET_ARGUMENT_COUNT_INNER( 0 __VA_OPT__(,) __VA_ARGS__, 1 , 0 )
+    #else
+    #define portGET_ARGUMENT_COUNT(...) portGET_ARGUMENT_COUNT_INNER( 0, ##__VA_ARGS__, 1, 0 )
+    #endif
+    #define portGET_ARGUMENT_COUNT_INNER( zero, one, count, ... ) count
+
+    _Static_assert( portGET_ARGUMENT_COUNT() == 0, "portGET_ARGUMENT_COUNT() result does not match for 0 arguments" );
+    _Static_assert( portGET_ARGUMENT_COUNT( 1 ) == 1, "portGET_ARGUMENT_COUNT() result does not match for 1 argument" );
+
+    #define portYIELD()	vPortYield()
+
+/* The macro below could be used when passing a single argument, or without any argument,
+ * it was developed to support both usages of portYIELD inside of an ISR. Any other usage form
+ * might result in undesired behaviour
+ */
+    #if defined( __cplusplus ) && ( __cplusplus >  201703L )
+    #define portYIELD_FROM_ISR(...) vPortEvaluateYieldFromISR( portGET_ARGUMENT_COUNT( __VA_ARGS__ ) __VA_OPT__( , ) __VA_ARGS__ )
+    #else
+    #define portYIELD_FROM_ISR(...) vPortEvaluateYieldFromISR( portGET_ARGUMENT_COUNT( __VA_ARGS__ ), ##__VA_ARGS__ )
+    #endif
+
+    static inline BaseType_t xPortGetCoreID();
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+
+/* When coprocessors are defined, we to maintain a pointer to coprocessors area. */
+/* We currently use a hack: redefine field xMPU_SETTINGS in TCB block as a structure that can hold: */
+/* MPU wrappers, coprocessor area pointer, trace code structure, and more if needed. */
+/* The field is normally used for memory protection. FreeRTOS should create another general purpose field. */
+    typedef struct
+    {
+        #if XCHAL_CP_NUM > 0
+            volatile StackType_t * coproc_area; /* Pointer to coprocessor save area; MUST BE FIRST */
+        #endif
+
+        #if portUSING_MPU_WRAPPERS
+            /* Define here mpu_settings, which is port dependent */
+            int mpu_setting; /* Just a dummy example here; MPU not ported to Xtensa yet */
+        #endif
+
+        #if configUSE_TRACE_FACILITY_2
+            struct
+            {
+                /* Cf. porttraceStamp() */
+                int taskstamp;      /* Stamp from inside task to see where we are */
+                int taskstampcount; /* A counter usually incremented when we restart the task's loop */
+            } porttrace;
+        #endif
+    } xMPU_SETTINGS;
+
+/* Main hack to use MPU_wrappers even when no MPU is defined (warning: mpu_setting should not be accessed; otherwise move this above xMPU_SETTINGS) */
+    #if ( XCHAL_CP_NUM > 0 || configUSE_TRACE_FACILITY_2 ) && !portUSING_MPU_WRAPPERS /* If MPU wrappers not used, we still need to allocate coproc area */
+        #undef portUSING_MPU_WRAPPERS
+        #define portUSING_MPU_WRAPPERS    1                                           /* Enable it to allocate coproc area */
+        #define MPU_WRAPPERS_H                                                        /* Override mpu_wrapper.h to disable unwanted code */
+        #define PRIVILEGED_FUNCTION
+        #define PRIVILEGED_DATA
+    #endif
+
+    void vApplicationSleep( TickType_t xExpectedIdleTime );
+
+    #define portSUPPRESS_TICKS_AND_SLEEP( idleTime )    vApplicationSleep( idleTime )
+
+    void _xt_coproc_release( volatile void * coproc_sa_base );
+
+    /*-----------------------------------------------------------*/
+
+    #if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0))
+    /* Architecture specific optimisations. */
+
+    #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+    /* Check the configuration. */
+    #if( configMAX_PRIORITIES > 32 )
+        #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice.
+    #endif
+
+    /* Store/clear the ready priorities in a bit map. */
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+    /*-----------------------------------------------------------*/
+
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __builtin_clz( ( uxReadyPriorities ) ) )
+
+    #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+    #endif /* ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0) */
+
+    /*-----------------------------------------------------------*/
+
+/*
+ * Map to the memory management routines required for the port.
+ *
+ * Note that libc standard malloc/free are also available for
+ * non-FreeRTOS-specific code, and behave the same as
+ * pvPortMalloc()/vPortFree().
+ */
+    #define pvPortMalloc                       heap_caps_malloc_default
+    #define vPortFree                          heap_caps_free
+    #define xPortGetFreeHeapSize               esp_get_free_heap_size
+    #define xPortGetMinimumEverFreeHeapSize    esp_get_minimum_free_heap_size
+
+#if (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0))
+/*
+ * Send an interrupt to another core in order to make the task running
+ * on it yield for a higher-priority task.
+ */
+
+        void vPortYieldOtherCore( BaseType_t coreid ) PRIVILEGED_FUNCTION;
+
+#endif /* ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0) */
+
+/*
+ * Callback to set a watchpoint on the end of the stack. Called every context switch to change the stack
+ * watchpoint around.
+ */
+    void vPortSetStackWatchpoint( void * pxStackStart );
+
+/*
+ * Returns true if the current core is in ISR context; low prio ISR, med prio ISR or timer tick ISR. High prio ISRs
+ * aren't detected here, but they normally cannot call C code, so that should not be an issue anyway.
+ */
+    BaseType_t xPortInIsrContext();
+
+
+/*
+ * This function will be called in High prio ISRs. Returns true if the current core was in ISR context
+ * before calling into high prio ISR context.
+ */
+    BaseType_t xPortInterruptedFromISRContext();
+
+/*
+ * The structures and methods of manipulating the MPU are contained within the
+ * port layer.
+ *
+ * Fills the xMPUSettings structure with the memory region information
+ * contained in xRegions.
+ */
+    #if ( portUSING_MPU_WRAPPERS == 1 )
+        struct xMEMORY_REGION;
+        void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
+                                        const struct xMEMORY_REGION * const xRegions,
+                                        StackType_t * pxBottomOfStack,
+                                        uint32_t usStackDepth ) PRIVILEGED_FUNCTION;
+        void vPortReleaseTaskMPUSettings( xMPU_SETTINGS * xMPUSettings );
+    #endif
+
+/* Multi-core: get current core ID */
+    static inline BaseType_t IRAM_ATTR xPortGetCoreID()
+    {
+        return ( uint32_t )cpu_hal_get_core_id();
+    }
+
+/* Get tick rate per second */
+    uint32_t xPortGetTickRateHz( void );
+
+    static inline bool IRAM_ATTR xPortCanYield(void)
+    {
+        uint32_t ps_reg = 0;
+
+        //Get the current value of PS (processor status) register
+        RSR(PS, ps_reg);
+
+        /*
+        * intlevel = (ps_reg & 0xf);
+        * excm  = (ps_reg >> 4) & 0x1;
+        * CINTLEVEL is max(excm * EXCMLEVEL, INTLEVEL), where EXCMLEVEL is 3.
+        * However, just return true, only intlevel is zero.
+        */
+
+        return ((ps_reg & PS_INTLEVEL_MASK) == 0);
+    }
+
+/* porttrace */
+    #if configUSE_TRACE_FACILITY_2
+        #include "porttrace.h"
+    #endif
+
+/* configASSERT_2 if requested */
+    #if configASSERT_2
+        #include <stdio.h>
+        void exit( int );
+        #define configASSERT( x )    if( !( x ) ) { porttracePrint( -1 ); printf( "\nAssertion failed in %s:%d\n", __FILE__, __LINE__ ); exit( -1 ); }
+    #endif
+
+/* Barriers */
+    #define portMEMORY_BARRIER()    __asm volatile ( "" ::: "memory" )
+
+
+#endif // __ASSEMBLER__
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+    }
+#endif
+/* *INDENT-ON* */
+
+#endif /* PORTMACRO_H */

kernel/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/xt_asm_utils.h

@@ -0,0 +1,75 @@
+/*
+ * SPDX-FileCopyrightText: 2017, Intel Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD
+ */
+
+/* File adapted to use on IDF FreeRTOS component, extracted
+ * originally from zephyr RTOS code base:
+ * https://github.com/zephyrproject-rtos/zephyr/blob/dafd348/arch/xtensa/include/xtensa-asm2-s.h
+ */
+
+#ifndef __XT_ASM_UTILS_H
+#define __XT_ASM_UTILS_H
+
+/*
+ * SPILL_ALL_WINDOWS
+ *
+ * Spills all windowed registers (i.e. registers not visible as
+ * A0-A15) to their ABI-defined spill regions on the stack.
+ *
+ * Unlike the Xtensa HAL implementation, this code requires that the
+ * EXCM and WOE bit be enabled in PS, and relies on repeated hardware
+ * exception handling to do the register spills.  The trick is to do a
+ * noop write to the high registers, which the hardware will trap
+ * (into an overflow exception) in the case where those registers are
+ * already used by an existing call frame.  Then it rotates the window
+ * and repeats until all but the A0-A3 registers of the original frame
+ * are guaranteed to be spilled, eventually rotating back around into
+ * the original frame.  Advantages:
+ *
+ * - Vastly smaller code size
+ *
+ * - More easily maintained if changes are needed to window over/underflow
+ *   exception handling.
+ *
+ * - Requires no scratch registers to do its work, so can be used safely in any
+ *   context.
+ *
+ * - If the WOE bit is not enabled (for example, in code written for
+ *   the CALL0 ABI), this becomes a silent noop and operates compatbily.
+ *
+ * - Hilariously it's ACTUALLY FASTER than the HAL routine.  And not
+ *   just a little bit, it's MUCH faster.  With a mostly full register
+ *   file on an LX6 core (ESP-32) I'm measuring 145 cycles to spill
+ *   registers with this vs. 279 (!) to do it with
+ *   xthal_spill_windows().
+ */
+
+.macro SPILL_ALL_WINDOWS
+#if XCHAL_NUM_AREGS == 64
+	and a12, a12, a12
+	rotw 3
+	and a12, a12, a12
+	rotw 3
+	and a12, a12, a12
+	rotw 3
+	and a12, a12, a12
+	rotw 3
+	and a12, a12, a12
+	rotw 4
+#elif XCHAL_NUM_AREGS == 32
+	and a12, a12, a12
+	rotw 3
+	and a12, a12, a12
+	rotw 3
+	and a4, a4, a4
+	rotw 2
+#else
+#error Unrecognized XCHAL_NUM_AREGS
+#endif
+.endm
+
+#endif

kernel/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_api.h

@@ -0,0 +1,30 @@
+/*
+ * SPDX-FileCopyrightText: 2015-2019 Cadence Design Systems, Inc.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD
+ */
+/*
+ * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#include <xtensa/xtensa_api.h>

kernel/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_config.h

@@ -0,0 +1,154 @@
+/*
+ * SPDX-FileCopyrightText: 2015-2019 Cadence Design Systems, Inc.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD
+ */
+/*
+ * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*******************************************************************************
+*
+*  Configuration-specific information for Xtensa build. This file must be
+*  included in FreeRTOSConfig.h to properly set up the config-dependent
+*  parameters correctly.
+*
+*  NOTE: To enable thread-safe C library support, XT_USE_THREAD_SAFE_CLIB must
+*  be defined to be > 0 somewhere above or on the command line.
+*
+*******************************************************************************/
+
+#ifndef XTENSA_CONFIG_H
+    #define XTENSA_CONFIG_H
+
+    #ifdef __cplusplus
+        extern "C" {
+    #endif
+
+    #include <xtensa/hal.h>
+    #include <xtensa/config/core.h>
+    #include <xtensa/config/system.h> /* required for XSHAL_CLIB */
+
+    #include "xtensa_context.h"
+
+
+/*-----------------------------------------------------------------------------
+ *                                 STACK REQUIREMENTS
+ *
+ * This section defines the minimum stack size, and the extra space required to
+ * be allocated for saving coprocessor state and/or C library state information
+ * (if thread safety is enabled for the C library). The sizes are in bytes.
+ *
+ * Stack sizes for individual tasks should be derived from these minima based on
+ * the maximum call depth of the task and the maximum level of interrupt nesting.
+ * A minimum stack size is defined by XT_STACK_MIN_SIZE. This minimum is based
+ * on the requirement for a task that calls nothing else but can be interrupted.
+ * This assumes that interrupt handlers do not call more than a few levels deep.
+ * If this is not true, i.e. one or more interrupt handlers make deep calls then
+ * the minimum must be increased.
+ *
+ * If the Xtensa processor configuration includes coprocessors, then space is
+ * allocated to save the coprocessor state on the stack.
+ *
+ * If thread safety is enabled for the C runtime library, (XT_USE_THREAD_SAFE_CLIB
+ * is defined) then space is allocated to save the C library context in the TCB.
+ *
+ * Allocating insufficient stack space is a common source of hard-to-find errors.
+ * During development, it is best to enable the FreeRTOS stack checking features.
+ *
+ * Usage:
+ *
+ * XT_USE_THREAD_SAFE_CLIB -- Define this to a nonzero value to enable thread-safe
+ *                            use of the C library. This will require extra stack
+ *                            space to be allocated for tasks that use the C library
+ *                            reentrant functions. See below for more information.
+ *
+ * NOTE: The Xtensa toolchain supports multiple C libraries and not all of them
+ * support thread safety. Check your core configuration to see which C library
+ * was chosen for your system.
+ *
+ * XT_STACK_MIN_SIZE       -- The minimum stack size for any task. It is recommended
+ *                            that you do not use a stack smaller than this for any
+ *                            task. In case you want to use stacks smaller than this
+ *                            size, you must verify that the smaller size(s) will work
+ *                            under all operating conditions.
+ *
+ * XT_STACK_EXTRA          -- The amount of extra stack space to allocate for a task
+ *                            that does not make C library reentrant calls. Add this
+ *                            to the amount of stack space required by the task itself.
+ *
+ * XT_STACK_EXTRA_CLIB     -- The amount of space to allocate for C library state.
+ *
+ *  -----------------------------------------------------------------------------*/
+
+/* Extra space required for interrupt/exception hooks. */
+    #ifdef XT_INTEXC_HOOKS
+        #ifdef __XTENSA_CALL0_ABI__
+            #define STK_INTEXC_EXTRA     0x200
+        #else
+            #define STK_INTEXC_EXTRA     0x180
+        #endif
+    #else
+        #define STK_INTEXC_EXTRA         0
+    #endif
+
+    #define XT_CLIB_CONTEXT_AREA_SIZE    0
+
+/*------------------------------------------------------------------------------
+ *  Extra size -- interrupt frame plus coprocessor save area plus hook space.
+ *  NOTE: Make sure XT_INTEXC_HOOKS is undefined unless you really need the hooks.
+ *  ------------------------------------------------------------------------------*/
+    #ifdef __XTENSA_CALL0_ABI__
+        #define XT_XTRA_SIZE    ( XT_STK_FRMSZ + STK_INTEXC_EXTRA + 0x10 + XT_CP_SIZE )
+    #else
+        #define XT_XTRA_SIZE    ( XT_STK_FRMSZ + STK_INTEXC_EXTRA + 0x20 + XT_CP_SIZE )
+    #endif
+
+/*------------------------------------------------------------------------------
+ *  Space allocated for user code -- function calls and local variables.
+ *  NOTE: This number can be adjusted to suit your needs. You must verify that the
+ *  amount of space you reserve is adequate for the worst-case conditions in your
+ *  application.
+ *  NOTE: The windowed ABI requires more stack, since space has to be reserved
+ *  for spilling register windows.
+ *  ------------------------------------------------------------------------------*/
+    #ifdef __XTENSA_CALL0_ABI__
+        #define XT_USER_SIZE    0x200
+    #else
+        #define XT_USER_SIZE    0x400
+    #endif
+
+/* Minimum recommended stack size. */
+    #define XT_STACK_MIN_SIZE      ( ( XT_XTRA_SIZE + XT_USER_SIZE ) / sizeof( unsigned char ) )
+
+/* OS overhead with and without C library thread context. */
+    #define XT_STACK_EXTRA         ( XT_XTRA_SIZE )
+    #define XT_STACK_EXTRA_CLIB    ( XT_XTRA_SIZE + XT_CLIB_CONTEXT_AREA_SIZE )
+
+
+    #ifdef __cplusplus
+        }
+    #endif
+
+#endif /* XTENSA_CONFIG_H */

kernel/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_context.h

@@ -0,0 +1,30 @@
+/*
+ * SPDX-FileCopyrightText: 2015-2019 Cadence Design Systems, Inc.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD
+ */
+/*
+ * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#include <xtensa/xtensa_context.h>

kernel/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_rtos.h

@@ -0,0 +1,242 @@
+/*
+ * SPDX-FileCopyrightText: 2015-2019 Cadence Design Systems, Inc.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD
+ */
+/*
+ * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*******************************************************************************
+*
+*       RTOS-SPECIFIC INFORMATION FOR XTENSA RTOS ASSEMBLER SOURCES
+*                           (FreeRTOS Port)
+*
+*  This header is the primary glue between generic Xtensa RTOS support
+*  sources and a specific RTOS port for Xtensa.  It contains definitions
+*  and macros for use primarily by Xtensa assembly coded source files.
+*
+*  Macros in this header map callouts from generic Xtensa files to specific
+*  RTOS functions. It may also be included in C source files.
+*
+*  Xtensa RTOS ports support all RTOS-compatible configurations of the Xtensa
+*  architecture, using the Xtensa hardware abstraction layer (HAL) to deal
+*  with configuration specifics.
+*
+*  Should be included by all Xtensa generic and RTOS port-specific sources.
+*
+*******************************************************************************/
+
+#ifndef XTENSA_RTOS_H
+#define XTENSA_RTOS_H
+
+#ifdef __ASSEMBLER__
+    #include    <xtensa/coreasm.h>
+#else
+    #include    <xtensa/config/core.h>
+#endif
+
+#include    <xtensa/corebits.h>
+#include    <xtensa/config/system.h>
+#include    "sdkconfig.h"
+/*
+ * Include any RTOS specific definitions that are needed by this header.
+ */
+#include    "FreeRTOSConfig.h"
+
+/*
+ * Convert FreeRTOSConfig definitions to XTENSA definitions.
+ * However these can still be overridden from the command line.
+ */
+
+#ifndef XT_SIMULATOR
+    #if configXT_SIMULATOR
+        #define XT_SIMULATOR    1       /* Simulator mode */
+    #endif
+#endif
+
+#ifndef XT_BOARD
+    #if configXT_BOARD
+        #define XT_BOARD    1           /* Board mode */
+    #endif
+#endif
+
+#ifndef XT_TIMER_INDEX
+    #if defined configXT_TIMER_INDEX
+        #define XT_TIMER_INDEX    configXT_TIMER_INDEX     /* Index of hardware timer to be used */
+    #endif
+#endif
+
+#ifndef XT_INTEXC_HOOKS
+    #if configXT_INTEXC_HOOKS
+        #define XT_INTEXC_HOOKS    1    /* Enables exception hooks */
+    #endif
+#endif
+
+#if !defined( XT_SIMULATOR ) && !defined( XT_BOARD )
+    #error Either XT_SIMULATOR or XT_BOARD must be defined.
+#endif
+
+
+/*
+ * Name of RTOS (for messages).
+ */
+#define XT_RTOS_NAME    FreeRTOS
+
+/*
+ * Check some Xtensa configuration requirements and report error if not met.
+ * Error messages can be customize to the RTOS port.
+ */
+
+#if !XCHAL_HAVE_XEA2
+    #error "FreeRTOS/Xtensa requires XEA2 (exception architecture 2)."
+#endif
+
+
+/*******************************************************************************
+*
+*  RTOS CALLOUT MACROS MAPPED TO RTOS PORT-SPECIFIC FUNCTIONS.
+*
+*  Define callout macros used in generic Xtensa code to interact with the RTOS.
+*  The macros are simply the function names for use in calls from assembler code.
+*  Some of these functions may call back to generic functions in xtensa_context.h .
+*
+*******************************************************************************/
+
+/*
+ * Inform RTOS of entry into an interrupt handler that will affect it.
+ * Allows RTOS to manage switch to any system stack and count nesting level.
+ * Called after minimal context has been saved, with interrupts disabled.
+ * RTOS port can call0 _xt_context_save to save the rest of the context.
+ * May only be called from assembly code by the 'call0' instruction.
+ */
+/* void XT_RTOS_INT_ENTER(void) */
+#define XT_RTOS_INT_ENTER    _frxt_int_enter
+
+/*
+ * Inform RTOS of completion of an interrupt handler, and give control to
+ * RTOS to perform thread/task scheduling, switch back from any system stack
+ * and restore the context, and return to the exit dispatcher saved in the
+ * stack frame at XT_STK_EXIT. RTOS port can call0 _xt_context_restore
+ * to save the context saved in XT_RTOS_INT_ENTER via _xt_context_save,
+ * leaving only a minimal part of the context to be restored by the exit
+ * dispatcher. This function does not return to the place it was called from.
+ * May only be called from assembly code by the 'call0' instruction.
+ */
+/* void XT_RTOS_INT_EXIT(void) */
+#define XT_RTOS_INT_EXIT    _frxt_int_exit
+
+/*
+ * Inform RTOS of the occurrence of a tick timer interrupt.
+ * If RTOS has no tick timer, leave XT_RTOS_TIMER_INT undefined.
+ * May be coded in or called from C or assembly, per ABI conventions.
+ * RTOS may optionally define XT_TICK_PER_SEC in its own way (eg. macro).
+ */
+/* void XT_RTOS_TIMER_INT(void) */
+#ifdef CONFIG_FREERTOS_SYSTICK_USES_CCOUNT
+#define XT_RTOS_TIMER_INT   _frxt_timer_int
+#endif
+#define XT_TICK_PER_SEC      configTICK_RATE_HZ
+
+/*
+ * Return in a15 the base address of the co-processor state save area for the
+ * thread that triggered a co-processor exception, or 0 if no thread was running.
+ * The state save area is structured as defined in xtensa_context.h and has size
+ * XT_CP_SIZE. Co-processor instructions should only be used in thread code, never
+ * in interrupt handlers or the RTOS kernel. May only be called from assembly code
+ * and by the 'call0' instruction. A result of 0 indicates an unrecoverable error.
+ * The implementation may use only a2-4, a15 (all other regs must be preserved).
+ */
+/* void* XT_RTOS_CP_STATE(void) */
+#define XT_RTOS_CP_STATE    _frxt_task_coproc_state
+
+
+/*******************************************************************************
+*
+*  HOOKS TO DYNAMICALLY INSTALL INTERRUPT AND EXCEPTION HANDLERS PER LEVEL.
+*
+*  This Xtensa RTOS port provides hooks for dynamically installing exception
+*  and interrupt handlers to facilitate automated testing where each test
+*  case can install its own handler for user exceptions and each interrupt
+*  priority (level). This consists of an array of function pointers indexed
+*  by interrupt priority, with index 0 being the user exception handler hook.
+*  Each entry in the array is initially 0, and may be replaced by a function
+*  pointer of type XT_INTEXC_HOOK. A handler may be uninstalled by installing 0.
+*
+*  The handler for low and medium priority obeys ABI conventions so may be coded
+*  in C. For the exception handler, the cause is the contents of the EXCCAUSE
+*  reg, and the result is -1 if handled, else the cause (still needs handling).
+*  For interrupt handlers, the cause is a mask of pending enabled interrupts at
+*  that level, and the result is the same mask with the bits for the handled
+*  interrupts cleared (those not cleared still need handling). This allows a test
+*  case to either pre-handle or override the default handling for the exception
+*  or interrupt level (see xtensa_vectors.S).
+*
+*  High priority handlers (including NMI) must be coded in assembly, are always
+*  called by 'call0' regardless of ABI, must preserve all registers except a0,
+*  and must not use or modify the interrupted stack. The hook argument 'cause'
+*  is not passed and the result is ignored, so as not to burden the caller with
+*  saving and restoring a2 (it assumes only one interrupt per level - see the
+*  discussion in high priority interrupts in xtensa_vectors.S). The handler
+*  therefore should be coded to prototype 'void h(void)' even though it plugs
+*  into an array of handlers of prototype 'unsigned h(unsigned)'.
+*
+*  To enable interrupt/exception hooks, compile the RTOS with '-DXT_INTEXC_HOOKS'.
+*
+*******************************************************************************/
+
+#define XT_INTEXC_HOOK_NUM    ( 1 + XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI )
+
+#ifndef __ASSEMBLER__
+    typedef unsigned (* XT_INTEXC_HOOK)( unsigned cause );
+    extern volatile XT_INTEXC_HOOK _xt_intexc_hooks[ XT_INTEXC_HOOK_NUM ];
+#endif
+
+
+/*******************************************************************************
+*
+*  CONVENIENCE INCLUSIONS.
+*
+*  Ensures RTOS specific files need only include this one Xtensa-generic header.
+*  These headers are included last so they can use the RTOS definitions above.
+*
+*******************************************************************************/
+
+#include    "xtensa_context.h"
+
+#ifdef XT_RTOS_TIMER_INT
+    #include    "xtensa_timer.h"
+#endif
+
+
+/*******************************************************************************
+*
+*  Xtensa Port Version.
+*
+*******************************************************************************/
+
+#define XTENSA_PORT_VERSION           1.4 .2
+#define XTENSA_PORT_VERSION_STRING    "1.4.2"
+
+#endif /* XTENSA_RTOS_H */

kernel/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_timer.h

@@ -0,0 +1,167 @@
+/*
+ * SPDX-FileCopyrightText: 2015-2019 Cadence Design Systems, Inc.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD
+ */
+/*
+ * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*******************************************************************************
+*
+*       XTENSA INFORMATION FOR RTOS TICK TIMER AND CLOCK FREQUENCY
+*
+*  This header contains definitions and macros for use primarily by Xtensa
+*  RTOS assembly coded source files. It includes and uses the Xtensa hardware
+*  abstraction layer (HAL) to deal with config specifics. It may also be
+*  included in C source files.
+*
+*  User may edit to modify timer selection and to specify clock frequency and
+*  tick duration to match timer interrupt to the real-time tick duration.
+*
+*  If the RTOS has no timer interrupt, then there is no tick timer and the
+*  clock frequency is irrelevant, so all of these macros are left undefined
+*  and the Xtensa core configuration need not have a timer.
+*
+*******************************************************************************/
+
+#ifndef XTENSA_TIMER_H
+#define XTENSA_TIMER_H
+
+#ifdef __ASSEMBLER__
+    #include    <xtensa/coreasm.h>
+#endif
+
+#include    <xtensa/corebits.h>
+#include    <xtensa/config/system.h>
+
+#include    "xtensa_rtos.h" /* in case this wasn't included directly */
+
+#include    "FreeRTOSConfig.h"
+
+/*
+ * Select timer to use for periodic tick, and determine its interrupt number
+ * and priority. User may specify a timer by defining XT_TIMER_INDEX with -D,
+ * in which case its validity is checked (it must exist in this core and must
+ * not be on a high priority interrupt - an error will be reported in invalid).
+ * Otherwise select the first low or medium priority interrupt timer available.
+ */
+#if XCHAL_NUM_TIMERS == 0
+
+    #error "This Xtensa configuration is unsupported, it has no timers."
+
+#else
+
+    #ifndef XT_TIMER_INDEX
+        #if XCHAL_TIMER3_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
+            #if XCHAL_INT_LEVEL( XCHAL_TIMER3_INTERRUPT ) <= XCHAL_EXCM_LEVEL
+                #undef  XT_TIMER_INDEX
+                #define XT_TIMER_INDEX    3
+            #endif
+        #endif
+        #if XCHAL_TIMER2_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
+            #if XCHAL_INT_LEVEL( XCHAL_TIMER2_INTERRUPT ) <= XCHAL_EXCM_LEVEL
+                #undef  XT_TIMER_INDEX
+                #define XT_TIMER_INDEX    2
+            #endif
+        #endif
+        #if XCHAL_TIMER1_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
+            #if XCHAL_INT_LEVEL( XCHAL_TIMER1_INTERRUPT ) <= XCHAL_EXCM_LEVEL
+                #undef  XT_TIMER_INDEX
+                #define XT_TIMER_INDEX    1
+            #endif
+        #endif
+        #if XCHAL_TIMER0_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
+            #if XCHAL_INT_LEVEL( XCHAL_TIMER0_INTERRUPT ) <= XCHAL_EXCM_LEVEL
+                #undef  XT_TIMER_INDEX
+                #define XT_TIMER_INDEX    0
+            #endif
+        #endif
+    #endif /* ifndef XT_TIMER_INDEX */
+    #ifndef XT_TIMER_INDEX
+        #error "There is no suitable timer in this Xtensa configuration."
+    #endif
+
+    #define XT_CCOMPARE        ( CCOMPARE + XT_TIMER_INDEX )
+    #define XT_TIMER_INTNUM    XCHAL_TIMER_INTERRUPT( XT_TIMER_INDEX )
+    #define XT_TIMER_INTPRI    XCHAL_INT_LEVEL( XT_TIMER_INTNUM )
+    #define XT_TIMER_INTEN     ( 1 << XT_TIMER_INTNUM )
+
+    #if XT_TIMER_INTNUM == XTHAL_TIMER_UNCONFIGURED
+        #error "The timer selected by XT_TIMER_INDEX does not exist in this core."
+    #elif XT_TIMER_INTPRI > XCHAL_EXCM_LEVEL
+        #error "The timer interrupt cannot be high priority (use medium or low)."
+    #endif
+
+#endif /* XCHAL_NUM_TIMERS */
+
+/*
+ * Set processor clock frequency, used to determine clock divisor for timer tick.
+ * User should BE SURE TO ADJUST THIS for the Xtensa platform being used.
+ * If using a supported board via the board-independent API defined in xtbsp.h,
+ * this may be left undefined and frequency and tick divisor will be computed
+ * and cached during run-time initialization.
+ *
+ * NOTE ON SIMULATOR:
+ * Under the Xtensa instruction set simulator, the frequency can only be estimated
+ * because it depends on the speed of the host and the version of the simulator.
+ * Also because it runs much slower than hardware, it is not possible to achieve
+ * real-time performance for most applications under the simulator. A frequency
+ * too low does not allow enough time between timer interrupts, starving threads.
+ * To obtain a more convenient but non-real-time tick duration on the simulator,
+ * compile with xt-xcc option "-DXT_SIMULATOR".
+ * Adjust this frequency to taste (it's not real-time anyway!).
+ */
+#if defined( XT_SIMULATOR ) && !defined( XT_CLOCK_FREQ )
+    #define XT_CLOCK_FREQ    configCPU_CLOCK_HZ
+#endif
+
+#if !defined( XT_CLOCK_FREQ ) && !defined( XT_BOARD )
+    #error "XT_CLOCK_FREQ must be defined for the target platform."
+#endif
+
+/*
+ * Default number of timer "ticks" per second (default 100 for 10ms tick).
+ * RTOS may define this in its own way (if applicable) in xtensa_rtos.h.
+ * User may redefine this to an optimal value for the application, either by
+ * editing this here or in xtensa_rtos.h, or compiling with xt-xcc option
+ * "-DXT_TICK_PER_SEC=<value>" where <value> is a suitable number.
+ */
+#ifndef XT_TICK_PER_SEC
+    #define XT_TICK_PER_SEC    configTICK_RATE_HZ    /* 10 ms tick = 100 ticks per second */
+#endif
+
+/*
+ * Derivation of clock divisor for timer tick and interrupt (one per tick).
+ */
+#ifdef XT_CLOCK_FREQ
+    #define XT_TICK_DIVISOR    ( XT_CLOCK_FREQ / XT_TICK_PER_SEC )
+#endif
+
+#ifndef __ASSEMBLER__
+    extern unsigned _xt_tick_divisor;
+    extern void _xt_tick_divisor_init( void );
+#endif
+
+#endif /* XTENSA_TIMER_H */

kernel/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/port.c

@@ -0,0 +1,568 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Amazon.com, Inc. or its affiliates
+ * SPDX-FileCopyrightText: 2015-2019 Cadence Design Systems, Inc.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD
+ */
+/*
+ * FreeRTOS Kernel V10.5.1
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+/*
+ * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <stdlib.h>
+#include <string.h>
+#include <xtensa/config/core.h>
+
+#include "xtensa_rtos.h"
+#include "esp_idf_version.h"
+
+#if (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0))
+#include "rom/ets_sys.h"
+#include "esp_panic.h"
+#include "esp_crosscore_int.h"
+#else
+#if CONFIG_IDF_TARGET_ESP32S3
+    #include "esp32s3/rom/ets_sys.h"
+#elif CONFIG_IDF_TARGET_ESP32S2
+    #include "esp32s2/rom/ets_sys.h"
+#elif CONFIG_IDF_TARGET_ESP32
+    #include "esp32/rom/ets_sys.h"
+#endif
+#include "esp_private/panic_reason.h"
+#include "esp_debug_helpers.h"
+#include "esp_private/crosscore_int.h"
+#include "esp_log.h"
+#endif /* ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0) */
+#include "soc/cpu.h"
+
+#include "FreeRTOS.h"
+#include "task.h"
+
+#include "esp_heap_caps.h"
+
+#include "esp_intr_alloc.h"
+
+#include "port_systick.h"
+
+/* Defined in xtensa_context.S */
+extern void _xt_coproc_init( void );
+
+_Static_assert(tskNO_AFFINITY == CONFIG_FREERTOS_NO_AFFINITY, "incorrect tskNO_AFFINITY value");
+
+/*-----------------------------------------------------------*/
+
+extern volatile int port_xSchedulerRunning[portNUM_PROCESSORS];
+unsigned port_interruptNesting[ portNUM_PROCESSORS ] = { 0 };  /* Interrupt nesting level. Increased/decreased in portasm.c, _frxt_int_enter/_frxt_int_exit */
+
+/*-----------------------------------------------------------*/
+
+/* User exception dispatcher when exiting */
+void _xt_user_exit( void );
+
+#if CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER
+/* Wrapper to allow task functions to return (increases stack overhead by 16 bytes) */
+    static void vPortTaskWrapper( TaskFunction_t pxCode,
+                                  void * pvParameters )
+    {
+        pxCode( pvParameters );
+        /*FreeRTOS tasks should not return. Log the task name and abort. */
+        char * pcTaskName = pcTaskGetTaskName( NULL );
+        ESP_LOGE( "FreeRTOS", "FreeRTOS Task \"%s\" should not return, Aborting now!", pcTaskName );
+        abort();
+    }
+#endif /* if CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER */
+
+/*
+ * Stack initialization
+ */
+/* *INDENT-OFF* */
+#if portUSING_MPU_WRAPPERS
+    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                         TaskFunction_t pxCode,
+                                         void * pvParameters,
+                                         BaseType_t xRunPrivileged )
+#else
+    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                         TaskFunction_t pxCode,
+                                         void * pvParameters )
+#endif
+/* *INDENT-ON* */
+{
+    StackType_t * sp;
+    StackType_t * tp;
+    XtExcFrame * frame;
+
+    #if XCHAL_CP_NUM > 0
+        uint32_t * p;
+    #endif
+
+    uint32_t * threadptr;
+    void * task_thread_local_start;
+    extern int _thread_local_start, _thread_local_end, _flash_rodata_start, _flash_rodata_align;
+
+    /* TODO: check that TLS area fits the stack */
+    uint32_t thread_local_sz = ( uint8_t * ) &_thread_local_end - ( uint8_t * ) &_thread_local_start;
+
+    thread_local_sz = ALIGNUP( 0x10, thread_local_sz );
+
+    /* Initialize task's stack so that we have the following structure at the top:
+
+        ----LOW ADDRESSES ----------------------------------------HIGH ADDRESSES----------
+         task stack | interrupt stack frame | thread local vars | co-processor save area |
+        ----------------------------------------------------------------------------------
+                    |                                                                    |
+                    SP                                                             pxTopOfStack
+
+        All parts are aligned to 16 byte boundary.
+    */
+
+    /* Create interrupt stack frame aligned to 16 byte boundary */
+    sp = ( StackType_t * ) ( ( ( UBaseType_t ) pxTopOfStack - XT_CP_SIZE - thread_local_sz - XT_STK_FRMSZ ) & ~0xf );
+
+    /* Clear the entire frame (do not use memset() because we don't depend on C library) */
+    for( tp = sp; tp <= pxTopOfStack; ++tp )
+    {
+        *tp = 0;
+    }
+
+    frame = ( XtExcFrame * ) sp;
+
+    /* Explicitly initialize certain saved registers */
+    #if CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER
+        frame->pc = ( UBaseType_t ) vPortTaskWrapper; /* task wrapper						*/
+    #else
+        frame->pc = ( UBaseType_t ) pxCode;           /* task entrypoint					*/
+    #endif
+    frame->a0 = 0;                                    /* to terminate GDB backtrace		*/
+    frame->a1 = ( UBaseType_t ) sp + XT_STK_FRMSZ;    /* physical top of stack frame		*/
+    frame->exit = ( UBaseType_t ) _xt_user_exit;      /* user exception exit dispatcher	*/
+
+    /* Set initial PS to int level 0, EXCM disabled ('rfe' will enable), user mode. */
+    /* Also set entry point argument parameter. */
+    #ifdef __XTENSA_CALL0_ABI__
+        #if CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER
+            frame->a2 = ( UBaseType_t ) pxCode;
+            frame->a3 = ( UBaseType_t ) pvParameters;
+        #else
+            frame->a2 = ( UBaseType_t ) pvParameters;
+        #endif
+        frame->ps = PS_UM | PS_EXCM;
+    #else
+        /* + for windowed ABI also set WOE and CALLINC (pretend task was 'call4'd). */
+        #if CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER
+            frame->a6 = ( UBaseType_t ) pxCode;
+            frame->a7 = ( UBaseType_t ) pvParameters;
+        #else
+            frame->a6 = ( UBaseType_t ) pvParameters;
+        #endif
+        frame->ps = PS_UM | PS_EXCM | PS_WOE | PS_CALLINC( 1 );
+    #endif /* ifdef __XTENSA_CALL0_ABI__ */
+
+    #ifdef XT_USE_SWPRI
+        /* Set the initial virtual priority mask value to all 1's. */
+        frame->vpri = 0xFFFFFFFF;
+    #endif
+
+    /* Init threadptr register and set up TLS run-time area. */
+    task_thread_local_start = ( void * ) ( ( ( uint32_t ) pxTopOfStack - XT_CP_SIZE - thread_local_sz ) & ~0xf );
+    memcpy( task_thread_local_start, &_thread_local_start, thread_local_sz );
+    threadptr = ( uint32_t * ) ( sp + XT_STK_EXTRA );
+
+    /* Calculate THREADPTR value.
+     * The generated code will add THREADPTR value to a constant value determined at link time,
+     * to get the address of the TLS variable.
+     * The constant value is calculated by the linker as follows
+     * (search for 'tpoff' in elf32-xtensa.c in BFD):
+     *    offset = address - tls_section_vma + align_up(TCB_SIZE, tls_section_alignment)
+     * where TCB_SIZE is hardcoded to 8.
+     */
+    const uint32_t tls_section_alignment = ( uint32_t ) &_flash_rodata_align; /* ALIGN value of .flash.rodata section */
+    const uint32_t tcb_size = 8;                                              /* Unrelated to FreeRTOS, this is the constant from BFD */
+    const uint32_t base = ( tcb_size + tls_section_alignment - 1 ) & ( ~( tls_section_alignment - 1 ) );
+    *threadptr = ( uint32_t ) task_thread_local_start - ( ( uint32_t ) &_thread_local_start - ( uint32_t ) &_flash_rodata_start ) - base;
+
+    #if XCHAL_CP_NUM > 0
+        /* Init the coprocessor save area (see xtensa_context.h) */
+
+        /* No access to TCB here, so derive indirectly. Stack growth is top to bottom.
+         * //p = (uint32_t *) xMPUSettings->coproc_area;
+         */
+        p = ( uint32_t * ) ( ( ( uint32_t ) pxTopOfStack - XT_CP_SIZE ) & ~0xf );
+        configASSERT( ( uint32_t ) p >= frame->a1 );
+        p[ 0 ] = 0;
+        p[ 1 ] = 0;
+        p[ 2 ] = ( ( ( uint32_t ) p ) + 12 + XCHAL_TOTAL_SA_ALIGN - 1 ) & -XCHAL_TOTAL_SA_ALIGN;
+    #endif
+
+    return sp;
+}
+
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+    /* It is unlikely that the Xtensa port will get stopped.  If required simply
+     * disable the tick interrupt here. */
+    abort();
+}
+
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+    portDISABLE_INTERRUPTS();
+    /* Interrupts are disabled at this point and stack contains PS with enabled interrupts when task context is restored */
+
+    #if XCHAL_CP_NUM > 0
+        /* Initialize co-processor management for tasks. Leave CPENABLE alone. */
+        _xt_coproc_init();
+    #endif
+
+    /* Setup the hardware to generate the tick */
+    vPortSetupTimer();
+
+    /* NOTE: For ESP32-S3, vPortSetupTimer allocates an interrupt for the
+     * systimer which is used as the source for FreeRTOS systick.
+     *
+     * The behaviour of portEXIT_CRITICAL is different in FreeRTOS and ESP-IDF -
+     * the former enables the interrupts no matter what the state was at the beginning
+     * of the call while the latter restores the interrupt state to what was at the
+     * beginning of the call.
+     *
+     * This resulted in the interrupts being enabled before the _frxt_dispatch call,
+     * who was unable to switch context to the queued tasks.
+     */
+    portDISABLE_INTERRUPTS();
+
+    port_xSchedulerRunning[ xPortGetCoreID() ] = 1;
+
+    /* Cannot be directly called from C; never returns */
+    __asm__ volatile ( "call0    _frxt_dispatch\n" );
+
+    /* Should not get here. */
+    return pdTRUE;
+}
+
+/*-----------------------------------------------------------*/
+
+void vPortYieldOtherCore( BaseType_t coreid )
+{
+    esp_crosscore_int_send_yield( coreid );
+}
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Used to set coprocessor area in stack. Current hack is to reuse MPU pointer for coprocessor area.
+ */
+#if portUSING_MPU_WRAPPERS
+    void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
+                                    const struct xMEMORY_REGION * const xRegions,
+                                    StackType_t * pxBottomOfStack,
+                                    uint32_t usStackDepth )
+    {
+        #if XCHAL_CP_NUM > 0
+            xMPUSettings->coproc_area = ( StackType_t * ) ( ( uint32_t ) ( pxBottomOfStack + usStackDepth - 1 ));
+            xMPUSettings->coproc_area = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) xMPUSettings->coproc_area ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) );
+            xMPUSettings->coproc_area = ( StackType_t * ) ( ( ( uint32_t ) xMPUSettings->coproc_area - XT_CP_SIZE ) & ~0xf );
+
+            /* NOTE: we cannot initialize the coprocessor save area here because FreeRTOS is going to
+             * clear the stack area after we return. This is done in pxPortInitialiseStack().
+             */
+        #endif
+    }
+
+    void vPortReleaseTaskMPUSettings( xMPU_SETTINGS * xMPUSettings )
+    {
+        /* If task has live floating point registers somewhere, release them */
+        _xt_coproc_release( xMPUSettings->coproc_area );
+    }
+
+#endif /* if portUSING_MPU_WRAPPERS */
+
+/*
+ * Returns true if the current core is in ISR context; low prio ISR, med prio ISR or timer tick ISR. High prio ISRs
+ * aren't detected here, but they normally cannot call C code, so that should not be an issue anyway.
+ */
+BaseType_t xPortInIsrContext()
+{
+    unsigned int irqStatus;
+    BaseType_t ret;
+
+    irqStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+    ret = ( port_interruptNesting[ xPortGetCoreID() ] != 0 );
+    portCLEAR_INTERRUPT_MASK_FROM_ISR( irqStatus );
+    return ret;
+}
+
+/*
+ * This function will be called in High prio ISRs. Returns true if the current core was in ISR context
+ * before calling into high prio ISR context.
+ */
+BaseType_t IRAM_ATTR xPortInterruptedFromISRContext()
+{
+    return( port_interruptNesting[ xPortGetCoreID() ] != 0 );
+}
+
+void IRAM_ATTR vPortEvaluateYieldFromISR( int argc, ... )
+{
+    BaseType_t xYield;
+    va_list ap;
+    va_start( ap, argc );
+
+    if( argc )
+    {
+        xYield = ( BaseType_t )va_arg( ap, int );
+        va_end( ap );
+    }
+    else
+    {
+        //it is a empty parameter vPortYieldFromISR macro call:
+        va_end( ap );
+        traceISR_EXIT_TO_SCHEDULER();
+        _frxt_setup_switch();
+        return;
+    }
+
+    //Yield exists, so need evaluate it first then switch:
+    if( xYield == pdTRUE )
+    {
+        traceISR_EXIT_TO_SCHEDULER();
+        _frxt_setup_switch();
+    }
+}
+
+void vPortAssertIfInISR()
+{
+    if( xPortInIsrContext() )
+    {
+        esp_rom_printf( "core=%d port_interruptNesting=%d\n\n", xPortGetCoreID(), port_interruptNesting[ xPortGetCoreID() ] );
+    }
+
+    configASSERT( !xPortInIsrContext() );
+}
+
+/*
+ * For kernel use: Initialize a per-CPU mux. Mux will be initialized unlocked.
+ */
+void vPortCPUInitializeMutex( portMUX_TYPE * mux )
+{
+    #ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
+        esp_rom_printf( "Initializing mux %p\n", mux );
+        mux->lastLockedFn = "(never locked)";
+        mux->lastLockedLine = -1;
+    #endif
+    mux->owner = portMUX_FREE_VAL;
+    mux->count = 0;
+}
+
+#include "portmux_impl.h"
+
+/*
+ * For kernel use: Acquire a per-CPU mux. Spinlocks, so don't hold on to these muxes for too long.
+ */
+#ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
+    void vPortCPUAcquireMutex( portMUX_TYPE * mux,
+                               const char * fnName,
+                               int line )
+    {
+        unsigned int irqStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+
+        vPortCPUAcquireMutexIntsDisabled( mux, portMUX_NO_TIMEOUT, fnName, line );
+        portCLEAR_INTERRUPT_MASK_FROM_ISR( irqStatus );
+    }
+
+    bool vPortCPUAcquireMutexTimeout( portMUX_TYPE * mux,
+                                      int timeout_cycles,
+                                      const char * fnName,
+                                      int line )
+    {
+        unsigned int irqStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+        bool result = vPortCPUAcquireMutexIntsDisabled( mux, timeout_cycles, fnName, line );
+
+        portCLEAR_INTERRUPT_MASK_FROM_ISR( irqStatus );
+        return result;
+    }
+
+#else /* ifdef CONFIG_FREERTOS_PORTMUX_DEBUG */
+    void vPortCPUAcquireMutex( portMUX_TYPE * mux )
+    {
+        unsigned int irqStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+
+        vPortCPUAcquireMutexIntsDisabled( mux, portMUX_NO_TIMEOUT );
+        portCLEAR_INTERRUPT_MASK_FROM_ISR( irqStatus );
+    }
+
+    bool vPortCPUAcquireMutexTimeout( portMUX_TYPE * mux,
+                                      int timeout_cycles )
+    {
+        unsigned int irqStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+        bool result = vPortCPUAcquireMutexIntsDisabled( mux, timeout_cycles );
+
+        portCLEAR_INTERRUPT_MASK_FROM_ISR( irqStatus );
+        return result;
+    }
+#endif /* ifdef CONFIG_FREERTOS_PORTMUX_DEBUG */
+
+
+/*
+ * For kernel use: Release a per-CPU mux
+ *
+ * Mux must be already locked by this core
+ */
+#ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
+    void vPortCPUReleaseMutex( portMUX_TYPE * mux,
+                               const char * fnName,
+                               int line )
+    {
+        unsigned int irqStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+
+        vPortCPUReleaseMutexIntsDisabled( mux, fnName, line );
+        portCLEAR_INTERRUPT_MASK_FROM_ISR( irqStatus );
+    }
+#else
+    void vPortCPUReleaseMutex( portMUX_TYPE * mux )
+    {
+        unsigned int irqStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+
+        vPortCPUReleaseMutexIntsDisabled( mux );
+        portCLEAR_INTERRUPT_MASK_FROM_ISR( irqStatus );
+    }
+#endif /* ifdef CONFIG_FREERTOS_PORTMUX_DEBUG */
+
+#define STACK_WATCH_AREA_SIZE ( 32 )
+#define STACK_WATCH_POINT_NUMBER ( SOC_CPU_WATCHPOINTS_NUM - 1 )
+
+void vPortSetStackWatchpoint( void * pxStackStart )
+{
+    /*Set watchpoint 1 to watch the last 32 bytes of the stack. */
+    /*Unfortunately, the Xtensa watchpoints can't set a watchpoint on a random [base - base+n] region because */
+    /*the size works by masking off the lowest address bits. For that reason, we futz a bit and watch the lowest 32 */
+    /*bytes of the stack we can actually watch. In general, this can cause the watchpoint to be triggered at most */
+    /*28 bytes early. The value 32 is chosen because it's larger than the stack canary, which in FreeRTOS is 20 bytes. */
+    /*This way, we make sure we trigger before/when the stack canary is corrupted, not after. */
+    int addr = ( int ) pxStackStart;
+
+    addr = ( addr + 31 ) & ( ~31 );
+    esp_cpu_set_watchpoint( STACK_WATCH_POINT_NUMBER, (char*)addr, 32, ESP_WATCHPOINT_STORE );
+}
+
+#if (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0))
+
+#if defined( CONFIG_SPIRAM_SUPPORT )
+
+/*
+ * Compare & set (S32C1) does not work in external RAM. Instead, this routine uses a mux (in internal memory) to fake it.
+ */
+    static portMUX_TYPE extram_mux = portMUX_INITIALIZER_UNLOCKED;
+
+    void uxPortCompareSetExtram( volatile uint32_t * addr,
+                                 uint32_t compare,
+                                 uint32_t * set )
+    {
+        uint32_t prev;
+
+        uint32_t oldlevel = portSET_INTERRUPT_MASK_FROM_ISR();
+
+        #ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
+            vPortCPUAcquireMutexIntsDisabled( &extram_mux, portMUX_NO_TIMEOUT, __FUNCTION__, __LINE__ );
+        #else
+            vPortCPUAcquireMutexIntsDisabled( &extram_mux, portMUX_NO_TIMEOUT );
+        #endif
+        prev = *addr;
+
+        if( prev == compare )
+        {
+            *addr = *set;
+        }
+
+        *set = prev;
+        #ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
+            vPortCPUReleaseMutexIntsDisabled( &extram_mux, __FUNCTION__, __LINE__ );
+        #else
+            vPortCPUReleaseMutexIntsDisabled( &extram_mux );
+        #endif
+
+        portCLEAR_INTERRUPT_MASK_FROM_ISR(oldlevel);
+    }
+#endif //defined(CONFIG_SPIRAM_SUPPORT)
+
+#endif /* ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0) */
+
+
+uint32_t xPortGetTickRateHz( void )
+{
+    return ( uint32_t ) configTICK_RATE_HZ;
+}
+
+// For now, running FreeRTOS on one core and a bare metal on the other (or other OSes)
+// is not supported. For now CONFIG_FREERTOS_UNICORE and CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
+// should mirror each other's values.
+//
+// And since this should be true, we can just check for CONFIG_FREERTOS_UNICORE.
+#if CONFIG_FREERTOS_UNICORE != CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
+    #error "FreeRTOS and system configuration mismatch regarding the use of multiple cores."
+#endif
+
+extern void esp_startup_start_app_common(void);
+
+void esp_startup_start_app(void)
+{
+#if !CONFIG_ESP_INT_WDT
+#if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
+    assert(!soc_has_cache_lock_bug() && "ESP32 Rev 3 + Dual Core + PSRAM requires INT WDT enabled in project config!");
+#endif
+#endif
+
+    esp_startup_start_app_common();
+
+    ESP_LOGI("cpu_start", "Starting scheduler on PRO CPU.");
+    vTaskStartScheduler();
+}

kernel/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/port_common.c

@@ -0,0 +1,159 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <string.h>
+#include "FreeRTOS.h"
+#include "task.h"
+#include "portmacro.h"
+#include "esp_system.h"
+#include "esp_heap_caps_init.h"
+#include "esp_int_wdt.h"
+#include "esp_task_wdt.h"
+#include "esp_task.h"
+#include "esp_private/crosscore_int.h"
+#include "esp_private/startup_internal.h"    /* Required by g_spiram_ok. [refactor-todo] for g_spiram_ok */
+#include "esp_log.h"
+#include "soc/soc_memory_types.h"
+#include "soc/dport_access.h"
+#include "sdkconfig.h"
+#include "esp_freertos_hooks.h"
+
+#if CONFIG_IDF_TARGET_ESP32
+#include "esp32/spiram.h"
+#elif CONFIG_IDF_TARGET_ESP32S2
+#include "esp32s2/spiram.h"
+#elif CONFIG_IDF_TARGET_ESP32S3
+#include "esp32s3/spiram.h"
+#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2
+// SPIRAM is not supported on ESP32-C3
+#endif
+
+#if CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL
+static const char* TAG = "cpu_start";
+#endif
+
+/* Architecture-agnostic parts of the FreeRTOS ESP-IDF port layer can go here.
+ *
+ * The actual call flow will be to call esp_startup_start_app() in <ARCH>/port.c,
+ * which will then call esp_startup_start_app_common()
+ */
+
+// Duplicate of inaccessible xSchedulerRunning; needed at startup to avoid counting nesting
+volatile unsigned port_xSchedulerRunning[portNUM_PROCESSORS] = {0};
+
+// For now, running FreeRTOS on one core and a bare metal on the other (or other OSes)
+// is not supported. For now CONFIG_FREERTOS_UNICORE and CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
+// should mirror each other's values.
+//
+// And since this should be true, we can just check for CONFIG_FREERTOS_UNICORE.
+#if CONFIG_FREERTOS_UNICORE != CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
+    #error "FreeRTOS and system configuration mismatch regarding the use of multiple cores."
+#endif
+
+static void main_task(void* args);
+
+#ifdef CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME
+void esp_gdbstub_init(void);
+#endif // CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME
+
+extern void app_main(void);
+
+void esp_startup_start_app_common(void)
+{
+#if CONFIG_ESP_INT_WDT
+    esp_int_wdt_init();
+    //Initialize the interrupt watch dog for CPU0.
+    esp_int_wdt_cpu_init();
+#endif
+
+    esp_crosscore_int_init();
+
+#ifdef CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME
+    esp_gdbstub_init();
+#endif // CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME
+
+    portBASE_TYPE res = xTaskCreatePinnedToCore(&main_task, "main",
+                                                ESP_TASK_MAIN_STACK, NULL,
+                                                ESP_TASK_MAIN_PRIO, NULL, ESP_TASK_MAIN_CORE);
+    assert(res == pdTRUE);
+    (void)res;
+}
+
+#if !CONFIG_FREERTOS_UNICORE
+static volatile bool s_other_cpu_startup_done = false;
+static bool other_cpu_startup_idle_hook_cb(void)
+{
+    s_other_cpu_startup_done = true;
+    return true;
+}
+#endif
+
+static void main_task(void* args)
+{
+#if !CONFIG_FREERTOS_UNICORE
+    // Wait for FreeRTOS initialization to finish on other core, before replacing its startup stack
+    esp_register_freertos_idle_hook_for_cpu(other_cpu_startup_idle_hook_cb, !xPortGetCoreID());
+    while (!s_other_cpu_startup_done) {
+        ;
+    }
+    esp_deregister_freertos_idle_hook_for_cpu(other_cpu_startup_idle_hook_cb, !xPortGetCoreID());
+#endif
+
+    // [refactor-todo] check if there is a way to move the following block to esp_system startup
+    heap_caps_enable_nonos_stack_heaps();
+
+    // Now we have startup stack RAM available for heap, enable any DMA pool memory
+#if CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL
+    if (g_spiram_ok) {
+        esp_err_t r = esp_spiram_reserve_dma_pool(CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL);
+        if (r != ESP_OK) {
+            ESP_EARLY_LOGE(TAG, "Could not reserve internal/DMA pool (error 0x%x)", r);
+            abort();
+        }
+    }
+#endif
+
+    //Initialize task wdt if configured to do so
+#ifdef CONFIG_ESP_TASK_WDT_PANIC
+    ESP_ERROR_CHECK(esp_task_wdt_init(CONFIG_ESP_TASK_WDT_TIMEOUT_S, true));
+#elif CONFIG_ESP_TASK_WDT
+    ESP_ERROR_CHECK(esp_task_wdt_init(CONFIG_ESP_TASK_WDT_TIMEOUT_S, false));
+#endif
+
+    //Add IDLE 0 to task wdt
+#ifdef CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0
+    TaskHandle_t idle_0 = xTaskGetIdleTaskHandleForCPU(0);
+    if(idle_0 != NULL){
+        ESP_ERROR_CHECK(esp_task_wdt_add(idle_0));
+    }
+#endif
+    //Add IDLE 1 to task wdt
+#ifdef CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU1
+    TaskHandle_t idle_1 = xTaskGetIdleTaskHandleForCPU(1);
+    if(idle_1 != NULL){
+        ESP_ERROR_CHECK(esp_task_wdt_add(idle_1));
+    }
+#endif
+
+    app_main();
+    vTaskDelete(NULL);
+}
+
+// -------------------- Heap Related -----------------------
+
+bool xPortCheckValidTCBMem(const void *ptr)
+{
+    return esp_ptr_internal(ptr) && esp_ptr_byte_accessible(ptr);
+}
+
+bool xPortcheckValidStackMem(const void *ptr)
+{
+#ifdef CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
+    return esp_ptr_byte_accessible(ptr);
+#else
+    return esp_ptr_internal(ptr) && esp_ptr_byte_accessible(ptr);
+#endif
+}

kernel/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/port_systick.c

@@ -0,0 +1,174 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdlib.h>
+#include <string.h>
+#include "soc/cpu.h"
+#include "FreeRTOS.h"
+#include "task.h"
+#include "esp_intr_alloc.h"
+#include "esp_err.h"
+#include "esp_log.h"
+#include "sdkconfig.h"
+#ifdef CONFIG_FREERTOS_SYSTICK_USES_SYSTIMER
+#include "soc/periph_defs.h"
+#include "soc/system_reg.h"
+#include "hal/systimer_hal.h"
+#include "hal/systimer_ll.h"
+#endif
+
+#ifdef CONFIG_PM_TRACE
+#include "esp_private/pm_trace.h"
+#endif //CONFIG_PM_TRACE
+
+BaseType_t xPortSysTickHandler(void);
+
+#ifdef CONFIG_FREERTOS_SYSTICK_USES_CCOUNT
+extern void _frxt_tick_timer_init(void);
+extern void _xt_tick_divisor_init(void);
+
+#ifdef CONFIG_FREERTOS_CORETIMER_0
+    #define SYSTICK_INTR_ID (ETS_INTERNAL_TIMER0_INTR_SOURCE+ETS_INTERNAL_INTR_SOURCE_OFF)
+#endif
+#ifdef CONFIG_FREERTOS_CORETIMER_1
+    #define SYSTICK_INTR_ID (ETS_INTERNAL_TIMER1_INTR_SOURCE+ETS_INTERNAL_INTR_SOURCE_OFF)
+#endif
+
+/**
+ * @brief Initialize CCONT timer to generate the tick interrupt
+ *
+ */
+void vPortSetupTimer(void)
+{
+    /* Init the tick divisor value */
+    _xt_tick_divisor_init();
+
+    _frxt_tick_timer_init();
+}
+
+
+#elif CONFIG_FREERTOS_SYSTICK_USES_SYSTIMER
+
+_Static_assert(SOC_CPU_CORES_NUM <= SOC_SYSTIMER_ALARM_NUM - 1, "the number of cores must match the number of core alarms in SYSTIMER");
+
+void SysTickIsrHandler(void *arg);
+
+static uint32_t s_handled_systicks[portNUM_PROCESSORS] = { 0 };
+
+#define SYSTICK_INTR_ID (ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE)
+
+/**
+ * @brief Set up the systimer peripheral to generate the tick interrupt
+ *
+ * Both timer alarms are configured in periodic mode.
+ * It is done at the same time so SysTicks for both CPUs occur at the same time or very close.
+ * Shifts a time of triggering interrupts for core 0 and core 1.
+ */
+void vPortSetupTimer(void)
+{
+    unsigned cpuid = xPortGetCoreID();
+#ifdef CONFIG_FREERTOS_CORETIMER_SYSTIMER_LVL3
+    const unsigned level = ESP_INTR_FLAG_LEVEL3;
+#else
+    const unsigned level = ESP_INTR_FLAG_LEVEL1;
+#endif
+    /* Systimer HAL layer object */
+    static systimer_hal_context_t systimer_hal;
+    /* set system timer interrupt vector */
+    ESP_ERROR_CHECK(esp_intr_alloc(ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE + cpuid, ESP_INTR_FLAG_IRAM | level, SysTickIsrHandler, &systimer_hal, NULL));
+
+    if (cpuid == 0) {
+        systimer_hal_init(&systimer_hal);
+        systimer_ll_set_counter_value(systimer_hal.dev, SYSTIMER_LL_COUNTER_OS_TICK, 0);
+        systimer_ll_apply_counter_value(systimer_hal.dev, SYSTIMER_LL_COUNTER_OS_TICK);
+
+        for (cpuid = 0; cpuid < SOC_CPU_CORES_NUM; cpuid++) {
+            systimer_hal_counter_can_stall_by_cpu(&systimer_hal, SYSTIMER_LL_COUNTER_OS_TICK, cpuid, false);
+        }
+
+        for (cpuid = 0; cpuid < portNUM_PROCESSORS; ++cpuid) {
+            uint32_t alarm_id = SYSTIMER_LL_ALARM_OS_TICK_CORE0 + cpuid;
+
+            /* configure the timer */
+            systimer_hal_connect_alarm_counter(&systimer_hal, alarm_id, SYSTIMER_LL_COUNTER_OS_TICK);
+            systimer_hal_set_alarm_period(&systimer_hal, alarm_id, 1000000UL / CONFIG_FREERTOS_HZ);
+            systimer_hal_select_alarm_mode(&systimer_hal, alarm_id, SYSTIMER_ALARM_MODE_PERIOD);
+            systimer_hal_counter_can_stall_by_cpu(&systimer_hal, SYSTIMER_LL_COUNTER_OS_TICK, cpuid, true);
+            if (cpuid == 0) {
+                systimer_hal_enable_alarm_int(&systimer_hal, alarm_id);
+                systimer_hal_enable_counter(&systimer_hal, SYSTIMER_LL_COUNTER_OS_TICK);
+#ifndef CONFIG_FREERTOS_UNICORE
+                // SysTick of core 0 and core 1 are shifted by half of period
+                systimer_hal_counter_value_advance(&systimer_hal, SYSTIMER_LL_COUNTER_OS_TICK, 1000000UL / CONFIG_FREERTOS_HZ / 2);
+#endif
+            }
+        }
+    } else {
+        uint32_t alarm_id = SYSTIMER_LL_ALARM_OS_TICK_CORE0 + cpuid;
+        systimer_hal_enable_alarm_int(&systimer_hal, alarm_id);
+    }
+}
+
+/**
+ * @brief Systimer interrupt handler.
+ *
+ * The Systimer interrupt for SysTick works in periodic mode no need to calc the next alarm.
+ * If a timer interrupt is ever serviced more than one tick late, it is necessary to process multiple ticks.
+ */
+IRAM_ATTR void SysTickIsrHandler(void *arg)
+{
+    uint32_t cpuid = xPortGetCoreID();
+    systimer_hal_context_t *systimer_hal = (systimer_hal_context_t *)arg;
+#ifdef CONFIG_PM_TRACE
+    ESP_PM_TRACE_ENTER(TICK, cpuid);
+#endif
+
+    uint32_t alarm_id = SYSTIMER_LL_ALARM_OS_TICK_CORE0 + cpuid;
+    do {
+        systimer_ll_clear_alarm_int(systimer_hal->dev, alarm_id);
+
+        uint32_t diff = systimer_hal_get_counter_value(systimer_hal, SYSTIMER_LL_COUNTER_OS_TICK) / systimer_ll_get_alarm_period(systimer_hal->dev, alarm_id) - s_handled_systicks[cpuid];
+        if (diff > 0) {
+            if (s_handled_systicks[cpuid] == 0) {
+                s_handled_systicks[cpuid] = diff;
+                diff = 1;
+            } else {
+                s_handled_systicks[cpuid] += diff;
+            }
+
+            do {
+                xPortSysTickHandler();
+            } while (--diff);
+        }
+    } while (systimer_ll_is_alarm_int_fired(systimer_hal->dev, alarm_id));
+
+#ifdef CONFIG_PM_TRACE
+    ESP_PM_TRACE_EXIT(TICK, cpuid);
+#endif
+}
+
+#endif // CONFIG_FREERTOS_SYSTICK_USES_CCOUNT
+
+/**
+ * @brief Handler of SysTick
+ *
+ * The function is called from:
+ *  - _frxt_timer_int for xtensa with CONFIG_FREERTOS_SYSTICK_USES_CCOUNT
+ *  - SysTickIsrHandler for xtensa with CONFIG_FREERTOS_SYSTICK_USES_SYSTIMER
+ *  - SysTickIsrHandler for riscv
+ */
+BaseType_t xPortSysTickHandler(void)
+{
+    portbenchmarkIntLatency();
+    traceISR_ENTER(SYSTICK_INTR_ID);
+    BaseType_t ret = xTaskIncrementTick();
+    if(ret != pdFALSE) {
+        portYIELD_FROM_ISR();
+    } else {
+        traceISR_EXIT();
+    }
+    return ret;
+}

kernel/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/portasm.S

@@ -0,0 +1,701 @@
+/*
+ * SPDX-FileCopyrightText: 2015-2019 Cadence Design Systems, Inc.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD
+ */
+/*
+ * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "xtensa_rtos.h"
+#include "sdkconfig.h"
+#include "esp_idf_version.h"
+
+#define TOPOFSTACK_OFFS                 0x00    /* StackType_t *pxTopOfStack */
+#define CP_TOPOFSTACK_OFFS              0x04    /* xMPU_SETTINGS.coproc_area */
+
+.extern pxCurrentTCB
+
+/*
+*******************************************************************************
+* Interrupt stack. The size of the interrupt stack is determined by the config
+* parameter "configISR_STACK_SIZE" in FreeRTOSConfig.h
+*******************************************************************************
+*/
+
+    .data
+    .align      16
+    .global     port_IntStack
+    .global     port_IntStackTop
+    .global     port_switch_flag
+port_IntStack:
+    .space      configISR_STACK_SIZE*portNUM_PROCESSORS		/* This allocates stacks for each individual CPU. */
+port_IntStackTop:
+    .word		0
+port_switch_flag:
+    .space      portNUM_PROCESSORS*4 /* One flag for each individual CPU. */
+
+    .text
+
+/*
+*******************************************************************************
+* _frxt_setup_switch
+* void _frxt_setup_switch(void);
+*
+* Sets an internal flag indicating that a task switch is required on return
+* from interrupt handling.
+*
+*******************************************************************************
+*/
+    .global     _frxt_setup_switch
+    .type       _frxt_setup_switch,@function
+    .align      4
+_frxt_setup_switch:
+
+    ENTRY(16)
+
+	getcoreid a3
+    movi    a2, port_switch_flag
+	addx4	a2,  a3, a2
+
+    movi    a3, 1
+    s32i    a3, a2, 0
+
+    RET(16)
+
+
+
+
+
+
+/*
+*******************************************************************************
+* _frxt_int_enter
+* void _frxt_int_enter(void)
+*
+* Implements the Xtensa RTOS porting layer's XT_RTOS_INT_ENTER function for
+* freeRTOS. Saves the rest of the interrupt context (not already saved).
+* May only be called from assembly code by the 'call0' instruction, with
+* interrupts disabled.
+* See the detailed description of the XT_RTOS_ENTER macro in xtensa_rtos.h.
+*
+*******************************************************************************
+*/
+    .globl  _frxt_int_enter
+    .type   _frxt_int_enter,@function
+    .align  4
+_frxt_int_enter:
+
+    /* Save a12-13 in the stack frame as required by _xt_context_save. */
+    s32i    a12, a1, XT_STK_A12
+    s32i    a13, a1, XT_STK_A13
+
+    /* Save return address in a safe place (free a0). */
+    mov     a12, a0
+
+    /* Save the rest of the interrupted context (preserves A12-13). */
+    call0   _xt_context_save
+
+    /*
+    Save interrupted task's SP in TCB only if not nesting.
+    Manage nesting directly rather than call the generic IntEnter()
+    (in windowed ABI we can't call a C function here anyway because PS.EXCM is still set).
+    */
+	getcoreid a4
+    movi    a2,  port_xSchedulerRunning
+	addx4	a2,  a4, a2
+    movi    a3,  port_interruptNesting
+	addx4	a3,  a4, a3
+    l32i    a2,  a2, 0                  /* a2 = port_xSchedulerRunning     */
+    beqz    a2,  1f                     /* scheduler not running, no tasks */
+    l32i    a2,  a3, 0                  /* a2 = port_interruptNesting      */
+    addi    a2,  a2, 1                  /* increment nesting count         */
+    s32i    a2,  a3, 0                  /* save nesting count              */
+    bnei    a2,  1, .Lnested            /* !=0 before incr, so nested      */
+
+    movi    a2,  pxCurrentTCB
+	addx4	a2,  a4, a2
+    l32i    a2,  a2, 0                  /* a2 = current TCB                */
+    beqz    a2,  1f
+    s32i    a1,  a2, TOPOFSTACK_OFFS    /* pxCurrentTCB->pxTopOfStack = SP */
+    movi    a1,  port_IntStack+configISR_STACK_SIZE   /* a1 = top of intr stack for CPU 0  */
+    movi    a2,  configISR_STACK_SIZE   /* add configISR_STACK_SIZE * cpu_num to arrive at top of stack for cpu_num */
+	mull	a2,  a4, a2
+	add     a1,  a1, a2					/* for current proc */
+
+    #if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0))
+    #ifdef CONFIG_FREERTOS_FPU_IN_ISR
+    #if XCHAL_CP_NUM > 0
+    rsr     a3, CPENABLE                /* Restore thread scope CPENABLE */
+    addi    sp, sp,-4                   /* ISR will manage FPU coprocessor by forcing */
+    s32i    a3, a1, 0                   /* its trigger */
+    #endif
+    #endif
+    #endif /* ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0) */
+
+.Lnested:
+1:
+    #if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0))
+    #ifdef CONFIG_FREERTOS_FPU_IN_ISR
+    #if XCHAL_CP_NUM > 0
+    movi    a3,  0              /* whilst ISRs pending keep CPENABLE exception active */
+    wsr     a3,  CPENABLE
+    rsync
+    #endif
+    #endif
+    #endif /* ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0) */
+
+    mov     a0,  a12                    /* restore return addr and return  */
+    ret
+
+/*
+*******************************************************************************
+* _frxt_int_exit
+* void _frxt_int_exit(void)
+*
+* Implements the Xtensa RTOS porting layer's XT_RTOS_INT_EXIT function for
+* FreeRTOS. If required, calls vPortYieldFromInt() to perform task context
+* switching, restore the (possibly) new task's context, and return to the
+* exit dispatcher saved in the task's stack frame at XT_STK_EXIT.
+* May only be called from assembly code by the 'call0' instruction. Does not
+* return to caller.
+* See the description of the XT_RTOS_ENTER macro in xtensa_rtos.h.
+*
+*******************************************************************************
+*/
+    .globl  _frxt_int_exit
+    .type   _frxt_int_exit,@function
+    .align  4
+_frxt_int_exit:
+
+	getcoreid a4
+    movi    a2,  port_xSchedulerRunning
+	addx4	a2,  a4, a2
+    movi    a3,  port_interruptNesting
+	addx4	a3,  a4, a3
+    rsil    a0,  XCHAL_EXCM_LEVEL       /* lock out interrupts             */
+    l32i    a2,  a2, 0                  /* a2 = port_xSchedulerRunning     */
+    beqz    a2,  .Lnoswitch             /* scheduler not running, no tasks */
+    l32i    a2,  a3, 0                  /* a2 = port_interruptNesting      */
+    addi    a2,  a2, -1                 /* decrement nesting count         */
+    s32i    a2,  a3, 0                  /* save nesting count              */
+    bnez    a2,  .Lnesting              /* !=0 after decr so still nested  */
+
+    #if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0))
+    #ifdef CONFIG_FREERTOS_FPU_IN_ISR
+    #if XCHAL_CP_NUM > 0
+    l32i    a3,  sp, 0                  /* Grab last CPENABLE before leave ISR */
+    addi    sp,  sp, 4
+    wsr     a3, CPENABLE
+    rsync                               /* ensure CPENABLE was modified */
+    #endif
+    #endif
+    #endif /* ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0) */
+
+    movi    a2,  pxCurrentTCB
+	addx4	a2,  a4, a2
+    l32i    a2,  a2, 0                  /* a2 = current TCB                */
+    beqz    a2,  1f                     /* no task ? go to dispatcher      */
+    l32i    a1,  a2, TOPOFSTACK_OFFS    /* SP = pxCurrentTCB->pxTopOfStack */
+
+    movi    a2,  port_switch_flag       /* address of switch flag          */
+	addx4	a2,  a4, a2					/* point to flag for this cpu      */
+    l32i    a3,  a2, 0                  /* a3 = port_switch_flag           */
+    beqz    a3,  .Lnoswitch             /* flag = 0 means no switch reqd   */
+    movi    a3,  0
+    s32i    a3,  a2, 0                  /* zero out the flag for next time */
+
+1:
+    /*
+    Call0 ABI callee-saved regs a12-15 need to be saved before possible preemption.
+    However a12-13 were already saved by _frxt_int_enter().
+    */
+    #ifdef __XTENSA_CALL0_ABI__
+    s32i    a14, a1, XT_STK_A14
+    s32i    a15, a1, XT_STK_A15
+    #endif
+
+    #ifdef __XTENSA_CALL0_ABI__
+    call0   vPortYieldFromInt       /* call dispatch inside the function; never returns */
+    #else
+    call4   vPortYieldFromInt       /* this one returns */
+    call0   _frxt_dispatch          /* tail-call dispatcher */
+    /* Never returns here. */
+    #endif
+
+.Lnoswitch:
+    /*
+    If we came here then about to resume the interrupted task.
+    */
+
+.Lnesting:
+    /*
+    We come here only if there was no context switch, that is if this
+    is a nested interrupt, or the interrupted task was not preempted.
+    In either case there's no need to load the SP.
+    */
+
+    /* Restore full context from interrupt stack frame */
+    call0   _xt_context_restore
+
+    /*
+    Must return via the exit dispatcher corresponding to the entrypoint from which
+    this was called. Interruptee's A0, A1, PS, PC are restored and the interrupt
+    stack frame is deallocated in the exit dispatcher.
+    */
+    l32i    a0,  a1, XT_STK_EXIT
+    ret
+
+
+/*
+**********************************************************************************************************
+*                                           _frxt_timer_int
+*                                      void _frxt_timer_int(void)
+*
+* Implements the Xtensa RTOS porting layer's XT_RTOS_TIMER_INT function for FreeRTOS.
+* Called every timer interrupt.
+* Manages the tick timer and calls xPortSysTickHandler() every tick.
+* See the detailed description of the XT_RTOS_ENTER macro in xtensa_rtos.h.
+*
+* Callable from C (obeys ABI conventions). Implemented in assmebly code for performance.
+*
+**********************************************************************************************************
+*/
+#ifdef CONFIG_FREERTOS_SYSTICK_USES_CCOUNT
+    .globl  _frxt_timer_int
+    .type   _frxt_timer_int,@function
+    .align  4
+_frxt_timer_int:
+
+    /*
+    Xtensa timers work by comparing a cycle counter with a preset value.  Once the match occurs
+    an interrupt is generated, and the handler has to set a new cycle count into the comparator.
+    To avoid clock drift due to interrupt latency, the new cycle count is computed from the old,
+    not the time the interrupt was serviced. However if a timer interrupt is ever serviced more
+    than one tick late, it is necessary to process multiple ticks until the new cycle count is
+    in the future, otherwise the next timer interrupt would not occur until after the cycle
+    counter had wrapped (2^32 cycles later).
+
+    do {
+        ticks++;
+        old_ccompare = read_ccompare_i();
+        write_ccompare_i( old_ccompare + divisor );
+        service one tick;
+        diff = read_ccount() - old_ccompare;
+    } while ( diff > divisor );
+    */
+
+    ENTRY(16)
+
+    #ifdef CONFIG_PM_TRACE
+    movi a6, 1 /* = ESP_PM_TRACE_TICK */
+    getcoreid a7
+    call4 esp_pm_trace_enter
+    #endif // CONFIG_PM_TRACE
+
+.L_xt_timer_int_catchup:
+
+    /* Update the timer comparator for the next tick. */
+    #ifdef XT_CLOCK_FREQ
+    movi    a2, XT_TICK_DIVISOR         /* a2 = comparator increment          */
+    #else
+    movi    a3, _xt_tick_divisor
+    l32i    a2, a3, 0                   /* a2 = comparator increment          */
+    #endif
+    rsr     a3, XT_CCOMPARE             /* a3 = old comparator value          */
+    add     a4, a3, a2                  /* a4 = new comparator value          */
+    wsr     a4, XT_CCOMPARE             /* update comp. and clear interrupt   */
+    esync
+
+    #ifdef __XTENSA_CALL0_ABI__
+    /* Preserve a2 and a3 across C calls. */
+    s32i    a2, sp, 4
+    s32i    a3, sp, 8
+    #endif
+
+    /* Call the FreeRTOS tick handler (see port_systick.c). */
+    #ifdef __XTENSA_CALL0_ABI__
+    call0   xPortSysTickHandler
+    #else
+    call4   xPortSysTickHandler
+    #endif
+
+    #ifdef __XTENSA_CALL0_ABI__
+    /* Restore a2 and a3. */
+    l32i    a2, sp, 4
+    l32i    a3, sp, 8
+    #endif
+
+    /* Check if we need to process more ticks to catch up. */
+    esync                               /* ensure comparator update complete  */
+    rsr     a4, CCOUNT                  /* a4 = cycle count                   */
+    sub     a4, a4, a3                  /* diff = ccount - old comparator     */
+    blt     a2, a4, .L_xt_timer_int_catchup  /* repeat while diff > divisor */
+
+#ifdef CONFIG_PM_TRACE
+    movi a6, 1 /* = ESP_PM_TRACE_TICK */
+    getcoreid a7
+    call4 esp_pm_trace_exit
+#endif // CONFIG_PM_TRACE
+
+    RET(16)
+#endif // CONFIG_FREERTOS_SYSTICK_USES_CCOUNT
+
+    /*
+**********************************************************************************************************
+*                                           _frxt_tick_timer_init
+*                                      void _frxt_tick_timer_init(void)
+*
+* Initialize timer and timer interrrupt handler (_xt_tick_divisor_init() has already been been called).
+* Callable from C (obeys ABI conventions on entry).
+*
+**********************************************************************************************************
+*/
+#ifdef CONFIG_FREERTOS_SYSTICK_USES_CCOUNT
+    .globl  _frxt_tick_timer_init
+    .type   _frxt_tick_timer_init,@function
+    .align  4
+_frxt_tick_timer_init:
+
+    ENTRY(16)
+
+
+    /* Set up the periodic tick timer (assume enough time to complete init). */
+    #ifdef XT_CLOCK_FREQ
+    movi    a3, XT_TICK_DIVISOR
+    #else
+    movi    a2, _xt_tick_divisor
+    l32i    a3, a2, 0
+    #endif
+    rsr     a2, CCOUNT              /* current cycle count */
+    add     a2, a2, a3              /* time of first timer interrupt */
+    wsr     a2, XT_CCOMPARE         /* set the comparator */
+
+    /*
+    Enable the timer interrupt at the device level. Don't write directly
+    to the INTENABLE register because it may be virtualized.
+    */
+    #ifdef __XTENSA_CALL0_ABI__
+    movi    a2, XT_TIMER_INTEN
+    call0   xt_ints_on
+    #else
+    movi    a6, XT_TIMER_INTEN
+    call4   xt_ints_on
+    #endif
+
+    RET(16)
+#endif // CONFIG_FREERTOS_SYSTICK_USES_CCOUNT
+
+/*
+**********************************************************************************************************
+*                                    DISPATCH THE HIGH READY TASK
+*                                     void _frxt_dispatch(void)
+*
+* Switch context to the highest priority ready task, restore its state and dispatch control to it.
+*
+* This is a common dispatcher that acts as a shared exit path for all the context switch functions
+* including vPortYield() and vPortYieldFromInt(), all of which tail-call this dispatcher
+* (for windowed ABI vPortYieldFromInt() calls it indirectly via _frxt_int_exit() ).
+*
+* The Xtensa port uses different stack frames for solicited and unsolicited task suspension (see
+* comments on stack frames in xtensa_context.h). This function restores the state accordingly.
+* If restoring a task that solicited entry, restores the minimal state and leaves CPENABLE clear.
+* If restoring a task that was preempted, restores all state including the task's CPENABLE.
+*
+* Entry:
+*   pxCurrentTCB  points to the TCB of the task to suspend,
+*   Because it is tail-called without a true function entrypoint, it needs no 'entry' instruction.
+*
+* Exit:
+*   If incoming task called vPortYield() (solicited), this function returns as if from vPortYield().
+*   If incoming task was preempted by an interrupt, this function jumps to exit dispatcher.
+*
+**********************************************************************************************************
+*/
+    .globl  _frxt_dispatch
+    .type   _frxt_dispatch,@function
+    .align  4
+_frxt_dispatch:
+
+    #ifdef __XTENSA_CALL0_ABI__
+    call0   vTaskSwitchContext  // Get next TCB to resume
+    movi    a2, pxCurrentTCB
+	getcoreid a3
+	addx4	a2,  a3, a2
+    #else
+    call4   vTaskSwitchContext  // Get next TCB to resume
+    movi    a2, pxCurrentTCB
+	getcoreid a3
+	addx4	a2,  a3, a2
+    #endif
+    l32i    a3,  a2, 0
+    l32i    sp,  a3, TOPOFSTACK_OFFS     /* SP = next_TCB->pxTopOfStack;  */
+    s32i    a3,  a2, 0
+
+    /* Determine the type of stack frame. */
+    l32i    a2,  sp, XT_STK_EXIT        /* exit dispatcher or solicited flag */
+    bnez    a2,  .L_frxt_dispatch_stk
+
+.L_frxt_dispatch_sol:
+
+    /* Solicited stack frame. Restore minimal context and return from vPortYield(). */
+    #if XCHAL_HAVE_THREADPTR
+    l32i    a2,  sp, XT_SOL_THREADPTR
+    wur.threadptr a2
+    #endif
+    l32i    a3,  sp, XT_SOL_PS
+    #ifdef __XTENSA_CALL0_ABI__
+    l32i    a12, sp, XT_SOL_A12
+    l32i    a13, sp, XT_SOL_A13
+    l32i    a14, sp, XT_SOL_A14
+    l32i    a15, sp, XT_SOL_A15
+    #endif
+    l32i    a0,  sp, XT_SOL_PC
+    #if XCHAL_CP_NUM > 0
+    /* Ensure wsr.CPENABLE is complete (should be, it was cleared on entry). */
+    rsync
+    #endif
+    /* As soons as PS is restored, interrupts can happen. No need to sync PS. */
+    wsr     a3,  PS
+    #ifdef __XTENSA_CALL0_ABI__
+    addi    sp,  sp, XT_SOL_FRMSZ
+    ret
+    #else
+    retw
+    #endif
+
+.L_frxt_dispatch_stk:
+
+    #if XCHAL_CP_NUM > 0
+    /* Restore CPENABLE from task's co-processor save area. */
+    movi    a3, pxCurrentTCB            /* cp_state =                       */
+	getcoreid a2
+	addx4	a3,  a2, a3
+    l32i    a3, a3, 0
+    l32i    a2, a3, CP_TOPOFSTACK_OFFS     /* StackType_t                       *pxStack; */
+    l16ui   a3, a2, XT_CPENABLE         /* CPENABLE = cp_state->cpenable;   */
+    wsr     a3, CPENABLE
+    #endif
+
+    /* Interrupt stack frame. Restore full context and return to exit dispatcher. */
+    call0   _xt_context_restore
+
+    /* In Call0 ABI, restore callee-saved regs (A12, A13 already restored). */
+    #ifdef __XTENSA_CALL0_ABI__
+    l32i    a14, sp, XT_STK_A14
+    l32i    a15, sp, XT_STK_A15
+    #endif
+
+    #if XCHAL_CP_NUM > 0
+    /* Ensure wsr.CPENABLE has completed. */
+    rsync
+    #endif
+
+    /*
+    Must return via the exit dispatcher corresponding to the entrypoint from which
+    this was called. Interruptee's A0, A1, PS, PC are restored and the interrupt
+    stack frame is deallocated in the exit dispatcher.
+    */
+    l32i    a0, sp, XT_STK_EXIT
+    ret
+
+
+/*
+**********************************************************************************************************
+*                            PERFORM A SOLICTED CONTEXT SWITCH (from a task)
+*                                        void vPortYield(void)
+*
+* This function saves the minimal state needed for a solicited task suspension, clears CPENABLE,
+* then tail-calls the dispatcher _frxt_dispatch() to perform the actual context switch
+*
+* At Entry:
+*   pxCurrentTCB  points to the TCB of the task to suspend
+*   Callable from C (obeys ABI conventions on entry).
+*
+* Does not return to caller.
+*
+**********************************************************************************************************
+*/
+    .globl  vPortYield
+    .type   vPortYield,@function
+    .align  4
+vPortYield:
+
+    #ifdef __XTENSA_CALL0_ABI__
+    addi    sp,  sp, -XT_SOL_FRMSZ
+    #else
+    entry   sp,  XT_SOL_FRMSZ
+    #endif
+
+    rsr     a2,  PS
+    s32i    a0,  sp, XT_SOL_PC
+    s32i    a2,  sp, XT_SOL_PS
+    #if XCHAL_HAVE_THREADPTR
+    rur.threadptr a2
+    s32i    a2,  sp, XT_SOL_THREADPTR
+    #endif
+    #ifdef __XTENSA_CALL0_ABI__
+    s32i    a12, sp, XT_SOL_A12         /* save callee-saved registers      */
+    s32i    a13, sp, XT_SOL_A13
+    s32i    a14, sp, XT_SOL_A14
+    s32i    a15, sp, XT_SOL_A15
+    #else
+    /* Spill register windows. Calling xthal_window_spill() causes extra    */
+    /* spills and reloads, so we will set things up to call the _nw version */
+    /* instead to save cycles.                                              */
+    movi    a6,  ~(PS_WOE_MASK|PS_INTLEVEL_MASK)  /* spills a4-a7 if needed */
+    and     a2,  a2, a6                           /* clear WOE, INTLEVEL    */
+    addi    a2,  a2, XCHAL_EXCM_LEVEL             /* set INTLEVEL           */
+    wsr     a2,  PS
+    rsync
+    call0   xthal_window_spill_nw
+    l32i    a2,  sp, XT_SOL_PS                    /* restore PS             */
+    wsr     a2,  PS
+    #endif
+
+    rsil    a2,  XCHAL_EXCM_LEVEL       /* disable low/med interrupts       */
+
+    #if XCHAL_CP_NUM > 0
+    /* Save coprocessor callee-saved state (if any). At this point CPENABLE */
+    /* should still reflect which CPs were in use (enabled).                */
+    call0   _xt_coproc_savecs
+    #endif
+
+    movi    a2,  pxCurrentTCB
+	getcoreid a3
+	addx4	a2,  a3, a2
+    l32i    a2,  a2, 0                  /* a2 = pxCurrentTCB                */
+    movi    a3,  0
+    s32i    a3,  sp, XT_SOL_EXIT        /* 0 to flag as solicited frame     */
+    s32i    sp,  a2, TOPOFSTACK_OFFS    /* pxCurrentTCB->pxTopOfStack = SP  */
+
+    #if XCHAL_CP_NUM > 0
+    /* Clear CPENABLE, also in task's co-processor state save area. */
+    l32i    a2,  a2, CP_TOPOFSTACK_OFFS /* a2 = pxCurrentTCB->cp_state      */
+    movi    a3,  0
+    wsr     a3,  CPENABLE
+    beqz    a2,  1f
+    s16i    a3,  a2, XT_CPENABLE        /* clear saved cpenable             */
+1:
+    #endif
+
+    /* Tail-call dispatcher. */
+    call0   _frxt_dispatch
+    /* Never reaches here. */
+
+
+/*
+**********************************************************************************************************
+*                         PERFORM AN UNSOLICITED CONTEXT SWITCH (from an interrupt)
+*                                        void vPortYieldFromInt(void)
+*
+* This calls the context switch hook (removed), saves and clears CPENABLE, then tail-calls the dispatcher
+* _frxt_dispatch() to perform the actual context switch.
+*
+* At Entry:
+*   Interrupted task context has been saved in an interrupt stack frame at pxCurrentTCB->pxTopOfStack.
+*   pxCurrentTCB  points to the TCB of the task to suspend,
+*   Callable from C (obeys ABI conventions on entry).
+*
+* At Exit:
+*   Windowed ABI defers the actual context switch until the stack is unwound to interrupt entry.
+*   Call0 ABI tail-calls the dispatcher directly (no need to unwind) so does not return to caller.
+*
+**********************************************************************************************************
+*/
+    .globl  vPortYieldFromInt
+    .type   vPortYieldFromInt,@function
+    .align  4
+vPortYieldFromInt:
+
+    ENTRY(16)
+
+    #if XCHAL_CP_NUM > 0
+    /* Save CPENABLE in task's co-processor save area, and clear CPENABLE.  */
+    movi    a3, pxCurrentTCB            /* cp_state =                       */
+	getcoreid a2
+	addx4	a3,  a2, a3
+    l32i    a3, a3, 0
+
+    l32i    a2, a3, CP_TOPOFSTACK_OFFS
+
+    rsr     a3, CPENABLE
+    s16i    a3, a2, XT_CPENABLE         /* cp_state->cpenable = CPENABLE;   */
+    movi    a3, 0
+    wsr     a3, CPENABLE                /* disable all co-processors        */
+    #endif
+
+    #ifdef __XTENSA_CALL0_ABI__
+    /* Tail-call dispatcher. */
+    call0   _frxt_dispatch
+    /* Never reaches here. */
+    #else
+    RET(16)
+    #endif
+
+/*
+**********************************************************************************************************
+*                                        _frxt_task_coproc_state
+*                                   void _frxt_task_coproc_state(void)
+*
+* Implements the Xtensa RTOS porting layer's XT_RTOS_CP_STATE function for FreeRTOS.
+*
+* May only be called when a task is running, not within an interrupt handler (returns 0 in that case).
+* May only be called from assembly code by the 'call0' instruction. Does NOT obey ABI conventions.
+* Returns in A15 a pointer to the base of the co-processor state save area for the current task.
+* See the detailed description of the XT_RTOS_ENTER macro in xtensa_rtos.h.
+*
+**********************************************************************************************************
+*/
+#if XCHAL_CP_NUM > 0
+
+    .globl  _frxt_task_coproc_state
+    .type   _frxt_task_coproc_state,@function
+    .align  4
+_frxt_task_coproc_state:
+
+
+	/* We can use a3 as a scratchpad, the instances of code calling XT_RTOS_CP_STATE don't seem to need it saved. */
+	getcoreid a3
+    movi    a15, port_xSchedulerRunning /* if (port_xSchedulerRunning              */
+	addx4	a15, a3,a15
+    l32i    a15, a15, 0
+    beqz    a15, 1f
+    movi    a15, port_interruptNesting  /* && port_interruptNesting == 0           */
+	addx4	a15, a3, a15
+    l32i    a15, a15, 0
+    bnez    a15, 1f
+
+    movi    a15, pxCurrentTCB
+	addx4	a15, a3, a15
+    l32i    a15, a15, 0                 /* && pxCurrentTCB != 0) {                 */
+
+    beqz    a15, 2f
+    l32i    a15, a15, CP_TOPOFSTACK_OFFS
+    ret
+
+1:  movi    a15, 0
+2:  ret
+
+#endif /* XCHAL_CP_NUM > 0 */

kernel/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/portmux_impl.h

@@ -0,0 +1,100 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* This header exists for performance reasons, in order to inline the
+ * implementation of vPortCPUAcquireMutexIntsDisabled and
+ * vPortCPUReleaseMutexIntsDisabled into the
+ * vTaskEnterCritical/vTaskExitCritical functions in task.c as well as the
+ * vPortCPUAcquireMutex/vPortCPUReleaseMutex implementations.
+ *
+ * Normally this kind of performance hack is over the top, but
+ * vTaskEnterCritical/vTaskExitCritical is called a great
+ * deal by FreeRTOS internals.
+ *
+ * It should be #included by freertos port.c or tasks.c, in esp-idf.
+ *
+ * The way it works is that it essentially uses portmux_impl.inc.h as a
+ * generator template of sorts. When no external memory is used, this
+ * template is only used to generate the vPortCPUAcquireMutexIntsDisabledInternal
+ * and vPortCPUReleaseMutexIntsDisabledInternal functions, which use S32C1 to
+ * do an atomic compare & swap. When external memory is used the functions
+ * vPortCPUAcquireMutexIntsDisabledExtram and vPortCPUReleaseMutexIntsDisabledExtram
+ * are also generated, which use uxPortCompareSetExtram to fake the S32C1 instruction.
+ * The wrapper functions vPortCPUAcquireMutexIntsDisabled and
+ * vPortCPUReleaseMutexIntsDisabled will then use the appropriate function to do the
+ * actual lock/unlock.
+ */
+#include "soc/cpu.h"
+#include "portable.h"
+
+/* XOR one core ID with this value to get the other core ID */
+#if (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0))
+#define CORE_ID_XOR_SWAP    ( CORE_ID_PRO ^ CORE_ID_APP )
+#else
+#define CORE_ID_REGVAL_XOR_SWAP (CORE_ID_REGVAL_PRO ^ CORE_ID_REGVAL_APP)
+#endif
+
+
+
+/*Define the mux routines for use with muxes in internal RAM */
+#define PORTMUX_AQUIRE_MUX_FN_NAME     vPortCPUAcquireMutexIntsDisabledInternal
+#define PORTMUX_RELEASE_MUX_FN_NAME    vPortCPUReleaseMutexIntsDisabledInternal
+#define PORTMUX_COMPARE_SET_FN_NAME    uxPortCompareSet
+#include "portmux_impl.inc.h"
+#undef PORTMUX_AQUIRE_MUX_FN_NAME
+#undef PORTMUX_RELEASE_MUX_FN_NAME
+#undef PORTMUX_COMPARE_SET_FN_NAME
+
+
+#if defined( CONFIG_SPIRAM_SUPPORT )
+
+    #define PORTMUX_AQUIRE_MUX_FN_NAME     vPortCPUAcquireMutexIntsDisabledExtram
+    #define PORTMUX_RELEASE_MUX_FN_NAME    vPortCPUReleaseMutexIntsDisabledExtram
+    #define PORTMUX_COMPARE_SET_FN_NAME    uxPortCompareSetExtram
+    #include "portmux_impl.inc.h"
+    #undef PORTMUX_AQUIRE_MUX_FN_NAME
+    #undef PORTMUX_RELEASE_MUX_FN_NAME
+    #undef PORTMUX_COMPARE_SET_FN_NAME
+
+#endif
+
+
+#ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
+    #define PORTMUX_AQUIRE_MUX_FN_ARGS     portMUX_TYPE * mux, int timeout_cycles, const char * fnName, int line
+    #define PORTMUX_RELEASE_MUX_FN_ARGS    portMUX_TYPE * mux, const char * fnName, int line
+    #define PORTMUX_AQUIRE_MUX_FN_CALL_ARGS( x )     x, timeout_cycles, fnName, line
+    #define PORTMUX_RELEASE_MUX_FN_CALL_ARGS( x )    x, fnName, line
+#else
+    #define PORTMUX_AQUIRE_MUX_FN_ARGS     portMUX_TYPE * mux, int timeout_cycles
+    #define PORTMUX_RELEASE_MUX_FN_ARGS    portMUX_TYPE * mux
+    #define PORTMUX_AQUIRE_MUX_FN_CALL_ARGS( x )     x, timeout_cycles
+    #define PORTMUX_RELEASE_MUX_FN_CALL_ARGS( x )    x
+#endif
+
+
+static inline bool __attribute__( ( always_inline ) ) vPortCPUAcquireMutexIntsDisabled( PORTMUX_AQUIRE_MUX_FN_ARGS )
+{
+    #if defined( CONFIG_SPIRAM_SUPPORT )
+        if( esp_ptr_external_ram( mux ) )
+        {
+            return vPortCPUAcquireMutexIntsDisabledExtram( PORTMUX_AQUIRE_MUX_FN_CALL_ARGS( mux ) );
+        }
+    #endif
+    return vPortCPUAcquireMutexIntsDisabledInternal( PORTMUX_AQUIRE_MUX_FN_CALL_ARGS( mux ) );
+}
+
+
+static inline void vPortCPUReleaseMutexIntsDisabled( PORTMUX_RELEASE_MUX_FN_ARGS )
+{
+    #if defined( CONFIG_SPIRAM_SUPPORT )
+        if( esp_ptr_external_ram( mux ) )
+        {
+            vPortCPUReleaseMutexIntsDisabledExtram( PORTMUX_RELEASE_MUX_FN_CALL_ARGS( mux ) );
+            return;
+        }
+    #endif
+    vPortCPUReleaseMutexIntsDisabledInternal( PORTMUX_RELEASE_MUX_FN_CALL_ARGS( mux ) );
+}

kernel/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/portmux_impl.inc.h

@@ -0,0 +1,195 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+
+/*
+ * Warning: funky preprocessor hackery ahead. Including these headers will generate two
+ * functions, which names are defined by the preprocessor macros
+ * PORTMUX_AQUIRE_MUX_FN_NAME and PORTMUX_RELEASE_MUX_FN_NAME. In order to do the compare
+ * and exchange function, they will use whatever PORTMUX_COMPARE_SET_FN_NAME resolves to.
+ *
+ * In some scenarios, this header is included *twice* in portmux_impl.h: one time
+ * for the 'normal' mux code which uses a compare&exchange routine, another time
+ * to generate code for a second set of these routines that use a second mux
+ * (in internal ram) to fake a compare&exchange on a variable in external memory.
+ */
+
+
+
+static inline bool __attribute__( ( always_inline ) )
+#ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
+    PORTMUX_AQUIRE_MUX_FN_NAME( portMUX_TYPE * mux,
+                                int timeout_cycles,
+                                const char * fnName,
+                                int line )
+    {
+#else
+    PORTMUX_AQUIRE_MUX_FN_NAME( portMUX_TYPE * mux, int timeout_cycles )
+    {
+        #endif
+
+
+        #if !CONFIG_FREERTOS_UNICORE
+            uint32_t res;
+            portBASE_TYPE coreID, otherCoreID;
+            uint32_t ccount_start;
+            bool set_timeout = timeout_cycles > portMUX_NO_TIMEOUT;
+            #ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
+                if( !set_timeout )
+                {
+                    timeout_cycles = 10000; /* Always set a timeout in debug mode */
+                    set_timeout = true;
+                }
+            #endif
+
+            if( set_timeout ) /* Timeout */
+            {
+                RSR( CCOUNT, ccount_start );
+            }
+
+            #ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
+                uint32_t owner = mux->owner;
+
+                #if (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0))
+                if( ( owner != portMUX_FREE_VAL ) && ( owner != CORE_ID_PRO ) && ( owner != CORE_ID_APP ) )
+                #else
+                if (owner != portMUX_FREE_VAL && owner != CORE_ID_REGVAL_PRO && owner != CORE_ID_REGVAL_APP)
+                #endif
+                {
+                    ets_printf( "ERROR: vPortCPUAcquireMutex: mux %p is uninitialized (0x%X)! Called from %s line %d.\n", mux, owner, fnName, line );
+                    mux->owner = portMUX_FREE_VAL;
+                }
+            #endif
+
+            /* Spin until we own the core */
+
+            RSR( PRID, coreID );
+
+            /* Note: coreID is the full 32 bit core ID (CORE_ID_PRO/CORE_ID_APP),
+             * not the 0/1 value returned by xPortGetCoreID()
+             */
+            #if (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0))
+            otherCoreID = CORE_ID_XOR_SWAP ^ coreID;
+            #else
+            otherCoreID = CORE_ID_REGVAL_XOR_SWAP ^ coreID;
+            #endif
+
+            do
+            {
+                /* mux->owner should be one of portMUX_FREE_VAL, CORE_ID_PRO,
+                 * CORE_ID_APP:
+                 *
+                 * - If portMUX_FREE_VAL, we want to atomically set to 'coreID'.
+                 * - If "our" coreID, we can drop through immediately.
+                 * - If "otherCoreID", we spin here.
+                 */
+                res = coreID;
+                PORTMUX_COMPARE_SET_FN_NAME( &mux->owner, portMUX_FREE_VAL, &res );
+
+                if( res != otherCoreID )
+                {
+                    break; /* mux->owner is "our" coreID */
+                }
+
+                if( set_timeout )
+                {
+                    uint32_t ccount_now;
+                    RSR( CCOUNT, ccount_now );
+
+                    if( ccount_now - ccount_start > ( unsigned ) timeout_cycles )
+                    {
+                        #ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
+                            ets_printf( "Timeout on mux! last non-recursive lock %s line %d, curr %s line %d\n", mux->lastLockedFn, mux->lastLockedLine, fnName, line );
+                            ets_printf( "Owner 0x%x count %d\n", mux->owner, mux->count );
+                        #endif
+                        return false;
+                    }
+                }
+            } while( 1 );
+
+            assert( res == coreID || res == portMUX_FREE_VAL );           /* any other value implies memory corruption or uninitialized mux */
+            assert( ( res == portMUX_FREE_VAL ) == ( mux->count == 0 ) ); /* we're first to lock iff count is zero */
+            assert( mux->count < 0xFF );                                  /* Bad count value implies memory corruption */
+
+            /* now we own it, we can increment the refcount */
+            mux->count++;
+
+
+            #ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
+                if( res == portMUX_FREE_VAL ) /*initial lock */
+                {
+                    mux->lastLockedFn = fnName;
+                    mux->lastLockedLine = line;
+                }
+                else
+                {
+                    ets_printf( "Recursive lock: count=%d last non-recursive lock %s line %d, curr %s line %d\n", mux->count - 1,
+                                mux->lastLockedFn, mux->lastLockedLine, fnName, line );
+                }
+            #endif /* CONFIG_FREERTOS_PORTMUX_DEBUG */
+        #endif /* CONFIG_FREERTOS_UNICORE */
+        return true;
+    }
+
+#ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
+        static inline void PORTMUX_RELEASE_MUX_FN_NAME( portMUX_TYPE * mux,
+                                                        const char * fnName,
+                                                        int line )
+        {
+#else
+        static inline void PORTMUX_RELEASE_MUX_FN_NAME( portMUX_TYPE * mux )
+        {
+            #endif
+
+
+            #if !CONFIG_FREERTOS_UNICORE
+                portBASE_TYPE coreID;
+                #ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
+                    const char * lastLockedFn = mux->lastLockedFn;
+                    int lastLockedLine = mux->lastLockedLine;
+                    mux->lastLockedFn = fnName;
+                    mux->lastLockedLine = line;
+                    uint32_t owner = mux->owner;
+
+                    #if (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0))
+                    if( ( owner != portMUX_FREE_VAL ) && ( owner != CORE_ID_PRO ) && ( owner != CORE_ID_APP ) )
+                    #else
+                    if (owner != portMUX_FREE_VAL && owner != CORE_ID_REGVAL_PRO && owner != CORE_ID_REGVAL_APP)
+                    #endif
+                    {
+                        ets_printf( "ERROR: vPortCPUReleaseMutex: mux %p is invalid (0x%x)!\n", mux, mux->owner );
+                    }
+                #endif /* ifdef CONFIG_FREERTOS_PORTMUX_DEBUG */
+
+                #if CONFIG_FREERTOS_PORTMUX_DEBUG || !defined( NDEBUG )
+                    RSR( PRID, coreID );
+                #endif
+
+                #ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
+                    if( coreID != mux->owner )
+                    {
+                        ets_printf( "ERROR: vPortCPUReleaseMutex: mux %p was already unlocked!\n", mux );
+                        ets_printf( "Last non-recursive unlock %s line %d, curr unlock %s line %d\n", lastLockedFn, lastLockedLine, fnName, line );
+                    }
+                #endif
+
+                assert( coreID == mux->owner ); /* This is a mutex we didn't lock, or it's corrupt */
+
+                mux->count--;
+
+                if( mux->count == 0 )
+                {
+                    mux->owner = portMUX_FREE_VAL;
+                }
+                else
+                {
+                    assert( mux->count < 0x100 ); /* Indicates memory corruption */
+                    #ifdef CONFIG_FREERTOS_PORTMUX_DEBUG_RECURSIVE
+                        ets_printf( "Recursive unlock: count=%d last locked %s line %d, curr %s line %d\n", mux->count, lastLockedFn, lastLockedLine, fnName, line );
+                    #endif
+                }
+            #endif //!CONFIG_FREERTOS_UNICORE
+        }

kernel/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_context.S

@@ -0,0 +1,712 @@
+/*
+ * SPDX-FileCopyrightText: 2015-2019 Cadence Design Systems, Inc.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD
+ */
+/*
+ * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*******************************************************************************
+
+        XTENSA CONTEXT SAVE AND RESTORE ROUTINES
+
+Low-level Call0 functions for handling generic context save and restore of
+registers not specifically addressed by the interrupt vectors and handlers.
+Those registers (not handled by these functions) are PC, PS, A0, A1 (SP).
+Except for the calls to RTOS functions, this code is generic to Xtensa.
+
+Note that in Call0 ABI, interrupt handlers are expected to preserve the callee-
+save regs (A12-A15), which is always the case if the handlers are coded in C.
+However A12, A13 are made available as scratch registers for interrupt dispatch
+code, so are presumed saved anyway, and are always restored even in Call0 ABI.
+Only A14, A15 are truly handled as callee-save regs.
+
+Because Xtensa is a configurable architecture, this port supports all user
+generated configurations (except restrictions stated in the release notes).
+This is accomplished by conditional compilation using macros and functions
+defined in the Xtensa HAL (hardware adaptation layer) for your configuration.
+Only the processor state included in your configuration is saved and restored,
+including any processor state added by user configuration options or TIE.
+
+*******************************************************************************/
+
+/*  Warn nicely if this file gets named with a lowercase .s instead of .S:  */
+#define NOERROR #
+NOERROR: .error "C preprocessor needed for this file: make sure its filename\
+ ends in uppercase .S, or use xt-xcc's -x assembler-with-cpp option."
+
+
+#include "xtensa_rtos.h"
+#include "xtensa_context.h"
+#include "esp_idf_version.h"
+#if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0))
+#include "xt_asm_utils.h"
+#endif
+
+#ifdef XT_USE_OVLY
+#include <xtensa/overlay_os_asm.h>
+#endif
+
+    .text
+
+/*******************************************************************************
+
+_xt_context_save
+
+    !! MUST BE CALLED ONLY BY 'CALL0' INSTRUCTION !!
+
+Saves all Xtensa processor state except PC, PS, A0, A1 (SP), A12, A13, in the
+interrupt stack frame defined in xtensa_rtos.h.
+Its counterpart is _xt_context_restore (which also restores A12, A13).
+
+Caller is expected to have saved PC, PS, A0, A1 (SP), A12, A13 in the frame.
+This function preserves A12 & A13 in order to provide the caller with 2 scratch
+regs that need not be saved over the call to this function. The choice of which
+2 regs to provide is governed by xthal_window_spill_nw and xthal_save_extra_nw,
+to avoid moving data more than necessary. Caller can assign regs accordingly.
+
+Entry Conditions:
+    A0  = Return address in caller.
+    A1  = Stack pointer of interrupted thread or handler ("interruptee").
+    Original A12, A13 have already been saved in the interrupt stack frame.
+    Other processor state except PC, PS, A0, A1 (SP), A12, A13, is as at the
+    point of interruption.
+    If windowed ABI, PS.EXCM = 1 (exceptions disabled).
+
+Exit conditions:
+    A0  = Return address in caller.
+    A1  = Stack pointer of interrupted thread or handler ("interruptee").
+    A12, A13 as at entry (preserved).
+    If windowed ABI, PS.EXCM = 1 (exceptions disabled).
+
+*******************************************************************************/
+
+    .global _xt_context_save
+    .type   _xt_context_save,@function
+    .align  4
+	.literal_position
+    .align  4
+
+_xt_context_save:
+
+    s32i    a2,  sp, XT_STK_A2
+    s32i    a3,  sp, XT_STK_A3
+    s32i    a4,  sp, XT_STK_A4
+    s32i    a5,  sp, XT_STK_A5
+    s32i    a6,  sp, XT_STK_A6
+    s32i    a7,  sp, XT_STK_A7
+    s32i    a8,  sp, XT_STK_A8
+    s32i    a9,  sp, XT_STK_A9
+    s32i    a10, sp, XT_STK_A10
+    s32i    a11, sp, XT_STK_A11
+
+    /*
+    Call0 ABI callee-saved regs a12-15 do not need to be saved here.
+    a12-13 are the caller's responsibility so it can use them as scratch.
+    So only need to save a14-a15 here for Windowed ABI (not Call0).
+    */
+    #ifndef __XTENSA_CALL0_ABI__
+    s32i    a14, sp, XT_STK_A14
+    s32i    a15, sp, XT_STK_A15
+    #endif
+
+    rsr     a3,  SAR
+    s32i    a3,  sp, XT_STK_SAR
+
+    #if XCHAL_HAVE_LOOPS
+    rsr     a3,  LBEG
+    s32i    a3,  sp, XT_STK_LBEG
+    rsr     a3,  LEND
+    s32i    a3,  sp, XT_STK_LEND
+    rsr     a3,  LCOUNT
+    s32i    a3,  sp, XT_STK_LCOUNT
+    #endif
+
+    #ifdef XT_USE_SWPRI
+    /* Save virtual priority mask */
+    movi    a3,  _xt_vpri_mask
+    l32i    a3,  a3, 0
+    s32i    a3,  sp, XT_STK_VPRI
+    #endif
+
+    #if XCHAL_EXTRA_SA_SIZE > 0 || !defined(__XTENSA_CALL0_ABI__)
+    mov     a9,  a0                     /* preserve ret addr */
+    #endif
+
+    #if (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0))
+    #ifndef __XTENSA_CALL0_ABI__
+    /*
+    To spill the reg windows, temp. need pre-interrupt stack ptr and a4-15.
+    Need to save a9,12,13 temporarily (in frame temps) and recover originals.
+    Interrupts need to be disabled below XCHAL_EXCM_LEVEL and window overflow
+    and underflow exceptions disabled (assured by PS.EXCM == 1).
+    */
+    s32i    a12, sp, XT_STK_TMP0        /* temp. save stuff in stack frame */
+    s32i    a13, sp, XT_STK_TMP1
+    s32i    a9,  sp, XT_STK_TMP2
+
+    /*
+    Save the overlay state if we are supporting overlays. Since we just saved
+    three registers, we can conveniently use them here. Note that as of now,
+    overlays only work for windowed calling ABI.
+    */
+    #ifdef XT_USE_OVLY
+    l32i    a9,  sp, XT_STK_PC          /* recover saved PC */
+    _xt_overlay_get_state    a9, a12, a13
+    s32i    a9,  sp, XT_STK_OVLY        /* save overlay state */
+    #endif
+
+    l32i    a12, sp, XT_STK_A12         /* recover original a9,12,13 */
+    l32i    a13, sp, XT_STK_A13
+    l32i    a9,  sp, XT_STK_A9
+    addi    sp,  sp, XT_STK_FRMSZ       /* restore the interruptee's SP */
+    call0   xthal_window_spill_nw       /* preserves only a4,5,8,9,12,13 */
+    addi    sp,  sp, -XT_STK_FRMSZ
+    l32i    a12, sp, XT_STK_TMP0        /* recover stuff from stack frame */
+    l32i    a13, sp, XT_STK_TMP1
+    l32i    a9,  sp, XT_STK_TMP2
+    #endif
+    #endif /* (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0)) */
+
+    #if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0))
+    s32i    a12, sp, XT_STK_TMP0        /* temp. save stuff in stack frame */
+    s32i    a13, sp, XT_STK_TMP1
+    s32i    a9,  sp, XT_STK_TMP2
+
+    l32i    a12, sp, XT_STK_A12         /* recover original a9,12,13 */
+    l32i    a13, sp, XT_STK_A13
+    l32i    a9,  sp, XT_STK_A9
+    #endif
+
+    #if XCHAL_EXTRA_SA_SIZE > 0
+    addi    a2,  sp, XT_STK_EXTRA       /* where to save it */
+    # if XCHAL_EXTRA_SA_ALIGN > 16
+    movi    a3, -XCHAL_EXTRA_SA_ALIGN
+    and     a2, a2, a3                  /* align dynamically >16 bytes */
+    # endif
+    call0   xthal_save_extra_nw         /* destroys a0,2,3 */
+    #endif
+
+    #if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0))
+    #ifndef __XTENSA_CALL0_ABI__
+    #ifdef XT_USE_OVLY
+    l32i    a9,  sp, XT_STK_PC          /* recover saved PC */
+    _xt_overlay_get_state    a9, a12, a13
+    s32i    a9,  sp, XT_STK_OVLY        /* save overlay state */
+    #endif
+
+    /* SPILL_ALL_WINDOWS macro requires window overflow exceptions to be enabled,
+     * i.e. PS.EXCM cleared and PS.WOE set.
+     * Since we are going to clear PS.EXCM, we also need to increase INTLEVEL
+     * at least to XCHAL_EXCM_LEVEL. This matches that value of effective INTLEVEL
+     * at entry (CINTLEVEL=max(PS.INTLEVEL, XCHAL_EXCM_LEVEL) when PS.EXCM is set.
+     * Since WindowOverflow exceptions will trigger inside SPILL_ALL_WINDOWS,
+     * need to save/restore EPC1 as well.
+     * Note: even though a4-a15 are saved into the exception frame, we should not
+     * clobber them until after SPILL_ALL_WINDOWS. This is because these registers
+     * may contain live windows belonging to previous frames in the call stack.
+     * These frames will be spilled by SPILL_ALL_WINDOWS, and if the register was
+     * used as a temporary by this code, the temporary value would get stored
+     * onto the stack, instead of the real value.
+     */
+    rsr     a2, PS                     /* to be restored after SPILL_ALL_WINDOWS */
+    movi    a0, PS_INTLEVEL_MASK
+    and     a3, a2, a0                 /* get the current INTLEVEL */
+    bgeui   a3, XCHAL_EXCM_LEVEL, 1f   /* calculate max(INTLEVEL, XCHAL_EXCM_LEVEL) */
+    movi    a3, XCHAL_EXCM_LEVEL
+1:
+    movi    a0, PS_UM | PS_WOE         /* clear EXCM, enable window overflow, set new INTLEVEL */
+    or      a3, a3, a0
+    wsr     a3, ps
+    rsr     a0, EPC1                   /* to be restored after SPILL_ALL_WINDOWS */
+
+    addi    sp,  sp, XT_STK_FRMSZ      /* restore the interruptee's SP */
+    SPILL_ALL_WINDOWS
+    addi    sp,  sp, -XT_STK_FRMSZ     /* return the current stack pointer and proceed with context save*/
+
+
+    wsr     a2, PS                     /* restore to the value at entry */
+    rsync
+    wsr     a0, EPC1                   /* likewise */
+
+    #endif /* __XTENSA_CALL0_ABI__ */
+
+    l32i    a12, sp, XT_STK_TMP0        /* restore the temp saved registers */
+    l32i    a13, sp, XT_STK_TMP1        /* our return address is there */
+    l32i    a9,  sp, XT_STK_TMP2
+    #endif /* ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0) */
+
+    #if XCHAL_EXTRA_SA_SIZE > 0 || !defined(__XTENSA_CALL0_ABI__)
+    mov     a0, a9                      /* retrieve ret addr */
+    #endif
+
+    ret
+
+/*******************************************************************************
+
+_xt_context_restore
+
+    !! MUST BE CALLED ONLY BY 'CALL0' INSTRUCTION !!
+
+Restores all Xtensa processor state except PC, PS, A0, A1 (SP) (and in Call0
+ABI, A14, A15 which are preserved by all interrupt handlers) from an interrupt
+stack frame defined in xtensa_rtos.h .
+Its counterpart is _xt_context_save (whose caller saved A12, A13).
+
+Caller is responsible to restore PC, PS, A0, A1 (SP).
+
+Entry Conditions:
+    A0  = Return address in caller.
+    A1  = Stack pointer of interrupted thread or handler ("interruptee").
+
+Exit conditions:
+    A0  = Return address in caller.
+    A1  = Stack pointer of interrupted thread or handler ("interruptee").
+    Other processor state except PC, PS, A0, A1 (SP), is as at the point
+    of interruption.
+
+*******************************************************************************/
+
+    .global _xt_context_restore
+    .type   _xt_context_restore,@function
+    .align  4
+	.literal_position
+    .align  4
+_xt_context_restore:
+
+    #if XCHAL_EXTRA_SA_SIZE > 0
+    /*
+    NOTE: Normally the xthal_restore_extra_nw macro only affects address
+    registers a2-a5. It is theoretically possible for Xtensa processor
+    designers to write TIE that causes more address registers to be
+    affected, but it is generally unlikely. If that ever happens,
+    more registers need to be saved/restored around this macro invocation.
+    Here we only assume a13 is preserved.
+    Future Xtensa tools releases might limit the regs that can be affected.
+    */
+    mov     a13, a0                     /* preserve ret addr */
+    addi    a2,  sp, XT_STK_EXTRA       /* where to find it */
+    # if XCHAL_EXTRA_SA_ALIGN > 16
+    movi    a3, -XCHAL_EXTRA_SA_ALIGN
+    and     a2, a2, a3                  /* align dynamically >16 bytes */
+    # endif
+    call0   xthal_restore_extra_nw      /* destroys a0,2,3,4,5 */
+    mov     a0,  a13                    /* retrieve ret addr */
+    #endif
+
+    #if XCHAL_HAVE_LOOPS
+    l32i    a2,  sp, XT_STK_LBEG
+    l32i    a3,  sp, XT_STK_LEND
+    wsr     a2,  LBEG
+    l32i    a2,  sp, XT_STK_LCOUNT
+    wsr     a3,  LEND
+    wsr     a2,  LCOUNT
+    #endif
+
+    #ifdef XT_USE_OVLY
+    /*
+    If we are using overlays, this is a good spot to check if we need
+    to restore an overlay for the incoming task. Here we have a bunch
+    of registers to spare. Note that this step is going to use a few
+    bytes of storage below SP (SP-20 to SP-32) if an overlay is going
+    to be restored.
+    */
+    l32i    a2,  sp, XT_STK_PC          /* retrieve PC */
+    l32i    a3,  sp, XT_STK_PS          /* retrieve PS */
+    l32i    a4,  sp, XT_STK_OVLY        /* retrieve overlay state */
+    l32i    a5,  sp, XT_STK_A1          /* retrieve stack ptr */
+    _xt_overlay_check_map    a2, a3, a4, a5, a6
+    s32i    a2,  sp, XT_STK_PC          /* save updated PC */
+    s32i    a3,  sp, XT_STK_PS          /* save updated PS */
+    #endif
+
+    #ifdef XT_USE_SWPRI
+    /* Restore virtual interrupt priority and interrupt enable */
+    movi    a3,  _xt_intdata
+    l32i    a4,  a3, 0                  /* a4 = _xt_intenable */
+    l32i    a5,  sp, XT_STK_VPRI        /* a5 = saved _xt_vpri_mask */
+    and     a4,  a4, a5
+    wsr     a4,  INTENABLE              /* update INTENABLE */
+    s32i    a5,  a3, 4                  /* restore _xt_vpri_mask */
+    #endif
+
+    l32i    a3,  sp, XT_STK_SAR
+    l32i    a2,  sp, XT_STK_A2
+    wsr     a3,  SAR
+    l32i    a3,  sp, XT_STK_A3
+    l32i    a4,  sp, XT_STK_A4
+    l32i    a5,  sp, XT_STK_A5
+    l32i    a6,  sp, XT_STK_A6
+    l32i    a7,  sp, XT_STK_A7
+    l32i    a8,  sp, XT_STK_A8
+    l32i    a9,  sp, XT_STK_A9
+    l32i    a10, sp, XT_STK_A10
+    l32i    a11, sp, XT_STK_A11
+
+    /*
+    Call0 ABI callee-saved regs a12-15 do not need to be restored here.
+    However a12-13 were saved for scratch before XT_RTOS_INT_ENTER(),
+    so need to be restored anyway, despite being callee-saved in Call0.
+    */
+    l32i    a12, sp, XT_STK_A12
+    l32i    a13, sp, XT_STK_A13
+    #ifndef __XTENSA_CALL0_ABI__
+    l32i    a14, sp, XT_STK_A14
+    l32i    a15, sp, XT_STK_A15
+    #endif
+
+    ret
+
+
+/*******************************************************************************
+
+_xt_coproc_init
+
+Initializes global co-processor management data, setting all co-processors
+to "unowned". Leaves CPENABLE as it found it (does NOT clear it).
+
+Called during initialization of the RTOS, before any threads run.
+
+This may be called from normal Xtensa single-threaded application code which
+might use co-processors. The Xtensa run-time initialization enables all
+co-processors. They must remain enabled here, else a co-processor exception
+might occur outside of a thread, which the exception handler doesn't expect.
+
+Entry Conditions:
+    Xtensa single-threaded run-time environment is in effect.
+    No thread is yet running.
+
+Exit conditions:
+    None.
+
+Obeys ABI conventions per prototype:
+    void _xt_coproc_init(void)
+
+*******************************************************************************/
+
+#if XCHAL_CP_NUM > 0
+
+    .global _xt_coproc_init
+    .type   _xt_coproc_init,@function
+    .align  4
+	.literal_position
+    .align  4
+_xt_coproc_init:
+    ENTRY0
+
+    /* Initialize thread co-processor ownerships to 0 (unowned). */
+    movi    a2, _xt_coproc_owner_sa         /* a2 = base of owner array */
+    addi    a3, a2, (XCHAL_CP_MAX*portNUM_PROCESSORS) << 2       /* a3 = top+1 of owner array */
+    movi    a4, 0                           /* a4 = 0 (unowned) */
+1:  s32i    a4, a2, 0
+    addi    a2, a2, 4
+    bltu    a2, a3, 1b
+
+    RET0
+
+#endif
+
+
+/*******************************************************************************
+
+_xt_coproc_release
+
+Releases any and all co-processors owned by a given thread. The thread is
+identified by it's co-processor state save area defined in xtensa_context.h .
+
+Must be called before a thread's co-proc save area is deleted to avoid
+memory corruption when the exception handler tries to save the state.
+May be called when a thread terminates or completes but does not delete
+the co-proc save area, to avoid the exception handler having to save the
+thread's co-proc state before another thread can use it (optimization).
+
+Needs to be called on the processor the thread was running on. Unpinned threads
+won't have an entry here because they get pinned as soon they use a coprocessor.
+
+Entry Conditions:
+    A2  = Pointer to base of co-processor state save area.
+
+Exit conditions:
+    None.
+
+Obeys ABI conventions per prototype:
+    void _xt_coproc_release(void * coproc_sa_base)
+
+*******************************************************************************/
+
+#if XCHAL_CP_NUM > 0
+
+    .global _xt_coproc_release
+    .type   _xt_coproc_release,@function
+    .align  4
+	.literal_position
+    .align  4
+_xt_coproc_release:
+    ENTRY0                                  /* a2 = base of save area */
+
+	getcoreid a5
+	movi    a3, XCHAL_CP_MAX << 2
+	mull    a5, a5, a3
+    movi    a3, _xt_coproc_owner_sa         /* a3 = base of owner array */
+	add     a3, a3, a5
+
+    addi    a4, a3, XCHAL_CP_MAX << 2       /* a4 = top+1 of owner array */
+    movi    a5, 0                           /* a5 = 0 (unowned) */
+
+    rsil    a6, XCHAL_EXCM_LEVEL            /* lock interrupts */
+
+1:  l32i    a7, a3, 0                       /* a7 = owner at a3 */
+    bne     a2, a7, 2f                      /* if (coproc_sa_base == owner) */
+    s32i    a5, a3, 0                       /*   owner = unowned */
+2:  addi    a3, a3, 1<<2                    /* a3 = next entry in owner array */
+    bltu    a3, a4, 1b                      /* repeat until end of array */
+
+3:  wsr     a6, PS                          /* restore interrupts */
+
+    RET0
+
+#endif
+
+
+/*******************************************************************************
+_xt_coproc_savecs
+
+If there is a current thread and it has a coprocessor state save area, then
+save all callee-saved state into this area. This function is called from the
+solicited context switch handler. It calls a system-specific function to get
+the coprocessor save area base address.
+
+Entry conditions:
+    - The thread being switched out is still the current thread.
+    - CPENABLE state reflects which coprocessors are active.
+    - Registers have been saved/spilled already.
+
+Exit conditions:
+    - All necessary CP callee-saved state has been saved.
+    - Registers a2-a7, a13-a15 have been trashed.
+
+Must be called from assembly code only, using CALL0.
+*******************************************************************************/
+#if XCHAL_CP_NUM > 0
+
+    .extern     _xt_coproc_sa_offset   /* external reference */
+
+    .global     _xt_coproc_savecs
+    .type       _xt_coproc_savecs,@function
+    .align  4
+	.literal_position
+    .align      4
+_xt_coproc_savecs:
+
+    /* At entry, CPENABLE should be showing which CPs are enabled. */
+
+    rsr     a2, CPENABLE                /* a2 = which CPs are enabled      */
+    beqz    a2, .Ldone                  /* quick exit if none              */
+    mov     a14, a0                     /* save return address             */
+    call0   XT_RTOS_CP_STATE            /* get address of CP save area     */
+    mov     a0, a14                     /* restore return address          */
+    beqz    a15, .Ldone                 /* if none then nothing to do      */
+    s16i    a2, a15, XT_CP_CS_ST        /* save mask of CPs being stored   */
+    movi    a13, _xt_coproc_sa_offset   /* array of CP save offsets        */
+    l32i    a15, a15, XT_CP_ASA         /* a15 = base of aligned save area */
+
+#if XCHAL_CP0_SA_SIZE
+    bbci.l  a2, 0, 2f                   /* CP 0 not enabled                */
+    l32i    a14, a13, 0                 /* a14 = _xt_coproc_sa_offset[0]   */
+    add     a3, a14, a15                /* a3 = save area for CP 0         */
+    xchal_cp0_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+#if XCHAL_CP1_SA_SIZE
+    bbci.l  a2, 1, 2f                   /* CP 1 not enabled                */
+    l32i    a14, a13, 4                 /* a14 = _xt_coproc_sa_offset[1]   */
+    add     a3, a14, a15                /* a3 = save area for CP 1         */
+    xchal_cp1_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+#if XCHAL_CP2_SA_SIZE
+    bbci.l  a2, 2, 2f
+    l32i    a14, a13, 8
+    add     a3, a14, a15
+    xchal_cp2_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+#if XCHAL_CP3_SA_SIZE
+    bbci.l  a2, 3, 2f
+    l32i    a14, a13, 12
+    add     a3, a14, a15
+    xchal_cp3_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+#if XCHAL_CP4_SA_SIZE
+    bbci.l  a2, 4, 2f
+    l32i    a14, a13, 16
+    add     a3, a14, a15
+    xchal_cp4_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+#if XCHAL_CP5_SA_SIZE
+    bbci.l  a2, 5, 2f
+    l32i    a14, a13, 20
+    add     a3, a14, a15
+    xchal_cp5_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+#if XCHAL_CP6_SA_SIZE
+    bbci.l  a2, 6, 2f
+    l32i    a14, a13, 24
+    add     a3, a14, a15
+    xchal_cp6_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+#if XCHAL_CP7_SA_SIZE
+    bbci.l  a2, 7, 2f
+    l32i    a14, a13, 28
+    add     a3, a14, a15
+    xchal_cp7_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+.Ldone:
+    ret
+#endif
+
+
+/*******************************************************************************
+_xt_coproc_restorecs
+
+Restore any callee-saved coprocessor state for the incoming thread.
+This function is called from coprocessor exception handling, when giving
+ownership to a thread that solicited a context switch earlier. It calls a
+system-specific function to get the coprocessor save area base address.
+
+Entry conditions:
+    - The incoming thread is set as the current thread.
+    - CPENABLE is set up correctly for all required coprocessors.
+    - a2 = mask of coprocessors to be restored.
+
+Exit conditions:
+    - All necessary CP callee-saved state has been restored.
+    - CPENABLE - unchanged.
+    - Registers a2-a7, a13-a15 have been trashed.
+
+Must be called from assembly code only, using CALL0.
+*******************************************************************************/
+#if XCHAL_CP_NUM > 0
+
+    .global     _xt_coproc_restorecs
+    .type       _xt_coproc_restorecs,@function
+    .align  4
+	.literal_position
+    .align      4
+_xt_coproc_restorecs:
+
+    mov     a14, a0                     /* save return address             */
+    call0   XT_RTOS_CP_STATE            /* get address of CP save area     */
+    mov     a0, a14                     /* restore return address          */
+    beqz    a15, .Ldone2                /* if none then nothing to do      */
+    l16ui   a3, a15, XT_CP_CS_ST        /* a3 = which CPs have been saved  */
+    xor     a3, a3, a2                  /* clear the ones being restored   */
+    s32i    a3, a15, XT_CP_CS_ST        /* update saved CP mask            */
+    movi    a13, _xt_coproc_sa_offset   /* array of CP save offsets        */
+    l32i    a15, a15, XT_CP_ASA         /* a15 = base of aligned save area */
+
+#if XCHAL_CP0_SA_SIZE
+    bbci.l  a2, 0, 2f                   /* CP 0 not enabled                */
+    l32i    a14, a13, 0                 /* a14 = _xt_coproc_sa_offset[0]   */
+    add     a3, a14, a15                /* a3 = save area for CP 0         */
+    xchal_cp0_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+#if XCHAL_CP1_SA_SIZE
+    bbci.l  a2, 1, 2f                   /* CP 1 not enabled                */
+    l32i    a14, a13, 4                 /* a14 = _xt_coproc_sa_offset[1]   */
+    add     a3, a14, a15                /* a3 = save area for CP 1         */
+    xchal_cp1_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+#if XCHAL_CP2_SA_SIZE
+    bbci.l  a2, 2, 2f
+    l32i    a14, a13, 8
+    add     a3, a14, a15
+    xchal_cp2_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+#if XCHAL_CP3_SA_SIZE
+    bbci.l  a2, 3, 2f
+    l32i    a14, a13, 12
+    add     a3, a14, a15
+    xchal_cp3_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+#if XCHAL_CP4_SA_SIZE
+    bbci.l  a2, 4, 2f
+    l32i    a14, a13, 16
+    add     a3, a14, a15
+    xchal_cp4_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+#if XCHAL_CP5_SA_SIZE
+    bbci.l  a2, 5, 2f
+    l32i    a14, a13, 20
+    add     a3, a14, a15
+    xchal_cp5_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+#if XCHAL_CP6_SA_SIZE
+    bbci.l  a2, 6, 2f
+    l32i    a14, a13, 24
+    add     a3, a14, a15
+    xchal_cp6_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+#if XCHAL_CP7_SA_SIZE
+    bbci.l  a2, 7, 2f
+    l32i    a14, a13, 28
+    add     a3, a14, a15
+    xchal_cp7_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+.Ldone2:
+    ret
+
+#endif
+
+

kernel/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_init.c

@@ -0,0 +1,75 @@
+/*
+ * SPDX-FileCopyrightText: 2015-2019 Cadence Design Systems, Inc.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD
+ */
+/*
+ * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*******************************************************************************
+*
+*       XTENSA INITIALIZATION ROUTINES CODED IN C
+*
+*  This file contains miscellaneous Xtensa RTOS-generic initialization functions
+*  that are implemented in C.
+*
+*******************************************************************************/
+
+
+#ifdef XT_BOARD
+#include "xtensa/xtbsp.h"
+#endif
+
+#include "xtensa_rtos.h"
+#include "sdkconfig.h"
+#include "esp_idf_version.h"
+#if (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0))
+#include    "esp_clk.h"
+#else
+#if CONFIG_IDF_TARGET_ESP32
+#include "esp32/clk.h"
+#elif CONFIG_IDF_TARGET_ESP32S2
+#include "esp32s2/clk.h"
+#elif CONFIG_IDF_TARGET_ESP32S3
+#include "esp32s3/clk.h"
+#endif
+#endif /* ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0) */
+
+#ifdef XT_RTOS_TIMER_INT
+
+unsigned _xt_tick_divisor = 0;  /* cached number of cycles per tick */
+
+void _xt_tick_divisor_init(void)
+{
+    _xt_tick_divisor = esp_clk_cpu_freq() / XT_TICK_PER_SEC;
+}
+
+/* Deprecated, to be removed */
+int xt_clock_freq(void)
+{
+    return esp_clk_cpu_freq();
+}
+
+#endif /* XT_RTOS_TIMER_INT */

kernel/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_loadstore_handler.S

@@ -0,0 +1,549 @@
+/*
+ * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ *  LoadStoreErrorCause:     Occurs when trying to access 32 bit addressable memory region as 8 bit or 16 bit
+ *  LoadStoreAlignmentCause: Occurs when trying to access in an unaligned manner
+ *
+ *          xxxx xxxx = imm8 field
+ *               yyyy = imm4 field
+ *               ssss = s field
+ *               tttt = t field
+ *
+ *                            16                0
+ *                            -------------------
+ *          L32I.N            yyyy ssss tttt 1000
+ *          S32I.N            yyyy ssss tttt 1001
+ *
+ *                  23                          0
+ *                  -----------------------------
+ *          L8UI    xxxx xxxx 0000 ssss tttt 0010               <- LoadStoreError
+ *          L16UI   xxxx xxxx 0001 ssss tttt 0010               <- LoadStoreError, LoadStoreAlignment
+ *          L16SI   xxxx xxxx 1001 ssss tttt 0010               <- LoadStoreError, LoadStoreAlignment
+ *          L32I    xxxx xxxx 0010 ssss tttt 0010               <- LoadStoreAlignment
+ *
+ *          S8I     xxxx xxxx 0100 ssss tttt 0010               <- LoadStoreError
+ *          S16I    xxxx xxxx 0101 ssss tttt 0010               <- LoadStoreError, LoadStoreAlignment
+ *          S32I    xxxx xxxx 0110 ssss tttt 0010               <- LoadStoreAlignment
+ *
+ *                   ******* UNSUPPORTED *******
+ *
+ *          L32E    0000 1001 rrrr ssss tttt 0000
+ *          S32E    0100 1001 rrrr ssss tttt 0000
+ *                  -----------------------------
+ */
+
+#include "xtensa_rtos.h"
+#include "sdkconfig.h"
+#include "soc/soc.h"
+
+#define LOADSTORE_HANDLER_STACK_SZ      8
+    .section .bss, "aw"
+    .balign 16
+LoadStoreHandlerStack:
+    .rept LOADSTORE_HANDLER_STACK_SZ
+    .word 0
+    .endr
+
+
+/* LoadStoreErrorCause handler:
+ *
+ * Completes 8-bit or 16-bit load/store instructions from 32-bit aligned memory region
+ * Called from UserExceptionVector if EXCCAUSE is LoadStoreErrorCause
+ */
+
+    .global   LoadStoreErrorHandler
+    .section .iram1, "ax"
+
+    .literal_position
+
+    .balign 4
+LoadStoreErrorHandler:
+    .type   LoadStoreErrorHandler, @function
+
+    wsr     a0, depc                            // Save return address in depc
+    mov     a0, sp
+    movi    sp, LoadStoreHandlerStack
+    s32i    a0, sp, 0x04                        // Since a0 contains value of a1
+    s32i    a2, sp, 0x08
+    s32i    a3, sp, 0x0c
+    s32i    a4, sp, 0x10
+
+    rsr     a0, sar                             // Save SAR in a0 to restore later
+
+    /* Check whether the address lies in the valid range */
+    rsr     a3, excvaddr
+    movi    a4, _iram_text_end                  // End of code section of IRAM
+    bge     a3, a4, 1f
+    movi    a4, SOC_CACHE_APP_LOW               // Check if in APP cache region
+    blt     a3, a4, .LS_wrong_opcode
+    movi    a4, SOC_CACHE_APP_HIGH
+    bge     a3, a4, .LS_wrong_opcode
+    j       2f
+
+1:
+    movi    a4, SOC_IRAM_HIGH                   // End of IRAM address range
+    bge     a3, a4, .LS_wrong_opcode
+
+2:
+    /* Examine the opcode which generated the exception */
+    /* Note: Instructions are in this order to avoid pipeline stalls. */
+    rsr     a2, epc1
+    movi    a4, ~3
+    ssa8l   a2                                  // sar is now correct shift for aligned read
+    and     a2, a2, a4                          // a2 now 4-byte aligned address of instruction
+    l32i    a4, a2, 0
+    l32i    a2, a2, 4
+
+    src     a2, a2, a4                          // a2 now instruction that failed
+    bbci    a2, 1, .LS_wrong_opcode
+    bbsi    a2, 14, .LSE_store_op               // Store instruction
+
+    /* l8/l16ui/l16si */
+    movi    a4, ~3
+    and     a4, a3, a4                          // a4 now word aligned read address
+
+    ssa8l   a3                                  // sar is now shift to extract a3's byte
+    l32i    a4, a4, 0                           // perform the actual read
+    srl     a4, a4                              // shift right correct distance
+    extui   a3, a2, 12, 4
+    bnez    a3, 1f                              // l16ui/l16si
+    extui   a4, a4, 0, 8                        // mask off bits needed for an l8
+    j       2f
+
+1:
+    extui   a4, a4, 0, 16
+    bbci    a2, 15, 2f                          // l16ui
+
+    /* Sign adjustment */
+    slli    a4, a4, 16
+    srai    a4, a4, 16                          // a4 contains the value
+
+2:
+    /* a4 contains the value */
+    rsr     a3, epc1
+    addi    a3, a3, 3
+    wsr     a3, epc1
+    wsr     a0, sar
+    rsr     a0, excsave1
+
+    extui   a2, a2, 3, 5
+    blti    a2, 10, .LSE_stack_reg
+
+    movi    a3, .LS_jumptable_base
+    addx8   a2, a2, a3                          // a2 is now the address to jump to
+    l32i    a3, sp, 0x0c
+    jx      a2
+
+.LSE_stack_reg:
+    addx2   a2, a2, sp
+    s32i    a4, a2, 0
+
+    /* Restore all values */
+    l32i    a4, sp, 0x10
+    l32i    a3, sp, 0x0c
+    l32i    a2, sp, 0x08
+    l32i    a1, sp, 0x04
+    rfe
+
+.LSE_store_op:
+    s32i    a5, a1, 0x14
+    s32i    a6, a1, 0x18
+
+    /* a2 -> instruction that caused the error */
+    /* a3 -> unaligned address */
+    extui   a4, a2, 4, 4
+    blti    a4, 7, 1f
+    movi    a5, .LSE_store_reg
+    addx8   a5, a4, a5
+    jx      a5
+
+1:
+    addx4   a4, a4, sp
+    l32i    a4, a4, 0
+
+.LSE_store_data:
+    /* a4 contains the value */
+    rsr     a6, epc1
+    addi    a6, a6, 3
+    wsr     a6, epc1
+
+    ssa8b   a3
+    movi    a5, -1
+    bbsi    a2, 12, 1f                          // s16
+    extui   a4, a4, 0, 8
+    movi    a6, 0xff
+    j       2f
+1:
+    extui   a4, a4, 0, 16
+    movi    a6, 0xffff
+2:
+    sll     a4, a4                              // shift the value to proper offset
+    sll     a6, a6
+    xor     a5, a5, a6                          // a5 contains the mask
+
+    movi    a6, ~3
+    and     a3, a3, a6                          // a3 has the aligned address
+    l32i    a6, a3, 0                           // a6 contains the data at the aligned address
+    and     a6, a6, a5
+    or      a4, a6, a4
+    s32i    a4, a3, 0
+
+    /* Restore registers */
+    wsr     a0, sar
+
+    l32i    a6, sp, 0x18
+    l32i    a5, sp, 0x14
+    l32i    a4, sp, 0x10
+    l32i    a3, sp, 0x0c
+    l32i    a2, sp, 0x08
+    l32i    a1, sp, 0x04
+    rsr     a0, excsave1
+
+    rfe
+
+.LSE_store_reg:
+    .org .LSE_store_reg + (7 * 8)
+    mov     a4, a7
+    j .LSE_store_data
+
+    .org .LSE_store_reg + (8 * 8)
+    mov     a4, a8
+    j .LSE_store_data
+
+    .org .LSE_store_reg + (9 * 8)
+    mov     a4, a9
+    j .LSE_store_data
+
+    .org .LSE_store_reg + (10 * 8)
+    mov     a4, a10
+    j .LSE_store_data
+
+    .org .LSE_store_reg + (11 * 8)
+    mov     a4, a11
+    j .LSE_store_data
+
+    .org .LSE_store_reg + (12 * 8)
+    mov     a4, a12
+    j .LSE_store_data
+
+    .org .LSE_store_reg + (13 * 8)
+    mov     a4, a13
+    j .LSE_store_data
+
+    .org .LSE_store_reg + (14 * 8)
+    mov     a4, a14
+    j .LSE_store_data
+
+    .org .LSE_store_reg + (15 * 8)
+    mov     a4, a15
+    j .LSE_store_data
+
+
+/* LoadStoreAlignmentCause handler:
+ *
+ * Completes unaligned 16-bit and 32-bit load/store instructions from 32-bit aligned memory region
+ * Called from UserExceptionVector if EXCCAUSE is LoadStoreAlignmentCause
+ */
+
+    .global   AlignmentErrorHandler
+    .section .iram1, "ax"
+
+    .literal_position
+
+    .balign 4
+AlignmentErrorHandler:
+    .type   AlignmentErrorHandler, @function
+
+    wsr     a0, depc                            // Save return address in depc
+    mov     a0, sp
+    movi    sp, LoadStoreHandlerStack
+    s32i    a0, sp, 0x04                        // Since a0 contains value of a1
+    s32i    a2, sp, 0x08
+    s32i    a3, sp, 0x0c
+    s32i    a4, sp, 0x10
+
+    rsr     a0, sar                             // Save SAR in a0 to restore later
+
+    /* Check whether the address lies in the valid range */
+    rsr     a3, excvaddr
+    movi    a4, _iram_text_end                  // End of code section of IRAM
+    bge     a3, a4, 1f
+    movi    a4, SOC_CACHE_APP_LOW               // Check if in APP cache region
+    blt     a3, a4, .LS_wrong_opcode
+    movi    a4, SOC_CACHE_APP_HIGH
+    bge     a3, a4, .LS_wrong_opcode
+    j       2f
+
+1:
+    movi    a4, SOC_IRAM_HIGH                   // End of IRAM address range
+    bge     a3, a4, .LS_wrong_opcode
+
+2:
+    /* Examine the opcode which generated the exception */
+    /* Note: Instructions are in this order to avoid pipeline stalls. */
+    rsr     a2, epc1
+    movi    a4, ~3
+    ssa8l   a2                                  // sar is now correct shift for aligned read
+    and     a2, a2, a4                          // a2 now 4-byte aligned address of instruction
+    l32i    a4, a2, 0
+    l32i    a2, a2, 4
+
+    /* a2 has the instruction that caused the error */
+    src     a2, a2, a4
+    extui   a4, a2, 0, 4
+    addi    a4, a4, -9
+    beqz    a4, .LSA_store_op
+    bbsi    a2, 14, .LSA_store_op
+
+    ssa8l   a3                                  // a3 contains the unaligned address
+    movi    a4, ~3
+    and     a4, a3, a4                          // a4 has the aligned address
+    l32i    a3, a4, 0
+    l32i    a4, a4, 4
+    src     a4, a4, a3
+
+    rsr     a3, epc1
+    addi    a3, a3, 2
+    bbsi    a2, 3, 1f                           // l32i.n
+    bbci    a2, 1, .LS_wrong_opcode
+    addi    a3, a3, 1
+
+    bbsi    a2, 13, 1f                          // l32
+    extui   a4, a4, 0, 16
+    bbci    a2, 15, 1f                          // l16ui
+
+    /* Sign adjustment */
+    slli    a4, a4, 16
+    srai    a4, a4, 16                          // a4 contains the value
+
+1:
+    wsr     a3, epc1
+    wsr     a0, sar
+    rsr     a0, excsave1
+
+    extui   a2, a2, 4, 4
+    blti    a2, 5, .LSA_stack_reg               // a3 contains the target register
+
+    movi    a3, .LS_jumptable_base
+    slli    a2, a2, 4
+    add     a2, a2, a3                          // a2 is now the address to jump to
+    l32i    a3, sp, 0x0c
+    jx      a2
+
+.LSA_stack_reg:
+    addx4   a2, a2, sp
+    s32i    a4, a2, 0
+
+    /* Restore all values */
+    l32i    a4, sp, 0x10
+    l32i    a3, sp, 0x0c
+    l32i    a2, sp, 0x08
+    l32i    a1, sp, 0x04
+    rfe
+
+/* Store instruction */
+.LSA_store_op:
+    s32i    a5, sp, 0x14
+    s32i    a6, sp, 0x18
+    s32i    a7, sp, 0x1c
+
+    /* a2 -> instruction that caused the error */
+    /* a3 -> unaligned address */
+    extui   a4, a2, 4, 4
+    blti    a4, 8, 1f
+    movi    a5, .LSA_store_reg
+    addx8   a5, a4, a5
+    jx      a5
+
+1:
+    addx4   a4, a4, sp
+    l32i    a4, a4, 0                           // a4 contains the value
+
+.LSA_store_data:
+    movi    a6, 0
+
+    rsr     a7, epc1
+    addi    a7, a7 ,2
+    bbsi    a2, 3, 1f                           // s32i.n
+    bbci    a2, 1, .LS_wrong_opcode
+
+    addi    a7, a7, 1
+    bbsi    a2, 13, 1f                          // s32i
+
+    movi    a5, -1
+    extui   a4, a4, 0, 16
+    slli    a6, a5, 16                          // 0xffff0000
+
+1:
+    wsr     a7, epc1
+    movi    a5, ~3
+    and     a5, a3, a5                          // a5 has the aligned address
+
+    ssa8b   a3
+    movi    a3, -1
+    src     a7, a6, a3
+    src     a3, a3, a6
+
+    /* Store data on lower address */
+    l32i    a6, a5, 0
+    and     a6, a6, a7
+    sll     a7, a4
+    or      a6, a6, a7
+    s32i    a6, a5, 0
+
+    /* Store data on higher address */
+    l32i    a7, a5, 4
+    srl     a6, a4
+    and     a3, a7, a3
+    or      a3, a3, a6
+    s32i    a3, a5, 4
+
+    /* Restore registers */
+    wsr     a0, sar
+    rsr     a0, excsave1
+
+    l32i    a7, sp, 0x1c
+    l32i    a6, sp, 0x18
+    l32i    a5, sp, 0x14
+    l32i    a4, sp, 0x10
+    l32i    a3, sp, 0x0c
+    l32i    a2, sp, 0x08
+    l32i    a1, sp, 0x04
+    rfe
+
+.LSA_store_reg:
+    .org .LSA_store_reg + (8 * 8)
+    mov     a4, a8
+    j       .LSA_store_data
+
+    .org .LSA_store_reg + (9 * 8)
+    mov     a4, a9
+    j       .LSA_store_data
+
+    .org .LSA_store_reg + (10 * 8)
+    mov     a4, a10
+    j       .LSA_store_data
+
+    .org .LSA_store_reg + (11 * 8)
+    mov     a4, a11
+    j       .LSA_store_data
+
+    .org .LSA_store_reg + (12 * 8)
+    mov     a4, a12
+    j       .LSA_store_data
+
+    .org .LSA_store_reg + (13 * 8)
+    mov     a4, a13
+    j       .LSA_store_data
+
+    .org .LSA_store_reg + (14 * 8)
+    mov     a4, a14
+    j       .LSA_store_data
+
+    .org .LSA_store_reg + (15 * 8)
+    mov     a4, a15
+    j       .LSA_store_data
+
+/*
+ * Common routines for both the exception handlers
+ */
+    .balign 4
+.LS_jumptable:
+    /*  The first 5 entries (80 bytes) of this table are unused (registers
+        a0..a4 are handled separately above).  Rather than have a whole bunch
+        of wasted space, just pretend that the table starts 80 bytes
+        earlier in memory. */
+    .set    .LS_jumptable_base, .LS_jumptable - (16 * 5)
+
+    .org    .LS_jumptable_base + (16 * 5)
+    mov     a5, a4
+    l32i    a4, sp, 0x10
+    l32i    a2, sp, 0x08
+    l32i    a1, sp, 0x04
+    rfe
+
+    .org    .LS_jumptable_base + (16 * 6)
+    mov     a6, a4
+    l32i    a4, sp, 0x10
+    l32i    a2, sp, 0x08
+    l32i    a1, sp, 0x04
+    rfe
+
+    .org    .LS_jumptable_base + (16 * 7)
+    mov     a7, a4
+    l32i    a4, sp, 0x10
+    l32i    a2, sp, 0x08
+    l32i    a1, sp, 0x04
+    rfe
+
+    .org    .LS_jumptable_base + (16 * 8)
+    mov     a8, a4
+    l32i    a4, sp, 0x10
+    l32i    a2, sp, 0x08
+    l32i    a1, sp, 0x04
+    rfe
+
+    .org    .LS_jumptable_base + (16 * 9)
+    mov     a9, a4
+    l32i    a4, sp, 0x10
+    l32i    a2, sp, 0x08
+    l32i    a1, sp, 0x04
+    rfe
+
+    .org    .LS_jumptable_base + (16 * 10)
+    mov     a10, a4
+    l32i    a4, sp, 0x10
+    l32i    a2, sp, 0x08
+    l32i    a1, sp, 0x04
+    rfe
+
+    .org    .LS_jumptable_base + (16 * 11)
+    mov     a11, a4
+    l32i    a4, sp, 0x10
+    l32i    a2, sp, 0x08
+    l32i    a1, sp, 0x04
+    rfe
+
+    .org    .LS_jumptable_base + (16 * 12)
+    mov     a12, a4
+    l32i    a4, sp, 0x10
+    l32i    a2, sp, 0x08
+    l32i    a1, sp, 0x04
+    rfe
+
+    .org    .LS_jumptable_base + (16 * 13)
+    mov     a13, a4
+    l32i    a4, sp, 0x10
+    l32i    a2, sp, 0x08
+    l32i    a1, sp, 0x04
+    rfe
+
+    .org    .LS_jumptable_base + (16 * 14)
+    mov     a14, a4
+    l32i    a4, sp, 0x10
+    l32i    a2, sp, 0x08
+    l32i    a1, sp, 0x04
+    rfe
+
+    .org    .LS_jumptable_base + (16 * 15)
+    mov     a15, a4
+    l32i    a4, sp, 0x10
+    l32i    a2, sp, 0x08
+    l32i    a1, sp, 0x04
+    rfe
+
+.LS_wrong_opcode:
+    /* Reaches here if the address is in invalid range or the opcode isn't supported.
+     * Restore registers and jump back to _xt_user_exc
+     */
+    wsr     a0, sar
+    l32i    a4, sp, 0x10
+    l32i    a3, sp, 0x0c
+    l32i    a2, sp, 0x08
+    l32i    a1, sp, 0x04
+    rsr     a0, depc
+    ret                                         // Equivalent to jx a0

kernel/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_overlay_os_hook.c

@@ -0,0 +1,75 @@
+/*
+ * SPDX-FileCopyrightText: 2015-2019 Cadence Design Systems, Inc.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD
+ */
+/*
+ * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/* xtensa_overlay_os_hook.c -- Overlay manager OS hooks for FreeRTOS. */
+
+#include "FreeRTOS.h"
+#include "semphr.h"
+
+#if configUSE_MUTEX
+
+/* Mutex object that controls access to the overlay. Currently only one
+ * overlay region is supported so one mutex suffices.
+ */
+    static SemaphoreHandle_t xt_overlay_mutex;
+
+
+/* This function should be overridden to provide OS specific init such
+ * as the creation of a mutex lock that can be used for overlay locking.
+ * Typically this mutex would be set up with priority inheritance. See
+ * overlay manager documentation for more details.
+ */
+    void xt_overlay_init_os( void )
+    {
+        /* Create the mutex for overlay access. Priority inheritance is
+         * required.
+         */
+        xt_overlay_mutex = xSemaphoreCreateMutex();
+    }
+
+
+/* This function locks access to shared overlay resources, typically
+ * by acquiring a mutex.
+ */
+    void xt_overlay_lock( void )
+    {
+        xSemaphoreTake( xt_overlay_mutex, 0 );
+    }
+
+
+/* This function releases access to shared overlay resources, typically
+ * by unlocking a mutex.
+ */
+    void xt_overlay_unlock( void )
+    {
+        xSemaphoreGive( xt_overlay_mutex );
+    }
+
+#endif /* if configUSE_MUTEX */

kernel/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_vector_defaults.S

@@ -0,0 +1,235 @@
+/*
+ * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "xtensa_rtos.h"
+#include "esp_idf_version.h"
+#if (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0))
+#include "esp_panic.h"
+#else
+#include "esp_private/panic_reason.h"
+#endif /* ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0) */
+#include "sdkconfig.h"
+#include "soc/soc.h"
+
+/*
+This file contains the default handlers for the high interrupt levels as well as some specialized exceptions.
+The default behaviour is to just exit the interrupt or call the panic handler on the exceptions
+*/
+
+
+#if XCHAL_HAVE_DEBUG
+    .global    xt_debugexception
+    .weak xt_debugexception
+    .set xt_debugexception, _xt_debugexception
+    .section .iram1,"ax"
+    .type       _xt_debugexception,@function
+    .align      4
+
+_xt_debugexception:
+#if (CONFIG_ESP32_ECO3_CACHE_LOCK_FIX && CONFIG_BTDM_CTRL_HLI)
+#define XT_DEBUGCAUSE_DI        (5)
+    getcoreid   a0
+#if (CONFIG_BTDM_CTRL_PINNED_TO_CORE == PRO_CPU_NUM)
+    beqz    a0, 1f
+#else
+    bnez    a0, 1f
+#endif
+
+    rsr     a0, DEBUGCAUSE
+    extui   a0, a0, XT_DEBUGCAUSE_DI, 1
+    bnez    a0, _xt_debug_di_exc
+1:
+#endif //(CONFIG_ESP32_ECO3_CACHE_LOCK_FIX && CONFIG_BTDM_CTRL_HLI)
+
+    movi    a0,PANIC_RSN_DEBUGEXCEPTION
+    wsr     a0,EXCCAUSE
+    /* _xt_panic assumes a level 1 exception. As we're
+       crashing anyhow, copy EPC & EXCSAVE from DEBUGLEVEL
+       to level 1. */
+    rsr     a0,(EPC + XCHAL_DEBUGLEVEL)
+    wsr     a0,EPC_1
+    rsr     a0,(EXCSAVE + XCHAL_DEBUGLEVEL)
+    wsr     a0,EXCSAVE_1
+    call0   _xt_panic                       /* does not return */
+    rfi     XCHAL_DEBUGLEVEL
+
+#if (CONFIG_ESP32_ECO3_CACHE_LOCK_FIX && CONFIG_BTDM_CTRL_HLI)
+    .align  4
+_xt_debug_di_exc:
+
+    /*
+    The delay time can be calculated by the following formula:
+      T = ceil(0.25 + max(t1, t2)) us
+
+      t1 = 80 / f1, t2 = (1 + 14/N) * 20 / f2
+
+      f1: PSRAM access frequency, unit: MHz.
+      f2: Flash access frequency, unit: MHz.
+
+      When flash is slow/fast read, N = 1.
+      When flash is DOUT/DIO read, N = 2.
+      When flash is QOUT/QIO read, N = 4.
+
+      And after testing, when CPU frequency is 240 MHz, it will take 1us to loop 27 times.
+    */
+#if defined(CONFIG_ESPTOOLPY_FLASHMODE_QIO) || defined(CONFIG_ESPTOOLPY_FLASHMODE_QOUT)
+
+# if defined(CONFIG_ESPTOOLPY_FLASHFREQ_80M) && defined(CONFIG_SPIRAM_SPEED_80M)
+    movi    a0, 54
+# elif defined(CONFIG_ESPTOOLPY_FLASHFREQ_80M) && defined(CONFIG_SPIRAM_SPEED_40M)
+    movi    a0, 81
+# elif defined(CONFIG_ESPTOOLPY_FLASHFREQ_40M) && defined(CONFIG_SPIRAM_SPEED_40M)
+    movi    a0, 81
+# elif defined(CONFIG_ESPTOOLPY_FLASHFREQ_26M) && defined(CONFIG_SPIRAM_SPEED_40M)
+    movi    a0, 108
+# else
+    movi    a0, 135
+# endif
+
+#elif defined(CONFIG_ESPTOOLPY_FLASHMODE_DIO) || defined(CONFIG_ESPTOOLPY_FLASHMODE_DOUT)
+
+# if defined(CONFIG_ESPTOOLPY_FLASHFREQ_80M) && defined(CONFIG_SPIRAM_SPEED_80M)
+    movi    a0, 81
+# elif defined(CONFIG_ESPTOOLPY_FLASHFREQ_80M) && defined(CONFIG_SPIRAM_SPEED_40M)
+    movi    a0, 81
+# elif defined(CONFIG_ESPTOOLPY_FLASHFREQ_40M) && defined(CONFIG_SPIRAM_SPEED_40M)
+    movi    a0, 135
+# elif defined(CONFIG_ESPTOOLPY_FLASHFREQ_26M) && defined(CONFIG_SPIRAM_SPEED_40M)
+    movi    a0, 189
+# else
+    movi    a0, 243
+# endif
+
+#else
+    movi    a0, 243
+#endif
+
+1:  addi    a0, a0, -1         /* delay_us(N) */
+    .rept   4
+    nop
+    .endr
+    bnez    a0, 1b
+
+    rsr     a0, EXCSAVE+XCHAL_DEBUGLEVEL
+    rfi     XCHAL_DEBUGLEVEL
+#endif //(CONFIG_ESP32_ECO3_CACHE_LOCK_FIX && CONFIG_BTDM_CTRL_HLI)
+#endif /* Debug exception */
+
+
+#if XCHAL_NUM_INTLEVELS >=2 && XCHAL_EXCM_LEVEL <2 && XCHAL_DEBUGLEVEL !=2
+    .global    xt_highint2
+    .weak xt_highint2
+    .set xt_highint2, _xt_highint2
+    .section .iram1,"ax"
+    .type       _xt_highint2,@function
+    .align      4
+_xt_highint2:
+
+    /* Default handler does nothing; just returns */
+    .align  4
+.L_xt_highint2_exit:
+    rsr     a0, EXCSAVE_2                   /* restore a0 */
+    rfi     2
+
+#endif  /* Level 2 */
+
+#if XCHAL_NUM_INTLEVELS >=3 && XCHAL_EXCM_LEVEL <3 && XCHAL_DEBUGLEVEL !=3
+
+    .global    xt_highint3
+    .weak xt_highint3
+    .set xt_highint3, _xt_highint3
+    .section .iram1,"ax"
+    .type       _xt_highint3,@function
+    .align      4
+_xt_highint3:
+
+    /* Default handler does nothing; just returns */
+
+    .align  4
+.L_xt_highint3_exit:
+    rsr     a0, EXCSAVE_3                   /* restore a0 */
+    rfi     3
+
+#endif  /* Level 3 */
+
+#if XCHAL_NUM_INTLEVELS >=4 && XCHAL_EXCM_LEVEL <4 && XCHAL_DEBUGLEVEL !=4
+
+    .global    xt_highint4
+    .weak xt_highint4
+    .set xt_highint4, _xt_highint4
+    .section .iram1,"ax"
+    .type       _xt_highint4,@function
+    .align      4
+_xt_highint4:
+
+    /* Default handler does nothing; just returns */
+
+    .align  4
+.L_xt_highint4_exit:
+    rsr     a0, EXCSAVE_4                   /* restore a0 */
+    rfi     4
+
+#endif  /* Level 4 */
+
+#if XCHAL_NUM_INTLEVELS >=5 && XCHAL_EXCM_LEVEL <5 && XCHAL_DEBUGLEVEL !=5
+
+    .global    xt_highint5
+    .weak xt_highint5
+    .set xt_highint5, _xt_highint5
+    .section .iram1,"ax"
+    .type       _xt_highint5,@function
+    .align      4
+_xt_highint5:
+
+    /* Default handler does nothing; just returns */
+
+    .align  4
+.L_xt_highint5_exit:
+    rsr     a0, EXCSAVE_5                   /* restore a0 */
+    rfi     5
+
+
+#endif  /* Level 5 */
+
+#if XCHAL_NUM_INTLEVELS >=6 && XCHAL_EXCM_LEVEL <6 && XCHAL_DEBUGLEVEL !=6
+
+    .global    _xt_highint6
+    .global    xt_highint6
+    .weak xt_highint6
+    .set xt_highint6, _xt_highint6
+    .section .iram1,"ax"
+    .type       _xt_highint6,@function
+    .align      4
+_xt_highint6:
+
+    /* Default handler does nothing; just returns */
+
+    .align  4
+.L_xt_highint6_exit:
+    rsr     a0, EXCSAVE_6                   /* restore a0 */
+    rfi     6
+
+#endif  /* Level 6 */
+
+#if XCHAL_HAVE_NMI
+
+    .global    _xt_nmi
+    .global    xt_nmi
+    .weak xt_nmi
+    .set xt_nmi, _xt_nmi
+    .section .iram1,"ax"
+    .type       _xt_nmi,@function
+    .align      4
+_xt_nmi:
+
+    /* Default handler does nothing; just returns */
+
+    .align  4
+.L_xt_nmi_exit:
+    rsr     a0, EXCSAVE + XCHAL_NMILEVEL    /* restore a0 */
+    rfi     XCHAL_NMILEVEL
+
+#endif  /* NMI */

kernel/FreeRTOS/Source/portable/ThirdParty/KnownIssues.md

@@ -0,0 +1,7 @@
+# Known Issues
+This document lists the known issues in various FreeRTOS third
+party ports.
+
+## ThirdParty/GCC/ARC_EM_HS
+* [Memory Read Protection Violation from Secure MPU on exit from
+interrupt](https://github.com/FreeRTOS/FreeRTOS-Kernel/issues/331)

kernel/FreeRTOS/Source/portable/ThirdParty/Partner-Supported-Ports/.github/CODE_OF_CONDUCT.md

@@ -0,0 +1,4 @@
+## Code of Conduct
+This project has adopted the [Amazon Open Source Code of Conduct](https://aws.github.io/code-of-conduct).
+For more information see the [Code of Conduct FAQ](https://aws.github.io/code-of-conduct-faq) or contact
+opensource-codeofconduct@amazon.com with any additional questions or comments.

kernel/FreeRTOS/Source/portable/ThirdParty/Partner-Supported-Ports/.github/CONTRIBUTING.md

@@ -0,0 +1,70 @@
+# Contribution guidelines
+
+Thank you for your interest in contributing to our project. Whether it's a bug report, new feature, code, or
+documentation, we welcome our community to be involved in this project.
+
+Please read through this document before submitting any issues or pull requests to ensure we are able to help you and all members of the community as effectively as possible.
+
+## Code of conduct
+This project has adopted the [Amazon Open Source Code of Conduct](https://aws.github.io/code-of-conduct).
+For more information see the [Code of Conduct FAQ](https://aws.github.io/code-of-conduct-faq) or contact
+opensource-codeofconduct@amazon.com with any additional questions or comments.
+
+
+## Security issue notifications
+If you discover a potential security issue in this project we ask that you notify AWS/Amazon Security via our [vulnerability reporting page](http://aws.amazon.com/security/vulnerability-reporting/). Please do **not** create a public github issue.
+
+
+## Submitting a bugs/feature request
+Have a bug to report or feature to request? Follow these steps:
+1. Search on the [FreeRTOS Community Support Forums](https://forums.freertos.org/) and [GitHub issue tracker](https://github.com/FreeRTOS/FreeRTOS/issues?utf8=%E2%9C%93&q=is%3Aissue) to be sure this hasn't been already reported or discussed.
+2. If your search turns up empty, create a new topic in the [forums](https://forums.freertos.org/) and work with the community to help clarify issues or refine the idea. Include as many of the details listed below.
+3. Once the community has had time to discuss and digest, we welcome you to create an [issue](https://github.com/FreeRTOS/FreeRTOS/issues) to report bugs or suggest features.
+
+When creating a new topic on the forums or filing an issue, please include as many relevant details as possible. Examples include:
+
+* A clear description of the situation — what you observe, what you expect, and your view on how the two differ.
+* A reproducible test case or sequence of steps.
+* The version of our code being used.
+* Any modifications you've made relevant to the bug.
+* Details of your environment or deployment. Highlight anything unusual.
+
+
+## Contributing via pull request
+Contributions via pull requests are much appreciated. Before sending us a pull request, please ensure that:
+
+1. You are working against the latest source on the *master* branch.
+2. You check existing open, and recently merged, pull requests to make sure someone else hasn't addressed the problem already.
+3. You open an issue to discuss any significant work - we would hate for your time to be wasted.
+
+To send us a pull request, please:
+
+1. Fork the repository.
+2. Modify the source; focus on the specific change you are contributing. If you also reformat all the code, it will be hard for us to focus on your change.
+3. Follow the [coding style guide](https://www.freertos.org/FreeRTOS-Coding-Standard-and-Style-Guide.html).
+4. Commit to your fork using clear commit messages.
+5. Send us a pull request, answering any default questions in the pull request interface.
+   NOTE: Please make sure the default option (Allow edits from maintainers) is left checked.
+6. Pay attention to any automated CI failures reported in the pull request, and stay involved in the conversation.
+
+GitHub provides additional document on [forking a repository](https://help.github.com/articles/fork-a-repo/) and
+[creating a pull request](https://help.github.com/articles/creating-a-pull-request/).
+
+## Coding style
+* Please ensure that your code complies to the [FreeRTOS coding style guidelines](https://www.freertos.org/FreeRTOS-Coding-Standard-and-Style-Guide.html).
+
+
+## Getting your pull request merged
+All pull requests must be approved by our review team before it can be merged in. We appreciate your patience while pull requests are reviewed. The time it takes to review will depend on complexity and consideration of wider implications.
+
+
+## Finding contributions to work on
+Looking at the existing issues is a great way to find something to contribute on. As our projects, by default, use the default GitHub issue labels (enhancement/bug/duplicate/help wanted/invalid/question/wontfix), tackling open 'help wanted' issues is a great place to start.
+
+
+## Licensing
+The FreeRTOS kernel is released under the MIT open source license, the text of which can be found [here](https://github.com/FreeRTOS/FreeRTOS/blob/master/FreeRTOS/License/license.txt)
+
+Additional license files can be found in the folders containing any supplementary libraries licensed by their respective copyright owners where applicable.
+
+We may ask you to sign a [Contributor License Agreement (CLA)](http://en.wikipedia.org/wiki/Contributor_License_Agreement) for larger changes.

kernel/FreeRTOS/Source/portable/ThirdParty/Partner-Supported-Ports/.github/SECURITY.md

@@ -0,0 +1,5 @@
+## Reporting a Vulnerability
+
+If you discover a potential security issue in this project we ask that you notify AWS/Amazon Security
+via our [vulnerability reporting page](http://aws.amazon.com/security/vulnerability-reporting/) or directly via email to aws-security@amazon.com.
+Please do **not** create a public github issue.

kernel/FreeRTOS/Source/portable/ThirdParty/Partner-Supported-Ports/.github/pull_request_template.md

@@ -0,0 +1,16 @@
+<!--- Title -->
+
+Description
+-----------
+<!--- Describe your changes in detail. -->
+
+Test Steps
+-----------
+<!-- Describe the steps to reproduce. -->
+
+Related Issue
+-----------
+<!-- If any, please provide issue ID. -->
+
+
+By submitting this pull request, I confirm that you can use, modify, copy, and redistribute this contribution, under the terms of your choice.

kernel/FreeRTOS/Source/portable/ThirdParty/Partner-Supported-Ports/GCC/AVR_AVRDx/port.c

@@ -0,0 +1,393 @@
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#include <stdlib.h>
+
+#include <avr/interrupt.h>
+#include "porthardware.h"
+#include "FreeRTOS.h"
+#include "task.h"
+
+/*-----------------------------------------------------------
+* Implementation of functions defined in portable.h for the AVR port.
+*----------------------------------------------------------*/
+
+/* Start tasks with interrupts enables. */
+#define portFLAGS_INT_ENABLED    ( ( StackType_t ) 0x80 )
+
+/*-----------------------------------------------------------*/
+
+/* We require the address of the pxCurrentTCB variable, but don't want to know
+ * any details of its type. */
+typedef void RTOS_TCB_t;
+extern volatile RTOS_TCB_t * volatile pxCurrentTCB;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Perform hardware setup to enable ticks from timer.
+ */
+static void prvSetupTimerInterrupt( void );
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
+{
+    uint16_t usAddress;
+
+    /*lint -e950 -e611 -e923 Lint doesn't like this much - but nothing I can do about it. */
+
+    /* Place a few bytes of known values on the bottom of the stack.
+     * This is just useful for debugging. Uncomment if needed. */
+    /* *pxTopOfStack = 0x11; */
+    /* pxTopOfStack--; */
+    /* *pxTopOfStack = 0x22; */
+    /* pxTopOfStack--; */
+    /* *pxTopOfStack = 0x33; */
+    /* pxTopOfStack--; */
+
+    /* The start of the task code will be popped off the stack last, so place
+     * it on first. */
+    usAddress = ( uint16_t ) pxCode;
+    *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
+    pxTopOfStack--;
+
+    usAddress >>= 8;
+    *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
+    pxTopOfStack--;
+
+    /* Next simulate the stack as if after a call to portSAVE_CONTEXT().
+    *  portSAVE_CONTEXT places the flags on the stack immediately after r0
+    *  to ensure the interrupts get disabled as soon as possible, and so ensuring
+    *  the stack use is minimal should a context switch interrupt occur. */
+    *pxTopOfStack = ( StackType_t ) 0x00; /* R0 */
+    pxTopOfStack--;
+    *pxTopOfStack = portFLAGS_INT_ENABLED;
+    pxTopOfStack--;
+#if defined(__AVR_HAVE_RAMPZ__)
+    *pxTopOfStack = (StackType_t)0x00; /* RAMPZ */
+    pxTopOfStack--;
+#endif
+
+    /* Now the remaining registers.   The compiler expects R1 to be 0. */
+    *pxTopOfStack = ( StackType_t ) 0x00; /* R1 */
+
+    /* Leave R2 - R23 untouched */
+    pxTopOfStack -= 23;
+
+    /* Place the parameter on the stack in the expected location. */
+    usAddress = ( uint16_t ) pvParameters;
+    *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
+    pxTopOfStack--;
+
+    usAddress >>= 8;
+    *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
+
+    /* Leave register R26 - R31 untouched */
+    pxTopOfStack -= 7;
+
+    /*lint +e950 +e611 +e923 */
+
+    return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+    /* Setup the hardware to generate the tick. */
+    prvSetupTimerInterrupt();
+
+    /* Restore the context of the first task that is going to run. */
+    portRESTORE_CONTEXT();
+
+    /* Simulate a function call end as generated by the compiler.  We will now
+     * jump to the start of the task the context of which we have just restored. */
+    asm volatile ( "ret" );
+
+    /* Should not get here. */
+    return pdTRUE;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+    /* vPortEndScheduler is not implemented in this port. */
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Manual context switch.  The first thing we do is save the registers so we
+ * can use a naked attribute.
+ */
+void vPortYield( void ) __attribute__( ( naked ) );
+void vPortYield( void )
+{
+    portSAVE_CONTEXT();
+    vTaskSwitchContext();
+    portRESTORE_CONTEXT();
+    asm volatile ( "ret" );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Manual context switch callable from ISRs. The first thing
+ * we do is save the registers so we can use a naked attribute.
+ */
+void vPortYieldFromISR( void ) __attribute__( ( naked ) );
+void vPortYieldFromISR( void )
+{
+    portSAVE_CONTEXT();
+    vTaskSwitchContext();
+    portRESTORE_CONTEXT();
+    asm volatile ( "reti" );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Context switch function used by the tick.  This must be identical to
+ * vPortYield() from the call to vTaskSwitchContext() onwards.  The only
+ * difference from vPortYield() is the tick count is incremented as the
+ * call comes from the tick ISR.
+ */
+void vPortYieldFromTick( void ) __attribute__( ( naked ) );
+void vPortYieldFromTick( void )
+{
+    portSAVE_CONTEXT();
+
+    if( xTaskIncrementTick() != pdFALSE )
+    {
+        vTaskSwitchContext();
+    }
+
+    portRESTORE_CONTEXT();
+
+    asm volatile ( "reti" );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup timer to generate a tick interrupt.
+ */
+static void prvSetupTimerInterrupt( void )
+{
+    /* Configure low-power timer  used in tickless mode */
+#if (configUSE_TICKLESS_IDLE == 1)
+    RTC_INIT();
+#endif
+    TICK_init();
+}
+/*-----------------------------------------------------------*/
+
+#if (configUSE_PREEMPTION == 1)
+
+/*
+ * Tick ISR for preemptive scheduler.  We can use a naked attribute as
+ * the context is saved at the start of vPortYieldFromTick().  The tick
+ * count is incremented after the context is saved.
+ */
+    ISR( TICK_INT_vect, ISR_NAKED )
+    {
+        /* Clear tick interrupt flag. */
+        CLR_INT( INT_FLAGS, INT_MASK );
+
+        vPortYieldFromTick();
+
+        asm volatile ( "reti" );
+    }
+#else  /* if configUSE_PREEMPTION == 1 */
+
+/*
+ * Tick ISR for the cooperative scheduler.  All this does is increment the
+ * tick count.  We don't need to switch context, this can only be done by
+ * manual calls to taskYIELD();
+ */
+    ISR( TICK_INT_vect )
+    {
+        /* Clear tick interrupt flag. */
+        INT_FLAGS = INT_MASK;
+        xTaskIncrementTick();
+    }
+#endif /* if configUSE_PREEMPTION == 1 */
+
+#if (configUSE_TICKLESS_IDLE == 1)
+
+volatile uint32_t RTC_OVF_Count = 0;
+
+ISR(RTC_CNT_vect)
+{
+    if (RTC.INTFLAGS & RTC_OVF_bm )
+    {
+        RTC_OVF_Count += 0x00010000;
+        RTC.INTFLAGS = (RTC_OVF_bm);
+    }  
+    
+    if (RTC.INTFLAGS & RTC_CMP_bm )
+    {
+        RTC.INTFLAGS = (RTC_CMP_bm);
+        //Disable compare interrupt
+        RTC.INTCTRL &= (0xFF ^ RTC_CMP_bm);
+    }    
+
+}
+
+static uint32_t ulGetExternalTime(void)
+{
+    uint32_t time_rtc;
+
+    while (RTC.STATUS & RTC_CNTBUSY_bm)
+    {
+        ;
+    }
+    time_rtc = RTC.CNT;
+    time_rtc += RTC_OVF_Count;
+    return time_rtc;
+}
+
+static void vSetWakeTimeInterrupt(uint16_t xExpectedIdleTime)
+{
+    uint32_t rtc_cnt_time;
+
+    /* compute the required  */
+    rtc_cnt_time = RTC_TICKS_TO_COUNTS(xExpectedIdleTime);
+    rtc_cnt_time += ulGetExternalTime();
+
+    while (RTC.STATUS & RTC_CMPBUSY_bm)
+    {
+        ;
+    }
+    RTC.CMP = (rtc_cnt_time & 0xFFFF);
+
+    //Enable compare interrupt
+    RTC.INTCTRL |= RTC_CMP_bm;
+}
+
+/* Define the function that is called by portSUPPRESS_TICKS_AND_SLEEP(). */
+__attribute__((weak)) void vPortSuppressTicksAndSleep(TickType_t xExpectedIdleTime)
+{
+     eSleepModeStatus eSleepStatus;
+     uint32_t ulLowPowerTimeBeforeSleep, ulLowPowerTimeAfterSleep;
+    
+    /* Read the current time from a time source that will remain operational
+    while the microcontroller is in a low power state. */
+    ulLowPowerTimeBeforeSleep = ulGetExternalTime();
+
+    /* Stop the timer that is generating the tick interrupt. */
+    TICK_TMR_STOP();
+
+    /* Enter a critical section that will not effect interrupts bringing the MCU
+    out of sleep mode. */
+    portDISABLE_INTERRUPTS();
+
+    /* Ensure it is still ok to enter the sleep mode. */
+    eSleepStatus = eTaskConfirmSleepModeStatus();
+
+    if (eSleepStatus == eAbortSleep)
+    {
+        /* A task has been moved out of the Blocked state since this macro was
+         * executed, or a context switch is being held pending.  Do not enter a
+         * sleep state.  Restart the tick and exit the critical section. */
+        TICK_TMR_START();
+        portENABLE_INTERRUPTS();
+    }
+    else
+    {
+        if (eSleepStatus == eNoTasksWaitingTimeout)
+        {
+            /* A user definable macro that allows application code to be inserted
+             * here.  Such application code can be used to minimize power consumption
+             * further by turning off IO, peripheral clocks, the Flash, etc. */
+            configPRE_PWR_DOWN_PROCESSING();
+
+            /* There are no running state tasks and no tasks that are blocked with a
+             * time out.  Assuming the application does not care if the tick time slips
+             * with respect to calendar time then enter a deep sleep that can only be
+             * woken by (in this demo case) the user button being pushed on the
+             * Curiosity Nano board.  If the application does require the tick time
+             * to keep better track of the calender time then the PIT peripheral can be
+             * used to make rough adjustments. */
+            portSET_MODE_AND_SLEEP(SLEEP_MODE_PWR_DOWN);
+
+            /* A user definable macro that allows application code to be inserted
+             * here.  Such application code can be used to reverse any actions taken
+             * by the configPRE_STOP_PROCESSING() */
+            configPOST_PWR_DOWN_PROCESSING();
+        }
+        else
+        {
+            /* Configure an interrupt to bring the microcontroller out of its low
+             * power state at the time the kernel next needs to execute.  The
+             * interrupt must be generated from a source that remains operational
+             * when the microcontroller is in a low power state. */
+            vSetWakeTimeInterrupt(xExpectedIdleTime);
+
+            /* Allow the application to define some pre-sleep processing.  This is
+             * the standard configPRE_SLEEP_PROCESSING() macro as described on the
+             * FreeRTOS.org website. */
+            configPRE_SLEEP_PROCESSING(xExpectedIdleTime);
+
+            /* Enter the low power state. */
+            portSET_MODE_AND_SLEEP(SLEEP_MODE_STANDBY);
+
+            /* Determine how long the microcontroller was actually in a low power
+             * state for, which will be less than xExpectedIdleTime if the
+             * microcontroller was brought out of low power mode by an interrupt
+             * other than that configured by the vSetWakeTimeInterrupt() call.
+             * Note that the scheduler is suspended before
+             * portSUPPRESS_TICKS_AND_SLEEP() is called, and resumed when
+             * portSUPPRESS_TICKS_AND_SLEEP() returns.  Therefore no other tasks will
+             * execute until this function completes. */
+            ulLowPowerTimeAfterSleep = ulGetExternalTime();
+
+            /* Allow the application to define some post sleep processing.  This is
+             * the standard configPOST_SLEEP_PROCESSING() macro, as described on the
+             * FreeRTOS.org website. 
+             * It can be used to reverse the actions of configPRE_SLEEP_PROCESSING(), 
+             * and in so doing, return the microcontroller back to its fully operational state */
+            configPOST_SLEEP_PROCESSING(xExpectedIdleTime);
+
+            /* Correct the kernels tick count to account for the time the
+            * microcontroller spent in its low power state. */
+            vTaskStepTick(RTC_COUNTS_TO_TICKS(ulLowPowerTimeAfterSleep - ulLowPowerTimeBeforeSleep));
+            //  vTaskStepTick(xExpectedIdleTime);
+
+        }
+
+        /* Exit the critical section - it might be possible to do this immediately
+         * after the SET_MODE_AND_SLEEP calls. */
+        portENABLE_INTERRUPTS();
+
+        /* Restart the timer that is generating the tick interrupt. */
+        TICK_TMR_START();
+    }
+}
+
+#endif 

kernel/FreeRTOS/Source/portable/ThirdParty/Partner-Supported-Ports/GCC/AVR_AVRDx/porthardware.h

@@ -0,0 +1,221 @@
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef PORTHARDWARE_H
+#define PORTHARDWARE_H
+
+#include "FreeRTOSConfig.h"
+
+/*-----------------------------------------------------------*/
+
+#define CLR_INT( FLAG_REG, FLAG_MASK )                                         \
+    asm volatile (                                                             \
+        "push r16\n\t"                                                         \
+        "ldi r16, %1\n\t"                                                      \
+        "sts %0, r16\n\t"                                                      \
+        "pop r16\n\t"                                                          \
+        :                                                                      \
+        : "i" ( _SFR_MEM_ADDR( FLAG_REG ) ), "i" ( ( uint8_t ) ( FLAG_MASK ) ) \
+        );
+
+#if ( configUSE_TIMER_INSTANCE == 0 )
+
+    #define TICK_INT_vect    TCB0_INT_vect
+    #define INT_FLAGS        TCB0_INTFLAGS
+    #define INT_MASK         TCB_CAPT_bm
+
+    #define TICK_init()                                      \
+    {                                                        \
+        TCB0.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \
+        TCB0.INTCTRL = TCB_CAPT_bm;                          \
+        TCB0.CTRLA = TCB_ENABLE_bm;                          \
+    }
+    
+    #define TICK_TMR_STOP()   TCB0.CTRLA = 0x00;
+    #define TICK_TMR_START()                                 \
+    {                                                        \
+        TCB0.INTFLAGS = TCB_CAPT_bm;                         \
+        TCB0.CTRLA = TCB_ENABLE_bm;                          \
+    }
+    #define TICK_TMR_READ()     TCB0.CNT
+    #define TICK_INT_READY()    (TCB0.INTCTRL & TCB_CAPT_bm)
+
+#elif ( configUSE_TIMER_INSTANCE == 1 )
+
+    #define TICK_INT_vect    TCB1_INT_vect
+    #define INT_FLAGS        TCB1_INTFLAGS
+    #define INT_MASK         TCB_CAPT_bm
+
+    #define TICK_init()                                      \
+    {                                                        \
+        TCB1.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \
+        TCB1.INTCTRL = TCB_CAPT_bm;                          \
+        TCB1.CTRLA = TCB_ENABLE_bm;                          \
+    }
+    
+    #define TICK_TMR_STOP()   TCB1.CTRLA = 0x00;
+    #define TICK_TMR_START()                                 \
+    {                                                        \
+        TCB1.INTFLAGS = TCB_CAPT_bm;                         \
+        TCB1.CTRLA = TCB_ENABLE_bm;                          \
+    }
+    #define TICK_TMR_READ()     TCB1.CNT
+    #define TICK_INT_READY()    (TCB1.INTCTRL & TCB_CAPT_bm)
+
+#elif ( configUSE_TIMER_INSTANCE == 2 )
+
+    #define TICK_INT_vect    TCB2_INT_vect
+    #define INT_FLAGS        TCB2_INTFLAGS
+    #define INT_MASK         TCB_CAPT_bm
+
+    #define TICK_init()                                      \
+    {                                                        \
+        TCB2.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \
+        TCB2.INTCTRL = TCB_CAPT_bm;                          \
+        TCB2.CTRLA = TCB_ENABLE_bm;                          \
+    }
+    
+    #define TICK_TMR_STOP()   TCB2.CTRLA = 0x00;
+    #define TICK_TMR_START()                                 \
+    {                                                        \
+        TCB2.INTFLAGS = TCB_CAPT_bm;                         \
+        TCB2.CTRLA = TCB_ENABLE_bm;                          \
+    }
+    #define TICK_TMR_READ()     TCB2.CNT
+    #define TICK_INT_READY()    (TCB2.INTCTRL & TCB_CAPT_bm)
+
+#elif ( configUSE_TIMER_INSTANCE == 3 )
+
+    #define TICK_INT_vect    TCB3_INT_vect
+    #define INT_FLAGS        TCB3_INTFLAGS
+    #define INT_MASK         TCB_CAPT_bm
+
+    #define TICK_init()                                      \
+    {                                                        \
+        TCB3.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \
+        TCB3.INTCTRL = TCB_CAPT_bm;                          \
+        TCB3.CTRLA = TCB_ENABLE_bm;                          \
+    }
+    
+    #define TICK_TMR_STOP()   TCB3.CTRLA = 0x00;
+    #define TICK_TMR_START()                                 \
+    {                                                        \
+        TCB3.INTFLAGS = TCB_CAPT_bm;                         \
+        TCB3.CTRLA = TCB_ENABLE_bm;                          \
+    }
+    #define TICK_TMR_READ()     TCB3.CNT
+    #define TICK_INT_READY()    (TCB3.INTCTRL & TCB_CAPT_bm)
+
+#elif ( configUSE_TIMER_INSTANCE == 4 )
+
+    #define TICK_INT_vect    TCB4_INT_vect
+    #define INT_FLAGS        TCB4_INTFLAGS
+    #define INT_MASK         TCB_CAPT_bm
+
+    #define TICK_init()                                      \
+    {                                                        \
+        TCB4.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \
+        TCB4.INTCTRL = TCB_CAPT_bm;                          \
+        TCB4.CTRLA = TCB_ENABLE_bm;                          \
+    }
+    #define TICK_TMR_STOP()   TCB4.CTRLA = 0x00;
+    #define TICK_TMR_START()                                 \
+    {                                                        \
+        TCB4.INTFLAGS = TCB_CAPT_bm;                         \
+        TCB4.CTRLA = TCB_ENABLE_bm;                          \
+    }
+    #define TICK_TMR_READ()     TCB4.CNT
+    #define TICK_INT_READY()    (TCB4.INTCTRL & TCB_CAPT_bm)
+
+#elif ( configUSE_TIMER_INSTANCE == 5 )
+
+    #if ( configUSE_TICKLESS_IDLE == 1 )
+        
+        /* RTC is not supported as tick timer when tickless mode is used */
+        #error Invalid timer setting.
+        
+    #else
+
+        #define TICK_INT_vect    RTC_CNT_vect
+        #define INT_FLAGS        RTC_INTFLAGS
+        #define INT_MASK         RTC_OVF_bm
+
+        /* Hertz to period for RTC setup */
+        #define RTC_PERIOD_HZ( x )    ( 32768 * ( ( 1.0 / x ) ) )
+        #define TICK_init()                                        \
+        {                                                          \
+            while( RTC.STATUS > 0 ) {; }                           \
+            RTC.CTRLA = RTC_PRESCALER_DIV1_gc | 1 << RTC_RTCEN_bp; \
+            RTC.PER = RTC_PERIOD_HZ( configTICK_RATE_HZ );         \
+            RTC.INTCTRL |= 1 << RTC_OVF_bp;                        \
+        }
+        #undef TICK_TMR_STOP()   
+        #undef TICK_TMR_START()  
+        #undef TICK_TMR_READ()     
+        #undef TICK_INT_READY()    
+    #endif
+
+#else /* if ( configUSE_TIMER_INSTANCE == 0 ) */
+    #undef TICK_INT_vect
+    #undef INT_FLAGS
+    #undef INT_MASK
+    #undef TICK_init()
+    #undef TICK_TMR_STOP()   
+    #undef TICK_TMR_START()                                    
+    #undef TICK_TMR_READ()     
+    #undef TICK_INT_READY()    
+    #error Invalid timer setting.
+#endif /* if ( configUSE_TIMER_INSTANCE == 0 ) */
+
+/*-----------------------------------------------------------*/
+
+
+#if ( configUSE_TICKLESS_IDLE == 1 )
+
+#define LOW_POWER_CLOCK     (32768UL)
+
+#define RTC_TICK_PERIOD_MS            ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define RTC_TICKS_TO_COUNTS(tick_cnt) (uint32_t)(((float)(tick_cnt * LOW_POWER_CLOCK)/configTICK_RATE_HZ) - 0.5)
+#define RTC_COUNTS_TO_TICKS(counts)   (uint32_t)((float)((counts * 1.0) * configTICK_RATE_HZ)/LOW_POWER_CLOCK  )
+
+
+#define RTC_INIT()                                                          \
+{                                                                           \
+    while( RTC.STATUS > 0 ) {; }                                            \
+    RTC.PER = 0xFFFF;                                                       \
+    RTC.CMP = 0x3FFF;                                                       \
+    RTC.CNT = 0;                                                            \
+    RTC.INTFLAGS = RTC_OVF_bm | RTC_CMP_bm;                                 \
+    RTC.CTRLA = RTC_RUNSTDBY_bm | RTC_PRESCALER_DIV1_gc | RTC_RTCEN_bm ;    \
+    RTC.INTCTRL = RTC_OVF_bm | RTC_CMP_bm;                                  \
+}
+
+#endif
+
+ 
+#endif /* PORTHARDWARE_H */

kernel/FreeRTOS/Source/portable/ThirdParty/Partner-Supported-Ports/GCC/AVR_AVRDx/portmacro.h

@@ -0,0 +1,267 @@
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+/* *INDENT-OFF* */
+    #ifdef __cplusplus
+        extern "C" {
+    #endif
+/* *INDENT-ON* */
+
+#include <avr/sleep.h>
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR                 char
+#define portFLOAT                float
+#define portDOUBLE               double
+#define portLONG                 long
+#define portSHORT                int
+#define portSTACK_TYPE           uint8_t
+#define portBASE_TYPE            char
+
+#define portPOINTER_SIZE_TYPE    uint16_t
+
+typedef portSTACK_TYPE   StackType_t;
+typedef signed char      BaseType_t;
+typedef unsigned char    UBaseType_t;
+
+#if ( configUSE_16_BIT_TICKS == 1 )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) 0xffff
+#else
+    typedef uint32_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+#define portENTER_CRITICAL()                     \
+    asm volatile ( "in __tmp_reg__, __SREG__" ); \
+    asm volatile ( "cli" );                      \
+    asm volatile ( "push __tmp_reg__" )
+
+#define portEXIT_CRITICAL()             \
+    asm volatile ( "pop __tmp_reg__" ); \
+    asm volatile ( "out __SREG__, __tmp_reg__" )
+
+#define portDISABLE_INTERRUPTS()    asm volatile ( "cli" ::);
+#define portENABLE_INTERRUPTS()     asm volatile ( "sei" ::);
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH      ( -1 )
+#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT    1
+#define portNOP()    asm volatile ( "nop" );
+/*-----------------------------------------------------------*/
+
+/* Kernel utilities. */
+extern void vPortYield( void ) __attribute__( ( naked ) );
+#define portYIELD()             vPortYield()
+
+extern void vPortYieldFromISR( void ) __attribute__( ( naked ) );
+#define portYIELD_FROM_ISR()    vPortYieldFromISR()
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+
+/* Macros for tickless idle/low power functionality. */
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+
+extern void vPortSuppressTicksAndSleep(TickType_t xExpectedIdleTime);
+#define portSUPPRESS_TICKS_AND_SLEEP(xExpectedIdleTime) vPortSuppressTicksAndSleep(xExpectedIdleTime)
+#endif
+
+#ifndef configPRE_PWR_DOWN_PROCESSING
+#define configPRE_PWR_DOWN_PROCESSING()
+#endif
+
+#ifndef configPOST_PWR_DOWN_PROCESSING
+#define configPOST_PWR_DOWN_PROCESSING()
+#endif
+
+/*-----------------------------------------------------------*/
+
+/* Helper macros for portSAVE_CONTEXT/ portRESTORE_CONTEXT - common support for Mega-0 and AVR-Dx families */
+
+#if defined(__AVR_HAVE_RAMPZ__)
+
+#define portSAVE_RAMPZ()                              \
+    asm volatile("in    r0, __RAMPZ__           \n\t" \
+                 "push  r0                      \n\t");
+
+#define portRESTORE_RAMPZ()                           \
+    asm volatile("pop   r0                      \n\t" \
+                 "out   __RAMPZ__, r0           \n\t");
+
+#else
+
+#define portSAVE_RAMPZ()
+#define portRESTORE_RAMPZ()
+
+#endif
+
+/* Macro to save all the general purpose registers, the save the stack pointer
+ * into the TCB.
+
+ * The first thing we do is save the flags then disable interrupts.  This is to
+ * guard our stack against having a context switch interrupt after we have already
+ * pushed the registers onto the stack - causing the 32 registers to be on the
+ * stack twice.
+
+ * r1 is set to zero as the compiler expects it to be thus, however some
+ * of the math routines make use of R1.
+
+ * The interrupts will have been disabled during the call to portSAVE_CONTEXT()
+ * so we need not worry about reading/writing to the stack pointer. */
+
+#define portSAVE_CONTEXT()                                  \
+    {                                                       \
+        asm volatile("push  r0                      \n\t"   \
+                     "in    r0, __SREG__            \n\t"   \
+                     "cli                           \n\t"   \
+                     "push  r0                      \n\t"); \
+        portSAVE_RAMPZ();                                   \
+        asm volatile("push  r1                      \n\t"   \
+                     "clr   r1                      \n\t"   \
+                     "push  r2                      \n\t"   \
+                     "push  r3                      \n\t"   \
+                     "push  r4                      \n\t"   \
+                     "push  r5                      \n\t"   \
+                     "push  r6                      \n\t"   \
+                     "push  r7                      \n\t"   \
+                     "push  r8                      \n\t"   \
+                     "push  r9                      \n\t"   \
+                     "push  r10                     \n\t"   \
+                     "push  r11                     \n\t"   \
+                     "push  r12                     \n\t"   \
+                     "push  r13                     \n\t"   \
+                     "push  r14                     \n\t"   \
+                     "push  r15                     \n\t"   \
+                     "push  r16                     \n\t"   \
+                     "push  r17                     \n\t"   \
+                     "push  r18                     \n\t"   \
+                     "push  r19                     \n\t"   \
+                     "push  r20                     \n\t"   \
+                     "push  r21                     \n\t"   \
+                     "push  r22                     \n\t"   \
+                     "push  r23                     \n\t"   \
+                     "push  r24                     \n\t"   \
+                     "push  r25                     \n\t"   \
+                     "push  r26                     \n\t"   \
+                     "push  r27                     \n\t"   \
+                     "push  r28                     \n\t"   \
+                     "push  r29                     \n\t"   \
+                     "push  r30                     \n\t"   \
+                     "push  r31                     \n\t"   \
+                     "lds   r26, pxCurrentTCB       \n\t"   \
+                     "lds   r27, pxCurrentTCB + 1   \n\t"   \
+                     "in    r0, __SP_L__            \n\t"   \
+                     "st    x+, r0                  \n\t"   \
+                     "in    r0, __SP_H__            \n\t"   \
+                     "st    x+, r0                  \n\t"); \
+    }
+
+/* Opposite to portSAVE_CONTEXT().  Interrupts will have been disabled during
+ * the context save so we can write to the stack pointer. */
+#define portRESTORE_CONTEXT()                               \
+    {                                                       \
+        asm volatile("lds   r26, pxCurrentTCB       \n\t"   \
+                     "lds   r27, pxCurrentTCB + 1   \n\t"   \
+                     "ld    r28, x+                 \n\t"   \
+                     "out   __SP_L__, r28           \n\t"   \
+                     "ld    r29, x+                 \n\t"   \
+                     "out   __SP_H__, r29           \n\t"   \
+                     "pop   r31                     \n\t"   \
+                     "pop   r30                     \n\t"   \
+                     "pop   r29                     \n\t"   \
+                     "pop   r28                     \n\t"   \
+                     "pop   r27                     \n\t"   \
+                     "pop   r26                     \n\t"   \
+                     "pop   r25                     \n\t"   \
+                     "pop   r24                     \n\t"   \
+                     "pop   r23                     \n\t"   \
+                     "pop   r22                     \n\t"   \
+                     "pop   r21                     \n\t"   \
+                     "pop   r20                     \n\t"   \
+                     "pop   r19                     \n\t"   \
+                     "pop   r18                     \n\t"   \
+                     "pop   r17                     \n\t"   \
+                     "pop   r16                     \n\t"   \
+                     "pop   r15                     \n\t"   \
+                     "pop   r14                     \n\t"   \
+                     "pop   r13                     \n\t"   \
+                     "pop   r12                     \n\t"   \
+                     "pop   r11                     \n\t"   \
+                     "pop   r10                     \n\t"   \
+                     "pop   r9                      \n\t"   \
+                     "pop   r8                      \n\t"   \
+                     "pop   r7                      \n\t"   \
+                     "pop   r6                      \n\t"   \
+                     "pop   r5                      \n\t"   \
+                     "pop   r4                      \n\t"   \
+                     "pop   r3                      \n\t"   \
+                     "pop   r2                      \n\t"   \
+                     "pop   r1                      \n\t"); \
+        portRESTORE_RAMPZ();                                \
+        asm volatile("pop   r0                      \n\t"   \
+                     "out   __SREG__, r0            \n\t"   \
+                     "pop   r0                      \n\t"); \
+    }
+/*-----------------------------------------------------------*/
+
+#define portSET_MODE_AND_SLEEP(mode)  \
+    {                                 \
+        set_sleep_mode(mode);         \
+        sleep_enable();               \
+        portENABLE_INTERRUPTS();      \
+        sleep_cpu();                  \
+        portDISABLE_INTERRUPTS();     \
+        sleep_disable();              \
+    }
+
+/* *INDENT-OFF* */
+    #ifdef __cplusplus
+        }
+    #endif
+/* *INDENT-ON* */
+
+#endif /* PORTMACRO_H */

kernel/FreeRTOS/Source/portable/ThirdParty/Partner-Supported-Ports/GCC/AVR_Mega0/port.c

@@ -0,0 +1,393 @@
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#include <stdlib.h>
+
+#include <avr/interrupt.h>
+#include "porthardware.h"
+#include "FreeRTOS.h"
+#include "task.h"
+
+/*-----------------------------------------------------------
+* Implementation of functions defined in portable.h for the AVR port.
+*----------------------------------------------------------*/
+
+/* Start tasks with interrupts enables. */
+#define portFLAGS_INT_ENABLED    ( ( StackType_t ) 0x80 )
+
+/*-----------------------------------------------------------*/
+
+/* We require the address of the pxCurrentTCB variable, but don't want to know
+ * any details of its type. */
+typedef void RTOS_TCB_t;
+extern volatile RTOS_TCB_t * volatile pxCurrentTCB;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Perform hardware setup to enable ticks from timer.
+ */
+static void prvSetupTimerInterrupt( void );
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
+{
+    uint16_t usAddress;
+
+    /*lint -e950 -e611 -e923 Lint doesn't like this much - but nothing I can do about it. */
+
+    /* Place a few bytes of known values on the bottom of the stack.
+     * This is just useful for debugging. Uncomment if needed. */
+    /* *pxTopOfStack = 0x11; */
+    /* pxTopOfStack--; */
+    /* *pxTopOfStack = 0x22; */
+    /* pxTopOfStack--; */
+    /* *pxTopOfStack = 0x33; */
+    /* pxTopOfStack--; */
+
+    /* The start of the task code will be popped off the stack last, so place
+     * it on first. */
+    usAddress = ( uint16_t ) pxCode;
+    *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
+    pxTopOfStack--;
+
+    usAddress >>= 8;
+    *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
+    pxTopOfStack--;
+
+    /* Next simulate the stack as if after a call to portSAVE_CONTEXT().
+    *  portSAVE_CONTEXT places the flags on the stack immediately after r0
+    *  to ensure the interrupts get disabled as soon as possible, and so ensuring
+    *  the stack use is minimal should a context switch interrupt occur. */
+    *pxTopOfStack = ( StackType_t ) 0x00; /* R0 */
+    pxTopOfStack--;
+    *pxTopOfStack = portFLAGS_INT_ENABLED;
+    pxTopOfStack--;
+#if defined(__AVR_HAVE_RAMPZ__)
+    *pxTopOfStack = (StackType_t)0x00; /* RAMPZ */
+    pxTopOfStack--;
+#endif
+
+    /* Now the remaining registers.   The compiler expects R1 to be 0. */
+    *pxTopOfStack = ( StackType_t ) 0x00; /* R1 */
+
+    /* Leave R2 - R23 untouched */
+    pxTopOfStack -= 23;
+
+    /* Place the parameter on the stack in the expected location. */
+    usAddress = ( uint16_t ) pvParameters;
+    *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
+    pxTopOfStack--;
+
+    usAddress >>= 8;
+    *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
+
+    /* Leave register R26 - R31 untouched */
+    pxTopOfStack -= 7;
+
+    /*lint +e950 +e611 +e923 */
+
+    return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+    /* Setup the hardware to generate the tick. */
+    prvSetupTimerInterrupt();
+
+    /* Restore the context of the first task that is going to run. */
+    portRESTORE_CONTEXT();
+
+    /* Simulate a function call end as generated by the compiler.  We will now
+     * jump to the start of the task the context of which we have just restored. */
+    asm volatile ( "ret" );
+
+    /* Should not get here. */
+    return pdTRUE;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+    /* vPortEndScheduler is not implemented in this port. */
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Manual context switch.  The first thing we do is save the registers so we
+ * can use a naked attribute.
+ */
+void vPortYield( void ) __attribute__( ( naked ) );
+void vPortYield( void )
+{
+    portSAVE_CONTEXT();
+    vTaskSwitchContext();
+    portRESTORE_CONTEXT();
+    asm volatile ( "ret" );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Manual context switch callable from ISRs. The first thing
+ * we do is save the registers so we can use a naked attribute.
+ */
+void vPortYieldFromISR( void ) __attribute__( ( naked ) );
+void vPortYieldFromISR( void )
+{
+    portSAVE_CONTEXT();
+    vTaskSwitchContext();
+    portRESTORE_CONTEXT();
+    asm volatile ( "reti" );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Context switch function used by the tick.  This must be identical to
+ * vPortYield() from the call to vTaskSwitchContext() onwards.  The only
+ * difference from vPortYield() is the tick count is incremented as the
+ * call comes from the tick ISR.
+ */
+void vPortYieldFromTick( void ) __attribute__( ( naked ) );
+void vPortYieldFromTick( void )
+{
+    portSAVE_CONTEXT();
+
+    if( xTaskIncrementTick() != pdFALSE )
+    {
+        vTaskSwitchContext();
+    }
+
+    portRESTORE_CONTEXT();
+
+    asm volatile ( "reti" );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup timer to generate a tick interrupt.
+ */
+static void prvSetupTimerInterrupt( void )
+{
+    /* Configure low-power timer  used in tickless mode */
+#if (configUSE_TICKLESS_IDLE == 1)
+    RTC_INIT();
+#endif
+    TICK_init();
+}
+/*-----------------------------------------------------------*/
+
+#if (configUSE_PREEMPTION == 1)
+
+/*
+ * Tick ISR for preemptive scheduler.  We can use a naked attribute as
+ * the context is saved at the start of vPortYieldFromTick().  The tick
+ * count is incremented after the context is saved.
+ */
+    ISR( TICK_INT_vect, ISR_NAKED )
+    {
+        /* Clear tick interrupt flag. */
+        CLR_INT( INT_FLAGS, INT_MASK );
+
+        vPortYieldFromTick();
+
+        asm volatile ( "reti" );
+    }
+#else  /* if configUSE_PREEMPTION == 1 */
+
+/*
+ * Tick ISR for the cooperative scheduler.  All this does is increment the
+ * tick count.  We don't need to switch context, this can only be done by
+ * manual calls to taskYIELD();
+ */
+    ISR( TICK_INT_vect )
+    {
+        /* Clear tick interrupt flag. */
+        INT_FLAGS = INT_MASK;
+        xTaskIncrementTick();
+    }
+#endif /* if configUSE_PREEMPTION == 1 */
+
+#if (configUSE_TICKLESS_IDLE == 1)
+
+volatile uint32_t RTC_OVF_Count = 0;
+
+ISR(RTC_CNT_vect)
+{
+    if (RTC.INTFLAGS & RTC_OVF_bm )
+    {
+        RTC_OVF_Count += 0x00010000;
+        RTC.INTFLAGS = (RTC_OVF_bm);
+    }  
+    
+    if (RTC.INTFLAGS & RTC_CMP_bm )
+    {
+        RTC.INTFLAGS = (RTC_CMP_bm);
+        //Disable compare interrupt
+        RTC.INTCTRL &= (0xFF ^ RTC_CMP_bm);
+    }    
+
+}
+
+static uint32_t ulGetExternalTime(void)
+{
+    uint32_t time_rtc;
+
+    while (RTC.STATUS & RTC_CNTBUSY_bm)
+    {
+        ;
+    }
+    time_rtc = RTC.CNT;
+    time_rtc += RTC_OVF_Count;
+    return time_rtc;
+}
+
+static void vSetWakeTimeInterrupt(uint16_t xExpectedIdleTime)
+{
+    uint32_t rtc_cnt_time;
+
+    /* compute the required  */
+    rtc_cnt_time = RTC_TICKS_TO_COUNTS(xExpectedIdleTime);
+    rtc_cnt_time += ulGetExternalTime();
+
+    while (RTC.STATUS & RTC_CMPBUSY_bm)
+    {
+        ;
+    }
+    RTC.CMP = (rtc_cnt_time & 0xFFFF);
+
+    //Enable compare interrupt
+    RTC.INTCTRL |= RTC_CMP_bm;
+}
+
+/* Define the function that is called by portSUPPRESS_TICKS_AND_SLEEP(). */
+__attribute__((weak)) void vPortSuppressTicksAndSleep(TickType_t xExpectedIdleTime)
+{
+     eSleepModeStatus eSleepStatus;
+     uint32_t ulLowPowerTimeBeforeSleep, ulLowPowerTimeAfterSleep;
+    
+    /* Read the current time from a time source that will remain operational
+    while the microcontroller is in a low power state. */
+    ulLowPowerTimeBeforeSleep = ulGetExternalTime();
+
+    /* Stop the timer that is generating the tick interrupt. */
+    TICK_TMR_STOP();
+
+    /* Enter a critical section that will not effect interrupts bringing the MCU
+    out of sleep mode. */
+    portDISABLE_INTERRUPTS();
+
+    /* Ensure it is still ok to enter the sleep mode. */
+    eSleepStatus = eTaskConfirmSleepModeStatus();
+
+    if (eSleepStatus == eAbortSleep)
+    {
+        /* A task has been moved out of the Blocked state since this macro was
+         * executed, or a context switch is being held pending.  Do not enter a
+         * sleep state.  Restart the tick and exit the critical section. */
+        TICK_TMR_START();
+        portENABLE_INTERRUPTS();
+    }
+    else
+    {
+        if (eSleepStatus == eNoTasksWaitingTimeout)
+        {
+            /* A user definable macro that allows application code to be inserted
+             * here.  Such application code can be used to minimize power consumption
+             * further by turning off IO, peripheral clocks, the Flash, etc. */
+            configPRE_PWR_DOWN_PROCESSING();
+
+            /* There are no running state tasks and no tasks that are blocked with a
+             * time out.  Assuming the application does not care if the tick time slips
+             * with respect to calendar time then enter a deep sleep that can only be
+             * woken by (in this demo case) the user button being pushed on the
+             * Curiosity Nano board.  If the application does require the tick time
+             * to keep better track of the calender time then the PIT peripheral can be
+             * used to make rough adjustments. */
+            portSET_MODE_AND_SLEEP(SLEEP_MODE_PWR_DOWN);
+
+            /* A user definable macro that allows application code to be inserted
+             * here.  Such application code can be used to reverse any actions taken
+             * by the configPRE_STOP_PROCESSING() */
+            configPOST_PWR_DOWN_PROCESSING();
+        }
+        else
+        {
+            /* Configure an interrupt to bring the microcontroller out of its low
+             * power state at the time the kernel next needs to execute.  The
+             * interrupt must be generated from a source that remains operational
+             * when the microcontroller is in a low power state. */
+            vSetWakeTimeInterrupt(xExpectedIdleTime);
+
+            /* Allow the application to define some pre-sleep processing.  This is
+             * the standard configPRE_SLEEP_PROCESSING() macro as described on the
+             * FreeRTOS.org website. */
+            configPRE_SLEEP_PROCESSING(xExpectedIdleTime);
+
+            /* Enter the low power state. */
+            portSET_MODE_AND_SLEEP(SLEEP_MODE_STANDBY);
+
+            /* Determine how long the microcontroller was actually in a low power
+             * state for, which will be less than xExpectedIdleTime if the
+             * microcontroller was brought out of low power mode by an interrupt
+             * other than that configured by the vSetWakeTimeInterrupt() call.
+             * Note that the scheduler is suspended before
+             * portSUPPRESS_TICKS_AND_SLEEP() is called, and resumed when
+             * portSUPPRESS_TICKS_AND_SLEEP() returns.  Therefore no other tasks will
+             * execute until this function completes. */
+            ulLowPowerTimeAfterSleep = ulGetExternalTime();
+
+            /* Allow the application to define some post sleep processing.  This is
+             * the standard configPOST_SLEEP_PROCESSING() macro, as described on the
+             * FreeRTOS.org website. 
+             * It can be used to reverse the actions of configPRE_SLEEP_PROCESSING(), 
+             * and in so doing, return the microcontroller back to its fully operational state */
+            configPOST_SLEEP_PROCESSING(xExpectedIdleTime);
+
+            /* Correct the kernels tick count to account for the time the
+            * microcontroller spent in its low power state. */
+            vTaskStepTick(RTC_COUNTS_TO_TICKS(ulLowPowerTimeAfterSleep - ulLowPowerTimeBeforeSleep));
+            //  vTaskStepTick(xExpectedIdleTime);
+
+        }
+
+        /* Exit the critical section - it might be possible to do this immediately
+         * after the SET_MODE_AND_SLEEP calls. */
+        portENABLE_INTERRUPTS();
+
+        /* Restart the timer that is generating the tick interrupt. */
+        TICK_TMR_START();
+    }
+}
+
+#endif 

kernel/FreeRTOS/Source/portable/ThirdParty/Partner-Supported-Ports/GCC/AVR_Mega0/porthardware.h

@@ -0,0 +1,183 @@
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef PORTHARDWARE_H
+#define PORTHARDWARE_H
+
+#include "FreeRTOSConfig.h"
+
+/*-----------------------------------------------------------*/
+
+#define CLR_INT( FLAG_REG, FLAG_MASK )                                         \
+    asm volatile (                                                             \
+        "push r16\n\t"                                                         \
+        "ldi r16, %1\n\t"                                                      \
+        "sts %0, r16\n\t"                                                      \
+        "pop r16\n\t"                                                          \
+        :                                                                      \
+        : "i" ( _SFR_MEM_ADDR( FLAG_REG ) ), "i" ( ( uint8_t ) ( FLAG_MASK ) ) \
+        );
+
+#if ( configUSE_TIMER_INSTANCE == 0 )
+
+    #define TICK_INT_vect    TCB0_INT_vect
+    #define INT_FLAGS        TCB0_INTFLAGS
+    #define INT_MASK         TCB_CAPT_bm
+
+    #define TICK_init()                                      \
+    {                                                        \
+        TCB0.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \
+        TCB0.INTCTRL = TCB_CAPT_bm;                          \
+        TCB0.CTRLA = TCB_ENABLE_bm;                          \
+    }
+    
+    #define TICK_TMR_STOP()   TCB0.CTRLA = 0x00;
+    #define TICK_TMR_START()                                 \
+    {                                                        \
+        TCB0.INTFLAGS = TCB_CAPT_bm;                         \
+        TCB0.CTRLA = TCB_ENABLE_bm;                          \
+    }
+    #define TICK_TMR_READ()     TCB0.CNT
+    #define TICK_INT_READY()    (TCB0.INTCTRL & TCB_CAPT_bm)
+
+#elif ( configUSE_TIMER_INSTANCE == 1 )
+
+    #define TICK_INT_vect    TCB1_INT_vect
+    #define INT_FLAGS        TCB1_INTFLAGS
+    #define INT_MASK         TCB_CAPT_bm
+
+    #define TICK_init()                                      \
+    {                                                        \
+        TCB1.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \
+        TCB1.INTCTRL = TCB_CAPT_bm;                          \
+        TCB1.CTRLA = TCB_ENABLE_bm;                          \
+    }
+    
+    #define TICK_TMR_STOP()   TCB1.CTRLA = 0x00;
+    #define TICK_TMR_START()                                 \
+    {                                                        \
+        TCB1.INTFLAGS = TCB_CAPT_bm;                         \
+        TCB1.CTRLA = TCB_ENABLE_bm;                          \
+    }
+    #define TICK_TMR_READ()     TCB1.CNT
+    #define TICK_INT_READY()    (TCB1.INTCTRL & TCB_CAPT_bm)
+
+#elif ( configUSE_TIMER_INSTANCE == 2 )
+
+    #define TICK_INT_vect    TCB2_INT_vect
+    #define INT_FLAGS        TCB2_INTFLAGS
+    #define INT_MASK         TCB_CAPT_bm
+
+    #define TICK_init()                                      \
+    {                                                        \
+        TCB2.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \
+        TCB2.INTCTRL = TCB_CAPT_bm;                          \
+        TCB2.CTRLA = TCB_ENABLE_bm;                          \
+    }
+    
+    #define TICK_TMR_STOP()   TCB2.CTRLA = 0x00;
+    #define TICK_TMR_START()                                 \
+    {                                                        \
+        TCB2.INTFLAGS = TCB_CAPT_bm;                         \
+        TCB2.CTRLA = TCB_ENABLE_bm;                          \
+    }
+    #define TICK_TMR_READ()     TCB2.CNT
+    #define TICK_INT_READY()    (TCB2.INTCTRL & TCB_CAPT_bm)
+
+#elif ( configUSE_TIMER_INSTANCE == 3 )
+
+    #define TICK_INT_vect    TCB3_INT_vect
+    #define INT_FLAGS        TCB3_INTFLAGS
+    #define INT_MASK         TCB_CAPT_bm
+
+    #define TICK_init()                                      \
+    {                                                        \
+        TCB3.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \
+        TCB3.INTCTRL = TCB_CAPT_bm;                          \
+        TCB3.CTRLA = TCB_ENABLE_bm;                          \
+    }
+    
+    #define TICK_TMR_STOP()   TCB3.CTRLA = 0x00;
+    #define TICK_TMR_START()                                 \
+    {                                                        \
+        TCB3.INTFLAGS = TCB_CAPT_bm;                         \
+        TCB3.CTRLA = TCB_ENABLE_bm;                          \
+    }
+    #define TICK_TMR_READ()     TCB3.CNT
+    #define TICK_INT_READY()    (TCB3.INTCTRL & TCB_CAPT_bm)
+
+#elif ( configUSE_TIMER_INSTANCE == 4 )
+
+    #define TICK_INT_vect    RTC_CNT_vect
+    #define INT_FLAGS        RTC_INTFLAGS
+    #define INT_MASK         RTC_OVF_bm
+
+/* Hertz to period for RTC setup */
+    #define RTC_PERIOD_HZ( x )    ( 32768 * ( ( 1.0 / x ) ) )
+    #define TICK_init()                                        \
+    {                                                          \
+        while( RTC.STATUS > 0 ) {; }                           \
+        RTC.CTRLA = RTC_PRESCALER_DIV1_gc | 1 << RTC_RTCEN_bp; \
+        RTC.PER = RTC_PERIOD_HZ( configTICK_RATE_HZ );         \
+        RTC.INTCTRL |= 1 << RTC_OVF_bp;                        \
+    }
+
+#else /* if ( configUSE_TIMER_INSTANCE == 0 ) */
+    #undef TICK_INT_vect
+    #undef INT_FLAGS
+    #undef INT_MASK
+    #undef TICK_init()
+    #error Invalid timer setting.
+#endif /* if ( configUSE_TIMER_INSTANCE == 0 ) */
+
+
+#if ( configUSE_TICKLESS_IDLE == 1 )
+
+#define LOW_POWER_CLOCK     (32768UL)
+
+#define RTC_TICK_PERIOD_MS            ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define RTC_TICKS_TO_COUNTS(tick_cnt) (uint32_t)(((float)(tick_cnt * LOW_POWER_CLOCK)/configTICK_RATE_HZ) - 0.5)
+#define RTC_COUNTS_TO_TICKS(counts)   (uint32_t)((float)((counts * 1.0) * configTICK_RATE_HZ)/LOW_POWER_CLOCK  )
+
+
+#define RTC_INIT()                                                          \
+{                                                                           \
+	while( RTC.STATUS > 0 ) {; }                                            \
+	RTC.PER = 0xFFFF;                                                       \
+	RTC.CMP = 0x3FFF;                                                       \
+	RTC.CNT = 0;                                                            \
+	RTC.INTFLAGS = RTC_OVF_bm | RTC_CMP_bm;                                 \
+	RTC.CTRLA = RTC_RUNSTDBY_bm | RTC_PRESCALER_DIV1_gc | RTC_RTCEN_bm ;    \
+	RTC.INTCTRL = RTC_OVF_bm | RTC_CMP_bm;                                  \
+}
+
+#endif
+
+/*-----------------------------------------------------------*/
+
+#endif /* PORTHARDWARE_H */

kernel/FreeRTOS/Source/portable/ThirdParty/Partner-Supported-Ports/GCC/AVR_Mega0/portmacro.h

@@ -0,0 +1,267 @@
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+/* *INDENT-OFF* */
+    #ifdef __cplusplus
+        extern "C" {
+    #endif
+/* *INDENT-ON* */
+
+#include <avr/sleep.h>
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR                 char
+#define portFLOAT                float
+#define portDOUBLE               double
+#define portLONG                 long
+#define portSHORT                int
+#define portSTACK_TYPE           uint8_t
+#define portBASE_TYPE            char
+
+#define portPOINTER_SIZE_TYPE    uint16_t
+
+typedef portSTACK_TYPE   StackType_t;
+typedef signed char      BaseType_t;
+typedef unsigned char    UBaseType_t;
+
+#if ( configUSE_16_BIT_TICKS == 1 )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) 0xffff
+#else
+    typedef uint32_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+#define portENTER_CRITICAL()                     \
+    asm volatile ( "in __tmp_reg__, __SREG__" ); \
+    asm volatile ( "cli" );                      \
+    asm volatile ( "push __tmp_reg__" )
+
+#define portEXIT_CRITICAL()             \
+    asm volatile ( "pop __tmp_reg__" ); \
+    asm volatile ( "out __SREG__, __tmp_reg__" )
+
+#define portDISABLE_INTERRUPTS()    asm volatile ( "cli" ::);
+#define portENABLE_INTERRUPTS()     asm volatile ( "sei" ::);
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH      ( -1 )
+#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT    1
+#define portNOP()    asm volatile ( "nop" );
+/*-----------------------------------------------------------*/
+
+/* Kernel utilities. */
+extern void vPortYield( void ) __attribute__( ( naked ) );
+#define portYIELD()             vPortYield()
+
+extern void vPortYieldFromISR( void ) __attribute__( ( naked ) );
+#define portYIELD_FROM_ISR()    vPortYieldFromISR()
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+
+/* Macros for tickless idle/low power functionality. */
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+
+extern void vPortSuppressTicksAndSleep(TickType_t xExpectedIdleTime);
+#define portSUPPRESS_TICKS_AND_SLEEP(xExpectedIdleTime) vPortSuppressTicksAndSleep(xExpectedIdleTime)
+#endif
+
+#ifndef configPRE_PWR_DOWN_PROCESSING
+#define configPRE_PWR_DOWN_PROCESSING()
+#endif
+
+#ifndef configPOST_PWR_DOWN_PROCESSING
+#define configPOST_PWR_DOWN_PROCESSING()
+#endif
+
+/*-----------------------------------------------------------*/
+
+/* Helper macros for portSAVE_CONTEXT/ portRESTORE_CONTEXT - common support for Mega-0 and AVR-Dx families */
+
+#if defined(__AVR_HAVE_RAMPZ__)
+
+#define portSAVE_RAMPZ()                              \
+    asm volatile("in    r0, __RAMPZ__           \n\t" \
+                 "push  r0                      \n\t");
+
+#define portRESTORE_RAMPZ()                           \
+    asm volatile("pop   r0                      \n\t" \
+                 "out   __RAMPZ__, r0           \n\t");
+
+#else
+
+#define portSAVE_RAMPZ()
+#define portRESTORE_RAMPZ()
+
+#endif
+
+/* Macro to save all the general purpose registers, the save the stack pointer
+ * into the TCB.
+
+ * The first thing we do is save the flags then disable interrupts.  This is to
+ * guard our stack against having a context switch interrupt after we have already
+ * pushed the registers onto the stack - causing the 32 registers to be on the
+ * stack twice.
+
+ * r1 is set to zero as the compiler expects it to be thus, however some
+ * of the math routines make use of R1.
+
+ * The interrupts will have been disabled during the call to portSAVE_CONTEXT()
+ * so we need not worry about reading/writing to the stack pointer. */
+
+#define portSAVE_CONTEXT()                                  \
+    {                                                       \
+        asm volatile("push  r0                      \n\t"   \
+                     "in    r0, __SREG__            \n\t"   \
+                     "cli                           \n\t"   \
+                     "push  r0                      \n\t"); \
+        portSAVE_RAMPZ();                                   \
+        asm volatile("push  r1                      \n\t"   \
+                     "clr   r1                      \n\t"   \
+                     "push  r2                      \n\t"   \
+                     "push  r3                      \n\t"   \
+                     "push  r4                      \n\t"   \
+                     "push  r5                      \n\t"   \
+                     "push  r6                      \n\t"   \
+                     "push  r7                      \n\t"   \
+                     "push  r8                      \n\t"   \
+                     "push  r9                      \n\t"   \
+                     "push  r10                     \n\t"   \
+                     "push  r11                     \n\t"   \
+                     "push  r12                     \n\t"   \
+                     "push  r13                     \n\t"   \
+                     "push  r14                     \n\t"   \
+                     "push  r15                     \n\t"   \
+                     "push  r16                     \n\t"   \
+                     "push  r17                     \n\t"   \
+                     "push  r18                     \n\t"   \
+                     "push  r19                     \n\t"   \
+                     "push  r20                     \n\t"   \
+                     "push  r21                     \n\t"   \
+                     "push  r22                     \n\t"   \
+                     "push  r23                     \n\t"   \
+                     "push  r24                     \n\t"   \
+                     "push  r25                     \n\t"   \
+                     "push  r26                     \n\t"   \
+                     "push  r27                     \n\t"   \
+                     "push  r28                     \n\t"   \
+                     "push  r29                     \n\t"   \
+                     "push  r30                     \n\t"   \
+                     "push  r31                     \n\t"   \
+                     "lds   r26, pxCurrentTCB       \n\t"   \
+                     "lds   r27, pxCurrentTCB + 1   \n\t"   \
+                     "in    r0, __SP_L__            \n\t"   \
+                     "st    x+, r0                  \n\t"   \
+                     "in    r0, __SP_H__            \n\t"   \
+                     "st    x+, r0                  \n\t"); \
+    }
+
+/* Opposite to portSAVE_CONTEXT().  Interrupts will have been disabled during
+ * the context save so we can write to the stack pointer. */
+#define portRESTORE_CONTEXT()                               \
+    {                                                       \
+        asm volatile("lds   r26, pxCurrentTCB       \n\t"   \
+                     "lds   r27, pxCurrentTCB + 1   \n\t"   \
+                     "ld    r28, x+                 \n\t"   \
+                     "out   __SP_L__, r28           \n\t"   \
+                     "ld    r29, x+                 \n\t"   \
+                     "out   __SP_H__, r29           \n\t"   \
+                     "pop   r31                     \n\t"   \
+                     "pop   r30                     \n\t"   \
+                     "pop   r29                     \n\t"   \
+                     "pop   r28                     \n\t"   \
+                     "pop   r27                     \n\t"   \
+                     "pop   r26                     \n\t"   \
+                     "pop   r25                     \n\t"   \
+                     "pop   r24                     \n\t"   \
+                     "pop   r23                     \n\t"   \
+                     "pop   r22                     \n\t"   \
+                     "pop   r21                     \n\t"   \
+                     "pop   r20                     \n\t"   \
+                     "pop   r19                     \n\t"   \
+                     "pop   r18                     \n\t"   \
+                     "pop   r17                     \n\t"   \
+                     "pop   r16                     \n\t"   \
+                     "pop   r15                     \n\t"   \
+                     "pop   r14                     \n\t"   \
+                     "pop   r13                     \n\t"   \
+                     "pop   r12                     \n\t"   \
+                     "pop   r11                     \n\t"   \
+                     "pop   r10                     \n\t"   \
+                     "pop   r9                      \n\t"   \
+                     "pop   r8                      \n\t"   \
+                     "pop   r7                      \n\t"   \
+                     "pop   r6                      \n\t"   \
+                     "pop   r5                      \n\t"   \
+                     "pop   r4                      \n\t"   \
+                     "pop   r3                      \n\t"   \
+                     "pop   r2                      \n\t"   \
+                     "pop   r1                      \n\t"); \
+        portRESTORE_RAMPZ();                                \
+        asm volatile("pop   r0                      \n\t"   \
+                     "out   __SREG__, r0            \n\t"   \
+                     "pop   r0                      \n\t"); \
+    }
+/*-----------------------------------------------------------*/
+
+#define portSET_MODE_AND_SLEEP(mode)  \
+    {                                 \
+        set_sleep_mode(mode);         \
+        sleep_enable();               \
+        portENABLE_INTERRUPTS();      \
+        sleep_cpu();                  \
+        portDISABLE_INTERRUPTS();     \
+        sleep_disable();              \
+    }
+
+/* *INDENT-OFF* */
+    #ifdef __cplusplus
+        }
+    #endif
+/* *INDENT-ON* */
+
+#endif /* PORTMACRO_H */

kernel/FreeRTOS/Source/portable/ThirdParty/Partner-Supported-Ports/LICENSE

@@ -0,0 +1 @@
+This repository contains multiple directories, each individually licensed. Please see the LICENSE file in each directory.

kernel/FreeRTOS/Source/portable/ThirdParty/Partner-Supported-Ports/README.md

@@ -0,0 +1,20 @@
+## FreeRTOS Partner Supported Ports
+
+This repository contains FreeRTOS ports supported by FreeRTOS partners. Follow
+the steps below to contribute a FreeRTOS port to this repository:
+
+1. Write the FreeRTOS port for your Compiler and Architecture.
+2. Create a project in the [FreeRTOS Partner Supported Demos Repository](https://github.com/FreeRTOS/FreeRTOS-Partner-Supported-Demos/tree/main)
+   for your hardware for running tests as mentioned [here](https://github.com/FreeRTOS/FreeRTOS/blob/main/FreeRTOS/Demo/ThirdParty/Template/README.md).
+3. Make sure all the tests pass. Add the test results in the Pull Request description.
+4. Add a README file with the following information:
+    1. How to use this port?
+    2. Link to the test project created in Step 2.
+    3. Any other relevant information.
+5. Raise a PR to merge the FreeRTOS port.
+6. Raise another PR to merge the test project in the [FreeRTOS-Partner-Supported-Demos Repository](https://github.com/FreeRTOS/FreeRTOS/tree/main/FreeRTOS/Demo/ThirdParty/Community-Supported).
+
+
+## License
+
+This repository contains multiple directories, each individually licensed. Please see the LICENSE file in each directory.

kernel/FreeRTOS/Source/portable/ThirdParty/README.md

@@ -0,0 +1,51 @@
+# FreeRTOS Third Party Ports
+
+FreeRTOS third party ports can be supported by the FreeRTOS team, a FreeRTOS
+partner or FreeRTOS community members. Depending on who supports it, the support
+provided will differ as follows:
+
+## FreeRTOS Team Supported Third Party FreeRTOS Ports
+
+Location: https://github.com/FreeRTOS/FreeRTOS-Kernel/tree/main/portable/ThirdParty
+
+These third party FreeRTOS ports are supported by the FreeRTOS team. For a
+FreeRTOS team supported third party FreeRTOS port:
+
+* The code has been reviewed by the FreeRTOS team.
+* FreeRTOS team has access to the hardware and the test results have been
+  verified by the FreeRTOS team.
+* Customer queries as well as bugs are addressed by the FreeRTOS team.
+* The code can be included in Long Term Support (LTS) releases.
+
+A new FreeRTOS port cannot be directly contributed to this location. Instead,
+the FreeRTOS team will decide to take ownership of a partner supported or a
+community supported FreeRTOS port based on the community interest.
+
+## Partner Supported FreeRTOS Ports
+
+Location: https://github.com/FreeRTOS/FreeRTOS-Kernel-Partner-Supported-Ports/tree/main
+
+These FreeRTOS ports are supported by a FreeRTOS partner. For a partner
+supported FreeRTOS port:
+
+* The code has not been reviewed by the FreeRTOS team.
+* FreeRTOS team has not verified the tests results but tests exist and are
+  reported to be successful by the partner.
+* Customer queries as well as bugs are addressed by the partner.
+
+A new FreeRTOS port can be directly contributed by a partner. The process to
+contribute a FreeRTOS port is documented [here](https://github.com/FreeRTOS/FreeRTOS-Kernel-Partner-Supported-Ports/blob/main/README.md).
+
+## Community Supported FreeRTOS Ports
+
+Location: https://github.com/FreeRTOS/FreeRTOS-Kernel-Community-Supported-Ports/tree/main
+
+These FreeRTOS ports are supported by the FreeRTOS community members. For a
+community supported FreeRTOS port:
+
+* The code has not been reviewed by the FreeRTOS team.
+* Tests may or may not exist for the FreeRTOS port.
+* Customer queries as well as bugs are addressed by the community.
+
+A new FreeRTOS port can be directly contributed by anyone. The process to
+contribute a FreeRTOS port is documented [here](https://github.com/FreeRTOS/FreeRTOS-Kernel-Community-Supported-Ports/blob/main/README.md).

kernel/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/Makefile

@@ -0,0 +1,98 @@
+### Makefile to build the FreeRTOS library ###
+
+# Build target (options: sim, board)
+
+TARGET      = sim
+SMALL       =
+
+# Tools
+
+CC          = xt-xcc
+AS          = xt-xcc
+AR          = xt-ar
+XT_CORE     = $(patsubst %-params,%,$(notdir $(shell xt-xcc --show-config=core)))
+CONFIGDIR   = $(shell xt-xcc --show-config=config)
+
+# For platform-specific commands
+
+include $(CONFIGDIR)/misc/hostenv.mk
+
+# Source code and build locations
+
+SRCROOT     = $(subst /,$(S),$(CURDIR))
+TSTROOT     = $(abspath $(SRCROOT)$(S)..$(S)..$(S)..$(S)..$(S)..$(S)demos$(S)cadence$(S)sim$(SMALL))
+BLDROOT     = $(TSTROOT)$(S)build
+BLDDIR      = $(BLDROOT)$(S)$(XT_CORE)
+
+FR_SRCDIR   = $(abspath $(SRCROOT)$(S)..$(S)..$(S)..)
+FR_SRCDIR2  = $(FR_SRCDIR)$(S)portable$(S)MemMang
+XT_SRCDIR   = $(SRCROOT)
+
+vpath %.c $(FR_SRCDIR) $(FR_SRCDIR2) $(XT_SRCDIR)
+vpath %.S $(XT_SRCDIR)
+
+# File lists
+
+FR_C_FILES  = $(notdir $(wildcard $(FR_SRCDIR)/*.c)) $(notdir $(wildcard $(FR_SRCDIR2)/*.c))
+XT_C_FILES  = $(notdir $(wildcard $(XT_SRCDIR)/*.c))
+XT_S_FILES  = $(notdir $(wildcard $(XT_SRCDIR)/*.S))
+
+# List of all .o files that will go into the library
+
+LIB_C_O     = $(patsubst %.c,%.o,$(XT_C_FILES) $(FR_C_FILES))
+LIB_S_O     = $(patsubst %.S,%.o,$(XT_S_FILES))
+LIB_O_LIST  = $(addprefix $(BLDDIR)/,$(LIB_C_O) $(LIB_S_O))
+
+# Output files
+
+OSLIB       = $(BLDDIR)$(S)libfreertos.a
+
+# Build options
+
+ifeq ($(TARGET),sim)
+DFLAGS      = -DXT_SIMULATOR
+endif
+ifeq ($(TARGET),board)
+DFLAGS      = -DXT_BOARD
+endif
+
+IFLAGS      = \
+  -I$(FR_SRCDIR)$(S)..$(S)include -I$(FR_SRCDIR)$(S)..$(S)include$(S)private \
+  -I$(XT_SRCDIR) -I$(TSTROOT)$(S)common$(S)config_files -I$(BLDDIR)
+
+CFLAGS      = -O2 -g
+CCFLAGS     = $(CFLAGS) -Wall -mno-coproc -mlongcalls -ffunction-sections -mno-l32r-flix $(DFLAGS)
+ASFLAGS     = $(CCFLAGS)
+
+# Include dependency rules (generated using -MD)
+
+-include $(wildcard $(BLDDIR)/*.d)
+
+# Targets
+
+all : mkdir $(OSLIB)
+
+mkdir : $(BLDDIR)/.mkdir
+
+$(BLDDIR)/.mkdir :
+	@$(MKPATH) $(BLDDIR)
+	@echo "" > $@
+	-$(CP) $(CONFIGDIR)/xtensa-elf/include/sys/reent.h $(BLDDIR)/reent.h
+
+$(OSLIB) : $(LIB_O_LIST)
+	$(AR) -rs $@ $^
+
+$(BLDDIR)/%.o : %.c
+	$(CC) $(CCFLAGS) $(IFLAGS) -MD -MF $(subst .o,.d,$@) -c -o $@ $<
+
+$(BLDDIR)/%.o : %.S
+	$(CC) $(ASFLAGS) $(IFLAGS) -MD -MF $(subst .o,.d,$@) -c -o $@ $<
+
+clean :
+	$(RM_R) $(BLDDIR)
+
+clean_all :
+	$(RM_R) $(BLDROOT)
+
+.PHONY : all mkdir clean clean_all
+

kernel/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/port.c

@@ -0,0 +1,208 @@
+/*
+ * FreeRTOS Kernel V10.5.1
+ * Copyright (C) 2015-2019 Cadence Design Systems, Inc.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#include <stdlib.h>
+#include <xtensa/config/core.h>
+
+#include "xtensa_rtos.h"
+
+#include "FreeRTOS.h"
+#include "task.h"
+
+
+/* Defined in portasm.h */
+extern void _frxt_tick_timer_init(void);
+
+/* Defined in xtensa_context.S */
+extern void _xt_coproc_init(void);
+
+
+/*-----------------------------------------------------------*/
+
+/* We require the address of the pxCurrentTCB variable, but don't want to know
+any details of its type. */
+typedef void TCB_t;
+extern volatile TCB_t * volatile pxCurrentTCB;
+
+unsigned port_xSchedulerRunning = 0; // Duplicate of inaccessible xSchedulerRunning; needed at startup to avoid counting nesting
+unsigned port_interruptNesting = 0;  // Interrupt nesting level
+
+/*-----------------------------------------------------------*/
+
+// User exception dispatcher when exiting
+void _xt_user_exit(void);
+
+/*
+ * Stack initialization
+ */
+#if portUSING_MPU_WRAPPERS
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged )
+#else
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+#endif
+{
+    StackType_t * sp;
+    StackType_t * tp;
+    XtExcFrame * frame;
+
+    #if XCHAL_CP_NUM > 0
+        uint32_t * p;
+    #endif
+
+    /* Create interrupt stack frame aligned to 16 byte boundary */
+    sp = ( StackType_t * ) ( ( ( UBaseType_t ) pxTopOfStack - XT_CP_SIZE - XT_STK_FRMSZ ) & ~0xf );
+
+    /* Clear the entire frame (do not use memset() because we don't depend on C library) */
+    for( tp = sp; tp <= pxTopOfStack; ++tp )
+    {
+        *tp = 0;
+    }
+
+    frame = ( XtExcFrame * ) sp;
+
+    /* Explicitly initialize certain saved registers */
+    frame->pc = ( UBaseType_t ) pxCode;             /* task entrypoint                */
+    frame->a0 = 0;                                  /* to terminate GDB backtrace     */
+    frame->a1 = ( UBaseType_t ) sp + XT_STK_FRMSZ;  /* physical top of stack frame    */
+    frame->exit = ( UBaseType_t ) _xt_user_exit;    /* user exception exit dispatcher */
+
+    /* Set initial PS to int level 0, EXCM disabled ('rfe' will enable), user mode. */
+    /* Also set entry point argument parameter. */
+    #ifdef __XTENSA_CALL0_ABI__
+        frame->a2 = ( UBaseType_t ) pvParameters;
+        frame->ps = PS_UM | PS_EXCM;
+    #else
+        /* + for windowed ABI also set WOE and CALLINC (pretend task was 'call4'd). */
+        frame->a6 = ( UBaseType_t ) pvParameters;
+        frame->ps = PS_UM | PS_EXCM | PS_WOE | PS_CALLINC( 1 );
+    #endif
+
+    #ifdef XT_USE_SWPRI
+        /* Set the initial virtual priority mask value to all 1's. */
+        frame->vpri = 0xFFFFFFFF;
+    #endif
+
+    #if XCHAL_CP_NUM > 0
+        /* Init the coprocessor save area (see xtensa_context.h) */
+
+        /* No access to TCB here, so derive indirectly. Stack growth is top to bottom.
+         * //p = (uint32_t *) xMPUSettings->coproc_area;
+         */
+        p = ( uint32_t * ) ( ( ( uint32_t ) pxTopOfStack - XT_CP_SIZE ) & ~0xf );
+        configASSERT( ( uint32_t ) p >= frame->a1 );
+        p[ 0 ] = 0;
+        p[ 1 ] = 0;
+        p[ 2 ] = ( ( ( uint32_t ) p ) + 12 + XCHAL_TOTAL_SA_ALIGN - 1 ) & -XCHAL_TOTAL_SA_ALIGN;
+    #endif
+
+    return sp;
+}
+
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* It is unlikely that the Xtensa port will get stopped.  If required simply
+	disable the tick interrupt here. */
+}
+
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+	// Interrupts are disabled at this point and stack contains PS with enabled interrupts when task context is restored
+
+	#if XCHAL_CP_NUM > 0
+	/* Initialize co-processor management for tasks. Leave CPENABLE alone. */
+	_xt_coproc_init();
+	#endif
+
+	/* Init the tick divisor value */
+	_xt_tick_divisor_init();
+
+	/* Setup the hardware to generate the tick. */
+	_frxt_tick_timer_init();
+
+	#if XT_USE_THREAD_SAFE_CLIB
+	// Init C library
+	vPortClibInit();
+	#endif
+
+	port_xSchedulerRunning = 1;
+
+	// Cannot be directly called from C; never returns
+	__asm__ volatile ("call0    _frxt_dispatch\n");
+
+	/* Should not get here. */
+	return pdTRUE;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortSysTickHandler( void )
+{
+	BaseType_t ret;
+	uint32_t interruptMask;
+
+	portbenchmarkIntLatency();
+
+	/* Interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY must be
+	 * disabled before calling xTaskIncrementTick as it access the
+	 * kernel lists. */
+	interruptMask = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		ret = xTaskIncrementTick();
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( interruptMask );
+
+	portYIELD_FROM_ISR( ret );
+
+	return ret;
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Used to set coprocessor area in stack. Current hack is to reuse MPU pointer for coprocessor area.
+ */
+#if portUSING_MPU_WRAPPERS
+void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
+                                const struct xMEMORY_REGION * const xRegions,
+                                StackType_t * pxBottomOfStack,
+                                uint32_t ulStackDepth )
+{
+    #if XCHAL_CP_NUM > 0
+        xMPUSettings->coproc_area = ( StackType_t * ) ( ( uint32_t ) ( pxBottomOfStack + ulStackDepth - 1 ));
+        xMPUSettings->coproc_area = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) xMPUSettings->coproc_area ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) );
+        xMPUSettings->coproc_area = ( StackType_t * ) ( ( ( uint32_t ) xMPUSettings->coproc_area - XT_CP_SIZE ) & ~0xf );
+
+        /* NOTE: we cannot initialize the coprocessor save area here because FreeRTOS is going to
+         * clear the stack area after we return. This is done in pxPortInitialiseStack().
+         */
+    #endif
+}
+#endif /* if portUSING_MPU_WRAPPERS */

kernel/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/portasm.S

@@ -0,0 +1,601 @@
+/*
+ * FreeRTOS Kernel V10.5.1
+ * Copyright (C) 2015-2019 Cadence Design Systems, Inc.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#include "xtensa_rtos.h"
+
+#define TOPOFSTACK_OFFS                 0x00    /* StackType_t *pxTopOfStack */
+#define CP_TOPOFSTACK_OFFS              0x04    /* xMPU_SETTINGS.coproc_area */
+
+.extern pxCurrentTCB
+
+
+/*
+*******************************************************************************
+* Interrupt stack. The size of the interrupt stack is determined by the config
+* parameter "configISR_STACK_SIZE" in FreeRTOSConfig.h
+*******************************************************************************
+*/
+    .data
+    .align      16
+    .global     port_IntStack
+port_IntStack:
+    .space      configISR_STACK_SIZE
+port_IntStackTop:
+    .word       0
+port_switch_flag:
+    .word       0
+
+    .text
+/*
+*******************************************************************************
+* _frxt_setup_switch
+* void _frxt_setup_switch(void);
+*
+* Sets an internal flag indicating that a task switch is required on return
+* from interrupt handling.
+*
+*******************************************************************************
+*/
+    .global     _frxt_setup_switch
+    .type       _frxt_setup_switch,@function
+    .align      4
+_frxt_setup_switch:
+
+    ENTRY(16)
+
+    movi    a2, port_switch_flag
+    movi    a3, 1
+    s32i    a3, a2, 0
+
+    RET(16)
+
+/*
+*******************************************************************************
+*                                            _frxt_int_enter
+*                                       void _frxt_int_enter(void)
+*
+* Implements the Xtensa RTOS porting layer's XT_RTOS_INT_ENTER function for
+* freeRTOS. Saves the rest of the interrupt context (not already saved).
+* May only be called from assembly code by the 'call0' instruction, with
+* interrupts disabled.
+* See the detailed description of the XT_RTOS_ENTER macro in xtensa_rtos.h.
+*
+*******************************************************************************
+*/
+    .globl  _frxt_int_enter
+    .type   _frxt_int_enter,@function
+    .align  4
+_frxt_int_enter:
+
+    /* Save a12-13 in the stack frame as required by _xt_context_save. */
+    s32i    a12, a1, XT_STK_A12
+    s32i    a13, a1, XT_STK_A13
+
+    /* Save return address in a safe place (free a0). */
+    mov     a12, a0
+
+    /* Save the rest of the interrupted context (preserves A12-13). */
+    call0   _xt_context_save
+
+    /*
+    Save interrupted task's SP in TCB only if not nesting.
+    Manage nesting directly rather than call the generic IntEnter()
+    (in windowed ABI we can't call a C function here anyway because PS.EXCM is still set).
+    */
+    movi    a2,  port_xSchedulerRunning
+    movi    a3,  port_interruptNesting
+    l32i    a2,  a2, 0                  /* a2 = port_xSchedulerRunning     */
+    beqz    a2,  1f                     /* scheduler not running, no tasks */
+    l32i    a2,  a3, 0                  /* a2 = port_interruptNesting      */
+    addi    a2,  a2, 1                  /* increment nesting count         */
+    s32i    a2,  a3, 0                  /* save nesting count              */
+    bnei    a2,  1, .Lnested            /* !=0 before incr, so nested      */
+
+    movi    a2,  pxCurrentTCB
+    l32i    a2,  a2, 0                  /* a2 = current TCB                */
+    beqz    a2,  1f
+    s32i    a1,  a2, TOPOFSTACK_OFFS    /* pxCurrentTCB->pxTopOfStack = SP */
+    movi    a1,  port_IntStackTop       /* a1 = top of intr stack          */
+
+.Lnested:
+1:
+    mov     a0,  a12                    /* restore return addr and return  */
+    ret
+
+/*
+*******************************************************************************
+*                                            _frxt_int_exit
+*                                       void _frxt_int_exit(void)
+*
+* Implements the Xtensa RTOS porting layer's XT_RTOS_INT_EXIT function for
+* FreeRTOS. If required, calls vPortYieldFromInt() to perform task context
+* switching, restore the (possibly) new task's context, and return to the
+* exit dispatcher saved in the task's stack frame at XT_STK_EXIT.
+* May only be called from assembly code by the 'call0' instruction. Does not
+* return to caller.
+* See the description of the XT_RTOS_ENTER macro in xtensa_rtos.h.
+*
+*******************************************************************************
+*/
+    .globl  _frxt_int_exit
+    .type   _frxt_int_exit,@function
+    .align  4
+_frxt_int_exit:
+
+    movi    a2,  port_xSchedulerRunning
+    movi    a3,  port_interruptNesting
+    rsil    a0,  XCHAL_EXCM_LEVEL       /* lock out interrupts             */
+    l32i    a2,  a2, 0                  /* a2 = port_xSchedulerRunning     */
+    beqz    a2,  .Lnoswitch             /* scheduler not running, no tasks */
+    l32i    a2,  a3, 0                  /* a2 = port_interruptNesting      */
+    addi    a2,  a2, -1                 /* decrement nesting count         */
+    s32i    a2,  a3, 0                  /* save nesting count              */
+    bnez    a2,  .Lnesting              /* !=0 after decr so still nested  */
+
+    movi    a2,  pxCurrentTCB
+    l32i    a2,  a2, 0                  /* a2 = current TCB                */
+    beqz    a2,  1f                     /* no task ? go to dispatcher      */
+    l32i    a1,  a2, TOPOFSTACK_OFFS    /* SP = pxCurrentTCB->pxTopOfStack */
+
+    movi    a2,  port_switch_flag       /* address of switch flag          */
+    l32i    a3,  a2, 0                  /* a3 = port_switch_flag           */
+    beqz    a3,  .Lnoswitch             /* flag = 0 means no switch reqd   */
+    movi    a3,  0
+    s32i    a3,  a2, 0                  /* zero out the flag for next time */
+
+1:
+    /*
+    Call0 ABI callee-saved regs a12-15 need to be saved before possible preemption.
+    However a12-13 were already saved by _frxt_int_enter().
+    */
+    #ifdef __XTENSA_CALL0_ABI__
+    s32i    a14, a1, XT_STK_A14
+    s32i    a15, a1, XT_STK_A15
+    #endif
+
+    #ifdef __XTENSA_CALL0_ABI__
+    call0   vPortYieldFromInt       /* call dispatch inside the function; never returns */
+    #else
+    call4   vPortYieldFromInt       /* this one returns */
+    call0   _frxt_dispatch          /* tail-call dispatcher */
+    /* Never returns here. */
+    #endif
+
+.Lnoswitch:
+    /*
+    If we came here then about to resume the interrupted task.
+    */
+
+.Lnesting:
+    /*
+    We come here only if there was no context switch, that is if this
+    is a nested interrupt, or the interrupted task was not preempted.
+    In either case there's no need to load the SP.
+    */
+
+    /* Restore full context from interrupt stack frame */
+    call0   _xt_context_restore
+
+    /*
+    Must return via the exit dispatcher corresponding to the entrypoint from which
+    this was called. Interruptee's A0, A1, PS, PC are restored and the interrupt
+    stack frame is deallocated in the exit dispatcher.
+    */
+    l32i    a0,  a1, XT_STK_EXIT
+    ret
+
+
+/*
+**********************************************************************************************************
+*                                           _frxt_timer_int
+*                                      void _frxt_timer_int(void)
+*
+* Implements the Xtensa RTOS porting layer's XT_RTOS_TIMER_INT function for FreeRTOS.
+* Called every timer interrupt.
+* Manages the tick timer and calls xPortSysTickHandler() every tick.
+* See the detailed description of the XT_RTOS_ENTER macro in xtensa_rtos.h.
+*
+* Callable from C (obeys ABI conventions). Implemented in assmebly code for performance.
+*
+**********************************************************************************************************
+*/
+    .globl  _frxt_timer_int
+    .type   _frxt_timer_int,@function
+    .align  4
+_frxt_timer_int:
+
+    /*
+    Xtensa timers work by comparing a cycle counter with a preset value.  Once the match occurs
+    an interrupt is generated, and the handler has to set a new cycle count into the comparator.
+    To avoid clock drift due to interrupt latency, the new cycle count is computed from the old,
+    not the time the interrupt was serviced. However if a timer interrupt is ever serviced more
+    than one tick late, it is necessary to process multiple ticks until the new cycle count is
+    in the future, otherwise the next timer interrupt would not occur until after the cycle
+    counter had wrapped (2^32 cycles later).
+
+    do {
+        ticks++;
+        old_ccompare = read_ccompare_i();
+        write_ccompare_i( old_ccompare + divisor );
+        service one tick;
+        diff = read_ccount() - old_ccompare;
+    } while ( diff > divisor );
+    */
+
+    ENTRY(16)
+
+.L_xt_timer_int_catchup:
+
+    /* Update the timer comparator for the next tick. */
+    #ifdef XT_CLOCK_FREQ
+    movi    a2, XT_TICK_DIVISOR         /* a2 = comparator increment          */
+    #else
+    movi    a3, _xt_tick_divisor
+    l32i    a2, a3, 0                   /* a2 = comparator increment          */
+    #endif
+    rsr     a3, XT_CCOMPARE             /* a3 = old comparator value          */
+    add     a4, a3, a2                  /* a4 = new comparator value          */
+    wsr     a4, XT_CCOMPARE             /* update comp. and clear interrupt   */
+    esync
+
+    #ifdef __XTENSA_CALL0_ABI__
+    /* Preserve a2 and a3 across C calls. */
+    s32i    a2, sp, 4
+    s32i    a3, sp, 8
+    #endif
+
+    /* Call the FreeRTOS tick handler (see port.c). */
+    #ifdef __XTENSA_CALL0_ABI__
+    call0   xPortSysTickHandler
+    #else
+    call4   xPortSysTickHandler
+    #endif
+
+    #ifdef __XTENSA_CALL0_ABI__
+    /* Restore a2 and a3. */
+    l32i    a2, sp, 4
+    l32i    a3, sp, 8
+    #endif
+
+    /* Check if we need to process more ticks to catch up. */
+    esync                               /* ensure comparator update complete  */
+    rsr     a4, CCOUNT                  /* a4 = cycle count                   */
+    sub     a4, a4, a3                  /* diff = ccount - old comparator     */
+    blt     a2, a4, .L_xt_timer_int_catchup  /* repeat while diff > divisor */
+
+    RET(16)
+
+    /*
+**********************************************************************************************************
+*                                           _frxt_tick_timer_init
+*                                      void _frxt_tick_timer_init(void)
+*
+* Initialize timer and timer interrrupt handler (_xt_tick_divisor_init() has already been been called).
+* Callable from C (obeys ABI conventions on entry).
+*
+**********************************************************************************************************
+*/
+    .globl  _frxt_tick_timer_init
+    .type   _frxt_tick_timer_init,@function
+    .align  4
+_frxt_tick_timer_init:
+
+    ENTRY(16)
+
+    /* Set up the periodic tick timer (assume enough time to complete init). */
+    #ifdef XT_CLOCK_FREQ
+    movi    a3, XT_TICK_DIVISOR
+    #else
+    movi    a2, _xt_tick_divisor
+    l32i    a3, a2, 0
+    #endif
+    rsr     a2, CCOUNT              /* current cycle count */
+    add     a2, a2, a3              /* time of first timer interrupt */
+    wsr     a2, XT_CCOMPARE         /* set the comparator */
+
+    /*
+    Enable the timer interrupt at the device level. Don't write directly
+    to the INTENABLE register because it may be virtualized.
+    */
+    #ifdef __XTENSA_CALL0_ABI__
+    movi    a2, XT_TIMER_INTEN
+    call0   xt_ints_on
+    #else
+    movi    a6, XT_TIMER_INTEN
+    call4   xt_ints_on
+    #endif
+
+    RET(16)
+
+/*
+**********************************************************************************************************
+*                                    DISPATCH THE HIGH READY TASK
+*                                     void _frxt_dispatch(void)
+*
+* Switch context to the highest priority ready task, restore its state and dispatch control to it.
+*
+* This is a common dispatcher that acts as a shared exit path for all the context switch functions
+* including vPortYield() and vPortYieldFromInt(), all of which tail-call this dispatcher
+* (for windowed ABI vPortYieldFromInt() calls it indirectly via _frxt_int_exit() ).
+*
+* The Xtensa port uses different stack frames for solicited and unsolicited task suspension (see
+* comments on stack frames in xtensa_context.h). This function restores the state accordingly.
+* If restoring a task that solicited entry, restores the minimal state and leaves CPENABLE clear.
+* If restoring a task that was preempted, restores all state including the task's CPENABLE.
+*
+* Entry:
+*   pxCurrentTCB  points to the TCB of the task to suspend,
+*   Because it is tail-called without a true function entrypoint, it needs no 'entry' instruction.
+*
+* Exit:
+*   If incoming task called vPortYield() (solicited), this function returns as if from vPortYield().
+*   If incoming task was preempted by an interrupt, this function jumps to exit dispatcher.
+*
+**********************************************************************************************************
+*/
+    .globl  _frxt_dispatch
+    .type   _frxt_dispatch,@function
+    .align  4
+_frxt_dispatch:
+
+    #ifdef __XTENSA_CALL0_ABI__
+    call0   vTaskSwitchContext  // Get next TCB to resume
+    movi    a2, pxCurrentTCB
+    #else
+    movi    a2, pxCurrentTCB
+    call4   vTaskSwitchContext  // Get next TCB to resume
+    #endif
+    l32i    a3,  a2, 0
+    l32i    sp,  a3, TOPOFSTACK_OFFS     /* SP = next_TCB->pxTopOfStack;  */
+    s32i    a3,  a2, 0
+
+    /* Determine the type of stack frame. */
+    l32i    a2,  sp, XT_STK_EXIT        /* exit dispatcher or solicited flag */
+    bnez    a2,  .L_frxt_dispatch_stk
+
+.L_frxt_dispatch_sol:
+
+    /* Solicited stack frame. Restore minimal context and return from vPortYield(). */
+    l32i    a3,  sp, XT_SOL_PS
+    #ifdef __XTENSA_CALL0_ABI__
+    l32i    a12, sp, XT_SOL_A12
+    l32i    a13, sp, XT_SOL_A13
+    l32i    a14, sp, XT_SOL_A14
+    l32i    a15, sp, XT_SOL_A15
+    #endif
+    l32i    a0,  sp, XT_SOL_PC
+    #if XCHAL_CP_NUM > 0
+    /* Ensure wsr.CPENABLE is complete (should be, it was cleared on entry). */
+    rsync
+    #endif
+    /* As soons as PS is restored, interrupts can happen. No need to sync PS. */
+    wsr     a3,  PS
+    #ifdef __XTENSA_CALL0_ABI__
+    addi    sp,  sp, XT_SOL_FRMSZ
+    ret
+    #else
+    retw
+    #endif
+
+.L_frxt_dispatch_stk:
+
+    #if XCHAL_CP_NUM > 0
+    /* Restore CPENABLE from task's co-processor save area. */
+    movi    a3, pxCurrentTCB            /* cp_state =                       */
+    l32i    a3, a3, 0
+    l32i    a2, a3, CP_TOPOFSTACK_OFFS     /* StackType_t                       *pxStack; */
+    l16ui    a3, a2, XT_CPENABLE         /* CPENABLE = cp_state->cpenable;   */
+    wsr     a3, CPENABLE
+    #endif
+
+    /* Interrupt stack frame. Restore full context and return to exit dispatcher. */
+    call0   _xt_context_restore
+
+    /* In Call0 ABI, restore callee-saved regs (A12, A13 already restored). */
+    #ifdef __XTENSA_CALL0_ABI__
+    l32i    a14, sp, XT_STK_A14
+    l32i    a15, sp, XT_STK_A15
+    #endif
+
+    #if XCHAL_CP_NUM > 0
+    /* Ensure wsr.CPENABLE has completed. */
+    rsync
+    #endif
+
+    /*
+    Must return via the exit dispatcher corresponding to the entrypoint from which
+    this was called. Interruptee's A0, A1, PS, PC are restored and the interrupt
+    stack frame is deallocated in the exit dispatcher.
+    */
+    l32i    a0, sp, XT_STK_EXIT
+    ret
+
+
+/*
+**********************************************************************************************************
+*                            PERFORM A SOLICTED CONTEXT SWITCH (from a task)
+*                                        void vPortYield(void)
+*
+* This function saves the minimal state needed for a solicited task suspension, clears CPENABLE,
+* then tail-calls the dispatcher _frxt_dispatch() to perform the actual context switch
+*
+* At Entry:
+*   pxCurrentTCB  points to the TCB of the task to suspend
+*   Callable from C (obeys ABI conventions on entry).
+*
+* Does not return to caller.
+*
+**********************************************************************************************************
+*/
+    .globl  vPortYield
+    .type   vPortYield,@function
+    .align  4
+vPortYield:
+
+    #ifdef __XTENSA_CALL0_ABI__
+    addi    sp,  sp, -XT_SOL_FRMSZ
+    #else
+    entry   sp,  XT_SOL_FRMSZ
+    #endif
+
+    rsr     a2,  PS
+    s32i    a0,  sp, XT_SOL_PC
+    s32i    a2,  sp, XT_SOL_PS
+    #ifdef __XTENSA_CALL0_ABI__
+    s32i    a12, sp, XT_SOL_A12         /* save callee-saved registers      */
+    s32i    a13, sp, XT_SOL_A13
+    s32i    a14, sp, XT_SOL_A14
+    s32i    a15, sp, XT_SOL_A15
+    #else
+    /* Spill register windows. Calling xthal_window_spill() causes extra    */
+    /* spills and reloads, so we will set things up to call the _nw version */
+    /* instead to save cycles.                                              */
+    movi    a6,  ~(PS_WOE_MASK|PS_INTLEVEL_MASK)  /* spills a4-a7 if needed */
+    and     a2,  a2, a6                           /* clear WOE, INTLEVEL    */
+    addi    a2,  a2, XCHAL_EXCM_LEVEL             /* set INTLEVEL           */
+    wsr     a2,  PS
+    rsync
+    call0   xthal_window_spill_nw
+    l32i    a2,  sp, XT_SOL_PS                    /* restore PS             */
+    wsr     a2,  PS
+    #endif
+
+    rsil    a2,  XCHAL_EXCM_LEVEL       /* disable low/med interrupts       */
+
+    #if XCHAL_CP_NUM > 0
+    /* Save coprocessor callee-saved state (if any). At this point CPENABLE */
+    /* should still reflect which CPs were in use (enabled).                */
+    call0   _xt_coproc_savecs
+    #endif
+
+    movi    a2,  pxCurrentTCB
+    movi    a3,  0
+    l32i    a2,  a2, 0                  /* a2 = pxCurrentTCB                */
+    s32i    a3,  sp, XT_SOL_EXIT        /* 0 to flag as solicited frame     */
+    s32i    sp,  a2, TOPOFSTACK_OFFS    /* pxCurrentTCB->pxTopOfStack = SP  */
+
+    #if XCHAL_CP_NUM > 0
+    /* Clear CPENABLE, also in task's co-processor state save area. */
+    l32i    a2,  a2, CP_TOPOFSTACK_OFFS /* a2 = pxCurrentTCB->cp_state      */
+    movi    a3,  0
+    wsr     a3,  CPENABLE
+    beqz    a2,  1f
+    s16i     a3,  a2, XT_CPENABLE        /* clear saved cpenable             */
+1:
+    #endif
+
+    /* Tail-call dispatcher. */
+    call0   _frxt_dispatch
+    /* Never reaches here. */
+
+
+/*
+**********************************************************************************************************
+*                         PERFORM AN UNSOLICITED CONTEXT SWITCH (from an interrupt)
+*                                        void vPortYieldFromInt(void)
+*
+* This calls the context switch hook (removed), saves and clears CPENABLE, then tail-calls the dispatcher
+* _frxt_dispatch() to perform the actual context switch.
+*
+* At Entry:
+*   Interrupted task context has been saved in an interrupt stack frame at pxCurrentTCB->pxTopOfStack.
+*   pxCurrentTCB  points to the TCB of the task to suspend,
+*   Callable from C (obeys ABI conventions on entry).
+*
+* At Exit:
+*   Windowed ABI defers the actual context switch until the stack is unwound to interrupt entry.
+*   Call0 ABI tail-calls the dispatcher directly (no need to unwind) so does not return to caller.
+*
+**********************************************************************************************************
+*/
+    .globl  vPortYieldFromInt
+    .type   vPortYieldFromInt,@function
+    .align  4
+vPortYieldFromInt:
+
+    ENTRY(16)
+
+    #if XCHAL_CP_NUM > 0
+    /* Save CPENABLE in task's co-processor save area, and clear CPENABLE.  */
+    movi    a3, pxCurrentTCB            /* cp_state =                       */
+    l32i    a3, a3, 0
+    l32i    a2, a3, CP_TOPOFSTACK_OFFS
+
+    rsr     a3, CPENABLE
+    s16i     a3, a2, XT_CPENABLE         /* cp_state->cpenable = CPENABLE;   */
+    movi    a3, 0
+    wsr     a3, CPENABLE                /* disable all co-processors        */
+    #endif
+
+    #ifdef __XTENSA_CALL0_ABI__
+    /* Tail-call dispatcher. */
+    call0   _frxt_dispatch
+    /* Never reaches here. */
+    #else
+    RET(16)
+    #endif
+
+/*
+**********************************************************************************************************
+*                                        _frxt_task_coproc_state
+*                                   void _frxt_task_coproc_state(void)
+*
+* Implements the Xtensa RTOS porting layer's XT_RTOS_CP_STATE function for FreeRTOS.
+*
+* May only be called when a task is running, not within an interrupt handler (returns 0 in that case).
+* May only be called from assembly code by the 'call0' instruction. Does NOT obey ABI conventions.
+* Returns in A15 a pointer to the base of the co-processor state save area for the current task.
+* See the detailed description of the XT_RTOS_ENTER macro in xtensa_rtos.h.
+*
+**********************************************************************************************************
+*/
+#if XCHAL_CP_NUM > 0
+
+    .globl  _frxt_task_coproc_state
+    .type   _frxt_task_coproc_state,@function
+    .align  4
+_frxt_task_coproc_state:
+
+    movi    a15, port_xSchedulerRunning /* if (port_xSchedulerRunning              */
+    l32i    a15, a15, 0
+    beqz    a15, 1f
+    movi    a15, port_interruptNesting  /* && port_interruptNesting == 0           */
+    l32i    a15, a15, 0
+    bnez    a15, 1f
+    movi    a15, pxCurrentTCB
+    l32i    a15, a15, 0                 /* && pxCurrentTCB != 0) {                 */
+    beqz    a15, 2f
+    l32i    a15, a15, CP_TOPOFSTACK_OFFS
+    ret
+
+1:  movi    a15, 0
+2:  ret
+
+#endif /* XCHAL_CP_NUM > 0 */
+

kernel/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/portbenchmark.h

@@ -0,0 +1,51 @@
+/*
+ * FreeRTOS Kernel V10.5.1
+ * Copyright (C) 2015-2019 Cadence Design Systems, Inc.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/*
+ * This utility helps benchmarking interrupt latency and context switches.
+ * In order to enable it, set configBENCHMARK to 1 in FreeRTOSConfig.h.
+ * You will also need to download the FreeRTOS_trace patch that contains
+ * portbenchmark.c and the complete version of portbenchmark.h
+ */
+
+#ifndef PORTBENCHMARK_H
+#define PORTBENCHMARK_H
+
+#if configBENCHMARK
+    #error "You need to download the FreeRTOS_trace patch that overwrites this file"
+#endif
+
+#define portbenchmarkINTERRUPT_DISABLE()
+#define portbenchmarkINTERRUPT_RESTORE(newstate)
+#define portbenchmarkIntLatency()
+#define portbenchmarkIntWait()
+#define portbenchmarkReset()
+#define portbenchmarkPrint()
+
+#endif /* PORTBENCHMARK */

kernel/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/portclib.c

@@ -0,0 +1,230 @@
+/*
+ * FreeRTOS Kernel V10.5.1
+ * Copyright (C) 2015-2019 Cadence Design Systems, Inc.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#include "FreeRTOS.h"
+
+#if XT_USE_THREAD_SAFE_CLIB
+
+#if XSHAL_CLIB == XTHAL_CLIB_XCLIB
+
+#include <errno.h>
+#include <sys/reent.h>
+
+#include "semphr.h"
+
+typedef SemaphoreHandle_t       _Rmtx;
+
+//-----------------------------------------------------------------------------
+//  Override this and set to nonzero to enable locking.
+//-----------------------------------------------------------------------------
+int32_t _xclib_use_mt = 1;
+
+
+//-----------------------------------------------------------------------------
+//  Init lock.
+//-----------------------------------------------------------------------------
+void
+_Mtxinit(_Rmtx * mtx)
+{
+    *mtx = xSemaphoreCreateRecursiveMutex();
+}
+
+//-----------------------------------------------------------------------------
+//  Destroy lock.
+//-----------------------------------------------------------------------------
+void
+_Mtxdst(_Rmtx * mtx)
+{
+    if ((mtx != NULL) && (*mtx != NULL)) {
+        vSemaphoreDelete(*mtx);
+    }
+}
+
+//-----------------------------------------------------------------------------
+//  Lock.
+//-----------------------------------------------------------------------------
+void
+_Mtxlock(_Rmtx * mtx)
+{
+    if ((mtx != NULL) && (*mtx != NULL)) {
+        xSemaphoreTakeRecursive(*mtx, portMAX_DELAY);
+    }
+}
+
+//-----------------------------------------------------------------------------
+//  Unlock.
+//-----------------------------------------------------------------------------
+void
+_Mtxunlock(_Rmtx * mtx)
+{
+    if ((mtx != NULL) && (*mtx != NULL)) {
+        xSemaphoreGiveRecursive(*mtx);
+    }
+}
+
+//-----------------------------------------------------------------------------
+//  Called by malloc() to allocate blocks of memory from the heap.
+//-----------------------------------------------------------------------------
+void *
+_sbrk_r (struct _reent * reent, int32_t incr)
+{
+    extern char _end;
+    extern char _heap_sentry;
+    static char * _heap_sentry_ptr = &_heap_sentry;
+    static char * heap_ptr;
+    char * base;
+
+    if (!heap_ptr)
+        heap_ptr = (char *) &_end;
+
+    base = heap_ptr;
+    if (heap_ptr + incr >= _heap_sentry_ptr) {
+        reent->_errno = ENOMEM;
+        return (char *) -1;
+    }
+
+    heap_ptr += incr;
+    return base;
+}
+
+//-----------------------------------------------------------------------------
+//  Global initialization for C library.
+//-----------------------------------------------------------------------------
+void
+vPortClibInit(void)
+{
+}
+
+//-----------------------------------------------------------------------------
+//  Per-thread cleanup stub provided for linking, does nothing.
+//-----------------------------------------------------------------------------
+void
+_reclaim_reent(void * ptr)
+{
+}
+
+#endif /* XSHAL_CLIB == XTHAL_CLIB_XCLIB */
+
+#if XSHAL_CLIB == XTHAL_CLIB_NEWLIB
+
+#include <errno.h>
+#include <malloc.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "semphr.h"
+
+static SemaphoreHandle_t xClibMutex;
+static uint32_t  ulClibInitDone = 0;
+
+//-----------------------------------------------------------------------------
+//  Get C library lock.
+//-----------------------------------------------------------------------------
+void
+__malloc_lock(struct _reent * ptr)
+{
+    if (!ulClibInitDone)
+        return;
+
+    xSemaphoreTakeRecursive(xClibMutex, portMAX_DELAY);
+}
+
+//-----------------------------------------------------------------------------
+//  Release C library lock.
+//-----------------------------------------------------------------------------
+void
+__malloc_unlock(struct _reent * ptr)
+{
+    if (!ulClibInitDone)
+        return;
+
+    xSemaphoreGiveRecursive(xClibMutex);
+}
+
+//-----------------------------------------------------------------------------
+//  Lock for environment. Since we have only one global lock we can just call
+//  the malloc() lock function.
+//-----------------------------------------------------------------------------
+void
+__env_lock(struct _reent * ptr)
+{
+    __malloc_lock(ptr);
+}
+
+
+//-----------------------------------------------------------------------------
+//  Unlock environment.
+//-----------------------------------------------------------------------------
+void
+__env_unlock(struct _reent * ptr)
+{
+    __malloc_unlock(ptr);
+}
+
+//-----------------------------------------------------------------------------
+//  Called by malloc() to allocate blocks of memory from the heap.
+//-----------------------------------------------------------------------------
+void *
+_sbrk_r (struct _reent * reent, int32_t incr)
+{
+    extern char _end;
+    extern char _heap_sentry;
+    static char * _heap_sentry_ptr = &_heap_sentry;
+    static char * heap_ptr;
+    char * base;
+
+    if (!heap_ptr)
+        heap_ptr = (char *) &_end;
+
+    base = heap_ptr;
+    if (heap_ptr + incr >= _heap_sentry_ptr) {
+        reent->_errno = ENOMEM;
+        return (char *) -1;
+    }
+
+    heap_ptr += incr;
+    return base;
+}
+
+//-----------------------------------------------------------------------------
+//  Global initialization for C library.
+//-----------------------------------------------------------------------------
+void
+vPortClibInit(void)
+{
+    configASSERT(!ulClibInitDone);
+
+    xClibMutex = xSemaphoreCreateRecursiveMutex();
+    ulClibInitDone  = 1;
+}
+
+#endif /* XSHAL_CLIB == XTHAL_CLIB_NEWLIB */
+
+#endif /* XT_USE_THREAD_SAFE_CLIB */