/*
 * $QNXLicenseC:
 * Copyright 2018 NXP
 * Copyright 2021, QNX Software Systems.
 * Licensed under the Apache License, Version 2.0 (the "License"). You
 * may not reproduce, modify or distribute this software except in
 * compliance with the License. You may obtain a copy of the License
 * at: http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" basis,
 * WITHOUT WARRANTIES OF ANY KIND, either express or implied.
 *
 * This file may contain contributions from others, either as
 * contributors under the License or as licensors under other terms.
 * Please review this entire file for other proprietary rights or license
 * notices, as well as the QNX Development Suite License Guide at
 * http://licensing.qnx.com/license-guide/ for other information.
 * $
 */

#ifndef IMX_CCM_ANALOG_H_
#define IMX_CCM_ANALOG_H_

/* Register AUDIO_PLL1_GEN_CTRL - AUDIO PLL1 General Function Control Register */
#define IMX_CCM_ANALOG_AUDIO_PLL1_GEN_CTRL       0
/* Field PLL_REF_CLK_SEL -  */
#define IMX_CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT 0
#define IMX_CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_MASK 0x3
#define IMX_CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_REF_CLK_SEL(v) (((v) << 0) & 0x3)
/* Field PAD_CLK_SEL -  */
#define IMX_CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PAD_CLK_SEL_SHIFT 2
#define IMX_CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PAD_CLK_SEL_MASK 0xC
#define IMX_CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PAD_CLK_SEL(v) (((v) << 2) & 0xC)
/* Field PLL_BYPASS -  */
#define IMX_CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_BYPASS_SHIFT 4
#define IMX_CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_BYPASS_MASK 0x10
#define IMX_CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_BYPASS(v) (((v) << 4) & 0x10)
/* Field PLL_RST_OVERRIDE -  */
#define IMX_CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT 8
#define IMX_CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_MASK 0x100
#define IMX_CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST_OVERRIDE(v) (((v) << 8) & 0x100)
/* Field PLL_RST -  */
#define IMX_CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST_SHIFT 9
#define IMX_CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST_MASK 0x200
#define IMX_CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST(v) (((v) << 9) & 0x200)
/* Field PLL_CLKE_OVERRIDE -  */
#define IMX_CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT 12
#define IMX_CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK 0x1000
#define IMX_CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE(v) (((v) << 12) & 0x1000)
/* Field PLL_CLKE -  */
#define IMX_CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_CLKE_SHIFT 13
#define IMX_CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_CLKE_MASK 0x2000
#define IMX_CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_CLKE(v) (((v) << 13) & 0x2000)
/* Field PLL_EXT_BYPASS -  */
#define IMX_CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_EXT_BYPASS_SHIFT 16
#define IMX_CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_EXT_BYPASS_MASK 0x10000
#define IMX_CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_EXT_BYPASS(v) (((v) << 16) & 0x10000)
/* Field PLL_LOCK -  */
#define IMX_CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_LOCK_SHIFT 31
#define IMX_CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_LOCK_MASK 0x80000000
#define IMX_CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_LOCK(v) (((v) << 31) & 0x80000000)

/* Register AUDIO_PLL1_FDIV_CTL0 - AUDIO PLL1 Divide and Fraction Data Control 0 Register */
#define IMX_CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0      0x4
/* Field PLL_POST_DIV -  */
#define IMX_CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_POST_DIV_SHIFT 0
#define IMX_CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_POST_DIV_MASK 0x7
#define IMX_CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_POST_DIV(v) (((v) << 0) & 0x7)
/* Field PLL_PRE_DIV -  */
#define IMX_CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_PRE_DIV_SHIFT 4
#define IMX_CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_PRE_DIV_MASK 0x3F0
#define IMX_CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_PRE_DIV(v) (((v) << 4) & 0x3F0)
/* Field PLL_MAIN_DIV -  */
#define IMX_CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_MAIN_DIV_SHIFT 12
#define IMX_CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_MAIN_DIV_MASK 0x3FF000
#define IMX_CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_MAIN_DIV(v) (((v) << 12) & 0x3FF000)

/* Register AUDIO_PLL1_FDIV_CTL1 - AUDIO PLL1 Divide and Fraction Data Control 1 Register */
#define IMX_CCM_ANALOG_AUDIO_PLL1_FDIV_CTL1      0x8
/* Field PLL_DSM -  */
#define IMX_CCM_ANALOG_AUDIO_PLL1_FDIV_CTL1_PLL_DSM_SHIFT 0
#define IMX_CCM_ANALOG_AUDIO_PLL1_FDIV_CTL1_PLL_DSM_MASK 0xFFFF
#define IMX_CCM_ANALOG_AUDIO_PLL1_FDIV_CTL1_PLL_DSM(v) (((v) << 0) & 0xFFFF)

/* Register AUDIO_PLL1_SSCG_CTRL - AUDIO PLL1 PLL SSCG Control Register */
#define IMX_CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL      0xC
/* Field SEL_PF -  */
#define IMX_CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_SEL_PF_SHIFT 0
#define IMX_CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_SEL_PF_MASK 0x3
#define IMX_CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_SEL_PF(v) (((v) << 0) & 0x3)
/* Field PLL_MRAT_CTL -  */
#define IMX_CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_PLL_MRAT_CTL_SHIFT 4
#define IMX_CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_PLL_MRAT_CTL_MASK 0x3F0
#define IMX_CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_PLL_MRAT_CTL(v) (((v) << 4) & 0x3F0)
/* Field PLL_MFREQ_CTL -  */
#define IMX_CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_PLL_MFREQ_CTL_SHIFT 12
#define IMX_CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_PLL_MFREQ_CTL_MASK 0xFF000
#define IMX_CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_PLL_MFREQ_CTL(v) (((v) << 12) & 0xFF000)
/* Field SSCG_EN -  */
#define IMX_CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_SSCG_EN_SHIFT 31
#define IMX_CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_SSCG_EN_MASK 0x80000000
#define IMX_CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_SSCG_EN(v) (((v) << 31) & 0x80000000)

/* Register AUDIO_PLL1_MNIT_CTRL - AUDIO PLL1 PLL Monitoring Control Register */
#define IMX_CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL      0x10
/* Field ICP -  */
#define IMX_CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_ICP_SHIFT 0
#define IMX_CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_ICP_MASK 0x7
#define IMX_CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_ICP(v) (((v) << 0) & 0x7)
/* Field AFC_EN -  */
#define IMX_CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFC_EN_SHIFT 3
#define IMX_CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFC_EN_MASK 0x8
#define IMX_CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFC_EN(v) (((v) << 3) & 0x8)
/* Field EXTAFC -  */
#define IMX_CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_EXTAFC_SHIFT 4
#define IMX_CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_EXTAFC_MASK 0x1F0
#define IMX_CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_EXTAFC(v) (((v) << 4) & 0x1F0)
/* Field FEED_EN -  */
#define IMX_CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_FEED_EN_SHIFT 14
#define IMX_CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_FEED_EN_MASK 0x4000
#define IMX_CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_FEED_EN(v) (((v) << 14) & 0x4000)
/* Field FSEL -  */
#define IMX_CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_FSEL_SHIFT 15
#define IMX_CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_FSEL_MASK 0x8000
#define IMX_CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_FSEL(v) (((v) << 15) & 0x8000)
/* Field AFCINIT_SEL -  */
#define IMX_CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFCINIT_SEL_SHIFT 17
#define IMX_CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFCINIT_SEL_MASK 0x20000
#define IMX_CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFCINIT_SEL(v) (((v) << 17) & 0x20000)
/* Field PBIAS_CTRL_EN -  */
#define IMX_CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT 18
#define IMX_CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_MASK 0x40000
#define IMX_CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_PBIAS_CTRL_EN(v) (((v) << 18) & 0x40000)
/* Field PBIAS_CTRL -  */
#define IMX_CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_PBIAS_CTRL_SHIFT 19
#define IMX_CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_PBIAS_CTRL_MASK 0x80000
#define IMX_CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_PBIAS_CTRL(v) (((v) << 19) & 0x80000)
/* Field AFC_SEL -  */
#define IMX_CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFC_SEL_SHIFT 20
#define IMX_CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFC_SEL_MASK 0x100000
#define IMX_CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFC_SEL(v) (((v) << 20) & 0x100000)

/* Register AUDIO_PLL2_GEN_CTRL - AUDIO PLL2 General Function Control Register */
#define IMX_CCM_ANALOG_AUDIO_PLL2_GEN_CTRL       0x14
/* Field PLL_REF_CLK_SEL -  */
#define IMX_CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT 0
#define IMX_CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_REF_CLK_SEL_MASK 0x3
#define IMX_CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_REF_CLK_SEL(v) (((v) << 0) & 0x3)
/* Field PAD_CLK_SEL -  */
#define IMX_CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PAD_CLK_SEL_SHIFT 2
#define IMX_CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PAD_CLK_SEL_MASK 0xC
#define IMX_CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PAD_CLK_SEL(v) (((v) << 2) & 0xC)
/* Field PLL_BYPASS -  */
#define IMX_CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_BYPASS_SHIFT 4
#define IMX_CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_BYPASS_MASK 0x10
#define IMX_CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_BYPASS(v) (((v) << 4) & 0x10)
/* Field PLL_RST_OVERRIDE -  */
#define IMX_CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT 8
#define IMX_CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_RST_OVERRIDE_MASK 0x100
#define IMX_CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_RST_OVERRIDE(v) (((v) << 8) & 0x100)
/* Field PLL_RST -  */
#define IMX_CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_RST_SHIFT 9
#define IMX_CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_RST_MASK 0x200
#define IMX_CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_RST(v) (((v) << 9) & 0x200)
/* Field PLL_CLKE_OVERRIDE -  */
#define IMX_CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT 12
#define IMX_CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK 0x1000
#define IMX_CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_CLKE_OVERRIDE(v) (((v) << 12) & 0x1000)
/* Field PLL_CLKE -  */
#define IMX_CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_CLKE_SHIFT 13
#define IMX_CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_CLKE_MASK 0x2000
#define IMX_CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_CLKE(v) (((v) << 13) & 0x2000)
/* Field PLL_EXT_BYPASS -  */
#define IMX_CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_EXT_BYPASS_SHIFT 16
#define IMX_CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_EXT_BYPASS_MASK 0x10000
#define IMX_CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_EXT_BYPASS(v) (((v) << 16) & 0x10000)
/* Field PLL_LOCK -  */
#define IMX_CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_LOCK_SHIFT 31
#define IMX_CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_LOCK_MASK 0x80000000
#define IMX_CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_LOCK(v) (((v) << 31) & 0x80000000)

/* Register AUDIO_PLL2_FDIV_CTL0 - AUDIO PLL2 Divide and Fraction Data Control 0 Register */
#define IMX_CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0      0x18
/* Field PLL_POST_DIV -  */
#define IMX_CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_POST_DIV_SHIFT 0
#define IMX_CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_POST_DIV_MASK 0x7
#define IMX_CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_POST_DIV(v) (((v) << 0) & 0x7)
/* Field PLL_PRE_DIV -  */
#define IMX_CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_PRE_DIV_SHIFT 4
#define IMX_CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_PRE_DIV_MASK 0x3F0
#define IMX_CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_PRE_DIV(v) (((v) << 4) & 0x3F0)
/* Field PLL_MAIN_DIV -  */
#define IMX_CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_MAIN_DIV_SHIFT 12
#define IMX_CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_MAIN_DIV_MASK 0x3FF000
#define IMX_CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_MAIN_DIV(v) (((v) << 12) & 0x3FF000)

/* Register AUDIO_PLL2_FDIV_CTL1 - AUDIO PLL2 Divide and Fraction Data Control 1 Register */
#define IMX_CCM_ANALOG_AUDIO_PLL2_FDIV_CTL1      0x1C
/* Field PLL_DSM -  */
#define IMX_CCM_ANALOG_AUDIO_PLL2_FDIV_CTL1_PLL_DSM_SHIFT 0
#define IMX_CCM_ANALOG_AUDIO_PLL2_FDIV_CTL1_PLL_DSM_MASK 0xFFFF
#define IMX_CCM_ANALOG_AUDIO_PLL2_FDIV_CTL1_PLL_DSM(v) (((v) << 0) & 0xFFFF)

/* Register AUDIO_PLL2_SSCG_CTRL - AUDIO PLL2 PLL SSCG Control Register */
#define IMX_CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL      0x20
/* Field SEL_PF -  */
#define IMX_CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_SEL_PF_SHIFT 0
#define IMX_CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_SEL_PF_MASK 0x3
#define IMX_CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_SEL_PF(v) (((v) << 0) & 0x3)
/* Field PLL_MRAT_CTL -  */
#define IMX_CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_PLL_MRAT_CTL_SHIFT 4
#define IMX_CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_PLL_MRAT_CTL_MASK 0x3F0
#define IMX_CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_PLL_MRAT_CTL(v) (((v) << 4) & 0x3F0)
/* Field PLL_MFREQ_CTL -  */
#define IMX_CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_PLL_MFREQ_CTL_SHIFT 12
#define IMX_CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_PLL_MFREQ_CTL_MASK 0xFF000
#define IMX_CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_PLL_MFREQ_CTL(v) (((v) << 12) & 0xFF000)
/* Field SSCG_EN -  */
#define IMX_CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_SSCG_EN_SHIFT 31
#define IMX_CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_SSCG_EN_MASK 0x80000000
#define IMX_CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_SSCG_EN(v) (((v) << 31) & 0x80000000)

/* Register AUDIO_PLL2_MNIT_CTRL - AUDIO PLL2 PLL Monitoring Control Register */
#define IMX_CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL      0x24
/* Field ICP -  */
#define IMX_CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_ICP_SHIFT 0
#define IMX_CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_ICP_MASK 0x7
#define IMX_CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_ICP(v) (((v) << 0) & 0x7)
/* Field AFC_EN -  */
#define IMX_CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFC_EN_SHIFT 3
#define IMX_CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFC_EN_MASK 0x8
#define IMX_CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFC_EN(v) (((v) << 3) & 0x8)
/* Field EXTAFC -  */
#define IMX_CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_EXTAFC_SHIFT 4
#define IMX_CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_EXTAFC_MASK 0x1F0
#define IMX_CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_EXTAFC(v) (((v) << 4) & 0x1F0)
/* Field FEED_EN -  */
#define IMX_CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_FEED_EN_SHIFT 14
#define IMX_CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_FEED_EN_MASK 0x4000
#define IMX_CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_FEED_EN(v) (((v) << 14) & 0x4000)
/* Field FSEL -  */
#define IMX_CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_FSEL_SHIFT 15
#define IMX_CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_FSEL_MASK 0x8000
#define IMX_CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_FSEL(v) (((v) << 15) & 0x8000)
/* Field AFCINIT_SEL -  */
#define IMX_CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFCINIT_SEL_SHIFT 17
#define IMX_CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFCINIT_SEL_MASK 0x20000
#define IMX_CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFCINIT_SEL(v) (((v) << 17) & 0x20000)
/* Field PBIAS_CTRL_EN -  */
#define IMX_CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT 18
#define IMX_CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_PBIAS_CTRL_EN_MASK 0x40000
#define IMX_CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_PBIAS_CTRL_EN(v) (((v) << 18) & 0x40000)
/* Field PBIAS_CTRL -  */
#define IMX_CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_PBIAS_CTRL_SHIFT 19
#define IMX_CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_PBIAS_CTRL_MASK 0x80000
#define IMX_CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_PBIAS_CTRL(v) (((v) << 19) & 0x80000)
/* Field AFC_SEL -  */
#define IMX_CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFC_SEL_SHIFT 20
#define IMX_CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFC_SEL_MASK 0x100000
#define IMX_CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFC_SEL(v) (((v) << 20) & 0x100000)

/* Register VIDEO_PLL1_GEN_CTRL - VIDEO PLL1 General Function Control Register */
#define IMX_CCM_ANALOG_VIDEO_PLL1_GEN_CTRL       0x28
/* Field PLL_REF_CLK_SEL -  */
#define IMX_CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT 0
#define IMX_CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_MASK 0x3
#define IMX_CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_REF_CLK_SEL(v) (((v) << 0) & 0x3)
/* Field PAD_CLK_SEL -  */
#define IMX_CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PAD_CLK_SEL_SHIFT 2
#define IMX_CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PAD_CLK_SEL_MASK 0xC
#define IMX_CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PAD_CLK_SEL(v) (((v) << 2) & 0xC)
/* Field PLL_BYPASS -  */
#define IMX_CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_BYPASS_SHIFT 4
#define IMX_CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_BYPASS_MASK 0x10
#define IMX_CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_BYPASS(v) (((v) << 4) & 0x10)
/* Field PLL_RST_OVERRIDE -  */
#define IMX_CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT 8
#define IMX_CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_MASK 0x100
#define IMX_CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_RST_OVERRIDE(v) (((v) << 8) & 0x100)
/* Field PLL_RST -  */
#define IMX_CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_RST_SHIFT 9
#define IMX_CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_RST_MASK 0x200
#define IMX_CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_RST(v) (((v) << 9) & 0x200)
/* Field PLL_CLKE_OVERRIDE -  */
#define IMX_CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT 12
#define IMX_CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK 0x1000
#define IMX_CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE(v) (((v) << 12) & 0x1000)
/* Field PLL_CLKE -  */
#define IMX_CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_CLKE_SHIFT 13
#define IMX_CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_CLKE_MASK 0x2000
#define IMX_CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_CLKE(v) (((v) << 13) & 0x2000)
/* Field PLL_EXT_BYPASS -  */
#define IMX_CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_EXT_BYPASS_SHIFT 16
#define IMX_CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_EXT_BYPASS_MASK 0x10000
#define IMX_CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_EXT_BYPASS(v) (((v) << 16) & 0x10000)
/* Field PLL_LOCK -  */
#define IMX_CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_LOCK_SHIFT 31
#define IMX_CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_LOCK_MASK 0x80000000
#define IMX_CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_LOCK(v) (((v) << 31) & 0x80000000)

/* Register VIDEO_PLL1_FDIV_CTL0 - VIDEO PLL1 Divide and Fraction Data Control 0 Register */
#define IMX_CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0      0x2C
/* Field PLL_POST_DIV -  */
#define IMX_CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_POST_DIV_SHIFT 0
#define IMX_CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_POST_DIV_MASK 0x7
#define IMX_CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_POST_DIV(v) (((v) << 0) & 0x7)
/* Field PLL_PRE_DIV -  */
#define IMX_CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_PRE_DIV_SHIFT 4
#define IMX_CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_PRE_DIV_MASK 0x3F0
#define IMX_CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_PRE_DIV(v) (((v) << 4) & 0x3F0)
/* Field PLL_MAIN_DIV -  */
#define IMX_CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_MAIN_DIV_SHIFT 12
#define IMX_CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_MAIN_DIV_MASK 0x3FF000
#define IMX_CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_MAIN_DIV(v) (((v) << 12) & 0x3FF000)

/* Register VIDEO_PLL1_FDIV_CTL1 - VIDEO PLL1 Divide and Fraction Data Control 1 Register */
#define IMX_CCM_ANALOG_VIDEO_PLL1_FDIV_CTL1      0x30
/* Field PLL_DSM -  */
#define IMX_CCM_ANALOG_VIDEO_PLL1_FDIV_CTL1_PLL_DSM_SHIFT 0
#define IMX_CCM_ANALOG_VIDEO_PLL1_FDIV_CTL1_PLL_DSM_MASK 0xFFFF
#define IMX_CCM_ANALOG_VIDEO_PLL1_FDIV_CTL1_PLL_DSM(v) (((v) << 0) & 0xFFFF)

/* Register VIDEO_PLL1_SSCG_CTRL - VIDEO PLL1 PLL SSCG Control Register */
#define IMX_CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL      0x34
/* Field SEL_PF -  */
#define IMX_CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_SEL_PF_SHIFT 0
#define IMX_CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_SEL_PF_MASK 0x3
#define IMX_CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_SEL_PF(v) (((v) << 0) & 0x3)
/* Field PLL_MRAT_CTL -  */
#define IMX_CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_PLL_MRAT_CTL_SHIFT 4
#define IMX_CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_PLL_MRAT_CTL_MASK 0x3F0
#define IMX_CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_PLL_MRAT_CTL(v) (((v) << 4) & 0x3F0)
/* Field PLL_MFREQ_CTL -  */
#define IMX_CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_PLL_MFREQ_CTL_SHIFT 12
#define IMX_CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_PLL_MFREQ_CTL_MASK 0xFF000
#define IMX_CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_PLL_MFREQ_CTL(v) (((v) << 12) & 0xFF000)
/* Field SSCG_EN -  */
#define IMX_CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_SSCG_EN_SHIFT 31
#define IMX_CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_SSCG_EN_MASK 0x80000000
#define IMX_CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_SSCG_EN(v) (((v) << 31) & 0x80000000)

/* Register VIDEO_PLL1_MNIT_CTRL - VIDEO PLL1 PLL Monitoring Control Register */
#define IMX_CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL      0x38
/* Field ICP -  */
#define IMX_CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_ICP_SHIFT 0
#define IMX_CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_ICP_MASK 0x7
#define IMX_CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_ICP(v) (((v) << 0) & 0x7)
/* Field AFC_EN -  */
#define IMX_CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFC_EN_SHIFT 3
#define IMX_CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFC_EN_MASK 0x8
#define IMX_CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFC_EN(v) (((v) << 3) & 0x8)
/* Field EXTAFC -  */
#define IMX_CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_EXTAFC_SHIFT 4
#define IMX_CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_EXTAFC_MASK 0x1F0
#define IMX_CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_EXTAFC(v) (((v) << 4) & 0x1F0)
/* Field FEED_EN -  */
#define IMX_CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_FEED_EN_SHIFT 14
#define IMX_CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_FEED_EN_MASK 0x4000
#define IMX_CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_FEED_EN(v) (((v) << 14) & 0x4000)
/* Field FSEL -  */
#define IMX_CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_FSEL_SHIFT 15
#define IMX_CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_FSEL_MASK 0x8000
#define IMX_CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_FSEL(v) (((v) << 15) & 0x8000)
/* Field AFCINIT_SEL -  */
#define IMX_CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFCINIT_SEL_SHIFT 17
#define IMX_CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFCINIT_SEL_MASK 0x20000
#define IMX_CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFCINIT_SEL(v) (((v) << 17) & 0x20000)
/* Field PBIAS_CTRL_EN -  */
#define IMX_CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT 18
#define IMX_CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_MASK 0x40000
#define IMX_CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_PBIAS_CTRL_EN(v) (((v) << 18) & 0x40000)
/* Field PBIAS_CTRL -  */
#define IMX_CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_PBIAS_CTRL_SHIFT 19
#define IMX_CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_PBIAS_CTRL_MASK 0x80000
#define IMX_CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_PBIAS_CTRL(v) (((v) << 19) & 0x80000)
/* Field AFC_SEL -  */
#define IMX_CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFC_SEL_SHIFT 20
#define IMX_CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFC_SEL_MASK 0x100000
#define IMX_CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFC_SEL(v) (((v) << 20) & 0x100000)

/* Register DRAM_PLL_GEN_CTRL - DRAM PLL General Function Control Register */
#define IMX_CCM_ANALOG_DRAM_PLL_GEN_CTRL         0x50
/* Field PLL_REF_CLK_SEL -  */
#define IMX_CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT 0
#define IMX_CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_REF_CLK_SEL_MASK 0x3
#define IMX_CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_REF_CLK_SEL(v) (((v) << 0) & 0x3)
/* Field PAD_CLK_SEL -  */
#define IMX_CCM_ANALOG_DRAM_PLL_GEN_CTRL_PAD_CLK_SEL_SHIFT 2
#define IMX_CCM_ANALOG_DRAM_PLL_GEN_CTRL_PAD_CLK_SEL_MASK 0xC
#define IMX_CCM_ANALOG_DRAM_PLL_GEN_CTRL_PAD_CLK_SEL(v) (((v) << 2) & 0xC)
/* Field PLL_BYPASS -  */
#define IMX_CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_BYPASS_SHIFT 4
#define IMX_CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_BYPASS_MASK 0x10
#define IMX_CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_BYPASS(v) (((v) << 4) & 0x10)
/* Field PLL_RST_OVERRIDE -  */
#define IMX_CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT 8
#define IMX_CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_RST_OVERRIDE_MASK 0x100
#define IMX_CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_RST_OVERRIDE(v) (((v) << 8) & 0x100)
/* Field PLL_RST -  */
#define IMX_CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_RST_SHIFT 9
#define IMX_CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_RST_MASK 0x200
#define IMX_CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_RST(v) (((v) << 9) & 0x200)
/* Field PLL_CLKE_OVERRIDE -  */
#define IMX_CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT 12
#define IMX_CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK 0x1000
#define IMX_CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE(v) (((v) << 12) & 0x1000)
/* Field PLL_CLKE -  */
#define IMX_CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_CLKE_SHIFT 13
#define IMX_CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_CLKE_MASK 0x2000
#define IMX_CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_CLKE(v) (((v) << 13) & 0x2000)
/* Field PLL_EXT_BYPASS -  */
#define IMX_CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_EXT_BYPASS_SHIFT 16
#define IMX_CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_EXT_BYPASS_MASK 0x10000
#define IMX_CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_EXT_BYPASS(v) (((v) << 16) & 0x10000)
/* Field PLL_LOCK -  */
#define IMX_CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_LOCK_SHIFT 31
#define IMX_CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_LOCK_MASK 0x80000000
#define IMX_CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_LOCK(v) (((v) << 31) & 0x80000000)

/* Register DRAM_PLL_FDIV_CTL0 - DRAM PLL Divide and Fraction Data Control 0 Register */
#define IMX_CCM_ANALOG_DRAM_PLL_FDIV_CTL0        0x54
/* Field PLL_POST_DIV -  */
#define IMX_CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_POST_DIV_SHIFT 0
#define IMX_CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_POST_DIV_MASK 0x7
#define IMX_CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_POST_DIV(v) (((v) << 0) & 0x7)
/* Field PLL_PRE_DIV -  */
#define IMX_CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_PRE_DIV_SHIFT 4
#define IMX_CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_PRE_DIV_MASK 0x3F0
#define IMX_CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_PRE_DIV(v) (((v) << 4) & 0x3F0)
/* Field PLL_MAIN_DIV -  */
#define IMX_CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_MAIN_DIV_SHIFT 12
#define IMX_CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_MAIN_DIV_MASK 0x3FF000
#define IMX_CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_MAIN_DIV(v) (((v) << 12) & 0x3FF000)

/* Register DRAM_PLL_FDIV_CTL1 - DRAM PLL Divide and Fraction Data Control 1 Register */
#define IMX_CCM_ANALOG_DRAM_PLL_FDIV_CTL1        0x58
/* Field PLL_DSM -  */
#define IMX_CCM_ANALOG_DRAM_PLL_FDIV_CTL1_PLL_DSM_SHIFT 0
#define IMX_CCM_ANALOG_DRAM_PLL_FDIV_CTL1_PLL_DSM_MASK 0xFFFF
#define IMX_CCM_ANALOG_DRAM_PLL_FDIV_CTL1_PLL_DSM(v) (((v) << 0) & 0xFFFF)

/* Register DRAM_PLL_SSCG_CTRL - DRAM PLL PLL SSCG Control Register */
#define IMX_CCM_ANALOG_DRAM_PLL_SSCG_CTRL        0x5C
/* Field SEL_PF -  */
#define IMX_CCM_ANALOG_DRAM_PLL_SSCG_CTRL_SEL_PF_SHIFT 0
#define IMX_CCM_ANALOG_DRAM_PLL_SSCG_CTRL_SEL_PF_MASK 0x3
#define IMX_CCM_ANALOG_DRAM_PLL_SSCG_CTRL_SEL_PF(v) (((v) << 0) & 0x3)
/* Field PLL_MRAT_CTL -  */
#define IMX_CCM_ANALOG_DRAM_PLL_SSCG_CTRL_PLL_MRAT_CTL_SHIFT 4
#define IMX_CCM_ANALOG_DRAM_PLL_SSCG_CTRL_PLL_MRAT_CTL_MASK 0x3F0
#define IMX_CCM_ANALOG_DRAM_PLL_SSCG_CTRL_PLL_MRAT_CTL(v) (((v) << 4) & 0x3F0)
/* Field PLL_MFREQ_CTL -  */
#define IMX_CCM_ANALOG_DRAM_PLL_SSCG_CTRL_PLL_MFREQ_CTL_SHIFT 12
#define IMX_CCM_ANALOG_DRAM_PLL_SSCG_CTRL_PLL_MFREQ_CTL_MASK 0xFF000
#define IMX_CCM_ANALOG_DRAM_PLL_SSCG_CTRL_PLL_MFREQ_CTL(v) (((v) << 12) & 0xFF000)
/* Field SSCG_EN -  */
#define IMX_CCM_ANALOG_DRAM_PLL_SSCG_CTRL_SSCG_EN_SHIFT 31
#define IMX_CCM_ANALOG_DRAM_PLL_SSCG_CTRL_SSCG_EN_MASK 0x80000000
#define IMX_CCM_ANALOG_DRAM_PLL_SSCG_CTRL_SSCG_EN(v) (((v) << 31) & 0x80000000)

/* Register DRAM_PLL_MNIT_CTRL - DRAM PLL PLL Monitoring Control Register */
#define IMX_CCM_ANALOG_DRAM_PLL_MNIT_CTRL        0x60
/* Field ICP -  */
#define IMX_CCM_ANALOG_DRAM_PLL_MNIT_CTRL_ICP_SHIFT 0
#define IMX_CCM_ANALOG_DRAM_PLL_MNIT_CTRL_ICP_MASK 0x7
#define IMX_CCM_ANALOG_DRAM_PLL_MNIT_CTRL_ICP(v) (((v) << 0) & 0x7)
/* Field AFC_EN -  */
#define IMX_CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFC_EN_SHIFT 3
#define IMX_CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFC_EN_MASK 0x8
#define IMX_CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFC_EN(v) (((v) << 3) & 0x8)
/* Field EXTAFC -  */
#define IMX_CCM_ANALOG_DRAM_PLL_MNIT_CTRL_EXTAFC_SHIFT 4
#define IMX_CCM_ANALOG_DRAM_PLL_MNIT_CTRL_EXTAFC_MASK 0x1F0
#define IMX_CCM_ANALOG_DRAM_PLL_MNIT_CTRL_EXTAFC(v) (((v) << 4) & 0x1F0)
/* Field FEED_EN -  */
#define IMX_CCM_ANALOG_DRAM_PLL_MNIT_CTRL_FEED_EN_SHIFT 14
#define IMX_CCM_ANALOG_DRAM_PLL_MNIT_CTRL_FEED_EN_MASK 0x4000
#define IMX_CCM_ANALOG_DRAM_PLL_MNIT_CTRL_FEED_EN(v) (((v) << 14) & 0x4000)
/* Field FSEL -  */
#define IMX_CCM_ANALOG_DRAM_PLL_MNIT_CTRL_FSEL_SHIFT 15
#define IMX_CCM_ANALOG_DRAM_PLL_MNIT_CTRL_FSEL_MASK 0x8000
#define IMX_CCM_ANALOG_DRAM_PLL_MNIT_CTRL_FSEL(v) (((v) << 15) & 0x8000)
/* Field AFCINIT_SEL -  */
#define IMX_CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFCINIT_SEL_SHIFT 17
#define IMX_CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFCINIT_SEL_MASK 0x20000
#define IMX_CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFCINIT_SEL(v) (((v) << 17) & 0x20000)
/* Field PBIAS_CTRL_EN -  */
#define IMX_CCM_ANALOG_DRAM_PLL_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT 18
#define IMX_CCM_ANALOG_DRAM_PLL_MNIT_CTRL_PBIAS_CTRL_EN_MASK 0x40000
#define IMX_CCM_ANALOG_DRAM_PLL_MNIT_CTRL_PBIAS_CTRL_EN(v) (((v) << 18) & 0x40000)
/* Field PBIAS_CTRL -  */
#define IMX_CCM_ANALOG_DRAM_PLL_MNIT_CTRL_PBIAS_CTRL_SHIFT 19
#define IMX_CCM_ANALOG_DRAM_PLL_MNIT_CTRL_PBIAS_CTRL_MASK 0x80000
#define IMX_CCM_ANALOG_DRAM_PLL_MNIT_CTRL_PBIAS_CTRL(v) (((v) << 19) & 0x80000)
/* Field AFC_SEL -  */
#define IMX_CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFC_SEL_SHIFT 20
#define IMX_CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFC_SEL_MASK 0x100000
#define IMX_CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFC_SEL(v) (((v) << 20) & 0x100000)

/* Register GPU_PLL_GEN_CTRL - GPU PLL General Function Control Register */
#define IMX_CCM_ANALOG_GPU_PLL_GEN_CTRL          0x64
/* Field PLL_REF_CLK_SEL -  */
#define IMX_CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT 0
#define IMX_CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_REF_CLK_SEL_MASK 0x3
#define IMX_CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_REF_CLK_SEL(v) (((v) << 0) & 0x3)
/* Field PAD_CLK_SEL -  */
#define IMX_CCM_ANALOG_GPU_PLL_GEN_CTRL_PAD_CLK_SEL_SHIFT 2
#define IMX_CCM_ANALOG_GPU_PLL_GEN_CTRL_PAD_CLK_SEL_MASK 0xC
#define IMX_CCM_ANALOG_GPU_PLL_GEN_CTRL_PAD_CLK_SEL(v) (((v) << 2) & 0xC)
/* Field PLL_BYPASS -  */
#define IMX_CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_BYPASS_SHIFT 4
#define IMX_CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_BYPASS_MASK 0x10
#define IMX_CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_BYPASS(v) (((v) << 4) & 0x10)
/* Field PLL_RST_OVERRIDE -  */
#define IMX_CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT 8
#define IMX_CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_RST_OVERRIDE_MASK 0x100
#define IMX_CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_RST_OVERRIDE(v) (((v) << 8) & 0x100)
/* Field PLL_RST -  */
#define IMX_CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_RST_SHIFT 9
#define IMX_CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_RST_MASK 0x200
#define IMX_CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_RST(v) (((v) << 9) & 0x200)
/* Field PLL_CLKE_OVERRIDE -  */
#define IMX_CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT 10
#define IMX_CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK 0x400
#define IMX_CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE(v) (((v) << 10) & 0x400)
/* Field PLL_CLKE -  */
#define IMX_CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_CLKE_SHIFT 11
#define IMX_CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_CLKE_MASK 0x800
#define IMX_CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_CLKE(v) (((v) << 11) & 0x800)
/* Field PLL_EXT_BYPASS -  */
#define IMX_CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_EXT_BYPASS_SHIFT 28
#define IMX_CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_EXT_BYPASS_MASK 0x10000000
#define IMX_CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_EXT_BYPASS(v) (((v) << 28) & 0x10000000)
/* Field PLL_LOCK_SEL -  */
#define IMX_CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_LOCK_SEL_SHIFT 29
#define IMX_CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_LOCK_SEL_MASK 0x20000000
#define IMX_CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_LOCK_SEL(v) (((v) << 29) & 0x20000000)
/* Field PLL_LOCK -  */
#define IMX_CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_LOCK_SHIFT 31
#define IMX_CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_LOCK_MASK 0x80000000
#define IMX_CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_LOCK(v) (((v) << 31) & 0x80000000)

/* Register GPU_PLL_FDIV_CTL0 - GPU PLL Divide and Fraction Data Control 0 Register */
#define IMX_CCM_ANALOG_GPU_PLL_FDIV_CTL0         0x68
/* Field PLL_POST_DIV -  */
#define IMX_CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_POST_DIV_SHIFT 0
#define IMX_CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_POST_DIV_MASK 0x7
#define IMX_CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_POST_DIV(v) (((v) << 0) & 0x7)
/* Field PLL_PRE_DIV -  */
#define IMX_CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_PRE_DIV_SHIFT 4
#define IMX_CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_PRE_DIV_MASK 0x3F0
#define IMX_CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_PRE_DIV(v) (((v) << 4) & 0x3F0)
/* Field PLL_MAIN_DIV -  */
#define IMX_CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_MAIN_DIV_SHIFT 12
#define IMX_CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_MAIN_DIV_MASK 0x3FF000
#define IMX_CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_MAIN_DIV(v) (((v) << 12) & 0x3FF000)

/* Register GPU_PLL_LOCKD_CTRL - PLL Lock Detector Control Register */
#define IMX_CCM_ANALOG_GPU_PLL_LOCKD_CTRL        0x6C
/* Field LOCK_CON_IN -  */
#define IMX_CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_IN_SHIFT 0
#define IMX_CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_IN_MASK 0x3
#define IMX_CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_IN(v) (((v) << 0) & 0x3)
/* Field LOCK_CON_OUT -  */
#define IMX_CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_OUT_SHIFT 2
#define IMX_CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_OUT_MASK 0xC
#define IMX_CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_OUT(v) (((v) << 2) & 0xC)
/* Field LOCK_CON_DLY -  */
#define IMX_CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_DLY_SHIFT 4
#define IMX_CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_DLY_MASK 0x30
#define IMX_CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_DLY(v) (((v) << 4) & 0x30)

/* Register GPU_PLL_MNIT_CTRL - PLL Monitoring Control Register */
#define IMX_CCM_ANALOG_GPU_PLL_MNIT_CTRL         0x70
/* Field ICP -  */
#define IMX_CCM_ANALOG_GPU_PLL_MNIT_CTRL_ICP_SHIFT 0
#define IMX_CCM_ANALOG_GPU_PLL_MNIT_CTRL_ICP_MASK 0x3
#define IMX_CCM_ANALOG_GPU_PLL_MNIT_CTRL_ICP(v)  (((v) << 0) & 0x3)
/* Field AFC_EN -  */
#define IMX_CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFC_EN_SHIFT 2
#define IMX_CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFC_EN_MASK 0x4
#define IMX_CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFC_EN(v) (((v) << 2) & 0x4)
/* Field EXTAFC -  */
#define IMX_CCM_ANALOG_GPU_PLL_MNIT_CTRL_EXTAFC_SHIFT 3
#define IMX_CCM_ANALOG_GPU_PLL_MNIT_CTRL_EXTAFC_MASK 0xF8
#define IMX_CCM_ANALOG_GPU_PLL_MNIT_CTRL_EXTAFC(v) (((v) << 3) & 0xF8)
/* Field FEED_EN -  */
#define IMX_CCM_ANALOG_GPU_PLL_MNIT_CTRL_FEED_EN_SHIFT 13
#define IMX_CCM_ANALOG_GPU_PLL_MNIT_CTRL_FEED_EN_MASK 0x2000
#define IMX_CCM_ANALOG_GPU_PLL_MNIT_CTRL_FEED_EN(v) (((v) << 13) & 0x2000)
/* Field FSEL -  */
#define IMX_CCM_ANALOG_GPU_PLL_MNIT_CTRL_FSEL_SHIFT 14
#define IMX_CCM_ANALOG_GPU_PLL_MNIT_CTRL_FSEL_MASK 0x4000
#define IMX_CCM_ANALOG_GPU_PLL_MNIT_CTRL_FSEL(v) (((v) << 14) & 0x4000)
/* Field AFCINIT_SEL -  */
#define IMX_CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFCINIT_SEL_SHIFT 16
#define IMX_CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFCINIT_SEL_MASK 0x10000
#define IMX_CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFCINIT_SEL(v) (((v) << 16) & 0x10000)
/* Field PBIAS_CTRL_EN -  */
#define IMX_CCM_ANALOG_GPU_PLL_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT 17
#define IMX_CCM_ANALOG_GPU_PLL_MNIT_CTRL_PBIAS_CTRL_EN_MASK 0x20000
#define IMX_CCM_ANALOG_GPU_PLL_MNIT_CTRL_PBIAS_CTRL_EN(v) (((v) << 17) & 0x20000)
/* Field PBIAS_CTRL -  */
#define IMX_CCM_ANALOG_GPU_PLL_MNIT_CTRL_PBIAS_CTRL_SHIFT 18
#define IMX_CCM_ANALOG_GPU_PLL_MNIT_CTRL_PBIAS_CTRL_MASK 0x40000
#define IMX_CCM_ANALOG_GPU_PLL_MNIT_CTRL_PBIAS_CTRL(v) (((v) << 18) & 0x40000)
/* Field AFC_SEL -  */
#define IMX_CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFC_SEL_SHIFT 19
#define IMX_CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFC_SEL_MASK 0x80000
#define IMX_CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFC_SEL(v) (((v) << 19) & 0x80000)
/* Field FOUT_MASK -  */
#define IMX_CCM_ANALOG_GPU_PLL_MNIT_CTRL_FOUT_MASK_SHIFT 20
#define IMX_CCM_ANALOG_GPU_PLL_MNIT_CTRL_FOUT_MASK_MASK 0x100000
#define IMX_CCM_ANALOG_GPU_PLL_MNIT_CTRL_FOUT_MASK(v) (((v) << 20) & 0x100000)
/* Field LRD_EN -  */
#define IMX_CCM_ANALOG_GPU_PLL_MNIT_CTRL_LRD_EN_SHIFT 21
#define IMX_CCM_ANALOG_GPU_PLL_MNIT_CTRL_LRD_EN_MASK 0x200000
#define IMX_CCM_ANALOG_GPU_PLL_MNIT_CTRL_LRD_EN(v) (((v) << 21) & 0x200000)

/* Register VPU_PLL_GEN_CTRL - VPU PLL General Function Control Register */
#define IMX_CCM_ANALOG_VPU_PLL_GEN_CTRL          0x74
/* Field PLL_REF_CLK_SEL -  */
#define IMX_CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT 0
#define IMX_CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_REF_CLK_SEL_MASK 0x3
#define IMX_CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_REF_CLK_SEL(v) (((v) << 0) & 0x3)
/* Field PAD_CLK_SEL -  */
#define IMX_CCM_ANALOG_VPU_PLL_GEN_CTRL_PAD_CLK_SEL_SHIFT 2
#define IMX_CCM_ANALOG_VPU_PLL_GEN_CTRL_PAD_CLK_SEL_MASK 0xC
#define IMX_CCM_ANALOG_VPU_PLL_GEN_CTRL_PAD_CLK_SEL(v) (((v) << 2) & 0xC)
/* Field PLL_BYPASS -  */
#define IMX_CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_BYPASS_SHIFT 4
#define IMX_CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_BYPASS_MASK 0x10
#define IMX_CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_BYPASS(v) (((v) << 4) & 0x10)
/* Field PLL_RST_OVERRIDE -  */
#define IMX_CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT 8
#define IMX_CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_RST_OVERRIDE_MASK 0x100
#define IMX_CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_RST_OVERRIDE(v) (((v) << 8) & 0x100)
/* Field PLL_RST -  */
#define IMX_CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_RST_SHIFT 9
#define IMX_CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_RST_MASK 0x200
#define IMX_CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_RST(v) (((v) << 9) & 0x200)
/* Field PLL_CLKE_OVERRIDE -  */
#define IMX_CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT 10
#define IMX_CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK 0x400
#define IMX_CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE(v) (((v) << 10) & 0x400)
/* Field PLL_CLKE -  */
#define IMX_CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_CLKE_SHIFT 11
#define IMX_CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_CLKE_MASK 0x800
#define IMX_CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_CLKE(v) (((v) << 11) & 0x800)
/* Field PLL_EXT_BYPASS -  */
#define IMX_CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_EXT_BYPASS_SHIFT 28
#define IMX_CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_EXT_BYPASS_MASK 0x10000000
#define IMX_CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_EXT_BYPASS(v) (((v) << 28) & 0x10000000)
/* Field PLL_LOCK_SEL -  */
#define IMX_CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_LOCK_SEL_SHIFT 29
#define IMX_CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_LOCK_SEL_MASK 0x20000000
#define IMX_CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_LOCK_SEL(v) (((v) << 29) & 0x20000000)
/* Field PLL_LOCK -  */
#define IMX_CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_LOCK_SHIFT 31
#define IMX_CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_LOCK_MASK 0x80000000
#define IMX_CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_LOCK(v) (((v) << 31) & 0x80000000)

/* Register VPU_PLL_FDIV_CTL0 - VPU PLL Divide and Fraction Data Control 0 Register */
#define IMX_CCM_ANALOG_VPU_PLL_FDIV_CTL0         0x78
/* Field PLL_POST_DIV -  */
#define IMX_CCM_ANALOG_VPU_PLL_FDIV_CTL0_PLL_POST_DIV_SHIFT 0
#define IMX_CCM_ANALOG_VPU_PLL_FDIV_CTL0_PLL_POST_DIV_MASK 0x7
#define IMX_CCM_ANALOG_VPU_PLL_FDIV_CTL0_PLL_POST_DIV(v) (((v) << 0) & 0x7)
/* Field PLL_PRE_DIV -  */
#define IMX_CCM_ANALOG_VPU_PLL_FDIV_CTL0_PLL_PRE_DIV_SHIFT 4
#define IMX_CCM_ANALOG_VPU_PLL_FDIV_CTL0_PLL_PRE_DIV_MASK 0x3F0
#define IMX_CCM_ANALOG_VPU_PLL_FDIV_CTL0_PLL_PRE_DIV(v) (((v) << 4) & 0x3F0)
/* Field PLL_MAIN_DIV -  */
#define IMX_CCM_ANALOG_VPU_PLL_FDIV_CTL0_PLL_MAIN_DIV_SHIFT 12
#define IMX_CCM_ANALOG_VPU_PLL_FDIV_CTL0_PLL_MAIN_DIV_MASK 0x3FF000
#define IMX_CCM_ANALOG_VPU_PLL_FDIV_CTL0_PLL_MAIN_DIV(v) (((v) << 12) & 0x3FF000)

/* Register VPU_PLL_LOCKD_CTRL - PLL Lock Detector Control Register */
#define IMX_CCM_ANALOG_VPU_PLL_LOCKD_CTRL        0x7C
/* Field LOCK_CON_IN -  */
#define IMX_CCM_ANALOG_VPU_PLL_LOCKD_CTRL_LOCK_CON_IN_SHIFT 0
#define IMX_CCM_ANALOG_VPU_PLL_LOCKD_CTRL_LOCK_CON_IN_MASK 0x3
#define IMX_CCM_ANALOG_VPU_PLL_LOCKD_CTRL_LOCK_CON_IN(v) (((v) << 0) & 0x3)
/* Field LOCK_CON_OUT -  */
#define IMX_CCM_ANALOG_VPU_PLL_LOCKD_CTRL_LOCK_CON_OUT_SHIFT 2
#define IMX_CCM_ANALOG_VPU_PLL_LOCKD_CTRL_LOCK_CON_OUT_MASK 0xC
#define IMX_CCM_ANALOG_VPU_PLL_LOCKD_CTRL_LOCK_CON_OUT(v) (((v) << 2) & 0xC)
/* Field LOCK_CON_DLY -  */
#define IMX_CCM_ANALOG_VPU_PLL_LOCKD_CTRL_LOCK_CON_DLY_SHIFT 4
#define IMX_CCM_ANALOG_VPU_PLL_LOCKD_CTRL_LOCK_CON_DLY_MASK 0x30
#define IMX_CCM_ANALOG_VPU_PLL_LOCKD_CTRL_LOCK_CON_DLY(v) (((v) << 4) & 0x30)

/* Register VPU_PLL_MNIT_CTRL - PLL Monitoring Control Register */
#define IMX_CCM_ANALOG_VPU_PLL_MNIT_CTRL         0x80
/* Field ICP -  */
#define IMX_CCM_ANALOG_VPU_PLL_MNIT_CTRL_ICP_SHIFT 0
#define IMX_CCM_ANALOG_VPU_PLL_MNIT_CTRL_ICP_MASK 0x3
#define IMX_CCM_ANALOG_VPU_PLL_MNIT_CTRL_ICP(v)  (((v) << 0) & 0x3)
/* Field AFC_EN -  */
#define IMX_CCM_ANALOG_VPU_PLL_MNIT_CTRL_AFC_EN_SHIFT 2
#define IMX_CCM_ANALOG_VPU_PLL_MNIT_CTRL_AFC_EN_MASK 0x4
#define IMX_CCM_ANALOG_VPU_PLL_MNIT_CTRL_AFC_EN(v) (((v) << 2) & 0x4)
/* Field EXTAFC -  */
#define IMX_CCM_ANALOG_VPU_PLL_MNIT_CTRL_EXTAFC_SHIFT 3
#define IMX_CCM_ANALOG_VPU_PLL_MNIT_CTRL_EXTAFC_MASK 0xF8
#define IMX_CCM_ANALOG_VPU_PLL_MNIT_CTRL_EXTAFC(v) (((v) << 3) & 0xF8)
/* Field FEED_EN -  */
#define IMX_CCM_ANALOG_VPU_PLL_MNIT_CTRL_FEED_EN_SHIFT 13
#define IMX_CCM_ANALOG_VPU_PLL_MNIT_CTRL_FEED_EN_MASK 0x2000
#define IMX_CCM_ANALOG_VPU_PLL_MNIT_CTRL_FEED_EN(v) (((v) << 13) & 0x2000)
/* Field FSEL -  */
#define IMX_CCM_ANALOG_VPU_PLL_MNIT_CTRL_FSEL_SHIFT 14
#define IMX_CCM_ANALOG_VPU_PLL_MNIT_CTRL_FSEL_MASK 0x4000
#define IMX_CCM_ANALOG_VPU_PLL_MNIT_CTRL_FSEL(v) (((v) << 14) & 0x4000)
/* Field AFCINIT_SEL -  */
#define IMX_CCM_ANALOG_VPU_PLL_MNIT_CTRL_AFCINIT_SEL_SHIFT 16
#define IMX_CCM_ANALOG_VPU_PLL_MNIT_CTRL_AFCINIT_SEL_MASK 0x10000
#define IMX_CCM_ANALOG_VPU_PLL_MNIT_CTRL_AFCINIT_SEL(v) (((v) << 16) & 0x10000)
/* Field PBIAS_CTRL_EN -  */
#define IMX_CCM_ANALOG_VPU_PLL_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT 17
#define IMX_CCM_ANALOG_VPU_PLL_MNIT_CTRL_PBIAS_CTRL_EN_MASK 0x20000
#define IMX_CCM_ANALOG_VPU_PLL_MNIT_CTRL_PBIAS_CTRL_EN(v) (((v) << 17) & 0x20000)
/* Field PBIAS_CTRL -  */
#define IMX_CCM_ANALOG_VPU_PLL_MNIT_CTRL_PBIAS_CTRL_SHIFT 18
#define IMX_CCM_ANALOG_VPU_PLL_MNIT_CTRL_PBIAS_CTRL_MASK 0x40000
#define IMX_CCM_ANALOG_VPU_PLL_MNIT_CTRL_PBIAS_CTRL(v) (((v) << 18) & 0x40000)
/* Field AFC_SEL -  */
#define IMX_CCM_ANALOG_VPU_PLL_MNIT_CTRL_AFC_SEL_SHIFT 19
#define IMX_CCM_ANALOG_VPU_PLL_MNIT_CTRL_AFC_SEL_MASK 0x80000
#define IMX_CCM_ANALOG_VPU_PLL_MNIT_CTRL_AFC_SEL(v) (((v) << 19) & 0x80000)
/* Field FOUT_MASK -  */
#define IMX_CCM_ANALOG_VPU_PLL_MNIT_CTRL_FOUT_MASK_SHIFT 20
#define IMX_CCM_ANALOG_VPU_PLL_MNIT_CTRL_FOUT_MASK_MASK 0x100000
#define IMX_CCM_ANALOG_VPU_PLL_MNIT_CTRL_FOUT_MASK(v) (((v) << 20) & 0x100000)
/* Field LRD_EN -  */
#define IMX_CCM_ANALOG_VPU_PLL_MNIT_CTRL_LRD_EN_SHIFT 21
#define IMX_CCM_ANALOG_VPU_PLL_MNIT_CTRL_LRD_EN_MASK 0x200000
#define IMX_CCM_ANALOG_VPU_PLL_MNIT_CTRL_LRD_EN(v) (((v) << 21) & 0x200000)

/* Register ARM_PLL_GEN_CTRL - ARM PLL General Function Control Register */
#define IMX_CCM_ANALOG_ARM_PLL_GEN_CTRL          0x84
/* Field PLL_REF_CLK_SEL -  */
#define IMX_CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT 0
#define IMX_CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_REF_CLK_SEL_MASK 0x3
#define IMX_CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_REF_CLK_SEL(v) (((v) << 0) & 0x3)
/* Field PAD_CLK_SEL -  */
#define IMX_CCM_ANALOG_ARM_PLL_GEN_CTRL_PAD_CLK_SEL_SHIFT 2
#define IMX_CCM_ANALOG_ARM_PLL_GEN_CTRL_PAD_CLK_SEL_MASK 0xC
#define IMX_CCM_ANALOG_ARM_PLL_GEN_CTRL_PAD_CLK_SEL(v) (((v) << 2) & 0xC)
/* Field PLL_BYPASS -  */
#define IMX_CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_BYPASS_SHIFT 4
#define IMX_CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_BYPASS_MASK 0x10
#define IMX_CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_BYPASS(v) (((v) << 4) & 0x10)
/* Field PLL_RST_OVERRIDE -  */
#define IMX_CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT 8
#define IMX_CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_RST_OVERRIDE_MASK 0x100
#define IMX_CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_RST_OVERRIDE(v) (((v) << 8) & 0x100)
/* Field PLL_RST -  */
#define IMX_CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_RST_SHIFT 9
#define IMX_CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_RST_MASK 0x200
#define IMX_CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_RST(v) (((v) << 9) & 0x200)
/* Field PLL_CLKE_OVERRIDE -  */
#define IMX_CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT 10
#define IMX_CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK 0x400
#define IMX_CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE(v) (((v) << 10) & 0x400)
/* Field PLL_CLKE -  */
#define IMX_CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_CLKE_SHIFT 11
#define IMX_CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_CLKE_MASK 0x800
#define IMX_CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_CLKE(v) (((v) << 11) & 0x800)
/* Field PLL_EXT_BYPASS -  */
#define IMX_CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_EXT_BYPASS_SHIFT 28
#define IMX_CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_EXT_BYPASS_MASK 0x10000000
#define IMX_CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_EXT_BYPASS(v) (((v) << 28) & 0x10000000)
/* Field PLL_LOCK_SEL -  */
#define IMX_CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_LOCK_SEL_SHIFT 29
#define IMX_CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_LOCK_SEL_MASK 0x20000000
#define IMX_CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_LOCK_SEL(v) (((v) << 29) & 0x20000000)
/* Field PLL_LOCK -  */
#define IMX_CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_LOCK_SHIFT 31
#define IMX_CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_LOCK_MASK 0x80000000
#define IMX_CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_LOCK(v) (((v) << 31) & 0x80000000)

/* Register ARM_PLL_FDIV_CTL0 - ARM PLL Divide and Fraction Data Control 0 Register */
#define IMX_CCM_ANALOG_ARM_PLL_FDIV_CTL0         0x88
/* Field PLL_POST_DIV -  */
#define IMX_CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_POST_DIV_SHIFT 0
#define IMX_CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_POST_DIV_MASK 0x7
#define IMX_CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_POST_DIV(v) (((v) << 0) & 0x7)
/* Field PLL_PRE_DIV -  */
#define IMX_CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_PRE_DIV_SHIFT 4
#define IMX_CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_PRE_DIV_MASK 0x3F0
#define IMX_CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_PRE_DIV(v) (((v) << 4) & 0x3F0)
/* Field PLL_MAIN_DIV -  */
#define IMX_CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_MAIN_DIV_SHIFT 12
#define IMX_CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_MAIN_DIV_MASK 0x3FF000
#define IMX_CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_MAIN_DIV(v) (((v) << 12) & 0x3FF000)

/* Register ARM_PLL_LOCKD_CTRL - PLL Lock Detector Control Register */
#define IMX_CCM_ANALOG_ARM_PLL_LOCKD_CTRL        0x8C
/* Field LOCK_CON_IN -  */
#define IMX_CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_IN_SHIFT 0
#define IMX_CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_IN_MASK 0x3
#define IMX_CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_IN(v) (((v) << 0) & 0x3)
/* Field LOCK_CON_OUT -  */
#define IMX_CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_OUT_SHIFT 2
#define IMX_CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_OUT_MASK 0xC
#define IMX_CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_OUT(v) (((v) << 2) & 0xC)
/* Field LOCK_CON_DLY -  */
#define IMX_CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_DLY_SHIFT 4
#define IMX_CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_DLY_MASK 0x30
#define IMX_CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_DLY(v) (((v) << 4) & 0x30)

/* Register ARM_PLL_MNIT_CTRL - PLL Monitoring Control Register */
#define IMX_CCM_ANALOG_ARM_PLL_MNIT_CTRL         0x90
/* Field ICP -  */
#define IMX_CCM_ANALOG_ARM_PLL_MNIT_CTRL_ICP_SHIFT 0
#define IMX_CCM_ANALOG_ARM_PLL_MNIT_CTRL_ICP_MASK 0x3
#define IMX_CCM_ANALOG_ARM_PLL_MNIT_CTRL_ICP(v)  (((v) << 0) & 0x3)
/* Field AFC_EN -  */
#define IMX_CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFC_EN_SHIFT 2
#define IMX_CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFC_EN_MASK 0x4
#define IMX_CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFC_EN(v) (((v) << 2) & 0x4)
/* Field EXTAFC -  */
#define IMX_CCM_ANALOG_ARM_PLL_MNIT_CTRL_EXTAFC_SHIFT 3
#define IMX_CCM_ANALOG_ARM_PLL_MNIT_CTRL_EXTAFC_MASK 0xF8
#define IMX_CCM_ANALOG_ARM_PLL_MNIT_CTRL_EXTAFC(v) (((v) << 3) & 0xF8)
/* Field FEED_EN -  */
#define IMX_CCM_ANALOG_ARM_PLL_MNIT_CTRL_FEED_EN_SHIFT 13
#define IMX_CCM_ANALOG_ARM_PLL_MNIT_CTRL_FEED_EN_MASK 0x2000
#define IMX_CCM_ANALOG_ARM_PLL_MNIT_CTRL_FEED_EN(v) (((v) << 13) & 0x2000)
/* Field FSEL -  */
#define IMX_CCM_ANALOG_ARM_PLL_MNIT_CTRL_FSEL_SHIFT 14
#define IMX_CCM_ANALOG_ARM_PLL_MNIT_CTRL_FSEL_MASK 0x4000
#define IMX_CCM_ANALOG_ARM_PLL_MNIT_CTRL_FSEL(v) (((v) << 14) & 0x4000)
/* Field AFCINIT_SEL -  */
#define IMX_CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFCINIT_SEL_SHIFT 16
#define IMX_CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFCINIT_SEL_MASK 0x10000
#define IMX_CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFCINIT_SEL(v) (((v) << 16) & 0x10000)
/* Field PBIAS_CTRL_EN -  */
#define IMX_CCM_ANALOG_ARM_PLL_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT 17
#define IMX_CCM_ANALOG_ARM_PLL_MNIT_CTRL_PBIAS_CTRL_EN_MASK 0x20000
#define IMX_CCM_ANALOG_ARM_PLL_MNIT_CTRL_PBIAS_CTRL_EN(v) (((v) << 17) & 0x20000)
/* Field PBIAS_CTRL -  */
#define IMX_CCM_ANALOG_ARM_PLL_MNIT_CTRL_PBIAS_CTRL_SHIFT 18
#define IMX_CCM_ANALOG_ARM_PLL_MNIT_CTRL_PBIAS_CTRL_MASK 0x40000
#define IMX_CCM_ANALOG_ARM_PLL_MNIT_CTRL_PBIAS_CTRL(v) (((v) << 18) & 0x40000)
/* Field AFC_SEL -  */
#define IMX_CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFC_SEL_SHIFT 19
#define IMX_CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFC_SEL_MASK 0x80000
#define IMX_CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFC_SEL(v) (((v) << 19) & 0x80000)
/* Field FOUT_MASK -  */
#define IMX_CCM_ANALOG_ARM_PLL_MNIT_CTRL_FOUT_MASK_SHIFT 20
#define IMX_CCM_ANALOG_ARM_PLL_MNIT_CTRL_FOUT_MASK_MASK 0x100000
#define IMX_CCM_ANALOG_ARM_PLL_MNIT_CTRL_FOUT_MASK(v) (((v) << 20) & 0x100000)
/* Field LRD_EN -  */
#define IMX_CCM_ANALOG_ARM_PLL_MNIT_CTRL_LRD_EN_SHIFT 21
#define IMX_CCM_ANALOG_ARM_PLL_MNIT_CTRL_LRD_EN_MASK 0x200000
#define IMX_CCM_ANALOG_ARM_PLL_MNIT_CTRL_LRD_EN(v) (((v) << 21) & 0x200000)

/* Register SYS_PLL1_GEN_CTRL - SYS PLL1 General Function Control Register */
#define IMX_CCM_ANALOG_SYS_PLL1_GEN_CTRL         0x94
/* Field PLL_REF_CLK_SEL -  */
#define IMX_CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT 0
#define IMX_CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_MASK 0x3
#define IMX_CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_REF_CLK_SEL(v) (((v) << 0) & 0x3)
/* Field PAD_CLK_SEL -  */
#define IMX_CCM_ANALOG_SYS_PLL1_GEN_CTRL_PAD_CLK_SEL_SHIFT 2
#define IMX_CCM_ANALOG_SYS_PLL1_GEN_CTRL_PAD_CLK_SEL_MASK 0xC
#define IMX_CCM_ANALOG_SYS_PLL1_GEN_CTRL_PAD_CLK_SEL(v) (((v) << 2) & 0xC)
/* Field PLL_BYPASS -  */
#define IMX_CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_BYPASS_SHIFT 4
#define IMX_CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_BYPASS_MASK 0x10
#define IMX_CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_BYPASS(v) (((v) << 4) & 0x10)
/* Field PLL_RST_OVERRIDE -  */
#define IMX_CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT 8
#define IMX_CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_MASK 0x100
#define IMX_CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST_OVERRIDE(v) (((v) << 8) & 0x100)
/* Field PLL_RST -  */
#define IMX_CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST_SHIFT 9
#define IMX_CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST_MASK 0x200
#define IMX_CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST(v) (((v) << 9) & 0x200)
/* Field PLL_CLKE_OVERRIDE -  */
#define IMX_CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT 10
#define IMX_CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK 0x400
#define IMX_CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE(v) (((v) << 10) & 0x400)
/* Field PLL_CLKE -  */
#define IMX_CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_CLKE_SHIFT 11
#define IMX_CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_CLKE_MASK 0x800
#define IMX_CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_CLKE(v) (((v) << 11) & 0x800)
/* Field PLL_DIV2_CLKE_OVERRIDE -  */
#define IMX_CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV2_CLKE_OVERRIDE_SHIFT 12
#define IMX_CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV2_CLKE_OVERRIDE_MASK 0x1000
#define IMX_CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV2_CLKE_OVERRIDE(v) (((v) << 12) & 0x1000)
/* Field PLL_DIV2_CLKE -  */
#define IMX_CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV2_CLKE_SHIFT 13
#define IMX_CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV2_CLKE_MASK 0x2000
#define IMX_CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV2_CLKE(v) (((v) << 13) & 0x2000)
/* Field PLL_DIV3_CLKE_OVERRIDE -  */
#define IMX_CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV3_CLKE_OVERRIDE_SHIFT 14
#define IMX_CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV3_CLKE_OVERRIDE_MASK 0x4000
#define IMX_CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV3_CLKE_OVERRIDE(v) (((v) << 14) & 0x4000)
/* Field PLL_DIV3_CLKE -  */
#define IMX_CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV3_CLKE_SHIFT 15
#define IMX_CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV3_CLKE_MASK 0x8000
#define IMX_CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV3_CLKE(v) (((v) << 15) & 0x8000)
/* Field PLL_DIV4_CLKE_OVERRIDE -  */
#define IMX_CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV4_CLKE_OVERRIDE_SHIFT 16
#define IMX_CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV4_CLKE_OVERRIDE_MASK 0x10000
#define IMX_CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV4_CLKE_OVERRIDE(v) (((v) << 16) & 0x10000)
/* Field PLL_DIV4_CLKE -  */
#define IMX_CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV4_CLKE_SHIFT 17
#define IMX_CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV4_CLKE_MASK 0x20000
#define IMX_CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV4_CLKE(v) (((v) << 17) & 0x20000)
/* Field PLL_DIV5_CLKE_OVERRIDE -  */
#define IMX_CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV5_CLKE_OVERRIDE_SHIFT 18
#define IMX_CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV5_CLKE_OVERRIDE_MASK 0x40000
#define IMX_CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV5_CLKE_OVERRIDE(v) (((v) << 18) & 0x40000)
/* Field PLL_DIV5_CLKE -  */
#define IMX_CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV5_CLKE_SHIFT 19
#define IMX_CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV5_CLKE_MASK 0x80000
#define IMX_CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV5_CLKE(v) (((v) << 19) & 0x80000)
/* Field PLL_DIV6_CLKE_OVERRIDE -  */
#define IMX_CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV6_CLKE_OVERRIDE_SHIFT 20
#define IMX_CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV6_CLKE_OVERRIDE_MASK 0x100000
#define IMX_CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV6_CLKE_OVERRIDE(v) (((v) << 20) & 0x100000)
/* Field PLL_DIV6_CLKE -  */
#define IMX_CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV6_CLKE_SHIFT 21
#define IMX_CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV6_CLKE_MASK 0x200000
#define IMX_CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV6_CLKE(v) (((v) << 21) & 0x200000)
/* Field PLL_DIV8_CLKE_OVERRIDE -  */
#define IMX_CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV8_CLKE_OVERRIDE_SHIFT 22
#define IMX_CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV8_CLKE_OVERRIDE_MASK 0x400000
#define IMX_CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV8_CLKE_OVERRIDE(v) (((v) << 22) & 0x400000)
/* Field PLL_DIV8_CLKE -  */
#define IMX_CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV8_CLKE_SHIFT 23
#define IMX_CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV8_CLKE_MASK 0x800000
#define IMX_CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV8_CLKE(v) (((v) << 23) & 0x800000)
/* Field PLL_DIV10_CLKE_OVERRIDE -  */
#define IMX_CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV10_CLKE_OVERRIDE_SHIFT 24
#define IMX_CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV10_CLKE_OVERRIDE_MASK 0x1000000
#define IMX_CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV10_CLKE_OVERRIDE(v) (((v) << 24) & 0x1000000)
/* Field PLL_DIV10_CLKE -  */
#define IMX_CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV10_CLKE_SHIFT 25
#define IMX_CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV10_CLKE_MASK 0x2000000
#define IMX_CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV10_CLKE(v) (((v) << 25) & 0x2000000)
/* Field PLL_DIV20_CLKE_OVERRIDE -  */
#define IMX_CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV20_CLKE_OVERRIDE_SHIFT 26
#define IMX_CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV20_CLKE_OVERRIDE_MASK 0x4000000
#define IMX_CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV20_CLKE_OVERRIDE(v) (((v) << 26) & 0x4000000)
/* Field PLL_DIV20_CLKE -  */
#define IMX_CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV20_CLKE_SHIFT 27
#define IMX_CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV20_CLKE_MASK 0x8000000
#define IMX_CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV20_CLKE(v) (((v) << 27) & 0x8000000)
/* Field PLL_EXT_BYPASS -  */
#define IMX_CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_EXT_BYPASS_SHIFT 28
#define IMX_CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_EXT_BYPASS_MASK 0x10000000
#define IMX_CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_EXT_BYPASS(v) (((v) << 28) & 0x10000000)
/* Field PLL_LOCK_SEL -  */
#define IMX_CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_LOCK_SEL_SHIFT 29
#define IMX_CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_LOCK_SEL_MASK 0x20000000
#define IMX_CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_LOCK_SEL(v) (((v) << 29) & 0x20000000)
/* Field PLL_LOCK -  */
#define IMX_CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_LOCK_SHIFT 31
#define IMX_CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_LOCK_MASK 0x80000000
#define IMX_CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_LOCK(v) (((v) << 31) & 0x80000000)

/* Register SYS_PLL1_FDIV_CTL0 - SYS PLL1 Divide and Fraction Data Control 0 Register */
#define IMX_CCM_ANALOG_SYS_PLL1_FDIV_CTL0        0x98
/* Field PLL_POST_DIV -  */
#define IMX_CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_POST_DIV_SHIFT 0
#define IMX_CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_POST_DIV_MASK 0x7
#define IMX_CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_POST_DIV(v) (((v) << 0) & 0x7)
/* Field PLL_PRE_DIV -  */
#define IMX_CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_PRE_DIV_SHIFT 4
#define IMX_CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_PRE_DIV_MASK 0x3F0
#define IMX_CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_PRE_DIV(v) (((v) << 4) & 0x3F0)
/* Field PLL_MAIN_DIV -  */
#define IMX_CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_MAIN_DIV_SHIFT 12
#define IMX_CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_MAIN_DIV_MASK 0x3FF000
#define IMX_CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_MAIN_DIV(v) (((v) << 12) & 0x3FF000)

/* Register SYS_PLL1_LOCKD_CTRL - PLL Lock Detector Control Register */
#define IMX_CCM_ANALOG_SYS_PLL1_LOCKD_CTRL       0x9C
/* Field LOCK_CON_IN -  */
#define IMX_CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_IN_SHIFT 0
#define IMX_CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_IN_MASK 0x3
#define IMX_CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_IN(v) (((v) << 0) & 0x3)
/* Field LOCK_CON_OUT -  */
#define IMX_CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_OUT_SHIFT 2
#define IMX_CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_OUT_MASK 0xC
#define IMX_CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_OUT(v) (((v) << 2) & 0xC)
/* Field LOCK_CON_DLY -  */
#define IMX_CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_DLY_SHIFT 4
#define IMX_CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_DLY_MASK 0x30
#define IMX_CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_DLY(v) (((v) << 4) & 0x30)

/* Register SYS_PLL1_MNIT_CTRL - PLL Monitoring Control Register */
#define IMX_CCM_ANALOG_SYS_PLL1_MNIT_CTRL        0x100
/* Field ICP -  */
#define IMX_CCM_ANALOG_SYS_PLL1_MNIT_CTRL_ICP_SHIFT 0
#define IMX_CCM_ANALOG_SYS_PLL1_MNIT_CTRL_ICP_MASK 0x3
#define IMX_CCM_ANALOG_SYS_PLL1_MNIT_CTRL_ICP(v) (((v) << 0) & 0x3)
/* Field AFC_EN -  */
#define IMX_CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFC_EN_SHIFT 2
#define IMX_CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFC_EN_MASK 0x4
#define IMX_CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFC_EN(v) (((v) << 2) & 0x4)
/* Field EXTAFC -  */
#define IMX_CCM_ANALOG_SYS_PLL1_MNIT_CTRL_EXTAFC_SHIFT 3
#define IMX_CCM_ANALOG_SYS_PLL1_MNIT_CTRL_EXTAFC_MASK 0xF8
#define IMX_CCM_ANALOG_SYS_PLL1_MNIT_CTRL_EXTAFC(v) (((v) << 3) & 0xF8)
/* Field FEED_EN -  */
#define IMX_CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FEED_EN_SHIFT 13
#define IMX_CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FEED_EN_MASK 0x2000
#define IMX_CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FEED_EN(v) (((v) << 13) & 0x2000)
/* Field FSEL -  */
#define IMX_CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FSEL_SHIFT 14
#define IMX_CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FSEL_MASK 0x4000
#define IMX_CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FSEL(v) (((v) << 14) & 0x4000)
/* Field AFCINIT_SEL -  */
#define IMX_CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFCINIT_SEL_SHIFT 16
#define IMX_CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFCINIT_SEL_MASK 0x10000
#define IMX_CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFCINIT_SEL(v) (((v) << 16) & 0x10000)
/* Field PBIAS_CTRL_EN -  */
#define IMX_CCM_ANALOG_SYS_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT 17
#define IMX_CCM_ANALOG_SYS_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_MASK 0x20000
#define IMX_CCM_ANALOG_SYS_PLL1_MNIT_CTRL_PBIAS_CTRL_EN(v) (((v) << 17) & 0x20000)
/* Field PBIAS_CTRL -  */
#define IMX_CCM_ANALOG_SYS_PLL1_MNIT_CTRL_PBIAS_CTRL_SHIFT 18
#define IMX_CCM_ANALOG_SYS_PLL1_MNIT_CTRL_PBIAS_CTRL_MASK 0x40000
#define IMX_CCM_ANALOG_SYS_PLL1_MNIT_CTRL_PBIAS_CTRL(v) (((v) << 18) & 0x40000)
/* Field AFC_SEL -  */
#define IMX_CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFC_SEL_SHIFT 19
#define IMX_CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFC_SEL_MASK 0x80000
#define IMX_CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFC_SEL(v) (((v) << 19) & 0x80000)
/* Field FOUT_MASK -  */
#define IMX_CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FOUT_MASK_SHIFT 20
#define IMX_CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FOUT_MASK_MASK 0x100000
#define IMX_CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FOUT_MASK(v) (((v) << 20) & 0x100000)
/* Field LRD_EN -  */
#define IMX_CCM_ANALOG_SYS_PLL1_MNIT_CTRL_LRD_EN_SHIFT 21
#define IMX_CCM_ANALOG_SYS_PLL1_MNIT_CTRL_LRD_EN_MASK 0x200000
#define IMX_CCM_ANALOG_SYS_PLL1_MNIT_CTRL_LRD_EN(v) (((v) << 21) & 0x200000)

/* Register SYS_PLL2_GEN_CTRL - SYS PLL2 General Function Control Register */
#define IMX_CCM_ANALOG_SYS_PLL2_GEN_CTRL         0x104
/* Field PLL_REF_CLK_SEL -  */
#define IMX_CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT 0
#define IMX_CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_REF_CLK_SEL_MASK 0x3
#define IMX_CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_REF_CLK_SEL(v) (((v) << 0) & 0x3)
/* Field PAD_CLK_SEL -  */
#define IMX_CCM_ANALOG_SYS_PLL2_GEN_CTRL_PAD_CLK_SEL_SHIFT 2
#define IMX_CCM_ANALOG_SYS_PLL2_GEN_CTRL_PAD_CLK_SEL_MASK 0xC
#define IMX_CCM_ANALOG_SYS_PLL2_GEN_CTRL_PAD_CLK_SEL(v) (((v) << 2) & 0xC)
/* Field PLL_BYPASS -  */
#define IMX_CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_BYPASS_SHIFT 4
#define IMX_CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_BYPASS_MASK 0x10
#define IMX_CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_BYPASS(v) (((v) << 4) & 0x10)
/* Field PLL_RST_OVERRIDE -  */
#define IMX_CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT 8
#define IMX_CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_RST_OVERRIDE_MASK 0x100
#define IMX_CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_RST_OVERRIDE(v) (((v) << 8) & 0x100)
/* Field PLL_RST -  */
#define IMX_CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_RST_SHIFT 9
#define IMX_CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_RST_MASK 0x200
#define IMX_CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_RST(v) (((v) << 9) & 0x200)
/* Field PLL_CLKE_OVERRIDE -  */
#define IMX_CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT 10
#define IMX_CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK 0x400
#define IMX_CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_CLKE_OVERRIDE(v) (((v) << 10) & 0x400)
/* Field PLL_CLKE -  */
#define IMX_CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_CLKE_SHIFT 11
#define IMX_CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_CLKE_MASK 0x800
#define IMX_CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_CLKE(v) (((v) << 11) & 0x800)
/* Field PLL_DIV2_CLKE_OVERRIDE -  */
#define IMX_CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV2_CLKE_OVERRIDE_SHIFT 12
#define IMX_CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV2_CLKE_OVERRIDE_MASK 0x1000
#define IMX_CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV2_CLKE_OVERRIDE(v) (((v) << 12) & 0x1000)
/* Field PLL_DIV2_CLKE -  */
#define IMX_CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV2_CLKE_SHIFT 13
#define IMX_CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV2_CLKE_MASK 0x2000
#define IMX_CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV2_CLKE(v) (((v) << 13) & 0x2000)
/* Field PLL_DIV3_CLKE_OVERRIDE -  */
#define IMX_CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV3_CLKE_OVERRIDE_SHIFT 14
#define IMX_CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV3_CLKE_OVERRIDE_MASK 0x4000
#define IMX_CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV3_CLKE_OVERRIDE(v) (((v) << 14) & 0x4000)
/* Field PLL_DIV3_CLKE -  */
#define IMX_CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV3_CLKE_SHIFT 15
#define IMX_CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV3_CLKE_MASK 0x8000
#define IMX_CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV3_CLKE(v) (((v) << 15) & 0x8000)
/* Field PLL_DIV4_CLKE_OVERRIDE -  */
#define IMX_CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV4_CLKE_OVERRIDE_SHIFT 16
#define IMX_CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV4_CLKE_OVERRIDE_MASK 0x10000
#define IMX_CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV4_CLKE_OVERRIDE(v) (((v) << 16) & 0x10000)
/* Field PLL_DIV4_CLKE -  */
#define IMX_CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV4_CLKE_SHIFT 17
#define IMX_CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV4_CLKE_MASK 0x20000
#define IMX_CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV4_CLKE(v) (((v) << 17) & 0x20000)
/* Field PLL_DIV5_CLKE_OVERRIDE -  */
#define IMX_CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV5_CLKE_OVERRIDE_SHIFT 18
#define IMX_CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV5_CLKE_OVERRIDE_MASK 0x40000
#define IMX_CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV5_CLKE_OVERRIDE(v) (((v) << 18) & 0x40000)
/* Field PLL_DIV5_CLKE -  */
#define IMX_CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV5_CLKE_SHIFT 19
#define IMX_CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV5_CLKE_MASK 0x80000
#define IMX_CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV5_CLKE(v) (((v) << 19) & 0x80000)
/* Field PLL_DIV6_CLKE_OVERRIDE -  */
#define IMX_CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV6_CLKE_OVERRIDE_SHIFT 20
#define IMX_CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV6_CLKE_OVERRIDE_MASK 0x100000
#define IMX_CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV6_CLKE_OVERRIDE(v) (((v) << 20) & 0x100000)
/* Field PLL_DIV6_CLKE -  */
#define IMX_CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV6_CLKE_SHIFT 21
#define IMX_CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV6_CLKE_MASK 0x200000
#define IMX_CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV6_CLKE(v) (((v) << 21) & 0x200000)
/* Field PLL_DIV8_CLKE_OVERRIDE -  */
#define IMX_CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV8_CLKE_OVERRIDE_SHIFT 22
#define IMX_CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV8_CLKE_OVERRIDE_MASK 0x400000
#define IMX_CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV8_CLKE_OVERRIDE(v) (((v) << 22) & 0x400000)
/* Field PLL_DIV8_CLKE -  */
#define IMX_CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV8_CLKE_SHIFT 23
#define IMX_CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV8_CLKE_MASK 0x800000
#define IMX_CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV8_CLKE(v) (((v) << 23) & 0x800000)
/* Field PLL_DIV10_CLKE_OVERRIDE -  */
#define IMX_CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV10_CLKE_OVERRIDE_SHIFT 24
#define IMX_CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV10_CLKE_OVERRIDE_MASK 0x1000000
#define IMX_CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV10_CLKE_OVERRIDE(v) (((v) << 24) & 0x1000000)
/* Field PLL_DIV10_CLKE -  */
#define IMX_CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV10_CLKE_SHIFT 25
#define IMX_CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV10_CLKE_MASK 0x2000000
#define IMX_CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV10_CLKE(v) (((v) << 25) & 0x2000000)
/* Field PLL_DIV20_CLKE_OVERRIDE -  */
#define IMX_CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV20_CLKE_OVERRIDE_SHIFT 26
#define IMX_CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV20_CLKE_OVERRIDE_MASK 0x4000000
#define IMX_CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV20_CLKE_OVERRIDE(v) (((v) << 26) & 0x4000000)
/* Field PLL_DIV20_CLKE -  */
#define IMX_CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV20_CLKE_SHIFT 27
#define IMX_CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV20_CLKE_MASK 0x8000000
#define IMX_CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV20_CLKE(v) (((v) << 27) & 0x8000000)
/* Field PLL_EXT_BYPASS -  */
#define IMX_CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_EXT_BYPASS_SHIFT 28
#define IMX_CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_EXT_BYPASS_MASK 0x10000000
#define IMX_CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_EXT_BYPASS(v) (((v) << 28) & 0x10000000)
/* Field PLL_LOCK_SEL -  */
#define IMX_CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_LOCK_SEL_SHIFT 29
#define IMX_CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_LOCK_SEL_MASK 0x20000000
#define IMX_CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_LOCK_SEL(v) (((v) << 29) & 0x20000000)
/* Field PLL_LOCK -  */
#define IMX_CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_LOCK_SHIFT 31
#define IMX_CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_LOCK_MASK 0x80000000
#define IMX_CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_LOCK(v) (((v) << 31) & 0x80000000)

/* Register SYS_PLL2_FDIV_CTL0 - SYS PLL2 Divide and Fraction Data Control 0 Register */
#define IMX_CCM_ANALOG_SYS_PLL2_FDIV_CTL0        0x108
/* Field PLL_POST_DIV -  */
#define IMX_CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_POST_DIV_SHIFT 0
#define IMX_CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_POST_DIV_MASK 0x7
#define IMX_CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_POST_DIV(v) (((v) << 0) & 0x7)
/* Field PLL_PRE_DIV -  */
#define IMX_CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_PRE_DIV_SHIFT 4
#define IMX_CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_PRE_DIV_MASK 0x3F0
#define IMX_CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_PRE_DIV(v) (((v) << 4) & 0x3F0)
/* Field PLL_MAIN_DIV -  */
#define IMX_CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_MAIN_DIV_SHIFT 12
#define IMX_CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_MAIN_DIV_MASK 0x3FF000
#define IMX_CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_MAIN_DIV(v) (((v) << 12) & 0x3FF000)

/* Register SYS_PLL2_LOCKD_CTRL - PLL Lock Detector Control Register */
#define IMX_CCM_ANALOG_SYS_PLL2_LOCKD_CTRL       0x10C
/* Field LOCK_CON_IN -  */
#define IMX_CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_IN_SHIFT 0
#define IMX_CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_IN_MASK 0x3
#define IMX_CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_IN(v) (((v) << 0) & 0x3)
/* Field LOCK_CON_OUT -  */
#define IMX_CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_OUT_SHIFT 2
#define IMX_CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_OUT_MASK 0xC
#define IMX_CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_OUT(v) (((v) << 2) & 0xC)
/* Field LOCK_CON_DLY -  */
#define IMX_CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_DLY_SHIFT 4
#define IMX_CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_DLY_MASK 0x30
#define IMX_CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_DLY(v) (((v) << 4) & 0x30)

/* Register SYS_PLL2_MNIT_CTRL - PLL Monitoring Control Register */
#define IMX_CCM_ANALOG_SYS_PLL2_MNIT_CTRL        0x110
/* Field ICP -  */
#define IMX_CCM_ANALOG_SYS_PLL2_MNIT_CTRL_ICP_SHIFT 0
#define IMX_CCM_ANALOG_SYS_PLL2_MNIT_CTRL_ICP_MASK 0x3
#define IMX_CCM_ANALOG_SYS_PLL2_MNIT_CTRL_ICP(v) (((v) << 0) & 0x3)
/* Field AFC_EN -  */
#define IMX_CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFC_EN_SHIFT 2
#define IMX_CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFC_EN_MASK 0x4
#define IMX_CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFC_EN(v) (((v) << 2) & 0x4)
/* Field EXTAFC -  */
#define IMX_CCM_ANALOG_SYS_PLL2_MNIT_CTRL_EXTAFC_SHIFT 3
#define IMX_CCM_ANALOG_SYS_PLL2_MNIT_CTRL_EXTAFC_MASK 0xF8
#define IMX_CCM_ANALOG_SYS_PLL2_MNIT_CTRL_EXTAFC(v) (((v) << 3) & 0xF8)
/* Field FEED_EN -  */
#define IMX_CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FEED_EN_SHIFT 13
#define IMX_CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FEED_EN_MASK 0x2000
#define IMX_CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FEED_EN(v) (((v) << 13) & 0x2000)
/* Field FSEL -  */
#define IMX_CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FSEL_SHIFT 14
#define IMX_CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FSEL_MASK 0x4000
#define IMX_CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FSEL(v) (((v) << 14) & 0x4000)
/* Field AFCINIT_SEL -  */
#define IMX_CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFCINIT_SEL_SHIFT 16
#define IMX_CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFCINIT_SEL_MASK 0x10000
#define IMX_CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFCINIT_SEL(v) (((v) << 16) & 0x10000)
/* Field PBIAS_CTRL_EN -  */
#define IMX_CCM_ANALOG_SYS_PLL2_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT 17
#define IMX_CCM_ANALOG_SYS_PLL2_MNIT_CTRL_PBIAS_CTRL_EN_MASK 0x20000
#define IMX_CCM_ANALOG_SYS_PLL2_MNIT_CTRL_PBIAS_CTRL_EN(v) (((v) << 17) & 0x20000)
/* Field PBIAS_CTRL -  */
#define IMX_CCM_ANALOG_SYS_PLL2_MNIT_CTRL_PBIAS_CTRL_SHIFT 18
#define IMX_CCM_ANALOG_SYS_PLL2_MNIT_CTRL_PBIAS_CTRL_MASK 0x40000
#define IMX_CCM_ANALOG_SYS_PLL2_MNIT_CTRL_PBIAS_CTRL(v) (((v) << 18) & 0x40000)
/* Field AFC_SEL -  */
#define IMX_CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFC_SEL_SHIFT 19
#define IMX_CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFC_SEL_MASK 0x80000
#define IMX_CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFC_SEL(v) (((v) << 19) & 0x80000)
/* Field FOUT_MASK -  */
#define IMX_CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FOUT_MASK_SHIFT 20
#define IMX_CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FOUT_MASK_MASK 0x100000
#define IMX_CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FOUT_MASK(v) (((v) << 20) & 0x100000)
/* Field LRD_EN -  */
#define IMX_CCM_ANALOG_SYS_PLL2_MNIT_CTRL_LRD_EN_SHIFT 21
#define IMX_CCM_ANALOG_SYS_PLL2_MNIT_CTRL_LRD_EN_MASK 0x200000
#define IMX_CCM_ANALOG_SYS_PLL2_MNIT_CTRL_LRD_EN(v) (((v) << 21) & 0x200000)

/* Register SYS_PLL3_GEN_CTRL - SYS PLL3 General Function Control Register */
#define IMX_CCM_ANALOG_SYS_PLL3_GEN_CTRL         0x114
/* Field PLL_REF_CLK_SEL -  */
#define IMX_CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT 0
#define IMX_CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_REF_CLK_SEL_MASK 0x3
#define IMX_CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_REF_CLK_SEL(v) (((v) << 0) & 0x3)
/* Field PAD_CLK_SEL -  */
#define IMX_CCM_ANALOG_SYS_PLL3_GEN_CTRL_PAD_CLK_SEL_SHIFT 2
#define IMX_CCM_ANALOG_SYS_PLL3_GEN_CTRL_PAD_CLK_SEL_MASK 0xC
#define IMX_CCM_ANALOG_SYS_PLL3_GEN_CTRL_PAD_CLK_SEL(v) (((v) << 2) & 0xC)
/* Field PLL_BYPASS -  */
#define IMX_CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_BYPASS_SHIFT 4
#define IMX_CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_BYPASS_MASK 0x10
#define IMX_CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_BYPASS(v) (((v) << 4) & 0x10)
/* Field PLL_RST_OVERRIDE -  */
#define IMX_CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT 8
#define IMX_CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_RST_OVERRIDE_MASK 0x100
#define IMX_CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_RST_OVERRIDE(v) (((v) << 8) & 0x100)
/* Field PLL_RST -  */
#define IMX_CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_RST_SHIFT 9
#define IMX_CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_RST_MASK 0x200
#define IMX_CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_RST(v) (((v) << 9) & 0x200)
/* Field PLL_CLKE_OVERRIDE -  */
#define IMX_CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT 10
#define IMX_CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK 0x400
#define IMX_CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_CLKE_OVERRIDE(v) (((v) << 10) & 0x400)
/* Field PLL_CLKE -  */
#define IMX_CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_CLKE_SHIFT 11
#define IMX_CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_CLKE_MASK 0x800
#define IMX_CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_CLKE(v) (((v) << 11) & 0x800)
/* Field PLL_EXT_BYPASS -  */
#define IMX_CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_EXT_BYPASS_SHIFT 28
#define IMX_CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_EXT_BYPASS_MASK 0x10000000
#define IMX_CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_EXT_BYPASS(v) (((v) << 28) & 0x10000000)
/* Field PLL_LOCK_SEL -  */
#define IMX_CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_LOCK_SEL_SHIFT 29
#define IMX_CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_LOCK_SEL_MASK 0x20000000
#define IMX_CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_LOCK_SEL(v) (((v) << 29) & 0x20000000)
/* Field PLL_LOCK -  */
#define IMX_CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_LOCK_SHIFT 31
#define IMX_CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_LOCK_MASK 0x80000000
#define IMX_CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_LOCK(v) (((v) << 31) & 0x80000000)

/* Register SYS_PLL3_FDIV_CTL0 - SYS PLL3 Divide and Fraction Data Control 0 Register */
#define IMX_CCM_ANALOG_SYS_PLL3_FDIV_CTL0        0x118
/* Field PLL_POST_DIV -  */
#define IMX_CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_POST_DIV_SHIFT 0
#define IMX_CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_POST_DIV_MASK 0x7
#define IMX_CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_POST_DIV(v) (((v) << 0) & 0x7)
/* Field PLL_PRE_DIV -  */
#define IMX_CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_PRE_DIV_SHIFT 4
#define IMX_CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_PRE_DIV_MASK 0x3F0
#define IMX_CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_PRE_DIV(v) (((v) << 4) & 0x3F0)
/* Field PLL_MAIN_DIV -  */
#define IMX_CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_MAIN_DIV_SHIFT 12
#define IMX_CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_MAIN_DIV_MASK 0x3FF000
#define IMX_CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_MAIN_DIV(v) (((v) << 12) & 0x3FF000)

/* Register SYS_PLL3_LOCKD_CTRL - PLL Lock Detector Control Register */
#define IMX_CCM_ANALOG_SYS_PLL3_LOCKD_CTRL       0x11C
/* Field LOCK_CON_IN -  */
#define IMX_CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_IN_SHIFT 0
#define IMX_CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_IN_MASK 0x3
#define IMX_CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_IN(v) (((v) << 0) & 0x3)
/* Field LOCK_CON_OUT -  */
#define IMX_CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_OUT_SHIFT 2
#define IMX_CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_OUT_MASK 0xC
#define IMX_CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_OUT(v) (((v) << 2) & 0xC)
/* Field LOCK_CON_DLY -  */
#define IMX_CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_DLY_SHIFT 4
#define IMX_CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_DLY_MASK 0x30
#define IMX_CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_DLY(v) (((v) << 4) & 0x30)

/* Register SYS_PLL3_MNIT_CTRL - PLL Monitoring Control Register */
#define IMX_CCM_ANALOG_SYS_PLL3_MNIT_CTRL        0x120
/* Field ICP -  */
#define IMX_CCM_ANALOG_SYS_PLL3_MNIT_CTRL_ICP_SHIFT 0
#define IMX_CCM_ANALOG_SYS_PLL3_MNIT_CTRL_ICP_MASK 0x3
#define IMX_CCM_ANALOG_SYS_PLL3_MNIT_CTRL_ICP(v) (((v) << 0) & 0x3)
/* Field AFC_EN -  */
#define IMX_CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFC_EN_SHIFT 2
#define IMX_CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFC_EN_MASK 0x4
#define IMX_CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFC_EN(v) (((v) << 2) & 0x4)
/* Field EXTAFC -  */
#define IMX_CCM_ANALOG_SYS_PLL3_MNIT_CTRL_EXTAFC_SHIFT 3
#define IMX_CCM_ANALOG_SYS_PLL3_MNIT_CTRL_EXTAFC_MASK 0xF8
#define IMX_CCM_ANALOG_SYS_PLL3_MNIT_CTRL_EXTAFC(v) (((v) << 3) & 0xF8)
/* Field FEED_EN -  */
#define IMX_CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FEED_EN_SHIFT 13
#define IMX_CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FEED_EN_MASK 0x2000
#define IMX_CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FEED_EN(v) (((v) << 13) & 0x2000)
/* Field FSEL -  */
#define IMX_CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FSEL_SHIFT 14
#define IMX_CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FSEL_MASK 0x4000
#define IMX_CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FSEL(v) (((v) << 14) & 0x4000)
/* Field AFCINIT_SEL -  */
#define IMX_CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFCINIT_SEL_SHIFT 16
#define IMX_CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFCINIT_SEL_MASK 0x10000
#define IMX_CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFCINIT_SEL(v) (((v) << 16) & 0x10000)
/* Field PBIAS_CTRL_EN -  */
#define IMX_CCM_ANALOG_SYS_PLL3_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT 17
#define IMX_CCM_ANALOG_SYS_PLL3_MNIT_CTRL_PBIAS_CTRL_EN_MASK 0x20000
#define IMX_CCM_ANALOG_SYS_PLL3_MNIT_CTRL_PBIAS_CTRL_EN(v) (((v) << 17) & 0x20000)
/* Field PBIAS_CTRL -  */
#define IMX_CCM_ANALOG_SYS_PLL3_MNIT_CTRL_PBIAS_CTRL_SHIFT 18
#define IMX_CCM_ANALOG_SYS_PLL3_MNIT_CTRL_PBIAS_CTRL_MASK 0x40000
#define IMX_CCM_ANALOG_SYS_PLL3_MNIT_CTRL_PBIAS_CTRL(v) (((v) << 18) & 0x40000)
/* Field AFC_SEL -  */
#define IMX_CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFC_SEL_SHIFT 19
#define IMX_CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFC_SEL_MASK 0x80000
#define IMX_CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFC_SEL(v) (((v) << 19) & 0x80000)
/* Field FOUT_MASK -  */
#define IMX_CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FOUT_MASK_SHIFT 20
#define IMX_CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FOUT_MASK_MASK 0x100000
#define IMX_CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FOUT_MASK(v) (((v) << 20) & 0x100000)
/* Field LRD_EN -  */
#define IMX_CCM_ANALOG_SYS_PLL3_MNIT_CTRL_LRD_EN_SHIFT 21
#define IMX_CCM_ANALOG_SYS_PLL3_MNIT_CTRL_LRD_EN_MASK 0x200000
#define IMX_CCM_ANALOG_SYS_PLL3_MNIT_CTRL_LRD_EN(v) (((v) << 21) & 0x200000)

/* Register OSC_MISC_CFG - Osc Misc Configuration Register */
#define IMX_CCM_ANALOG_OSC_MISC_CFG              0x124
/* Field OSC_32K_SEL -  */
#define IMX_CCM_ANALOG_OSC_MISC_CFG_OSC_32K_SEL_SHIFT 0
#define IMX_CCM_ANALOG_OSC_MISC_CFG_OSC_32K_SEL_MASK 0x1
#define IMX_CCM_ANALOG_OSC_MISC_CFG_OSC_32K_SEL(v) (((v) << 0) & 0x1)

/* Register ANAMIX_PLL_MNIT_CTL - PLL Clock Output for Test Enable and Select Register */
#define IMX_CCM_ANALOG_ANAMIX_PLL_MNIT_CTL       0x128
/* Field CLKOUT1_OUTPUT_DIV_VAL -  */
#define IMX_CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_DIV_VAL_SHIFT 0
#define IMX_CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_DIV_VAL_MASK 0xF
#define IMX_CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_DIV_VAL(v) (((v) << 0) & 0xF)
/* Field CLKOUT1_OUTPUT_SEL -  */
#define IMX_CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_SEL_SHIFT 4
#define IMX_CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_SEL_MASK 0xF0
#define IMX_CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_SEL(v) (((v) << 4) & 0xF0)
/* Field CLKOUT1_OUTPUT_CKE -  */
#define IMX_CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_CKE_SHIFT 8
#define IMX_CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_CKE_MASK 0x100
#define IMX_CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_CKE(v) (((v) << 8) & 0x100)
/* Field CLKOUT2_OUTPUT_DIV_VAL -  */
#define IMX_CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_DIV_VAL_SHIFT 16
#define IMX_CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_DIV_VAL_MASK 0xF0000
#define IMX_CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_DIV_VAL(v) (((v) << 16) & 0xF0000)
/* Field CLKOUT2_OUTPUT_SEL -  */
#define IMX_CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_SEL_SHIFT 20
#define IMX_CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_SEL_MASK 0xF00000
#define IMX_CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_SEL(v) (((v) << 20) & 0xF00000)
/* Field CLKOUT2_OUTPUT_CKE -  */
#define IMX_CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_CKE_SHIFT 24
#define IMX_CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_CKE_MASK 0x1000000
#define IMX_CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_CKE(v) (((v) << 24) & 0x1000000)

/* Register DIGPROG - DIGPROG Register */
#define IMX_CCM_ANALOG_DIGPROG                   0x800
/* Field DIGPROG_MINOR -  */
#define IMX_CCM_ANALOG_DIGPROG_DIGPROG_MINOR_SHIFT 0
#define IMX_CCM_ANALOG_DIGPROG_DIGPROG_MINOR_MASK 0xFF
#define IMX_CCM_ANALOG_DIGPROG_DIGPROG_MINOR(v)  (((v) << 0) & 0xFF)
/* Field DIGPROG_MAJOR_LOWER -  */
#define IMX_CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_LOWER_SHIFT 8
#define IMX_CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_LOWER_MASK 0xFF00
#define IMX_CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_LOWER(v) (((v) << 8) & 0xFF00)
/* Field DIGPROG_MAJOR_UPPER -  */
#define IMX_CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_UPPER_SHIFT 16
#define IMX_CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_UPPER_MASK 0xFF0000
#define IMX_CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_UPPER(v) (((v) << 16) & 0xFF0000)

#endif /* IMX_CCM_ANALOG_H */

#if defined(__QNXNTO__) && defined(__USESRCVERSION)
#include <sys/srcversion.h>
__SRCVERSION("$URL: http://svn.ott.qnx.com/product/hardware/branches/release/hardware/startup/boards/public/aarch64/imx8mm/imx_ccm_analog.h $ $Rev: 994161 $")
#endif
