/*
 * Copyright 2022, 2023, BlackBerry Limited. All rights reserved.
 *
 * Licensed under the Apache License, Version 2.0 (the "License"). You
 * may not reproduce, modify or distribute this software except in
 * compliance with the License. You may obtain a copy of the License
 * at: http://www.apache.org/licenses/LICENSE-2.
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" basis,
 * WITHOUT WARRANTIES OF ANY KIND, either express or implied.
 *
 * This file may contain contributions from others, either as
 * contributors under the License or as licensors under other terms.
 * Please review this entire file for other proprietary rights or license
 * notices, as well as the QNX Development Suite License Guide at
 * http://licensing.qnx.com/license-guide/ for other information.
 * $
 */

#ifndef _PCAL6524_INCLUDE_H_
#define _PCAL6524_INCLUDE_H_

#define PCAL6524_INPUT_PORT0                    0x00
#define PCAL6524_INPUT_PORT1                    0x01
#define PCAL6524_INPUT_PORT2                    0x02
#define PCAL6524_OUTPUT_PORT0                   0x04
#define PCAL6524_OUTPUT_PORT1                   0x05
#define PCAL6524_OUTPUT_PORT2                   0x06
#define PCAL6524_POLARITY_INVERSION_PORT0       0x08
#define PCAL6524_POLARITY_INVERSION_PORT1       0x09
#define PCAL6524_POLARITY_INVERSION_PORT2       0x0A
#define PCAL6524_CONFIGURATION_PORT0            0x0C
#define PCAL6524_CONFIGURATION_PORT1            0x0D
#define PCAL6524_CONFIGURATION_PORT2            0x0E
#define PCAL6524_OUT_DRIVE_STRENGTH_PORT0A      0x40
#define PCAL6524_OUT_DRIVE_STRENGTH_PORT0B      0x41
#define PCAL6524_OUT_DRIVE_STRENGTH_PORT1A      0x42
#define PCAL6524_OUT_DRIVE_STRENGTH_PORT1B      0x43
#define PCAL6524_OUT_DRIVE_STRENGTH_PORT2A      0x44
#define PCAL6524_OUT_DRIVE_STRENGTH_PORT2B      0x45
#define PCAL6524_INPUT_LATCH_PORT0              0x48
#define PCAL6524_INPUT_LATCH_PORT1              0x49
#define PCAL6524_INPUT_LATCH_PORT2              0x4A
#define PCAL6524_PULL_ENABLE_PORT0              0x4C
#define PCAL6524_PULL_ENABLE_PORT1              0x4D
#define PCAL6524_PULL_ENABLE_PORT2              0x4E
#define PCAL6524_PULL_SELECT_PORT0              0x50
#define PCAL6524_PULL_SELECT_PORT1              0x51
#define PCAL6524_PULL_SELECT_PORT2              0x52
#define PCAL6524_INTERRUPT_MASK_PORT0           0x54
#define PCAL6524_INTERRUPT_MASK_PORT1           0x55
#define PCAL6524_INTERRUPT_MASK_PORT2           0x56
#define PCAL6524_INTERRUPT_STATUS_PORT0         0x58
#define PCAL6524_INTERRUPT_STATUS_PORT1         0x59
#define PCAL6524_INTERRUPT_STATUS_PORT2         0x5A
#define PCAL6524_OUTPUT_PORT_CONFIGURATION      0x5C
#define PCAL6524_INTERRUPT_EDGE_PORT0A          0x60
#define PCAL6524_INTERRUPT_EDGE_PORT0B          0x61
#define PCAL6524_INTERRUPT_EDGE_PORT1A          0x62
#define PCAL6524_INTERRUPT_EDGE_PORT1B          0x63
#define PCAL6524_INTERRUPT_EDGE_PORT2A          0x64
#define PCAL6524_INTERRUPT_EDGE_PORT2B          0x65
#define PCAL6524_INTERRUPT_CLEAR_PORT0          0x68
#define PCAL6524_INTERRUPT_CLEAR_PORT1          0x69
#define PCAL6524_INTERRUPT_CLEAR_PORT2          0x6A
#define PCAL6524_INPUT_STATUS_PORT0             0x6C
#define PCAL6524_INPUT_STATUS_PORT1             0x6D
#define PCAL6524_INPUT_STATUS_PORT2             0x6E
#define PCAL6524_INVID_PIN_CONFIG_PORT0         0x70
#define PCAL6524_INVID_PIN_CONFIG_PORT1         0x71
#define PCAL6524_INVID_PIN_CONFIG_PORT2         0x72
#define PCAL6524_SWITCH_DEBOUNCE_PORT0          0x74
#define PCAL6524_SWITCH_DEBOUNCE_PORT1          0x75
#define PCAL6524_SWITCH_DEBOUNCE_COUNT_PORT0    0x76

#endif

