/*
 * $QNXLicenseC:
 * Copyright 2016, QNX Software Systems.
 *
 * Licensed under the Apache License, Version 2.0 (the "License"). You
 * may not reproduce, modify or distribute this software except in
 * compliance with the License. You may obtain a copy of the License
 * at: http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" basis,
 * WITHOUT WARRANTIES OF ANY KIND, either express or implied.
 *
 * This file may contain contributions from others, either as
 * contributors under the License or as licensors under other terms.
 * Please review this entire file for other proprietary rights or license
 * notices, as well as the QNX Development Suite License Guide at
 * http://licensing.qnx.com/license-guide/ for other information.
 * $
 */

#ifndef __RENESAS_REG_H_INCLUDED
#define __RENESAS_REG_H_INCLUDED

/* Bit definitions */
#define BIT0				0x00000001
#define BIT1				0x00000002
#define BIT2				0x00000004
#define BIT3				0x00000008
#define BIT4				0x00000010
#define BIT5				0x00000020
#define BIT6				0x00000040
#define BIT7				0x00000080
#define BIT8				0x00000100
#define BIT9				0x00000200
#define BIT10				0x00000400
#define BIT11				0x00000800
#define BIT12				0x00001000
#define BIT13				0x00002000
#define BIT14				0x00004000
#define BIT15				0x00008000
#define BIT16				0x00010000
#define BIT17				0x00020000
#define BIT18				0x00040000
#define BIT19				0x00080000
#define BIT20				0x00100000
#define BIT21				0x00200000
#define BIT22				0x00400000
#define BIT23				0x00800000
#define BIT24				0x01000000
#define BIT25				0x02000000
#define BIT26				0x04000000
#define BIT27				0x08000000
#define BIT28				0x10000000
#define BIT29				0x20000000
#define BIT30				0x40000000
#define BIT31				0x80000000

/* L2 Cache*/
#define CACHE_L2C310_BASE		0xF0100000
#define MERAM_BASE			0xE8080000
#define HPB_BASE			0xE6000000
#define RWDT_BASE			0xE6020000
#define SWDT_BASE			0xE6030000
#define GPIO_BASE			0xE6050000
#define PFC_BASE			0xE6060000

/* The base address of counter module control */
#define CNTCTL_BASE			0xE6080000
#define CMT1_BASE			0xE6130000
#define CPG_BASE			0xE6150000

/* On chip secure RAM */
#define SECRAM_BASE			0xE6300000
#define MMCIF0_BASE			0xEE200000
#define MMCIF1_BASE			0xEE220000
#define SDHI0_BASE			0xEE100000
#define SDHI1_BASE			0xEE120000
#define SDHI2_BASE			0xEE140000
#define SDHI3_BASE			0xEE160000
#define SBSC1_BASE			0xFE400000
#define BSC_BASE			0xFEC10000
#define SYSC_BASE			0xE6180000
#define S3C_BASE			0xE6784000

#define CCI_400_MAXOT_1			0xF0091110
#define CCI_400_MAXOT_2			0xF0092110

/* MXI */
#define	MXI_BASE			0xFE960000

/* PRR */
#define RCAR_PRR			0xFF000044
#define PRR_REGSIZE			4
#define PRR_PRODUCT_SHIFT		8
#define PRR_PRODUCT_MASK		0x7F
#define PRR_PRODUCT_H2			0x45
#define PRR_PRODUCT_M2W			0x47
#define PRR_PRODUCT_V2H			0x4A
#define PRR_PRODUCT_M2N			0x4B
#define PRR_PRODUCT_E2			0x4C
#define R_CARM2_ES10			0x00004700
#define R_CARM2_ES20			0x00004710

/* SYSC */
#define SYSCSR				0x00
#define SYSCISR				0x04
#define SYSCISCR			0x08
#define SYSCIER				0x0C
#define SYSCIMR				0x10
#define PWRSR2				0xC0
#define PWROFFCR2			0xC4
#define PWROFFSR2			0xC8
#define PWRONCR2			0xCC
#define PWRONSR2			0xD0
#define PWRER2				0xD4

/* SYS AXI */
#define SYS_AXI_SYX64TO128_BASE		0xFF800300
#define SYS_AXI_AVB_BASE		0xFF800340
#define SYS_AXI_G2D_BASE		0xFF800540
#define SYS_AXI_IMP0_BASE		0xFF800580
#define SYS_AXI_IMP1_BASE		0xFF8005C0
#define SYS_AXI_IMUX0_BASE		0xFF800600
#define SYS_AXI_IMUX1_BASE		0xFF800640
#define SYS_AXI_IMUX2_BASE		0xFF800680
#define SYS_AXI_LBS_BASE		0xFF8006C0
#define SYS_AXI_MMUDS_BASE		0xFF800700
#define SYS_AXI_MMUM_BASE		0xFF800740
#define SYS_AXI_MMUR_BASE		0xFF800780
#define SYS_AXI_MMUS0_BASE		0xFF8007C0
#define SYS_AXI_MMUS1_BASE		0xFF800800
#define SYS_AXI_MTSB0_BASE		0xFF800880
#define SYS_AXI_MTSB1_BASE		0xFF8008C0
#define SYS_AXI_PCI_BASE		0xFF800900
#define SYS_AXI_RTX_BASE		0xFF800940
#define SYS_AXI_SDS0_BASE		0xFF800A80
#define SYS_AXI_SDS1_BASE		0xFF800AC0
#define SYS_AXI_USB20_BASE		0xFF800C00
#define SYS_AXI_USB21_BASE		0xFF800C40
#define SYS_AXI_USB22_BASE		0xFF800C80
#define SYS_AXI_USB30_BASE		0xFF800CC0
#define SYS_AXI_AX2M_BASE		0xFF800380
#define SYS_AXI_CC50_BASE		0xFF8003C0
#define SYS_AXI_CCI_BASE		0xFF800440
#define SYS_AXI_CS_BASE			0xFF800480
#define SYS_AXI_DDM_BASE		0xFF8004C0
#define SYS_AXI_ETH_BASE		0xFF800500
#define SYS_AXI_MPXM_BASE		0xFF800840
#define SYS_AXI_SAT0_BASE		0xFF800980
#define SYS_AXI_SAT1_BASE		0xFF8009C0
#define SYS_AXI_SDM0_BASE		0xFF800A00
#define SYS_AXI_SDM1_BASE		0xFF800A40
#define SYS_AXI_TRAB_BASE		0xFF800B00
#define SYS_AXI_UDM0_BASE		0xFF800B80
#define SYS_AXI_UDM1_BASE		0xFF800BC0

/* RT AXI */
#define RT_AXI_SHX_BASE			0xFF810100
#define RT_AXI_DBG_BASE			0xFF810140 /* R8A7791 only */
#define RT_AXI_RDM_BASE			0xFF810180 /* R8A7791 only */
#define RT_AXI_RDS_BASE			0xFF8101C0
#define RT_AXI_RTX64TO128_BASE		0xFF810200
#define RT_AXI_STPRO_BASE		0xFF810240
#define RT_AXI_SY2RT_BASE		0xFF810280 /* R8A7791 only */

/* MP AXI */
#define MP_AXI_ADSP_BASE		0xFF820100
#define MP_AXI_ASDS0_BASE		0xFF8201C0
#define MP_AXI_ASDS1_BASE		0xFF820200
#define MP_AXI_MLP_BASE			0xFF820240
#define MP_AXI_MMUMP_BASE		0xFF820280
#define MP_AXI_SPU_BASE			0xFF8202C0
#define MP_AXI_SPUC_BASE		0xFF820300

#define SYS_AXI256_AXI128TO256_BASE	0xFF860100
#define SYS_AXI256_SYX_BASE		0xFF860140
#define SYS_AXI256_MPX_BASE		0xFF860180
#define SYS_AXI256_MXI_BASE		0xFF8601C0

/* CCI AXI */
#define CCI_AXI_MMUS0_BASE		0xFF880100
#define CCI_AXI_SYX2_BASE		0xFF880140
#define CCI_AXI_MMUR_BASE		0xFF880180
#define CCI_AXI_MMUDS_BASE		0xFF8801C0
#define CCI_AXI_MMUM_BASE		0xFF880200
#define CCI_AXI_MXI_BASE		0xFF880240
#define CCI_AXI_MMUS1_BASE		0xFF880280
#define CCI_AXI_MMUMP_BASE		0xFF8802C0

/* MEDIA AXI */
#define MEDIA_AXI_MXR_BASE		0xFE960080 /* R8A7791 only */
#define MEDIA_AXI_MXW_BASE		0xFE9600C0 /* R8A7791 only */
#define MEDIA_AXI_JPR_BASE		0xFE964100
#define MEDIA_AXI_JPW_BASE		0xFE966100
#define MEDIA_AXI_GCU0R_BASE		0xFE964140
#define MEDIA_AXI_GCU0W_BASE		0xFE966140
#define MEDIA_AXI_GCU1R_BASE		0xFE964180
#define MEDIA_AXI_GCU1W_BASE		0xFE966180
#define MEDIA_AXI_TDMR_BASE		0xFE964500
#define MEDIA_AXI_TDMW_BASE		0xFE966500
#define MEDIA_AXI_VSP0CR_BASE		0xFE964540
#define MEDIA_AXI_VSP0CW_BASE		0xFE966540
#define MEDIA_AXI_VSP1CR_BASE		0xFE964580
#define MEDIA_AXI_VSP1CW_BASE		0xFE966580
#define MEDIA_AXI_VSPDU0CR_BASE		0xFE9645C0
#define MEDIA_AXI_VSPDU0CW_BASE		0xFE9665C0
#define MEDIA_AXI_VSPDU1CR_BASE		0xFE964600
#define MEDIA_AXI_VSPDU1CW_BASE		0xFE966600
#define MEDIA_AXI_VIN0W_BASE		0xFE966900
#define MEDIA_AXI_VSP0R_BASE		0xFE964D00
#define MEDIA_AXI_VSP0W_BASE		0xFE966D00
#define MEDIA_AXI_FDP0R_BASE		0xFE964D40
#define MEDIA_AXI_FDP0W_BASE		0xFE966D40
#define MEDIA_AXI_IMSR_BASE		0xFE964D80
#define MEDIA_AXI_IMSW_BASE		0xFE966D80
#define MEDIA_AXI_VSP1R_BASE		0xFE965100
#define MEDIA_AXI_VSP1W_BASE		0xFE967100
#define MEDIA_AXI_FDP1R_BASE		0xFE965140
#define MEDIA_AXI_FDP1W_BASE		0xFE967140
#define MEDIA_AXI_IMRR_BASE		0xFE965180
#define MEDIA_AXI_IMRW_BASE		0xFE967180
#define MEDIA_AXI_FDP2R_BASE		0xFE9651C0
#define MEDIA_AXI_FDP2W_BASE		0xFE966DC0
#define MEDIA_AXI_VSPD0R_BASE		0xFE965500
#define MEDIA_AXI_VSPD0W_BASE		0xFE967500
#define MEDIA_AXI_VSPD1R_BASE		0xFE965540
#define MEDIA_AXI_VSPD1W_BASE		0xFE967540
#define MEDIA_AXI_DU0R_BASE		0xFE965580
#define MEDIA_AXI_DU0W_BASE		0xFE967580
#define MEDIA_AXI_DU1R_BASE		0xFE9655C0
#define MEDIA_AXI_DU1W_BASE		0xFE9675C0
#define MEDIA_AXI_VCP0CR_BASE		0xFE965900
#define MEDIA_AXI_VCP0CW_BASE		0xFE967900
#define MEDIA_AXI_VCP0VR_BASE		0xFE965940
#define MEDIA_AXI_VCP0VW_BASE		0xFE967940
#define MEDIA_AXI_VPC0R_BASE		0xFE965980
#define MEDIA_AXI_VCP1CR_BASE		0xFE965D00
#define MEDIA_AXI_VCP1CW_BASE		0xFE967D00
#define MEDIA_AXI_VCP1VR_BASE		0xFE965D40
#define MEDIA_AXI_VCP1VW_BASE		0xFE967D40
#define MEDIA_AXI_VPC1R_BASE		0xFE965D80

#define SYS_AXI_AVBDMSCR		0xFF802000
#define SYS_AXI_SYX2DMSCR		0xFF802004
#define SYS_AXI_CC50DMSCR		0xFF802008
#define SYS_AXI_CC51DMSCR		0xFF80200C
#define SYS_AXI_CCIDMSCR		0xFF802010
#define SYS_AXI_CSDMSCR			0xFF802014
#define SYS_AXI_DDMDMSCR		0xFF802018
#define SYS_AXI_ETHDMSCR		0xFF80201C
#define SYS_AXI_G2DDMSCR		0xFF802020
#define SYS_AXI_IMP0DMSCR		0xFF802024
#define SYS_AXI_IMP1DMSCR		0xFF802028
#define SYS_AXI_LBSDMSCR		0xFF80202C
#define SYS_AXI_MMUDSDMSCR		0xFF802030
#define SYS_AXI_MMUMXDMSCR		0xFF802034
#define SYS_AXI_MMURDDMSCR		0xFF802038
#define SYS_AXI_MMUS0DMSCR		0xFF80203C
#define SYS_AXI_MMUS1DMSCR		0xFF802040
#define SYS_AXI_MPXDMSCR		0xFF802044
#define SYS_AXI_MTSB0DMSCR		0xFF802048
#define SYS_AXI_MTSB1DMSCR		0xFF80204C
#define SYS_AXI_PCIDMSCR		0xFF802050
#define SYS_AXI_RTXDMSCR		0xFF802054
#define SYS_AXI_SAT0DMSCR		0xFF802058
#define SYS_AXI_SAT1DMSCR		0xFF80205C
#define SYS_AXI_SDM0DMSCR		0xFF802060
#define SYS_AXI_SDM1DMSCR		0xFF802064
#define SYS_AXI_SDS0DMSCR		0xFF802068
#define SYS_AXI_SDS1DMSCR		0xFF80206C
#define SYS_AXI_ETRABDMSCR		0xFF802070
#define SYS_AXI_ETRKFDMSCR		0xFF802074
#define SYS_AXI_UDM0DMSCR		0xFF802078
#define SYS_AXI_UDM1DMSCR		0xFF80207C
#define SYS_AXI_USB20DMSCR		0xFF802080
#define SYS_AXI_USB21DMSCR		0xFF802084
#define SYS_AXI_USB22DMSCR		0xFF802088
#define SYS_AXI_USB30DMSCR		0xFF80208C
#define SYS_AXI_X128TO64SLVDMSCR	0xFF802100
#define SYS_AXI_X64TO128SLVDMSCR	0xFF802104
#define SYS_AXI_AVBSLVDMSCR		0xFF802108
#define SYS_AXI_SYX2SLVDMSCR		0xFF80210C
#define SYS_AXI_ETHSLVDMSCR		0xFF802110
#define SYS_AXI_GICSLVDMSCR		0xFF802114
#define SYS_AXI_IMPSLVDMSCR		0xFF802118
#define SYS_AXI_IMX0SLVDMSCR		0xFF80211C
#define SYS_AXI_IMX1SLVDMSCR		0xFF802120
#define SYS_AXI_IMX2SLVDMSCR		0xFF802124
#define SYS_AXI_LBSSLVDMSCR		0xFF802128
#define SYS_AXI_MMC0SLVDMSCR		0xFF80212C
#define SYS_AXI_MMC1SLVDMSCR		0xFF802130
#define SYS_AXI_MPXSLVDMSCR		0xFF802134
#define SYS_AXI_MTSB0SLVDMSCR		0xFF802138
#define SYS_AXI_MTSB1SLVDMSCR		0xFF80213C
#define SYS_AXI_MXTSLVDMSCR		0xFF802140
#define SYS_AXI_PCISLVDMSCR		0xFF802144
#define SYS_AXI_SYAPBSLVDMSCR		0xFF802148
#define SYS_AXI_QSAPBSLVDMSCR		0xFF80214C
#define SYS_AXI_RTXSLVDMSCR		0xFF802150
#define SYS_AXI_SAT0SLVDMSCR		0xFF802168
#define SYS_AXI_SAT1SLVDMSCR		0xFF80216C
#define SYS_AXI_SDAP0SLVDMSCR		0xFF802170
#define SYS_AXI_SDAP1SLVDMSCR		0xFF802174
#define SYS_AXI_SDAP2SLVDMSCR		0xFF802178
#define SYS_AXI_SDAP3SLVDMSCR		0xFF80217C
#define SYS_AXI_SGXSLVDMSCR		0xFF802180
#define SYS_AXI_STBSLVDMSCR		0xFF802188
#define SYS_AXI_STMSLVDMSCR		0xFF80218C
#define SYS_AXI_TSPL0SLVDMSCR		0xFF802194
#define SYS_AXI_TSPL1SLVDMSCR		0xFF802198
#define SYS_AXI_TSPL2SLVDMSCR		0xFF80219C
#define SYS_AXI_USB20SLVDMSCR		0xFF8021A0
#define SYS_AXI_USB21SLVDMSCR		0xFF8021A4
#define SYS_AXI_USB22SLVDMSCR		0xFF8021A8
#define SYS_AXI_USB30SLVDMSCR		0xFF8021AC

#define RT_AXI_CBMDMSCR			0xFF812000
#define RT_AXI_DBDMSCR			0xFF812004
#define RT_AXI_RDMDMSCR			0xFF812008
#define RT_AXI_RDSDMSCR			0xFF81200C
#define RT_AXI_STRDMSCR			0xFF812010
#define RT_AXI_SY2RTDMSCR		0xFF812014
#define RT_AXI_CBSSLVDMSCR		0xFF812100
#define RT_AXI_DBSSLVDMSCR		0xFF812104
#define RT_AXI_RTAP1SLVDMSCR		0xFF812108
#define RT_AXI_RTAP2SLVDMSCR		0xFF81210C
#define RT_AXI_RTAP3SLVDMSCR		0xFF812110
#define RT_AXI_RT2SYSLVDMSCR		0xFF812114
#define RT_AXI_A128TO64SLVDMSCR		0xFF812118
#define RT_AXI_A64TO128SLVDMSCR		0xFF81211C
#define RT_AXI_A64TO128CSLVDMSCR	0xFF812120
#define RT_AXI_UTLBRSLVDMSCR		0xFF812128

#define MP_AXI_ADSPDMSCR		0xFF822000
#define MP_AXI_ASDM0DMSCR		0xFF822004
#define MP_AXI_ASDM1DMSCR		0xFF822008
#define MP_AXI_ASDS0DMSCR		0xFF82200C
#define MP_AXI_ASDS1DMSCR		0xFF822010
#define MP_AXI_MLPDMSCR			0xFF822014
#define MP_AXI_MMUMPDMSCR		0xFF822018
#define MP_AXI_SPUDMSCR			0xFF82201C
#define MP_AXI_SPUCDMSCR		0xFF822020
#define MP_AXI_SY2MPDMSCR		0xFF822024
#define MP_AXI_ADSPSLVDMSCR		0xFF822100
#define MP_AXI_MLMSLVDMSCR		0xFF822104
#define MP_AXI_MPAP4SLVDMSCR		0xFF822108
#define MP_AXI_MPAP5SLVDMSCR		0xFF82210C
#define MP_AXI_MPAP6SLVDMSCR		0xFF822110
#define MP_AXI_MPAP7SLVDMSCR		0xFF822114
#define MP_AXI_MP2SYSLVDMSCR		0xFF822118
#define MP_AXI_MP2SY2SLVDMSCR		0xFF82211C
#define MP_AXI_MPXAPSLVDMSCR		0xFF822124
#define MP_AXI_SPUSLVDMSCR		0xFF822128
#define MP_AXI_UTLBMPSLVDMSCR		0xFF82212C

#define ADM_AXI_ASDM0DMSCR		0xFF842000
#define ADM_AXI_ASDM1DMSCR		0xFF842004
#define ADM_AXI_MPAP1SLVDMSCR		0xFF842104
#define ADM_AXI_MPAP2SLVDMSCR		0xFF842108
#define ADM_AXI_MPAP3SLVDMSCR		0xFF84210C

#define DM_AXI_RDMDMSCR			0xFF852000
#define DM_AXI_SDM0DMSCR		0xFF852004
#define DM_AXI_SDM1DMSCR		0xFF852008
#define DM_AXI_MMAP0SLVDMSCR		0xFF852100
#define DM_AXI_MMAP1SLVDMSCR		0xFF852104
#define DM_AXI_QSPAPSLVDMSCR		0xFF852108
#define DM_AXI_RAP4SLVDMSCR		0xFF85210C
#define DM_AXI_RAP5SLVDMSCR		0xFF852110
#define DM_AXI_SAP4SLVDMSCR		0xFF852114
#define DM_AXI_SAP5SLVDMSCR		0xFF852118
#define DM_AXI_SAP6SLVDMSCR		0xFF85211C
#define DM_AXI_SAP65SLVDMSCR		0xFF852120
#define DM_AXI_SDAP0SLVDMSCR		0xFF852124
#define DM_AXI_SDAP1SLVDMSCR		0xFF852128
#define DM_AXI_SDAP2SLVDMSCR		0xFF85212C
#define DM_AXI_SDAP3SLVDMSCR		0xFF852130

#define SYS_AXI256_SYXDMSCR		0xFF862000
#define SYS_AXI256_MPXDMSCR		0xFF862004
#define SYS_AXI256_MXIDMSCR		0xFF862008
#define SYS_AXI256_X128TO256SLVDMSCR	0xFF862100
#define SYS_AXI256_X256TO128SLVDMSCR	0xFF862104
#define SYS_AXI256_SYXSLVDMSCR		0xFF862108
#define SYS_AXI256_CCXSLVDMSCR		0xFF86210C
#define SYS_AXI256_S3CSLVDMSCR		0xFF862110

#define MXT_SYXDMSCR			0xFF872000
#define MXT_CMM0SLVDMSCR		0xFF872100
#define MXT_CMM1SLVDMSCR		0xFF872104
#define MXT_CMM2SLVDMSCR		0xFF872108
#define MXT_FDPSLVDMSCR			0xFF87210C
#define MXT_IMRSLVDMSCR			0xFF872110
#define MXT_VINSLVDMSCR			0xFF872114
#define MXT_VPC0SLVDMSCR		0xFF872118
#define MXT_VPC1SLVDMSCR		0xFF87211C
#define MXT_VSP0SLVDMSCR		0xFF872120
#define MXT_VSP1SLVDMSCR		0xFF872124
#define MXT_VSPD0SLVDMSCR		0xFF872128
#define MXT_VSPD1SLVDMSCR		0xFF87212C
#define MXT_MAP1SLVDMSCR		0xFF872130
#define MXT_MAP2SLVDMSCR		0xFF872134

#define CCI_AXI_MMUS0DMSCR		0xFF882000
#define CCI_AXI_SYX2DMSCR		0xFF882004
#define CCI_AXI_MMURDMSCR		0xFF882008
#define CCI_AXI_MMUDSDMSCR		0xFF88200C
#define CCI_AXI_MMUMDMSCR		0xFF882010
#define CCI_AXI_MXIDMSCR		0xFF882014
#define CCI_AXI_MMUS1DMSCR		0xFF882018
#define CCI_AXI_MMUMPDMSCR		0xFF88201C
#define CCI_AXI_DVMDMSCR		0xFF882020
#define CCI_AXI_CCISLVDMSCR		0xFF882100

#define CCI_AXI_IPMMUIDVMCR		0xFF880400
#define CCI_AXI_IPMMURDVMCR		0xFF880404
#define CCI_AXI_IPMMUS0DVMCR		0xFF880408
#define CCI_AXI_IPMMUS1DVMCR		0xFF88040C
#define CCI_AXI_IPMMUMPDVMCR		0xFF880410
#define CCI_AXI_IPMMUDSDVMCR		0xFF880414
#define CCI_AXI_AX2ADDRMASK		0xFF88041C

#define RWTCSRA0			(RWDT_BASE + 0x04)
#define RWTCSRB0			(RWDT_BASE + 0x08)
#define SWTCSRA0			(SWDT_BASE + 0x04)

/* CPG Symbols */
#define EXTAL  	 	20000000 			/* External crystal clock */
#define A7_CLK		780000000UL 		/* Fixed clock for A7 core */
#define FRQCRA				(CPG_BASE + 0x0000)
#define FRQCRB				(CPG_BASE + 0x0004)
#define FRQCRC				(CPG_BASE + 0x00E0)
#define FRQCRD				(CPG_BASE + 0x00E4)
#define VCLKCR1				(CPG_BASE + 0x0008)
#define VCLKCR2				(CPG_BASE + 0x000C)
#define VCLKCR3				(CPG_BASE + 0x001C)
#define VCLKCR4				(CPG_BASE + 0x0014)
#define ZBCKCR				(CPG_BASE + 0x0010)
#define SDCKCR				(CPG_BASE + 0x0074)
#define SD2CKCR				(CPG_BASE + 0x0078)
#define SD3CKCR				(CPG_BASE + 0x026C)
#define RCANCKCR            (CPG_BASE + 0x0270)
#define MMC0CKCR			(CPG_BASE + 0x0240)
#define MMC1CKCR			(CPG_BASE + 0x0244)
#define FSIACKCR			(CPG_BASE + 0x0018)
#define FSIBCKCR			(CPG_BASE + 0x0090)
#define MPCKCR				(CPG_BASE + 0x0080)
#define SPUACKCR			(CPG_BASE + 0x0084)
#define HSICKCR				(CPG_BASE + 0x008C)
#define DSITCKCR			(CPG_BASE + 0x0060)
#define DSI0PCKCR			(CPG_BASE + 0x0064)
#define DSI0PHYCR			(CPG_BASE + 0x006C)
#define MPMODE				(CPG_BASE + 0x00CC)
#define PLLECR				(CPG_BASE + 0x00D0)
#define PLL0CR				(CPG_BASE + 0x00D8)
#define PLL1CR				(CPG_BASE + 0x0028)
#define PLL2CR				(CPG_BASE + 0x002C)
#define PLL3CR				(CPG_BASE + 0x00DC)
#define PLL0STPCR			(CPG_BASE + 0x00F0)
#define PLL1STPCR			(CPG_BASE + 0x00C8)
#define PLL2STPCR			(CPG_BASE + 0x00F8)
#define PLL3STPCR			(CPG_BASE + 0x00FC)
#define MSTPSR0				(CPG_BASE + 0x0030)
#define MSTPSR1				(CPG_BASE + 0x0038)
#define MSTPSR2				(CPG_BASE + 0x0040)
#define MSTPSR3				(CPG_BASE + 0x0048)
#define MSTPSR4				(CPG_BASE + 0x004C)
#define MSTPSR5				(CPG_BASE + 0x003C)
#define MSTPSR6				(CPG_BASE + 0x01C0)
#define MSTPSR7				(CPG_BASE + 0x01C4)
#define MSTPSR8				(CPG_BASE + 0x09A0)
#define MSTPSR9				(CPG_BASE + 0x09A4)
#define MSTPSR10			(CPG_BASE + 0x09A8)
#define MSTPSR11			(CPG_BASE + 0x09AC)

#define RMSTPCR0			(CPG_BASE + 0x0110)
#define RMSTPCR1			(CPG_BASE + 0x0114)
#define RMSTPCR2			(CPG_BASE + 0x0118)
#define RMSTPCR3			(CPG_BASE + 0x011C)
#define RMSTPCR4			(CPG_BASE + 0x0120)
#define RMSTPCR5			(CPG_BASE + 0x0124)
#define RMSTPCR6			(CPG_BASE + 0x0128)
#define RMSTPCR7			(CPG_BASE + 0x012c)
#define RMSTPCR8			(CPG_BASE + 0x0980)
#define RMSTPCR9			(CPG_BASE + 0x0984)
#define RMSTPCR10			(CPG_BASE + 0x0988)
#define RMSTPCR11			(CPG_BASE + 0x098c)

#define GPUCKCR				(CPG_BASE + 0x0234)

#define SMSTPCR0			(CPG_BASE + 0x0130)
#define SMSTPCR1			(CPG_BASE + 0x0134)
#define SMSTPCR2			(CPG_BASE + 0x0138)
#define SMSTPCR3			(CPG_BASE + 0x013C)
#define SMSTPCR4			(CPG_BASE + 0x0140)
#define SMSTPCR5			(CPG_BASE + 0x0144)
#define SMSTPCR6			(CPG_BASE + 0x0148)
#define SMSTPCR7			(CPG_BASE + 0x014C)
#define SMSTPCR8			(CPG_BASE + 0x0990)
#define SMSTPCR9			(CPG_BASE + 0x0994)
#define SMSTPCR10			(CPG_BASE + 0x0998)
#define SMSTPCR11			(CPG_BASE + 0x099C)

#define SRCR0				(CPG_BASE + 0x00A0)
#define SRCR1				(CPG_BASE + 0x00A8)
#define SRCR2				(CPG_BASE + 0x00B0)
#define SRCR3				(CPG_BASE + 0x00B8)
#define SRCR4				(CPG_BASE + 0x00BC)
#define SRCR5				(CPG_BASE + 0x00C4)
#define SRCR6				(CPG_BASE + 0x01C8)
#define SRCR7				(CPG_BASE + 0x01CC)
#define SRCR8				(CPG_BASE + 0x0920)
#define SRCR9				(CPG_BASE + 0x0924)
#define SRCR10				(CPG_BASE + 0x0928)
#define SRCR11				(CPG_BASE + 0x092C)

#define CKSCR				(CPG_BASE + 0x00C0)
#define VREFCR				(CPG_BASE + 0x00EC)
#define PCLKCR				(CPG_BASE + 0x1020)

#define CPG_SMSTPCR0			(SMSTPCR0)
#define CPG_SMSTPCR1			(SMSTPCR1)
#define CPG_SMSTPCR2			(SMSTPCR2)
#define CPG_SMSTPCR3			(SMSTPCR3)
#define CPG_SMSTPCR4			(SMSTPCR4)
#define CPG_SMSTPCR5			(SMSTPCR5)
#define CPG_SMSTPCR6			(SMSTPCR6)
#define CPG_SMSTPCR7			(SMSTPCR7)
#define CPG_SMSTPCR8			(SMSTPCR8)
#define CPG_SMSTPCR9			(SMSTPCR9)
#define CPG_SMSTPCR10			(SMSTPCR10)
#define CPG_SMSTPCR11			(SMSTPCR11)

#define CPG_SRCR0			(SRCR0)
#define CPG_SRCR1			(SRCR1)
#define CPG_SRCR2			(SRCR2)
#define CPG_SRCR3			(SRCR3)
#define CPG_SRCR4			(SRCR4)
#define CPG_SRCR5			(SRCR5)
#define CPG_SRCR6			(SRCR6)
#define CPG_SRCR7			(SRCR7)
#define CPG_SRCR8			(SRCR8)
#define CPG_SRCR9			(SRCR9)
#define CPG_SRCR10			(SRCR10)
#define CPG_SRCR11			(SRCR11)

#define SRSTCLR0			(CPG_BASE + 0x0940)
#define SRSTCLR1			(CPG_BASE + 0x0944)
#define SRSTCLR2			(CPG_BASE + 0x0948)
#define SRSTCLR3			(CPG_BASE + 0x094c)
#define SRSTCLR4			(CPG_BASE + 0x0950)
#define SRSTCLR5			(CPG_BASE + 0x0954)
#define SRSTCLR6			(CPG_BASE + 0x0958)
#define SRSTCLR7			(CPG_BASE + 0x095c)
#define SRSTCLR8			(CPG_BASE + 0x0960)
#define SRSTCLR9			(CPG_BASE + 0x0964)
#define SRSTCLR10			(CPG_BASE + 0x0968)
#define SRSTCLR11			(CPG_BASE + 0x096c)

/* RST Registers */
#define RBAR				(CPG_BASE + 0x10000)
#define RBAR2				(CPG_BASE + 0x10004)
#define SBAR				(CPG_BASE + 0x10010)
#define SBAR2				(CPG_BASE + 0x10014)
#define CA15BAR				(CPG_BASE + 0x10020)
#define CA15BAR2			(CPG_BASE + 0x10024)
#define CA7BAR				(CPG_BASE + 0x10030)
#define CA7BAR2				(CPG_BASE + 0x10034)
#define CA15RESCNT			(CPG_BASE + 0x10040)
#define CA7RESCNT			(CPG_BASE + 0x10044)

/* PCCU Registers */
#define CA15WUPCR			(CPG_BASE + 0x4010)

//tmu
#define RCAR_MMR_TMU_TSTR0			0xE61E0004

#define RCAR_MMR_TMU_TCOR0			0xE61E0008
#define RCAR_MMR_TMU_TCNT0			0xE61E000c
#define RCAR_MMR_TMU_TCR0			0xE61E0010

/*INTCA INTERRUPT NUMBER */
#define INTCA_CMT1_CMT10		(120+32)
#define INTCA_CMT1_CMT11		(121+32)
#define INTCA_CMT1_CMT12		(122+32)
#define INTCA_CMT1_CMT13		(123+32)
#define INTCA_CMT1_CMT14		(124+32)
#define INTCA_CMT1_CMT15		(125+32)
#define INTCA_CMT1_CMT16		(126+32)
#define INTCA_CMT1_CMT17		(127+32)
#define INTCA_SCIFA0			(144+32)
#define INTCA_SCIFA1			(145+32)
//#define Reserved			(146+32)
//#define Reserved			(147+32)
#define INTCA_SCIFB0			(148+32)
#define INTCA_SCIFB1			(149+32)
#define INTCA_SCIFB2			(150+32)
#define INTCA_SCIFB3			(151+32)
#define INTCA_SCIF0			(152+32)
#define INTCA_SCIF1			(153+32)

#define INTCA0_PINT1			(33+32)
#define INTCA0_INTCS			(50+32)
#define INTCSYS_IIC0			(174+32)
#define INTCSYS_IIC1			(175+32)
#define INTCSYS_IIC2			(176+32)
#define INTCSYS_IIC3			(173+32)

#define INTCSYS_I2C0			(287+32)
#define INTCSYS_I2C1			(288+32)
#define INTCSYS_I2C2			(286+32)
#define INTCSYS_I2C3			(290+32)
#define INTCSYS_I2C4			(19+32)
#define INTCSYS_I2C5			(20+32)

/* Counter Control Register */
#define CNTCTL_CNTCR			(CNTCTL_BASE + 0x0000)

/* IIC */
#define IIC0_BADR			(0xE6820000)
#define	ICDR0_ADDR			(IIC0_BADR+0x0000)
#define	ICCR0_ADDR			(IIC0_BADR+0x0004)
#define	ICSR0_ADDR			(IIC0_BADR+0x0008)
#define	ICIC0_ADDR			(IIC0_BADR+0x000C)
#define	ICCL0_ADDR			(IIC0_BADR+0x0010)
#define	ICCH0_ADDR			(IIC0_BADR+0x0014)
#define	ICTC0_ADDR			(IIC0_BADR+0x0028)

#define IIC1_BADR			(0xE6822000)
#define	ICDR1_ADDR			(IIC1_BADR+0x0000)
#define	ICCR1_ADDR			(IIC1_BADR+0x0004)
#define	ICSR1_ADDR			(IIC1_BADR+0x0008)
#define	ICIC1_ADDR			(IIC1_BADR+0x000C)
#define	ICCL1_ADDR			(IIC1_BADR+0x0010)
#define	ICCH1_ADDR			(IIC1_BADR+0x0014)
#define	ICTC1_ADDR			(IIC1_BADR+0x0028)

#define IIC2_BADR			(0xE6824000)
#define	ICDR2_ADDR			(IIC2_BADR+0x0000)
#define	ICCR2_ADDR			(IIC2_BADR+0x0004)
#define	ICSR2_ADDR			(IIC2_BADR+0x0008)
#define	ICIC2_ADDR			(IIC2_BADR+0x000C)
#define	ICCL2_ADDR			(IIC2_BADR+0x0010)
#define	ICCH2_ADDR			(IIC2_BADR+0x0014)
#define	ICTC2_ADDR			(IIC2_BADR+0x0028)

#define PINTADR				0xE60580C0
#define PINTCDR				0xE60580c4

/* I2C */
#define I2C0_REG_BASE			0xE6508000
#define I2C1_REG_BASE			0xE6518000
#define I2C2_REG_BASE			0xE6530000
#define I2C3_REG_BASE			0xE6540000
#define I2C4_REG_BASE			0xE6520000
#define I2C5_REG_BASE			0xE6528000

#define I2C_REG_LEN			0x40

#define I2C_ICSCR			0x00
#define I2C_ICMCR			0x04
#define I2C_ICSSR			0x08
#define I2C_ICMSR			0x0c
#define I2C_ICSIER			0x10
#define I2C_ICMIER			0x14
#define I2C_ICCCR			0x18
#define I2C_ICSAR			0x1c
#define I2C_ICMAR			0x20
#define I2C_ICRXD			0x24
#define I2C_ICTXD			0x24
#define I2C_ICCCR2			0x28
#define I2C_ICMPR			0x2C
#define I2C_ICHPR			0x30
#define I2C_ICLPR			0x34

#define I2C_ICTXD_FULL			16
#define I2C_ICSCR_SDBS			0x0008
#define I2C_ICSCR_SIE			0x0004
#define I2C_ICSCR_GCAE			0x0002
#define I2C_ICSCR_FNA			0x0001

#define I2C_ICSSR_GCAR			0x0040
#define I2C_ICSSR_STM			0x0020
#define I2C_ICSSR_SSR			0x0010
#define I2C_ICSSR_SDE			0x0008
#define I2C_ICSSR_SDT			0x0004
#define I2C_ICSSR_SDR			0x0002
#define I2C_ICSSR_SAR			0x0001

#define I2C_ICSIER_SSRE			0x0010
#define I2C_ICSIER_SDEE			0x0008
#define I2C_ICSIER_SDTE			0x0004
#define I2C_ICSIER_SDRE			0x0002
#define I2C_ICSIER_SARE			0x0001

#define I2C_ICMCR_MDBS			0x0080
#define I2C_ICMCR_FSCL			0x0040
#define I2C_ICMCR_FSDA			0x0020
#define I2C_ICMCR_OBPC			0x0010
#define I2C_ICMCR_MIE			0x0008
#define I2C_ICMCR_TSBE			0x0004
#define I2C_ICMCR_FSB			0x0002
#define I2C_ICMCR_ESG			0x0001

#define I2C_ICMSR_MNR			0x0040
#define I2C_ICMSR_MAL			0x0020
#define I2C_ICMSR_MST			0x0010
#define I2C_ICMSR_MDE			0x0008
#define I2C_ICMSR_MDT			0x0004
#define I2C_ICMSR_MDR			0x0002
#define I2C_ICMSR_MAT			0x0001

#define I2C_ICMIER_MNRE			0x0040
#define I2C_ICMIER_MALE			0x0020
#define I2C_ICMIER_MSTE			0x0010
#define I2C_ICMIER_MDEE			0x0008
#define I2C_ICMIER_MDTE			0x0004
#define I2C_ICMIER_MDRE			0x0002
#define I2C_ICMIER_MATE			0x0001

#define I2C_ICMAR_STM1			0x0001
#define I2C_ICCCR_SCGD(x)		(((x) << 2) & 0xfc)
#define I2C_ICCCR_CDF(x)		((x) & 0x3)
#define I2C_ICCCR2_CDFD			0x0004
#define I2C_ICCCR2_HLSE			0x0002
#define I2C_ICCCR2_SME			0x0001

/*Watchdog Timer */
#define RWTCNT0				0xE6020000
//#define RWTCSRA0			0xE6020004
#define WDOG_CNT_OFF			(RWTCNT0-RWTCNT0)
#define WDOG_CSRA_OFF			(RWTCSRA0-RWTCNT0)
#define WDOG_CSRB_OFF			(RWTCSRB0-RWTCNT0)
#define RWT_TME				(1<<7)
#define RWT_WOVF			(1<<4)

#define IRQC0_BASE			0xe61c0000
#define IRQC0_INTREQ_STS0		(IRQC0_BASE + 0x000)	/* R */
#define IRQC0_INTEN_STS0		(IRQC0_BASE + 0x004)	/* R/WC1 */
#define IRQC0_INTEN_SET0		(IRQC0_BASE + 0x008)	/* W */
#define IRQC0_WAKREQ_STS0		(IRQC0_BASE + 0x080)	/* R */
#define IRQC0_WAKEN_STS0		(IRQC0_BASE + 0x084)	/* R/WC1 */
#define IRQC0_WAKEN_SET0		(IRQC0_BASE + 0x088)	/* W */
#define IRQC0_DETECT_STATUS		(IRQC0_BASE + 0x100)	/* R/WC1 */
#define IRQC0_CONFIG_00			(IRQC0_BASE + 0x180)	/* R/W */

#define IRQC1_BASE			0xe61c0200
#define IRQC1_INTREQ_STS0		(IRQC1_BASE + 0x000)	/* R */
#define IRQC1_INTEN_STS0		(IRQC1_BASE + 0x004)	/* R/WC1 */
#define IRQC1_INTEN_SET0		(IRQC1_BASE + 0x008)	/* W */
#define IRQC1_WAKREQ_STS0		(IRQC1_BASE + 0x080)	/* R */
#define IRQC1_WAKEN_STS0		(IRQC1_BASE + 0x084)	/* R/WC1 */
#define IRQC1_WAKEN_SET0		(IRQC1_BASE + 0x088)	/* W */
#define IRQC1_DETECT_STATUS		(IRQC1_BASE + 0x100)	/* R/WC1 */
#define IRQC1_MONITOR_STATUS		(IRQC1_BASE + 0x128)
#define IRQC1_CONFIG_00			(IRQC1_BASE + 0x180)	/* R/W */

/*
 * -----------------------------------------------------------------------
 * Interrupt Distributor CPU interface
 * Register offsets from GIC_BASE
 * -----------------------------------------------------------------------
 */
#define GIC400				0xF1000000
#define GIC_CPU_BASE			0x2000
#define GIC_DIST_BASE			0x1000

/*
 * PFC
 */
#define PFC_PMMR			(PFC_BASE + 0x0000)
#define PFC_GPSR0			(PFC_BASE + 0x0004)
#define PFC_GPSR1			(PFC_BASE + 0x0008)
#define PFC_GPSR2			(PFC_BASE + 0x000C)
#define PFC_GPSR3			(PFC_BASE + 0x0010)
#define PFC_GPSR4			(PFC_BASE + 0x0014)
#define PFC_GPSR5			(PFC_BASE + 0x0018)
#define PFC_GPSR6			(PFC_BASE + 0x001C)
#define PFC_GPSR7			(PFC_BASE + 0x0074)

#define PFC_IPSR0			(PFC_BASE + 0x0020)
#define PFC_IPSR1			(PFC_BASE + 0x0024)
#define PFC_IPSR2			(PFC_BASE + 0x0028)
#define PFC_IPSR3			(PFC_BASE + 0x002C)
#define PFC_IPSR4			(PFC_BASE + 0x0030)
#define PFC_IPSR5			(PFC_BASE + 0x0034)
#define PFC_IPSR6			(PFC_BASE + 0x0038)
#define PFC_IPSR7			(PFC_BASE + 0x003C)
#define PFC_IPSR8			(PFC_BASE + 0x0040)
#define PFC_IPSR9			(PFC_BASE + 0x0044)
#define PFC_IPSR10			(PFC_BASE + 0x0048)
#define PFC_IPSR11			(PFC_BASE + 0x004C)
#define PFC_IPSR12			(PFC_BASE + 0x0050)
#define PFC_IPSR13			(PFC_BASE + 0x0054)
#define PFC_IPSR14			(PFC_BASE + 0x0058)
#define PFC_IPSR15			(PFC_BASE + 0x005C)
#define PFC_IPSR16			(PFC_BASE + 0x0160)

#define PFC_MOD_SEL			(PFC_BASE + 0x0090)
#define PFC_MOD_SEL2			(PFC_BASE + 0x0094)
#define PFC_MOD_SEL3			(PFC_BASE + 0x0098)
#define PFC_MOD_SEL4			(PFC_BASE + 0x009C)

#define PFC_PUPR0			(PFC_BASE + 0x0100)
#define PFC_PUPR1			(PFC_BASE + 0x0104)
#define PFC_PUPR2			(PFC_BASE + 0x0108)
#define PFC_PUPR3			(PFC_BASE + 0x010C)
#define PFC_PUPR4			(PFC_BASE + 0x0110)
#define PFC_PUPR5			(PFC_BASE + 0x0114)
#define PFC_PUPR6			(PFC_BASE + 0x0118)
#define PFC_PUPR7			(PFC_BASE + 0x011C)

#define PFC_IOCTRL0			(PFC_BASE + 0x0060)
#define PFC_IOCTRL1			(PFC_BASE + 0x0064)
#define PFC_IOCTRL4			(PFC_BASE + 0x0084)
#define PFC_IOCTRL5			(PFC_BASE + 0x0088)
#define PFC_IOCTRL6			(PFC_BASE + 0x008C)
#define PFC_IOCTRL7			(PFC_BASE + 0x0070)

#define PFC_DDR3GPEN			(PFC_BASE + 0x0240)
#define PFC_DDR3GPOE			(PFC_BASE + 0x0244)
#define PFC_DDR3GPOD			(PFC_BASE + 0x0248)
#define PFC_DDR3GPID			(PFC_BASE + 0x024C)

/* GPIO Registers */
// Register offsets
#define GPIO_IOINTSEL_OFFSET		0x0000
#define GPIO_INOUTSEL_OFFSET		0x0004
#define GPIO_OUTDT_OFFSET		0x0008
#define GPIO_INDT_OFFSET		0x000C
#define GPIO_INTDT_OFFSET		0x0010
#define GPIO_INTCLR_OFFSET		0x0014
#define GPIO_INTMSK_OFFSET		0x0018
#define GPIO_MSKCLR_OFFSET		0x001C
#define GPIO_POSNEG_OFFSET		0x0020
#define GPIO_EDGLEVEL_OFFSET		0x0024
#define GPIO_FILONOFF_OFFSET		0x0028
#define GPIO_INTMSKS_OFFSET		0x0038
#define GPIO_MSKCLRS_OFFSET		0x003C
#define GPIO_OUTDTSEL_OFFSET		0x0040
#define GPIO_OUTDTH_OFFSET		0x0044
#define GPIO_OUTDTL_OFFSET		0x0048
#define GPIO_BOTHEDGE_OFFSET		0x004C

#define GPIO0_REGBASE			(GPIO_BASE)
#define GPIO_IOINTSEL0			(GPIO0_REGBASE + GPIO_IOINTSEL_OFFSET)
#define GPIO_INOUTSEL0			(GPIO0_REGBASE + GPIO_INOUTSEL_OFFSET)
#define GPIO_OUTDT0			(GPIO0_REGBASE + GPIO_OUTDT_OFFSET)
#define GPIO_INDT0			(GPIO0_REGBASE + GPIO_INDT_OFFSET)
#define GPIO_INTDT0			(GPIO0_REGBASE + GPIO_INTDT_OFFSET)
#define GPIO_INTCLR0			(GPIO0_REGBASE + GPIO_INTCLR_OFFSET)
#define GPIO_INTMSK0			(GPIO0_REGBASE + GPIO_INTMSK_OFFSET)
#define GPIO_MSKCLR0			(GPIO0_REGBASE + GPIO_MSKCLR_OFFSET)
#define GPIO_POSNEG0			(GPIO0_REGBASE + GPIO_POSNEG_OFFSET)
#define GPIO_EDGLEVEL0			(GPIO0_REGBASE + GPIO_EDGLEVEL_OFFSET)
#define GPIO_FILONOFF0			(GPIO0_REGBASE + GPIO_FILONOFF_OFFSET)
#define GPIO_INTMSKS0			(GPIO0_REGBASE + GPIO_INTMSKS_OFFSET)
#define GPIO_MSKCLRS0			(GPIO0_REGBASE + GPIO_MSKCLRS_OFFSET)
#define GPIO_OUTDTSEL0			(GPIO0_REGBASE + GPIO_OUTDTSEL_OFFSET)
#define GPIO_OUTDTH0			(GPIO0_REGBASE + GPIO_OUTDTH_OFFSET)
#define GPIO_OUTDTL0			(GPIO0_REGBASE + GPIO_OUTDTL_OFFSET)
#define GPIO_BOTHEDGE0			(GPIO0_REGBASE + GPIO_BOTHEDGE_OFFSET)

#define GPIO1_REGBASE			(GPIO_BASE + 0x1000)
#define GPIO_IOINTSEL1			(GPIO1_REGBASE + GPIO_IOINTSEL_OFFSET)
#define GPIO_INOUTSEL1			(GPIO1_REGBASE + GPIO_INOUTSEL_OFFSET)
#define GPIO_OUTDT1			(GPIO1_REGBASE + GPIO_OUTDT_OFFSET)
#define GPIO_INDT1			(GPIO1_REGBASE + GPIO_INDT_OFFSET)
#define GPIO_INTDT1			(GPIO1_REGBASE + GPIO_INTDT_OFFSET)
#define GPIO_INTCLR1			(GPIO1_REGBASE + GPIO_INTCLR_OFFSET)
#define GPIO_INTMSK1			(GPIO1_REGBASE + GPIO_INTMSK_OFFSET)
#define GPIO_MSKCLR1			(GPIO1_REGBASE + GPIO_MSKCLR_OFFSET)
#define GPIO_POSNEG1			(GPIO1_REGBASE + GPIO_POSNEG_OFFSET)
#define GPIO_EDGLEVEL1			(GPIO1_REGBASE + GPIO_EDGLEVEL_OFFSET)
#define GPIO_FILONOFF1			(GPIO1_REGBASE + GPIO_FILONOFF_OFFSET)
#define GPIO_INTMSKS1			(GPIO1_REGBASE + GPIO_INTMSKS_OFFSET)
#define GPIO_MSKCLRS1			(GPIO1_REGBASE + GPIO_MSKCLRS_OFFSET)
#define GPIO_OUTDTSEL1			(GPIO1_REGBASE + GPIO_OUTDTSEL_OFFSET)
#define GPIO_OUTDTH1			(GPIO1_REGBASE + GPIO_OUTDTH_OFFSET)
#define GPIO_OUTDTL1			(GPIO1_REGBASE + GPIO_OUTDTL_OFFSET)
#define GPIO_BOTHEDGE1			(GPIO1_REGBASE + GPIO_BOTHEDGE_OFFSET)

#define GPIO2_REGBASE			(GPIO_BASE + 0x2000)
#define GPIO_IOINTSEL2			(GPIO2_REGBASE + GPIO_IOINTSEL_OFFSET)
#define GPIO_INOUTSEL2			(GPIO2_REGBASE + GPIO_INOUTSEL_OFFSET)
#define GPIO_OUTDT2			(GPIO2_REGBASE + GPIO_OUTDT_OFFSET)
#define GPIO_INDT2			(GPIO2_REGBASE + GPIO_INDT_OFFSET)
#define GPIO_INTDT2			(GPIO2_REGBASE + GPIO_INTDT_OFFSET)
#define GPIO_INTCLR2			(GPIO2_REGBASE + GPIO_INTCLR_OFFSET)
#define GPIO_INTMSK2			(GPIO2_REGBASE + GPIO_INTMSK_OFFSET)
#define GPIO_MSKCLR2			(GPIO2_REGBASE + GPIO_MSKCLR_OFFSET)
#define GPIO_POSNEG2			(GPIO2_REGBASE + GPIO_POSNEG_OFFSET)
#define GPIO_EDGLEVEL2			(GPIO2_REGBASE + GPIO_EDGLEVEL_OFFSET)
#define GPIO_FILONOFF2			(GPIO2_REGBASE + GPIO_FILONOFF_OFFSET)
#define GPIO_INTMSKS2			(GPIO2_REGBASE + GPIO_INTMSKS_OFFSET)
#define GPIO_MSKCLRS2			(GPIO2_REGBASE + GPIO_MSKCLRS_OFFSET)
#define GPIO_OUTDTSEL2			(GPIO2_REGBASE + GPIO_OUTDTSEL_OFFSET)
#define GPIO_OUTDTH2			(GPIO2_REGBASE + GPIO_OUTDTH_OFFSET)
#define GPIO_OUTDTL2			(GPIO2_REGBASE + GPIO_OUTDTL_OFFSET)
#define GPIO_BOTHEDGE2			(GPIO2_REGBASE + GPIO_BOTHEDGE_OFFSET)

#define GPIO3_REGBASE			(GPIO_BASE + 0x3000)
#define GPIO_IOINTSEL3			(GPIO3_REGBASE + GPIO_IOINTSEL_OFFSET)
#define GPIO_INOUTSEL3			(GPIO3_REGBASE + GPIO_INOUTSEL_OFFSET)
#define GPIO_OUTDT3			(GPIO3_REGBASE + GPIO_OUTDT_OFFSET)
#define GPIO_INDT3			(GPIO3_REGBASE + GPIO_INDT_OFFSET)
#define GPIO_INTDT3			(GPIO3_REGBASE + GPIO_INTDT_OFFSET)
#define GPIO_INTCLR3			(GPIO3_REGBASE + GPIO_INTCLR_OFFSET)
#define GPIO_INTMSK3			(GPIO3_REGBASE + GPIO_INTMSK_OFFSET)
#define GPIO_MSKCLR3			(GPIO3_REGBASE + GPIO_MSKCLR_OFFSET)
#define GPIO_POSNEG3			(GPIO3_REGBASE + GPIO_POSNEG_OFFSET)
#define GPIO_EDGLEVEL3			(GPIO3_REGBASE + GPIO_EDGLEVEL_OFFSET)
#define GPIO_FILONOFF3			(GPIO3_REGBASE + GPIO_FILONOFF_OFFSET)
#define GPIO_INTMSKS3			(GPIO3_REGBASE + GPIO_INTMSKS_OFFSET)
#define GPIO_MSKCLRS3			(GPIO3_REGBASE + GPIO_MSKCLRS_OFFSET)
#define GPIO_OUTDTSEL3			(GPIO3_REGBASE + GPIO_OUTDTSEL_OFFSET)
#define GPIO_OUTDTH3			(GPIO3_REGBASE + GPIO_OUTDTH_OFFSET)
#define GPIO_OUTDTL3			(GPIO3_REGBASE + GPIO_OUTDTL_OFFSET)
#define GPIO_BOTHEDGE3			(GPIO3_REGBASE + GPIO_BOTHEDGE_OFFSET)

#define GPIO4_REGBASE			(GPIO_BASE + 0x4000)
#define GPIO_IOINTSEL4			(GPIO4_REGBASE + GPIO_IOINTSEL_OFFSET)
#define GPIO_INOUTSEL4			(GPIO4_REGBASE + GPIO_INOUTSEL_OFFSET)
#define GPIO_OUTDT4			(GPIO4_REGBASE + GPIO_OUTDT_OFFSET)
#define GPIO_INDT4			(GPIO4_REGBASE + GPIO_INDT_OFFSET)
#define GPIO_INTDT4			(GPIO4_REGBASE + GPIO_INTDT_OFFSET)
#define GPIO_INTCLR4			(GPIO4_REGBASE + GPIO_INTCLR_OFFSET)
#define GPIO_INTMSK4			(GPIO4_REGBASE + GPIO_INTMSK_OFFSET)
#define GPIO_MSKCLR4			(GPIO4_REGBASE + GPIO_MSKCLR_OFFSET)
#define GPIO_POSNEG4			(GPIO4_REGBASE + GPIO_POSNEG_OFFSET)
#define GPIO_EDGLEVEL4			(GPIO4_REGBASE + GPIO_EDGLEVEL_OFFSET)
#define GPIO_FILONOFF4			(GPIO4_REGBASE + GPIO_FILONOFF_OFFSET)
#define GPIO_INTMSKS4			(GPIO4_REGBASE + GPIO_INTMSKS_OFFSET)
#define GPIO_MSKCLRS4			(GPIO4_REGBASE + GPIO_MSKCLRS_OFFSET)
#define GPIO_OUTDTSEL4			(GPIO4_REGBASE + GPIO_OUTDTSEL_OFFSET)
#define GPIO_OUTDTH4			(GPIO4_REGBASE + GPIO_OUTDTH_OFFSET)
#define GPIO_OUTDTL4			(GPIO4_REGBASE + GPIO_OUTDTL_OFFSET)
#define GPIO_BOTHEDGE4			(GPIO4_REGBASE + GPIO_BOTHEDGE_OFFSET)

#define GPIO5_REGBASE			(GPIO_BASE + 0x5000)
#define GPIO_IOINTSEL5			(GPIO5_REGBASE + GPIO_IOINTSEL_OFFSET)
#define GPIO_INOUTSEL5			(GPIO5_REGBASE + GPIO_INOUTSEL_OFFSET)
#define GPIO_OUTDT5			(GPIO5_REGBASE + GPIO_OUTDT_OFFSET)
#define GPIO_INDT5			(GPIO5_REGBASE + GPIO_INDT_OFFSET)
#define GPIO_INTDT5			(GPIO5_REGBASE + GPIO_INTDT_OFFSET)
#define GPIO_INTCLR5			(GPIO5_REGBASE + GPIO_INTCLR_OFFSET)
#define GPIO_INTMSK5			(GPIO5_REGBASE + GPIO_INTMSK_OFFSET)
#define GPIO_MSKCLR5			(GPIO5_REGBASE + GPIO_MSKCLR_OFFSET)
#define GPIO_POSNEG5			(GPIO5_REGBASE + GPIO_POSNEG_OFFSET)
#define GPIO_EDGLEVEL5			(GPIO5_REGBASE + GPIO_EDGLEVEL_OFFSET)
#define GPIO_FILONOFF5			(GPIO5_REGBASE + GPIO_FILONOFF_OFFSET)
#define GPIO_INTMSKS5			(GPIO5_REGBASE + GPIO_INTMSKS_OFFSET)
#define GPIO_MSKCLRS5			(GPIO5_REGBASE + GPIO_MSKCLRS_OFFSET)
#define GPIO_OUTDTSEL5			(GPIO5_REGBASE + GPIO_OUTDTSEL_OFFSET)
#define GPIO_OUTDTH5			(GPIO5_REGBASE + GPIO_OUTDTH_OFFSET)
#define GPIO_OUTDTL5			(GPIO5_REGBASE + GPIO_OUTDTL_OFFSET)
#define GPIO_BOTHEDGE5			(GPIO5_REGBASE + GPIO_BOTHEDGE_OFFSET)

#define GPIO6_REGBASE			(GPIO_BASE + 0x5400)
#define GPIO_IOINTSEL6			(GPIO6_REGBASE + GPIO_IOINTSEL_OFFSET)
#define GPIO_INOUTSEL6			(GPIO6_REGBASE + GPIO_INOUTSEL_OFFSET)
#define GPIO_OUTDT6			(GPIO6_REGBASE + GPIO_OUTDT_OFFSET)
#define GPIO_INDT6			(GPIO6_REGBASE + GPIO_INDT_OFFSET)
#define GPIO_INTDT6			(GPIO6_REGBASE + GPIO_INTDT_OFFSET)
#define GPIO_INTCLR6			(GPIO6_REGBASE + GPIO_INTCLR_OFFSET)
#define GPIO_INTMSK6			(GPIO6_REGBASE + GPIO_INTMSK_OFFSET)
#define GPIO_MSKCLR6			(GPIO6_REGBASE + GPIO_MSKCLR_OFFSET)
#define GPIO_POSNEG6			(GPIO6_REGBASE + GPIO_POSNEG_OFFSET)
#define GPIO_EDGLEVEL6			(GPIO6_REGBASE + GPIO_EDGLEVEL_OFFSET)
#define GPIO_FILONOFF6			(GPIO6_REGBASE + GPIO_FILONOFF_OFFSET)
#define GPIO_INTMSKS6			(GPIO6_REGBASE + GPIO_INTMSKS_OFFSET)
#define GPIO_MSKCLRS6			(GPIO6_REGBASE + GPIO_MSKCLRS_OFFSET)
#define GPIO_OUTDTSEL6			(GPIO6_REGBASE + GPIO_OUTDTSEL_OFFSET)
#define GPIO_OUTDTH6			(GPIO6_REGBASE + GPIO_OUTDTH_OFFSET)
#define GPIO_OUTDTL6			(GPIO6_REGBASE + GPIO_OUTDTL_OFFSET)
#define GPIO_BOTHEDGE6			(GPIO6_REGBASE + GPIO_BOTHEDGE_OFFSET)

#define GPIO7_REGBASE			(GPIO_BASE + 0x5800)
#define GPIO_IOINTSEL7			(GPIO7_REGBASE + GPIO_IOINTSEL_OFFSET)
#define GPIO_INOUTSEL7			(GPIO7_REGBASE + GPIO_INOUTSEL_OFFSET)
#define GPIO_OUTDT7			(GPIO7_REGBASE + GPIO_OUTDT_OFFSET)
#define GPIO_INDT7			(GPIO7_REGBASE + GPIO_INDT_OFFSET)
#define GPIO_INTDT7			(GPIO7_REGBASE + GPIO_INTDT_OFFSET)
#define GPIO_INTCLR7			(GPIO7_REGBASE + GPIO_INTCLR_OFFSET)
#define GPIO_INTMSK7			(GPIO7_REGBASE + GPIO_INTMSK_OFFSET)
#define GPIO_MSKCLR7			(GPIO7_REGBASE + GPIO_MSKCLR_OFFSET)
#define GPIO_POSNEG7			(GPIO7_REGBASE + GPIO_POSNEG_OFFSET)
#define GPIO_EDGLEVEL7			(GPIO7_REGBASE + GPIO_EDGLEVEL_OFFSET)
#define GPIO_FILONOFF7			(GPIO7_REGBASE + GPIO_FILONOFF_OFFSET)
#define GPIO_INTMSKS7			(GPIO7_REGBASE + GPIO_INTMSKS_OFFSET)
#define GPIO_MSKCLRS7			(GPIO7_REGBASE + GPIO_MSKCLRS_OFFSET)
#define GPIO_OUTDTSEL7			(GPIO7_REGBASE + GPIO_OUTDTSEL_OFFSET)
#define GPIO_OUTDTH7			(GPIO7_REGBASE + GPIO_OUTDTH_OFFSET)
#define GPIO_OUTDTL7			(GPIO7_REGBASE + GPIO_OUTDTL_OFFSET)
#define GPIO_BOTHEDGE7			(GPIO7_REGBASE + GPIO_BOTHEDGE_OFFSET)

//++++++++ USB Module ++++++++++++++++//
#define BASE_USBCTR			0xE6590000

#define HSUSB_SYSCFG			BASE_USBCTR + 0x0000
#define HSUSB_BUSWAIT			BASE_USBCTR + 0x0002
#define HSUSB_SYSSTS			BASE_USBCTR + 0x0004
#define HSUSB_DVSTCTR			BASE_USBCTR + 0x0008
#define HSUSB_TESTMODE			BASE_USBCTR + 0x000c

#define HSUSB_INTENB0			BASE_USBCTR + 0x0030
#define HSUSB_INTSTS0			BASE_USBCTR + 0x0040

#define HSUSB_UGCTRL			BASE_USBCTR + 0x0180
#define HSUSB_UGCTRL2			BASE_USBCTR + 0x0184
#define HSUSB_UGSTS			BASE_USBCTR + 0x0190

/* Watch dog timer */
#define WDTRSTCR			0xE6160054
#define WTCNT_OFF			(0x00)
#define WTCSRA_OFF			(0x04)
#define WTCSRB_OFF			(0x08)

#define WTCSRA_WRFLG			(1 << 5)
#define WTCSRA_WOVF			(1 << 4)
#define WTCSRA_TME			(1 << 7)

/* SPI numbers for ARM*/
#define SPI_IRQ0			0x00+32
#define SPI_IRQ1			0x01+32
#define SPI_IRQ2			0x02+32
#define SPI_IRQ3			0x03+32
#define SPI_GPIO0			0x04+32
#define SPI_GPIO1			0x05+32
#define SPI_GPIO2			0x06+32
#define SPI_GPIO3			0x07+32
#define SPI_GPIO4			0x08+32
#define SPI_GPIO5			0x09+32
#define SPI_MTSB0HS			0x0C+32
#define SPI_MTSB1HS			0x0D+32
#define SPI_MTSB2HS			0x0E+32
#define SPI_MTSB3HS			0x0F+32
#define SPI_MTSB4HS			0x10+32
#define SPI_MTSB5HS			0x11+32
#define SPI_MTSB6HS			0x12+32
#define SPI_MTSB7HS			0x13+32
#define SPI_MTSB8HS			0x14+32
#define SPI_MTSB9HS			0x15+32
#define SPI_MTSB10HS			0x16+32
#define SPI_MTSB11HS			0x17+32
#define SPI_MTSB12HS			0x18+32
#define SPI_MTSB13HS			0x19+32
#define SPI_MTSB14HS			0x1A+32
#define SPI_MTSB15HS			0x1B+32
#define SPI_MTSB16HS			0x1C+32
#define SPI_MTSB17HS			0x1D+32
#define SPI_MTSB18HS			0x1E+32
#define SPI_MTSB19HS			0x1F+32
#define SPI_MTSB0LS			0x20+32
#define SPI_MTSB1LS			0x21+32
#define SPI_MTSB2LS			0x22+32
#define SPI_MTSB3LS			0x23+32
#define SPI_MTSB4LS			0x24+32
#define SPI_MTSB5LS			0x25+32
#define SPI_MTSB6LS			0x26+32
#define SPI_MTSB7LS			0x27+32
#define SPI_MTSB8LS			0x28+32
#define SPI_MTSB9LS			0x29+32
#define SPI_MTSB10LS			0x2A+32
#define SPI_MTSB11LS			0x2B+32
#define SPI_MTSB12LS			0x2C+32
#define SPI_MTSB13LS			0x2D+32
#define SPI_MTSB14LS			0x2E+32
#define SPI_MTSB15LS			0x2F+32
#define SPI_MTSB16LS			0x30+32
#define SPI_MTSB17LS			0x31+32
#define SPI_MTSB18LS			0x32+32
#define SPI_MTSB19LS			0x33+32
#define SPI_MTSB20LS			0x34+32
#define SPI_MTSB21LS			0x35+32
#define SPI_MTSB22LS			0x36+32
#define SPI_MTSB23LS			0x37+32
#define SPI_MTSB24LS			0x38+32
#define SPI_MTSB25LS			0x39+32
#define SPI_MTSB26LS			0x3A+32
#define SPI_MTSB27LS			0x3B+32
#define SPI_MTSB28LS			0x3C+32
#define SPI_MTSB29LS			0x3D+32
#define SPI_MTSB30LS			0x3E+32
#define SPI_MTSB31LS			0x3F+32
//#define SPI_Reserved			0x40+32
//#define SPI_Reserved			0x41+32
//#define SPI_Reserved			0x42+32
//#define SPI_Reserved			0x43+32
//#define SPI_Reserved			0x44+32
#define Thermal_Sensor			0x45+32
#define SPI_CC4_2_0			0x46+32
#define SPI_CC4_2_1			0x47+32
#define SPI_CA15_IRQPNU_CORE0		0x48+32
#define SPI_CA15_IRQPNU_CORE1		0x49+32
#define SPI_CA15_IRQPNU_CORE2		0x4A+32
#define SPI_CA15_IRQPNU_CORE3		0x4B+32
#define CA15_CTIIRQ_CORE0		0x4C+32
#define CA15_CTIIRQ_CORE1		0x4D+32
#define CA15_CTIIRQ_CORE2		0x4E+32
#define CA15_CTIIRQ_CORE3		0x4F+32
#define SPI_CA15_nINTERRIRQ		0x50+32
#define SPI_CA15_nAXIERRIRQ		0x51+32
#define SPI_CA7_IRQPNU_CORE0		0x52+32
#define SPI_CA7_IRQPNU_CORE1		0x53+32
#define SPI_CA7_IRQPNU_CORE2		0x54+32
#define SPI_CA7_IRQPNU_CORE3		0x55+32
#define CA7_CTIIRQ_CORE0		0x56+32
#define CA7_CTIIRQ_CORE1		0x57+32
#define CA7_CTIIRQ_CORE2		0x58+32
#define CA7_CTIIRQ_CORE3		0x59+32
//#define SPI_Reserved			0x5A+32
#define SPI_CA7_nAXIERRIRQ		0x5B+32
#define SPI_CCI400			0x5C+32
#define SPI_CCI400_OVF			0x5D+32
#define SPI_TDBG			0x5E+32
#define SPI_HUDI			0x5F+32
#define SPI_LBSC_WT0			0x60+32
#define SPI_LBSC_ATA			0x61+32
#define SPI_LBSC_DMAC0			0x62+32
#define SPI_LBSC_DMAC1			0x63+32
#define SPI_LBSC_DMAC2			0x64+32
#define SPI_USB3_0_HOST			0x65+32
//#define SPI_Reserved			0x66+32
//#define SPI_Reserved			0x67+32
//#define SPI_Reserved			0x69+32
#define SPI_SATA0			0x69+32
#define SPI_SATA1			0x6A+32
#define SPI_USB2_0_597			0x6B+32
#define SPI_USB2_0_EHCI_0		0x6C+32
#define SPI_USBHSDMAC1			0x6D+32
#define SPI_USBHSDMAC2			0x6D+32
#define SPI_DDM				0x6F+32
#define SPI_USB2_0_EHCI_1		0x70+32
#define SPI_USB2_0_EHCI_2		0x71+32
#define SPI_R_GP2			0x72+32
//#define SPI_Reserved			0x73+32
#define SPI_PCIe			0x74+32
#define SPI_PCIe_DMA			0x75+32
#define SPI_PCIe_ERROR			0x76+32
#define SPI_SGX_3DG			0x77+32
#define SPI_CMT1_0			0x78+32
#define SPI_CMT1_1			0x79+32
#define SPI_CMT1_2			0x7A+32
#define SPI_CMT1_3			0x7B+32
#define SPI_CMT1_4			0x7C+32
#define SPI_CMT1_5			0x7D+32
#define SPI_CMT1_6			0x7E+32
#define SPI_CMT1_7			0x7F+32
#define SPI_TMU1_TUNI0			0x80+32
#define SPI_TMU1_TUNI1			0x81+32
#define SPI_TMU1_TUNI2			0x82+32
#define SPI_TMU3_TUNI0			0x83+32
#define SPI_TMU3_TUNI1			0x84+32
#define SPI_TMU3_TUNI2			0x85+32
#define SPI_SECURE_TIMER		0x86+32
#define SPI_TPU0			0x87+32
#define SPI_TMU0_TUNI0			0x88+32
#define SPI_TMU0_TUNI1			0x89+32
#define SPI_TMU0_TUNI2			0x8A+32
#define SPI_SECURE_UP_TIMER		0x8B+32
#define SPI_RWDT			0x8C+32
#define SPI_SECURE_RWDT			0x8D+32
#define SPI_CMT0_0			0x8E+32

#define SPI_SCIFA0			0x90+32
#define SPI_SCIFA1			0x91+32
//#define SPI_Reserved			0x92+32
#define SPI_TMU1_TUNI3			0x93+32
#define SPI_SCIFB0			0x94+32
#define SPI_SCIFB1			0x95+32
#define SPI_SCIFB2			0x96+32
#define SPI_SCIFA2			0x97+32
#define SPI_SCIF0			152+32
#define SPI_SCIF1			153+32
#define SPI_HSCIF0			154+32
#define SPI_HSCIF1			155+32
#define SPI_MSIOF0			156+32
#define SPI_MSIOF1			157+32
#define SPI_MSIOF2			158+32
#define SPI_MSIOF3			159+32
//#define SPI_Reserved			160+32
//#define SPI_Reserved			161+32
#define SPI_ETHER_Fast			162+32
#define SPI_ETHER_AVB			163+32
#define SPI_SCIF2			164+32
#define SPI_SDHI0			165+32
#define SPI_SDHI1			166+32
#define SPI_SDHI2			167+32
#define SPI_SDHI3			168+32
#define SPI_MMC0			169+32
#define SPI_MMC1			170+32
#define SPI_MFIS			171+32
#define SPI_MFIS_CA7_Core0		172+32
#define SPI_IIC_DVFS			173+32
#define SPI_IIC0			174+32
#define SPI_IIC1			175+32
#define SPI_IIC2			176+32
#define SPI_MFIS_CA7_Core1		177+32
#define SPI_MFIS_CA7_Core2		178+32
#define SPI_MFIS_CA7_Core3		179+32
#define SPI_MFIS_CA15_Core0		180+32
#define SPI_MFIS_CA15_Core1		181+32
#define SPI_MFIS_CA15_Core2		182+32
#define SPI_MFIS_CA15_Core3		183+32
#define SPI_QSPI			184+32
#define SPI_STB				185+32
#define SPI_RCAN0			186+32
#define SPI_RCAN1			187+32
#define SPI_VIN0			188+32
#define SPI_VIN1			189+32
#define SPI_VIN2			190+32
#define SPI_VIN3			191+32
#define SPI_IMR_X2_0			192+32
#define SPI_IMR_X2_1			193+32
#define SPI_IMR_LSX_0			194+32
#define SPI_IMR_LSX_1			195+32
#define SPI_IMP_X4			196+32
#define SPI_SYSDMAC0_ERR		197+32
#define SPI_IPMMUDS0			198+32
#define SPI_IPMMUDS0_SEC		199+32
#define SPI_SYSDMAC_DEI0		200+32
#define SPI_SYSDMAC_DEI1		201+32
#define SPI_SYSDMAC_DEI2		202+32
#define SPI_SYSDMAC_DEI3		203+32
#define SPI_SYSDMAC_DEI4		204+32
#define SPI_SYSDMAC_DEI5		205+32
#define SPI_SYSDMAC_DEI6		206+32
#define SPI_SYSDMAC_DEI7		207+32
#define SPI_SYSDMAC_DEI8		208+32
#define SPI_SYSDMAC_DEI9		209+32
#define SPI_SYSDMAC_DEI10		210+32
#define SPI_SYSDMAC_DEI11		211+32
#define SPI_SYSDMAC_DEI12		212+32
#define SPI_SYSDMAC_DEI13		213+32
#define SPI_SYSDMAC_DEI14		214+32
//#define SPI_Reserved			215+32
#define SPI_SYSDMAC_DEI15		216+32
#define SPI_SYSDMAC_DEI16		217+32
#define SPI_SYSDMAC_DEI17		218+32
#define SPI_SYSDMAC_DEI18		219+32
#define SPI_SYSDMAC1_ERR		220+32

#define SPI_I2C2			286+32
#define SPI_I2C0			287+32
#define SPI_I2C1			288+32
#define SPI_I2C3			290+32

#define SPI_AUDIODMAC_DEI0		(320+32)
#define SPI_AUDIODMAC_DEI1		(321+32)
#define SPI_AUDIODMAC_DEI2 		(322+32)
#define SPI_AUDIODMAC_DEI3 		(323+32)

/* QSPI */
#define QSPI_BASE			0xE6B10000
#define QSPI_SPCR			(QSPI_BASE + 0x00)	// Control register
#define QSPI_SSLP			(QSPI_BASE + 0x01)	// Slave select polarity register
#define QSPI_SPPCR			(QSPI_BASE + 0x02)	// Pin control register
#define QSPI_SPSR			(QSPI_BASE + 0x03)	// Status register
#define QSPI_SPDR			(QSPI_BASE + 0x04)	// Data register
#define QSPI_SPSCR			(QSPI_BASE + 0x08)	// Sequence control register
#define QSPI_SPSSR			(QSPI_BASE + 0x09)	// Sequence status register
#define QSPI_SPBR			(QSPI_BASE + 0x0A)	// Bit rate register
#define QSPI_SPDCR			(QSPI_BASE + 0x0B)	// Data control register
#define QSPI_SPCKD			(QSPI_BASE + 0x0C)	// Clock delay register
#define QSPI_SSLND			(QSPI_BASE + 0x0D)	// Slave select negation delay register
#define QSPI_SPND			(QSPI_BASE + 0x0E)	// Next-access delay register
#define QSPI_SPCMD0			(QSPI_BASE + 0x10)	// Command register 0
#define QSPI_SPCMD1			(QSPI_BASE + 0x12)	// Command register 1
#define QSPI_SPCMD2			(QSPI_BASE + 0x14)	// Command register 2
#define QSPI_SPCMD3			(QSPI_BASE + 0x16)	// Command register 3
#define QSPI_SPBFCR			(QSPI_BASE + 0x18)	// Buffer control register
#define QSPI_SPBDCR			(QSPI_BASE + 0x1A)	// Buffer data count register
#define QSPI_SPBMUL0			(QSPI_BASE + 0x1C)	// Transfer data length multiplier setting register 0
#define QSPI_SPBMUL1			(QSPI_BASE + 0x20)	// Transfer data length multiplier setting register 1
#define QSPI_SPBMUL2			(QSPI_BASE + 0x24)	// Transfer data length multiplier setting register 2
#define QSPI_SPBMUL3			(QSPI_BASE + 0x28)	// Transfer data length multiplier setting register 3

/* SCIF0 */
#define SCIF0_BASE			0xE6E60000

#define SCIF0_SCSMR			(SCIF0_BASE + 0x00)		// 16
#define SCIF0_SCBRR			(SCIF0_BASE + 0x04)		// 8
#define SCIF0_SCSCR			(SCIF0_BASE + 0x08)		// 16
#define SCIF0_SCFTDR			(SCIF0_BASE + 0x0C)		// 8
#define SCIF0_SCFSR			(SCIF0_BASE + 0x10)		// 16
#define SCIF0_SCFRDR			(SCIF0_BASE + 0x14)		// 8
#define SCIF0_SCFCR			(SCIF0_BASE + 0x18)		// 16
#define SCIF0_SCFDR			(SCIF0_BASE + 0x1C)		// 16
#define SCIF0_SCSPTR			(SCIF0_BASE + 0x20)		// 16
#define SCIF0_SCLSR			(SCIF0_BASE + 0x24)		// 16
#define SCIF0_DL			(SCIF0_BASE + 0x30)		// 16
#define SCIF0_CKS			(SCIF0_BASE + 0x34)		// 16
#define SCIF0_SCFER			(SCIF0_BASE + 0x44)		// 16

/* these should be removed and replaced with the ones below */
#define SH_BRG_DL			0x30
#define SH_BRG_CKS			0x34
#define SH_SCIF_FIFO_LEN		16

#define RCAR_BRG_DL         0x30
#define RCAR_BRG_CKS        0x34
#define RCAR_SCIF_FIFO_LEN  16

/* SYS-Direct Memory Access Controller (SYS-DMAC) */
#define SYSDMAC0_BASE			0xE6700000			// SYSDMAC0_BASE 0xE6700000
#define SYSDMAC_DMAISTA_L		(SYSDMAC0_BASE + 0x0020)	//DMA interrupt status register (for low channel number)
#define SYSDMAC_DMASEC_L		(SYSDMAC0_BASE + 0x0030)	//DMA secure control register (for low channel number)
#define SYSDMAC_DMAOR_L			(SYSDMAC0_BASE + 0x0060)	//DMA operation register (for low channel number)
#define SYSDMAC_DMACHCLR_L		(SYSDMAC0_BASE + 0x0080)	//DMA channel clear register (for low channel number)
#define SYSDMAC_DMADPSEC_L		(SYSDMAC0_BASE + 0x00A0)	//DPRAM secure control register (for low channel number)

#define SYSDMAC_DMASAR_01		(SYSDMAC0_BASE + 0x8080)	//DMA source address register _01
#define SYSDMAC_DMADAR_01		(SYSDMAC0_BASE + 0x8084)	//DMA destination address register _01
#define SYSDMAC_DMATCR_01		(SYSDMAC0_BASE + 0x8088)	//DMA transfer count register _01
#define SYSDMAC_DMATSR_01		(SYSDMAC0_BASE + 0x80A8)	//DMA transfer size register _01
#define SYSDMAC_DMACHCR_01		(SYSDMAC0_BASE + 0x808C)	//DMA channel control register _01
#define SYSDMAC_DMATCRB_01		(SYSDMAC0_BASE + 0x8098)	//DMA transfer count register B_01
#define SYSDMAC_DMATSRB_01		(SYSDMAC0_BASE + 0x80B8)	//DMA transfer size register B_01

#define SYSDMAC_DMACHCRB_01		(SYSDMAC0_BASE + 0x809C)	//DMA channel control register B_01
#define SYSDMAC_DMARS_01		(SYSDMAC0_BASE + 0x80C0)	//DMA extended resource register _01
#define SYSDMAC_DMABUFCR_01		(SYSDMAC0_BASE + 0x80C8)	//DMA buffer control register _01
#define SYSDMAC_DMADPBASE_01		(SYSDMAC0_BASE + 0x80D0)	//DMA descriptor base address register _01
#define SYSDMAC_DMADPCR_01		(SYSDMAC0_BASE + 0x80D4)	//DMA descriptor control register _01
#define SYSDMAC_DMAFIXDPBASE_01		(SYSDMAC0_BASE + 0x80E0)	//DMA fixed descriptor base address register _01
#define SYSDMAC_DMAFIXSAR_01		(SYSDMAC0_BASE + 0x8090)	//DMA fixed source address register _01
#define SYSDMAC_DMAFIXDAR_01		(SYSDMAC0_BASE + 0x8094)	//DMA fixed destination address register _01

/* LBSC Registers */
#define LBSC_BASE			0xFEC00000

#define LBSC_CS0CTRL			(LBSC_BASE + 0x0200)
#define LBSC_CS1CTRL			(LBSC_BASE + 0x0204)
#define LBSC_ECS0CTRL			(LBSC_BASE + 0x0208)
#define LBSC_ECS1CTRL			(LBSC_BASE + 0x020C)
#define LBSC_ECS2CTRL			(LBSC_BASE + 0x0210)
#define LBSC_ECS3CTRL			(LBSC_BASE + 0x0214)
#define LBSC_ECS4CTRL			(LBSC_BASE + 0x0218)
#define LBSC_ECS5CTRL			(LBSC_BASE + 0x021C)
#define LBSC_CSWCR0			(LBSC_BASE + 0x0230)
#define LBSC_CSWCR1			(LBSC_BASE + 0x0234)
#define LBSC_ECSWCR0			(LBSC_BASE + 0x0238)
#define LBSC_ECSWCR1			(LBSC_BASE + 0x023C)
#define LBSC_ECSWCR2			(LBSC_BASE + 0x0240)
#define LBSC_ECSWCR3			(LBSC_BASE + 0x0244)
#define LBSC_ECSWCR4			(LBSC_BASE + 0x0248)
#define LBSC_ECSWCR5			(LBSC_BASE + 0x024C)
#define LBSC_EXDMAWCR0			(LBSC_BASE + 0x0250)
#define LBSC_EXDMAWCR1			(LBSC_BASE + 0x0254)
#define LBSC_EXDMAWCR2			(LBSC_BASE + 0x0258)
#define LBSC_CSPWCR0			(LBSC_BASE + 0x0280)
#define LBSC_CSPWCR1			(LBSC_BASE + 0x0284)
#define LBSC_ECSPWCR0			(LBSC_BASE + 0x0288)
#define LBSC_ECSPWCR1			(LBSC_BASE + 0x028C)
#define LBSC_ECSPWCR2			(LBSC_BASE + 0x0290)
#define LBSC_ECSPWCR3			(LBSC_BASE + 0x0294)
#define LBSC_ECSPWCR4			(LBSC_BASE + 0x0298)
#define LBSC_ECSPWCR5			(LBSC_BASE + 0x029C)
#define LBSC_EXWTSYNC			(LBSC_BASE + 0x02A0)
#define LBSC_CS0BSTCTL			(LBSC_BASE + 0x02B0)
#define LBSC_CS0BTPH			(LBSC_BASE + 0x02B4)
#define LBSC_CS1GDST			(LBSC_BASE + 0x02C0)
#define LBSC_ECS0GDST			(LBSC_BASE + 0x02C4)
#define LBSC_ECS1GDST			(LBSC_BASE + 0x02C8)
#define LBSC_ECS2GDST			(LBSC_BASE + 0x02CC)
#define LBSC_ECS3GDST			(LBSC_BASE + 0x02D0)
#define LBSC_ECS4GDST			(LBSC_BASE + 0x02D4)
#define LBSC_ECS5GDST			(LBSC_BASE + 0x02D8)
#define LBSC_EXDMASET0			(LBSC_BASE + 0x02F0)
#define LBSC_EXDMASET1			(LBSC_BASE + 0x02F4)
#define LBSC_EXDMASET2			(LBSC_BASE + 0x02F8)
#define LBSC_EXDMCR0			(LBSC_BASE + 0x0310)
#define LBSC_EXDMCR1			(LBSC_BASE + 0x0314)
#define LBSC_EXDMCR2			(LBSC_BASE + 0x0318)
#define LBSC_BCINTSR			(LBSC_BASE + 0x0330)
#define LBSC_BCINTCR			(LBSC_BASE + 0x0334)
#define LBSC_BCINTMR			(LBSC_BASE + 0x0338)
#define LBSC_EXBATLV			(LBSC_BASE + 0x0340)
#define LBSC_EXWTSTS			(LBSC_BASE + 0x0344)
#define LBSC_ATACSCTRL			(LBSC_BASE + 0x0380)
#define LBSC_EXBCT			(LBSC_BASE + 0x03C0)
#define LBSC_EXTCT			(LBSC_BASE + 0x03C4)
#define LBSC_EXTSR			(LBSC_BASE + 0x0010)
#define LBSC_EXTADR			(LBSC_BASE + 0x0014)

/* DBSC3 Registers */
#define DBSC3_0_BASE			0xE6790000

#define DBSC3_0_DBSTATE1		(DBSC3_0_BASE + 0x00C)
#define DBSC3_0_DBACEN			(DBSC3_0_BASE + 0x010)
#define DBSC3_0_DBRFEN			(DBSC3_0_BASE + 0x014)
#define DBSC3_0_DBCMD			(DBSC3_0_BASE + 0x018)
#define DBSC3_0_DBWAIT			(DBSC3_0_BASE + 0x01C)
#define DBSC3_0_DBKIND			(DBSC3_0_BASE + 0x020)
#define DBSC3_0_DBCONF0			(DBSC3_0_BASE + 0x024)
#define DBSC3_0_DBPHYTYPE		(DBSC3_0_BASE + 0x030)
#define DBSC3_0_DBTR0			(DBSC3_0_BASE + 0x040)
#define DBSC3_0_DBTR1			(DBSC3_0_BASE + 0x044)
#define DBSC3_0_DBTR2			(DBSC3_0_BASE + 0x048)
#define DBSC3_0_DBTR3			(DBSC3_0_BASE + 0x050)
#define DBSC3_0_DBTR4			(DBSC3_0_BASE + 0x054)
#define DBSC3_0_DBTR5			(DBSC3_0_BASE + 0x058)
#define DBSC3_0_DBTR6			(DBSC3_0_BASE + 0x05C)
#define DBSC3_0_DBTR7			(DBSC3_0_BASE + 0x060)
#define DBSC3_0_DBTR8			(DBSC3_0_BASE + 0x064)
#define DBSC3_0_DBTR9			(DBSC3_0_BASE + 0x068)
#define DBSC3_0_DBTR10			(DBSC3_0_BASE + 0x06C)
#define DBSC3_0_DBTR11			(DBSC3_0_BASE + 0x070)
#define DBSC3_0_DBTR12			(DBSC3_0_BASE + 0x074)
#define DBSC3_0_DBTR13			(DBSC3_0_BASE + 0x078)
#define DBSC3_0_DBTR14			(DBSC3_0_BASE + 0x07C)
#define DBSC3_0_DBTR15			(DBSC3_0_BASE + 0x080)
#define DBSC3_0_DBTR16			(DBSC3_0_BASE + 0x084)
#define DBSC3_0_DBTR17			(DBSC3_0_BASE + 0x088)
#define DBSC3_0_DBTR18			(DBSC3_0_BASE + 0x08C)
#define DBSC3_0_DBTR19			(DBSC3_0_BASE + 0x090)
#define DBSC3_0_DBBL			(DBSC3_0_BASE + 0x0B0)
#define DBSC3_0_DBADJ0			(DBSC3_0_BASE + 0x0C0)
#define DBSC3_0_DBADJ2			(DBSC3_0_BASE + 0x0C8)
#define DBSC3_0_DBRFCNF0		(DBSC3_0_BASE + 0x0E0)
#define DBSC3_0_DBRFCNF1		(DBSC3_0_BASE + 0x0E4)
#define DBSC3_0_DBRFCNF2		(DBSC3_0_BASE + 0x0E8)
#define DBSC3_0_DBCALCNF		(DBSC3_0_BASE + 0x0F4)
#define DBSC3_0_DBCALTR			(DBSC3_0_BASE + 0x0F8)
#define DBSC3_0_DBRNK0			(DBSC3_0_BASE + 0x100)
#define DBSC3_0_DBPDNCNF		(DBSC3_0_BASE + 0x180)
#define DBSC3_0_DBDFISTAT		(DBSC3_0_BASE + 0x240)
#define DBSC3_0_DBDFICNT		(DBSC3_0_BASE + 0x244)
#define DBSC3_0_DBPDLCK			(DBSC3_0_BASE + 0x280)
#define DBSC3_0_DBPDRGA			(DBSC3_0_BASE + 0x290)
#define DBSC3_0_DBPDRGD			(DBSC3_0_BASE + 0x2A0)
#define DBSC3_0_DBBS0CNT1		(DBSC3_0_BASE + 0x304)
#define DBSC3_0_DBWT0CNF0		(DBSC3_0_BASE + 0x380)
#define DBSC3_0_DBWT0CNF4		(DBSC3_0_BASE + 0x390)
#define DBSC3_0_DBSCHECNT0		(DBSC3_0_BASE + 0x500)

#define DBSC3_1_BASE			0xE67A0000

#define DBSC3_1_DBSTATE1		(DBSC3_1_BASE + 0x00C)
#define DBSC3_1_DBACEN			(DBSC3_1_BASE + 0x010)
#define DBSC3_1_DBRFEN			(DBSC3_1_BASE + 0x014)
#define DBSC3_1_DBCMD			(DBSC3_1_BASE + 0x018)
#define DBSC3_1_DBWAIT			(DBSC3_1_BASE + 0x01C)
#define DBSC3_1_DBKIND			(DBSC3_1_BASE + 0x020)
#define DBSC3_1_DBCONF0			(DBSC3_1_BASE + 0x024)
#define DBSC3_1_DBPHYTYPE		(DBSC3_1_BASE + 0x030)
#define DBSC3_1_DBTR0			(DBSC3_1_BASE + 0x040)
#define DBSC3_1_DBTR1			(DBSC3_1_BASE + 0x044)
#define DBSC3_1_DBTR2			(DBSC3_1_BASE + 0x048)
#define DBSC3_1_DBTR3			(DBSC3_1_BASE + 0x050)
#define DBSC3_1_DBTR4			(DBSC3_1_BASE + 0x054)
#define DBSC3_1_DBTR5			(DBSC3_1_BASE + 0x058)
#define DBSC3_1_DBTR6			(DBSC3_1_BASE + 0x05C)
#define DBSC3_1_DBTR7			(DBSC3_1_BASE + 0x060)
#define DBSC3_1_DBTR8			(DBSC3_1_BASE + 0x064)
#define DBSC3_1_DBTR9			(DBSC3_1_BASE + 0x068)
#define DBSC3_1_DBTR10			(DBSC3_1_BASE + 0x06C)
#define DBSC3_1_DBTR11			(DBSC3_1_BASE + 0x070)
#define DBSC3_1_DBTR12			(DBSC3_1_BASE + 0x074)
#define DBSC3_1_DBTR13			(DBSC3_1_BASE + 0x078)
#define DBSC3_1_DBTR14			(DBSC3_1_BASE + 0x07C)
#define DBSC3_1_DBTR15			(DBSC3_1_BASE + 0x080)
#define DBSC3_1_DBTR16			(DBSC3_1_BASE + 0x084)
#define DBSC3_1_DBTR17			(DBSC3_1_BASE + 0x088)
#define DBSC3_1_DBTR18			(DBSC3_1_BASE + 0x08C)
#define DBSC3_1_DBTR19			(DBSC3_1_BASE + 0x090)
#define DBSC3_1_DBBL			(DBSC3_1_BASE + 0x0B0)
#define DBSC3_1_DBADJ0			(DBSC3_1_BASE + 0x0C0)
#define DBSC3_1_DBADJ2			(DBSC3_1_BASE + 0x0C8)
#define DBSC3_1_DBRFCNF0		(DBSC3_1_BASE + 0x0E0)
#define DBSC3_1_DBRFCNF1		(DBSC3_1_BASE + 0x0E4)
#define DBSC3_1_DBRFCNF2		(DBSC3_1_BASE + 0x0E8)
#define DBSC3_1_DBCALCNF		(DBSC3_1_BASE + 0x0F4)
#define DBSC3_1_DBCALTR			(DBSC3_1_BASE + 0x0F8)
#define DBSC3_1_DBRNK0			(DBSC3_1_BASE + 0x100)
#define DBSC3_1_DBPDNCNF		(DBSC3_1_BASE + 0x180)
#define DBSC3_1_DBDFISTAT		(DBSC3_1_BASE + 0x240)
#define DBSC3_1_DBDFICNT		(DBSC3_1_BASE + 0x244)
#define DBSC3_1_DBPDLCK			(DBSC3_1_BASE + 0x280)
#define DBSC3_1_DBPDRGA			(DBSC3_1_BASE + 0x290)
#define DBSC3_1_DBPDRGD			(DBSC3_1_BASE + 0x2A0)
#define DBSC3_1_DBBS0CNT1		(DBSC3_1_BASE + 0x304)
#define DBSC3_1_DBWT0CNF0		(DBSC3_1_BASE + 0x380)
#define DBSC3_1_DBWT0CNF4		(DBSC3_1_BASE + 0x390)
#define DBSC3_1_DBSCHECNT0		(DBSC3_1_BASE + 0x500)

#define DBSC3_0_QOS_R0_BASE		0xE6791000
#define DBSC3_0_QOS_R1_BASE		0xE6791100
#define DBSC3_0_QOS_R2_BASE		0xE6791200
#define DBSC3_0_QOS_R3_BASE		0xE6791300
#define DBSC3_0_QOS_R4_BASE		0xE6791400
#define DBSC3_0_QOS_R5_BASE		0xE6791500
#define DBSC3_0_QOS_R6_BASE		0xE6791600
#define DBSC3_0_QOS_R7_BASE		0xE6791700
#define DBSC3_0_QOS_R8_BASE		0xE6791800
#define DBSC3_0_QOS_R9_BASE		0xE6791900
#define DBSC3_0_QOS_R10_BASE		0xE6791A00
#define DBSC3_0_QOS_R11_BASE		0xE6791B00
#define DBSC3_0_QOS_R12_BASE		0xE6791C00
#define DBSC3_0_QOS_R13_BASE		0xE6791D00
#define DBSC3_0_QOS_R14_BASE		0xE6791E00
#define DBSC3_0_QOS_R15_BASE		0xE6791F00
#define DBSC3_0_QOS_W0_BASE		0xE6792000
#define DBSC3_0_QOS_W1_BASE		0xE6792100
#define DBSC3_0_QOS_W2_BASE		0xE6792200
#define DBSC3_0_QOS_W3_BASE		0xE6792300
#define DBSC3_0_QOS_W4_BASE		0xE6792400
#define DBSC3_0_QOS_W5_BASE		0xE6792500
#define DBSC3_0_QOS_W6_BASE		0xE6792600
#define DBSC3_0_QOS_W7_BASE		0xE6792700
#define DBSC3_0_QOS_W8_BASE		0xE6792800
#define DBSC3_0_QOS_W9_BASE		0xE6792900
#define DBSC3_0_QOS_W10_BASE		0xE6792A00
#define DBSC3_0_QOS_W11_BASE		0xE6792B00
#define DBSC3_0_QOS_W12_BASE		0xE6792C00
#define DBSC3_0_QOS_W13_BASE		0xE6792D00
#define DBSC3_0_QOS_W14_BASE		0xE6792E00
#define DBSC3_0_QOS_W15_BASE		0xE6792F00

#define DBSC3_1_QOS_R0_BASE		0xE67A1000
#define DBSC3_1_QOS_R1_BASE		0xE67A1100
#define DBSC3_1_QOS_R2_BASE		0xE67A1200
#define DBSC3_1_QOS_R3_BASE		0xE67A1300
#define DBSC3_1_QOS_R4_BASE		0xE67A1400
#define DBSC3_1_QOS_R5_BASE		0xE67A1500
#define DBSC3_1_QOS_R6_BASE		0xE67A1600
#define DBSC3_1_QOS_R7_BASE		0xE67A1700
#define DBSC3_1_QOS_R8_BASE		0xE67A1800
#define DBSC3_1_QOS_R9_BASE		0xE67A1900
#define DBSC3_1_QOS_R10_BASE		0xE67A1A00
#define DBSC3_1_QOS_R11_BASE		0xE67A1B00
#define DBSC3_1_QOS_R12_BASE		0xE67A1C00
#define DBSC3_1_QOS_R13_BASE		0xE67A1D00
#define DBSC3_1_QOS_R14_BASE		0xE67A1E00
#define DBSC3_1_QOS_R15_BASE		0xE67A1F00
#define DBSC3_1_QOS_W0_BASE		0xE67A2000
#define DBSC3_1_QOS_W1_BASE		0xE67A2100
#define DBSC3_1_QOS_W2_BASE		0xE67A2200
#define DBSC3_1_QOS_W3_BASE		0xE67A2300
#define DBSC3_1_QOS_W4_BASE		0xE67A2400
#define DBSC3_1_QOS_W5_BASE		0xE67A2500
#define DBSC3_1_QOS_W6_BASE		0xE67A2600
#define DBSC3_1_QOS_W7_BASE		0xE67A2700
#define DBSC3_1_QOS_W8_BASE		0xE67A2800
#define DBSC3_1_QOS_W9_BASE		0xE67A2900
#define DBSC3_1_QOS_W10_BASE		0xE67A2A00
#define DBSC3_1_QOS_W11_BASE		0xE67A2B00
#define DBSC3_1_QOS_W12_BASE		0xE67A2C00
#define DBSC3_1_QOS_W13_BASE		0xE67A2D00
#define DBSC3_1_QOS_W14_BASE		0xE67A2E00
#define DBSC3_1_QOS_W15_BASE		0xE67A2F00

#define S3C_QOS_DCACHE_BASE		0xE6784BDC
#define S3C_QOS_CCI0_BASE		0xE6784C00
#define S3C_QOS_CCI1_BASE		0xE6784C24
#define S3C_QOS_MXI_BASE		0xE6784C48
#define S3C_QOS_AXI_BASE		0xE6784C6C

#define CCI_400_QOSCNTL_1		0xF009110C
#define CCI_400_QOSCNTL_2		0xF009210C

#define	MXI_QOS_BASE			0xFE960300

#endif /* __RENESAS_REG_H_INCLUDED */

#if defined(__QNXNTO__) && defined(__USESRCVERSION)
#include <sys/srcversion.h>
__SRCVERSION("$URL: http://svn.ott.qnx.com/product/hardware/branches/release/hardware/startup/boards/public/arm/renesas_reg.h $ $Rev: 994161 $")
#endif
