353 lines
11 KiB
C
353 lines
11 KiB
C
/*
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* $QNXLicenseC:
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* Copyright 2007, 2008, QNX Software Systems.
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*
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* Licensed under the Apache License, Version 2.0 (the "License"). You
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* may not reproduce, modify or distribute this software except in
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* compliance with the License. You may obtain a copy of the License
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* at: http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" basis,
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* WITHOUT WARRANTIES OF ANY KIND, either express or implied.
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*
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* This file may contain contributions from others, either as
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* contributors under the License or as licensors under other terms.
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* Please review this entire file for other proprietary rights or license
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* notices, as well as the QNX Development Suite License Guide at
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* http://licensing.qnx.com/license-guide/ for other information.
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* $
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*/
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#ifndef _SD_H_INCLUDED
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#define _SD_H_INCLUDED
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#define SD_CID_SIZE 16
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#define SD_CSD_SIZE 16
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#define SD_ERASE_TIMEOUT 250 // 250ms
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#define SD_GO_IDLE_STATE 0
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#define SD_ALL_SEND_CID 2
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#define SD_SEND_RELATIVE_ADDR 3
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#define SD_SEND_RELATIVE_ADDR_RETRIES 255
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#define SD_SET_DSR 4
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#define SD_SLEEP_AWAKE 5
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#define SD_SA_SLEEP (1 << 15 )
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#define SD_SWITCH_FUNC 6
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#define SD_SF_MODE_SET 0x1
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#define SD_SF_MODE_CHECK 0x0
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#define SD_SF_GRP_DFLT 0x0
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#define SD_SF_GRP_BUS_SPD 0x0 // Bus Speed
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#define SD_SF_GRP_CMD_EXT 0x1 // Command System Extension
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#define SD_SF_GRP_DRV_STR 0x2 // Driver Strength
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#define SD_SF_GRP_CUR_LMT 0x3 // Current Limit
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#define SD_SF_CUR_FCN 0xf
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#define SD_SF_STATUS_SIZE 64
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#define SD_SEL_DES_CARD 7
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#define SD_SEND_IF_COND 8
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#define SD_SIC_VHS_27_36V 1
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#define SD_SIC_TEST_PATTERN 0xaa
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#define SD_SEND_EXT_CSD 8
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#define SD_SEND_CSD 9
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#define SD_SEND_CID 10
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#define SD_VOLTAGE_SWITCH 11
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#define SD_STOP_TRANSMISSION 12
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#define SD_SEND_STATUS 13
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// Card/Device Status Response Bits
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#define CDS_OUT_OF_RANGE (1 << 31)
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#define CDS_ADDRESS_ERROR (1 << 30)
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#define CDS_BLOCK_LEN_ERROR (1 << 29)
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#define CDS_ERASE_SEQ_ERROR (1 << 28)
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#define CDS_ERASE_PARAM (1 << 27)
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#define CDS_WP_VIOLATION (1 << 26)
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#define CDS_CARD_IS_LOCKED (1 << 25)
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#define CDS_LOCK_UNLOCK_FAILED (1 << 24)
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#define CDS_COM_CRC_ERROR (1 << 23)
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#define CDS_ILLEGAL_COMMAND (1 << 22)
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#define CDS_CARD_ECC_FAILED (1 << 21)
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#define CDS_CC_ERROR (1 << 20)
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#define CDS_ERROR (1 << 19)
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#define CDS_UNDERRUN (1 << 18)
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#define CDS_OVERRUN (1 << 17)
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#define CDS_CID_CSD_OVERWRITE (1 << 16)
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#define CDS_WP_ERASE_SKIP (1 << 15)
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#define CDS_CARD_ECC_DISABLED (1 << 14)
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#define CDS_ERASE_RESET (1 << 13)
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#define CDS_CUR_STATE_MSK ( 0xf << 9 )
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#define CDS_CUR_STATE_IDLE (0 << 9)
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#define CDS_CUR_STATE_READY (1 << 9)
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#define CDS_CUR_STATE_IDENT (2 << 9)
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#define CDS_CUR_STATE_STANDBY (3 << 9)
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#define CDS_CUR_STATE_TRAN (4 << 9)
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#define CDS_CUR_STATE_DATA (5 << 9)
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#define CDS_CUR_STATE_RCV (6 << 9)
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#define CDS_CUR_STATE_PRG (7 << 9)
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#define CDS_CUR_STATE_DIS (8 << 9)
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#define CDS_READY_FOR_DATA (1 << 8)
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#define CDS_SWITCH_ERROR (1 << 7)
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#define CDS_URGENT_BKOPS (1 << 6)
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#define CDS_APP_CMD_S (1 << 5)
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#define CDS_ERROR_MSK ( CDS_OUT_OF_RANGE | \
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CDS_ADDRESS_ERROR | \
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CDS_BLOCK_LEN_ERROR | \
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CDS_ERASE_SEQ_ERROR | \
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CDS_ERASE_PARAM | \
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CDS_WP_VIOLATION | \
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CDS_CARD_IS_LOCKED | \
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CDS_LOCK_UNLOCK_FAILED | \
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CDS_COM_CRC_ERROR | \
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CDS_ILLEGAL_COMMAND | \
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CDS_CARD_ECC_FAILED | \
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CDS_CC_ERROR | \
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CDS_ERROR | \
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CDS_SWITCH_ERROR | \
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CDS_CID_CSD_OVERWRITE )
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#define SD_GO_INACTIVE_STATE 15
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#define SD_SET_BLOCKLEN 16
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#define SD_READ_SINGLE_BLOCK 17
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#define SD_READ_MULTIPLE_BLOCK 18
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#define SD_SEND_TUNING_BLOCK 19
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#define SD_SPEED_CLASS_CONTROL 20
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#define SD_SET_UPPER_ADDR 22
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#define SD_SET_BLOCK_COUNT 23
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#define SD_WRITE_BLOCK 24
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#define SD_WRITE_MULTIPLE_BLOCK 25
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#define SD_PROGRAM_CSD 27
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#define SD_SET_WRITE_PROT 28
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#define SD_CLR_WRITE_PROT 29
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#define SD_SEND_WRITE_PROT 30
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#define SD_ERASE_WR_BLK_START 32
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#define SD_ERASE_WR_BLK_END 33
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#define SD_ERASE 38
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#define SD_ERASE_NORM 0x00000000
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#define SD_ERASE_TRIM 0x00000001
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#define SD_ERASE_GARBAGE_COLLECT 0x80008001
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#define SD_ERASE_SECURE_TRIM 0x80000001
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#define SD_ERASE_SECURE 0x80000000
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#define SD_LOCK_UNLOCK 42
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#define SD_LU_ERASE 0x08
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#define SD_LU_LOCK 0x04
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#define SD_LU_UNLOCK 0x00
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#define SD_LU_CLR_PWD 0x02
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#define SD_LU_SET_PWD 0x01
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#define SD_LU_PWD_SIZE 16 // max password size
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#define SD_READ_EXTR_SINGLE 48
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#define SD_WRITE_EXTR_SINGLE 49
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#define SD_READ_EXTR_MULTI 58
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#define SD_WRITE_EXTR_MULTI 59
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#define SD_EXTR_SIZE 512
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#define SD_EXTR_MIO( _t ) ( (_t) & SD_EXTR_MIO_MSK )
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#define SD_EXTR_IO ( 1 << 31 )
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#define SD_EXTR_MEM ( 0 << 31 )
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#define SD_EXTR_MIO_MSK ( 1 << 31 )
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#define SD_EXTR_MW ( 1 << 26 )
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#define SD_EXTR_MWM( _m ) ( (_m) & SD_EXTR_MWM_MSK )
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#define SD_EXTR_MWM_MSK ( 1 << 26 )
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#define SD_EXTR_FNO( _f ) ( ( (_f) & 0xf ) << 27 )
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#define SD_EXTR_ADDR( _a ) ( ( (_a) & 0x1ffff ) << 9 )
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#define SD_EXTR_LEN_MSK( _l, _m ) ( (_m) ? ( (_l) & 0xff ) : ( ( (_l) - 1 ) & 0x1ff ) )
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#define SD_APP_CMD 55
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#define SD_GEN_CMD 56
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#define SD_READ_OCR 58
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#define SD_CRC_ON_OFF 59
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// ACMDS - preceded with APP_CMD (CMD55)
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#define SD_AC_SET_BUS_WIDTH 6
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#define SD_BUS_WIDTH_1 0
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#define SD_BUS_WIDTH_4 2
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#define SD_AC_SD_STATUS 13
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#define SD_STATUS_SIZE 64
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#define SD_AC_SEND_NUM_WR_BLOCKS 22
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#define SD_AC_SET_WR_BLK_ERASE_COUNT 23
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#define SD_AC_SEND_OP_COND 41
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#define SD_AC_SET_CLR_CARD_DETECT 42
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#define SD_AC_SEND_SCR 51
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#define SD_SCR_SIZE 8
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// ASSD commands
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#define SD_READ_SEC_CMD 34
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#define SD_WRITE_SEC_CMD 35
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#define SD_SEC_CMD_SIZE 512
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#define SD_SEND_PSI 36
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#define SD_PSI_ASSD_SR 0 // ASSD Status Register
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#define SD_PSI_ASSD_PR 4 // ASSD Properties Register
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#define SD_PSI_ASSD_RNR 6 // ASSD Random Number Register
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#define SD_PSI_SIZE 32
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#define SD_CONTROL_ASSD_SYSTEM 37
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#define SD_DIRECT_SECURE_READ 50
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#define SD_DIRECT_SECURE_WRITE 57
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typedef struct _sd_cid_t {
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_Uint8t mid; // Manufacture ID
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_Uint8t oid[3]; // OEM/Application ID
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_Uint8t pnm[6]; // Product name
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_Uint8t prv; // Product revision
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_Uint32t psn; // Product serial number
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_Uint16t mdt; // Manufacture date
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} sd_cid_t;
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typedef struct _sd_scr_t {
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_Uint8t scr_structure; // SCR structure
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// SD version is a combination of sd_spec, sd_spec3, sd_spec4 and sd_specx. See specification.
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#define SCR_SPEC_VER_0 0 // Version 1.0 - 1.01
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#define SCR_SPEC_VER_1 1 // Version 1.10
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#define SCR_SPEC_VER_2 2 // Version 2.0 or Version 3.0X
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#define SCR_SPEC3_VER_3 1 // Version 3
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#define SCR_SPEC4_VER_4 1 // Version 4
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#define SCR_SPECX_VER_5 1 // Version 5
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#define SCR_SPECX_VER_6 2 // Version 6
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#define SCR_SPECX_VER_7 3 // Version 7
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#define SCR_SPECX_VER_8 4 // Version 8
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_Uint8t sd_spec; // Physical layer specification
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_Uint8t data_stat_after_erase;
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_Uint8t sd_security;
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#define SCR_BUS_WIDTH_1 (1 << 0)
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#define SCR_BUS_WIDTH_4 (1 << 2)
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_Uint8t sd_bus_widths;
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_Uint8t sd_spec3;
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_Uint8t sd_spec4;
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_Uint8t sd_specx;
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_Uint8t ex_security;
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#define SCR_CMD58_59_SUP (1 << 3)
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#define SCR_CMD48_49_SUP (1 << 2)
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#define SCR_CMD23_SUP (1 << 1)
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#define SCR_CMD20_SUP (1 << 0)
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_Uint8t cmd_support;
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} sd_scr_t;
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typedef struct _sd_sds_t { // SD Status
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_Uint32t speed_class;
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_Uint32t uhs_speed_grade;
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_Uint32t au_size;
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_Uint32t uhs_au_size;
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_Uint32t erase_timeout;
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_Uint32t erase_offset;
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#define SD_PERF_CLASS_A2 2
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_Uint32t perf_class;
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_Uint32t perf_enh;
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} sd_sds_t;
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typedef struct _sd_switch_cap {
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_Uint32t dtr_max_hs;
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#define SD_BUS_MODE_LS ( 1 << 0 )
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#define SD_BUS_MODE_SDR12 ( 1 << 0 )
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#define SD_BUS_MODE_HS ( 1 << 1 )
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#define SD_BUS_MODE_SDR25 ( 1 << 1 )
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#define SD_BUS_MODE_SDR50 ( 1 << 2 )
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#define SD_BUS_MODE_SDR104 ( 1 << 3 )
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#define SD_BUS_MODE_DDR50 ( 1 << 4 )
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#define SD_BUS_MODE_UHS ( SD_BUS_MODE_SDR50 | SD_BUS_MODE_SDR104 | SD_BUS_MODE_DDR50 )
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#define SD_BUS_MODE_MSK 0x1f
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_Uint32t bus_mode;
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#define SD_CMD_SYS_EC ( 1 << 1 ) // eCommerce
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#define SD_CMD_SYS_OTP ( 1 << 3 )
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#define SD_CMD_SYS_ASSD ( 1 << 4 )
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_Uint32t cmd_sys;
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#define SD_DRV_TYPE_B 0x01
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#define SD_DRV_TYPE_A 0x02
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#define SD_DRV_TYPE_C 0x04
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#define SD_DRV_TYPE_D 0x08
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#define SD_DRV_TYPE_MSK 0x0f
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_Uint32t drv_type;
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#define SD_CURR_LIMIT_200 ( 1 << 0 )
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#define SD_CURR_LIMIT_400 ( 1 << 1 )
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#define SD_CURR_LIMIT_600 ( 1 << 2 )
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#define SD_CURR_LIMIT_800 ( 1 << 3 )
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#define SD_CURR_LIMIT_MSK 0xf
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_Uint32t curr_limit;
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} sd_switch_cap_t;
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#define SD_FCN_PG_SZ 512
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typedef struct _sd_fcn_ext_hdr {
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uint8_t structure_revsion[2];
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uint8_t gen_info_length[2];
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uint8_t number_extensions;
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uint8_t rsvd[11];
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} sd_fcn_ext_hdr;
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typedef struct _sd_fcn_ext {
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#define SFC_PWR_MGNT 0x01
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#define SFC_PERF_ENH 0x02
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uint16_t sfc; // Standard Function Code
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uint16_t fcc; // Function Capability Code
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uint16_t fmc; // Function Manufacturer Code
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uint8_t fmn[16]; // Function Manufacturer Name
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uint16_t pfc; // Particular Function Code
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uint8_t fn[16]; // Function Name
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uint16_t pne; // Pointer to Next Extension
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uint8_t nrs; // Number of Register Sets
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uint8_t rsvd;
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#define SD_FCN_EXT_FNO( _rsa ) ( ( (_rsa) >> 18 ) & 0xf )
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#define SD_FCN_EXT_SADDR( _rsa ) ( (_rsa) & 0x1ffff )
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uint32_t rsa[1]; // Variable length Register Set Addresses
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} sd_fcn_ext;
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// Power Management Function Register definitions
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#define PWR_MGNT_REV 0 // Ronly
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#define PWR_MGNT_REV_MSK 0xf
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#define PWR_MGNT_STATUS 1 // Ronly
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#define PWR_MGNT_STATUS_PDMS 0x40 // Power down support
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#define PWR_MGNT_STATUS_PSUS 0x20 // Power sustenance support
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#define PWR_MGNT_STATUS_POFS 0x10 // Power off support
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#define PWR_MGNT_STATUS_PDMR 0x04 // Power down mode ready
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#define PWR_MGNT_STATUS_PSUR 0x02 // Power sustenance request
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#define PWR_MGNT_STATUS_POFR 0x01 // Power off ready
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#define PWR_MGNT_SETTING 2 // R/W
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#define PWR_MGNT_SETTING_PDMN 0x04 // Power down mode notification
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#define PWR_MGNT_SETTING_PSUN 0x02 // Power sustenance notification
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#define PWR_MGNT_SETTING_POFN 0x01 // Power off notification
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// Performance Enhancement Function Register definitions
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#define PERF_ENH_REV 0 // Ronly
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#define PERF_ENH_EVT_SUP 1 // Ronly
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#define PERF_ENH_MAINT_SUP 2 // Ronly
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#define PERF_ENH_MAINT_URGENCY 3 // Ronly
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#define PERF_ENH_CACHE_SUP 4 // Ronly
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#define PERF_ENH_CACHE_SUPPORTED 0x1
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#define PERF_ENH_CQ_DEPTH 6 // Ronly
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#define PERF_ENH_TASK_STATUS 8 // 8 - 15 Ronly
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#define PERF_ENH_EVT_FX 257 // R/W
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#define PERF_ENH_EVT_FX_EN 0x1
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#define PERF_ENH_MAINT_TYP 258 // R/W
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#define PERF_ENH_MAINT_TYP_HOST_EN 0x2
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#define PERF_ENH_MAINT_CARD_EN 0x1
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#define PERF_ENH_MAINT 259 // R/W
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#define PERF_ENH_MAINT_HOST_START 0x1
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#define PERF_ENH_CACHE 260 // R/W
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#define PERF_ENH_CACHE_EN 0x01
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#define PERF_ENH_CACHE_FLUSH 261 // R/W
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#define PERF_ENH_CACHE_FLUSH_START 0x01
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#define PERF_ENH_CQ_EN 262 // R/W
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#endif
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#if defined(__QNXNTO__) && defined(__USESRCVERSION)
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#include <sys/srcversion.h>
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__SRCVERSION("$URL: http://svn.ott.qnx.com/product/hardware/branches/release/hardware/devb/sdmmc/sdiodi/include/sd.h $ $Rev: 953628 $")
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#endif
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