From 303ec5da3ba7e806720f255be57ce210f1a5188f Mon Sep 17 00:00:00 2001 From: forum_service Date: Mon, 18 Dec 2023 13:48:09 +0800 Subject: [PATCH] linux: version release v4.1.5 [flash]: add GSS01GSAK1/GSS02GSAK1 to support list [flash]: add FM25S01B/PY25Q64HA to support list [panel]: add new spi panel jd9853 Change-Id: Id52d6c3df02215564a4a923e63f973ad192610c9 --- .../drivers/mtd/nand/raw/cvitek/cvsnfc.c | 41 ++-- .../drivers/mtd/nand/raw/cvitek/cvsnfc.h | 2 +- .../mtd/nand/raw/cvitek/cvsnfc_spi_ids.c | 146 +++++++++++- .../drivers/mtd/spi-nor/cvitek_support_list.c | 10 + linux_5.10/drivers/staging/fbtft/Kconfig | 10 + linux_5.10/drivers/staging/fbtft/Makefile | 1 + linux_5.10/drivers/staging/fbtft/fb_jd9853.c | 208 ++++++++++++++++++ 7 files changed, 385 insertions(+), 33 deletions(-) create mode 100644 linux_5.10/drivers/staging/fbtft/fb_jd9853.c diff --git a/linux_5.10/drivers/mtd/nand/raw/cvitek/cvsnfc.c b/linux_5.10/drivers/mtd/nand/raw/cvitek/cvsnfc.c index a526a42b5..4e7c96e35 100644 --- a/linux_5.10/drivers/mtd/nand/raw/cvitek/cvsnfc.c +++ b/linux_5.10/drivers/mtd/nand/raw/cvitek/cvsnfc.c @@ -11,7 +11,7 @@ #include #include #include - +#include #include "cvsnfc_common.h" #include "cvsnfc_spi_ids.h" #include "cvsnfc.h" @@ -463,8 +463,10 @@ static void cvsnfc_cmd_ctrl(struct nand_chip *chip, int dat, unsigned int ctrl) static int cvsnfc_waitfunc(struct nand_chip *chip) { unsigned int regval; - unsigned int deadline = 0; struct cvsnfc_host *host = nand_get_controller_data(chip); + unsigned long start_time = jiffies; + /* 4ms */ + unsigned long max_erase_time = 4 * 3; pr_debug("=>%s\n", __func__); @@ -474,9 +476,7 @@ static int cvsnfc_waitfunc(struct nand_chip *chip) if (!(regval & STATUS_OIP_MASK)) return NAND_STATUS_READY; - udelay(1); - /* maybe need to sure */ - } while (deadline++ < (40 << 5)); + } while (jiffies_to_msecs(jiffies - start_time) < max_erase_time); pr_err("%s timeout.\n", __func__); @@ -487,15 +487,16 @@ static int cvsnfc_waitfunc(struct nand_chip *chip) static int cvsnfc_dev_ready(struct nand_chip *chip) { unsigned int regval; - unsigned int deadline = 0; struct cvsnfc_host *host = chip->priv; + unsigned long start_time = jiffies; + /* 4ms */ + unsigned long max_erase_time = 4 * 3; do { spi_feature_op(host, GET_OP, STATUS_ADDR, ®val); if (!(regval & STATUS_OIP_MASK)) return 1; - udelay(1); - } while (deadline++ < (40 << 5)); + } while (jiffies_to_msecs(jiffies - start_time) < max_erase_time); pr_err("%s timeout.\n", __func__); @@ -785,15 +786,15 @@ static int parse_status_info(struct cvsnfc_host *host) /* read SR */ spi_feature_op(host, GET_OP, ecc_info->ecc_sr_addr, &ecc_status0); - if (((ecc_status0 & 0x30) >> 4) == 0) - return 0; - - if (((ecc_status0 & 0x30) >> 4) == ecc_info->uncorr_val) - return -EBADMSG; - mask = GENMASK(ecc_info->ecc_bits - 1, 0); status = (ecc_status0 >> ecc_info->ecc_bit_shift) & mask; + if (status == 0) + return 0; + + if (status == ecc_info->uncorr_val) + return -EBADMSG; + if (ecc_info->ecc_sr_addr && !ecc_info->read_ecc_opcode && !ecc_info->ecc_mbf_addr) { if (ecc_info->remap) { corr_bit = ecc_info->remap[status] != 0xff ? ecc_info->remap[status] : 0; @@ -819,7 +820,7 @@ static int parse_status_info(struct cvsnfc_host *host) spi_nand_read_eccsr(host, ecc_info->read_ecc_opcode, &ecc_status0); corr_bit = (ecc_status0 >> ecc_info->ecc_bit_shift) & mask; } - pr_info("ECC CORR, correct bits %u\n", corr_bit); + //pr_info("ECC CORR, correct bits %u\n", corr_bit); return corr_bit; } @@ -871,15 +872,7 @@ RETRY_READ_CMD: } ret = parse_status_info(host); - if (ret < 0) { - mtd->ecc_stats.failed++; - pr_info("%s caddr 0x%x, r_raddr 0x%x, len %d\n", __func__, col_addr, r_col_addr, len); - } else { - mtd->ecc_stats.corrected += ret; - max_bitflips = max_t(unsigned int, max_bitflips, ret); - } - - return max_bitflips; + return ret; } __attribute__((unused)) diff --git a/linux_5.10/drivers/mtd/nand/raw/cvitek/cvsnfc.h b/linux_5.10/drivers/mtd/nand/raw/cvitek/cvsnfc.h index 712f38940..638a5dde3 100644 --- a/linux_5.10/drivers/mtd/nand/raw/cvitek/cvsnfc.h +++ b/linux_5.10/drivers/mtd/nand/raw/cvitek/cvsnfc.h @@ -495,7 +495,7 @@ struct nand_ecc_info { uint8_t ecc_bits; uint8_t ecc_bit_shift; uint8_t uncorr_val; - char *remap; + short *remap; }; struct spi_nand_driver { diff --git a/linux_5.10/drivers/mtd/nand/raw/cvitek/cvsnfc_spi_ids.c b/linux_5.10/drivers/mtd/nand/raw/cvitek/cvsnfc_spi_ids.c index 100fe4947..7668e6760 100644 --- a/linux_5.10/drivers/mtd/nand/raw/cvitek/cvsnfc_spi_ids.c +++ b/linux_5.10/drivers/mtd/nand/raw/cvitek/cvsnfc_spi_ids.c @@ -60,7 +60,7 @@ static struct spi_nand_driver spi_nand_driver_toshiba = { */ /* only for 8 bit threshold */ -char ECC_3bits_remap[8] = {0, 1, -1, 4, 0xff, 7, 0xff, 0xff }; +short ECC_3bits_remap[8] = {0, 1, -1, 4, 0xff, 7, 0xff, 0xff }; /* * ECCS1 ECCS0 Description @@ -70,7 +70,7 @@ char ECC_3bits_remap[8] = {0, 1, -1, 4, 0xff, 7, 0xff, 0xff }; * 1 1 Bit errors were detected and corrected,Bit errors count was equal * to the threshold bit count (8 bits) */ -char ECC_XT26G11C[4] = {0, 1, -1, 8}; +short ECC_XT26G11C[4] = {0, 1, -1, 8}; /* * ECCS1 ECCS0 Description @@ -79,7 +79,8 @@ char ECC_XT26G11C[4] = {0, 1, -1, 8}; * 1 0 More than 4-bit error and not corrected. * 1 1 Reserved */ -char ECC_2bits_remap[4] = {0, 1, -1, 0xff}; +short ECC_2bits_remap[4] = {0, 1, -1, 0xff}; +short ECC_1bits_remap[4] = {0, 1, -1, -1}; /* * ECCS1 ECCS0 ECCSE1 ECCSE0 Description @@ -93,11 +94,62 @@ char ECC_2bits_remap[4] = {0, 1, -1, 0xff}; * ECCS0-ECCS1 is located in field 4-5 of addr of 0xC0 * ECCSE0-ECCSE1 is located in field 4-5 of addr of 0xF0 */ -char ECC_GD_4bit_remap[16] = {0, 0, 0, 0, 1, 2, 3, 4, 0, 0, 0, 0, 0xff, 0xff, 0xff, 0xff}; -char ECC_GD_8bit_remap[16] = {0, 0, 0, 0, 4, 5, 6, 7, 0, 0, 0, 0, 8, 8, 8, 8}; -char ECC_HYF2G_remap[4] = {0, 1, -1, 14}; +short ECC_GD_4bit_remap[16] = {0, 0, 0, 0, 1, 2, 3, 4, 0, 0, 0, 0, 0xff, 0xff, 0xff, 0xff}; +short ECC_GD_8bit_remap[16] = {0, 0, 0, 0, 4, 5, 6, 7, 0, 0, 0, 0, 8, 8, 8, 8}; +short ECC_HYF2G_remap[4] = {0, 1, -1, 14}; struct cvsnfc_chip_info nand_flash_cvitek_supported_ids[] = { + { + { .name = "GSS01GSAK1", + .id = {0x52, 0xba, 0x13}, + .pagesize = SZ_2K, + .chipsize = SZ_128, + .erasesize = SZ_128K, + .options = 0, + .id_len = 3, + .oobsize = 64, + { .strength_ds = 4, + .step_ds = 512 + }, + }, + + { .ecc_sr_addr = 0xc0, + .ecc_mbf_addr = 0, + .read_ecc_opcode = 0, + .ecc_bits = 2, + .ecc_bit_shift = 4, + .uncorr_val = 0x2, + .remap = ECC_2bits_remap, + }, + .driver = &spi_nand_driver_general, + .flags = 0 + }, + + { + { .name = "GSS02GSAK1", + .id = {0x52, 0xba, 0x23}, + .pagesize = SZ_2K, + .chipsize = SZ_256, + .erasesize = SZ_128K, + .options = 0, + .id_len = 3, + .oobsize = 128, + { .strength_ds = 4, + .step_ds = 512 + }, + }, + + { .ecc_sr_addr = 0xc0, + .ecc_mbf_addr = 0, + .read_ecc_opcode = 0, + .ecc_bits = 2, + .ecc_bit_shift = 4, + .uncorr_val = 0x2, + .remap = ECC_2bits_remap, + }, + .driver = &spi_nand_driver_general, + .flags = 0 + }, { { .name = "F50L1G41LB", @@ -524,7 +576,7 @@ struct cvsnfc_chip_info nand_flash_cvitek_supported_ids[] = { .options = 0, .id_len = 2, .oobsize = SZ_64, - { .strength_ds = 8, + { .strength_ds = 4, .step_ds = SZ_512 }, }, @@ -535,7 +587,7 @@ struct cvsnfc_chip_info nand_flash_cvitek_supported_ids[] = { .ecc_bits = 2, .ecc_bit_shift = 4, .uncorr_val = 0x2, - .remap = ECC_GD_8bit_remap + .remap = ECC_GD_4bit_remap }, .driver = &spi_nand_driver_gd, .flags = 0 @@ -1220,6 +1272,84 @@ struct cvsnfc_chip_info nand_flash_cvitek_supported_ids[] = { .flags = 0 }, + { + { .name = "FM25S01A", + .id = {0xA1, 0xE4}, + .pagesize = SZ_2K, + .chipsize = SZ_128, + .erasesize = SZ_128K, + .options = 0, + .id_len = 2, + .oobsize = SZ_64, + { .strength_ds = 1, + .step_ds = SZ_512 + }, + }, + + { .ecc_sr_addr = 0xc0, + .ecc_mbf_addr = 0x0, + .read_ecc_opcode = 0, + .ecc_bits = 2, + .ecc_bit_shift = 4, + .uncorr_val = 0x2, + .remap = ECC_1bits_remap + }, + .driver = &spi_nand_driver_gd, + .flags = 0 + }, + + { + { .name = "FM25S02A", + .id = {0xA1, 0xE5}, + .pagesize = SZ_2K, + .chipsize = SZ_256, + .erasesize = SZ_128K, + .options = 0, + .id_len = 2, + .oobsize = SZ_64, + { .strength_ds = 1, + .step_ds = SZ_512 + }, + }, + + { .ecc_sr_addr = 0xc0, + .ecc_mbf_addr = 0x0, + .read_ecc_opcode = 0, + .ecc_bits = 2, + .ecc_bit_shift = 4, + .uncorr_val = 0x2, + .remap = ECC_1bits_remap + }, + .driver = &spi_nand_driver_gd, + .flags = 0 + }, + + { + { .name = "FM25S01B", + .id = {0xA1, 0xD4}, + .pagesize = SZ_2K, + .chipsize = SZ_128, + .erasesize = SZ_128K, + .options = 0, + .id_len = 2, + .oobsize = SZ_128, + { .strength_ds = 8, + .step_ds = SZ_512 + }, + }, + + { .ecc_sr_addr = 0xc0, + .ecc_mbf_addr = 0x0, + .read_ecc_opcode = 0, + .ecc_bits = 3, + .ecc_bit_shift = 4, + .uncorr_val = 0x2, + .remap = ECC_3bits_remap + }, + .driver = &spi_nand_driver_gd, + .flags = 0 + }, + { NULL } }; diff --git a/linux_5.10/drivers/mtd/spi-nor/cvitek_support_list.c b/linux_5.10/drivers/mtd/spi-nor/cvitek_support_list.c index 2dc7454af..e1bd3c682 100644 --- a/linux_5.10/drivers/mtd/spi-nor/cvitek_support_list.c +++ b/linux_5.10/drivers/mtd/spi-nor/cvitek_support_list.c @@ -78,6 +78,10 @@ static const struct flash_info cvitek_parts[] = { SPI_NOR_DUAL_READ | SPI_NOR_QUAD_OP | SECT_4K | SPI_NOR_4B_OPCODES) .fixups = &sr_bit1_qe_fixups }, + { "XM25QH256B", INFO(0x206019, 0x0, 64 * 1024, 512, + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_OP | SECT_4K | + SPI_NOR_4B_OPCODES) + .fixups = &sr1_bit6_qe_fixups }, { "MT25QL256A", INFO6(0x20ba19, 0x104400, 64 * 1024, 512, SECT_4K | USE_FSR | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_OP | SPI_NOR_4B_OPCODES | SPI_NOR_HAS_FIX_DUMMY) @@ -163,6 +167,9 @@ static const struct flash_info cvitek_parts[] = { { "FM25W128A", INFO(0xA12818, 0x0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_OP) .fixups = &sr_bit1_qe_fixups }, + { "BY25Q64ES", INFO(0x684017, 0x0, 64 * 1024, 128, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_OP) + .fixups = &sr_bit1_qe_fixups }, { "BY25Q128AS", INFO(0x684018, 0x0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_OP) .fixups = &sr_bit1_qe_fixups }, @@ -173,6 +180,9 @@ static const struct flash_info cvitek_parts[] = { { "PY25Q128HA", INFO(0x852018, 0x0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_OP) .fixups = &sr_bit1_qe_fixups }, + { "PY25Q64HA", INFO(0x852017, 0x0, 64 * 1024, 128, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_OP) + .fixups = &sr_bit1_qe_fixups }, { "P25Q64SH", INFO(0x856017, 0x0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_OP) .fixups = &sr_bit1_qe_fixups }, diff --git a/linux_5.10/drivers/staging/fbtft/Kconfig b/linux_5.10/drivers/staging/fbtft/Kconfig index dad1ddcd7..fa51de89e 100644 --- a/linux_5.10/drivers/staging/fbtft/Kconfig +++ b/linux_5.10/drivers/staging/fbtft/Kconfig @@ -88,6 +88,16 @@ config FB_TFT_ILI9486 help Generic Framebuffer support for ILI9486 +config FB_TFT_JD9853 + tristate "FB driver for the JD9853 LCD Controller" + depends on FB_TFT + help + This enables generic framebuffer support for the JADARD JD9853 + display controller. The controller is intended for small color + displays with a resolution of up to 240x320 pixels. + + Say Y if you have such a display that utilizes this controller. + config FB_TFT_PCD8544 tristate "FB driver for the PCD8544 LCD Controller" depends on FB_TFT diff --git a/linux_5.10/drivers/staging/fbtft/Makefile b/linux_5.10/drivers/staging/fbtft/Makefile index e87193f7d..aff25cae8 100644 --- a/linux_5.10/drivers/staging/fbtft/Makefile +++ b/linux_5.10/drivers/staging/fbtft/Makefile @@ -17,6 +17,7 @@ obj-$(CONFIG_FB_TFT_ILI9340) += fb_ili9340.o obj-$(CONFIG_FB_TFT_ILI9341) += fb_ili9341.o obj-$(CONFIG_FB_TFT_ILI9481) += fb_ili9481.o obj-$(CONFIG_FB_TFT_ILI9486) += fb_ili9486.o +obj-$(CONFIG_FB_TFT_JD9853) += fb_jd9853.o obj-$(CONFIG_FB_TFT_PCD8544) += fb_pcd8544.o obj-$(CONFIG_FB_TFT_RA8875) += fb_ra8875.o obj-$(CONFIG_FB_TFT_S6D02A1) += fb_s6d02a1.o diff --git a/linux_5.10/drivers/staging/fbtft/fb_jd9853.c b/linux_5.10/drivers/staging/fbtft/fb_jd9853.c new file mode 100644 index 000000000..f57f0df20 --- /dev/null +++ b/linux_5.10/drivers/staging/fbtft/fb_jd9853.c @@ -0,0 +1,208 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * FB driver for the JD9853 LCD display controller + * + * This display uses 9-bit SPI: Data/Command bit + 8 data bits + * For platforms that doesn't support 9-bit, the driver is capable + * of emulating this using 8-bit transfer. + * This is done by transferring eight 9-bit words in 9 bytes. + * + * Copyright (C) 2013 Christian Vogelgsang + * Based on adafruit22fb.c by Noralf Tronnes + */ + +#include +#include +#include +#include +#include