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[uboot] porting cvitek asic chips:

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1. add cvitek folders to u-boot-2021.10
	2. add cv183x/cv182x part
	3. add cv181x/cv180x part

Change-Id: I6dc2e5ff509dbab16bd60bfb3fd61852da5e01f6
This commit is contained in:
sam.xiang
2023-02-22 13:43:23 +08:00
parent f8fc109960
commit 3a4bcfca2f
244 changed files with 41355 additions and 1273 deletions
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33
u-boot-2021.10/drivers/video/cvitek/dsi_phy.h Normal file
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/*
* Copyright (C) Cvitek Co., Ltd. 2019-2020. All rights reserved.
*
*/
#ifndef _CVI_DSI_PHY_H_
#define _CVI_DSI_PHY_H_
#include "scaler.h"
enum lane_id {
DSI_LANE_CLK = 0,
DSI_LANE_0,
DSI_LANE_1,
DSI_LANE_2,
DSI_LANE_3,
DSI_LANE_MAX,
};
void dphy_set_base_addr(void *base);
void dphy_dsi_lane_en(bool clk_en, bool *data_en, bool preamble_en);
int dphy_dsi_set_lane(u8 lane_num, enum lane_id lane, bool pn_swap);
void dphy_init(enum sclr_vo_intf intf);
void dphy_dsi_set_pll(u32 clkkHz, u8 lane, u8 bits);
void dphy_lvds_enable(bool en);
void dphy_lvds_set_pll(u32 clkkHz, u8 link);
void dpyh_mipi_tx_manual_packet(const u8 *data, u8 count);
void dphy_set_hs_settle(u8 prepare, u8 zero, u8 trail);
void dphy_get_hs_settle(u8 *prepare, u8 *zero, u8 *trail);
#endif // _CVI_DSI_PHY_H