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[uboot] Upgrade the MMF SDK from V4.0.0 to V4.1.0

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1. add cv181x functions
	2. Delete some useless files and add .gitignore

Change-Id: Iea2b2fa43b5a1152e5e99fb32b88f8d2c249251a
This commit is contained in:
wangliang.wang
2023-03-10 00:31:09 +08:00
committed by sam.xiang
parent aa1b345a00
commit 607778300c
102 changed files with 11818 additions and 1862 deletions
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29
u-boot-2021.10/drivers/video/cvitek/scaler.c
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@ -1,5 +1,5 @@
#include <common.h>
#include <linux/delay.h>
#include "vip_common.h"
#include "scaler.h"
#include "scaler_reg.h"
@ -754,7 +754,7 @@ void sclr_disp_set_pattern(enum sclr_disp_pat_type type,
break;
}
default:
debug("%s - unacceptiable pattern-type(%d)\n", __func__, type);
printf("%s - unacceptiable pattern-type(%d)\n", __func__, type);
break;
}
}
@ -1074,7 +1074,7 @@ int sclr_dsi_long_packet_raw(const u8 *data, u8 count)
u8 i = 0;
if ((count > SCL_MAX_DSI_LP) || (count == 0)) {
debug("%s: count(%d) invalid\n", __func__, count);
printf("%s: count(%d) invalid\n", __func__, count);
return -1;
}
@ -1172,20 +1172,20 @@ int sclr_dsi_short_packet(u8 di, const u8 *data, u8 count, bool sw_mode)
int sclr_dsi_dcs_write_buffer(u8 di, const void *data, size_t len, bool sw_mode)
{
if (len == 0) {
debug("[cvi_mipi_tx] %s: 0 param unacceptable.\n", __func__);
printf("[cvi_mipi_tx] %s: 0 param unacceptable.\n", __func__);
return -1;
}
if ((di == 0x06) || (di == 0x05) || (di == 0x04) || (di == 0x03)) {
if (len != 1) {
debug("[cvi_mipi_tx] %s: cmd(0x%02x) should has 1 param.\n", __func__, di);
printf("[cvi_mipi_tx] %s: cmd(0x%02x) should has 1 param.\n", __func__, di);
return -1;
}
return sclr_dsi_short_packet(di, data, len, sw_mode);
}
if ((di == 0x15) || (di == 0x37) || (di == 0x13) || (di == 0x14)) {
if (len != 2) {
debug("[cvi_mipi_tx] %s: cmd(0x%02x) should has 2 param.\n", __func__, di);
printf("[cvi_mipi_tx] %s: cmd(0x%02x) should has 2 param.\n", __func__, di);
return -1;
}
return sclr_dsi_short_packet(di, data, len, sw_mode);
@ -1214,11 +1214,12 @@ int sclr_dsi_dcs_read_buffer(u8 di, const u16 data_param, u8 *data, size_t len,
len = 4;
if (sclr_dsi_get_mode() == SCLR_DSI_MODE_HS) {
debug("[cvi_mipi_tx] %s: not work in HS.\n", __func__);
printf("[cvi_mipi_tx] %s: not work in HS.\n", __func__);
return -1;
}
_reg_write(reg_base + REG_SCL_DSI_ESC, 0x04);
// only set necessery bits
_reg_write_mask(reg_base + REG_SCL_DSI_ESC, 0x07, 0x04);
// send read cmd
sclr_dsi_short_packet(di, (u8 *)&data_param, 2, sw_mode);
@ -1230,7 +1231,7 @@ int sclr_dsi_dcs_read_buffer(u8 di, const u16 data_param, u8 *data, size_t len,
if (ret == 0) {
sclr_dsi_clr_mode();
} else {
debug("[cvi_mipi_tx] %s: BTA error.\n", __func__);
printf("[cvi_mipi_tx] %s: BTA error.\n", __func__);
return ret;
}
@ -1253,12 +1254,12 @@ int sclr_dsi_dcs_read_buffer(u8 di, const u16 data_param, u8 *data, size_t len,
data[i] = (rx_data >> (i * 8)) & 0xff;
break;
case ACK_WR:
debug("[cvi_mipi_tx] %s: dcs read, ack with error(%#x %#x).\n"
printf("[cvi_mipi_tx] %s: dcs read, ack with error(%#x %#x).\n"
, __func__, (rx_data >> 8) & 0xff, (rx_data >> 16) & 0xff);
ret = -1;
break;
default:
debug("[cvi_mipi_tx] %s: unknown DT, %#x.", __func__, rx_data);
printf("[cvi_mipi_tx] %s: unknown DT, %#x.", __func__, rx_data);
ret = -1;
break;
}
@ -1280,7 +1281,7 @@ int sclr_dsi_config(u8 lane_num, enum sclr_dsi_fmt fmt, u16 width)
lane_num >>= 1;
val = (fmt << 30) | (lane_num << 24);
_reg_write_mask(reg_base + REG_SCL_DSI_HS_0, 0xc3000000, val);
val = (width / 6) << 16 | ((width * bit_depth[fmt] + 7) >> 3);
val = (width / 10) << 16 | ((width * bit_depth[fmt] + 7) >> 3);
_reg_write(reg_base + REG_SCL_DSI_HS_1, val);
return 0;
@ -1311,7 +1312,7 @@ void sclr_i80_packet(u32 cmd)
} while (++cnt < 10);
if (cnt == 10)
debug("[cvi_vip] %s: cmd(%#x) not ready.\n", __func__, cmd);
printf("[cvi_vip] %s: cmd(%#x) not ready.\n", __func__, cmd);
}
void sclr_i80_run(void)
@ -1327,7 +1328,7 @@ void sclr_i80_run(void)
} while (++cnt < 10);
if (cnt == 10) {
debug("[cvi_vip] %s: not finish. sw clear it.\n", __func__);
printf("[cvi_vip] %s: not finish. sw clear it.\n", __func__);
_reg_write_mask(reg_base + REG_SCL_DISP_MCU_IF_CTRL, BIT(10), BIT(10));
}
}