Merge branch 'Branch_Gaoyang3513' of https://gaoyang3513.synology.me:3000/gaoyang3513/MilkV-Duo into Branch_Gaoyang3513

[详细说明]
    1.使用dts方式，Pstore工作正常；模块加载方式未通过(dts中未声明reserver-memory)；
    2.resever-memory定义：DRAM 末尾3MB位置开始,大小1MB(RTOS区域紧跟其后)：{0x9fd0_0000, 0x9fdf_ffff};

.gitignore

@@ -20,3 +20,7 @@ ncscope.*
 
 __pycache__
 .vscode
+
+.cache/
+compile_commands.json
+

build/boards/cv181x/cv1813h_milkv_duos_sd/linux/cvitek_cv1813h_milkv_duos_sd_defconfig

@@ -530,3 +530,22 @@ CONFIG_BT_HCIUART_H4=y
 # CONFIG_BT_HCIVHCI is not set
 # CONFIG_BT_MRVL is not set
 # CONFIG_BT_MTKSDIO is not set
+
+# 死锁检测
+CONFIG_LOCK_STAT=y
+CONFIG_PROVE_LOCKING=y
+
+# Ftracer
+CONFIG_FUNCTION_TRACER=y
+CONFIG_PSTORE_FTRACE=y
+
+# Sysrq
+CONFIG_MAGIC_SYSRQ=y
+
+# Pstore
+CONFIG_PSTORE=y
+#	Frontend
+CONFIG_PSTORE_PMSG=y
+CONFIG_PSTORE_CONSOLE=y
+#	Backend
+CONFIG_PSTORE_RAM=y

build/boards/default/dts/cv181x/cv181x_default_memmap.dtsi

@@ -21,5 +21,12 @@
 			compatible = "ion-region";
 			size = <0x0 CVIMMAP_ION_SIZE>;
 		};
+
+		ramoops@9fd00000 {
+			compatible = "ramoops";
+			reg = <0 0x9fd00000 0 0x100000>;
+			record-size = <0x4000>;
+			console-size = <0x4000>;
+		};
 	};
 };

buildroot-2021.05/package/skeleton-init-sysv/skeleton/etc/fstab

@@ -7,3 +7,4 @@ tmpfs		/tmp			tmpfs	mode=1777				0	0
 tmpfs		/run			tmpfs	mode=0755,nosuid,nodev			0	0
 sysfs		/sys			sysfs	defaults				0	0
 debug		/sys/kernel/debug	debugfs	defaults				0	0
+pstore		/sys/fs/pstore		pstore	defaults				0	0

fsbl/.gitignore

@@ -1,6 +1 @@
-*.d
-fip.bin
-build_message.o
-blmacros.dis
-build/cvi_board_memmap.h
 build/

fsbl/Makefile

@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
 .PHONY: FORCE
 # Default goal is build all images
 .DEFAULT_GOAL := all

fsbl/include/cpu/aarch64/bl2_helper.h

@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+
 #ifndef __BL2_HELPER_H__
 #define __BL2_HELPER_H__
 

fsbl/include/cpu/aarch64/cpu_helper.h

@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+
 #ifndef __CPU_HELP_H__
 #define __CPU_HELP_H__
 

fsbl/include/cpu/cpu.h

@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+
 #ifndef __CPU_H__
 #define __CPU_H__
 

fsbl/include/cpu/riscv/arch_helpers.h

@@ -1,6 +1,8 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+
 #ifndef __ARCH_HELPERS_H__
 #define __ARCH_HELPERS_H__
-//#include <cpu.h>    /* for additional register definitions */
+
 #include <cdefs.h>  /* For __dead2 */
 #include <stdint.h>
 #include <sys/types.h>

fsbl/include/cpu/riscv/cpu_helper.h

@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+
 #ifndef __CPU_HELP_H__
 #define __CPU_HELP_H__
 

fsbl/lib/cpu/aarch64/bl2_helper.c

@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: BSD-3-Clause
+
 #include <debug.h>
 #include <console.h>
 #include <platform.h>

fsbl/lib/cpu/aarch64/cpu.mk

@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
 include lib/cpu/${BOOT_CPU}/cpu-ops.mk
 
 ASFLAGS +=\

fsbl/lib/cpu/aarch64/cpu_helper.c

@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: BSD-3-Clause
+
 #include <mmio.h>
 #include <debug.h>
 #include <assert.h>

fsbl/lib/cpu/riscv/bits.h

@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+
 #ifndef _RISCV_BITS_H
 #define _RISCV_BITS_H
 

fsbl/lib/cpu/riscv/bl1_entrypoint.S

@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+
 #include "bits.h"
 #include "csr.h"
 #include <platform.h>

fsbl/lib/cpu/riscv/bl2_entrypoint.S

@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+
 #include "bits.h"
 #include "csr.h"
 #include <riscv/asm_macros.S>

fsbl/lib/cpu/riscv/bl2_helper.c

@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: BSD-3-Clause
+
 #include <debug.h>
 #include <console.h>
 #include <platform.h>

fsbl/lib/cpu/riscv/cache.c

@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: BSD-3-Clause
+
 #include <platform.h>
 #include <arch_helpers.h>
 

fsbl/lib/cpu/riscv/cpu.mk

@@ -1,4 +1,4 @@
-#include lib/cpu/${BOOT_CPU}/cpu-ops.mk
+# SPDX-License-Identifier: BSD-3-Clause
 
 ASFLAGS +=\
 	$(CPPFLAGS) \
@@ -38,9 +38,7 @@ CPU_SOURCES := \
 
 
 BL1_CPU_SOURCES := \
-	lib/cpu/${BOOT_CPU}/bl1_entrypoint.S \
-#	lib/cpu/${BOOT_CPU}/bl1_exceptions.S
+	lib/cpu/${BOOT_CPU}/bl1_entrypoint.S
 
 BL2_CPU_SOURCES := \
-	lib/cpu/${BOOT_CPU}/bl2_entrypoint.S \
-#	lib/cpu/${BOOT_CPU}/bl2_exceptions.S
+	lib/cpu/${BOOT_CPU}/bl2_entrypoint.S

fsbl/lib/cpu/riscv/cpu_helper.c

@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: BSD-3-Clause
+
 #include <mmio.h>
 #include <debug.h>
 #include <assert.h>

fsbl/lib/cpu/riscv/csr.h

@@ -1,4 +1,4 @@
-// See LICENSE for license details.
+/* SPDX-License-Identifier: BSD-3-Clause */
 
 #ifndef RISCV_CSR_ENCODING_H
 #define RISCV_CSR_ENCODING_H

fsbl/lib/cpu/riscv/misc_helpers.c

@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: BSD-3-Clause
+
 #include <string.h>
 
 void *memcpy16(void *dest, const void *src, size_t length)

fsbl/lib/stdlib/misc.c

@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: BSD-3-Clause
+
 #include <stdint.h>
 #include <ctype.h>
 #include <string.h>

fsbl/lib/utils/decompress.c

@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: BSD-3-Clause
+
 #include <debug.h>
 #include <errno.h>
 #include <string.h>
@@ -119,9 +121,6 @@ int decompress_lz4(void *dst, size_t *dst_size, const void *src, size_t src_size
 		return -1;
 	}
 
-	// No need to free.
-	// LZ4F_freeDecompressionContext(dctx);
-
 	return 0;
 }
 

fsbl/lib/utils/decompress.h

@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+
 #ifndef __DECOMPRESS_H__
 #define __DECOMPRESS_H__
 

fsbl/make_helpers/fip.mk

@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
 BLCP_PATH = ../fast_image_mcu/riscv/output/fast_image_mcu.bin
 ifeq ("$(wildcard $(BLCP_PATH))","")
 BLCP_PATH = test/empty.bin
@@ -16,7 +18,7 @@ fip%: export BLCP_IMG_RUNADDR=0x05200200
 fip%: export BLCP_PARAM_LOADADDR=0
 fip%: export NAND_INFO=00000000
 fip%: export NOR_INFO=$(shell printf '%72s' | tr ' ' 'FF')
-fip%: export DDR_PARAM_TEST_PATH = test/cv181x/ddr_param.bin
+fip%: export DDR_PARAM_TEST_PATH = test/sophon/ddr_param.bin
 
 ${BUILD_PLAT}:
 	@mkdir -p '${BUILD_PLAT}'

fsbl/make_helpers/get_macros.ld.S

@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+
 #include <platform.h>
 #include <cdefs.h>
 

fsbl/make_helpers/get_rsa_n.py

@@ -1,4 +1,5 @@
 #!/usr/bin/env python3
+# SPDX-License-Identifier: BSD-3-Clause
 # PYTHON_ARGCOMPLETE_OK
 
 import sys

fsbl/plat/cv180x/bl2/bl2_main.c

@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: BSD-3-Clause
+
 #include <debug.h>
 #include <console.h>
 #include <platform.h>
@@ -5,6 +7,10 @@
 #include <string.h>
 #include <delay_timer.h>
 
+#define UART_DLL 0x04140000
+#define UART_DLH 0x04140004
+#define UART_LCR 0x0414000C
+
 #ifdef RTOS_ENABLE_FREERTOS
 int init_comm_info(int ret)
 {
@@ -46,11 +52,6 @@ int dec_verify_image(const void *image, size_t size, size_t dec_skip, struct fip
 }
 #endif
 
-// Start of addition
-#define UART_DLL 0x04140000
-#define UART_DLH 0x04140004
-#define UART_LCR 0x0414000C
-
 void set_baudrate()
 {
 	// 14 for 115200, 13 for 128000
@@ -66,13 +67,10 @@ void set_baudrate()
 	// set DLAB back to 0
 	*(volatile uint32_t*)(UART_LCR) &= (uint32_t)(~0x80);
 }
-// End of addition
 
 void bl2_main(void)
 {
-	// Start of addition
 	set_baudrate();
-	// End of addition
 
 	ATF_STATE = ATF_STATE_BL2_MAIN;
 	time_records->fsbl_start = read_time_ms();
@@ -85,7 +83,6 @@ void bl2_main(void)
 
 	INFO("CP_STATE_REG=0x%x\n", mmio_read_32(0x0E000018));
 
-	// print_sram_log();
 	lock_efuse_chipsn();
 
 	setup_dl_flag();

fsbl/plat/cv180x/bl2/bl2_opt.c

@@ -0,0 +1,536 @@
+/*
+ * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <debug.h>
+#include <bitwise_ops.h>
+#include <console.h>
+#include <platform.h>
+#include <rom_api.h>
+#include <bl2.h>
+#include <ddr.h>
+#include <string.h>
+#include <decompress.h>
+#include <delay_timer.h>
+#include <security/security.h>
+#include <cv_usb.h>
+
+struct _time_records *time_records = (void *)TIME_RECORDS_ADDR;
+struct fip_param1 *fip_param1 = (void *)PARAM1_BASE;
+static struct fip_param2 fip_param2 __aligned(BLOCK_SIZE);
+static union {
+	struct ddr_param ddr_param;
+	struct loader_2nd_header loader_2nd_header;
+	uint8_t buf[BLOCK_SIZE];
+} sram_union_buf __aligned(BLOCK_SIZE);
+
+int init_comm_info(int ret) __attribute__((weak));
+int init_comm_info(int ret)
+{
+	return ret;
+}
+
+void print_sram_log(void)
+{
+	uint32_t *const log_size = (void *)BOOT_LOG_LEN_ADDR;
+	uint8_t *const log_buf = (void *)phys_to_dma(BOOT_LOG_BUF_BASE);
+	uint32_t i;
+
+	static const char m1[] = "\nSRAM Log: ========================================\n";
+	static const char m2[] = "\nSRAM Log end: ====================================\n";
+
+	for (i = 0; m1[i]; i++)
+		console_putc(m1[i]);
+
+	for (i = 0; i < *log_size; i++)
+		console_putc(log_buf[i]);
+
+	for (i = 0; m2[i]; i++)
+		console_putc(m2[i]);
+}
+
+void lock_efuse_chipsn(void)
+{
+	int value = mmio_read_32(EFUSE_W_LOCK0_REG);
+
+	if (efuse_power_on()) {
+		NOTICE("efuse power on fail\n");
+		return;
+	}
+
+	if ((value & (0x1 << BIT_FTSN3_LOCK)) == 0)
+		efuse_program_bit(0x26, BIT_FTSN3_LOCK);
+
+	if ((value & (0x1 << BIT_FTSN4_LOCK)) == 0)
+		efuse_program_bit(0x26, BIT_FTSN4_LOCK);
+
+	if (efuse_refresh_shadow()) {
+		NOTICE("efuse refresh shadow fail\n");
+		return;
+	}
+
+	value = mmio_read_32(EFUSE_W_LOCK0_REG);
+	if (((value & (0x3 << BIT_FTSN3_LOCK)) >> BIT_FTSN3_LOCK) !=  0x3)
+		NOTICE("lock efuse chipsn fail\n");
+
+	if (efuse_power_off()) {
+		NOTICE("efuse power off fail\n");
+		return;
+	}
+}
+
+#ifdef USB_DL_BY_FSBL
+int load_image_by_usb(void *buf, uint32_t offset, size_t image_size, int retry_num)
+{
+
+	int ret = -1;
+
+	if (usb_polling(buf, offset, image_size) == CV_USB_DL)
+		ret = 0;
+	else
+		ret = -2;
+
+	INFO("LIE/%d/%p/0x%x/%lu.\n", ret, buf, offset, image_size);
+
+	return ret;
+}
+#endif
+
+int load_param2(int retry)
+{
+	uint32_t crc;
+	int ret = -1;
+
+	NOTICE("P2S/0x%lx/%p.\n", sizeof(fip_param2), &fip_param2);
+
+#ifdef USB_DL_BY_FSBL
+	if (p_rom_api_get_boot_src() == BOOT_SRC_USB)
+		ret = load_image_by_usb(&fip_param2, fip_param1->param2_loadaddr, PARAM2_SIZE, retry);
+	else
+#endif
+		ret = p_rom_api_load_image(&fip_param2, fip_param1->param2_loadaddr, PARAM2_SIZE, retry);
+
+	if (ret < 0) {
+		return ret;
+	}
+
+	if (fip_param2.magic1 != FIP_PARAM2_MAGIC1) {
+		WARN("LP2_NOMAGIC\n");
+		return -1;
+	}
+
+	crc = p_rom_api_image_crc(&fip_param2.reserved1, sizeof(fip_param2) - 12);
+	if (crc != fip_param2.param2_cksum) {
+		ERROR("param2_cksum (0x%x/0x%x)\n", crc, fip_param2.param2_cksum);
+		return -1;
+	}
+
+	NOTICE("P2E.\n");
+
+	return 0;
+}
+
+int load_ddr_param(int retry)
+{
+	uint32_t crc;
+	int ret = -1;
+
+	NOTICE("DPS/0x%x/0x%x.\n", fip_param2.ddr_param_loadaddr, fip_param2.ddr_param_size);
+
+	if (fip_param2.ddr_param_size >= sizeof(sram_union_buf.ddr_param))
+		fip_param2.ddr_param_size = sizeof(sram_union_buf.ddr_param);
+
+#ifdef USB_DL_BY_FSBL
+	if (p_rom_api_get_boot_src() == BOOT_SRC_USB)
+		ret = load_image_by_usb(&sram_union_buf.ddr_param, fip_param2.ddr_param_loadaddr,
+		fip_param2.ddr_param_size,  retry);
+	else
+#endif
+		ret = p_rom_api_load_image(&sram_union_buf.ddr_param, fip_param2.ddr_param_loadaddr,
+		fip_param2.ddr_param_size, retry);
+	if (ret < 0) {
+		return ret;
+	}
+
+	crc = p_rom_api_image_crc(&sram_union_buf.ddr_param, fip_param2.ddr_param_size);
+	if (crc != fip_param2.ddr_param_cksum) {
+		ERROR("ddr_param_cksum (0x%x/0x%x)\n", crc, fip_param2.ddr_param_cksum);
+		return -1;
+	}
+
+	NOTICE("DPE.\n");
+
+	return 0;
+}
+
+int load_ddr(void)
+{
+	int retry = 0;
+
+retry_from_flash:
+	for (retry = 0; retry < p_rom_api_get_number_of_retries(); retry++) {
+		if (load_param2(retry) < 0)
+			continue;
+		if (load_ddr_param(retry) < 0)
+			continue;
+
+		break;
+	}
+
+	if (retry >= p_rom_api_get_number_of_retries()) {
+		switch (p_rom_api_get_boot_src()) {
+		case BOOT_SRC_UART:
+		case BOOT_SRC_SD:
+		case BOOT_SRC_USB:
+			WARN("DL cancelled. Load flash. (%d).\n", retry);
+			// Continue to boot from flash if boot from external source
+			p_rom_api_flash_init();
+			goto retry_from_flash;
+		default:
+			ERROR("Failed to load DDR param (%d).\n", retry);
+			panic_handler();
+		}
+	}
+
+	time_records->ddr_init_start = read_time_ms();
+	ddr_init(&sram_union_buf.ddr_param);
+	time_records->ddr_init_end = read_time_ms();
+
+	return 0;
+}
+
+int load_blcp_2nd(int retry)
+{
+	uint32_t crc, rtos_base;
+	int ret = -1;
+
+	// if no blcp_2nd, release_blcp_2nd should be ddr_init_end
+	time_records->release_blcp_2nd = time_records->ddr_init_end;
+
+	NOTICE("C2S/0x%x/0x%x/0x%x.\n", fip_param2.blcp_2nd_loadaddr, fip_param2.blcp_2nd_runaddr,
+	       fip_param2.blcp_2nd_size);
+
+	if (!fip_param2.blcp_2nd_runaddr) {
+		NOTICE("No C906L image.\n");
+		return 0;
+	}
+
+	if (!IN_RANGE(fip_param2.blcp_2nd_runaddr, DRAM_BASE, DRAM_SIZE)) {
+		ERROR("blcp_2nd_runaddr (0x%x) is not in DRAM.\n", fip_param2.blcp_2nd_runaddr);
+		panic_handler();
+	}
+
+	if (!IN_RANGE(fip_param2.blcp_2nd_runaddr + fip_param2.blcp_2nd_size, DRAM_BASE, DRAM_SIZE)) {
+		ERROR("blcp_2nd_size (0x%x) is not in DRAM.\n", fip_param2.blcp_2nd_size);
+		panic_handler();
+	}
+
+#ifdef USB_DL_BY_FSBL
+	if (p_rom_api_get_boot_src() == BOOT_SRC_USB)
+		ret = load_image_by_usb((void *)(uintptr_t)fip_param2.blcp_2nd_runaddr, fip_param2.blcp_2nd_loadaddr,
+					fip_param2.blcp_2nd_size, retry);
+	else
+#endif
+		ret = p_rom_api_load_image((void *)(uintptr_t)fip_param2.blcp_2nd_runaddr, fip_param2.blcp_2nd_loadaddr,
+					fip_param2.blcp_2nd_size, retry);
+	if (ret < 0) {
+		return ret;
+	}
+
+	crc = p_rom_api_image_crc((void *)(uintptr_t)fip_param2.blcp_2nd_runaddr, fip_param2.blcp_2nd_size);
+	if (crc != fip_param2.blcp_2nd_cksum) {
+		ERROR("blcp_2nd_cksum (0x%x/0x%x)\n", crc, fip_param2.blcp_2nd_cksum);
+		return -1;
+	}
+
+	ret = dec_verify_image((void *)(uintptr_t)fip_param2.blcp_2nd_runaddr, fip_param2.blcp_2nd_size, 0, fip_param1);
+	if (ret < 0) {
+		ERROR("verify blcp 2nd (%d)\n", ret);
+		return ret;
+	}
+
+	flush_dcache_range(fip_param2.blcp_2nd_runaddr, fip_param2.blcp_2nd_size);
+
+	rtos_base = mmio_read_32(AXI_SRAM_RTOS_BASE);
+	init_comm_info(0);
+
+	time_records->release_blcp_2nd = read_time_ms();
+	if (rtos_base == CVI_RTOS_MAGIC_CODE) {
+		mmio_write_32(AXI_SRAM_RTOS_BASE, fip_param2.blcp_2nd_runaddr);
+	} else {
+		reset_c906l(fip_param2.blcp_2nd_runaddr);
+	}
+
+	NOTICE("C2E.\n");
+
+	return 0;
+}
+
+int load_monitor(int retry, uint64_t *monitor_entry)
+{
+	uint32_t crc;
+	int ret = -1;
+
+	NOTICE("MS/0x%x/0x%x/0x%x.\n", fip_param2.monitor_loadaddr, fip_param2.monitor_runaddr,
+	       fip_param2.monitor_size);
+
+	if (!fip_param2.monitor_runaddr) {
+		NOTICE("No monitor.\n");
+		return 0;
+	}
+
+	if (!IN_RANGE(fip_param2.monitor_runaddr, DRAM_BASE, DRAM_SIZE)) {
+		ERROR("monitor_runaddr (0x%x) is not in DRAM.\n", fip_param2.monitor_runaddr);
+		panic_handler();
+	}
+
+	if (!IN_RANGE(fip_param2.monitor_runaddr + fip_param2.monitor_size, DRAM_BASE, DRAM_SIZE)) {
+		ERROR("monitor_size (0x%x) is not in DRAM.\n", fip_param2.monitor_size);
+		panic_handler();
+	}
+
+#ifdef USB_DL_BY_FSBL
+	if (p_rom_api_get_boot_src() == BOOT_SRC_USB)
+		ret = load_image_by_usb((void *)(uintptr_t)fip_param2.monitor_runaddr, fip_param2.monitor_loadaddr,
+					fip_param2.monitor_size, retry);
+	else
+#endif
+		ret = p_rom_api_load_image((void *)(uintptr_t)fip_param2.monitor_runaddr, fip_param2.monitor_loadaddr,
+					fip_param2.monitor_size, retry);
+	if (ret < 0) {
+		return ret;
+	}
+
+	crc = p_rom_api_image_crc((void *)(uintptr_t)fip_param2.monitor_runaddr, fip_param2.monitor_size);
+	if (crc != fip_param2.monitor_cksum) {
+		ERROR("monitor_cksum (0x%x/0x%x)\n", crc, fip_param2.monitor_cksum);
+		return -1;
+	}
+
+	ret = dec_verify_image((void *)(uintptr_t)fip_param2.monitor_runaddr, fip_param2.monitor_size, 0, fip_param1);
+	if (ret < 0) {
+		ERROR("verify monitor (%d)\n", ret);
+		return ret;
+	}
+
+	flush_dcache_range(fip_param2.monitor_runaddr, fip_param2.monitor_size);
+	NOTICE("ME.\n");
+
+	*monitor_entry = fip_param2.monitor_runaddr;
+
+	return 0;
+}
+
+int load_loader_2nd(int retry, uint64_t *loader_2nd_entry)
+{
+	struct loader_2nd_header *loader_2nd_header = &sram_union_buf.loader_2nd_header;
+	uint32_t crc;
+	int ret = -1;
+	const int cksum_offset =
+		offsetof(struct loader_2nd_header, cksum) + sizeof(((struct loader_2nd_header *)0)->cksum);
+
+	enum COMPRESS_TYPE comp_type = COMP_NONE;
+	int reading_size;
+	void *image_buf;
+
+	NOTICE("L2/0x%x.\n", fip_param2.loader_2nd_loadaddr);
+
+#ifdef USB_DL_BY_FSBL
+	if (p_rom_api_get_boot_src() == BOOT_SRC_USB)
+		ret = load_image_by_usb(loader_2nd_header, fip_param2.loader_2nd_loadaddr, BLOCK_SIZE, retry);
+	else
+#endif
+		ret = p_rom_api_load_image(loader_2nd_header, fip_param2.loader_2nd_loadaddr, BLOCK_SIZE, retry);
+	if (ret < 0) {
+		return -1;
+	}
+
+	reading_size = ROUND_UP(loader_2nd_header->size, BLOCK_SIZE);
+
+	NOTICE("L2/0x%x/0x%x/0x%lx/0x%x/0x%x\n", loader_2nd_header->magic, loader_2nd_header->cksum,
+	       loader_2nd_header->runaddr, loader_2nd_header->size, reading_size);
+
+	switch (loader_2nd_header->magic) {
+	case LOADER_2ND_MAGIC_LZMA:
+		comp_type = COMP_LZMA;
+		break;
+	case LOADER_2ND_MAGIC_LZ4:
+		comp_type = COMP_LZ4;
+		break;
+	default:
+		comp_type = COMP_NONE;
+		break;
+	}
+
+	if (comp_type) {
+		NOTICE("COMP/%d.\n", comp_type);
+		image_buf = (void *)DECOMP_BUF_ADDR;
+	} else {
+		image_buf = (void *)loader_2nd_header->runaddr;
+	}
+
+#ifdef USB_DL_BY_FSBL
+	if (p_rom_api_get_boot_src() == BOOT_SRC_USB)
+		ret = load_image_by_usb(image_buf, fip_param2.loader_2nd_loadaddr, reading_size, retry);
+	else
+#endif
+		ret = p_rom_api_load_image(image_buf, fip_param2.loader_2nd_loadaddr, reading_size, retry);
+	if (ret < 0) {
+		return -1;
+	}
+
+	crc = p_rom_api_image_crc(image_buf + cksum_offset, loader_2nd_header->size - cksum_offset);
+	if (crc != loader_2nd_header->cksum) {
+		ERROR("loader_2nd_cksum (0x%x/0x%x)\n", crc, loader_2nd_header->cksum);
+		return -1;
+	}
+
+	ret = dec_verify_image(image_buf + cksum_offset, loader_2nd_header->size - cksum_offset,
+			       sizeof(struct loader_2nd_header) - cksum_offset, fip_param1);
+	if (ret < 0) {
+		ERROR("verify loader 2nd (%d)\n", ret);
+		return ret;
+	}
+
+	time_records->load_loader_2nd_end = read_time_ms();
+
+	sys_switch_all_to_pll();
+
+	time_records->fsbl_decomp_start = read_time_ms();
+	if (comp_type) {
+		size_t dst_size = DECOMP_DST_SIZE;
+
+		// header is not compressed.
+		void *dst = (void *)loader_2nd_header->runaddr;
+
+		memcpy(dst, image_buf, sizeof(struct loader_2nd_header));
+		image_buf += sizeof(struct loader_2nd_header);
+
+		ret = decompress(dst + sizeof(struct loader_2nd_header), &dst_size, image_buf, loader_2nd_header->size,
+				 comp_type);
+		if (ret < 0) {
+			ERROR("Failed to decompress loader_2nd (%d/%lu)\n", ret, dst_size);
+			return -1;
+		}
+
+		reading_size = dst_size;
+	}
+
+	flush_dcache_range(loader_2nd_header->runaddr, reading_size);
+	time_records->fsbl_decomp_end = read_time_ms();
+	NOTICE("Loader_2nd loaded.\n");
+
+	*loader_2nd_entry = loader_2nd_header->runaddr + sizeof(struct loader_2nd_header);
+
+	return 0;
+}
+
+int load_rest(void)
+{
+	int retry = 0;
+	uint64_t monitor_entry = 0;
+	uint64_t loader_2nd_entry = 0;
+
+	// Init sys PLL and switch clocks to PLL
+	sys_pll_init();
+
+retry_from_flash:
+	for (retry = 0; retry < p_rom_api_get_number_of_retries(); retry++) {
+		if (load_blcp_2nd(retry) < 0)
+			continue;
+
+		if (load_monitor(retry, &monitor_entry) < 0)
+			continue;
+
+		if (load_loader_2nd(retry, &loader_2nd_entry) < 0)
+			continue;
+
+		break;
+	}
+
+	if (retry >= p_rom_api_get_number_of_retries()) {
+		switch (p_rom_api_get_boot_src()) {
+		case BOOT_SRC_UART:
+		case BOOT_SRC_SD:
+		case BOOT_SRC_USB:
+			WARN("DL cancelled. Load flash. (%d).\n", retry);
+			// Continue to boot from flash if boot from external source
+			p_rom_api_flash_init();
+			goto retry_from_flash;
+		default:
+			ERROR("Failed to load rest (%d).\n", retry);
+			panic_handler();
+		}
+	}
+
+	sync_cache();
+	console_flush();
+
+	switch_rtc_mode_2nd_stage();
+
+	if (monitor_entry) {
+		NOTICE("Jump to monitor at 0x%lx.\n", monitor_entry);
+		jump_to_monitor(monitor_entry, loader_2nd_entry);
+	} else {
+		NOTICE("Jump to loader_2nd at 0x%lx.\n", loader_2nd_entry);
+		jump_to_loader_2nd(loader_2nd_entry);
+	}
+
+	return 0;
+}
+
+int load_rest_od_sel(void)
+{
+	int retry = 0;
+	uint64_t monitor_entry = 0;
+	uint64_t loader_2nd_entry = 0;
+
+	// Init sys PLL and switch clocks to PLL
+	sys_pll_init_od_sel();
+
+retry_from_flash:
+	for (retry = 0; retry < p_rom_api_get_number_of_retries(); retry++) {
+		if (load_blcp_2nd(retry) < 0)
+			continue;
+
+		if (load_monitor(retry, &monitor_entry) < 0)
+			continue;
+
+		if (load_loader_2nd(retry, &loader_2nd_entry) < 0)
+			continue;
+
+		break;
+	}
+
+	if (retry >= p_rom_api_get_number_of_retries()) {
+		switch (p_rom_api_get_boot_src()) {
+		case BOOT_SRC_UART:
+		case BOOT_SRC_SD:
+		case BOOT_SRC_USB:
+			WARN("DL cancelled. Load flash. (%d).\n", retry);
+			// Continue to boot from flash if boot from external source
+			p_rom_api_flash_init();
+			goto retry_from_flash;
+		default:
+			ERROR("Failed to load rest (%d).\n", retry);
+			panic_handler();
+		}
+	}
+
+	sync_cache();
+	console_flush();
+
+	switch_rtc_mode_2nd_stage();
+
+	if (monitor_entry) {
+		NOTICE("Jump to monitor at 0x%lx.\n", monitor_entry);
+		jump_to_monitor(monitor_entry, loader_2nd_entry);
+	} else {
+		NOTICE("Jump to loader_2nd at 0x%lx.\n", loader_2nd_entry);
+		jump_to_loader_2nd(loader_2nd_entry);
+	}
+
+	return 0;
+}

fsbl/plat/cv180x/bl2_objs/cv1800b_milkv_duo_sd

@@ -1 +0,0 @@
-cv1800b_sophpi_duo_sd

fsbl/plat/cv180x/bl2_objs/cv1800b_milkv_duo_spinand

@@ -1 +0,0 @@
-cv1800b_wdmb_0008a_spinor

fsbl/plat/cv180x/bl2_objs/cv1800b_milkv_duo_spinor

@@ -1 +0,0 @@
-cv1800b_wdmb_0008a_spinor