3a4bcfca2f
1. add cvitek folders to u-boot-2021.10 2. add cv183x/cv182x part 3. add cv181x/cv180x part Change-Id: I6dc2e5ff509dbab16bd60bfb3fd61852da5e01f6
168 lines
5.1 KiB
C
168 lines
5.1 KiB
C
#ifndef __CVSNFC_SPI_IDSH
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#define __CVSNFC_SPI_IDSH
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/*****************************************************************************/
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#define INFINITE (0xFFFFFFFF)
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#define DEFAULT_ID_LEN 2
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#define MAX_ID_LEN 3
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#define MAX_SPI_NAND_OP 8
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#define BBP_LAST_PAGE 0x01
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#define BBP_FIRST_PAGE 0x02
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#define BBP_FIRST_2_PAGE 0x03
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/*****************************************************************************/
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#define SPI_IF_READ_STD (0x01)
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#define SPI_IF_READ_FAST (0x02)
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#define SPI_IF_READ_DUAL (0x04)
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#define SPI_IF_READ_DUAL_ADDR (0x08)
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#define SPI_IF_READ_QUAD (0x10)
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#define SPI_IF_READ_QUAD_ADDR (0x20)
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#define SPI_IF_WRITE_STD (0x01)
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#define SPI_IF_WRITE_DUAL (0x02)
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#define SPI_IF_WRITE_DUAL_ADDR (0x04)
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#define SPI_IF_WRITE_QUAD (0x08)
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#define SPI_IF_WRITE_QUAD_ADDR (0x10)
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#define SPI_IF_ERASE_SECTOR_128K (0x08) /* 128K */
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#define SPI_IF_ERASE_SECTOR_256K (0x10) /* 256K */
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/******************************************************************************/
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#define CVSNFC_SUPPORT_READ (SPI_IF_READ_STD \
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| SPI_IF_READ_FAST \
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| SPI_IF_READ_DUAL \
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| SPI_IF_READ_DUAL_ADDR \
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| SPI_IF_READ_QUAD \
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| SPI_IF_READ_QUAD_ADDR)
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#define CVSNFC_SUPPORT_WRITE (SPI_IF_WRITE_STD | SPI_IF_WRITE_QUAD)
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#define CVSNFC_SUPPORT_MAX_DUMMY 8
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#define SPI_NAND_READ 0
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#define SPI_NAND_WRITE 1
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#define CVSNFC_IFCYCLE_STD 0
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#define CVSNFC_IFCYCLE_DUAL 1
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#define CVSNFC_IFCYCLE_DUAL_ADDR 2
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#define CVSNFC_IFCYCLE_QUAD 3
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#define CVSNFC_IFCYCLE_QUAD_ADDR 4
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/*****************************************************************************/
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#define SPI_CMD_WREN 0x06 /* Write Enable */
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#define SPI_CMD_WRDI 0x04 /* Write Disable */
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#define SPI_CMD_GET_FEATURES 0x0F /* Get Features */
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#define SPI_CMD_SET_FEATURE 0x1F /* Set Feature */
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#define SPI_CMD_PAGE_READ 0x13 /* Page Read to Cache */
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#define SPI_CMD_READ_STD 0x03 /* Read From Cache at Standard Speed */
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#define SPI_CMD_READ_FAST 0x0B /* Read From Cache at Higher Speed */
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#define SPI_CMD_READ_DUAL 0x3B /* Read From Cache at Dual Output */
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#define SPI_CMD_READ_QUAD 0x6B /* Read From Cache at Quad Output */
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#define SPI_CMD_READ_DUAL_ADDR 0xBB /* Read From Cache at Dual I/O */
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#define SPI_CMD_READ_QUAD_ADDR 0xEB /* Read From Cache at Quad I/O */
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#define SPI_CMD_RDID 0x9F /* Read Identification */
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#define SPI_CMD_WRITE_STD 0x02 /* Page Load at Standard Input */
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#define SPI_CMD_WRITE_QUAD 0x32 /* Page Load at Quad Input */
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#define SPI_CMD_SE_128K 0xD8 /* 128KB sector Erase */
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#define SPI_CMD_SE_256K 0xD8 /* 256KB sector Erase */
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#define SPI_CMD_RESET 0xff /* Reset the device */
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/*****************************************************************************/
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/* SPI operation information */
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struct spi_op_info {
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unsigned char iftype;
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unsigned char cmd;
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unsigned char dummy;
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unsigned int size;
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unsigned int clock;
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};
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struct spi_nand_driver;
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struct cvsnfc_op {
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void *host;
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struct spi_nand_driver *driver;
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struct spi_op_info read[1];
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struct spi_op_info write[1];
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struct spi_op_info erase[MAX_SPI_NAND_OP];
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};
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struct spi_nand_driver {
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int (*wait_ready)(struct cvsnfc_op *spi);
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int (*write_enable)(struct cvsnfc_op *spi);
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int (*qe_enable)(struct cvsnfc_op *spi);
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int (*ecc_enable)(struct cvsnfc_op *spi);
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int (*select_die)(struct cvsnfc_op *spi, unsigned int id);
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unsigned char ecc_uncorr;
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};
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#define FLAGS_SET_PLANE_BIT BIT(0)
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#define NAND_SET_PLANE_BIT BIT(0)
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#define SPI_NAND_MULTIPLANE_BIT BIT(12)
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#define FLAGS_SET_QE_BIT (BIT(1))
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#define FLAGS_ENABLE_X2_BIT (BIT(2))
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#define FLAGS_ENABLE_X4_BIT (BIT(3))
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#define FLAGS_OW_SETTING_BIT (BIT(4))
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#define FLAGS_ONLY_ONEBIT_MODE_BIT (BIT(5))
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#define FLAGS_CONTORL_WP_BIT (BIT(6))
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#define FLAGS_SUPPORT_W_TWICE_DEBUG (BIT(7))
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#define SPI_NAND_FREQ_XTAL 0 /* 6.25 Mhz */
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#define SPI_NAND_FREQ_23MHz 1 /* 23.4375 Mhz */
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#define SPI_NAND_FREQ_26MHz 2 /* 26.7857 Mhz */
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#define SPI_NAND_FREQ_31MHz 3 /* 31.25 Mhz */
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#define SPI_NAND_FREQ_37MHz 4 /* 37.5 Mhz */
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#define SPI_NAND_FREQ_46MHz 5 /* 46.875 Mhz */
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#define SPI_NAND_FREQ_62MHz 6 /* 62.5 Mhz */
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#define SPI_NAND_FREQ_93MHz 7 /* 93.75 Mhz */
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struct cvsnfc_chip_info {
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char *name;
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unsigned char id[MAX_ID_LEN];
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unsigned char id_len;
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unsigned long long chipsize;
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unsigned long long diesize;
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unsigned int erasesize;
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unsigned int pagesize;
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unsigned int oobsize;
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unsigned int badblock_pos;
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unsigned int flags;
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struct spi_op_info *read[MAX_SPI_NAND_OP];
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struct spi_op_info *write[MAX_SPI_NAND_OP];
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struct spi_op_info *erase[MAX_SPI_NAND_OP];
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struct spi_nand_driver *driver;
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uint8_t ecc_en_feature_offset;
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uint8_t ecc_en_mask;
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uint8_t ecc_status_offset;
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uint8_t ecc_status_mask;
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uint8_t ecc_status_shift;
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uint8_t ecc_status_uncorr_val;
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uint8_t sck_l;
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uint8_t sck_h;
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uint16_t max_freq;
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uint32_t sample_param;
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uint8_t xtal_switch;
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};
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/*****************************************************************************/
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void spi_nand_ids_register(void);
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void cvsnfc_get_best_clock(unsigned int *clock);
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struct cvsnfc_host;
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void spi_feature_op(struct cvsnfc_host *host, int op, int addr, unsigned int *val);
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/******************************************************************************/
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#endif /* __CVSNFC_SPI_IDSH */
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